1 /* IRA hard register and memory cost calculation for allocnos.
2 Copyright (C) 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
41 /* The file contains code is similar to one in regclass but the code
42 works on the allocno basis. */
44 #ifdef FORBIDDEN_INC_DEC_CLASSES
45 /* Indexed by n, is TRUE if allocno with number N is used in an
46 auto-inc or auto-dec context. */
47 static bool *in_inc_dec
;
50 /* The `costs' struct records the cost of using hard registers of each
51 class considered for the calculation and of using memory for each
56 /* Costs for register classes start here. We process only some
57 register classes (cover classes on the 1st cost calculation
58 iteration and important classes on the 2nd iteration). */
62 /* Initialized once. It is a maximal possible size of the allocated
64 static int max_struct_costs_size
;
66 /* Allocated and initialized once, and used to initialize cost values
68 static struct costs
*init_cost
;
70 /* Allocated once, and used for temporary purposes. */
71 static struct costs
*temp_costs
;
73 /* Allocated once, and used for the cost calculation. */
74 static struct costs
*op_costs
[MAX_RECOG_OPERANDS
];
75 static struct costs
*this_op_costs
[MAX_RECOG_OPERANDS
];
77 /* Record the initial and accumulated cost of each class for each
79 static struct costs
*total_costs
;
81 /* Classes used for cost calculation. They may be different on
82 different iterations of the cost calculations or in different
83 optimization modes. */
84 static enum reg_class
*cost_classes
;
86 /* The size of the previous array. */
87 static int cost_classes_num
;
89 /* Map: cost class -> order number (they start with 0) of the cost
91 static int cost_class_nums
[N_REG_CLASSES
];
93 /* It is the current size of struct costs. */
94 static int struct_costs_size
;
96 /* Return pointer to structure containing costs of allocno with given
98 #define COSTS_OF_ALLOCNO(arr, num) \
99 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
101 /* Record register class preferences of each allocno. Null value
102 means no preferences. It happens on the 1st iteration of the cost
104 static enum reg_class
*allocno_pref
;
106 /* Allocated buffers for allocno_pref. */
107 static enum reg_class
*allocno_pref_buffer
;
109 /* Execution frequency of the current insn. */
110 static int frequency
;
114 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
115 TO_P is FALSE) a register of class CLASS in mode MODE. X must not
116 be a pseudo register. */
118 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class
class, bool to_p
,
119 secondary_reload_info
*prev_sri
)
121 secondary_reload_info sri
;
122 enum reg_class secondary_class
= NO_REGS
;
124 /* If X is a SCRATCH, there is actually nothing to move since we are
125 assuming optimal allocation. */
126 if (GET_CODE (x
) == SCRATCH
)
129 /* Get the class we will actually use for a reload. */
130 class = PREFERRED_RELOAD_CLASS (x
, class);
132 /* If we need a secondary reload for an intermediate, the cost is
133 that to load the input into the intermediate register, then to
135 sri
.prev_sri
= prev_sri
;
137 secondary_class
= targetm
.secondary_reload (to_p
, x
, class, mode
, &sri
);
139 if (register_move_cost
[mode
] == NULL
)
140 init_register_move_cost (mode
);
142 if (secondary_class
!= NO_REGS
)
143 return (move_cost
[mode
][secondary_class
][class] + sri
.extra_cost
144 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
146 /* For memory, use the memory move cost, for (hard) registers, use
147 the cost to move between the register classes, and use 2 for
148 everything else (constants). */
149 if (MEM_P (x
) || class == NO_REGS
)
150 return sri
.extra_cost
+ memory_move_cost
[mode
][class][to_p
!= 0];
153 (sri
.extra_cost
+ move_cost
[mode
][REGNO_REG_CLASS (REGNO (x
))][class]);
155 /* If this is a constant, we may eventually want to call rtx_cost
157 return sri
.extra_cost
+ COSTS_N_INSNS (1);
162 /* Record the cost of using memory or hard registers of various
163 classes for the operands in INSN.
165 N_ALTS is the number of alternatives.
166 N_OPS is the number of operands.
167 OPS is an array of the operands.
168 MODES are the modes of the operands, in case any are VOIDmode.
169 CONSTRAINTS are the constraints to use for the operands. This array
170 is modified by this procedure.
172 This procedure works alternative by alternative. For each
173 alternative we assume that we will be able to allocate all allocnos
174 to their ideal register class and calculate the cost of using that
175 alternative. Then we compute, for each operand that is a
176 pseudo-register, the cost of having the allocno allocated to each
177 register class and using it in that alternative. To this cost is
178 added the cost of the alternative.
180 The cost of each class for this insn is its lowest cost among all
183 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
184 enum machine_mode
*modes
, const char **constraints
,
185 rtx insn
, struct costs
**op_costs
,
186 enum reg_class
*allocno_pref
)
192 /* Process each alternative, each time minimizing an operand's cost
193 with the cost for each operand in that alternative. */
194 for (alt
= 0; alt
< n_alts
; alt
++)
196 enum reg_class classes
[MAX_RECOG_OPERANDS
];
197 int allows_mem
[MAX_RECOG_OPERANDS
];
200 int alt_cost
= 0, op_cost_add
;
202 for (i
= 0; i
< n_ops
; i
++)
205 const char *p
= constraints
[i
];
207 enum machine_mode mode
= modes
[i
];
211 /* Initially show we know nothing about the register class. */
212 classes
[i
] = NO_REGS
;
215 /* If this operand has no constraints at all, we can
216 conclude nothing about it since anything is valid. */
219 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
220 memset (this_op_costs
[i
], 0, struct_costs_size
);
224 /* If this alternative is only relevant when this operand
225 matches a previous operand, we do different things
226 depending on whether this operand is a allocno-reg or not.
227 We must process any modifiers for the operand before we
228 can make this test. */
229 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
232 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
234 /* Copy class and whether memory is allowed from the
235 matching alternative. Then perform any needed cost
236 computations and/or adjustments. */
238 classes
[i
] = classes
[j
];
239 allows_mem
[i
] = allows_mem
[j
];
241 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
243 /* If this matches the other operand, we have no
244 added cost and we win. */
245 if (rtx_equal_p (ops
[j
], op
))
247 /* If we can put the other operand into a register,
248 add to the cost of this alternative the cost to
249 copy this operand to the register used for the
251 else if (classes
[j
] != NO_REGS
)
253 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
257 else if (! REG_P (ops
[j
])
258 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
260 /* This op is an allocno but the one it matches is
263 /* If we can't put the other operand into a
264 register, this alternative can't be used. */
266 if (classes
[j
] == NO_REGS
)
268 /* Otherwise, add to the cost of this alternative
269 the cost to copy the other operand to the hard
270 register used for this operand. */
272 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
276 /* The costs of this operand are not the same as the
277 other operand since move costs are not symmetric.
278 Moreover, if we cannot tie them, this alternative
279 needs to do a copy, which is one insn. */
280 struct costs
*pp
= this_op_costs
[i
];
282 if (register_move_cost
[mode
] == NULL
)
283 init_register_move_cost (mode
);
285 for (k
= 0; k
< cost_classes_num
; k
++)
287 class = cost_classes
[k
];
289 = ((recog_data
.operand_type
[i
] != OP_OUT
290 ? register_may_move_in_cost
[mode
][class]
291 [classes
[i
]] * frequency
: 0)
292 + (recog_data
.operand_type
[i
] != OP_IN
293 ? register_may_move_out_cost
[mode
][classes
[i
]]
294 [class] * frequency
: 0));
297 /* If the alternative actually allows memory, make
298 things a bit cheaper since we won't need an extra
301 = ((recog_data
.operand_type
[i
] != OP_IN
302 ? memory_move_cost
[mode
][classes
[i
]][0] : 0)
303 + (recog_data
.operand_type
[i
] != OP_OUT
304 ? memory_move_cost
[mode
][classes
[i
]][1] : 0)
305 - allows_mem
[i
]) * frequency
;
306 /* If we have assigned a class to this allocno in our
307 first pass, add a cost to this alternative
308 corresponding to what we would add if this allocno
309 were not in the appropriate class. We could use
310 cover class here but it is less accurate
314 enum reg_class pref_class
315 = allocno_pref
[ALLOCNO_NUM
316 (ira_curr_regno_allocno_map
319 if (pref_class
== NO_REGS
)
321 += ((recog_data
.operand_type
[i
] != OP_IN
322 ? memory_move_cost
[mode
][classes
[i
]][0] : 0)
323 + (recog_data
.operand_type
[i
] != OP_OUT
324 ? memory_move_cost
[mode
][classes
[i
]][1] : 0));
325 else if (reg_class_intersect
326 [pref_class
][classes
[i
]] == NO_REGS
)
328 += register_move_cost
[mode
][pref_class
][classes
[i
]];
330 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
331 && ! find_reg_note (insn
, REG_DEAD
, op
))
334 /* This is in place of ordinary cost computation for
335 this operand, so skip to the end of the
336 alternative (should be just one character). */
337 while (*p
&& *p
++ != ',')
345 /* Scan all the constraint letters. See if the operand
346 matches any of the constraints. Collect the valid
347 register classes and see if this operand accepts
356 /* Ignore the next letter for this pass. */
362 case '!': case '#': case '&':
363 case '0': case '1': case '2': case '3': case '4':
364 case '5': case '6': case '7': case '8': case '9':
369 win
= address_operand (op
, GET_MODE (op
));
370 /* We know this operand is an address, so we want it
371 to be allocated to a register that can be the
372 base of an address, i.e. BASE_REG_CLASS. */
374 = reg_class_union
[classes
[i
]]
375 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
378 case 'm': case 'o': case 'V':
379 /* It doesn't seem worth distinguishing between
380 offsettable and non-offsettable addresses
389 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
390 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
396 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
397 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
403 if (GET_CODE (op
) == CONST_DOUBLE
404 || (GET_CODE (op
) == CONST_VECTOR
405 && (GET_MODE_CLASS (GET_MODE (op
))
406 == MODE_VECTOR_FLOAT
)))
412 if (GET_CODE (op
) == CONST_DOUBLE
413 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
418 if (GET_CODE (op
) == CONST_INT
419 || (GET_CODE (op
) == CONST_DOUBLE
420 && GET_MODE (op
) == VOIDmode
))
425 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
430 if (GET_CODE (op
) == CONST_INT
431 || (GET_CODE (op
) == CONST_DOUBLE
432 && GET_MODE (op
) == VOIDmode
))
444 if (GET_CODE (op
) == CONST_INT
445 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
456 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
460 classes
[i
] = reg_class_union
[classes
[i
]][GENERAL_REGS
];
464 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
465 classes
[i
] = reg_class_union
[classes
[i
]]
466 [REG_CLASS_FROM_CONSTRAINT (c
, p
)];
467 #ifdef EXTRA_CONSTRAINT_STR
468 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
471 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
473 /* Every MEM can be reloaded to fit. */
478 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
480 /* Every address can be reloaded to fit. */
482 if (address_operand (op
, GET_MODE (op
)))
484 /* We know this operand is an address, so we
485 want it to be allocated to a hard register
486 that can be the base of an address,
487 i.e. BASE_REG_CLASS. */
489 = reg_class_union
[classes
[i
]]
490 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
495 p
+= CONSTRAINT_LEN (c
, p
);
502 /* How we account for this operand now depends on whether it
503 is a pseudo register or not. If it is, we first check if
504 any register classes are valid. If not, we ignore this
505 alternative, since we want to assume that all allocnos get
506 allocated for register preferencing. If some register
507 class is valid, compute the costs of moving the allocno
509 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
511 if (classes
[i
] == NO_REGS
)
513 /* We must always fail if the operand is a REG, but
514 we did not find a suitable class.
516 Otherwise we may perform an uninitialized read
517 from this_op_costs after the `continue' statement
523 struct costs
*pp
= this_op_costs
[i
];
525 if (register_move_cost
[mode
] == NULL
)
526 init_register_move_cost (mode
);
528 for (k
= 0; k
< cost_classes_num
; k
++)
530 class = cost_classes
[k
];
532 = ((recog_data
.operand_type
[i
] != OP_OUT
533 ? register_may_move_in_cost
[mode
][class]
534 [classes
[i
]] * frequency
: 0)
535 + (recog_data
.operand_type
[i
] != OP_IN
536 ? register_may_move_out_cost
[mode
][classes
[i
]]
537 [class] * frequency
: 0));
540 /* If the alternative actually allows memory, make
541 things a bit cheaper since we won't need an extra
544 = ((recog_data
.operand_type
[i
] != OP_IN
545 ? memory_move_cost
[mode
][classes
[i
]][0] : 0)
546 + (recog_data
.operand_type
[i
] != OP_OUT
547 ? memory_move_cost
[mode
][classes
[i
]][1] : 0)
548 - allows_mem
[i
]) * frequency
;
549 /* If we have assigned a class to this allocno in our
550 first pass, add a cost to this alternative
551 corresponding to what we would add if this allocno
552 were not in the appropriate class. We could use
553 cover class here but it is less accurate
557 enum reg_class pref_class
558 = allocno_pref
[ALLOCNO_NUM
559 (ira_curr_regno_allocno_map
562 if (pref_class
== NO_REGS
)
564 += ((recog_data
.operand_type
[i
] != OP_IN
565 ? memory_move_cost
[mode
][classes
[i
]][0] : 0)
566 + (recog_data
.operand_type
[i
] != OP_OUT
567 ? memory_move_cost
[mode
][classes
[i
]][1] : 0));
568 else if (reg_class_intersect
[pref_class
][classes
[i
]]
571 += register_move_cost
[mode
][pref_class
][classes
[i
]];
576 /* Otherwise, if this alternative wins, either because we
577 have already determined that or if we have a hard
578 register of the proper class, there is no cost for this
580 else if (win
|| (REG_P (op
)
581 && reg_fits_class_p (op
, classes
[i
],
585 /* If registers are valid, the cost of this alternative
586 includes copying the object to and/or from a
588 else if (classes
[i
] != NO_REGS
)
590 if (recog_data
.operand_type
[i
] != OP_OUT
)
591 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
593 if (recog_data
.operand_type
[i
] != OP_IN
)
594 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
596 /* The only other way this alternative can be used is if
597 this is a constant that could be placed into memory. */
598 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
599 alt_cost
+= memory_move_cost
[mode
][classes
[i
]][1];
607 op_cost_add
= alt_cost
* frequency
;
608 /* Finally, update the costs with the information we've
609 calculated about this alternative. */
610 for (i
= 0; i
< n_ops
; i
++)
611 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
613 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
614 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
616 pp
->mem_cost
= MIN (pp
->mem_cost
,
617 (qq
->mem_cost
+ op_cost_add
) * scale
);
619 for (k
= 0; k
< cost_classes_num
; k
++)
621 = MIN (pp
->cost
[k
], (qq
->cost
[k
] + op_cost_add
) * scale
);
625 /* If this insn is a single set copying operand 1 to operand 0 and
626 one operand is an allocno with the other a hard reg or an allocno
627 that prefers a hard register that is in its own register class
628 then we may want to adjust the cost of that register class to -1.
630 Avoid the adjustment if the source does not die to avoid
631 stressing of register allocator by preferrencing two colliding
632 registers into single class.
634 Also avoid the adjustment if a copy between hard registers of the
635 class is expensive (ten times the cost of a default copy is
636 considered arbitrarily expensive). This avoids losing when the
637 preferred class is very expensive as the source of a copy
639 if ((set
= single_set (insn
)) != 0
640 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
641 && REG_P (ops
[0]) && REG_P (ops
[1])
642 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
643 for (i
= 0; i
<= 1; i
++)
644 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
646 unsigned int regno
= REGNO (ops
[!i
]);
647 enum machine_mode mode
= GET_MODE (ops
[!i
]);
651 if (regno
< FIRST_PSEUDO_REGISTER
)
652 for (k
= 0; k
< cost_classes_num
; k
++)
654 class = cost_classes
[k
];
655 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
656 && (reg_class_size
[class]
657 == (unsigned) CLASS_MAX_NREGS (class, mode
)))
659 if (reg_class_size
[class] == 1)
660 op_costs
[i
]->cost
[k
] = -frequency
;
664 nr
< (unsigned) hard_regno_nregs
[regno
][mode
];
666 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
670 if (nr
== (unsigned) hard_regno_nregs
[regno
][mode
])
671 op_costs
[i
]->cost
[k
] = -frequency
;
680 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
682 ok_for_index_p_nonstrict (rtx reg
)
684 unsigned regno
= REGNO (reg
);
686 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
689 /* A version of regno_ok_for_base_p for use here, when all
690 pseudo-registers should count as OK. Arguments as for
691 regno_ok_for_base_p. */
693 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
694 enum rtx_code outer_code
, enum rtx_code index_code
)
696 unsigned regno
= REGNO (reg
);
698 if (regno
>= FIRST_PSEUDO_REGISTER
)
700 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
703 /* Record the pseudo registers we must reload into hard registers in a
704 subexpression of a memory address, X.
706 If CONTEXT is 0, we are looking at the base part of an address,
707 otherwise we are looking at the index part.
709 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
710 give the context that the rtx appears in. These three arguments
711 are passed down to base_reg_class.
713 SCALE is twice the amount to multiply the cost by (it is twice so
714 we can represent half-cost adjustments). */
716 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
717 enum rtx_code outer_code
, enum rtx_code index_code
,
720 enum rtx_code code
= GET_CODE (x
);
721 enum reg_class
class;
724 class = INDEX_REG_CLASS
;
726 class = base_reg_class (mode
, outer_code
, index_code
);
739 /* When we have an address that is a sum, we must determine
740 whether registers are "base" or "index" regs. If there is a
741 sum of two registers, we must choose one to be the "base".
742 Luckily, we can use the REG_POINTER to make a good choice
743 most of the time. We only need to do this on machines that
744 can have two registers in an address and where the base and
745 index register classes are different.
747 ??? This code used to set REGNO_POINTER_FLAG in some cases,
748 but that seems bogus since it should only be set when we are
749 sure the register is being used as a pointer. */
751 rtx arg0
= XEXP (x
, 0);
752 rtx arg1
= XEXP (x
, 1);
753 enum rtx_code code0
= GET_CODE (arg0
);
754 enum rtx_code code1
= GET_CODE (arg1
);
756 /* Look inside subregs. */
758 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
760 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
762 /* If this machine only allows one register per address, it
763 must be in the first operand. */
764 if (MAX_REGS_PER_ADDRESS
== 1)
765 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
767 /* If index and base registers are the same on this machine,
768 just record registers in any non-constant operands. We
769 assume here, as well as in the tests below, that all
770 addresses are in canonical form. */
771 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
773 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
774 if (! CONSTANT_P (arg1
))
775 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
778 /* If the second operand is a constant integer, it doesn't
779 change what class the first operand must be. */
780 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
781 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
782 /* If the second operand is a symbolic constant, the first
783 operand must be an index register. */
784 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
785 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
786 /* If both operands are registers but one is already a hard
787 register of index or reg-base class, give the other the
788 class that the hard register is not. */
789 else if (code0
== REG
&& code1
== REG
790 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
791 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
792 || ok_for_index_p_nonstrict (arg0
)))
793 record_address_regs (mode
, arg1
,
794 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
797 else if (code0
== REG
&& code1
== REG
798 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
799 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
800 || ok_for_index_p_nonstrict (arg1
)))
801 record_address_regs (mode
, arg0
,
802 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
805 /* If one operand is known to be a pointer, it must be the
806 base with the other operand the index. Likewise if the
807 other operand is a MULT. */
808 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
810 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
811 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
813 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
815 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
816 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
818 /* Otherwise, count equal chances that each might be a base or
819 index register. This case should be rare. */
822 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
823 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
824 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
825 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
830 /* Double the importance of an allocno that is incremented or
831 decremented, since it would take two extra insns if it ends
832 up in the wrong place. */
835 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
836 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
837 if (REG_P (XEXP (XEXP (x
, 1), 1)))
838 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
846 /* Double the importance of an allocno that is incremented or
847 decremented, since it would take two extra insns if it ends
848 up in the wrong place. If the operand is a pseudo-register,
849 show it is being used in an INC_DEC context. */
850 #ifdef FORBIDDEN_INC_DEC_CLASSES
851 if (REG_P (XEXP (x
, 0))
852 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
853 in_inc_dec
[ALLOCNO_NUM (ira_curr_regno_allocno_map
854 [REGNO (XEXP (x
, 0))])] = true;
856 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
864 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
867 pp
= COSTS_OF_ALLOCNO (total_costs
,
868 ALLOCNO_NUM (ira_curr_regno_allocno_map
870 pp
->mem_cost
+= (memory_move_cost
[Pmode
][class][1] * scale
) / 2;
871 if (register_move_cost
[Pmode
] == NULL
)
872 init_register_move_cost (Pmode
);
873 for (k
= 0; k
< cost_classes_num
; k
++)
877 += (register_may_move_in_cost
[Pmode
][i
][class] * scale
) / 2;
884 const char *fmt
= GET_RTX_FORMAT (code
);
886 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
888 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
896 /* Calculate the costs of insn operands. */
898 record_operand_costs (rtx insn
, struct costs
**op_costs
,
899 enum reg_class
*allocno_pref
)
901 const char *constraints
[MAX_RECOG_OPERANDS
];
902 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
905 for (i
= 0; i
< recog_data
.n_operands
; i
++)
907 constraints
[i
] = recog_data
.constraints
[i
];
908 modes
[i
] = recog_data
.operand_mode
[i
];
911 /* If we get here, we are set up to record the costs of all the
912 operands for this insn. Start by initializing the costs. Then
913 handle any address registers. Finally record the desired classes
914 for any allocnos, doing it twice if some pair of operands are
916 for (i
= 0; i
< recog_data
.n_operands
; i
++)
918 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
920 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
921 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
923 if (MEM_P (recog_data
.operand
[i
]))
924 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
925 XEXP (recog_data
.operand
[i
], 0),
926 0, MEM
, SCRATCH
, frequency
* 2);
927 else if (constraints
[i
][0] == 'p'
928 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0],
930 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
931 SCRATCH
, frequency
* 2);
934 /* Check for commutative in a separate loop so everything will have
935 been initialized. We must do this even if one operand is a
936 constant--see addsi3 in m68k.md. */
937 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
938 if (constraints
[i
][0] == '%')
940 const char *xconstraints
[MAX_RECOG_OPERANDS
];
943 /* Handle commutative operands by swapping the constraints.
944 We assume the modes are the same. */
945 for (j
= 0; j
< recog_data
.n_operands
; j
++)
946 xconstraints
[j
] = constraints
[j
];
948 xconstraints
[i
] = constraints
[i
+1];
949 xconstraints
[i
+1] = constraints
[i
];
950 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
951 recog_data
.operand
, modes
,
952 xconstraints
, insn
, op_costs
, allocno_pref
);
954 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
955 recog_data
.operand
, modes
,
956 constraints
, insn
, op_costs
, allocno_pref
);
961 /* Process one insn INSN. Scan it and record each time it would save
962 code to put a certain allocnos in a certain class. Return the last
963 insn processed, so that the scan can be continued from there. */
965 scan_one_insn (rtx insn
)
967 enum rtx_code pat_code
;
974 pat_code
= GET_CODE (PATTERN (insn
));
975 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
976 || pat_code
== ADDR_VEC
|| pat_code
== ADDR_DIFF_VEC
)
979 set
= single_set (insn
);
982 /* If this insn loads a parameter from its stack slot, then it
983 represents a savings, rather than a cost, if the parameter is
984 stored in memory. Record this fact. */
985 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
986 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
987 && MEM_P (XEXP (note
, 0)))
989 COSTS_OF_ALLOCNO (total_costs
,
990 ALLOCNO_NUM (ira_curr_regno_allocno_map
991 [REGNO (SET_DEST (set
))]))->mem_cost
992 -= (memory_move_cost
[GET_MODE (SET_DEST (set
))][GENERAL_REGS
][1]
994 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
995 0, MEM
, SCRATCH
, frequency
* 2);
998 record_operand_costs (insn
, op_costs
, allocno_pref
);
1000 /* Now add the cost for each operand to the total costs for its
1002 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1003 if (REG_P (recog_data
.operand
[i
])
1004 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1006 int regno
= REGNO (recog_data
.operand
[i
]);
1008 = COSTS_OF_ALLOCNO (total_costs
,
1009 ALLOCNO_NUM (ira_curr_regno_allocno_map
[regno
]));
1010 struct costs
*q
= op_costs
[i
];
1012 p
->mem_cost
+= q
->mem_cost
;
1013 for (k
= 0; k
< cost_classes_num
; k
++)
1014 p
->cost
[k
] += q
->cost
[k
];
1022 /* Print allocnos costs to file F. */
1024 print_costs (FILE *f
)
1028 allocno_iterator ai
;
1031 FOR_EACH_ALLOCNO (a
, ai
)
1035 int regno
= ALLOCNO_REGNO (a
);
1037 i
= ALLOCNO_NUM (a
);
1038 fprintf (f
, " a%d(r%d,", i
, regno
);
1039 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1040 fprintf (f
, "b%d", bb
->index
);
1042 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1043 fprintf (f
, ") costs:");
1044 for (k
= 0; k
< cost_classes_num
; k
++)
1046 class = cost_classes
[k
];
1047 if (contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (regno
)]
1048 #ifdef FORBIDDEN_INC_DEC_CLASSES
1049 && (! in_inc_dec
[i
] || ! forbidden_inc_dec_class
[class])
1051 #ifdef CANNOT_CHANGE_MODE_CLASS
1052 && ! invalid_mode_change_p (regno
, (enum reg_class
) class,
1053 PSEUDO_REGNO_MODE (regno
))
1056 fprintf (f
, " %s:%d", reg_class_names
[class],
1057 COSTS_OF_ALLOCNO (total_costs
, i
)->cost
[k
]);
1059 fprintf (f
, " MEM:%i\n", COSTS_OF_ALLOCNO (total_costs
, i
)->mem_cost
);
1063 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1066 process_bb_node_for_costs (loop_tree_node_t loop_tree_node
)
1071 bb
= loop_tree_node
->bb
;
1074 frequency
= REG_FREQ_FROM_BB (bb
);
1077 FOR_BB_INSNS (bb
, insn
)
1078 insn
= scan_one_insn (insn
);
1081 /* Find costs of register classes and memory for allocnos and their
1084 find_allocno_class_costs (void)
1091 #ifdef FORBIDDEN_INC_DEC_CLASSES
1092 in_inc_dec
= ira_allocate (sizeof (bool) * allocnos_num
);
1093 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1095 allocno_pref
= NULL
;
1096 /* Normally we scan the insns once and determine the best class to
1097 use for each allocno. However, if -fexpensive-optimizations are
1098 on, we do so twice, the second time using the tentative best
1099 classes to guide the selection. */
1100 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1102 if (internal_flag_ira_verbose
> 0 && ira_dump_file
)
1103 fprintf (ira_dump_file
, "\nPass %i for finding allocno costs\n\n",
1105 /* We could use only cover classes. Unfortunately it does not
1106 work well for some targets where some subclass of cover class
1107 is costly and wrong cover class is chosen. */
1108 for (cost_classes_num
= 0;
1109 cost_classes_num
< important_classes_num
;
1112 cost_classes
[cost_classes_num
]
1113 = important_classes
[cost_classes_num
];
1114 cost_class_nums
[cost_classes
[cost_classes_num
]]
1118 = sizeof (struct costs
) + sizeof (int) * (cost_classes_num
- 1);
1119 /* Zero out our accumulation of the cost of each class for each
1121 memset (total_costs
, 0, allocnos_num
* struct_costs_size
);
1122 #ifdef FORBIDDEN_INC_DEC_CLASSES
1123 memset (in_inc_dec
, 0, allocnos_num
* sizeof (bool));
1126 /* Scan the instructions and record each time it would save code
1127 to put a certain allocno in a certain class. */
1128 traverse_loop_tree (true, ira_loop_tree_root
,
1129 process_bb_node_for_costs
, NULL
);
1132 allocno_pref
= allocno_pref_buffer
;
1134 /* Now for each allocno look at how desirable each class is and
1135 find which class is preferred. */
1136 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1138 allocno_t a
, parent_a
;
1139 int class, a_num
, parent_a_num
;
1140 loop_tree_node_t parent
;
1142 enum reg_class best
, alt_class
, common_class
;
1143 #ifdef FORBIDDEN_INC_DEC_CLASSES
1144 int inc_dec_p
= false;
1147 if (regno_allocno_map
[i
] == NULL
)
1149 memset (temp_costs
, 0, struct_costs_size
);
1150 /* Find cost of all allocnos with the same regno. */
1151 for (a
= regno_allocno_map
[i
];
1153 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1155 a_num
= ALLOCNO_NUM (a
);
1156 if ((flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1157 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
)
1158 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1159 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
)
1161 /* Propagate costs to upper levels in the region
1163 parent_a_num
= ALLOCNO_NUM (parent_a
);
1164 for (k
= 0; k
< cost_classes_num
; k
++)
1165 COSTS_OF_ALLOCNO (total_costs
, parent_a_num
)->cost
[k
]
1166 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1167 COSTS_OF_ALLOCNO (total_costs
, parent_a_num
)->mem_cost
1168 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->mem_cost
;
1170 for (k
= 0; k
< cost_classes_num
; k
++)
1172 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1173 temp_costs
->mem_cost
1174 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->mem_cost
;
1175 #ifdef FORBIDDEN_INC_DEC_CLASSES
1176 if (in_inc_dec
[a_num
])
1180 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1182 alt_class
= NO_REGS
;
1183 /* Find best common class for all allocnos with the same
1185 for (k
= 0; k
< cost_classes_num
; k
++)
1187 class = cost_classes
[k
];
1188 /* Ignore classes that are too small for this operand or
1189 invalid for an operand that was auto-incremented. */
1190 if (! contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1191 #ifdef FORBIDDEN_INC_DEC_CLASSES
1192 || (inc_dec_p
&& forbidden_inc_dec_class
[class])
1194 #ifdef CANNOT_CHANGE_MODE_CLASS
1195 || invalid_mode_change_p (i
, (enum reg_class
) class,
1196 PSEUDO_REGNO_MODE (i
))
1200 if (temp_costs
->cost
[k
] < best_cost
)
1202 best_cost
= temp_costs
->cost
[k
];
1203 best
= (enum reg_class
) class;
1205 else if (temp_costs
->cost
[k
] == best_cost
)
1206 best
= reg_class_union
[best
][class];
1207 if (pass
== flag_expensive_optimizations
1208 && temp_costs
->cost
[k
] < temp_costs
->mem_cost
1209 && (reg_class_size
[reg_class_subunion
[alt_class
][class]]
1210 > reg_class_size
[alt_class
]))
1211 alt_class
= reg_class_subunion
[alt_class
][class];
1213 if (pass
== flag_expensive_optimizations
)
1215 if (best_cost
> temp_costs
->mem_cost
)
1216 best
= alt_class
= NO_REGS
;
1217 else if (best
== alt_class
)
1218 alt_class
= NO_REGS
;
1219 setup_reg_classes (i
, best
, alt_class
);
1220 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1221 fprintf (ira_dump_file
,
1222 " r%d: preferred %s, alternative %s\n",
1223 i
, reg_class_names
[best
], reg_class_names
[alt_class
]);
1225 if (best_cost
> temp_costs
->mem_cost
)
1226 common_class
= NO_REGS
;
1228 /* Make the common class a cover class. Remember all
1229 allocnos with the same regno should have the same cover
1231 common_class
= class_translate
[best
];
1232 for (a
= regno_allocno_map
[i
];
1234 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1236 a_num
= ALLOCNO_NUM (a
);
1237 if (common_class
== NO_REGS
)
1241 /* Finding best class which is subset of the common
1243 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1245 for (k
= 0; k
< cost_classes_num
; k
++)
1247 class = cost_classes
[k
];
1248 if (! class_subset_p
[class][common_class
])
1250 /* Ignore classes that are too small for this
1251 operand or invalid for an operand that was
1252 auto-incremented. */
1253 if (! contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1254 #ifdef FORBIDDEN_INC_DEC_CLASSES
1255 || (inc_dec_p
&& forbidden_inc_dec_class
[class])
1257 #ifdef CANNOT_CHANGE_MODE_CLASS
1258 || invalid_mode_change_p (i
, (enum reg_class
) class,
1259 PSEUDO_REGNO_MODE (i
))
1263 else if (COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
]
1267 = COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1268 best
= (enum reg_class
) class;
1270 else if (COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
]
1272 best
= reg_class_union
[best
][class];
1275 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
1276 && (pass
== 0 || allocno_pref
[a_num
] != best
))
1278 fprintf (ira_dump_file
, " a%d (r%d,", a_num
, i
);
1279 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1280 fprintf (ira_dump_file
, "b%d", bb
->index
);
1282 fprintf (ira_dump_file
, "l%d",
1283 ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1284 fprintf (ira_dump_file
, ") best %s, cover %s\n",
1285 reg_class_names
[best
],
1286 reg_class_names
[class_translate
[best
]]);
1288 allocno_pref
[a_num
] = best
;
1292 if (internal_flag_ira_verbose
> 4 && ira_dump_file
)
1294 print_costs (ira_dump_file
);
1295 fprintf (ira_dump_file
,"\n");
1299 #ifdef FORBIDDEN_INC_DEC_CLASSES
1300 ira_free (in_inc_dec
);
1306 /* Process moves involving hard regs to modify allocno hard register
1307 costs. We can do this only after determining allocno cover class.
1308 If a hard register forms a register class, than moves with the hard
1309 register are already taken into account in class costs for the
1312 process_bb_node_for_hard_reg_moves (loop_tree_node_t loop_tree_node
)
1314 int i
, freq
, cost
, src_regno
, dst_regno
, hard_regno
;
1317 enum reg_class
class, cover_class
, hard_reg_class
;
1318 enum machine_mode mode
;
1320 rtx insn
, set
, src
, dst
;
1322 bb
= loop_tree_node
->bb
;
1325 freq
= REG_FREQ_FROM_BB (bb
);
1328 FOR_BB_INSNS (bb
, insn
)
1330 if (! INSN_P (insn
))
1332 set
= single_set (insn
);
1333 if (set
== NULL_RTX
)
1335 dst
= SET_DEST (set
);
1336 src
= SET_SRC (set
);
1337 if (! REG_P (dst
) || ! REG_P (src
))
1339 dst_regno
= REGNO (dst
);
1340 src_regno
= REGNO (src
);
1341 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1342 && src_regno
< FIRST_PSEUDO_REGISTER
)
1344 hard_regno
= src_regno
;
1346 a
= ira_curr_regno_allocno_map
[dst_regno
];
1348 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1349 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1351 hard_regno
= dst_regno
;
1353 a
= ira_curr_regno_allocno_map
[src_regno
];
1357 class = ALLOCNO_COVER_CLASS (a
);
1358 if (! TEST_HARD_REG_BIT (reg_class_contents
[class], hard_regno
))
1360 i
= class_hard_reg_index
[class][hard_regno
];
1363 mode
= ALLOCNO_MODE (a
);
1364 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
1365 cost
= (to_p
? register_move_cost
[mode
][hard_reg_class
][class]
1366 : register_move_cost
[mode
][class][hard_reg_class
]) * freq
;
1367 allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), class,
1368 ALLOCNO_COVER_CLASS_COST (a
));
1369 allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
), class, 0);
1370 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1371 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1372 ALLOCNO_COVER_CLASS_COST (a
) = MIN (ALLOCNO_COVER_CLASS_COST (a
),
1373 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1374 if (flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1375 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
)
1377 /* Propagate changes to the upper levels in the region
1379 loop_tree_node_t parent
;
1380 int regno
= ALLOCNO_REGNO (a
);
1384 if ((parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) == NULL
)
1386 if ((a
= parent
->regno_allocno_map
[regno
]) == NULL
)
1388 cover_class
= ALLOCNO_COVER_CLASS (a
);
1389 allocate_and_set_costs
1390 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1391 ALLOCNO_COVER_CLASS_COST (a
));
1392 allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1394 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1395 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1396 ALLOCNO_COVER_CLASS_COST (a
)
1397 = MIN (ALLOCNO_COVER_CLASS_COST (a
),
1398 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1404 /* After we find hard register and memory costs for allocnos, define
1405 its cover class and modify hard register cost because insns moving
1406 allocno to/from hard registers. */
1408 setup_allocno_cover_class_and_costs (void)
1412 enum reg_class cover_class
, class;
1413 enum machine_mode mode
;
1415 allocno_iterator ai
;
1417 FOR_EACH_ALLOCNO (a
, ai
)
1419 i
= ALLOCNO_NUM (a
);
1420 mode
= ALLOCNO_MODE (a
);
1421 cover_class
= class_translate
[allocno_pref
[i
]];
1422 ira_assert (allocno_pref
[i
] == NO_REGS
|| cover_class
!= NO_REGS
);
1423 ALLOCNO_MEMORY_COST (a
) = ALLOCNO_UPDATED_MEMORY_COST (a
)
1424 = COSTS_OF_ALLOCNO (total_costs
, i
)->mem_cost
;
1425 set_allocno_cover_class (a
, cover_class
);
1426 if (cover_class
== NO_REGS
)
1428 ALLOCNO_AVAILABLE_REGS_NUM (a
) = available_class_regs
[cover_class
];
1429 ALLOCNO_COVER_CLASS_COST (a
)
1430 = (COSTS_OF_ALLOCNO (total_costs
, i
)
1431 ->cost
[cost_class_nums
[allocno_pref
[i
]]]);
1432 if (optimize
&& ALLOCNO_COVER_CLASS (a
) != allocno_pref
[i
])
1434 n
= class_hard_regs_num
[cover_class
];
1435 ALLOCNO_HARD_REG_COSTS (a
)
1436 = reg_costs
= allocate_cost_vector (cover_class
);
1437 for (j
= n
- 1; j
>= 0; j
--)
1439 regno
= class_hard_regs
[cover_class
][j
];
1440 class = REGNO_REG_CLASS (regno
);
1441 reg_costs
[j
] = (COSTS_OF_ALLOCNO (total_costs
, i
)
1442 ->cost
[cost_class_nums
[class]]);
1447 traverse_loop_tree (true, ira_loop_tree_root
,
1448 process_bb_node_for_hard_reg_moves
, NULL
);
1453 /* Function called once during compiler work. */
1455 init_ira_costs_once (void)
1460 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1463 this_op_costs
[i
] = NULL
;
1466 cost_classes
= NULL
;
1469 /* Free allocated temporary cost vectors. */
1471 free_ira_costs (void)
1475 if (init_cost
!= NULL
)
1478 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1480 if (op_costs
[i
] != NULL
)
1482 if (this_op_costs
[i
] != NULL
)
1483 free (this_op_costs
[i
]);
1484 op_costs
[i
] = this_op_costs
[i
] = NULL
;
1486 if (temp_costs
!= NULL
)
1489 if (cost_classes
!= NULL
)
1490 free (cost_classes
);
1491 cost_classes
= NULL
;
1494 /* This is called each time register related information is
1497 init_ira_costs (void)
1502 max_struct_costs_size
1503 = sizeof (struct costs
) + sizeof (int) * (important_classes_num
- 1);
1504 /* Don't use ira_allocate because vectors live through several IRA calls. */
1505 init_cost
= xmalloc (max_struct_costs_size
);
1506 init_cost
->mem_cost
= 1000000;
1507 for (i
= 0; i
< important_classes_num
; i
++)
1508 init_cost
->cost
[i
] = 1000000;
1509 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1511 op_costs
[i
] = xmalloc (max_struct_costs_size
);
1512 this_op_costs
[i
] = xmalloc (max_struct_costs_size
);
1514 temp_costs
= xmalloc (max_struct_costs_size
);
1515 cost_classes
= xmalloc (sizeof (enum reg_class
) * important_classes_num
);
1518 /* Function called once at the end of compiler work. */
1520 finish_ira_costs_once (void)
1527 /* Entry function which defines cover class, memory and hard register
1528 costs for each allocno. */
1533 allocno_iterator ai
;
1535 total_costs
= ira_allocate (max_struct_costs_size
* allocnos_num
);
1536 allocno_pref_buffer
= ira_allocate (sizeof (enum reg_class
) * allocnos_num
);
1537 find_allocno_class_costs ();
1538 setup_allocno_cover_class_and_costs ();
1539 /* Because we could process operands only as subregs, check mode of
1540 the registers themselves too. */
1541 FOR_EACH_ALLOCNO (a
, ai
)
1542 if (register_move_cost
[ALLOCNO_MODE (a
)] == NULL
1543 && have_regs_of_mode
[ALLOCNO_MODE (a
)])
1544 init_register_move_cost (ALLOCNO_MODE (a
));
1545 ira_free (allocno_pref_buffer
);
1546 ira_free (total_costs
);
1551 /* Change hard register costs for allocnos which lives through
1552 function calls. This is called only when we found all intersected
1553 calls during building allocno live ranges. */
1555 tune_allocno_costs_and_cover_classes (void)
1557 int j
, k
, n
, regno
, freq
;
1558 int cost
, min_cost
, *reg_costs
;
1559 enum reg_class cover_class
, class;
1560 enum machine_mode mode
;
1562 rtx call
, *allocno_calls
;
1563 HARD_REG_SET clobbered_regs
;
1564 allocno_iterator ai
;
1566 FOR_EACH_ALLOCNO (a
, ai
)
1568 cover_class
= ALLOCNO_COVER_CLASS (a
);
1569 if (cover_class
== NO_REGS
)
1571 mode
= ALLOCNO_MODE (a
);
1572 n
= class_hard_regs_num
[cover_class
];
1574 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0)
1576 allocate_and_set_costs
1577 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1578 ALLOCNO_COVER_CLASS_COST (a
));
1579 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
1580 for (j
= n
- 1; j
>= 0; j
--)
1582 regno
= class_hard_regs
[cover_class
][j
];
1583 class = REGNO_REG_CLASS (regno
);
1585 if (! flag_ira_ipra
)
1587 /* ??? If only part is call clobbered. */
1588 if (! hard_reg_not_in_set_p (regno
, mode
, call_used_reg_set
))
1590 cost
+= (ALLOCNO_CALL_FREQ (a
)
1591 * (memory_move_cost
[mode
][class][0]
1592 + memory_move_cost
[mode
][class][1]));
1598 = (VEC_address (rtx
, regno_calls
[ALLOCNO_REGNO (a
)])
1599 + ALLOCNO_CALLS_CROSSED_START (a
));
1600 ira_assert (allocno_calls
!= NULL
);
1601 for (k
= ALLOCNO_CALLS_CROSSED_NUM (a
) - 1; k
>= 0; k
--)
1603 call
= allocno_calls
[k
];
1604 freq
= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (call
));
1607 get_call_invalidated_used_regs (call
, &clobbered_regs
,
1609 /* ??? If only part is call clobbered. */
1610 if (! hard_reg_not_in_set_p (regno
, mode
,
1613 += freq
* (memory_move_cost
[mode
][class][0]
1614 + memory_move_cost
[mode
][class][1]);
1617 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
1618 cost
+= ((memory_move_cost
[mode
][class][0]
1619 + memory_move_cost
[mode
][class][1]) * ALLOCNO_FREQ (a
)
1620 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
1622 reg_costs
[j
] += cost
;
1623 if (min_cost
> reg_costs
[j
])
1624 min_cost
= reg_costs
[j
];
1627 if (min_cost
!= INT_MAX
)
1628 ALLOCNO_COVER_CLASS_COST (a
) = min_cost
;