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* config/arm/arm.c (arm_return_in_msb): New function.
[official-gcc.git] / gcc / config / arm / arm.h
blob61ff2133c5f72262666e8f4dfb111a7620e6e0d7
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Run-time compilation parameters selecting different hardware subsets. */
121 extern int target_flags;
122 /* The floating point mode. */
123 extern const char *target_fpu_name;
124 /* For backwards compatibility. */
125 extern const char *target_fpe_name;
126 /* Whether to use floating point hardware. */
127 extern const char *target_float_abi_name;
128 /* For -m{soft,hard}-float. */
129 extern const char *target_float_switch;
130 /* Which ABI to use. */
131 extern const char *target_abi_name;
132 /* Define the information needed to generate branch insns. This is
133 stored from the compare operation. */
134 extern GTY(()) rtx arm_compare_op0;
135 extern GTY(()) rtx arm_compare_op1;
136 /* The label of the current constant pool. */
137 extern rtx pool_vector_label;
138 /* Set to 1 when a return insn is output, this means that the epilogue
139 is not needed. */
140 extern int return_used_this_function;
141 /* Used to produce AOF syntax assembler. */
142 extern GTY(()) rtx aof_pic_label;
143 \f
144 /* Just in case configure has failed to define anything. */
145 #ifndef TARGET_CPU_DEFAULT
146 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
147 #endif
148
149
150 #undef CPP_SPEC
151 #define CPP_SPEC "%(subtarget_cpp_spec) \
152 %{msoft-float:%{mhard-float: \
153 %e-msoft-float and -mhard_float may not be used together}} \
154 %{mbig-endian:%{mlittle-endian: \
155 %e-mbig-endian and -mlittle-endian may not be used together}}"
156
157 #ifndef CC1_SPEC
158 #define CC1_SPEC ""
159 #endif
160
161 /* This macro defines names of additional specifications to put in the specs
162 that can be used in various specifications like CC1_SPEC. Its definition
163 is an initializer with a subgrouping for each command option.
164
165 Each subgrouping contains a string constant, that defines the
166 specification name, and a string constant that used by the GCC driver
167 program.
168
169 Do not define this macro if it does not need to do anything. */
170 #define EXTRA_SPECS \
171 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
172 SUBTARGET_EXTRA_SPECS
173
174 #ifndef SUBTARGET_EXTRA_SPECS
175 #define SUBTARGET_EXTRA_SPECS
176 #endif
177
178 #ifndef SUBTARGET_CPP_SPEC
179 #define SUBTARGET_CPP_SPEC ""
180 #endif
181 \f
182 /* Run-time Target Specification. */
183 #ifndef TARGET_VERSION
184 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
185 #endif
186
187 /* Nonzero if the function prologue (and epilogue) should obey
188 the ARM Procedure Call Standard. */
189 #define ARM_FLAG_APCS_FRAME (1 << 0)
190
191 /* Nonzero if the function prologue should output the function name to enable
192 the post mortem debugger to print a backtrace (very useful on RISCOS,
193 unused on RISCiX). Specifying this flag also enables
194 -fno-omit-frame-pointer.
195 XXX Must still be implemented in the prologue. */
196 #define ARM_FLAG_POKE (1 << 1)
197
198 /* Nonzero if floating point instructions are emulated by the FPE, in which
199 case instruction scheduling becomes very uninteresting. */
200 #define ARM_FLAG_FPE (1 << 2)
201
202 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
203
204 /* Nonzero if stack checking should be performed on entry to each function
205 which allocates temporary variables on the stack. */
206 #define ARM_FLAG_APCS_STACK (1 << 4)
207
208 /* Nonzero if floating point parameters should be passed to functions in
209 floating point registers. */
210 #define ARM_FLAG_APCS_FLOAT (1 << 5)
211
212 /* Nonzero if re-entrant, position independent code should be generated.
213 This is equivalent to -fpic. */
214 #define ARM_FLAG_APCS_REENT (1 << 6)
215
216 /* FLAG 0x0080 now spare (used to be alignment traps). */
217 /* FLAG (1 << 8) is now spare (used to be soft-float). */
218
219 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
220 #define ARM_FLAG_BIG_END (1 << 9)
221
222 /* Nonzero if we should compile for Thumb interworking. */
223 #define ARM_FLAG_INTERWORK (1 << 10)
224
225 /* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
227 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
228
229 /* Nonzero if we need to protect the prolog from scheduling */
230 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
231
232 /* Nonzero if a call to abort should be generated if a noreturn
233 function tries to return. */
234 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
235
236 /* Nonzero if function prologues should not load the PIC register. */
237 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
238
239 /* Nonzero if all call instructions should be indirect. */
240 #define ARM_FLAG_LONG_CALLS (1 << 15)
241
242 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
243 #define ARM_FLAG_THUMB (1 << 16)
244
245 /* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247 #define THUMB_FLAG_BACKTRACE (1 << 17)
248
249 /* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
252
253 /* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
256
257 /* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
260
261 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
262 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
263
264 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
265 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
267 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
270 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
271 /* Use hardware floating point instructions. */
272 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
273 /* Use hardware floating point calling convention. */
274 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
275 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
276 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
277 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
278 #define TARGET_IWMMXT (arm_arch_iwmmxt)
279 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
280 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
281 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
282 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
283 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
284 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
285 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
286 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
287 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
288 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
289 #define TARGET_ARM (! TARGET_THUMB)
290 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
291 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
292 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
293 #define TARGET_BACKTRACE (leaf_function_p () \
294 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
295 : (target_flags & THUMB_FLAG_BACKTRACE))
296 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
297 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
298 #define TARGET_AAPCS_BASED \
299 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
300
301 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
302 then TARGET_AAPCS_BASED must be true -- but the converse does not
303 hold. TARGET_BPABI implies the use of the BPABI runtime library,
304 etc., in addition to just the AAPCS calling conventions. */
305 #ifndef TARGET_BPABI
306 #define TARGET_BPABI false
307 #endif
308
309 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
310 #ifndef SUBTARGET_SWITCHES
311 #define SUBTARGET_SWITCHES
312 #endif
313
314 #define TARGET_SWITCHES \
315 { \
316 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
317 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
318 N_("Generate APCS conformant stack frames") }, \
319 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
320 {"poke-function-name", ARM_FLAG_POKE, \
321 N_("Store function names in object code") }, \
322 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
323 {"fpe", ARM_FLAG_FPE, "" }, \
324 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
325 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
326 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
327 N_("Pass FP arguments in FP registers") }, \
328 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
329 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
330 N_("Generate re-entrant, PIC code") }, \
331 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
332 {"big-endian", ARM_FLAG_BIG_END, \
333 N_("Assume target CPU is configured as big endian") }, \
334 {"little-endian", -ARM_FLAG_BIG_END, \
335 N_("Assume target CPU is configured as little endian") }, \
336 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
337 N_("Assume big endian bytes, little endian words") }, \
338 {"thumb-interwork", ARM_FLAG_INTERWORK, \
339 N_("Support calls between Thumb and ARM instruction sets") }, \
340 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
341 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
342 N_("Generate a call to abort if a noreturn function returns")}, \
343 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
344 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
345 N_("Do not move instructions into a function's prologue") }, \
346 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
347 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
348 N_("Do not load the PIC register in function prologues") }, \
349 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
350 {"long-calls", ARM_FLAG_LONG_CALLS, \
351 N_("Generate call insns as indirect calls, if necessary") }, \
352 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
353 {"thumb", ARM_FLAG_THUMB, \
354 N_("Compile for the Thumb not the ARM") }, \
355 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
356 {"arm", -ARM_FLAG_THUMB, "" }, \
357 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
358 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
359 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
360 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
361 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
362 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
363 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
364 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
365 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
366 "" }, \
367 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
368 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
369 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
370 "" }, \
371 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
372 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
373 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
374 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
375 SUBTARGET_SWITCHES \
376 {"", TARGET_DEFAULT, "" } \
377 }
378
379 #define TARGET_OPTIONS \
380 { \
381 {"cpu=", & arm_select[0].string, \
382 N_("Specify the name of the target CPU"), 0}, \
383 {"arch=", & arm_select[1].string, \
384 N_("Specify the name of the target architecture"), 0}, \
385 {"tune=", & arm_select[2].string, "", 0}, \
386 {"fpe=", & target_fpe_name, "", 0}, \
387 {"fp=", & target_fpe_name, "", 0}, \
388 {"fpu=", & target_fpu_name, \
389 N_("Specify the name of the target floating point hardware/format"), 0}, \
390 {"float-abi=", & target_float_abi_name, \
391 N_("Specify if floating point hardware should be used"), 0}, \
392 {"structure-size-boundary=", & structure_size_string, \
393 N_("Specify the minimum bit alignment of structures"), 0}, \
394 {"pic-register=", & arm_pic_register_string, \
395 N_("Specify the register to be used for PIC addressing"), 0}, \
396 {"abi=", &target_abi_name, N_("Specify an ABI"), 0}, \
397 {"soft-float", &target_float_switch, \
398 N_("Alias for -mfloat-abi=soft"), "s"}, \
399 {"hard-float", &target_float_switch, \
400 N_("Alias for -mfloat-abi=hard"), "h"} \
401 }
402
403 /* Support for a compile-time default CPU, et cetera. The rules are:
404 --with-arch is ignored if -march or -mcpu are specified.
405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
406 by --with-arch.
407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
408 by -march).
409 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
410 specified.
411 --with-fpu is ignored if -mfpu is specified.
412 --with-abi is ignored is -mabi is specified. */
413 #define OPTION_DEFAULT_SPECS \
414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
417 {"float", \
418 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
421
422 struct arm_cpu_select
423 {
424 const char * string;
425 const char * name;
426 const struct processors * processors;
427 };
428
429 /* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
432 extern struct arm_cpu_select arm_select[];
433
434 /* Which floating point model to use. */
435 enum arm_fp_model
436 {
437 ARM_FP_MODEL_UNKNOWN,
438 /* FPA model (Hardware or software). */
439 ARM_FP_MODEL_FPA,
440 /* Cirrus Maverick floating point model. */
441 ARM_FP_MODEL_MAVERICK,
442 /* VFP floating point model. */
443 ARM_FP_MODEL_VFP
444 };
445
446 extern enum arm_fp_model arm_fp_model;
447
448 /* Which floating point hardware is available. Also update
449 fp_model_for_fpu in arm.c when adding entries to this list. */
450 enum fputype
451 {
452 /* No FP hardware. */
453 FPUTYPE_NONE,
454 /* Full FPA support. */
455 FPUTYPE_FPA,
456 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
457 FPUTYPE_FPA_EMU2,
458 /* Emulated FPA hardware, Issue 3 emulator. */
459 FPUTYPE_FPA_EMU3,
460 /* Cirrus Maverick floating point co-processor. */
461 FPUTYPE_MAVERICK,
462 /* VFP. */
463 FPUTYPE_VFP
464 };
465
466 /* Recast the floating point class to be the floating point attribute. */
467 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
468
469 /* What type of floating point to tune for */
470 extern enum fputype arm_fpu_tune;
471
472 /* What type of floating point instructions are available */
473 extern enum fputype arm_fpu_arch;
474
475 enum float_abi_type
476 {
477 ARM_FLOAT_ABI_SOFT,
478 ARM_FLOAT_ABI_SOFTFP,
479 ARM_FLOAT_ABI_HARD
480 };
481
482 extern enum float_abi_type arm_float_abi;
483
484 #ifndef TARGET_DEFAULT_FLOAT_ABI
485 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
486 #endif
487
488 /* Which ABI to use. */
489 enum arm_abi_type
490 {
491 ARM_ABI_APCS,
492 ARM_ABI_ATPCS,
493 ARM_ABI_AAPCS,
494 ARM_ABI_IWMMXT
495 };
496
497 extern enum arm_abi_type arm_abi;
498
499 #ifndef ARM_DEFAULT_ABI
500 #define ARM_DEFAULT_ABI ARM_ABI_APCS
501 #endif
502
503 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
504 extern int arm_arch3m;
505
506 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
507 extern int arm_arch4;
508
509 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
510 extern int arm_arch4t;
511
512 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
513 extern int arm_arch5;
514
515 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
516 extern int arm_arch5e;
517
518 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
519 extern int arm_arch6;
520
521 /* Nonzero if this chip can benefit from load scheduling. */
522 extern int arm_ld_sched;
523
524 /* Nonzero if generating thumb code. */
525 extern int thumb_code;
526
527 /* Nonzero if this chip is a StrongARM. */
528 extern int arm_tune_strongarm;
529
530 /* Nonzero if this chip is a Cirrus variant. */
531 extern int arm_arch_cirrus;
532
533 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
534 extern int arm_arch_iwmmxt;
535
536 /* Nonzero if this chip is an XScale. */
537 extern int arm_arch_xscale;
538
539 /* Nonzero if tuning for XScale. */
540 extern int arm_tune_xscale;
541
542 /* Nonzero if tuning for stores via the write buffer. */
543 extern int arm_tune_wbuf;
544
545 /* Nonzero if we should define __THUMB_INTERWORK__ in the
546 preprocessor.
547 XXX This is a bit of a hack, it's intended to help work around
548 problems in GLD which doesn't understand that armv5t code is
549 interworking clean. */
550 extern int arm_cpp_interwork;
551
552 #ifndef TARGET_DEFAULT
553 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
554 #endif
555
556 /* The frame pointer register used in gcc has nothing to do with debugging;
557 that is controlled by the APCS-FRAME option. */
558 #define CAN_DEBUG_WITHOUT_FP
559
560 #define OVERRIDE_OPTIONS arm_override_options ()
561
562 /* Nonzero if PIC code requires explicit qualifiers to generate
563 PLT and GOT relocs rather than the assembler doing so implicitly.
564 Subtargets can override these if required. */
565 #ifndef NEED_GOT_RELOC
566 #define NEED_GOT_RELOC 0
567 #endif
568 #ifndef NEED_PLT_RELOC
569 #define NEED_PLT_RELOC 0
570 #endif
571
572 /* Nonzero if we need to refer to the GOT with a PC-relative
573 offset. In other words, generate
574
575 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
576
577 rather than
578
579 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
580
581 The default is true, which matches NetBSD. Subtargets can
582 override this if required. */
583 #ifndef GOT_PCREL
584 #define GOT_PCREL 1
585 #endif
586 \f
587 /* Target machine storage Layout. */
588
589
590 /* Define this macro if it is advisable to hold scalars in registers
591 in a wider mode than that declared by the program. In such cases,
592 the value is constrained to be within the bounds of the declared
593 type, but kept valid in the wider mode. The signedness of the
594 extension may differ from that of the type. */
595
596 /* It is far faster to zero extend chars than to sign extend them */
597
598 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
599 if (GET_MODE_CLASS (MODE) == MODE_INT \
600 && GET_MODE_SIZE (MODE) < 4) \
601 { \
602 if (MODE == QImode) \
603 UNSIGNEDP = 1; \
604 else if (MODE == HImode) \
605 UNSIGNEDP = 1; \
606 (MODE) = SImode; \
607 }
608
609 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
610 if ((GET_MODE_CLASS (MODE) == MODE_INT \
611 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
612 && GET_MODE_SIZE (MODE) < 4) \
613 (MODE) = SImode; \
614
615 /* Define this if most significant bit is lowest numbered
616 in instructions that operate on numbered bit-fields. */
617 #define BITS_BIG_ENDIAN 0
618
619 /* Define this if most significant byte of a word is the lowest numbered.
620 Most ARM processors are run in little endian mode, so that is the default.
621 If you want to have it run-time selectable, change the definition in a
622 cover file to be TARGET_BIG_ENDIAN. */
623 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
624
625 /* Define this if most significant word of a multiword number is the lowest
626 numbered.
627 This is always false, even when in big-endian mode. */
628 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
629
630 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
631 on processor pre-defineds when compiling libgcc2.c. */
632 #if defined(__ARMEB__) && !defined(__ARMWEL__)
633 #define LIBGCC2_WORDS_BIG_ENDIAN 1
634 #else
635 #define LIBGCC2_WORDS_BIG_ENDIAN 0
636 #endif
637
638 /* Define this if most significant word of doubles is the lowest numbered.
639 The rules are different based on whether or not we use FPA-format,
640 VFP-format or some other floating point co-processor's format doubles. */
641 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
642
643 #define UNITS_PER_WORD 4
644
645 /* True if natural alignment is used for doubleword types. */
646 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
647
648 #define DOUBLEWORD_ALIGNMENT 64
649
650 #define PARM_BOUNDARY 32
651
652 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
653
654 #define PREFERRED_STACK_BOUNDARY \
655 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
656
657 #define FUNCTION_BOUNDARY 32
658
659 /* The lowest bit is used to indicate Thumb-mode functions, so the
660 vbit must go into the delta field of pointers to member
661 functions. */
662 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
663
664 #define EMPTY_FIELD_BOUNDARY 32
665
666 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
667
668 /* XXX Blah -- this macro is used directly by libobjc. Since it
669 supports no vector modes, cut out the complexity and fall back
670 on BIGGEST_FIELD_ALIGNMENT. */
671 #ifdef IN_TARGET_LIBS
672 #define BIGGEST_FIELD_ALIGNMENT 64
673 #endif
674
675 /* Make strings word-aligned so strcpy from constants will be faster. */
676 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
677
678 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
679 ((TREE_CODE (EXP) == STRING_CST \
680 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
681 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
682
683 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
684 value set in previous versions of this toolchain was 8, which produces more
685 compact structures. The command line option -mstructure_size_boundary=<n>
686 can be used to change this value. For compatibility with the ARM SDK
687 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
688 0020D) page 2-20 says "Structures are aligned on word boundaries".
689 The AAPCS specifies a value of 8. */
690 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
691 extern int arm_structure_size_boundary;
692
693 /* This is the value used to initialize arm_structure_size_boundary. If a
694 particular arm target wants to change the default value it should change
695 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
696 for an example of this. */
697 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
698 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
699 #endif
700
701 /* Used when parsing command line option -mstructure_size_boundary. */
702 extern const char * structure_size_string;
703
704 /* Nonzero if move instructions will actually fail to work
705 when given unaligned data. */
706 #define STRICT_ALIGNMENT 1
707
708 /* wchar_t is unsigned under the AAPCS. */
709 #ifndef WCHAR_TYPE
710 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
711
712 #define WCHAR_TYPE_SIZE BITS_PER_WORD
713 #endif
714
715 #ifndef SIZE_TYPE
716 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
717 #endif
718
719 /* AAPCS requires that structure alignment is affected by bitfields. */
720 #ifndef PCC_BITFIELD_TYPE_MATTERS
721 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
722 #endif
723
724 \f
725 /* Standard register usage. */
726
727 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
728 (S - saved over call).
729
730 r0 * argument word/integer result
731 r1-r3 argument word
732
733 r4-r8 S register variable
734 r9 S (rfp) register variable (real frame pointer)
735
736 r10 F S (sl) stack limit (used by -mapcs-stack-check)
737 r11 F S (fp) argument pointer
738 r12 (ip) temp workspace
739 r13 F S (sp) lower end of current stack frame
740 r14 (lr) link address/workspace
741 r15 F (pc) program counter
742
743 f0 floating point result
744 f1-f3 floating point scratch
745
746 f4-f7 S floating point variable
747
748 cc This is NOT a real register, but is used internally
749 to represent things that use or set the condition
750 codes.
751 sfp This isn't either. It is used during rtl generation
752 since the offset between the frame pointer and the
753 auto's isn't known until after register allocation.
754 afp Nor this, we only need this because of non-local
755 goto. Without it fp appears to be used and the
756 elimination code won't get rid of sfp. It tracks
757 fp exactly at all times.
758
759 *: See CONDITIONAL_REGISTER_USAGE */
760
761 /*
762 mvf0 Cirrus floating point result
763 mvf1-mvf3 Cirrus floating point scratch
764 mvf4-mvf15 S Cirrus floating point variable. */
765
766 /* s0-s15 VFP scratch (aka d0-d7).
767 s16-s31 S VFP variable (aka d8-d15).
768 vfpcc Not a real register. Represents the VFP condition
769 code flags. */
770
771 /* The stack backtrace structure is as follows:
772 fp points to here: | save code pointer | [fp]
773 | return link value | [fp, #-4]
774 | return sp value | [fp, #-8]
775 | return fp value | [fp, #-12]
776 [| saved r10 value |]
777 [| saved r9 value |]
778 [| saved r8 value |]
779 [| saved r7 value |]
780 [| saved r6 value |]
781 [| saved r5 value |]
782 [| saved r4 value |]
783 [| saved r3 value |]
784 [| saved r2 value |]
785 [| saved r1 value |]
786 [| saved r0 value |]
787 [| saved f7 value |] three words
788 [| saved f6 value |] three words
789 [| saved f5 value |] three words
790 [| saved f4 value |] three words
791 r0-r3 are not normally saved in a C function. */
792
793 /* 1 for registers that have pervasive standard uses
794 and are not available for the register allocator. */
795 #define FIXED_REGISTERS \
796 { \
797 0,0,0,0,0,0,0,0, \
798 0,0,0,0,0,1,0,1, \
799 0,0,0,0,0,0,0,0, \
800 1,1,1, \
801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1,1,1,1,1,1,1,1, \
804 1,1,1,1,1,1,1,1, \
805 1,1,1,1, \
806 1,1,1,1,1,1,1,1, \
807 1,1,1,1,1,1,1,1, \
808 1,1,1,1,1,1,1,1, \
809 1,1,1,1,1,1,1,1, \
810 1 \
811 }
812
813 /* 1 for registers not available across function calls.
814 These must include the FIXED_REGISTERS and also any
815 registers that can be used without being saved.
816 The latter must include the registers where values are returned
817 and the register where structure-value addresses are passed.
818 Aside from that, you can include as many other registers as you like.
819 The CC is not preserved over function calls on the ARM 6, so it is
820 easier to assume this for all. SFP is preserved, since FP is. */
821 #define CALL_USED_REGISTERS \
822 { \
823 1,1,1,1,0,0,0,0, \
824 0,0,0,0,1,1,1,1, \
825 1,1,1,1,0,0,0,0, \
826 1,1,1, \
827 1,1,1,1,1,1,1,1, \
828 1,1,1,1,1,1,1,1, \
829 1,1,1,1,1,1,1,1, \
830 1,1,1,1,1,1,1,1, \
831 1,1,1,1, \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1,1,1,1,1,1,1,1, \
836 1 \
837 }
838
839 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
840 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
841 #endif
842
843 #define CONDITIONAL_REGISTER_USAGE \
844 { \
845 int regno; \
846 \
847 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
848 { \
849 for (regno = FIRST_FPA_REGNUM; \
850 regno <= LAST_FPA_REGNUM; ++regno) \
851 fixed_regs[regno] = call_used_regs[regno] = 1; \
852 } \
853 \
854 if (TARGET_THUMB && optimize_size) \
855 { \
856 /* When optimizing for size, it's better not to use \
857 the HI regs, because of the overhead of stacking \
858 them. */ \
859 for (regno = FIRST_HI_REGNUM; \
860 regno <= LAST_HI_REGNUM; ++regno) \
861 fixed_regs[regno] = call_used_regs[regno] = 1; \
862 } \
863 \
864 /* The link register can be clobbered by any branch insn, \
865 but we have no way to track that at present, so mark \
866 it as unavailable. */ \
867 if (TARGET_THUMB) \
868 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
869 \
870 if (TARGET_ARM && TARGET_HARD_FLOAT) \
871 { \
872 if (TARGET_MAVERICK) \
873 { \
874 for (regno = FIRST_FPA_REGNUM; \
875 regno <= LAST_FPA_REGNUM; ++ regno) \
876 fixed_regs[regno] = call_used_regs[regno] = 1; \
877 for (regno = FIRST_CIRRUS_FP_REGNUM; \
878 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
879 { \
880 fixed_regs[regno] = 0; \
881 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
882 } \
883 } \
884 if (TARGET_VFP) \
885 { \
886 for (regno = FIRST_VFP_REGNUM; \
887 regno <= LAST_VFP_REGNUM; ++ regno) \
888 { \
889 fixed_regs[regno] = 0; \
890 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
891 } \
892 } \
893 } \
894 \
895 if (TARGET_REALLY_IWMMXT) \
896 { \
897 regno = FIRST_IWMMXT_GR_REGNUM; \
898 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
899 and wCG1 as call-preserved registers. The 2002/11/21 \
900 revision changed this so that all wCG registers are \
901 scratch registers. */ \
902 for (regno = FIRST_IWMMXT_GR_REGNUM; \
903 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
904 fixed_regs[regno] = 0; \
905 /* The XScale ABI has wR0 - wR9 as scratch registers, \
906 the rest as call-preserved registers. */ \
907 for (regno = FIRST_IWMMXT_REGNUM; \
908 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
909 { \
910 fixed_regs[regno] = 0; \
911 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
912 } \
913 } \
914 \
915 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
916 { \
917 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
918 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
919 } \
920 else if (TARGET_APCS_STACK) \
921 { \
922 fixed_regs[10] = 1; \
923 call_used_regs[10] = 1; \
924 } \
925 /* -mcaller-super-interworking reserves r11 for calls to \
926 _interwork_r11_call_via_rN(). Making the register global \
927 is an easy way of ensuring that it remains valid for all \
928 calls. */ \
929 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING) \
930 { \
931 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
932 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
933 if (TARGET_CALLER_INTERWORKING) \
934 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
935 } \
936 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
937 }
938
939 /* These are a couple of extensions to the formats accepted
940 by asm_fprintf:
941 %@ prints out ASM_COMMENT_START
942 %r prints out REGISTER_PREFIX reg_names[arg] */
943 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
944 case '@': \
945 fputs (ASM_COMMENT_START, FILE); \
946 break; \
947 \
948 case 'r': \
949 fputs (REGISTER_PREFIX, FILE); \
950 fputs (reg_names [va_arg (ARGS, int)], FILE); \
951 break;
952
953 /* Round X up to the nearest word. */
954 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
955
956 /* Convert fron bytes to ints. */
957 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
958
959 /* The number of (integer) registers required to hold a quantity of type MODE.
960 Also used for VFP registers. */
961 #define ARM_NUM_REGS(MODE) \
962 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
963
964 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
965 #define ARM_NUM_REGS2(MODE, TYPE) \
966 ARM_NUM_INTS ((MODE) == BLKmode ? \
967 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
968
969 /* The number of (integer) argument register available. */
970 #define NUM_ARG_REGS 4
971
972 /* Return the register number of the N'th (integer) argument. */
973 #define ARG_REGISTER(N) (N - 1)
974
975 /* Specify the registers used for certain standard purposes.
976 The values of these macros are register numbers. */
977
978 /* The number of the last argument register. */
979 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
980
981 /* The numbers of the Thumb register ranges. */
982 #define FIRST_LO_REGNUM 0
983 #define LAST_LO_REGNUM 7
984 #define FIRST_HI_REGNUM 8
985 #define LAST_HI_REGNUM 11
986
987 /* We use sjlj exceptions for backwards compatibility. */
988 #define MUST_USE_SJLJ_EXCEPTIONS 1
989 /* We can generate DWARF2 Unwind info, even though we don't use it. */
990 #define DWARF2_UNWIND_INFO 1
991
992 /* Use r0 and r1 to pass exception handling information. */
993 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
994
995 /* The register that holds the return address in exception handlers. */
996 #define ARM_EH_STACKADJ_REGNUM 2
997 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
998
999 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1000 as an invisible last argument (possible since varargs don't exist in
1001 Pascal), so the following is not true. */
1002 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1003
1004 /* Define this to be where the real frame pointer is if it is not possible to
1005 work out the offset between the frame pointer and the automatic variables
1006 until after register allocation has taken place. FRAME_POINTER_REGNUM
1007 should point to a special register that we will make sure is eliminated.
1008
1009 For the Thumb we have another problem. The TPCS defines the frame pointer
1010 as r11, and GCC believes that it is always possible to use the frame pointer
1011 as base register for addressing purposes. (See comments in
1012 find_reloads_address()). But - the Thumb does not allow high registers,
1013 including r11, to be used as base address registers. Hence our problem.
1014
1015 The solution used here, and in the old thumb port is to use r7 instead of
1016 r11 as the hard frame pointer and to have special code to generate
1017 backtrace structures on the stack (if required to do so via a command line
1018 option) using r11. This is the only 'user visible' use of r11 as a frame
1019 pointer. */
1020 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1021 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1022
1023 #define HARD_FRAME_POINTER_REGNUM \
1024 (TARGET_ARM \
1025 ? ARM_HARD_FRAME_POINTER_REGNUM \
1026 : THUMB_HARD_FRAME_POINTER_REGNUM)
1027
1028 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1029
1030 /* Register to use for pushing function arguments. */
1031 #define STACK_POINTER_REGNUM SP_REGNUM
1032
1033 /* ARM floating pointer registers. */
1034 #define FIRST_FPA_REGNUM 16
1035 #define LAST_FPA_REGNUM 23
1036 #define IS_FPA_REGNUM(REGNUM) \
1037 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1038
1039 #define FIRST_IWMMXT_GR_REGNUM 43
1040 #define LAST_IWMMXT_GR_REGNUM 46
1041 #define FIRST_IWMMXT_REGNUM 47
1042 #define LAST_IWMMXT_REGNUM 62
1043 #define IS_IWMMXT_REGNUM(REGNUM) \
1044 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1045 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1046 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1047
1048 /* Base register for access to local variables of the function. */
1049 #define FRAME_POINTER_REGNUM 25
1050
1051 /* Base register for access to arguments of the function. */
1052 #define ARG_POINTER_REGNUM 26
1053
1054 #define FIRST_CIRRUS_FP_REGNUM 27
1055 #define LAST_CIRRUS_FP_REGNUM 42
1056 #define IS_CIRRUS_REGNUM(REGNUM) \
1057 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1058
1059 #define FIRST_VFP_REGNUM 63
1060 #define LAST_VFP_REGNUM 94
1061 #define IS_VFP_REGNUM(REGNUM) \
1062 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1063
1064 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1065 /* + 16 Cirrus registers take us up to 43. */
1066 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1067 /* VFP adds 32 + 1 more. */
1068 #define FIRST_PSEUDO_REGISTER 96
1069
1070 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1071
1072 /* Value should be nonzero if functions must have frame pointers.
1073 Zero means the frame pointer need not be set up (and parms may be accessed
1074 via the stack pointer) in functions that seem suitable.
1075 If we have to have a frame pointer we might as well make use of it.
1076 APCS says that the frame pointer does not need to be pushed in leaf
1077 functions, or simple tail call functions. */
1078 #define FRAME_POINTER_REQUIRED \
1079 (current_function_has_nonlocal_label \
1080 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1081
1082 /* Return number of consecutive hard regs needed starting at reg REGNO
1083 to hold something of mode MODE.
1084 This is ordinarily the length in words of a value of mode MODE
1085 but can be less for certain modes in special long registers.
1086
1087 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1088 mode. */
1089 #define HARD_REGNO_NREGS(REGNO, MODE) \
1090 ((TARGET_ARM \
1091 && REGNO >= FIRST_FPA_REGNUM \
1092 && REGNO != FRAME_POINTER_REGNUM \
1093 && REGNO != ARG_POINTER_REGNUM) \
1094 && !IS_VFP_REGNUM (REGNO) \
1095 ? 1 : ARM_NUM_REGS (MODE))
1096
1097 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1098 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1099 arm_hard_regno_mode_ok ((REGNO), (MODE))
1100
1101 /* Value is 1 if it is a good idea to tie two pseudo registers
1102 when one has mode MODE1 and one has mode MODE2.
1103 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1104 for any hard reg, then this must be 0 for correct output. */
1105 #define MODES_TIEABLE_P(MODE1, MODE2) \
1106 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1107
1108 #define VALID_IWMMXT_REG_MODE(MODE) \
1109 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1110
1111 /* The order in which register should be allocated. It is good to use ip
1112 since no saving is required (though calls clobber it) and it never contains
1113 function parameters. It is quite good to use lr since other calls may
1114 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1115 least likely to contain a function parameter; in addition results are
1116 returned in r0. */
1117
1118 #define REG_ALLOC_ORDER \
1119 { \
1120 3, 2, 1, 0, 12, 14, 4, 5, \
1121 6, 7, 8, 10, 9, 11, 13, 15, \
1122 16, 17, 18, 19, 20, 21, 22, 23, \
1123 27, 28, 29, 30, 31, 32, 33, 34, \
1124 35, 36, 37, 38, 39, 40, 41, 42, \
1125 43, 44, 45, 46, 47, 48, 49, 50, \
1126 51, 52, 53, 54, 55, 56, 57, 58, \
1127 59, 60, 61, 62, \
1128 24, 25, 26, \
1129 78, 77, 76, 75, 74, 73, 72, 71, \
1130 70, 69, 68, 67, 66, 65, 64, 63, \
1131 79, 80, 81, 82, 83, 84, 85, 86, \
1132 87, 88, 89, 90, 91, 92, 93, 94, \
1133 95 \
1134 }
1135
1136 /* Interrupt functions can only use registers that have already been
1137 saved by the prologue, even if they would normally be
1138 call-clobbered. */
1139 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1140 (! IS_INTERRUPT (cfun->machine->func_type) || \
1141 regs_ever_live[DST])
1142 \f
1143 /* Register and constant classes. */
1144
1145 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1146 Now that the Thumb is involved it has become more complicated. */
1147 enum reg_class
1148 {
1149 NO_REGS,
1150 FPA_REGS,
1151 CIRRUS_REGS,
1152 VFP_REGS,
1153 IWMMXT_GR_REGS,
1154 IWMMXT_REGS,
1155 LO_REGS,
1156 STACK_REG,
1157 BASE_REGS,
1158 HI_REGS,
1159 CC_REG,
1160 VFPCC_REG,
1161 GENERAL_REGS,
1162 ALL_REGS,
1163 LIM_REG_CLASSES
1164 };
1165
1166 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1167
1168 /* Give names of register classes as strings for dump file. */
1169 #define REG_CLASS_NAMES \
1170 { \
1171 "NO_REGS", \
1172 "FPA_REGS", \
1173 "CIRRUS_REGS", \
1174 "VFP_REGS", \
1175 "IWMMXT_GR_REGS", \
1176 "IWMMXT_REGS", \
1177 "LO_REGS", \
1178 "STACK_REG", \
1179 "BASE_REGS", \
1180 "HI_REGS", \
1181 "CC_REG", \
1182 "VFPCC_REG", \
1183 "GENERAL_REGS", \
1184 "ALL_REGS", \
1185 }
1186
1187 /* Define which registers fit in which classes.
1188 This is an initializer for a vector of HARD_REG_SET
1189 of length N_REG_CLASSES. */
1190 #define REG_CLASS_CONTENTS \
1191 { \
1192 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1193 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1194 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1195 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1196 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1197 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1198 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1199 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1200 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1201 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1202 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1203 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1204 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1205 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1206 }
1207
1208 /* The same information, inverted:
1209 Return the class number of the smallest class containing
1210 reg number REGNO. This could be a conditional expression
1211 or could index an array. */
1212 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1213
1214 /* FPA registers can't do subreg as all values are reformatted to internal
1215 precision. VFP registers may only be accessed in the mode they
1216 were set. */
1217 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1218 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1219 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1220 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1221 : 0)
1222
1223 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1224 using r0-r4 for function arguments, r7 for the stack frame and don't
1225 have enough left over to do doubleword arithmetic. */
1226 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1227 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1228 || (CLASS) == CC_REG)
1229
1230 /* The class value for index registers, and the one for base regs. */
1231 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1232 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1233
1234 /* For the Thumb the high registers cannot be used as base registers
1235 when addressing quantities in QI or HI mode; if we don't know the
1236 mode, then we must be conservative. */
1237 #define MODE_BASE_REG_CLASS(MODE) \
1238 (TARGET_ARM ? GENERAL_REGS : \
1239 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1240
1241 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1242 instead of BASE_REGS. */
1243 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1244
1245 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1246 registers explicitly used in the rtl to be used as spill registers
1247 but prevents the compiler from extending the lifetime of these
1248 registers. */
1249 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1250
1251 /* Get reg_class from a letter such as appears in the machine description.
1252 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1253 ARM, but several more letters for the Thumb. */
1254 #define REG_CLASS_FROM_LETTER(C) \
1255 ( (C) == 'f' ? FPA_REGS \
1256 : (C) == 'v' ? CIRRUS_REGS \
1257 : (C) == 'w' ? VFP_REGS \
1258 : (C) == 'y' ? IWMMXT_REGS \
1259 : (C) == 'z' ? IWMMXT_GR_REGS \
1260 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1261 : TARGET_ARM ? NO_REGS \
1262 : (C) == 'h' ? HI_REGS \
1263 : (C) == 'b' ? BASE_REGS \
1264 : (C) == 'k' ? STACK_REG \
1265 : (C) == 'c' ? CC_REG \
1266 : NO_REGS)
1267
1268 /* The letters I, J, K, L and M in a register constraint string
1269 can be used to stand for particular ranges of immediate operands.
1270 This macro defines what the ranges are.
1271 C is the letter, and VALUE is a constant value.
1272 Return 1 if VALUE is in the range specified by C.
1273 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1274 J: valid indexing constants.
1275 K: ~value ok in rhs argument of data operand.
1276 L: -value ok in rhs argument of data operand.
1277 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1278 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1279 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1280 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1281 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1282 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1283 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1284 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1285 : 0)
1286
1287 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1288 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1289 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1290 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1291 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1292 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1293 && ((VAL) & 3) == 0) : \
1294 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1295 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1296 : 0)
1297
1298 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1299 (TARGET_ARM ? \
1300 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1301
1302 /* Constant letter 'G' for the FP immediate constants.
1303 'H' means the same constant negated. */
1304 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1305 ((C) == 'G' ? arm_const_double_rtx (X) : \
1306 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1307
1308 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1309 (TARGET_ARM ? \
1310 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1311
1312 /* For the ARM, `Q' means that this is a memory operand that is just
1313 an offset from a register.
1314 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1315 address. This means that the symbol is in the text segment and can be
1316 accessed without using a load.
1317 'D' Prefixes a number of const_double operands where:
1318 'Da' is a constant that takes two ARM insns to load.
1319 'Db' takes three ARM insns.
1320 'Dc' takes four ARM insns, if we allow that in this compilation.
1321 'U' Prefixes an extended memory constraint where:
1322 'Uv' is an address valid for VFP load/store insns.
1323 'Uy' is an address valid for iwmmxt load/store insns.
1324 'Uq' is an address valid for ldrsb. */
1325
1326 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1327 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1328 || GET_CODE (OP) == CONST_INT \
1329 || GET_CODE (OP) == CONST_VECTOR) \
1330 && (((STR)[1] == 'a' \
1331 && arm_const_double_inline_cost (OP) == 2) \
1332 || ((STR)[1] == 'b' \
1333 && arm_const_double_inline_cost (OP) == 3) \
1334 || ((STR)[1] == 'c' \
1335 && arm_const_double_inline_cost (OP) == 4 \
1336 && !(optimize_size || arm_ld_sched)))) : \
1337 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1338 && GET_CODE (XEXP (OP, 0)) == REG) : \
1339 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1340 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1341 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1342 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1343 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1344 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1345 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1346 ((C) == 'U' && (STR)[1] == 'q') \
1347 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1348 : 0)
1349
1350 #define CONSTRAINT_LEN(C,STR) \
1351 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1352
1353 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1354 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1355 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1356
1357 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1358 (TARGET_ARM \
1359 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1360 : EXTRA_CONSTRAINT_THUMB (X, C))
1361
1362 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1363
1364 /* Given an rtx X being reloaded into a reg required to be
1365 in class CLASS, return the class of reg to actually use.
1366 In general this is just CLASS, but for the Thumb we prefer
1367 a LO_REGS class or a subset. */
1368 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1369 (TARGET_ARM ? (CLASS) : \
1370 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1371
1372 /* Must leave BASE_REGS reloads alone */
1373 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1374 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1375 ? ((true_regnum (X) == -1 ? LO_REGS \
1376 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1377 : NO_REGS)) \
1378 : NO_REGS)
1379
1380 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1381 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1382 ? ((true_regnum (X) == -1 ? LO_REGS \
1383 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1384 : NO_REGS)) \
1385 : NO_REGS)
1386
1387 /* Return the register class of a scratch register needed to copy IN into
1388 or out of a register in CLASS in MODE. If it can be done directly,
1389 NO_REGS is returned. */
1390 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1391 /* Restrict which direct reloads are allowed for VFP regs. */ \
1392 ((TARGET_VFP && TARGET_HARD_FLOAT \
1393 && (CLASS) == VFP_REGS) \
1394 ? vfp_secondary_reload_class (MODE, X) \
1395 : TARGET_ARM \
1396 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1397 ? GENERAL_REGS : NO_REGS) \
1398 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1399
1400 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1401 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1402 /* Restrict which direct reloads are allowed for VFP regs. */ \
1403 ((TARGET_VFP && TARGET_HARD_FLOAT \
1404 && (CLASS) == VFP_REGS) \
1405 ? vfp_secondary_reload_class (MODE, X) : \
1406 /* Cannot load constants into Cirrus registers. */ \
1407 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1408 && (CLASS) == CIRRUS_REGS \
1409 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1410 ? GENERAL_REGS : \
1411 (TARGET_ARM ? \
1412 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1413 && CONSTANT_P (X)) \
1414 ? GENERAL_REGS : \
1415 (((MODE) == HImode && ! arm_arch4 \
1416 && (GET_CODE (X) == MEM \
1417 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1418 && true_regnum (X) == -1))) \
1419 ? GENERAL_REGS : NO_REGS) \
1420 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1421
1422 /* Try a machine-dependent way of reloading an illegitimate address
1423 operand. If we find one, push the reload and jump to WIN. This
1424 macro is used in only one place: `find_reloads_address' in reload.c.
1425
1426 For the ARM, we wish to handle large displacements off a base
1427 register by splitting the addend across a MOV and the mem insn.
1428 This can cut the number of reloads needed. */
1429 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1430 do \
1431 { \
1432 if (GET_CODE (X) == PLUS \
1433 && GET_CODE (XEXP (X, 0)) == REG \
1434 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1435 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1436 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1437 { \
1438 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1439 HOST_WIDE_INT low, high; \
1440 \
1441 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1442 low = ((val & 0xf) ^ 0x8) - 0x8; \
1443 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1444 /* Need to be careful, -256 is not a valid offset. */ \
1445 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1446 else if (MODE == SImode \
1447 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1448 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1449 /* Need to be careful, -4096 is not a valid offset. */ \
1450 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1451 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1452 /* Need to be careful, -256 is not a valid offset. */ \
1453 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1454 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1455 && TARGET_HARD_FLOAT && TARGET_FPA) \
1456 /* Need to be careful, -1024 is not a valid offset. */ \
1457 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1458 else \
1459 break; \
1460 \
1461 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1462 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1463 - (unsigned HOST_WIDE_INT) 0x80000000); \
1464 /* Check for overflow or zero */ \
1465 if (low == 0 || high == 0 || (high + low != val)) \
1466 break; \
1467 \
1468 /* Reload the high part into a base reg; leave the low part \
1469 in the mem. */ \
1470 X = gen_rtx_PLUS (GET_MODE (X), \
1471 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1472 GEN_INT (high)), \
1473 GEN_INT (low)); \
1474 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1475 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1476 VOIDmode, 0, 0, OPNUM, TYPE); \
1477 goto WIN; \
1478 } \
1479 } \
1480 while (0)
1481
1482 /* XXX If an HImode FP+large_offset address is converted to an HImode
1483 SP+large_offset address, then reload won't know how to fix it. It sees
1484 only that SP isn't valid for HImode, and so reloads the SP into an index
1485 register, but the resulting address is still invalid because the offset
1486 is too big. We fix it here instead by reloading the entire address. */
1487 /* We could probably achieve better results by defining PROMOTE_MODE to help
1488 cope with the variances between the Thumb's signed and unsigned byte and
1489 halfword load instructions. */
1490 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1491 { \
1492 if (GET_CODE (X) == PLUS \
1493 && GET_MODE_SIZE (MODE) < 4 \
1494 && GET_CODE (XEXP (X, 0)) == REG \
1495 && XEXP (X, 0) == stack_pointer_rtx \
1496 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1497 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1498 { \
1499 rtx orig_X = X; \
1500 X = copy_rtx (X); \
1501 push_reload (orig_X, NULL_RTX, &X, NULL, \
1502 MODE_BASE_REG_CLASS (MODE), \
1503 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1504 goto WIN; \
1505 } \
1506 }
1507
1508 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1509 if (TARGET_ARM) \
1510 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1511 else \
1512 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1513
1514 /* Return the maximum number of consecutive registers
1515 needed to represent mode MODE in a register of class CLASS.
1516 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1517 #define CLASS_MAX_NREGS(CLASS, MODE) \
1518 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1519
1520 /* If defined, gives a class of registers that cannot be used as the
1521 operand of a SUBREG that changes the mode of the object illegally. */
1522
1523 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1524 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1525 (TARGET_ARM ? \
1526 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1527 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1528 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1529 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1530 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1531 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1532 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1533 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1534 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1535 2) \
1536 : \
1537 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1538 \f
1539 /* Stack layout; function entry, exit and calling. */
1540
1541 /* Define this if pushing a word on the stack
1542 makes the stack pointer a smaller address. */
1543 #define STACK_GROWS_DOWNWARD 1
1544
1545 /* Define this if the nominal address of the stack frame
1546 is at the high-address end of the local variables;
1547 that is, each additional local variable allocated
1548 goes at a more negative offset in the frame. */
1549 #define FRAME_GROWS_DOWNWARD 1
1550
1551 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1552 When present, it is one word in size, and sits at the top of the frame,
1553 between the soft frame pointer and either r7 or r11.
1554
1555 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1556 and only then if some outgoing arguments are passed on the stack. It would
1557 be tempting to also check whether the stack arguments are passed by indirect
1558 calls, but there seems to be no reason in principle why a post-reload pass
1559 couldn't convert a direct call into an indirect one. */
1560 #define CALLER_INTERWORKING_SLOT_SIZE \
1561 (TARGET_CALLER_INTERWORKING \
1562 && current_function_outgoing_args_size != 0 \
1563 ? UNITS_PER_WORD : 0)
1564
1565 /* Offset within stack frame to start allocating local variables at.
1566 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1567 first local allocated. Otherwise, it is the offset to the BEGINNING
1568 of the first local allocated. */
1569 #define STARTING_FRAME_OFFSET 0
1570
1571 /* If we generate an insn to push BYTES bytes,
1572 this says how many the stack pointer really advances by. */
1573 /* The push insns do not do this rounding implicitly.
1574 So don't define this. */
1575 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1576
1577 /* Define this if the maximum size of all the outgoing args is to be
1578 accumulated and pushed during the prologue. The amount can be
1579 found in the variable current_function_outgoing_args_size. */
1580 #define ACCUMULATE_OUTGOING_ARGS 1
1581
1582 /* Offset of first parameter from the argument pointer register value. */
1583 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1584
1585 /* Value is the number of byte of arguments automatically
1586 popped when returning from a subroutine call.
1587 FUNDECL is the declaration node of the function (as a tree),
1588 FUNTYPE is the data type of the function (as a tree),
1589 or for a library call it is an identifier node for the subroutine name.
1590 SIZE is the number of bytes of arguments passed on the stack.
1591
1592 On the ARM, the caller does not pop any of its arguments that were passed
1593 on the stack. */
1594 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1595
1596 /* Define how to find the value returned by a library function
1597 assuming the value has mode MODE. */
1598 #define LIBCALL_VALUE(MODE) \
1599 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1600 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1601 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1602 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1603 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1604 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1605 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1606 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1607 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1608
1609 /* Define how to find the value returned by a function.
1610 VALTYPE is the data type of the value (as a tree).
1611 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1612 otherwise, FUNC is 0. */
1613 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1614 arm_function_value (VALTYPE, FUNC);
1615
1616 /* 1 if N is a possible register number for a function value.
1617 On the ARM, only r0 and f0 can return results. */
1618 /* On a Cirrus chip, mvf0 can return results. */
1619 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1620 ((REGNO) == ARG_REGISTER (1) \
1621 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1622 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1623 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1624 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1625 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1626
1627 /* Amount of memory needed for an untyped call to save all possible return
1628 registers. */
1629 #define APPLY_RESULT_SIZE arm_apply_result_size()
1630
1631 /* How large values are returned */
1632 /* A C expression which can inhibit the returning of certain function values
1633 in registers, based on the type of value. */
1634 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1635
1636 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1637 values must be in memory. On the ARM, they need only do so if larger
1638 than a word, or if they contain elements offset from zero in the struct. */
1639 #define DEFAULT_PCC_STRUCT_RETURN 0
1640
1641 /* Flags for the call/call_value rtl operations set up by function_arg. */
1642 #define CALL_NORMAL 0x00000000 /* No special processing. */
1643 #define CALL_LONG 0x00000001 /* Always call indirect. */
1644 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1645
1646 /* These bits describe the different types of function supported
1647 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1648 normal function and an interworked function, for example. Knowing the
1649 type of a function is important for determining its prologue and
1650 epilogue sequences.
1651 Note value 7 is currently unassigned. Also note that the interrupt
1652 function types all have bit 2 set, so that they can be tested for easily.
1653 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1654 machine_function structure is initialized (to zero) func_type will
1655 default to unknown. This will force the first use of arm_current_func_type
1656 to call arm_compute_func_type. */
1657 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1658 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1659 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1660 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1661 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1662 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1663
1664 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1665
1666 /* In addition functions can have several type modifiers,
1667 outlined by these bit masks: */
1668 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1669 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1670 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1671 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1672
1673 /* Some macros to test these flags. */
1674 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1675 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1676 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1677 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1678 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1679
1680
1681 /* Structure used to hold the function stack frame layout. Offsets are
1682 relative to the stack pointer on function entry. Positive offsets are
1683 in the direction of stack growth.
1684 Only soft_frame is used in thumb mode. */
1685
1686 typedef struct arm_stack_offsets GTY(())
1687 {
1688 int saved_args; /* ARG_POINTER_REGNUM. */
1689 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1690 int saved_regs;
1691 int soft_frame; /* FRAME_POINTER_REGNUM. */
1692 int outgoing_args; /* STACK_POINTER_REGNUM. */
1693 }
1694 arm_stack_offsets;
1695
1696 /* A C structure for machine-specific, per-function data.
1697 This is added to the cfun structure. */
1698 typedef struct machine_function GTY(())
1699 {
1700 /* Additional stack adjustment in __builtin_eh_throw. */
1701 rtx eh_epilogue_sp_ofs;
1702 /* Records if LR has to be saved for far jumps. */
1703 int far_jump_used;
1704 /* Records if ARG_POINTER was ever live. */
1705 int arg_pointer_live;
1706 /* Records if the save of LR has been eliminated. */
1707 int lr_save_eliminated;
1708 /* The size of the stack frame. Only valid after reload. */
1709 arm_stack_offsets stack_offsets;
1710 /* Records the type of the current function. */
1711 unsigned long func_type;
1712 /* Record if the function has a variable argument list. */
1713 int uses_anonymous_args;
1714 /* Records if sibcalls are blocked because an argument
1715 register is needed to preserve stack alignment. */
1716 int sibcall_blocked;
1717 /* Labels for per-function Thumb call-via stubs. One per potential calling
1718 register. We can never call via LR or PC. We can call via SP if a
1719 trampoline happens to be on the top of the stack. */
1720 rtx call_via[14];
1721 }
1722 machine_function;
1723
1724 /* As in the machine_function, a global set of call-via labels, for code
1725 that is in text_section(). */
1726 extern GTY(()) rtx thumb_call_via_label[14];
1727
1728 /* A C type for declaring a variable that is used as the first argument of
1729 `FUNCTION_ARG' and other related values. For some target machines, the
1730 type `int' suffices and can hold the number of bytes of argument so far. */
1731 typedef struct
1732 {
1733 /* This is the number of registers of arguments scanned so far. */
1734 int nregs;
1735 /* This is the number of iWMMXt register arguments scanned so far. */
1736 int iwmmxt_nregs;
1737 int named_count;
1738 int nargs;
1739 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1740 int call_cookie;
1741 int can_split;
1742 } CUMULATIVE_ARGS;
1743
1744 /* Define where to put the arguments to a function.
1745 Value is zero to push the argument on the stack,
1746 or a hard register in which to store the argument.
1747
1748 MODE is the argument's machine mode.
1749 TYPE is the data type of the argument (as a tree).
1750 This is null for libcalls where that information may
1751 not be available.
1752 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1753 the preceding args and about the function being called.
1754 NAMED is nonzero if this argument is a named parameter
1755 (otherwise it is an extra parameter matching an ellipsis).
1756
1757 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1758 other arguments are passed on the stack. If (NAMED == 0) (which happens
1759 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1760 defined), say it is passed in the stack (function_prologue will
1761 indeed make it pass in the stack if necessary). */
1762 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1763 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1764
1765 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1766 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1767
1768 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1769 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1770
1771 /* For AAPCS, padding should never be below the argument. For other ABIs,
1772 * mimic the default. */
1773 #define PAD_VARARGS_DOWN \
1774 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1775
1776 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1777 for a call to a function whose data type is FNTYPE.
1778 For a library call, FNTYPE is 0.
1779 On the ARM, the offset starts at 0. */
1780 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1781 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1782
1783 /* Update the data in CUM to advance over an argument
1784 of mode MODE and data type TYPE.
1785 (TYPE is null for libcalls where that information may not be available.) */
1786 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1787 (CUM).nargs += 1; \
1788 if (arm_vector_mode_supported_p (MODE) \
1789 && (CUM).named_count > (CUM).nargs) \
1790 (CUM).iwmmxt_nregs += 1; \
1791 else \
1792 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1793
1794 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1795 argument with the specified mode and type. If it is not defined,
1796 `PARM_BOUNDARY' is used for all arguments. */
1797 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1798 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1799 ? DOUBLEWORD_ALIGNMENT \
1800 : PARM_BOUNDARY )
1801
1802 /* 1 if N is a possible register number for function argument passing.
1803 On the ARM, r0-r3 are used to pass args. */
1804 #define FUNCTION_ARG_REGNO_P(REGNO) \
1805 (IN_RANGE ((REGNO), 0, 3) \
1806 || (TARGET_IWMMXT_ABI \
1807 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1808
1809 \f
1810 /* If your target environment doesn't prefix user functions with an
1811 underscore, you may wish to re-define this to prevent any conflicts.
1812 e.g. AOF may prefix mcount with an underscore. */
1813 #ifndef ARM_MCOUNT_NAME
1814 #define ARM_MCOUNT_NAME "*mcount"
1815 #endif
1816
1817 /* Call the function profiler with a given profile label. The Acorn
1818 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1819 On the ARM the full profile code will look like:
1820 .data
1821 LP1
1822 .word 0
1823 .text
1824 mov ip, lr
1825 bl mcount
1826 .word LP1
1827
1828 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1829 will output the .text section.
1830
1831 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1832 ``prof'' doesn't seem to mind about this!
1833
1834 Note - this version of the code is designed to work in both ARM and
1835 Thumb modes. */
1836 #ifndef ARM_FUNCTION_PROFILER
1837 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1838 { \
1839 char temp[20]; \
1840 rtx sym; \
1841 \
1842 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1843 IP_REGNUM, LR_REGNUM); \
1844 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1845 fputc ('\n', STREAM); \
1846 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1847 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1848 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1849 }
1850 #endif
1851
1852 #ifdef THUMB_FUNCTION_PROFILER
1853 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1854 if (TARGET_ARM) \
1855 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1856 else \
1857 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1858 #else
1859 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1860 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1861 #endif
1862
1863 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1864 the stack pointer does not matter. The value is tested only in
1865 functions that have frame pointers.
1866 No definition is equivalent to always zero.
1867
1868 On the ARM, the function epilogue recovers the stack pointer from the
1869 frame. */
1870 #define EXIT_IGNORE_STACK 1
1871
1872 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1873
1874 /* Determine if the epilogue should be output as RTL.
1875 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1876 #define USE_RETURN_INSN(ISCOND) \
1877 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1878
1879 /* Definitions for register eliminations.
1880
1881 This is an array of structures. Each structure initializes one pair
1882 of eliminable registers. The "from" register number is given first,
1883 followed by "to". Eliminations of the same "from" register are listed
1884 in order of preference.
1885
1886 We have two registers that can be eliminated on the ARM. First, the
1887 arg pointer register can often be eliminated in favor of the stack
1888 pointer register. Secondly, the pseudo frame pointer register can always
1889 be eliminated; it is replaced with either the stack or the real frame
1890 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1891 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1892
1893 #define ELIMINABLE_REGS \
1894 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1895 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1896 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1897 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1898 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1899 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1900 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1901
1902 /* Given FROM and TO register numbers, say whether this elimination is
1903 allowed. Frame pointer elimination is automatically handled.
1904
1905 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1906 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1907 pointer, we must eliminate FRAME_POINTER_REGNUM into
1908 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1909 ARG_POINTER_REGNUM. */
1910 #define CAN_ELIMINATE(FROM, TO) \
1911 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1912 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1913 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1914 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1915 1)
1916
1917 /* Define the offset between two registers, one to be eliminated, and the
1918 other its replacement, at the start of a routine. */
1919 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1920 if (TARGET_ARM) \
1921 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1922 else \
1923 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1924
1925 /* Special case handling of the location of arguments passed on the stack. */
1926 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1927
1928 /* Initialize data used by insn expanders. This is called from insn_emit,
1929 once for every function before code is generated. */
1930 #define INIT_EXPANDERS arm_init_expanders ()
1931
1932 /* Output assembler code for a block containing the constant parts
1933 of a trampoline, leaving space for the variable parts.
1934
1935 On the ARM, (if r8 is the static chain regnum, and remembering that
1936 referencing pc adds an offset of 8) the trampoline looks like:
1937 ldr r8, [pc, #0]
1938 ldr pc, [pc]
1939 .word static chain value
1940 .word function's address
1941 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1942 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1943 { \
1944 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1945 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1946 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1947 PC_REGNUM, PC_REGNUM); \
1948 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1949 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1950 }
1951
1952 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1953 Why - because it is easier. This code will always be branched to via
1954 a BX instruction and since the compiler magically generates the address
1955 of the function the linker has no opportunity to ensure that the
1956 bottom bit is set. Thus the processor will be in ARM mode when it
1957 reaches this code. So we duplicate the ARM trampoline code and add
1958 a switch into Thumb mode as well. */
1959 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1960 { \
1961 fprintf (FILE, "\t.code 32\n"); \
1962 fprintf (FILE, ".Ltrampoline_start:\n"); \
1963 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1964 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1965 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1966 IP_REGNUM, PC_REGNUM); \
1967 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1968 IP_REGNUM, IP_REGNUM); \
1969 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1970 fprintf (FILE, "\t.word\t0\n"); \
1971 fprintf (FILE, "\t.word\t0\n"); \
1972 fprintf (FILE, "\t.code 16\n"); \
1973 }
1974
1975 #define TRAMPOLINE_TEMPLATE(FILE) \
1976 if (TARGET_ARM) \
1977 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1978 else \
1979 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1980
1981 /* Length in units of the trampoline for entering a nested function. */
1982 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1983
1984 /* Alignment required for a trampoline in bits. */
1985 #define TRAMPOLINE_ALIGNMENT 32
1986
1987 /* Emit RTL insns to initialize the variable parts of a trampoline.
1988 FNADDR is an RTX for the address of the function's pure code.
1989 CXT is an RTX for the static chain value for the function. */
1990 #ifndef INITIALIZE_TRAMPOLINE
1991 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1992 { \
1993 emit_move_insn (gen_rtx_MEM (SImode, \
1994 plus_constant (TRAMP, \
1995 TARGET_ARM ? 8 : 16)), \
1996 CXT); \
1997 emit_move_insn (gen_rtx_MEM (SImode, \
1998 plus_constant (TRAMP, \
1999 TARGET_ARM ? 12 : 20)), \
2000 FNADDR); \
2001 }
2002 #endif
2003
2004 \f
2005 /* Addressing modes, and classification of registers for them. */
2006 #define HAVE_POST_INCREMENT 1
2007 #define HAVE_PRE_INCREMENT TARGET_ARM
2008 #define HAVE_POST_DECREMENT TARGET_ARM
2009 #define HAVE_PRE_DECREMENT TARGET_ARM
2010 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2011 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2012 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2013 #define HAVE_POST_MODIFY_REG TARGET_ARM
2014
2015 /* Macros to check register numbers against specific register classes. */
2016
2017 /* These assume that REGNO is a hard or pseudo reg number.
2018 They give nonzero only if REGNO is a hard reg of the suitable class
2019 or a pseudo reg currently allocated to a suitable hard reg.
2020 Since they use reg_renumber, they are safe only once reg_renumber
2021 has been allocated, which happens in local-alloc.c. */
2022 #define TEST_REGNO(R, TEST, VALUE) \
2023 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2024
2025 /* On the ARM, don't allow the pc to be used. */
2026 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2027 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2028 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2029 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2030
2031 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2032 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2033 || (GET_MODE_SIZE (MODE) >= 4 \
2034 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2035
2036 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2037 (TARGET_THUMB \
2038 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2039 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2040
2041 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2042 For Thumb, we can not use SP + reg, so reject SP. */
2043 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2044 REGNO_OK_FOR_INDEX_P (X)
2045
2046 /* For ARM code, we don't care about the mode, but for Thumb, the index
2047 must be suitable for use in a QImode load. */
2048 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2049 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2050
2051 /* Maximum number of registers that can appear in a valid memory address.
2052 Shifts in addresses can't be by a register. */
2053 #define MAX_REGS_PER_ADDRESS 2
2054
2055 /* Recognize any constant value that is a valid address. */
2056 /* XXX We can address any constant, eventually... */
2057
2058 #ifdef AOF_ASSEMBLER
2059
2060 #define CONSTANT_ADDRESS_P(X) \
2061 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2062
2063 #else
2064
2065 #define CONSTANT_ADDRESS_P(X) \
2066 (GET_CODE (X) == SYMBOL_REF \
2067 && (CONSTANT_POOL_ADDRESS_P (X) \
2068 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2069
2070 #endif /* AOF_ASSEMBLER */
2071
2072 /* Nonzero if the constant value X is a legitimate general operand.
2073 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2074
2075 On the ARM, allow any integer (invalid ones are removed later by insn
2076 patterns), nice doubles and symbol_refs which refer to the function's
2077 constant pool XXX.
2078
2079 When generating pic allow anything. */
2080 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2081
2082 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2083 ( GET_CODE (X) == CONST_INT \
2084 || GET_CODE (X) == CONST_DOUBLE \
2085 || CONSTANT_ADDRESS_P (X) \
2086 || flag_pic)
2087
2088 #define LEGITIMATE_CONSTANT_P(X) \
2089 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2090
2091 /* Special characters prefixed to function names
2092 in order to encode attribute like information.
2093 Note, '@' and '*' have already been taken. */
2094 #define SHORT_CALL_FLAG_CHAR '^'
2095 #define LONG_CALL_FLAG_CHAR '#'
2096
2097 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2098 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2099
2100 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2101 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2102
2103 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2104 #define SUBTARGET_NAME_ENCODING_LENGTHS
2105 #endif
2106
2107 /* This is a C fragment for the inside of a switch statement.
2108 Each case label should return the number of characters to
2109 be stripped from the start of a function's name, if that
2110 name starts with the indicated character. */
2111 #define ARM_NAME_ENCODING_LENGTHS \
2112 case SHORT_CALL_FLAG_CHAR: return 1; \
2113 case LONG_CALL_FLAG_CHAR: return 1; \
2114 case '*': return 1; \
2115 SUBTARGET_NAME_ENCODING_LENGTHS
2116
2117 /* This is how to output a reference to a user-level label named NAME.
2118 `assemble_name' uses this. */
2119 #undef ASM_OUTPUT_LABELREF
2120 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2121 arm_asm_output_labelref (FILE, NAME)
2122
2123 /* True if the operating system can merge entities with vague linkage
2124 (e.g., symbols in COMDAT group) during dynamic linking. */
2125 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2126 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2127 #endif
2128
2129 /* Set the short-call flag for any function compiled in the current
2130 compilation unit. We skip this for functions with the section
2131 attribute when long-calls are in effect as this tells the compiler
2132 that the section might be placed a long way from the caller.
2133 See arm_is_longcall_p() for more information. */
2134 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2135 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2136 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2137
2138 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2139 and check its validity for a certain class.
2140 We have two alternate definitions for each of them.
2141 The usual definition accepts all pseudo regs; the other rejects
2142 them unless they have been allocated suitable hard regs.
2143 The symbol REG_OK_STRICT causes the latter definition to be used. */
2144 #ifndef REG_OK_STRICT
2145
2146 #define ARM_REG_OK_FOR_BASE_P(X) \
2147 (REGNO (X) <= LAST_ARM_REGNUM \
2148 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2149 || REGNO (X) == FRAME_POINTER_REGNUM \
2150 || REGNO (X) == ARG_POINTER_REGNUM)
2151
2152 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2153 (REGNO (X) <= LAST_LO_REGNUM \
2154 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2155 || (GET_MODE_SIZE (MODE) >= 4 \
2156 && (REGNO (X) == STACK_POINTER_REGNUM \
2157 || (X) == hard_frame_pointer_rtx \
2158 || (X) == arg_pointer_rtx)))
2159
2160 #define REG_STRICT_P 0
2161
2162 #else /* REG_OK_STRICT */
2163
2164 #define ARM_REG_OK_FOR_BASE_P(X) \
2165 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2166
2167 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2168 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2169
2170 #define REG_STRICT_P 1
2171
2172 #endif /* REG_OK_STRICT */
2173
2174 /* Now define some helpers in terms of the above. */
2175
2176 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2177 (TARGET_THUMB \
2178 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2179 : ARM_REG_OK_FOR_BASE_P (X))
2180
2181 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2182
2183 /* For Thumb, a valid index register is anything that can be used in
2184 a byte load instruction. */
2185 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2186
2187 /* Nonzero if X is a hard reg that can be used as an index
2188 or if it is a pseudo reg. On the Thumb, the stack pointer
2189 is not suitable. */
2190 #define REG_OK_FOR_INDEX_P(X) \
2191 (TARGET_THUMB \
2192 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2193 : ARM_REG_OK_FOR_INDEX_P (X))
2194
2195 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2196 For Thumb, we can not use SP + reg, so reject SP. */
2197 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2198 REG_OK_FOR_INDEX_P (X)
2199 \f
2200 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2201 that is a valid memory address for an instruction.
2202 The MODE argument is the machine mode for the MEM expression
2203 that wants to use this address. */
2204
2205 #define ARM_BASE_REGISTER_RTX_P(X) \
2206 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2207
2208 #define ARM_INDEX_REGISTER_RTX_P(X) \
2209 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2210
2211 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2212 { \
2213 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2214 goto WIN; \
2215 }
2216
2217 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2218 { \
2219 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2220 goto WIN; \
2221 }
2222
2223 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2224 if (TARGET_ARM) \
2225 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2226 else /* if (TARGET_THUMB) */ \
2227 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2228
2229 \f
2230 /* Try machine-dependent ways of modifying an illegitimate address
2231 to be legitimate. If we find one, return the new, valid address. */
2232 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2233 do { \
2234 X = arm_legitimize_address (X, OLDX, MODE); \
2235 } while (0)
2236
2237 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2238 do { \
2239 X = thumb_legitimize_address (X, OLDX, MODE); \
2240 } while (0)
2241
2242 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2243 do { \
2244 if (TARGET_ARM) \
2245 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2246 else \
2247 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2248 \
2249 if (memory_address_p (MODE, X)) \
2250 goto WIN; \
2251 } while (0)
2252
2253 /* Go to LABEL if ADDR (a legitimate address expression)
2254 has an effect that depends on the machine mode it is used for. */
2255 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2256 { \
2257 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2258 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2259 goto LABEL; \
2260 }
2261
2262 /* Nothing helpful to do for the Thumb */
2263 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2264 if (TARGET_ARM) \
2265 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2266 \f
2267
2268 /* Specify the machine mode that this machine uses
2269 for the index in the tablejump instruction. */
2270 #define CASE_VECTOR_MODE Pmode
2271
2272 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2273 unsigned is probably best, but may break some code. */
2274 #ifndef DEFAULT_SIGNED_CHAR
2275 #define DEFAULT_SIGNED_CHAR 0
2276 #endif
2277
2278 /* Max number of bytes we can move from memory to memory
2279 in one reasonably fast instruction. */
2280 #define MOVE_MAX 4
2281
2282 #undef MOVE_RATIO
2283 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2284
2285 /* Define if operations between registers always perform the operation
2286 on the full register even if a narrower mode is specified. */
2287 #define WORD_REGISTER_OPERATIONS
2288
2289 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2290 will either zero-extend or sign-extend. The value of this macro should
2291 be the code that says which one of the two operations is implicitly
2292 done, UNKNOWN if none. */
2293 #define LOAD_EXTEND_OP(MODE) \
2294 (TARGET_THUMB ? ZERO_EXTEND : \
2295 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2296 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2297
2298 /* Nonzero if access to memory by bytes is slow and undesirable. */
2299 #define SLOW_BYTE_ACCESS 0
2300
2301 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2302
2303 /* Immediate shift counts are truncated by the output routines (or was it
2304 the assembler?). Shift counts in a register are truncated by ARM. Note
2305 that the native compiler puts too large (> 32) immediate shift counts
2306 into a register and shifts by the register, letting the ARM decide what
2307 to do instead of doing that itself. */
2308 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2309 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2310 On the arm, Y in a register is used modulo 256 for the shift. Only for
2311 rotates is modulo 32 used. */
2312 /* #define SHIFT_COUNT_TRUNCATED 1 */
2313
2314 /* All integers have the same format so truncation is easy. */
2315 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2316
2317 /* Calling from registers is a massive pain. */
2318 #define NO_FUNCTION_CSE 1
2319
2320 /* The machine modes of pointers and functions */
2321 #define Pmode SImode
2322 #define FUNCTION_MODE Pmode
2323
2324 #define ARM_FRAME_RTX(X) \
2325 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2326 || (X) == arg_pointer_rtx)
2327
2328 /* Moves to and from memory are quite expensive */
2329 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2330 (TARGET_ARM ? 10 : \
2331 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2332 * (CLASS == LO_REGS ? 1 : 2)))
2333
2334 /* Try to generate sequences that don't involve branches, we can then use
2335 conditional instructions */
2336 #define BRANCH_COST \
2337 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2338 \f
2339 /* Position Independent Code. */
2340 /* We decide which register to use based on the compilation options and
2341 the assembler in use; this is more general than the APCS restriction of
2342 using sb (r9) all the time. */
2343 extern int arm_pic_register;
2344
2345 /* Used when parsing command line option -mpic-register=. */
2346 extern const char * arm_pic_register_string;
2347
2348 /* The register number of the register used to address a table of static
2349 data addresses in memory. */
2350 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2351
2352 /* We can't directly access anything that contains a symbol,
2353 nor can we indirect via the constant pool. */
2354 #define LEGITIMATE_PIC_OPERAND_P(X) \
2355 (!(symbol_mentioned_p (X) \
2356 || label_mentioned_p (X) \
2357 || (GET_CODE (X) == SYMBOL_REF \
2358 && CONSTANT_POOL_ADDRESS_P (X) \
2359 && (symbol_mentioned_p (get_pool_constant (X)) \
2360 || label_mentioned_p (get_pool_constant (X))))))
2361
2362 /* We need to know when we are making a constant pool; this determines
2363 whether data needs to be in the GOT or can be referenced via a GOT
2364 offset. */
2365 extern int making_const_table;
2366 \f
2367 /* Handle pragmas for compatibility with Intel's compilers. */
2368 #define REGISTER_TARGET_PRAGMAS() do { \
2369 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2370 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2371 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2372 } while (0)
2373
2374 /* Condition code information. */
2375 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2376 return the mode to be used for the comparison. */
2377
2378 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2379
2380 #define REVERSIBLE_CC_MODE(MODE) 1
2381
2382 #define REVERSE_CONDITION(CODE,MODE) \
2383 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2384 ? reverse_condition_maybe_unordered (code) \
2385 : reverse_condition (code))
2386
2387 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2388 do \
2389 { \
2390 if (GET_CODE (OP1) == CONST_INT \
2391 && ! (const_ok_for_arm (INTVAL (OP1)) \
2392 || (const_ok_for_arm (- INTVAL (OP1))))) \
2393 { \
2394 rtx const_op = OP1; \
2395 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2396 OP1 = const_op; \
2397 } \
2398 } \
2399 while (0)
2400
2401 /* The arm5 clz instruction returns 32. */
2402 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2403 \f
2404 #undef ASM_APP_OFF
2405 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2406
2407 /* Output a push or a pop instruction (only used when profiling). */
2408 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2409 do \
2410 { \
2411 if (TARGET_ARM) \
2412 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2413 STACK_POINTER_REGNUM, REGNO); \
2414 else \
2415 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2416 } while (0)
2417
2418
2419 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2420 do \
2421 { \
2422 if (TARGET_ARM) \
2423 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2424 STACK_POINTER_REGNUM, REGNO); \
2425 else \
2426 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2427 } while (0)
2428
2429 /* This is how to output a label which precedes a jumptable. Since
2430 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2431 #undef ASM_OUTPUT_CASE_LABEL
2432 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2433 do \
2434 { \
2435 if (TARGET_THUMB) \
2436 ASM_OUTPUT_ALIGN (FILE, 2); \
2437 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2438 } \
2439 while (0)
2440
2441 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2442 do \
2443 { \
2444 if (TARGET_THUMB) \
2445 { \
2446 if (is_called_in_ARM_mode (DECL) \
2447 || current_function_is_thunk) \
2448 fprintf (STREAM, "\t.code 32\n") ; \
2449 else \
2450 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2451 } \
2452 if (TARGET_POKE_FUNCTION_NAME) \
2453 arm_poke_function_name (STREAM, (char *) NAME); \
2454 } \
2455 while (0)
2456
2457 /* For aliases of functions we use .thumb_set instead. */
2458 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2459 do \
2460 { \
2461 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2462 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2463 \
2464 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2465 { \
2466 fprintf (FILE, "\t.thumb_set "); \
2467 assemble_name (FILE, LABEL1); \
2468 fprintf (FILE, ","); \
2469 assemble_name (FILE, LABEL2); \
2470 fprintf (FILE, "\n"); \
2471 } \
2472 else \
2473 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2474 } \
2475 while (0)
2476
2477 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2478 /* To support -falign-* switches we need to use .p2align so
2479 that alignment directives in code sections will be padded
2480 with no-op instructions, rather than zeroes. */
2481 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2482 if ((LOG) != 0) \
2483 { \
2484 if ((MAX_SKIP) == 0) \
2485 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2486 else \
2487 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2488 (int) (LOG), (int) (MAX_SKIP)); \
2489 }
2490 #endif
2491 \f
2492 /* Only perform branch elimination (by making instructions conditional) if
2493 we're optimizing. Otherwise it's of no use anyway. */
2494 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2495 if (TARGET_ARM && optimize) \
2496 arm_final_prescan_insn (INSN); \
2497 else if (TARGET_THUMB) \
2498 thumb_final_prescan_insn (INSN)
2499
2500 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2501 (CODE == '@' || CODE == '|' \
2502 || (TARGET_ARM && (CODE == '?')) \
2503 || (TARGET_THUMB && (CODE == '_')))
2504
2505 /* Output an operand of an instruction. */
2506 #define PRINT_OPERAND(STREAM, X, CODE) \
2507 arm_print_operand (STREAM, X, CODE)
2508
2509 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2510 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2511 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2512 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2513 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2514 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2515 : 0))))
2516
2517 /* Output the address of an operand. */
2518 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2519 { \
2520 int is_minus = GET_CODE (X) == MINUS; \
2521 \
2522 if (GET_CODE (X) == REG) \
2523 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2524 else if (GET_CODE (X) == PLUS || is_minus) \
2525 { \
2526 rtx base = XEXP (X, 0); \
2527 rtx index = XEXP (X, 1); \
2528 HOST_WIDE_INT offset = 0; \
2529 if (GET_CODE (base) != REG) \
2530 { \
2531 /* Ensure that BASE is a register. */ \
2532 /* (one of them must be). */ \
2533 rtx temp = base; \
2534 base = index; \
2535 index = temp; \
2536 } \
2537 switch (GET_CODE (index)) \
2538 { \
2539 case CONST_INT: \
2540 offset = INTVAL (index); \
2541 if (is_minus) \
2542 offset = -offset; \
2543 asm_fprintf (STREAM, "[%r, #%wd]", \
2544 REGNO (base), offset); \
2545 break; \
2546 \
2547 case REG: \
2548 asm_fprintf (STREAM, "[%r, %s%r]", \
2549 REGNO (base), is_minus ? "-" : "", \
2550 REGNO (index)); \
2551 break; \
2552 \
2553 case MULT: \
2554 case ASHIFTRT: \
2555 case LSHIFTRT: \
2556 case ASHIFT: \
2557 case ROTATERT: \
2558 { \
2559 asm_fprintf (STREAM, "[%r, %s%r", \
2560 REGNO (base), is_minus ? "-" : "", \
2561 REGNO (XEXP (index, 0))); \
2562 arm_print_operand (STREAM, index, 'S'); \
2563 fputs ("]", STREAM); \
2564 break; \
2565 } \
2566 \
2567 default: \
2568 abort(); \
2569 } \
2570 } \
2571 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2572 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2573 { \
2574 extern enum machine_mode output_memory_reference_mode; \
2575 \
2576 if (GET_CODE (XEXP (X, 0)) != REG) \
2577 abort (); \
2578 \
2579 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2580 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2581 REGNO (XEXP (X, 0)), \
2582 GET_CODE (X) == PRE_DEC ? "-" : "", \
2583 GET_MODE_SIZE (output_memory_reference_mode)); \
2584 else \
2585 asm_fprintf (STREAM, "[%r], #%s%d", \
2586 REGNO (XEXP (X, 0)), \
2587 GET_CODE (X) == POST_DEC ? "-" : "", \
2588 GET_MODE_SIZE (output_memory_reference_mode)); \
2589 } \
2590 else if (GET_CODE (X) == PRE_MODIFY) \
2591 { \
2592 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2593 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2594 asm_fprintf (STREAM, "#%wd]!", \
2595 INTVAL (XEXP (XEXP (X, 1), 1))); \
2596 else \
2597 asm_fprintf (STREAM, "%r]!", \
2598 REGNO (XEXP (XEXP (X, 1), 1))); \
2599 } \
2600 else if (GET_CODE (X) == POST_MODIFY) \
2601 { \
2602 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2603 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2604 asm_fprintf (STREAM, "#%wd", \
2605 INTVAL (XEXP (XEXP (X, 1), 1))); \
2606 else \
2607 asm_fprintf (STREAM, "%r", \
2608 REGNO (XEXP (XEXP (X, 1), 1))); \
2609 } \
2610 else output_addr_const (STREAM, X); \
2611 }
2612
2613 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2614 { \
2615 if (GET_CODE (X) == REG) \
2616 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2617 else if (GET_CODE (X) == POST_INC) \
2618 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2619 else if (GET_CODE (X) == PLUS) \
2620 { \
2621 if (GET_CODE (XEXP (X, 0)) != REG) \
2622 abort (); \
2623 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2624 asm_fprintf (STREAM, "[%r, #%wd]", \
2625 REGNO (XEXP (X, 0)), \
2626 INTVAL (XEXP (X, 1))); \
2627 else \
2628 asm_fprintf (STREAM, "[%r, %r]", \
2629 REGNO (XEXP (X, 0)), \
2630 REGNO (XEXP (X, 1))); \
2631 } \
2632 else \
2633 output_addr_const (STREAM, X); \
2634 }
2635
2636 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2637 if (TARGET_ARM) \
2638 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2639 else \
2640 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2641
2642 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2643 if (GET_CODE (X) != CONST_VECTOR \
2644 || ! arm_emit_vector_const (FILE, X)) \
2645 goto FAIL;
2646
2647 /* A C expression whose value is RTL representing the value of the return
2648 address for the frame COUNT steps up from the current frame. */
2649
2650 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2651 arm_return_addr (COUNT, FRAME)
2652
2653 /* Mask of the bits in the PC that contain the real return address
2654 when running in 26-bit mode. */
2655 #define RETURN_ADDR_MASK26 (0x03fffffc)
2656
2657 /* Pick up the return address upon entry to a procedure. Used for
2658 dwarf2 unwind information. This also enables the table driven
2659 mechanism. */
2660 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2661 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2662
2663 /* Used to mask out junk bits from the return address, such as
2664 processor state, interrupt status, condition codes and the like. */
2665 #define MASK_RETURN_ADDR \
2666 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2667 in 26 bit mode, the condition codes must be masked out of the \
2668 return address. This does not apply to ARM6 and later processors \
2669 when running in 32 bit mode. */ \
2670 ((arm_arch4 || TARGET_THUMB) \
2671 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2672 : arm_gen_return_addr_mask ())
2673
2674 \f
2675 enum arm_builtins
2676 {
2677 ARM_BUILTIN_GETWCX,
2678 ARM_BUILTIN_SETWCX,
2679
2680 ARM_BUILTIN_WZERO,
2681
2682 ARM_BUILTIN_WAVG2BR,
2683 ARM_BUILTIN_WAVG2HR,
2684 ARM_BUILTIN_WAVG2B,
2685 ARM_BUILTIN_WAVG2H,
2686
2687 ARM_BUILTIN_WACCB,
2688 ARM_BUILTIN_WACCH,
2689 ARM_BUILTIN_WACCW,
2690
2691 ARM_BUILTIN_WMACS,
2692 ARM_BUILTIN_WMACSZ,
2693 ARM_BUILTIN_WMACU,
2694 ARM_BUILTIN_WMACUZ,
2695
2696 ARM_BUILTIN_WSADB,
2697 ARM_BUILTIN_WSADBZ,
2698 ARM_BUILTIN_WSADH,
2699 ARM_BUILTIN_WSADHZ,
2700
2701 ARM_BUILTIN_WALIGN,
2702
2703 ARM_BUILTIN_TMIA,
2704 ARM_BUILTIN_TMIAPH,
2705 ARM_BUILTIN_TMIABB,
2706 ARM_BUILTIN_TMIABT,
2707 ARM_BUILTIN_TMIATB,
2708 ARM_BUILTIN_TMIATT,
2709
2710 ARM_BUILTIN_TMOVMSKB,
2711 ARM_BUILTIN_TMOVMSKH,
2712 ARM_BUILTIN_TMOVMSKW,
2713
2714 ARM_BUILTIN_TBCSTB,
2715 ARM_BUILTIN_TBCSTH,
2716 ARM_BUILTIN_TBCSTW,
2717
2718 ARM_BUILTIN_WMADDS,
2719 ARM_BUILTIN_WMADDU,
2720
2721 ARM_BUILTIN_WPACKHSS,
2722 ARM_BUILTIN_WPACKWSS,
2723 ARM_BUILTIN_WPACKDSS,
2724 ARM_BUILTIN_WPACKHUS,
2725 ARM_BUILTIN_WPACKWUS,
2726 ARM_BUILTIN_WPACKDUS,
2727
2728 ARM_BUILTIN_WADDB,
2729 ARM_BUILTIN_WADDH,
2730 ARM_BUILTIN_WADDW,
2731 ARM_BUILTIN_WADDSSB,
2732 ARM_BUILTIN_WADDSSH,
2733 ARM_BUILTIN_WADDSSW,
2734 ARM_BUILTIN_WADDUSB,
2735 ARM_BUILTIN_WADDUSH,
2736 ARM_BUILTIN_WADDUSW,
2737 ARM_BUILTIN_WSUBB,
2738 ARM_BUILTIN_WSUBH,
2739 ARM_BUILTIN_WSUBW,
2740 ARM_BUILTIN_WSUBSSB,
2741 ARM_BUILTIN_WSUBSSH,
2742 ARM_BUILTIN_WSUBSSW,
2743 ARM_BUILTIN_WSUBUSB,
2744 ARM_BUILTIN_WSUBUSH,
2745 ARM_BUILTIN_WSUBUSW,
2746
2747 ARM_BUILTIN_WAND,
2748 ARM_BUILTIN_WANDN,
2749 ARM_BUILTIN_WOR,
2750 ARM_BUILTIN_WXOR,
2751
2752 ARM_BUILTIN_WCMPEQB,
2753 ARM_BUILTIN_WCMPEQH,
2754 ARM_BUILTIN_WCMPEQW,
2755 ARM_BUILTIN_WCMPGTUB,
2756 ARM_BUILTIN_WCMPGTUH,
2757 ARM_BUILTIN_WCMPGTUW,
2758 ARM_BUILTIN_WCMPGTSB,
2759 ARM_BUILTIN_WCMPGTSH,
2760 ARM_BUILTIN_WCMPGTSW,
2761
2762 ARM_BUILTIN_TEXTRMSB,
2763 ARM_BUILTIN_TEXTRMSH,
2764 ARM_BUILTIN_TEXTRMSW,
2765 ARM_BUILTIN_TEXTRMUB,
2766 ARM_BUILTIN_TEXTRMUH,
2767 ARM_BUILTIN_TEXTRMUW,
2768 ARM_BUILTIN_TINSRB,
2769 ARM_BUILTIN_TINSRH,
2770 ARM_BUILTIN_TINSRW,
2771
2772 ARM_BUILTIN_WMAXSW,
2773 ARM_BUILTIN_WMAXSH,
2774 ARM_BUILTIN_WMAXSB,
2775 ARM_BUILTIN_WMAXUW,
2776 ARM_BUILTIN_WMAXUH,
2777 ARM_BUILTIN_WMAXUB,
2778 ARM_BUILTIN_WMINSW,
2779 ARM_BUILTIN_WMINSH,
2780 ARM_BUILTIN_WMINSB,
2781 ARM_BUILTIN_WMINUW,
2782 ARM_BUILTIN_WMINUH,
2783 ARM_BUILTIN_WMINUB,
2784
2785 ARM_BUILTIN_WMULUM,
2786 ARM_BUILTIN_WMULSM,
2787 ARM_BUILTIN_WMULUL,
2788
2789 ARM_BUILTIN_PSADBH,
2790 ARM_BUILTIN_WSHUFH,
2791
2792 ARM_BUILTIN_WSLLH,
2793 ARM_BUILTIN_WSLLW,
2794 ARM_BUILTIN_WSLLD,
2795 ARM_BUILTIN_WSRAH,
2796 ARM_BUILTIN_WSRAW,
2797 ARM_BUILTIN_WSRAD,
2798 ARM_BUILTIN_WSRLH,
2799 ARM_BUILTIN_WSRLW,
2800 ARM_BUILTIN_WSRLD,
2801 ARM_BUILTIN_WRORH,
2802 ARM_BUILTIN_WRORW,
2803 ARM_BUILTIN_WRORD,
2804 ARM_BUILTIN_WSLLHI,
2805 ARM_BUILTIN_WSLLWI,
2806 ARM_BUILTIN_WSLLDI,
2807 ARM_BUILTIN_WSRAHI,
2808 ARM_BUILTIN_WSRAWI,
2809 ARM_BUILTIN_WSRADI,
2810 ARM_BUILTIN_WSRLHI,
2811 ARM_BUILTIN_WSRLWI,
2812 ARM_BUILTIN_WSRLDI,
2813 ARM_BUILTIN_WRORHI,
2814 ARM_BUILTIN_WRORWI,
2815 ARM_BUILTIN_WRORDI,
2816
2817 ARM_BUILTIN_WUNPCKIHB,
2818 ARM_BUILTIN_WUNPCKIHH,
2819 ARM_BUILTIN_WUNPCKIHW,
2820 ARM_BUILTIN_WUNPCKILB,
2821 ARM_BUILTIN_WUNPCKILH,
2822 ARM_BUILTIN_WUNPCKILW,
2823
2824 ARM_BUILTIN_WUNPCKEHSB,
2825 ARM_BUILTIN_WUNPCKEHSH,
2826 ARM_BUILTIN_WUNPCKEHSW,
2827 ARM_BUILTIN_WUNPCKEHUB,
2828 ARM_BUILTIN_WUNPCKEHUH,
2829 ARM_BUILTIN_WUNPCKEHUW,
2830 ARM_BUILTIN_WUNPCKELSB,
2831 ARM_BUILTIN_WUNPCKELSH,
2832 ARM_BUILTIN_WUNPCKELSW,
2833 ARM_BUILTIN_WUNPCKELUB,
2834 ARM_BUILTIN_WUNPCKELUH,
2835 ARM_BUILTIN_WUNPCKELUW,
2836
2837 ARM_BUILTIN_MAX
2838 };
2839 #endif /* ! GCC_ARM_H */
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