| blob | bf57c846db942b77b0abb9741f5ecdda6946fa8c |
1 2024-03-21 Andrew Stubbs <ams@baylibre.com>
3 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
5 2024-03-21 Andrew Stubbs <ams@baylibre.com>
7 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
9 2024-03-21 Andrew Stubbs <ams@baylibre.com>
11 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
12 device_malloc call.
14 2024-03-21 liuhongt <hongtao.liu@intel.com>
16 PR tree-optimization/114396
17 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
18 and true to wi::from_mpz.
20 2024-03-21 Richard Biener <rguenther@suse.de>
22 PR tree-optimization/111736
23 * asan.cc (instrument_derefs): Do not instrument accesses
24 to non-generic address-spaces.
26 2024-03-21 Richard Biener <rguenther@suse.de>
28 PR tree-optimization/113727
29 * tree-sra.cc (analyze_access_subtree): Do not allow
30 replacements in subtrees when grp_partial_lhs.
32 2024-03-21 liuhongt <hongtao.liu@intel.com>
34 PR middle-end/114347
35 * doc/invoke.texi: Document -fexcess-precision=16.
37 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
39 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
40 field contains a DECL_NAME.
42 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
44 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
45 Add assert to validate the string is set.
46 * config/bpf/core-builtins.cc (cr_final): Make string struct
47 field as const.
48 (process_enum_value): Correct for field type change.
49 (process_type): Set access string to "0".
51 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
53 * config/bpf/core-builtins.cc (core_field_info): Add
54 support for POINTER_PLUS_EXPR in the root of the field expression.
55 (bpf_core_get_index): Likewise.
56 (pack_field_expr): Make the BTF type to point to the structure
57 related node, instead of its pointer type.
58 (make_core_safe_access_index): Correct to new code.
60 2024-03-20 Xi Ruoyao <xry111@xry111.site>
62 PR target/114407
63 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
64 Fix typo in diagnostic message, enabing -> enabling.
66 2024-03-20 Jakub Jelinek <jakub@redhat.com>
68 PR target/114175
69 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
70 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
71 if arg.type is NULL.
73 2024-03-20 Jakub Jelinek <jakub@redhat.com>
75 PR target/114175
76 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
77 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
78 if arg.type is NULL.
80 2024-03-20 Jakub Jelinek <jakub@redhat.com>
82 PR target/114175
83 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
84 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
85 if arg.type is NULL.
87 2024-03-20 Jakub Jelinek <jakub@redhat.com>
89 PR target/114175
90 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
91 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
92 if arg.type is NULL.
94 2024-03-20 Jakub Jelinek <jakub@redhat.com>
96 PR target/114175
97 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
98 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
99 if arg.type is NULL.
101 2024-03-20 Jakub Jelinek <jakub@redhat.com>
103 PR target/114175
104 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
105 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
106 if arg.type is NULL.
108 2024-03-20 Jakub Jelinek <jakub@redhat.com>
110 PR target/114175
111 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
112 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
113 if arg.type is NULL.
115 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
117 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
119 2024-03-20 Jakub Jelinek <jakub@redhat.com>
121 PR tree-optimization/114365
122 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
123 a PHI node, set iv2 to its result afterwards.
125 2024-03-20 Jakub Jelinek <jakub@redhat.com>
127 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
128 probabbility -> probability.
129 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
131 2024-03-20 Jakub Jelinek <jakub@redhat.com>
133 PR bootstrap/114369
134 * system.h (vec_step): Define to vec_step_ when compiling
135 with clang on PowerPC.
137 2024-03-20 demin.han <demin.han@starfivetech.com>
139 PR target/112651
140 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
141 (enum rvv_max_lmul_enum): Ditto
142 (TARGET_MAX_LMUL): Ditto
143 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
144 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
145 (costs::better_main_loop_than_p): Ditto
146 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
148 2024-03-20 Richard Biener <rguenther@suse.de>
150 PR middle-end/113396
151 * tree-dfa.cc (get_ref_base_and_extent): Use index range
152 bounds only if they fit within the address-range constraints
153 of offset_int.
155 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
157 * config/loongarch/loongarch.cc
158 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
159 UNITS_PER_FPREG macros.
160 (loongarch_hard_regno_nregs): Ditto.
161 (loongarch_class_max_nregs): Ditto.
162 (loongarch_get_separate_components): Ditto.
163 (loongarch_process_components): Ditto.
164 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
165 (UNITS_PER_HWFPVALUE): Ditto.
166 (UNITS_PER_FPVALUE): Ditto.
168 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
170 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
171 of loongarch_expand_vec_cmp()'s return value.
172 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
173 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
174 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
175 * config/loongarch/loongarch-protos.h
176 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
177 type from bool to void.
178 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
180 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
182 * config/loongarch/loongarch-protos.h
183 (loongarch_cfun_has_cprestore_slot_p): Delete.
184 (loongarch_adjust_insn_length): Delete.
185 (current_section_name): Delete.
186 (loongarch_split_symbol_type): Delete.
187 * config/loongarch/loongarch.cc
188 (loongarch_case_values_threshold): Delete.
189 (loongarch_spill_class): Delete.
190 (TARGET_OPTAB_SUPPORTED_P): Delete.
191 (TARGET_CASE_VALUES_THRESHOLD): Delete.
192 (TARGET_SPILL_CLASS): Delete.
194 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
196 PR c++/111918
197 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
198 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
199 Make use of DK_ANY to indicate a diagnostic was initially enabled.
200 (diagnostic_context::diagnostic_enabled): Do not change the type of
201 a diagnostic if the saved classification is type DK_ANY.
203 2024-03-19 Martin Jambor <mjambor@suse.cz>
205 PR ipa/108802
206 PR ipa/114254
207 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
208 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
209 a pointer parameter.
210 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
211 parameter, also recognize the case when pfn pointer is loaded in its
212 own BB.
214 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
216 PR target/99829
217 * lra-constraints.cc (lra_constraints): Prevent removing insn
218 with reverse equivalence to memory if the memory was reloaded.
220 2024-03-19 David Malcolm <dmalcolm@redhat.com>
222 PR middle-end/114348
223 * diagnostic-format-json.cc
224 (json_stderr_output_format::machine_readable_stderr_p): New.
225 (json_file_output_format::machine_readable_stderr_p): New.
226 * diagnostic-format-sarif.cc
227 (sarif_stream_output_format::machine_readable_stderr_p): New.
228 (sarif_file_output_format::machine_readable_stderr_p): New.
229 * diagnostic.cc (diagnostic_context::action_after_output): Move
230 "fnotice" to before "finish" call, so that we still have the
231 diagnostic_context.
232 (fnotice): Bail out if the user requested one of the
233 machine-readable diagnostic output formats on stderr.
234 * diagnostic.h
235 (diagnostic_output_format::machine_readable_stderr_p): New pure
236 virtual function.
237 (diagnostic_text_output_format::machine_readable_stderr_p): New.
238 (diagnostic_context::get_output_format): New accessor.
240 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
242 PR target/114175
243 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
244 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
245 if arg.type is NULL
247 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
249 * doc/install.texi (Prerequisites): Document use of autogen for
250 libstdc++.
252 2024-03-19 Richard Biener <rguenther@suse.de>
254 PR tree-optimization/114151
255 PR tree-optimization/114269
256 PR tree-optimization/114322
257 PR tree-optimization/114074
258 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
259 unsigned arithmetic when actual overflow on constant operands
260 is observed.
262 2024-03-19 Jakub Jelinek <jakub@redhat.com>
264 PR target/114175
265 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
266 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
267 if arg.type is NULL.
269 2024-03-19 Xi Ruoyao <xry111@xry111.site>
271 PR target/114175
272 * config/loongarch/loongarch.cc
273 (loongarch_setup_incoming_varargs): Only skip
274 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
275 functions if arg.type is NULL.
277 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
279 PR target/114323
280 * config/arm/arm-mve-builtins.cc
281 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
282 into account.
284 2024-03-19 Jakub Jelinek <jakub@redhat.com>
286 PR target/114175
287 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
288 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
289 if arg.type is NULL.
291 2024-03-19 Jakub Jelinek <jakub@redhat.com>
293 PR target/114175
294 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
295 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
296 if arg.type is NULL.
298 2024-03-19 Richard Biener <rguenther@suse.de>
300 PR tree-optimization/114375
301 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
302 load permutation for masked loads but reject it when any
303 such is necessary.
304 * tree-vect-stmts.cc (vectorizable_load): Reject masked
305 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
306 supported.
308 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
310 * common/config/riscv/riscv-common.cc: Create XCVbi extension
311 support.
312 * config/riscv/riscv.opt: Likewise.
313 * config/riscv/corev.md: Implement cv_branch<mode> pattern
314 for cv.beqimm and cv.bneimm.
315 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
316 branch instruction pattern.
317 * config/riscv/constraints.md: Implement constraints
318 cv_bi_s5 - signed 5-bit immediate.
319 * config/riscv/predicates.md: Implement predicate
320 const_int5s_operand - signed 5 bit immediate.
321 * doc/sourcebuild.texi: Add XCVbi documentation.
323 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
325 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
326 (RISCV_CORE): Ditto.
327 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
328 option.
329 * config/riscv/riscv.cc: New def.
330 * config/riscv/riscv.md: New include.
331 * config/riscv/xiangshan.md: New file.
333 2024-03-18 David Malcolm <dmalcolm@redhat.com>
335 PR analyzer/110902
336 PR analyzer/110928
337 PR analyzer/111305
338 PR analyzer/111441
339 * selftest.h (ASSERT_NE_AT): New macro.
341 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
343 PR target/111822
344 * config/i386/i386-features.cc (smode_convert_cst): New function
345 to handle SImode, DImode and TImode immediates, generalized from
346 timode_convert_cst.
347 (timode_convert_cst): Remove.
348 (scalar_chain::convert_op): Unify from
349 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
350 (general_scalar_chain::convert_op): Remove.
351 (timode_scalar_chain::convert_op): Remove.
352 (timode_scalar_chain::convert_insn): Update the call to
353 renamed timode_convert_cst.
354 * config/i386/i386-features.h (class scalar_chain):
355 Redeclare convert_op as protected class member.
356 (class general_calar_chain): Remove convert_op.
357 (class timode_scalar_chain): Ditto.
359 2024-03-18 Jan Hubicka <jh@suse.cz>
361 * config/i386/zn4zn5.md: Add file missed in the previous commit.
363 2024-03-18 Jan Hubicka <jh@suse.cz>
364 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
366 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
367 * common/config/i386/i386-common.cc (processor_names): Add znver5.
368 (processor_alias_table): Likewise.
369 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
370 family.
371 (processor_subtypes): Add znver5.
372 * config.gcc (x86_64-*-* |...): Likewise.
373 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
374 march=native detect znver5 cpu's.
375 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
376 znver5.
377 * config/i386/i386-options.cc (m_ZNVER5): New definition
378 (processor_cost_table): Add znver5.
379 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
380 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
381 (PTA_ZNVER5): New definition.
382 * config/i386/i386.md (define_attr "cpu"): Add znver5.
383 (Scheduling descriptions) Add znver5.md.
384 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
385 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
386 (ix86_adjust_cost): Likewise.
387 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
388 (avx512_store_by_pieces): Add m_ZNVER5.
389 * doc/extend.texi: Add znver5.
390 * doc/invoke.texi: Likewise.
391 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
393 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
395 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
396 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
397 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
398 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
399 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
400 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
402 2024-03-18 liuhongt <hongtao.liu@intel.com>
404 PR target/114334
405 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
406 (MODEF248): New mode iterator.
407 (ssevecmodesuffix): Hanlde BF and HF.
408 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
409 (<code><mode>3): Ditto.
411 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
413 PR rtl-optimization/112415
414 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
415 for symbolic memory operands.
416 (pa_legitimate_address_p): Revise LO_SUM condition.
417 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
418 comment about GNU linker to predicates.md.
419 * config/pa/predicates.md (floating_point_store_memory_operand):
420 Revise condition for symbolic memory operands. Update
421 comment.
423 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
425 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
427 2024-03-16 Jakub Jelinek <jakub@redhat.com>
429 PR target/114175
430 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
431 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
432 if arg.type is NULL.
434 2024-03-16 Jakub Jelinek <jakub@redhat.com>
436 PR tree-optimization/114329
437 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
438 build_bit_field_ref method.
439 (bitint_large_huge::build_bit_field_ref): New method.
440 (bitint_large_huge::lower_mergeable_stmt): Use it.
442 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
444 * config/riscv/riscv.opt.urls: Regenerated.
445 * config/rs6000/sysv4.opt.urls: Likewise.
446 * config/xtensa/xtensa.opt.urls: Likewise.
448 2024-03-15 Jakub Jelinek <jakub@redhat.com>
450 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
451 betwee -> between.
452 * edit-context.cc (class line_event): Fix comment typo,
453 betweeen -> between.
455 2024-03-15 Jakub Jelinek <jakub@redhat.com>
457 PR target/114339
458 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
459 a pasto, compare code against LE rather than GE.
461 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
463 * match.pd: Fix truncation pattern for -fno-signed-zeroes
465 2024-03-15 Jakub Jelinek <jakub@redhat.com>
467 PR middle-end/114332
468 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
470 2024-03-15 Jakub Jelinek <jakub@redhat.com>
472 PR tree-optimization/113466
473 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
474 member.
475 (bitint_large_huge::bitint_large_huge): Initialize it.
476 (bitint_large_huge::~bitint_large_huge): Release it.
477 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
478 before which at least one statement has been inserted.
479 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
480 calls to a different block and add corresponding PHIs.
482 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
484 * config/mips/mips.opt: Support -mstrict-align, and use
485 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
486 as alias.
487 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
488 * config/mips/mips.opt.urls: Regenerate.
489 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
491 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
493 PR middle-end/114108
494 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
495 vect_convert_output with the correct vecitype.
497 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
499 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
500 Remove masking of operand 3.
502 2024-03-14 Jason Merrill <jason@redhat.com>
504 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
505 comments.
507 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
509 PR target/114288
510 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
511 14-bit displacements before reload for modes that may use
512 a floating-point load or store.
514 2024-03-14 David Faust <david.faust@oracle.com>
516 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
518 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
520 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
521 patterns ahead of the l32i.n and s32i.n.
523 2024-03-14 Jakub Jelinek <jakub@redhat.com>
525 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
527 2024-03-14 Jakub Jelinek <jakub@redhat.com>
529 PR middle-end/113907
530 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
531 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
532 functions.
534 2024-03-14 Xi Ruoyao <xry111@xry111.site>
536 * config/loongarch/loongarch.md (any_ge): Remove.
537 (sge<u>_<X:mode><GPR:mode>): Remove.
539 2024-03-14 Jakub Jelinek <jakub@redhat.com>
541 PR target/114310
542 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
543 TImode force newval into a register.
545 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
547 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
548 (OMP_CLAUSE__CACHE__READONLY): New macro.
549 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
550 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
551 OMP_CLAUSE__CACHE__READONLY.
552 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
553 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
555 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
557 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
558 for misaligned symbols.
559 * config/s390/s390.opt: Improve documentation.
561 2024-03-14 Jakub Jelinek <jakub@redhat.com>
563 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
564 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
565 are computed, recompute immediate dominator of other_edge->src
566 and other_edge->dest.
567 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
568 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
569 with update it for bb splitting.
571 2024-03-14 liuhongt <hongtao.liu@intel.com>
573 * config/i386/i386-features.cc
574 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
575 (convert_scalars_to_vector): Ditto.
576 * config/i386/i386-features.h (class scalar_chain): New
577 memeber control_flow_insns.
579 2024-03-13 Jakub Jelinek <jakub@redhat.com>
581 PR middle-end/114319
582 * gimple-ssa-store-merging.cc
583 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
584 allow matching __builtin_bswap64 if there is bswapsi2 optab.
586 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
588 * config/s390/s390.cc (s390_secondary_reload): Guard
589 SYMBOL_FLAG_NOTALIGN2_P.
591 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
593 * config/s390/s390-builtin-types.def: Update to reflect latest
594 changes.
595 * config/s390/s390-builtins.def: Streamline vector builtins with
596 LLVM.
598 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
600 * config/s390/s390-builtins.def (vec_permi): Deprecate.
601 (vec_ctd): Deprecate.
602 (vec_ctd_s64): Deprecate.
603 (vec_ctd_u64): Deprecate.
604 (vec_ctsl): Deprecate.
605 (vec_ctul): Deprecate.
606 (vec_ld2f): Deprecate.
607 (vec_st2f): Deprecate.
608 (vec_insert): Deprecate overloads with bool vectors.
610 2024-03-13 Jakub Jelinek <jakub@redhat.com>
612 PR middle-end/114313
613 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
614 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
615 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
616 rhs_type to limb_access for the bitfield load cases.
617 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
618 lhs_type to limb_access if nlhs is non-NULL.
620 2024-03-13 Jakub Jelinek <jakub@redhat.com>
622 PR sanitizer/112709
623 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
624 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
625 gsi_safe_insert_before instead of gsi_insert_before.
627 2024-03-13 Jakub Jelinek <jakub@redhat.com>
629 PR sanitizer/112709
630 * gimple-iterator.h (gsi_safe_insert_before,
631 gsi_safe_insert_seq_before): Declare.
632 * gimple-iterator.cc: Include gimplify.h.
633 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
634 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
635 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
636 instrument_nonnull_arg, instrument_nonnull_return): Use
637 gsi_safe_insert_before instead of gsi_insert_before.
638 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
639 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
640 instead of force_gimple_operand_gsi.
641 (instrument_object_size): Likewise. Use gsi_safe_insert_before
642 instead of gsi_insert_before.
644 2024-03-12 Richard Biener <rguenther@suse.de>
646 PR tree-optimization/114121
647 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
648 converted operand properly.
649 (chrec_fold_multiply): Likewise. Handle missed recursion.
651 2024-03-12 Jakub Jelinek <jakub@redhat.com>
653 PR sanitizer/112709
654 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
655 stores on the caller side unless it is a call to a builtin or
656 internal function or function doesn't return by hidden reference.
657 (maybe_instrument_call): Likewise.
658 (instrument_derefs): Instrument stores to RESULT_DECL if
659 returning by hidden reference.
661 2024-03-12 Jakub Jelinek <jakub@redhat.com>
663 PR tree-optimization/114293
664 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
665 max is smaller than min, set max to ~(size_t)0.
667 2024-03-12 Pan Li <pan2.li@intel.com>
669 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
670 code style greater than 80 chars.
671 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
672 with 3 space(s) and argument unalignment.
674 2024-03-12 Richard Biener <rguenther@suse.de>
676 PR tree-optimization/114297
677 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
678 live stmts SLP node to vect_create_epilog_for_reduction.
680 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
682 PR driver/114314
683 * common.opt (fmultiflags): Add RejectNegative.
685 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
687 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
688 * config/aarch64/aarch64.opt: Likewise.
689 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
690 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
691 (aarch64_expand_epilogue): Likewise.
692 (aarch64_post_cfi_startproc): Likewise.
693 (aarch64_handle_no_branch_protection): Copy and rename.
694 (aarch64_handle_standard_branch_protection): Likewise.
695 (aarch64_handle_pac_ret_protection): Likewise.
696 (aarch64_handle_pac_ret_leaf): Likewise.
697 (aarch64_handle_pac_ret_b_key): Likewise.
698 (aarch64_handle_bti_protection): Likewise.
699 (aarch64_override_options): Update branch protection validation.
700 (aarch64_handle_attr_branch_protection): Likewise.
701 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
702 Pass branch protection type description as argument.
703 (struct aarch_branch_protect_type): Move from aarch-common.h.
704 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
705 Remove.
706 (aarch_handle_standard_branch_protection): Remove.
707 (aarch_handle_pac_ret_protection): Remove.
708 (aarch_handle_pac_ret_leaf): Remove.
709 (aarch_handle_pac_ret_b_key): Remove.
710 (aarch_handle_bti_protection): Remove.
711 (aarch_validate_mbranch_protection): Pass branch protection type
712 description as argument.
713 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
714 (struct aarch_branch_protect_type): Remove.
715 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
716 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
717 (arm_handle_standard_branch_protection): Likewise.
718 (arm_handle_pac_ret_protection): Likewise.
719 (arm_handle_pac_ret_leaf): Likewise.
720 (arm_handle_bti_protection): Likewise.
721 (arm_configure_build_target): Update branch protection validation.
722 * config/arm/arm.opt: Remove aarch_ra_sign_key.
724 2024-03-11 Richard Biener <rguenther@suse.de>
726 PR middle-end/114299
727 * gimplify.cc (internal_get_tmp_var): When gimplification
728 of VAL failed, return a decl.
730 2024-03-11 Jakub Jelinek <jakub@redhat.com>
732 PR tree-optimization/114278
733 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
734 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
736 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
738 PR debug/113519
739 PR debug/113777
740 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
741 generate the DIE with the same parent as in the regular case.
743 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
745 PR middle-end/95351
746 * fold-const.cc (merge_truthop_with_opposite_arm): Use
747 the type of the operands of the comparison and not the type
748 of the comparison.
750 2024-03-10 jlaw <jeffreyalaw@gmail.com>
752 PR tree-optimization/110199
753 * tree-ssa-scopedtables.cc
754 (avail_exprs_stack::simplify_binary_operation): Generalize handling
755 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
756 comparison operands for other cases.
758 2024-03-10 Pan Li <pan2.li@intel.com>
760 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
761 during transform process.
762 (vectorizable_load): Ditto.
764 2024-03-10 jlaw <jeffreyalaw@gmail.com>
766 PR target/102250
767 * doc/install.texi: Document need for python when building
768 RISC-V compilers.
770 2024-03-10 jlaw <jeffreyalaw@gmail.com>
772 PR target/111362
773 * mode-switching.cc (optimize_mode_switching): Only process
774 NONDEBUG insns.
776 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
778 * config/avr/avr.md: Fix typos in comment, indentation glitches
779 and some other nits.
781 2024-03-09 Jakub Jelinek <jakub@redhat.com>
783 PR target/114284
784 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
785 src containing MEMs unless prop.likely_profitable_p ().
787 2024-03-09 Xi Ruoyao <xry111@xry111.site>
789 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
790 Support 'Q' for R_LARCH_RELAX for TLS IE.
791 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
792 IE.
793 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
795 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
797 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
798 usum_widenqihi and add_zero_extend1.
799 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
800 sub+sign_extend.
801 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
802 Compute exact insn lengths.
803 (*usum_widenqihi3): Allow input operands to commute.
805 2024-03-09 Jakub Jelinek <jakub@redhat.com>
807 * config/i386/i386.opt.urls: Regenerate.
809 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
811 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
812 In loongarch64, a sign extension operation is added when
813 operands[2] is a register operand and the mode is SImode.
815 2024-03-08 Martin Jambor <mjambor@suse.cz>
817 PR ipa/113757
818 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
819 id->killed_new_ssa_names.
821 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
823 PR target/113790
824 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
825 for non-reload pseudo too.
827 2024-03-08 David Faust <david.faust@oracle.com>
829 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
830 not attempt inline expansion if size is above threshold.
831 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
832 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
833 Document.
835 2024-03-08 Richard Biener <rguenther@suse.de>
837 PR tree-optimization/114269
838 PR tree-optimization/114074
839 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
840 in the third CASE_CONVERT case as well.
841 (chrec_fold_multiply): Handle sign-conversions from unsigned
842 by performing the operation in the unsigned type.
844 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
846 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
847 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
849 2024-03-08 Jakub Jelinek <jakub@redhat.com>
851 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
852 asm_noperands < 0 means it is not asm goto too.
854 2024-03-08 Jakub Jelinek <jakub@redhat.com>
856 PR target/38534
857 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
858 option.
859 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
860 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
861 ix86_noreturn_no_callee_saved_registers is enabled.
862 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
864 2024-03-08 Jakub Jelinek <jakub@redhat.com>
866 PR debug/113918
867 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
868 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
870 2024-03-08 demin.han <demin.han@starfivetech.com>
872 PR target/114264
873 * config/riscv/riscv-vector-costs.cc: Fix ICE
875 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
877 * fwprop.cc (forward_propagate_into): Return false for volatile set
878 source rtx.
880 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
882 PR target/113618
883 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
884 (aarch64_expand_cpymem): Emit single load/store only.
885 (aarch64_set_one_block): Emit single stores only.
887 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
889 PR middle-end/114196
890 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
891 vectorization guards.
893 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
895 * doc/cppopts.texi: Remove incorrect claim about -dD not
896 outputting predefined macros.
898 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
900 PR target/113950
901 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
902 and simplify else if with else.
904 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
906 * system.h: Include safe-ctype.h after C++ standard headers.
908 2024-03-07 Jakub Jelinek <jakub@redhat.com>
910 PR rtl-optimization/110079
911 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
912 asm goto.
914 2024-03-07 Jakub Jelinek <jakub@redhat.com>
916 PR middle-end/105533
917 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
918 if val is not HOST_WIDE_INT_MIN or if mode has exactly
919 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
920 val - 1.
922 2024-03-07 Jakub Jelinek <jakub@redhat.com>
924 PR middle-end/105533
925 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
926 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
927 LOG2_BITS_PER_UNIT.
929 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
931 * config.gcc: Add a case for loongarch*-*-linux-musl*.
932 * config/loongarch/linux.h: Disable the multilib-compatible
933 treatment for *musl* targets.
934 * config/loongarch/musl.h: New file.
936 2024-03-07 Jakub Jelinek <jakub@redhat.com>
938 PR tree-optimization/114009
939 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
940 argument even for GENERIC, not just for GIMPLE.
941 * match.pd (a * !a -> 0): New simplifications.
943 2024-03-07 demin.han <demin.han@starfivetech.com>
945 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
946 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
947 (expand_vec_cmp_float): Adapt arguments
949 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
951 PR target/114232
952 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
953 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
954 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
955 (<plusminus:insn>v2qi3): Enable for optimize_size instead
956 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
957 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
958 (<any_shift:insn>v2qi3): Enable for optimize_size instead
959 of optimize_function_for_size_p.
961 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
963 PR target/114200
964 PR target/114202
965 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
967 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
969 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
970 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
971 offset handling.
972 (costs::add_stmt_cost): Also adjust cost for statements without
973 stmt_info.
974 * config/riscv/riscv-vector-costs.h: Define zero constant.
976 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
978 PR target/113915
979 * config/arm/arm.md (NOCOND): Improve comment.
980 (arm_rev*) Add predicable.
981 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
982 PREDICABLE_YES.
984 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
986 PR target/113001
987 PR target/112871
988 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
989 operands when the comparison operand is the same as the false
990 arm for a NE test.
992 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
994 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
995 Eliminate common code and use generic code instead.
997 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
999 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1000 rtx cost.
1002 2024-03-06 Richard Biener <rguenther@suse.de>
1004 PR tree-optimization/114239
1005 * tree-vect-loop.cc (vect_get_vect_def): Remove.
1006 (vect_create_epilog_for_reduction): The passed in stmt_info
1007 should now be the live stmt that produces the scalar reduction
1008 result. Revert PR114192 fix. Base reduction info off
1009 info_for_reduction. Remove special handling of
1010 early-break/peeled, restore original vector def gathering.
1011 Make sure to pick the correct exit PHIs.
1012 (vectorizable_live_operation): Pass in the proper stmt_info
1013 for early break exits.
1015 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
1017 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1018 out-of-class definitions of static constants.
1020 2024-03-06 Richard Biener <rguenther@suse.de>
1022 PR tree-optimization/114249
1023 * tree-vect-slp.cc (vect_build_slp_instance): Move making
1024 a BB reduction lane number even ...
1025 (vect_slp_check_for_roots): ... here to avoid leaking
1026 pattern defs.
1028 2024-03-06 Richard Biener <rguenther@suse.de>
1030 PR tree-optimization/114246
1031 * tree-ssa-dse.cc (increment_start_addr): Strip useless
1032 type conversions from the adjusted address.
1034 2024-03-06 Jakub Jelinek <jakub@redhat.com>
1036 PR rtl-optimization/114190
1037 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1038 Call df_remove_problem for df_note before calling df_analyze.
1040 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
1041 Indu Bhagat <indu.bhagat@oracle.com>
1043 PR debug/114186
1044 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1045 in the correct order of the dimensions.
1046 (gen_ctf_subrange_type): Refactor out handling of
1047 DW_TAG_subrange_type DIE to here.
1049 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1051 PR sanitizer/97696
1052 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1054 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1056 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1057 and luti_strided.
1058 * config/aarch64/aarch64-sme.md
1059 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1060 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1061 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1062 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1063 (early_ra::maybe_convert_to_strided_access): Remove support for
1064 strided LUTI2 and LUTI4.
1066 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
1068 PR target/113510
1069 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1070 low_register_operand.
1072 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
1074 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1075 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1076 to "X = Y, X o= CST".
1078 2024-03-05 Xi Ruoyao <xry111@xry111.site>
1080 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1081 s9 as an alias of r22.
1083 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
1085 * config/avr/avr-protos.h (avr_out_insv): New proto.
1086 * config/avr/avr.cc (avr_out_insv): New function.
1087 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1088 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1089 * config/avr/avr.md (define_attr "adjust_len") Add insv.
1090 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1091 Add constraint alternative where the 3rd operand is a power
1092 of 2, and the source register may differ from the destination.
1093 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1094 instructions. Set attr "length" to "insv".
1095 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1097 2024-03-05 Richard Biener <rguenther@suse.de>
1099 PR tree-optimization/114231
1100 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1101 processing a BB SLP root.
1103 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1105 PR rtl-optimization/114211
1106 * lower-subreg.cc (resolve_simple_move): For double-word
1107 rotates by BITS_PER_WORD if there is overlap between source
1108 and destination use a temporary.
1110 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1112 PR middle-end/114157
1113 * gimple-lower-bitint.cc: Include stor-layout.h.
1114 (mergeable_op): Return true for BIT_FIELD_REF.
1115 (struct bitint_large_huge): Declare handle_bit_field_ref method.
1116 (bitint_large_huge::handle_bit_field_ref): New method.
1117 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1119 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1121 PR target/114116
1122 * config/i386/i386.h (enum call_saved_registers_type): Add
1123 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1124 * config/i386/i386-options.cc (ix86_set_func_type): Remove
1125 has_no_callee_saved_registers variable, add no_callee_saved_registers
1126 instead, initialize it depending on whether it is
1127 no_callee_saved_registers function or not. Don't set it if
1128 no_caller_saved_registers attribute is present. Adjust users.
1129 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1130 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1131 TYPE_NO_CALLEE_SAVED_REGISTERS.
1132 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1134 2024-03-05 Pan Li <pan2.li@intel.com>
1136 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1137 mode_size related code.
1139 2024-03-05 Patrick Palka <ppalka@redhat.com>
1141 * doc/invoke.texi (-Wno-global-module): Document.
1143 2024-03-04 David Faust <david.faust@oracle.com>
1145 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1146 * config/bpf/bpf.cc (bpf_expand_setmem): New.
1147 * config/bpf/bpf.md (setmemdi): New define_expand.
1149 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1151 PR rtl-optimization/113010
1152 * combine.cc (simplify_comparison): Guard the
1153 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1154 and initialize inner_mode.
1156 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1158 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1159 VMLALDAVAXQ_U cases.
1160 (VMLALDAVXQ): Remove iterator.
1161 (VMLALDAVXQ_P): Likewise.
1162 (VMLALDAVAXQ): Likewise.
1163 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1164 mode iterator attribute with V4BI mode.
1165 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1166 VMLALDAVAXQ_U): Remove unused unspecs.
1168 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1170 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1171 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1172 attribute.
1173 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1174 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1175 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1176 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1177 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1178 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1179 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1180 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1181 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1182 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1184 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1186 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1187 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1188 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1189 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1190 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1191 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1192 (arm_vcx1q<a>v16qi): Likewise.
1193 (arm_vcx1qav16qi): Likewise.
1194 (arm_vcx1qv16qi): Likewise.
1195 (arm_vcx2q<a>_p_v16qi): Likewise.
1196 (arm_vcx2q<a>v16qi): Likewise.
1197 (arm_vcx2qav16qi): Likewise.
1198 (arm_vcx2qv16qi): Likewise.
1199 (arm_vcx3q<a>_p_v16qi): Likewise.
1200 (arm_vcx3q<a>v16qi): Likewise.
1201 (arm_vcx3qav16qi): Likewise.
1202 (arm_vcx3qv16qi): Likewise.
1203 (@mve_<mve_insn>q_<supf><mode>): Likewise.
1204 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1205 (@mve_<mve_insn>q_<supf>v4si): Likewise.
1206 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1207 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1208 (@mve_<mve_insn>q_f<mode>): Likewise.
1209 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1210 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1211 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1212 (@mve_<mve_insn>q_m_f<mode>): Likewise.
1213 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1214 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1215 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1216 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1217 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1218 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1219 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1220 (mve_v<absneg_str>q_f<mode>): Likewise.
1221 (mve_<mve_addsubmul>q<mode>): Likewise.
1222 (mve_<mve_addsubmul>q_f<mode>): Likewise.
1223 (mve_vadciq_<supf>v4si): Likewise.
1224 (mve_vadciq_m_<supf>v4si): Likewise.
1225 (mve_vadcq_<supf>v4si): Likewise.
1226 (mve_vadcq_m_<supf>v4si): Likewise.
1227 (mve_vandq_<supf><mode>): Likewise.
1228 (mve_vandq_f<mode>): Likewise.
1229 (mve_vandq_m_<supf><mode>): Likewise.
1230 (mve_vandq_m_f<mode>): Likewise.
1231 (mve_vandq_s<mode>): Likewise.
1232 (mve_vandq_u<mode>): Likewise.
1233 (mve_vbicq_<supf><mode>): Likewise.
1234 (mve_vbicq_f<mode>): Likewise.
1235 (mve_vbicq_m_<supf><mode>): Likewise.
1236 (mve_vbicq_m_f<mode>): Likewise.
1237 (mve_vbicq_m_n_<supf><mode>): Likewise.
1238 (mve_vbicq_n_<supf><mode>): Likewise.
1239 (mve_vbicq_s<mode>): Likewise.
1240 (mve_vbicq_u<mode>): Likewise.
1241 (@mve_vclzq_s<mode>): Likewise.
1242 (mve_vclzq_u<mode>): Likewise.
1243 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1244 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1245 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1246 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1247 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1248 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1249 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1250 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1251 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1252 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1253 (mve_vcvtaq_<supf><mode>): Likewise.
1254 (mve_vcvtaq_m_<supf><mode>): Likewise.
1255 (mve_vcvtbq_f16_f32v8hf): Likewise.
1256 (mve_vcvtbq_f32_f16v4sf): Likewise.
1257 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1258 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1259 (mve_vcvtmq_<supf><mode>): Likewise.
1260 (mve_vcvtmq_m_<supf><mode>): Likewise.
1261 (mve_vcvtnq_<supf><mode>): Likewise.
1262 (mve_vcvtnq_m_<supf><mode>): Likewise.
1263 (mve_vcvtpq_<supf><mode>): Likewise.
1264 (mve_vcvtpq_m_<supf><mode>): Likewise.
1265 (mve_vcvtq_from_f_<supf><mode>): Likewise.
1266 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1267 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1268 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1269 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1270 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1271 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1272 (mve_vcvtq_to_f_<supf><mode>): Likewise.
1273 (mve_vcvttq_f16_f32v8hf): Likewise.
1274 (mve_vcvttq_f32_f16v4sf): Likewise.
1275 (mve_vcvttq_m_f16_f32v8hf): Likewise.
1276 (mve_vcvttq_m_f32_f16v4sf): Likewise.
1277 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1278 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1279 (mve_veorq_s><mode>): Likewise.
1280 (mve_veorq_u><mode>): Likewise.
1281 (mve_veorq_f<mode>): Likewise.
1282 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1283 (mve_vidupq_u<mode>_insn): Likewise.
1284 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1285 (mve_viwdupq_wb_u<mode>_insn): Likewise.
1286 (mve_vldrbq_<supf><mode>): Likewise.
1287 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1288 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1289 (mve_vldrbq_z_<supf><mode>): Likewise.
1290 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1291 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1292 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1293 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1294 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1295 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1296 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1297 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1298 (mve_vldrhq_<supf><mode>): Likewise.
1299 (mve_vldrhq_fv8hf): Likewise.
1300 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1301 (mve_vldrhq_gather_offset_fv8hf): Likewise.
1302 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1303 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1304 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1305 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1306 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1307 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1308 (mve_vldrhq_z_<supf><mode>): Likewise.
1309 (mve_vldrhq_z_fv8hf): Likewise.
1310 (mve_vldrwq_<supf>v4si): Likewise.
1311 (mve_vldrwq_fv4sf): Likewise.
1312 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1313 (mve_vldrwq_gather_base_fv4sf): Likewise.
1314 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1315 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1316 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1317 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1318 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1319 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1320 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1321 (mve_vldrwq_gather_offset_fv4sf): Likewise.
1322 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1323 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1324 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1325 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1326 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1327 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1328 (mve_vldrwq_z_<supf>v4si): Likewise.
1329 (mve_vldrwq_z_fv4sf): Likewise.
1330 (mve_vmvnq_s<mode>): Likewise.
1331 (mve_vmvnq_u<mode>): Likewise.
1332 (mve_vornq_<supf><mode>): Likewise.
1333 (mve_vornq_f<mode>): Likewise.
1334 (mve_vornq_m_<supf><mode>): Likewise.
1335 (mve_vornq_m_f<mode>): Likewise.
1336 (mve_vornq_s<mode>): Likewise.
1337 (mve_vornq_u<mode>): Likewise.
1338 (mve_vorrq_<supf><mode>): Likewise.
1339 (mve_vorrq_f<mode>): Likewise.
1340 (mve_vorrq_m_<supf><mode>): Likewise.
1341 (mve_vorrq_m_f<mode>): Likewise.
1342 (mve_vorrq_m_n_<supf><mode>): Likewise.
1343 (mve_vorrq_n_<supf><mode>): Likewise.
1344 (mve_vorrq_s<mode>): Likewise.
1345 (mve_vorrq_s<mode>): Likewise.
1346 (mve_vsbciq_<supf>v4si): Likewise.
1347 (mve_vsbciq_m_<supf>v4si): Likewise.
1348 (mve_vsbcq_<supf>v4si): Likewise.
1349 (mve_vsbcq_m_<supf>v4si): Likewise.
1350 (mve_vshlcq_<supf><mode>): Likewise.
1351 (mve_vshlcq_m_<supf><mode>): Likewise.
1352 (mve_vshrq_m_n_<supf><mode>): Likewise.
1353 (mve_vshrq_n_<supf><mode>): Likewise.
1354 (mve_vstrbq_<supf><mode>): Likewise.
1355 (mve_vstrbq_p_<supf><mode>): Likewise.
1356 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1357 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1358 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1359 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1360 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1361 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1362 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1363 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1364 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1365 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1366 (mve_vstrhq_<supf><mode>): Likewise.
1367 (mve_vstrhq_fv8hf): Likewise.
1368 (mve_vstrhq_p_<supf><mode>): Likewise.
1369 (mve_vstrhq_p_fv8hf): Likewise.
1370 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1371 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1372 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1373 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1374 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1375 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1376 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1377 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1378 (mve_vstrwq_<supf>v4si): Likewise.
1379 (mve_vstrwq_fv4sf): Likewise.
1380 (mve_vstrwq_p_<supf>v4si): Likewise.
1381 (mve_vstrwq_p_fv4sf): Likewise.
1382 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1383 (mve_vstrwq_scatter_base_fv4sf): Likewise.
1384 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1385 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1386 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1387 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1388 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1389 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1390 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1391 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1392 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1393 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1394 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1395 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1396 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1397 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1399 2024-03-04 Marek Polacek <polacek@redhat.com>
1401 * doc/extend.texi: Update [[gnu::no_dangling]].
1403 2024-03-04 Andrew Stubbs <ams@baylibre.com>
1405 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1406 * expr.cc (store_constructor): Likewise.
1407 (do_store_flag): Likewise.
1409 2024-03-04 Mark Wielaard <mark@klomp.org>
1411 * common.opt.urls: Regenerate.
1412 * config/avr/avr.opt.urls: Likewise.
1413 * config/i386/i386.opt.urls: Likewise.
1414 * config/pru/pru.opt.urls: Likewise.
1415 * config/riscv/riscv.opt.urls: Likewise.
1416 * config/rs6000/rs6000.opt.urls: Likewise.
1418 2024-03-04 Richard Biener <rguenther@suse.de>
1420 PR tree-optimization/114197
1421 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1422 there are volatile bitfield accesses.
1423 (pass_if_conversion::execute): Throw away result if the
1424 if-converted and original loops are not nested as expected.
1426 2024-03-04 Richard Biener <rguenther@suse.de>
1428 PR tree-optimization/114164
1429 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1430 the code generated for mask argument setup is not supported.
1432 2024-03-04 Richard Biener <rguenther@suse.de>
1434 PR tree-optimization/114203
1435 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1436 adjustment before making the result defined at zero.
1438 2024-03-04 Richard Biener <rguenther@suse.de>
1440 PR tree-optimization/114192
1441 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1442 appropriate def for the live out stmt in case of an alternate
1443 exit.
1445 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1447 PR middle-end/114209
1448 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1449 unshare_expr when creating a MEM_REF from MEM_REF.
1450 (bitint_large_huge::lower_stmt): Call unshare_expr.
1452 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1454 PR target/114184
1455 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1456 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1457 register.
1459 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
1461 PR target/114187
1462 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1463 lowpart_subreg to perform type conversion, to avoid confusion
1464 over the offset to use in the call to simplify_reg_subreg.
1466 2024-03-03 Greg McGary <gkm@rivosinc.com>
1468 PR rtl-optimization/113010
1469 * combine.cc (simplify_comparison): Simplify a SUBREG on
1470 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1471 MEM load.
1473 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1475 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
1476 Use bool in place of int for boolean logic (if possible).
1477 Move declarations to definitions (if possible).
1478 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
1479 * config/avr/avr-dimode.md: Same.
1480 * config/avr/constraints.md: Same.
1481 * config/avr/predicates.md: Same.
1483 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
1485 PR target/113720
1486 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
1487 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
1488 simplify insn RTX using UMUL_HIGHPART rtx_code.
1489 (*umuldi3_highpart_const): Remove.
1491 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1493 PR target/114100
1494 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
1495 * config/avr/avr.cc (_reg_unused_after): Make static. And
1496 add 3rd argument to skip the current insn.
1497 (reg_unused_after): Adjust call of reg_unused_after.
1498 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
1499 unneeded frame pointer adjustments.
1501 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1503 PR target/92729
1504 * config/avr/avr.md (define_attr "cc"): Remove.
1505 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1506 from prototype.
1507 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1508 its uses. Add insn argument.
1509 (avr_out_plus_symbol): Remove pcc argument and its uses.
1510 (avr_out_plus): Remove pcc argument and its uses.
1511 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1512 (avr_out_round): Adjust call of avr_out_plus.
1514 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1516 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1517 from r14-9273.
1519 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
1521 PR target/101737
1522 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1523 is not an insn, but e.g. a code label.
1525 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1527 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1528 * config/avr/avr.cc: Use them instead of magic numbers when it
1529 means a register number.
1531 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1533 * config/avr/avr.cc: Adjust some comments.
1535 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1537 PR target/114100
1538 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1539 the low part of the frame pointer with 8-bit stack pointer.
1541 2024-03-01 Patrick Palka <ppalka@redhat.com>
1543 PR c++/104919
1544 PR c++/106009
1545 * tree-inline.cc (remap_decl): Handle copy_decl returning the
1546 original decl.
1547 (remap_decls): Handle remap_decl returning the original decl.
1548 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
1549 CONST_DECL.
1551 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
1553 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
1554 type attribute.
1555 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
1556 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
1557 (movhi_internal, movqi_internal): Likewise.
1558 (movsf_softfloat, movsf_hardfloat): Likewise.
1559 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
1560 (movdf_softfloat): Likewise.
1562 2024-03-01 Marek Polacek <polacek@redhat.com>
1564 PR c++/110358
1565 PR c++/109642
1566 * doc/extend.texi: Document gnu::no_dangling.
1567 * doc/invoke.texi: Mention that gnu::no_dangling disables
1568 -Wdangling-reference.
1570 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1572 * config/avr/avr.opt: Overhaul help screen.
1574 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1575 Tobias Burnus <tburnus@baylibre.com>
1577 PR c++/110347
1578 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
1579 lang_hooks.decls.omp_disregard_value_expr for
1580 (first)private in target regions.
1582 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1584 PR middle-end/114136
1585 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
1586 n_named_args initially before INIT_CUMULATIVE_ARGS to
1587 structure_value_addr_parm rather than 0, after it don't modify
1588 it if strict_argument_naming and clear only if
1589 !pretend_outgoing_varargs_named.
1591 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1593 PR debug/114015
1594 * dwarf2out.cc (should_move_die_to_comdat): Return false for
1595 aggregates without DW_AT_byte_size attribute or with non-constant
1596 DW_AT_byte_size.
1598 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1600 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
1601 valid values for level.
1603 2024-03-01 Richard Biener <rguenther@suse.de>
1605 PR middle-end/114070
1606 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
1607 Allow the folding if before lowering and the current IL
1608 isn't supported with vcond_mask.
1610 2024-03-01 xuli <xuli1@eswincomputing.com>
1612 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
1613 attribute to riscv_attribute_table.
1614 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
1615 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
1616 * doc/extend.texi: Add riscv_vector_cc attribute description.
1618 2024-03-01 Pan Li <pan2.li@intel.com>
1620 PR target/112817
1621 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
1622 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
1623 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
1624 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
1625 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
1626 comments for option replacement.
1627 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
1628 riscv_autovec_preference to rvv_vector_bits.
1629 (vls_mode_valid_p): Ditto.
1630 (estimated_poly_value): Ditto.
1631 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
1632 vector chunks and honor new option mrvv-vector-bits.
1633 (riscv_override_options_internal): Update comments and rename the
1634 vector chunks.
1635 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
1636 internal option param=riscv-autovec-preference.
1638 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1640 * function.cc (assign_parms): Only call assign_parms_setup_varargs
1641 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
1643 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1645 PR middle-end/114156
1646 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
1647 rhs1 of a VCE to have no underlying variable if it is a load and
1648 handle that case.
1650 2024-02-29 David Malcolm <dmalcolm@redhat.com>
1652 PR analyzer/114159
1653 * function.cc (function_name): Make param const.
1654 * function.h (function_name): Likewise.
1656 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1658 PR target/114100
1659 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
1660 * config/avr/avr.opt (-mfuse-add=): New target option.
1661 * common/config/avr/avr-common.cc (avr_option_optimization_table)
1662 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
1663 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
1664 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
1665 * config/avr/avr-protos.h (avr_split_tiny_move)
1666 (make_avr_pass_fuse_add): New protos.
1667 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
1668 avr_split_tiny_move to split indirect memory accesses.
1669 (gen_move_clobbercc): New define_expand helper.
1670 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
1671 (avr_pass_fuse_add): New class from rtl_opt_pass.
1672 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
1673 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
1674 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
1675 of PLUS addressing for AVR_TINY.
1676 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
1677 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
1678 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
1680 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1682 PR target/114132
1683 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
1684 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
1685 (avr_function_arg): Set it.
1686 (avr_frame_pointer_required_p): Use it instead of .nregs.
1688 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
1690 PR target/108174
1691 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
1692 static and mark with GTY.
1694 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1696 * config/loongarch/loongarch.md
1697 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
1699 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1701 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
1702 (crc): New define_int_attr.
1703 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
1704 into ...
1705 (loongarch_<crc>_w_<size>_w): ... here.
1707 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
1709 PR target/114130
1710 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
1711 extend the expected value if needed.
1713 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1715 * config.gcc (target_gtfiles): Change coreout to btfext-out.
1716 (extra_objs): Change coreout to btfext-out.
1717 * config/bpf/coreout.cc: Rename to btfext-out.cc.
1718 * config/bpf/btfext-out.cc: Add.
1719 * config/bpf/coreout.h: Rename to btfext-out.h.
1720 * config/bpf/btfext-out.h: Add.
1721 * config/bpf/core-builtins.cc: Change include.
1722 * config/bpf/core-builtins.h: Change include.
1723 * config/bpf/t-bpf: Accomodate renamed files.
1725 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1727 PR target/113453
1728 * config/bpf/bpf.cc (bpf_function_prologue): Define target
1729 hook.
1730 * config/bpf/coreout.cc (brf_ext_info_section)
1731 (btf_ext_info): Move from coreout.h
1732 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
1733 (bpf_core_reloc): Rename to btf_ext_core_reloc.
1734 (btf_ext): Add static variable.
1735 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
1736 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
1737 (btf_ext_add_string, btf_funcinfo_type_callback)
1738 (btf_add_func_info_for, btf_validate_funcinfo)
1739 (btf_ext_info_len, output_btfext_func_info): Add function.
1740 (output_btfext_header, bpf_core_reloc_add)
1741 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
1742 Change to support new structs.
1743 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
1744 Move and change in coreout.cc.
1745 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
1747 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1749 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
1750 enabled by default for BPF.
1751 (bpf_file_end): Call BTF deallocation.
1752 (bpf_asm_init_sections): Correct condition.
1753 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
1754 deallocation.
1755 (ctf_debuf_finish): Correct condition for calling
1756 ctf_debug_finalize.
1758 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1760 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
1761 (traverse_btf_func_types): Define function.
1762 * ctfc.h (funcs_traverse_callback): Typedef for function
1763 prototype.
1764 (traverse_btf_func_types): Add prototype.
1766 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1768 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
1770 2024-02-28 Richard Biener <rguenther@suse.de>
1772 PR tree-optimization/113831
1773 PR tree-optimization/108355
1774 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
1775 PR113831 fix.
1777 2024-02-28 Richard Biener <rguenther@suse.de>
1779 PR tree-optimization/114121
1780 * tree-ssa-sccvn.h (vn_reference_s::offset,
1781 vn_reference_s::max_size): New fields.
1782 (vn_reference_insert_pieces): Adjust prototype.
1783 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
1784 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
1785 size, allow using "don't know" state.
1786 (vn_walk_cb_data::finish): Pass along offset/max_size.
1787 (vn_reference_lookup_or_insert_for_pieces): Take offset and
1788 max_size as argument and use it.
1789 (vn_reference_lookup_3): Properly adjust offset and max_size
1790 according to the adjusted ao_ref.
1791 (vn_reference_lookup_pieces): Initialize offset and max_size.
1792 (vn_reference_lookup): Likewise.
1793 (vn_reference_lookup_call): Likewise.
1794 (vn_reference_insert): Likewise.
1795 (visit_reference_op_call): Likewise.
1796 (vn_reference_insert_pieces): Take offset and max_size
1797 as argument and use it.
1799 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
1801 PR tree-optimization/114075
1802 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
1803 point vectors
1805 2024-02-28 Jakub Jelinek <jakub@redhat.com>
1807 PR tree-optimization/114041
1808 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
1809 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
1811 2024-02-28 Jakub Jelinek <jakub@redhat.com>
1813 PR tree-optimization/113988
1814 * stor-layout.h (bitwise_mode_for_size): Declare.
1815 * stor-layout.cc (bitwise_mode_for_size): New function.
1816 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
1817 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
1818 Use BITS_PER_UNIT instead of 8.
1820 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
1822 PR target/113871
1823 * config/i386/mmx.md (V248FI): Add V2BF mode.
1824 (V24FI_32): Ditto.
1826 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
1828 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
1829 if either ref->offset is not byte aligned or ref->size is not known
1830 to be equal to ref->max_size.
1831 (maybe_trim_complex_store): Fix description.
1832 (maybe_trim_constructor_store): Likewise.
1833 (maybe_trim_partially_dead_store): Likewise.
1835 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
1837 * config/arm/mmintrin.h: Warn if this header is included without
1838 defining __ENABLE_DEPRECATED_IWMMXT.
1840 2024-02-27 Richard Biener <rguenther@suse.de>
1842 PR tree-optimization/114074
1843 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
1844 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
1845 Handle poly vs. non-poly multiplication correctly with respect
1846 to undefined behavior on overflow.
1848 2024-02-27 Jakub Jelinek <jakub@redhat.com>
1850 PR rtl-optimization/114044
1851 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
1852 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
1853 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
1854 expand_PARITY): Declare.
1855 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
1856 expand_CTZ, expand_FFS, expand_PARITY): New functions.
1857 (expand_POPCOUNT): Use expand_bitquery.
1859 2024-02-27 Richard Biener <rguenther@suse.de>
1861 PR tree-optimization/114081
1862 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1863 Perform manual dominator update for prologue peeling.
1864 (vect_do_peeling): Properly update dominators after adding the
1865 prologue-around guard.
1867 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
1869 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
1870 (mstrict-X): Tag as "Optimization".
1872 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
1874 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
1875 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
1877 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1878 H.J. Lu <hjl.tools@gmail.com>
1880 PR rtl-optimization/113617
1881 * varasm.cc (default_elf_select_rtx_section): For
1882 references to private symbols in comdat sections
1883 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
1884 or .rodata.<comdat> comdat sections.
1886 2024-02-26 Richard Biener <rguenther@suse.de>
1888 PR tree-optimization/114099
1889 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1890 Create and fill in a needed virtual LC PHI for the alternate
1891 exits. Remove code dealing with that missing.
1893 2024-02-26 Richard Biener <rguenther@suse.de>
1895 PR tree-optimization/114068
1896 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
1897 New function.
1898 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
1899 on the main exit if needed. Remove band-aid for the case
1900 it was missing.
1902 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
1904 PR target/114097
1905 * config/i386/i386-options.cc (ix86_set_func_type): Check
1906 interrupt instead of noreturn attribute.
1908 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1910 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
1911 !TARGET_64BIT.
1913 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1915 PR tree-optimization/114090
1916 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
1917 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
1918 types.
1919 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
1921 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1923 PR middle-end/114084
1924 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
1925 if all subtrees of var0 come from one of the op0 or op1 operands
1926 and all subtrees of con0 come from the other one. Don't clear
1927 variables which are never used afterwards.
1929 2024-02-26 Richard Biener <rguenther@suse.de>
1931 PR middle-end/114070
1932 * genmatch.cc (parser::parse_c_expr): Do not record operand
1933 lists but only mark operators used.
1934 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
1935 Properly guard the case of tcc_comparison changing the VEC_COND
1936 value operand type.
1938 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1940 PR target/114094
1941 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
1942 to printed instruction.
1944 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
1946 PR target/114098
1947 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
1948 __builtin_ia32_ldtilecfg.
1949 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
1950 * config/i386/i386-builtin.def (BDESC): Add
1951 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
1952 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
1953 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
1954 * config/i386/i386.md (ldtilecfg): New pattern.
1955 (sttilecfg): Likewise.
1957 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
1959 PR tree-optimization/113205
1960 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
1961 the proposed layout if it does not allow a source partition with
1962 layout 2 to keep that layout.
1964 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1966 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
1967 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
1968 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
1969 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
1970 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
1971 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
1972 macros.
1973 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
1974 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
1975 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
1976 HOST_WIDE_INT_UC macros.
1977 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
1978 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
1979 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
1980 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
1981 macros.
1982 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
1983 * config/i386/constraints.md (define_constraint "L"): Use
1984 HOST_WIDE_INT_C macro.
1985 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
1986 macro.
1987 (movl + movb peephole2): Likewise.
1988 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
1989 (const_32bit_mask): Likewise.
1991 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1993 PR middle-end/114073
1994 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
1995 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
1996 types like vector or complex types.
1997 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
1998 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
1999 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2001 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
2003 PR target/114028
2004 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2005 Return false if inner mode is already Pmode.
2006 (rvv_builder::is_all_same_sequence): New function.
2007 (expand_vec_init): Emit broadcast if sequence is all same.
2009 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2011 PR target/113613
2012 * config/aarch64/aarch64-early-ra.cc
2013 (early_ra::m_current_region): New member variable.
2014 (early_ra::m_fpr_recency): Likewise.
2015 (early_ra::start_new_region): Bump m_current_region.
2016 (early_ra::allocate_colors): Prefer less recently used registers
2017 in the event of a tie. Add a comment to explain why we prefer(ed)
2018 higher-numbered registers.
2019 (early_ra::find_oldest_color): Prefer less recently used registers
2020 here too.
2021 (early_ra::finalize_allocation): Update recency information for
2022 allocated registers.
2023 (early_ra::process_blocks): Initialize m_current_region and
2024 m_fpr_recency.
2026 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2028 PR target/113295
2029 * config/aarch64/aarch64-early-ra.cc
2030 (early_ra::test_strictness): New enum.
2031 (early_ra::is_chain_candidate): Add a strictness parameter to
2032 control whether only correctness matters, or whether both correctness
2033 and heuristics should be used. Handle multiple levels of equivalence.
2034 (early_ra::find_related_start): Update call accordingly.
2035 (early_ra::strided_polarity_pref): Likewise.
2036 (early_ra::form_chains): Likewise.
2037 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2038 correctness mode rather than trying to inline the test.
2040 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2042 PR target/113295
2043 * config/aarch64/aarch64-early-ra.cc
2044 (early_ra::find_related_start): Account for definitions by shared
2045 registers when testing for a single register definition.
2046 (early_ra::accumulate_defs): New function.
2047 (early_ra::record_copy): If A shares B's register, fold A's
2048 definition information into B's. Fold A's use information into B's.
2050 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
2052 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2053 if R_X86_64_CODE_6_GOTTPOFF is supported.
2054 * config.in: Regenerated.
2055 * configure: Likewise.
2056 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2057 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2059 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
2061 PR target/108120
2062 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2063 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2065 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2067 PR rtl-optimization/114054
2068 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2069 temp variable instead of target parameter for result.
2071 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2073 PR tree-optimization/114040
2074 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2075 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2076 probability from likely to unlikely. When handling the true true
2077 store, first cast to limb_access_type and then to l's type.
2079 2024-02-23 Richard Biener <rguenther@suse.de>
2081 PR target/90785
2082 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2084 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2086 PR other/109668
2087 * config/riscv/arch-canonicalize: Move to python3
2088 * config/riscv/multilib-generator: Likewise
2090 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2092 * doc/invoke.texi: Document -mcpu.
2094 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
2096 * configure: Regenerate.
2097 * configure.ac: Add parameter "--fatal-warnings" to assemble
2098 when checking whether the assemble support conditional branch
2099 relaxation.
2101 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2103 PR c/114007
2104 * doc/extend.texi: (__extension__): Remove comments about scope
2105 tokens vs. two colons.
2107 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
2109 PR tree-optimization/109804
2110 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2111 DEMANGLE_COMPONENT_UNNAMED_TYPE.
2113 2024-02-22 Richard Biener <rguenther@suse.de>
2115 PR tree-optimization/114048
2116 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2117 can also produce -1 off.
2119 2024-02-22 Richard Biener <rguenther@suse.de>
2121 PR tree-optimization/114027
2122 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2123 condition reduction classification only for single-element
2124 chains.
2126 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2128 PR ipa/111960
2129 * profile-count.h (profile_count::dump): Remove overload with
2130 char * first argument.
2131 * profile-count.cc (profile_count::dump): Change overload with char *
2132 first argument which uses sprintf into the overfload with FILE *
2133 first argument and use fprintf instead. Remove overload which wrapped
2134 it.
2136 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2138 PR tree-optimization/113993
2139 * tree-call-cdce.cc (get_no_error_domain): Handle
2140 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
2141 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2142 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2143 the as the F128 suffixed cases, otherwise as non-suffixed ones.
2144 Handle BUILT_IN_{EXP,POW}10L for
2145 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2146 as (-inf, 4932).
2148 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2150 PR tree-optimization/114038
2151 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2152 loop exit condition if end is divisible by limb_prec.
2154 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
2156 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2157 problem of mabi=, mno-flush-func, mexplicit-relocs;
2158 add missing leading - of mbranch-cost option.
2159 * config/mips/mips.opt.urls: Regenerate.
2161 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
2163 PR target/109987
2164 * config/rs6000/constraints.md (we): Update internal doc without
2165 referring to option -mpower9-vector.
2166 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2167 special handlings.
2168 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2169 OTHER_P8_VECTOR_MASKS): Merge to ...
2170 (OTHER_VSX_VECTOR_MASKS): ... here.
2171 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2172 some error message handlings and explicit option mask adjustments on
2173 explicit option power{8,9}-vector conflicting with other options.
2174 (rs6000_print_isa_options): Update comments.
2175 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2176 related array items and handlings.
2177 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2178 special handlings.
2179 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2180 WarnRemoved.
2181 * doc/extend.texi: Remove documentation referring to option
2182 -mpower8-vector.
2183 * doc/invoke.texi: Remove documentation for option
2184 -mpower{8,9}-vector and adjust some documentation referring to them.
2185 * doc/md.texi: Update documentation for constraint we.
2186 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2188 2024-02-22 Pan Li <pan2.li@intel.com>
2190 PR target/114017
2191 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2192 the version to 0.12.
2194 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2196 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2198 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2199 Robin Dapp <rdapp.gcc@gmail.com>
2201 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2202 (generic_ooo_vec_load): Ditto
2203 (generic_ooo_vec_store): Ditto
2204 (generic_ooo_vec_loadstore_seg): Ditto
2205 (generic_ooo_vec_alu): Ditto
2206 (generic_ooo_vec_fcmp): Ditto
2207 (generic_ooo_vec_imul): Ditto
2208 (generic_ooo_vec_fadd): Ditto
2209 (generic_ooo_vec_fmul): Ditto
2210 (generic_ooo_crypto): Ditto
2211 (generic_ooo_perm): Ditto
2212 (generic_ooo_vec_reduction): Ditto
2213 (generic_ooo_vec_ordered_reduction): Ditto
2214 (generic_ooo_vec_idiv): Ditto
2215 (generic_ooo_vec_float_divsqrt): Ditto
2216 (generic_ooo_vec_mask): Ditto
2217 (generic_ooo_vec_vesetvl): Ditto
2218 (generic_ooo_vec_setrm): Ditto
2219 (generic_ooo_vec_readlen): Ditto
2220 * config/riscv/riscv.md: Include generic-vector-ooo
2221 * config/riscv/generic-vector-ooo.md: New file. To here
2223 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2225 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2226 (generic_ooo_branch): Ditto
2227 * config/riscv/generic.md (generic_sfb_alu): Ditto
2228 (generic_fmul_half): Ditto
2229 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2230 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2231 (sifive_7_popcount): Ditto
2232 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2233 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2234 * config/riscv/vector.md: Change rdfrm to fmove
2235 * config/riscv/zc.md: Change pushpop to load/store
2237 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
2239 * doc/invoke.texi (Warning Options): Fix typos.
2241 2024-02-21 David Faust <david.faust@oracle.com>
2243 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2244 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2245 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2247 2024-02-21 Martin Jambor <mjambor@suse.cz>
2249 PR ipa/113476
2250 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2251 initializers in the contructor.
2252 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2253 * ipa-cp.h: New file.
2254 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2255 (ipcp_value_source): Move to ipa-cp.h.
2256 (ipcp_value_base): Likewise.
2257 (ipcp_value): Likewise.
2258 (ipcp_lattice): Likewise.
2259 (ipcp_agg_lattice): Likewise.
2260 (ipcp_bits_lattice): Likewise.
2261 (ipcp_vr_lattice): Likewise.
2262 (ipcp_param_lattices): Likewise.
2263 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2264 (ipa_value_from_jfunc): Adjust a check for empty lattices.
2265 (ipa_context_from_jfunc): Likewise.
2266 (ipa_agg_value_from_jfunc): Likewise.
2267 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2268 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2269 just in contiguous memory.
2270 (ipcp_store_vr_results): Adjust a check for empty lattices.
2271 * auto-profile.cc: Include sreal.h and ipa-cp.h.
2272 * cgraph.cc: Likewise.
2273 * cgraphclones.cc: Likewise.
2274 * cgraphunit.cc: Likewise.
2275 * config/aarch64/aarch64.cc: Likewise.
2276 * config/i386/i386-builtins.cc: Likewise.
2277 * config/i386/i386-expand.cc: Likewise.
2278 * config/i386/i386-features.cc: Likewise.
2279 * config/i386/i386-options.cc: Likewise.
2280 * config/i386/i386.cc: Likewise.
2281 * config/rs6000/rs6000.cc: Likewise.
2282 * config/s390/s390.cc: Likewise.
2283 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2284 files to be included in gtype-desc.cc.
2285 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2286 * ipa-devirt.cc: Likewise.
2287 * ipa-fnsummary.cc: Likewise.
2288 * ipa-icf.cc: Likewise.
2289 * ipa-inline-analysis.cc: Likewise.
2290 * ipa-inline-transform.cc: Likewise.
2291 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2292 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2293 * ipa-param-manipulation.cc: Likewise.
2294 * ipa-predicate.cc: Likewise.
2295 * ipa-profile.cc: Likewise.
2296 * ipa-prop.cc: Likewise.
2297 (ipa_node_params_t::duplicate): Assert new lattices remain empty
2298 instead of setting them to NULL.
2299 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2300 * ipa-split.cc: Likewise.
2301 * ipa-sra.cc: Likewise.
2302 * ipa-strub.cc: Likewise.
2303 * ipa-utils.cc: Likewise.
2304 * ipa.cc: Likewise.
2305 * toplev.cc: Likewise.
2306 * tree-ssa-ccp.cc: Likewise.
2307 * tree-ssa-sccvn.cc: Likewise.
2308 * tree-vrp.cc: Likewise.
2310 2024-02-21 Tamar Christina <tamar.christina@arm.com>
2312 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2313 Armv8.7-a.
2315 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2317 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2318 Use aarch64_gen_compare_zero_and_branch rather than emitting
2319 a CBZ directly.
2321 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2323 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2324 Remove duplicated call.
2326 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2328 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2329 Check that each individual piece of state is shared in the same
2330 way, rather than using an aggregate check for PSTATE.ZA.
2332 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2334 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2335 In the code that commits a lazy save, only zero ZA if the function
2336 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
2338 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2340 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2341 directly inserting the associated sequence
2342 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2343 ...here instead.
2345 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2347 PR target/113995
2348 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2349 fold the SVE allocation into the initial allocation if the
2350 initial allocation includes a VG save.
2352 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2354 PR target/113220
2355 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2356 contain jumps even if called after initial RTL expansion.
2357 * mode-switching.cc: Include cfgbuild.h.
2358 (optimize_mode_switching): Allow the sequence returned by the
2359 emit hook to contain internal jumps. Record which blocks
2360 contain such jumps and split the blocks at the end.
2361 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2362 non-debug insns when scanning the sequence.
2364 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
2366 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2367 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2369 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2371 * doc/invoke.texi (-mmcu): Add information about MCU specs.
2373 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2375 * doc/invoke.texi (-minrt): Clarify that main
2376 must take no arguments.
2378 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2380 * config/avr/builtins.def: Use function prototypes of given size
2381 and signedness.
2382 * config/avr/avr.cc (avr_init_builtins): Adjust types required
2383 by builtins.def.
2384 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2386 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2388 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2389 instead of @table.
2391 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
2393 * config/bpf/bpf.opt: Add help information for -mcpu.
2395 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
2397 PR target/113805
2398 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2399 New pass.
2400 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2401 Declare.
2402 * config/aarch64/aarch64.md (is_call): New attribute.
2403 (*and<mode>3nr_compare0): Rename to...
2404 (@aarch64_and<mode>3nr_compare0): ...this.
2405 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2406 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2407 * config/aarch64/aarch64-speculation.cc: Update file comment to
2408 describe the new late pass.
2409 (aarch64_do_track_speculation): Handle is_call insns like other calls.
2410 (pass_track_speculation): Add an is_late member variable.
2411 (pass_track_speculation::gate): Run the late pass for streaming-
2412 compatible functions and the early pass for other functions.
2413 (make_pass_track_speculation): Update accordingly.
2414 (make_pass_late_track_speculation): New function.
2415 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2416 function.
2417 (aarch64_guard_switch_pstate_sm): Use it.
2419 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
2421 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2422 Register these builtins with a pointer to uint64_t rather than unsigned
2423 DI mode.
2425 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2427 PR target/113615
2428 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2429 Conditionalize on '!TARGET_RDNA2_PLUS'.
2430 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2431 (gcn_expand_reduc_scalar):
2432 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2434 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2436 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2437 '__gfx90a__' target CPU definition. Add some safeguards for the future.
2439 2024-02-19 Richard Biener <rguenther@suse.de>
2441 PR rtl-optimization/54052
2442 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2443 local defs by LR_OUT.
2445 2024-02-19 Jakub Jelinek <jakub@redhat.com>
2447 PR tree-optimization/113967
2448 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2449 in condition that @rpos is multiple of vector element size.
2451 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2453 PR target/113696
2454 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2455 Suppress vsetvl fusion.
2457 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
2459 PR target/113912
2460 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2461 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2462 (ix86_emit_save_regs): Don't generate push2 if
2463 ix86_can_use_push2pop2 return false.
2464 (ix86_expand_epilogue): Don't generate pop2 if
2465 ix86_can_use_push2pop2 return false.
2467 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2469 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2470 Note on complete device support.
2472 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2474 * doc/extend.texi (AVR Function Attributes): Fuse description
2475 of "signal" and "interrupt" attribute. Link pseudo instruction.
2477 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2479 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
2480 symbol type conversions.
2481 (__cacop_d): Likewise.
2482 (__cpucfg): Likewise.
2483 (__asrtle_d): Likewise.
2484 (__asrtgt_d): Likewise.
2485 (__lddir_d): Likewise.
2486 (__ldpte_d): Likewise.
2487 (__crc_w_b_w): Likewise.
2488 (__crc_w_h_w): Likewise.
2489 (__crc_w_w_w): Likewise.
2490 (__crc_w_d_w): Likewise.
2491 (__crcc_w_b_w): Likewise.
2492 (__crcc_w_h_w): Likewise.
2493 (__crcc_w_w_w): Likewise.
2494 (__crcc_w_d_w): Likewise.
2495 (__csrrd_w): Likewise.
2496 (__csrwr_w): Likewise.
2497 (__csrxchg_w): Likewise.
2498 (__csrrd_d): Likewise.
2499 (__csrwr_d): Likewise.
2500 (__csrxchg_d): Likewise.
2501 (__iocsrrd_b): Likewise.
2502 (__iocsrrd_h): Likewise.
2503 (__iocsrrd_w): Likewise.
2504 (__iocsrrd_d): Likewise.
2505 (__iocsrwr_b): Likewise.
2506 (__iocsrwr_h): Likewise.
2507 (__iocsrwr_w): Likewise.
2508 (__iocsrwr_d): Likewise.
2509 (__frecipe_s): Likewise.
2510 (__frecipe_d): Likewise.
2511 (__frsqrte_s): Likewise.
2512 (__frsqrte_d): Likewise.
2514 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2516 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2517 function return value type to unsigned short.
2519 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
2521 * doc/sourcebuild.texi: add scan-assembler-bound
2523 2024-02-16 Jason Merrill <jason@redhat.com>
2525 * gdbhooks.py: Fix regex syntax.
2527 2024-02-16 Richard Biener <rguenther@suse.de>
2529 PR tree-optimization/113895
2530 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2531 consistency checking when there are out-of-bound array
2532 accesses. Allow -1 off when from an array reference with
2533 constant index.
2535 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2537 PR target/106543
2538 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2539 pattern.
2541 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2543 * doc/sourcebuild.texi (Effective-Target Keywords, Other
2544 attribugs): Document linker_plugin.
2545 (Require Support): Document dg-require-linker-plugin.
2547 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2549 PR target/109349
2550 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
2551 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
2552 (RISCV_MINOR_VERSION_BASE): Ditto.
2553 (RISCV_REVISION_VERSION_BASE): Ditto.
2554 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
2555 rather than magic number.
2556 * config/riscv/riscv.h (riscv_arch_help): New.
2557 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
2558 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
2559 --print-supported-extensions.
2560 * config/riscv/riscv.opt (march=help): New.
2561 (print-supported-extensions): New.
2562 (-print-supported-extensions): New.
2563 * doc/invoke.texi (RISC-V Options): Document -march=help.
2565 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
2567 PR target/113780
2568 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
2569 for indirect calls with 4 or more arguments in pac-enabled functions.
2571 2024-02-15 David Faust <david.faust@oracle.com>
2573 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
2574 use ldxb instead of ldxh.
2576 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2578 PR middle-end/113921
2579 * cfgrtl.h (prepend_insn_to_edge): New declaration.
2580 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
2581 comment.
2582 (prepend_insn_to_edge): New function.
2583 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
2584 insert_insn_on_edge.
2586 2024-02-15 Richard Biener <rguenther@suse.de>
2588 PR tree-optimization/111156
2589 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
2590 at the pattern stmt if any.
2592 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
2594 PR target/113927
2595 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
2596 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
2597 * config/avr/avr.cc (avr_adiw_reg_p): New function.
2598 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
2599 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
2600 * config/avr/avr.md: Same.
2601 (attr "isa") <tiny, no_tiny>: Remove.
2602 <adiw, no_adiw>: Add.
2603 (define_insn, define_insn_and_split): When an alternative has
2604 constraint "w", then set attribute "isa" to "adiw".
2605 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
2606 Built-in define __AVR_HAVE_ADIW__.
2607 * doc/invoke.texi (AVR Options): Document it.
2609 2024-02-15 Andrew Stubbs <ams@baylibre.com>
2611 * config/gcn/gcn-valu.md
2612 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
2613 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
2614 details are supported on RDNA devices.
2616 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2618 PR middle-end/113508
2619 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
2620 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
2621 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
2622 Add sentence about what the mode m is.
2624 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2626 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
2627 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
2628 var.
2630 2024-02-15 Richard Biener <rguenther@suse.de>
2632 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
2633 stmts.
2635 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2637 PR tree-optimization/113567
2638 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
2639 _BitInt multiplication, division or modulo with
2640 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
2641 force the affected inputs into a new SSA_NAME.
2643 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
2645 PR target/113871
2646 * config/i386/mmx.md (V248FI): New mode iterator.
2647 (V24FI_32): DItto.
2648 (vec_shl_<V248FI:mode>): New expander.
2649 (vec_shl_<V24FI_32:mode>): Ditto.
2650 (vec_shr_<V248FI:mode>): Ditto.
2651 (vec_shr_<V24FI_32:mode>): Ditto.
2652 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
2653 (vec_shr_<V248FI:mode>): Ditto.
2655 2024-02-14 Jan Hubicka <jh@suse.cz>
2657 PR tree-optimization/111054
2658 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
2660 2024-02-14 Tamar Christina <tamar.christina@arm.com>
2662 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
2664 2024-02-14 Richard Biener <rguenther@suse.de>
2666 PR tree-optimization/113910
2667 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
2668 the hashval_t hash.
2670 2024-02-14 Jakub Jelinek <jakub@redhat.com>
2672 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
2673 (pp_integer_with_precision): For unsigned ptrdiff_t printing
2674 with u, o or x print ptrdiff_t argument converted to
2675 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
2677 2024-02-14 Richard Biener <rguenther@suse.de>
2679 PR middle-end/113576
2680 * expr.cc (do_store_flag): For vector bool compares of vectors
2681 with padding zero that.
2682 * dojump.cc (do_compare_and_jump): Likewise.
2684 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
2686 * doc/install.texi (Prerequisites): Update gettext link.
2688 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
2690 PR target/113876
2691 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
2692 Return false if the incoming stack isn't 16-byte aligned.
2694 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
2696 PR middle-end/113904
2697 * omp-general.cc (struct omp_ts_info): Update for splitting of
2698 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2699 * omp-selectors.h (enum omp_tp_type): Replace
2700 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2702 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
2704 PR target/113742
2705 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
2706 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
2708 2024-02-13 Richard Biener <rguenther@suse.de>
2710 PR tree-optimization/113895
2711 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
2712 offset to discover constant array indices in bits, handle
2713 COMPONENT_REF to bitfields.
2715 2024-02-13 Richard Biener <rguenther@suse.de>
2717 PR tree-optimization/113831
2718 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
2719 typo in comment.
2721 2024-02-13 Richard Biener <rguenther@suse.de>
2723 PR tree-optimization/113902
2724 * tree-vect-loop.cc (move_early_exit_stmts): Track
2725 last_seen_vuse for VUSE updating.
2727 2024-02-13 Tamar Christina <tamar.christina@arm.com>
2729 PR tree-optimization/113734
2730 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
2731 an early break loop as partial.
2733 2024-02-13 Richard Biener <rguenther@suse.de>
2735 PR tree-optimization/113898
2736 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
2737 missing accumulated off adjustment.
2739 2024-02-13 Jakub Jelinek <jakub@redhat.com>
2741 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
2742 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
2743 it against UINT_MAX and ULONG_MAX.
2745 2024-02-13 David Malcolm <dmalcolm@redhat.com>
2747 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
2748 to...
2749 (emit_diagnostic_valist_meta): ...this.
2750 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
2751 (emit_diagnostic_valist_meta): ...this.
2753 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2755 PR tree-optimization/113849
2756 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
2757 fast path for widening casts where !m_upwards_2limb and lhs_type
2758 has precision which is a multiple of limb_prec.
2760 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2762 PR c++/113674
2763 * attribs.cc (extract_attribute_substring): Remove.
2764 (lookup_scoped_attribute_spec): Don't call it.
2766 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2768 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
2769 and cast to fmt_size_t instead of %lu and cast to unsigned long.
2771 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
2773 * Makefile.in: Add no-info dependency.
2774 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
2775 available.
2776 * configure: Regenerate.
2778 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
2780 PR target/113855
2781 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
2782 available to all sub-targets.
2783 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2784 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2786 2024-02-12 Richard Biener <rguenther@suse.de>
2788 PR tree-optimization/113831
2789 PR tree-optimization/108355
2790 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
2791 we see variable array indices and get_ref_base_and_extent
2792 can resolve those to constants fix up the ops to constants
2793 as well.
2794 (ao_ref_init_from_vn_reference): Use 'off' member for
2795 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
2796 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
2798 2024-02-12 Pan Li <pan2.li@intel.com>
2800 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
2801 Replace args to arguments for misspelled term.
2803 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
2805 PR target/112944
2806 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
2807 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
2808 when not linked with -mrodata-in-ram.
2810 2024-02-12 Richard Biener <rguenther@suse.de>
2812 PR tree-optimization/113863
2813 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2814 Record crossed virtual PHIs.
2815 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
2816 virtual PHIs.
2818 2024-02-10 Marek Polacek <polacek@redhat.com>
2820 DR 2237
2821 PR c++/107126
2822 PR c++/97202
2823 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
2825 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2827 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
2828 computation of idx for i == 4 of bitint_prec_huge.
2830 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2832 PR middle-end/110754
2833 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
2834 decls create PARM_DECL with pointer to original type, set
2835 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
2836 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
2837 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
2838 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
2839 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
2840 of the var as argument.
2842 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2844 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
2845 size_t and precision 4 for ptrdiff_t. Formatting fix.
2846 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
2847 Formatting fixes.
2848 (test_pp_format): Test t and z modifiers.
2849 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
2851 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2853 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
2854 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
2855 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2856 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
2857 and casts to fmt_size_t instead of "%ld" and casts to long.
2858 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
2859 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
2860 instead of "%lu" and casts to unsigned long.
2861 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
2862 unsigned long.
2863 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2864 and casts to fmt_size_t instead of "%ld" and casts to long.
2865 * cfgexpand.cc (dump_stack_var_partition): Use
2866 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
2867 and casts to unsigned long.
2868 * gengtype.cc (adjust_field_rtx_def): Likewise.
2869 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2870 and casts to fmt_size_t instead of "%ld" and casts to long.
2871 * postreload-gcse.cc (dump_hash_table): Likewise.
2872 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
2873 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2874 (ggc_internal_alloc, ggc_free): Likewise.
2875 * genpreds.cc (write_lookup_constraint_1): Likewise.
2876 (write_insn_constraint_len): Likewise.
2877 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
2878 and casts to fmt_size_t instead of "%ld" and casts to long.
2879 * varasm.cc (output_constant_pool_contents): Use
2880 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
2881 * var-tracking.cc (dump_var): Likewise.
2883 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2885 PR tree-optimization/113783
2886 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
2887 through VIEW_CONVERT_EXPR for final cast checks. Handle
2888 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
2889 INTEGER_TYPEs.
2890 (gimple_lower_bitint): Don't merge mergeable operations or other
2891 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
2892 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
2893 mode is BLKmode.
2895 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2897 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
2898 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
2899 HOST_SIZE_T_PRINT_HEX_PURE): Define.
2900 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
2901 fixes.
2903 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2905 PR middle-end/113415
2906 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
2907 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
2908 of hand written loop with emit_insn of copy_insn and emit original
2909 after_rtl_seq on the last edge.
2911 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2913 PR tree-optimization/113818
2914 * gimple-lower-bitint.cc (add_eh_edge): New function.
2915 (bitint_large_huge::handle_load,
2916 bitint_large_huge::lower_mergeable_stmt,
2917 bitint_large_huge::lower_muldiv_stmt): Use it.
2919 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2921 PR tree-optimization/113774
2922 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
2923 emit any comparison if m_first and low + 1 is equal to
2924 m_upwards_2limb, simplify condition for that. If not
2925 single_comparison, not m_first and we can prove that the idx <= low
2926 comparison will be always true, emit instead of idx <= low
2927 comparison low <= low such that cfg cleanup will optimize it at
2928 the end of the pass.
2930 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
2932 PR tree-optimization/113735
2933 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
2934 limit_check().
2936 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2938 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
2939 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
2941 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
2943 PR target/113711
2944 PR target/113733
2945 * config/i386/constraints.md: List all constraints with j prefix.
2946 (j>): Change auto-dec to auto-inc in documentation.
2947 (je): Changed to a memory constraint with APX NDD TLS operand
2948 check.
2949 (jM): New memory constraint for APX NDD instructions.
2950 (jO): Likewise.
2951 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
2952 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
2953 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
2954 (*add<mode>_1[SWI48]): Use je and jM.
2955 (addsi_1_zext): Use jM.
2956 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
2957 (*sub<mode>_1[SWI]): Use jM.
2958 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
2959 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
2960 (*and<dwi>3_doubleword): Likewise.
2961 (*anddi_1): Use jM.
2962 (*andsi_1_zext): Likewise.
2963 (*and<mode>_1[SWI24]): Likewise.
2964 (*<code><dwi>3_doubleword[any_or]): Use rjO
2965 (*code<mode>_1[any_or SWI248]): Use jM.
2966 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
2967 * config/i386/predicates.md (apx_ndd_memory_operand): New.
2968 (apx_ndd_add_memory_operand): Likewise.
2970 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2972 PR target/113824
2973 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
2974 * doc/avr-mmcu.texi: Rebuild.
2976 2024-02-08 Tamar Christina <tamar.christina@arm.com>
2978 PR tree-optimization/113808
2979 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
2980 value cross iterations.
2982 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2984 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
2985 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
2987 2024-02-08 Richard Biener <rguenther@suse.de>
2989 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2990 Revert last change to dr_may_alias_p.
2992 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2994 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
2995 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
2996 Remove spec asm_misc.
2997 * config/avr/specs.h: Same.
2999 2024-02-08 Pan Li <pan2.li@intel.com>
3001 PR target/113766
3002 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3003 sure the c.arg_num is >= 2 before checking.
3004 (struct build_frm_base): Ditto.
3005 (struct narrow_alu_def): Ditto.
3007 2024-02-07 Richard Biener <rguenther@suse.de>
3009 PR tree-optimization/113796
3010 * tree-if-conv.cc (combine_blocks): Wipe range-info before
3011 replacing PHIs and inserting predicates.
3013 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
3014 Uros Bizjak <ubizjak@gmail.com>
3016 PR target/113690
3017 * config/i386/i386-features.cc (timode_convert_cst): New helper
3018 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3019 CONST_VECTOR.
3020 (timode_scalar_chain::convert_op): Use timode_convert_cst.
3021 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3022 Use timode_convert_cst.
3024 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
3026 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3027 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3028 (AARCH64_FL_DEBUGv8p9): Likewise.
3029 (AARCH64_FL_FGT2): Likewise.Likewise.
3030 (AARCH64_FL_ITE): Likewise.
3031 (AARCH64_FL_PFAR): Likewise.
3032 (AARCH64_FL_PMUv3_ICNTR): Likewise.
3033 (AARCH64_FL_PMUv3_SS): Likewise.
3034 (AARCH64_FL_PMUv3p9): Likewise.
3035 (AARCH64_FL_RASv2): Likewise.
3036 (AARCH64_FL_S1PIE): Likewise.
3037 (AARCH64_FL_S1POE): Likewise.
3038 (AARCH64_FL_S2PIE): Likewise.
3039 (AARCH64_FL_S2POE): Likewise.
3040 (AARCH64_FL_SCTLR2): Likewise.
3041 (AARCH64_FL_SEBEP): Likewise.
3042 (AARCH64_FL_SPE_FDS): Likewise.
3043 (AARCH64_FL_TCR2): Likewise.
3045 2024-02-07 Richard Biener <rguenther@suse.de>
3047 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3048 Only check whether reads are in-bound in places that are not safe.
3049 Fix dependence check. Add missing newline. Clarify comments.
3051 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3053 PR tree-optimization/113750
3054 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3055 for single predecessor when doing early break vect.
3056 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3057 after labels.
3059 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3061 PR tree-optimization/113731
3062 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3063 method.
3064 * gimple-iterator.h (gsi_move_before): Default new param to
3065 GSI_SAME_STMT.
3066 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3067 GSI_NEW_STMT.
3069 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3071 PR tree-optimization/113756
3072 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3073 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3074 of lh_bits value and mask.
3076 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3078 PR tree-optimization/113753
3079 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3080 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
3081 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3082 so that they start with r[half_blocks_needed] lowest bit. Fix up
3083 computation of top mask for SIGNED.
3085 2024-02-07 Pan Li <pan2.li@intel.com>
3087 PR target/113766
3088 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3089 the signature of func.
3090 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3091 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3092 overloaded func with empty args error.
3094 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
3096 PR target/113689
3097 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3098 R10_REG after sorry.
3100 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
3102 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3103 Move before new caller, and add ".default" suffix.
3104 (get_suffixed_assembler_name): New.
3105 (make_resolver_func): Use get_suffixed_assembler_name.
3106 (aarch64_generate_version_dispatcher_body): Redo name mangling.
3108 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3110 PR target/113763
3111 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3112 element from std::pair<unsigned int, char> to an unnamed struct.
3113 Adjust uses of tile range variable.
3115 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3117 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3118 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3120 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3122 PR sanitizer/110676
3123 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3124 reset maxlen to sizetype maximum.
3126 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3128 PR tree-optimization/113736
3129 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3130 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3132 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3134 PR tree-optimization/113759
3135 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3136 or from_unsignedN differs from properties of typeN, update typeN
3137 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
3138 uselessly convertible to typeN, convert it using fold_convert or
3139 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3140 (convert_plusminus_to_widen): Likewise.
3142 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
3144 PR target/112577
3145 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3146 vector structure modes correctly.
3148 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
3150 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3151 warning.
3153 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
3155 PR target/113689
3156 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3157 (x86_function_profiler): Call x86_64_select_profile_regnum to
3158 get a scratch register for large model profiling.
3160 2024-02-05 Richard Ball <richard.ball@arm.com>
3162 * config/arm/arm.cc (arm_output_mi_thunk): Emit
3163 insn for bti_c when bti is enabled.
3165 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3167 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3168 neg.
3170 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3172 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3173 (neg<mode>2): Change the mode iterator from MSA to IMSA because
3174 in FP arithmetic we cannot use (0 - x) for -x.
3175 (neg<mode>2): New define_insn to implement FP vector negation,
3176 using a bnegi instruction to negate the sign bit.
3178 2024-02-05 Richard Biener <rguenther@suse.de>
3180 PR tree-optimization/113707
3181 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3182 checking the avail set treat out-of-region defines as
3183 available.
3185 2024-02-05 Richard Biener <rguenther@suse.de>
3187 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3188 the default mode when building a pointer.
3190 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3192 PR tree-optimization/113737
3193 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3194 has just a single label, remove it and make single successor edge
3195 EDGE_FALLTHRU.
3197 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3199 PR target/113059
3200 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3201 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3202 df_analyze call.
3204 2024-02-05 Richard Biener <rguenther@suse.de>
3206 PR target/113255
3207 * config/i386/i386-expand.cc
3208 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3209 Use a new pseudo for the skipped number of bytes.
3211 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3213 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3214 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3215 sifive-p670.
3217 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3219 * config/riscv/riscv.md: Include sifive-p400.md.
3220 * config/riscv/sifive-p400.md: New file.
3221 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3222 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3223 Add sifive_p400.
3224 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3225 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3226 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3228 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3230 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3231 Add missing ":SI" to the match_operator.
3233 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3235 * config/xtensa/xtensa.md (SHI): New mode iterator.
3236 (2 split patterns related to constsynth):
3237 Change to also accept HImode operands.
3239 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
3241 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3242 similarly.
3244 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3246 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3247 incorrect expand.
3248 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3249 (elmsgnbit): Likewise.
3250 (neg<mode:FVEC>2): New define_insn.
3251 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3252 are now instantiated in simd.md.
3254 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3256 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3257 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3258 MAX_MACHINE_MODE.
3260 2024-02-04 Li Wei <liwei@loongson.cn>
3262 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3263 (loongarch_expand_vselect_vconcat): Ditto.
3264 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3265 all 128-bit constant permutation situations.
3266 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3267 (loongarch_is_imm_set_shuffle): Renamed function name.
3268 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3269 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3270 extract-even and extract-odd permutations.
3271 (loongarch_is_odd_extraction): Delete.
3272 (loongarch_is_even_extraction): Ditto.
3273 (loongarch_expand_vec_perm_const): Adjust.
3275 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3277 PR middle-end/113722
3278 * wide-int.cc (wi::bswap_large): Rename third argument from
3279 len to xlen and adjust use in safe_uhwi. Add len variable, set
3280 it to BLOCKS_NEEDED (precision) and use it for clearing of val
3281 and as canonize argument. Clear val using memset instead of
3282 a loop.
3284 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3286 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3287 mmi.preferred_base + mmi.size - sizeof (void *).
3289 2024-02-03 Xi Ruoyao <xry111@xry111.site>
3291 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3292 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3293 the ODR-violating locale declaration.
3295 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3297 PR tree-optimization/113588
3298 PR tree-optimization/113467
3299 * tree-vect-data-refs.cc
3300 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
3301 (vect_analyze_early_break_dependences): Update comments.
3303 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
3305 PR target/59778
3306 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3307 and PA_BUILTIN_SET_FPSR builtins.
3308 * (pa_builtins_icode): Declare.
3309 * (def_builtin, pa_fpu_init_builtins): New.
3310 * (pa_init_builtins): Initialize FPU builtins.
3311 * (pa_builtin_decl, pa_expand_builtin_1): New.
3312 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3313 PA_BUILTIN_SET_FPSR builtins.
3314 * (pa_atomic_assign_expand_fenv): New.
3315 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3316 UNSPECV constants.
3317 (get_fpsr, put_fpsr): New expanders.
3318 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3319 insn patterns.
3321 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3323 PR target/113697
3324 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3326 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
3328 * doc/extend.texi (Common Type Attributes): Fix typo in
3329 description of hardbool.
3331 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3333 PR tree-optimization/113692
3334 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3335 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3336 final_cast_p.
3338 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3340 PR middle-end/113699
3341 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3342 uninitialized large/huge _BitInt SSA_NAME inputs.
3344 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3346 PR middle-end/113705
3347 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3348 around wi::to_wide in order to compare value in prec precision.
3350 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
3352 Revert:
3353 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3355 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3357 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3359 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3361 2024-02-02 Pan Li <pan2.li@intel.com>
3363 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3364 (riscv_pass_by_reference): Ditto.
3365 (riscv_fntype_abi): Ditto.
3367 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3369 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3370 (pre_vsetvl::cleaup): Remove vsetvl_pre.
3371 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3373 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
3375 * config/loongarch/larchintrin.h
3376 (__frecipe_s): Update function return type.
3377 (__frecipe_d): Ditto.
3378 (__frsqrte_s): Ditto.
3379 (__frsqrte_d): Ditto.
3381 2024-02-02 Li Wei <liwei@loongson.cn>
3383 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3384 (loongarch_vector_costs::add_stmt_cost): Adjust.
3386 2024-02-02 Xi Ruoyao <xry111@xry111.site>
3388 * config/loongarch/loongarch.md (unspec): Add
3389 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3390 (la_pcrel64_two_parts): New define_insn.
3391 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3392 typo in the comment.
3393 (loongarch_call_tls_get_addr): If -mcmodel=extreme
3394 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3395 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
3396 note to allow CSE addressing __tls_get_addr.
3397 (loongarch_legitimize_tls_address): If -mcmodel=extreme
3398 -mexplicit-relocs={always,auto}, address TLS IE symbols with
3399 la_pcrel64_two_parts.
3400 (loongarch_split_symbol): If -mcmodel=extreme
3401 -mexplicit-relocs={always,auto}, address symbols with
3402 la_pcrel64_two_parts.
3403 (loongarch_output_mi_thunk): Clean up unreachable code. If
3404 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3405 thunks with la_pcrel64_two_parts.
3407 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3409 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3410 Add support for call36.
3412 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3414 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3415 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3416 the macro instruction loading symbol address is not applicable.
3417 (loongarch_call_tls_get_addr): Adjust code.
3418 (loongarch_legitimize_tls_address): Likewise.
3420 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3422 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3423 Add function declaration.
3424 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3425 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3426 is not allowed
3427 (loongarch_load_tls): Added macro support in extreme mode.
3428 (loongarch_call_tls_get_addr): Likewise.
3429 (loongarch_legitimize_tls_address): Likewise.
3430 (loongarch_force_address): Likewise.
3431 (loongarch_legitimize_move): Likewise.
3432 (loongarch_output_mi_thunk): Likewise.
3433 (loongarch_option_override_internal): Remove the code that detects
3434 explicit relocs status.
3435 (loongarch_handle_model_attribute): Likewise.
3436 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3437 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3438 (symbolic_off64_or_reg_operand): Likewise.
3440 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3442 * config/loongarch/loongarch.cc (loongarch_load_tls):
3443 Load all types of tls symbols through one function.
3444 (loongarch_got_load_tls_gd): Delete.
3445 (loongarch_got_load_tls_ld): Delete.
3446 (loongarch_got_load_tls_ie): Delete.
3447 (loongarch_got_load_tls_le): Delete.
3448 (loongarch_call_tls_get_addr): Modify the called function name.
3449 (loongarch_legitimize_tls_address): Likewise.
3450 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3451 (@load_tls<mode>): New template.
3452 (@got_load_tls_ld<mode>): Delete.
3453 (@got_load_tls_le<mode>): Delete.
3454 (@got_load_tls_ie<mode>): Delete.
3456 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3458 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3459 (loongarch_legitimize_address): Add logical transformation code.
3461 2024-02-01 Marek Polacek <polacek@redhat.com>
3463 * doc/invoke.texi: Update -Wdangling-reference documentation.
3465 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
3467 PR target/113701
3468 * config/i386/i386.md (*cmp<dwi>_doubleword):
3469 Do not force SUBREG pieces to pseudos.
3471 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
3473 * config/pa/pa.md (atomic_storedi_1): Fix bug in
3474 alternative 1.
3476 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
3478 * config/avr/avr.cc: Tabify.
3480 2024-02-01 Richard Ball <richard.ball@arm.com>
3482 PR tree-optimization/111268
3483 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
3484 Add variable-length check for vector input arguments
3485 to a function.
3487 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3489 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
3490 hard-code number of SGPR/VGPR/AVGPR registers.
3491 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
3492 SGPR/VGPR/AVGPR registers.
3494 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3496 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
3497 attribute, and include sifive-p600.md.
3498 * config/riscv/generic-ooo.md: Update type attribute.
3499 * config/riscv/generic.md: Update type attribute.
3500 * config/riscv/sifive-7.md: Update type attribute.
3501 * config/riscv/sifive-p600.md: New file.
3502 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3503 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3504 Add sifive_p600.
3505 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3506 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3507 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3509 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3511 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3512 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3513 * config/riscv/riscv.opt: New macro for 7 new unprivileged
3514 extensions.
3515 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3516 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3518 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3520 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3521 -static-libasan. Add missing whitespace.
3523 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3525 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3526 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3527 Don't 'define_constants'.
3529 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3531 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3533 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3535 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3536 [TARGET_RDNA3]: Adjust.
3538 2024-02-01 Richard Biener <rguenther@suse.de>
3540 PR tree-optimization/113693
3541 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3542 data when available.
3544 2024-02-01 Jakub Jelinek <jakub@redhat.com>
3545 Jason Merrill <jason@redhat.com>
3547 PR c++/113531
3548 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
3549 on variables which were promoted to TREE_STATIC.
3551 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
3552 Richard Biener <rguenther@suse.de>
3554 PR target/113560
3555 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
3556 information via tree_non_zero_bits to check if this operand
3557 is suitably extended for a widening (or highpart) multiplication.
3558 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
3559 isn't already of the claimed type.
3561 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3563 Revert:
3564 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3566 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3567 (generic_ooo_branch): ditto
3568 * config/riscv/generic.md (generic_sfb_alu): ditto
3569 (generic_fmul_half): ditto
3570 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3571 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3572 (sifive_7_popcount): ditto
3573 * config/riscv/vector.md: change rdfrm to fmove
3574 * config/riscv/zc.md: change pushpop to load/store
3576 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3578 Revert:
3579 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3580 Robin Dapp <rdapp.gcc@gmail.com>
3582 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3583 (generic_ooo_vec_load): ditto
3584 (generic_ooo_vec_store): ditto
3585 (generic_ooo_vec_loadstore_seg): ditto
3586 (generic_ooo_vec_alu): ditto
3587 (generic_ooo_vec_fcmp): ditto
3588 (generic_ooo_vec_imul): ditto
3589 (generic_ooo_vec_fadd): ditto
3590 (generic_ooo_vec_fmul): ditto
3591 (generic_ooo_crypto): ditto
3592 (generic_ooo_perm): ditto
3593 (generic_ooo_vec_reduction): ditto
3594 (generic_ooo_vec_ordered_reduction): ditto
3595 (generic_ooo_vec_idiv): ditto
3596 (generic_ooo_vec_float_divsqrt): ditto
3597 (generic_ooo_vec_mask): ditto
3598 (generic_ooo_vec_vesetvl): ditto
3599 (generic_ooo_vec_setrm): ditto
3600 (generic_ooo_vec_readlen): ditto
3601 * config/riscv/riscv.md: include generic-vector-ooo
3602 * config/riscv/generic-vector-ooo.md: New file. to here
3604 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3606 Revert:
3607 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3609 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3611 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3613 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3615 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3616 Robin Dapp <rdapp.gcc@gmail.com>
3618 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3619 (generic_ooo_vec_load): ditto
3620 (generic_ooo_vec_store): ditto
3621 (generic_ooo_vec_loadstore_seg): ditto
3622 (generic_ooo_vec_alu): ditto
3623 (generic_ooo_vec_fcmp): ditto
3624 (generic_ooo_vec_imul): ditto
3625 (generic_ooo_vec_fadd): ditto
3626 (generic_ooo_vec_fmul): ditto
3627 (generic_ooo_crypto): ditto
3628 (generic_ooo_perm): ditto
3629 (generic_ooo_vec_reduction): ditto
3630 (generic_ooo_vec_ordered_reduction): ditto
3631 (generic_ooo_vec_idiv): ditto
3632 (generic_ooo_vec_float_divsqrt): ditto
3633 (generic_ooo_vec_mask): ditto
3634 (generic_ooo_vec_vesetvl): ditto
3635 (generic_ooo_vec_setrm): ditto
3636 (generic_ooo_vec_readlen): ditto
3637 * config/riscv/riscv.md: include generic-vector-ooo
3638 * config/riscv/generic-vector-ooo.md: New file. to here
3640 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3642 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3643 (generic_ooo_branch): ditto
3644 * config/riscv/generic.md (generic_sfb_alu): ditto
3645 (generic_fmul_half): ditto
3646 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3647 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3648 (sifive_7_popcount): ditto
3649 * config/riscv/vector.md: change rdfrm to fmove
3650 * config/riscv/zc.md: change pushpop to load/store
3652 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
3654 PR target/113657
3655 * config/aarch64/aarch64-simd.md (split for movv8di):
3656 For strict aligned mode, use DImode instead of TImode.
3658 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
3660 PR middle-end/113607
3661 * match.pd: Make sure else values match when folding a
3662 vec_cond into a conditional operation.
3664 2024-01-31 Marek Polacek <polacek@redhat.com>
3666 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
3668 2024-01-31 Tamar Christina <tamar.christina@arm.com>
3669 Matthew Malcomson <matthew.malcomson@arm.com>
3671 PR sanitizer/112644
3672 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
3673 memcmp.
3674 * builtins.cc (expand_builtin): Include HWASAN when checking for
3675 builtin inlining.
3677 2024-01-31 Richard Biener <rguenther@suse.de>
3679 PR middle-end/110176
3680 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
3681 to match INTEGER_CST only without outstanding conversion.
3683 2024-01-31 Alex Coplan <alex.coplan@arm.com>
3685 PR target/111677
3686 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
3687 V16QImode for the full 16-byte FPR saves in the vector PCS case.
3689 2024-01-31 Richard Biener <rguenther@suse.de>
3691 PR tree-optimization/111444
3692 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
3693 vn_reference_lookup_2 when optimistically skipping may-defs.
3695 2024-01-31 Richard Biener <rguenther@suse.de>
3697 PR tree-optimization/113630
3698 * tree-ssa-pre.cc (compute_avail): Avoid registering a
3699 reference with a representation with not matching base
3700 access size.
3702 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3704 PR rtl-optimization/113656
3705 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
3706 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
3708 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3710 PR debug/113637
3711 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
3712 with BLKmode are larger than DWARF2_ADDR_SIZE.
3714 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3716 PR tree-optimization/113639
3717 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3718 For VIEW_CONVERT_EXPR set rhs1 to its operand.
3720 2024-01-31 Richard Biener <rguenther@suse.de>
3722 PR tree-optimization/113670
3723 * tree-vect-data-refs.cc (vect_check_gather_scatter):
3724 Make sure we can take the address of the reference base.
3726 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
3728 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
3729 ATA5835, ATtiny64AUTO, ATA5700M322.
3730 * doc/avr-mmcu.texi: Rebuild.
3732 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3734 PR debug/113394
3735 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
3736 caller.
3738 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3740 PR middle-end/112917
3741 PR middle-end/113100
3742 * builtins.cc (expand_builtin_stack_address): Use
3743 STACK_ADDRESS_OFFSET.
3744 * doc/extend.texi (__builtin_stack_address): Adjust.
3745 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
3746 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
3747 * doc/tm.texi: Rebuilt.
3749 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3751 PR target/113495
3752 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
3753 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
3754 (pre_vsetvl::compute_transparent): New function.
3755 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
3757 2024-01-30 Fangrui Song <maskray@google.com>
3759 PR target/105576
3760 * config/i386/constraints.md: Define constraint "Ws".
3761 * doc/md.texi: Document it.
3763 2024-01-30 Marek Polacek <polacek@redhat.com>
3765 PR c++/110358
3766 PR c++/109640
3767 * doc/invoke.texi: Update -Wdangling-reference description.
3769 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3771 * config/xtensa/constraints.md (R, T, U):
3772 Change define_constraint to define_memory_constraint.
3773 * config/xtensa/predicates.md (move_operand): Don't check that a
3774 constant pool operand size is a multiple of UNITS_PER_WORD.
3775 * config/xtensa/xtensa.cc
3776 (xtensa_lra_p, TARGET_LRA_P): Remove.
3777 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
3778 clause as it can no longer be true.
3779 (fixup_subreg_mem): Drop function.
3780 (xtensa_output_integer_literal_parts): Consider 16-bit wide
3781 constants.
3782 (xtensa_legitimate_constant_p): Add short-circuit path for
3783 integer load instructions. Don't check that mode size is
3784 at least UNITS_PER_WORD.
3785 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
3786 rather reload_in_progress and reload_completed.
3787 (doloop_end): Drop operand 2.
3788 (movhi_internal): Add alternative loading constant from a
3789 literal pool.
3790 (define_split for DI register_operand): Don't limit to
3791 !TARGET_AUTO_LITPOOLS.
3792 * config/xtensa/xtensa.opt (mlra): Change to no effect.
3794 2024-01-30 Pan Li <pan2.li@intel.com>
3796 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
3797 calculate the gpr count required by vls mode.
3798 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
3799 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
3800 for vls mode.
3801 (riscv_get_arg_info): Add vls mode handling.
3802 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
3804 2024-01-30 Richard Biener <rguenther@suse.de>
3806 PR tree-optimization/113659
3807 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3808 Handle main exit without virtual use.
3810 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
3812 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
3814 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
3816 PR libgcc/113403
3817 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
3818 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
3819 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
3820 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
3821 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
3822 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
3824 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3826 PR target/113623
3827 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
3828 Mark all registers that occur in addresses as needing a GPR.
3830 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3832 PR target/113636
3833 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
3834 the containing insn as an extra parameter. Reset debug instructions
3835 if they reference a register that is no longer used by real insns.
3836 (early_ra::apply_allocation): Update calls accordingly.
3838 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3840 PR tree-optimization/113603
3841 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
3842 count_nonzero_bytes call refetch si using get_strinfo in case it
3843 has been unshared in the meantime.
3845 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3847 PR middle-end/101195
3848 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
3849 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
3851 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
3853 * config/riscv/thead.cc (th_print_operand_address): Change %ld
3854 to %lld.
3856 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
3857 Manolis Tsamis <manolis.tsamis@vrull.eu>
3858 Philipp Tomsich <philipp.tomsich@vrull.eu>
3860 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
3861 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
3862 Likewise.
3863 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
3864 Call on framework moved later.
3866 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
3868 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
3869 instruction in naked function epilogues.
3871 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
3873 PR target/113655
3874 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
3875 gcc_cv_as_mips_explicit_relocs.
3876 * configure: Regnerated.
3878 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
3880 PR target/108933
3881 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
3882 Correct generated RTL.
3883 (arm_rev16si2_alt1): Correctly handle conditional execution.
3884 (arm_rev16si2_alt2): Likewise.
3886 2024-01-29 Richard Biener <rguenther@suse.de>
3888 PR middle-end/113622
3889 * expr.cc (expand_assignment): Spill hard registers if
3890 we index them with a variable offset.
3892 2024-01-29 Richard Biener <rguenther@suse.de>
3894 PR middle-end/113622
3895 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
3896 Also allow DECL_HARD_REGISTER variables.
3898 2024-01-29 Alex Coplan <alex.coplan@arm.com>
3900 PR target/113616
3901 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
3902 Use iterate_safely when iterating over debug uses.
3903 (fixup_debug_uses): Likewise.
3904 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
3905 over nondebug insns instead of manually maintaining the next insn.
3906 * iterator-utils.h (class safe_iterator): New.
3907 (iterate_safely): New.
3909 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
3911 PR target/38534
3912 * config/i386/i386-options.cc (ix86_set_func_type): Save
3913 callee-saved registers in noreturn functions for -O0/-Og.
3915 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3917 PR target/113615
3918 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
3919 define for !TARGET_RDNA2_PLUS.
3921 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
3923 PR target/113281
3924 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
3925 workaround for right shifts.
3926 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
3927 (vect_determine_precisions_from_range): Be more selective about
3928 which codes can be narrowed based on their input and output ranges.
3929 For shifts, require at least one more bit of precision than the
3930 maximum shift amount.
3932 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3934 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
3936 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3938 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
3939 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
3940 LLVM 13.0.1+.
3942 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3944 PR other/111966
3945 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
3946 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
3947 (SET_SRAM_ECC_UNSET): ... this.
3948 (copy_early_debug_info): Remove gfx900 special case, now handled as
3949 part of the generic handling.
3950 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
3952 2024-01-29 Jakub Jelinek <jakub@redhat.com>
3954 PR tree-optimization/110603
3955 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
3956 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
3957 overwritten anyway). Avoid creating invalid range with minlen
3958 larger than maxlen. Formatting fix.
3960 2024-01-29 Richard Biener <rguenther@suse.de>
3962 PR debug/103047
3963 * tree-inline.cc (initialize_inlined_parameters): Reverse
3964 the decl chain of inlined parameters.
3966 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3968 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
3969 alignment of CFString constants by setting DECL_USER_ALIGN.
3971 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3972 Jakub Jelinek <jakub@redhat.com>
3974 PR libgcc/113402
3975 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
3976 and BUILT_IN_GCC_NESTED_PTR_DELETED.
3977 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
3978 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
3979 rename the library fallbacks to __gcc_nested_func_ptr_created and
3980 __gcc_nested_func_ptr_deleted.
3981 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
3982 and __gcc_nested_func_ptr_deleted.
3983 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
3984 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
3985 * tree.cc (build_common_builtin_nodes): Build the
3986 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
3987 builtins only for non-explicit.
3989 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
3991 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
3993 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3995 PR target/38534
3996 * config/i386/i386-options.cc (ix86_set_func_type): Don't
3997 save and restore callee saved registers for a noreturn function
3998 with nothrow or compiled with -fno-exceptions.
4000 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4002 PR target/103503
4003 PR target/113312
4004 * config/i386/i386-expand.cc (ix86_expand_call): Replace
4005 no_caller_saved_registers check with call_saved_registers check.
4006 Clobber all registers that are not used by the callee with
4007 no_callee_saved_registers attribute.
4008 * config/i386/i386-options.cc (ix86_set_func_type): Set
4009 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4010 noreturn function. Disallow no_callee_saved_registers with
4011 interrupt or no_caller_saved_registers attributes together.
4012 (ix86_set_current_function): Replace no_caller_saved_registers
4013 check with call_saved_registers check.
4014 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4015 (ix86_handle_call_saved_registers_attribute): This.
4016 (ix86_gnu_attributes): Add
4017 ix86_handle_call_saved_registers_attribute.
4018 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4019 no_caller_saved_registers check with call_saved_registers check.
4020 (ix86_function_ok_for_sibcall): Don't allow callee with
4021 no_callee_saved_registers attribute when the calling function
4022 has callee-saved registers.
4023 (ix86_comp_type_attributes): Also check
4024 no_callee_saved_registers.
4025 (ix86_epilogue_uses): Replace no_caller_saved_registers check
4026 with call_saved_registers check.
4027 (ix86_hard_regno_scratch_ok): Likewise.
4028 (ix86_save_reg): Replace no_caller_saved_registers check with
4029 call_saved_registers check. Don't save any registers for
4030 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
4031 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4032 no_callee_saved_registers attribute is called.
4033 (find_drap_reg): Replace no_caller_saved_registers check with
4034 call_saved_registers check.
4035 * config/i386/i386.h (call_saved_registers_type): New enum.
4036 (machine_function): Replace no_caller_saved_registers with
4037 call_saved_registers.
4038 * doc/extend.texi: Document no_callee_saved_registers attribute.
4040 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4042 PR tree-optimization/113614
4043 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4044 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4045 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4047 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4049 PR tree-optimization/113568
4050 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4051 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4052 in the widening extension checks.
4054 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4056 * gimple-lower-bitint.cc (gimple_lower_bitint): For
4057 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4059 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
4061 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4062 the warning for an attribute-always_inline without inline declaration.
4064 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
4066 PR other/113575
4067 * genopinit.cc (main): Split init_all_optabs into functions
4068 of 1000 patterns each.
4070 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4072 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4073 TM_MULTILIB_CONFIG.
4074 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4075 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4076 -march/-mtune.
4078 2024-01-26 Andrew Stubbs <ams@baylibre.com>
4080 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4081 * config/gcn/gcn-valu.md (all_convert): New iterator.
4082 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4083 define_expand, and rename the old one to ...
4084 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4085 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4086 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4087 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4088 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4089 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4090 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4091 (<u>mulqihi3_scalar): Likewise.
4093 2024-01-26 Richard Biener <rguenther@suse.de>
4095 PR tree-optimization/113602
4096 * tree-data-ref.cc (dr_analyze_innermost): Fail when
4097 the base object isn't addressable.
4099 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4101 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4102 "--amdhsa-code-object-version=" argument.
4103 (ASM_SPEC): Use it; replace previous version of it.
4105 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4107 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4108 (pre_vsetvl::emit_vsetvl): Ditto.
4110 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4112 * config/loongarch/lasx.md (vec_extract<mode>_0):
4113 New define_insn_and_split patten.
4115 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4117 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4119 2024-01-26 Li Wei <liwei@loongson.cn>
4121 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4123 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4125 PR target/113469
4126 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4128 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
4130 PR target/100212
4131 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4132 undefined shift after the call to exact_log2.
4134 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
4136 PR target/100204
4137 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4138 before taking the negative of it.
4140 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
4142 PR target/113526
4143 * lra-constraints.cc (curr_insn_transform): Change class even for
4144 spilled pseudo successfully matched with with NO_REGS.
4146 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
4148 PR target/113601
4149 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4151 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
4153 PR target/112987
4154 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4155 (aarch64_expand_epilogue): Use the new function.
4156 (aarch64_split_compare_and_swap): Likewise.
4157 (aarch64_split_atomic_op): Likewise.
4159 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
4161 PR middle-end/112971
4162 * fold-const.cc (simplify_const_binop): New function for binop
4163 simplification of two constant vectors when element-wise
4164 handling is not necessary.
4165 (const_binop): Call new function.
4167 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
4169 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4170 * config/riscv/constraints.md: Likewise.
4171 * config/riscv/corev.def: Likewise.
4172 * config/riscv/corev.md: Likewise.
4173 * config/riscv/predicates.md: Likewise.
4174 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4175 * config/riscv/riscv-ftypes.def: Likewise.
4176 * config/riscv/riscv.opt: Likewise.
4177 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4178 * doc/extend.texi: Add XCVbitmanip builtin documentation.
4179 * doc/sourcebuild.texi: Likewise.
4181 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
4183 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4185 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
4187 PR target/113538
4188 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4189 (riscv_fntype_abi): Ditto.
4190 * config/riscv/riscv.opt: Ditto.
4192 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4194 PR middle-end/113574
4195 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4196 count against TYPE_PRECISION rather than TYPE_SIZE.
4198 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4200 PR target/113572
4201 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4202 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4204 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4206 PR target/113550
4207 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4208 whether each split instruction is a load that clobbers the source
4209 address. Emit that instruction last if so.
4211 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4213 PR target/113485
4214 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4215 pattern.
4216 (<optab><Vnarrowq><mode>2): Use it instead of generating a
4217 paradoxical subreg for the input.
4219 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4221 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4222 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4223 predecessors dump information.
4225 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4227 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4228 redundant full available computation.
4229 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4231 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4233 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4234 * doc/rtl.texi (CONST_VECTOR): Likewise.
4236 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4238 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4239 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4240 (pass_vsetvl::execute): Ditto.
4241 * config/riscv/riscv.opt: Ditto.
4243 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
4245 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4246 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4248 2024-01-25 Richard Biener <rguenther@suse.de>
4250 PR tree-optimization/113576
4251 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4252 exits with may_be_zero niters when its the last one.
4254 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
4256 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4257 For symbols of type tls, non-zero Offset is not generated.
4259 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
4261 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4262 P9 with m32 and mpowerpc64.
4264 2024-01-25 liuhongt <hongtao.liu@intel.com>
4266 * config/i386/i386-options.cc (ix86_option_override_internal):
4267 Enable -mlam=u57 by default when compiled with
4268 -fsanitize=hwaddress.
4270 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
4272 * common/config/riscv/riscv-common.cc (riscv_implied_info):
4273 Remove {"ztso", "a"}.
4275 2024-01-24 Martin Jambor <mjambor@suse.cz>
4277 PR ipa/108007
4278 PR ipa/112616
4279 * cgraph.h (cgraph_edge): Add a parameter to
4280 redirect_call_stmt_to_callee.
4281 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4282 parameter to modify_call.
4283 (ipa_release_ssas_in_hash): Declare.
4284 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4285 parameter killed_ssas, pass it to padjs->modify_call.
4286 * ipa-param-manipulation.cc (purge_all_uses): New function.
4287 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4288 Instead of substituting uses, invoke purge_all_uses. If
4289 hash of killed SSAs has not been provided, create a temporary one
4290 and release SSAs that have been added to it.
4291 (compare_ssa_versions): New function.
4292 (ipa_release_ssas_in_hash): Likewise.
4293 * tree-inline.cc (redirect_all_calls): Create
4294 id->killed_new_ssa_names earlier, pass it to edge redirection,
4295 adjust a comment.
4296 (copy_body): Release SSAs in id->killed_new_ssa_names.
4298 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
4300 PR target/113486
4301 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4302 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4304 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
4306 PR target/113095
4307 * config/riscv/sfb.md: New splitters to rewrite single bit
4308 sign extension as the condition to SFB instructions.
4310 2024-01-24 Jan Hubicka <jh@suse.cz>
4312 PR middle-end/88345
4313 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4314 (fmin-function-alignment): New parameter.
4315 * doc/invoke.texi: (-fmin-function-alignment): Document.
4316 (-falign-functions,-falign-loops,-falign-labels): Mention that
4317 aglinments are ignored in cold code.
4318 * varasm.cc (assemble_start_function): Handle min-function-alignment.
4320 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4322 PR target/109636
4323 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4324 mulv2di3): Remove.
4325 * config/aarch64/iterators.md (VQDIV): Remove.
4326 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4327 SVE_I_SIMD_DI): New.
4328 (VPRED, sve_lane_con): Add V4SI and V2DI.
4329 * config/aarch64/aarch64-sve.md (<optab><mode>3,
4330 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4331 (mul<mode>3): New, split from <optab><mode>3.
4332 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4333 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4334 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4335 SVE_FULL_HSDI_SIMD_DI.
4337 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4339 PR tree-optimization/113552
4340 * config/aarch64/aarch64.cc
4341 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4343 2024-01-24 Martin Jambor <mjambor@suse.cz>
4345 PR ipa/113490
4346 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4347 count is equal or greater than the limit. Use the limit from the
4348 callee.
4350 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
4352 * configure.ac: Detect the explicit relocs support for
4353 mips, and define C macro MIPS_EXPLICIT_RELOCS.
4354 * config.in: Regenerated.
4355 * configure: Regenerated.
4356 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4357 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4358 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4359 !TARGET_EXPLICIT_RELOCS instead of just set it.
4360 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4361 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4362 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4363 and define -m(no-)explicit-relocs as aliases.
4365 2024-01-24 Alex Coplan <alex.coplan@arm.com>
4367 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4368 to 1.
4369 (-mlate-ldp-fusion): Likewise.
4371 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4373 * tree-vect-loop.cc (vect_get_vect_def,
4374 vect_create_epilog_for_reduction): Rename main_exit_p to
4375 last_val_reduc_p.
4377 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4379 PR tree-optimization/113364
4380 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4381 early exits then we must reduce from the first offset for all of them.
4383 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4385 PR target/113495
4386 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4387 (get_regno): Ditto.
4388 (get_bb_index): Ditto.
4389 (pre_vsetvl::compute_avl_def_data): Ditto.
4390 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4391 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4393 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
4394 Richard Sandiford <richard.sandiford@arm.com>
4396 PR target/100942
4397 * ccmp.cc (ccmp_candidate_p): Add outer argument.
4398 Allow if the outer is true and the lhs is used more
4399 than once.
4400 (expand_ccmp_expr): Update call to ccmp_candidate_p.
4401 * expr.h (expand_expr_real_gassign): Declare.
4402 * expr.cc (expand_expr_real_gassign): New function, split out from...
4403 (expand_expr_real_1): ...here.
4404 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4406 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4408 PR target/113089
4409 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4410 (fixup_debug_use): New.
4411 (fixup_debug_uses_trailing_add): New.
4412 (fixup_debug_uses): New. Use it ...
4413 (ldp_bb_info::fuse_pair): ... here.
4414 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4415 fix up debug uses of the base register that are affected by
4416 folding in the trailing add insn.
4418 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4420 PR target/113089
4421 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4422 Update trailing nondebug uses of the base register in the case
4423 of cancelling writeback.
4425 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4427 PR target/113089
4428 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4429 (debug_insn_use_iterator): New.
4430 (set_info::first_debug_insn_use): New.
4431 (set_info::debug_insn_uses): New.
4432 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4433 (set_info::first_debug_insn_use): New.
4434 (set_info::debug_insn_uses): New.
4436 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4438 PR target/113356
4439 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4440 Don't record hazards against the opposite insn in the pair.
4442 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4444 PR target/113070
4445 * config/aarch64/aarch64-ldp-fusion.cc
4446 (struct stp_change_builder): New.
4447 (decide_stp_strategy): Reanme to ...
4448 (try_repurpose_store): ... this.
4449 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4450 construct stp changes. Fix up uses when inserting new stp insns.
4452 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4454 PR target/113070
4455 * rtl-ssa.h: Include hash-set.h.
4456 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4457 new_sets parameter and use it to keep track of new user-created sets.
4458 (function_info::apply_changes_to_insn): Also call add_def on new sets.
4459 (function_info::change_insns): Add hash_set to keep track of new
4460 user-created defs. Plumb it through.
4461 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4462 apply_changes_to_insn.
4464 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4466 PR target/113070
4467 * rtl-ssa/accesses.cc (function_info::create_use): New.
4468 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4469 Ensure new uses end up referring to permanent defs.
4470 * rtl-ssa/functions.h (function_info::create_use): Declare.
4472 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4474 PR target/113070
4475 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
4476 to finalize_new_accesses from the backwards placement loop, run it
4477 forwards in a separate loop.
4479 2024-01-23 Richard Biener <rguenther@suse.de>
4481 PR tree-optimization/113552
4482 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
4483 floor_log2 instead of exact_log2 on the number of calls.
4485 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
4486 Jakub Jelinek <jakub@redhat.com>
4488 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
4489 decl.
4491 2024-01-23 Richard Biener <rguenther@suse.de>
4493 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4494 Separate single and multi-exit case when creating PHIs between
4495 the main and epilogue.
4497 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
4499 PR target/112989
4500 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4501 MODE_single variants of functions that don't take tuple arguments.
4503 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4505 PR target/113114
4506 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4507 Don't assert recog success, just punt if the writeback pair
4508 isn't recognized.
4510 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4512 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4513 ATTRIBUTE_UNUSED to decl.
4515 2024-01-23 Richard Biener <rguenther@suse.de>
4517 PR debug/107058
4518 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4519 handle unexpected but bogus DIE contexts when not checking
4520 enabled.
4522 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4524 PR tree-optimization/113462
4525 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4526 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4527 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4528 sizes between 129 and 8192 bytes.
4530 2024-01-23 Xi Ruoyao <xry111@xry111.site>
4532 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4533 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4534 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4535 (loongarch_call_tls_get_addr): Do not split symbols of
4536 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4537 EXPLICIT_RELOCS_AUTO.
4539 2024-01-23 Richard Biener <rguenther@suse.de>
4541 * alias.cc (known_base_value_p): Remove.
4542 (find_base_value): Remove PLUS/MINUS handling
4543 when both operands are not CONST_INT_P.
4545 2024-01-23 Richard Biener <rguenther@suse.de>
4547 PR rtl-optimization/113255
4548 * alias.cc (find_base_term): Remove PLUS/MINUS handling
4549 when both operands are not CONST_INT_P.
4551 2024-01-23 Richard Biener <rguenther@suse.de>
4553 PR debug/112718
4554 * dwarf2out.cc (dwarf2out_finish): Reset all type units
4555 for the fat part of an LTO compile.
4557 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
4559 * doc/sourcebuild.texi: Add attributes for keywords.
4561 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
4563 PR c++/90463
4564 * doc/invoke.texi (Warning Options): Correct lists of options
4565 enabled by -Wall and -Wextra by checking against common.opt
4566 and c-family/c.opt.
4568 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
4570 PR target/113030
4571 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
4572 instead of cpu_optaliases.
4573 (check_arch): Use arch_opt_alias instead of arch_optaliases.
4575 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4577 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
4578 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
4579 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
4581 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4583 PR target/109092
4584 * config/riscv/riscv.md: Use reg instead of subreg.
4586 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
4588 PR other/111966
4589 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
4590 to match the compiler default.
4591 (simple_object_copy_lto_debug_sections): Never unlink the outfile
4592 on error as the caller does so.
4593 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
4594 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
4596 2024-01-22 Richard Biener <rguenther@suse.de>
4598 PR tree-optimization/113373
4599 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4600 Create LC PHIs in the exit blocks where necessary.
4601 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
4602 to handle missing LC PHIs.
4603 (find_connected_edge): Remove.
4604 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
4606 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4608 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
4610 2024-01-22 xuli <xuli1@eswincomputing.com>
4612 PR target/113420
4613 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
4614 (registered_function::overloaded_hash):refactor.
4615 (resolve_overloaded_builtin):avoid internal ICE.
4617 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
4619 PR target/82420
4620 PR target/111279
4621 * calls.cc (emit_library_call_value_1): Pass valid TYPE
4622 to emit_push_insn.
4623 * expr.cc (emit_push_insn): Likewise.
4625 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4627 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
4628 correcction version of last change.
4630 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4632 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
4633 fix bugs in signature.
4635 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
4636 Richard Biener <rguenther@suse.de>
4638 PR rtl-optimization/111267
4639 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
4640 profitable_p method to likely_profitable_p.
4641 (try_fwprop_subst_node): Update call to likely_profitable_p.
4642 Only bail-out early when !prop.likely_profitable_p for instructions
4643 that are not single sets. When comparing costs, bail-out if the
4644 cost is unchanged and !prop.likely_profitable_p.
4646 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4648 PR c++/90464
4649 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
4650 isn't enabled by -Wunused unless -Wextra is provided, and that
4651 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
4652 -Wunused doesn't enable -Wunused-* options documented as behaving
4653 otherwise, and list them explicitly.
4655 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4657 PR c/109708
4658 * doc/invoke.texi (Warning Options): Fix broken example and
4659 clean up/reorganize the others. Also describe what the short-form
4660 options mean.
4662 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
4664 PR c/102998
4665 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
4666 (Warning Options): Correct/edit discussion of -Warray-parameter
4667 to make the first example less confusing, and fill in missing info.
4669 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4671 PR tree-optimization/113462
4672 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
4673 Handle rhs1 INTEGER_CST like SSA_NAME.
4675 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4677 PR tree-optimization/113491
4678 * tree-switch-conversion.cc (switch_conversion::build_constructors):
4679 If elt.index has precision higher than sizetype, fold_convert it to
4680 sizetype.
4681 (switch_conversion::array_value_type): Return type if type is
4682 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
4683 (switch_conversion::build_arrays): Use unsigned_type_for rather than
4684 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
4685 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
4686 higher than sizetype, use sizetype as tidx type and fold_convert the
4687 subtraction to sizetype.
4689 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4691 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
4692 (riscv_vector_mode_supported_any_target_p): Ditto.
4694 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4696 PR target/110934
4697 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
4698 (TARGET_ZERO_CALL_USED_REGS): Define.
4700 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4702 PR target/108640
4703 * config/m68k/m68k.cc (output_andsi3): Use QImode for
4704 address adjusted for 1-byte RMW access.
4705 (output_iorsi3): Likewise.
4706 (output_xorsi3): Likewise.
4708 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4710 * doc/invoke.texi (RISC-V Options): Add list of supported
4711 extensions.
4713 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4715 PR target/113495
4716 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
4717 (RVV_VUNDEF): Ditto.
4718 * config/riscv/riscv-vsetvl.cc: Add timevar.
4720 2024-01-19 Richard Biener <rguenther@suse.de>
4722 PR debug/113488
4723 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
4724 an early DIE but there should be, do not pretend there is.
4726 2024-01-19 Richard Biener <rguenther@suse.de>
4728 PR tree-optimization/113494
4729 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4730 Handle endless loop on exit. Handle re-allocated PHI.
4732 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4734 PR tree-optimization/113464
4735 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
4736 optimize loads into GIMPLE_ASM stmts.
4738 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4740 PR tree-optimization/113463
4741 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
4742 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
4743 lhs.
4745 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4747 PR tree-optimization/113459
4748 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
4749 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
4750 of SCALAR_INT_TYPE_MODE if type has BLKmode.
4751 (vn_reference_lookup_3): Likewise. Formatting fix.
4753 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4754 Richard Biener <rguenther@suse.de>
4756 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
4757 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
4758 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
4759 but adjust_address also for BLKmode mode and MEM op0.
4761 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
4763 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
4764 extensions.
4766 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4768 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
4770 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4772 * common/config/riscv/riscv-common.cc
4773 (riscv_subset_list::parse_std_ext): Remove.
4774 (riscv_subset_list::parse_multiletter_ext): Remove.
4775 * config/riscv/riscv-subset.h
4776 (riscv_subset_list::parse_std_ext): Remove.
4777 (riscv_subset_list::parse_multiletter_ext): Remove.
4779 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4781 * common/config/riscv/riscv-common.cc
4782 (riscv_subset_list::parse_single_std_ext): New parameter.
4783 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4784 (riscv_subset_list::parse_single_ext): Ditto.
4785 (riscv_subset_list::parse): Relax the order for the input of ISA
4786 string.
4787 * config/riscv/riscv-subset.h
4788 (riscv_subset_list::parse_single_std_ext): New parameter.
4789 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4790 (riscv_subset_list::parse_single_ext): Ditto.
4792 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4794 * common/config/riscv/riscv-common.cc
4795 (riscv_subset_list::parse_base_ext): New.
4796 (riscv_subset_list::parse): Extract part of logic into
4797 riscv_subset_list::parse_base_ext.
4798 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
4799 New.
4801 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4803 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
4804 sorry message.
4806 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
4808 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
4809 UNSPEC_CLMUL_VC.
4811 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
4813 PR c/110029
4814 * doc/extend.texi (Common Variable Attributes): Explain what
4815 happens when multiple variables with cleanups are in the same scope.
4817 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4819 PR ipa/108470
4820 * doc/extend.texi (Common Function Attributes): Document that
4821 noinline also disables some interprocedural optimizations and
4822 improve flow to the part about using inline asm instead to
4823 disable calls from being optimized away completely. Remove the
4824 sentence that says noipa is mainly for internal compiler testing.
4826 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
4828 PR tree-optimization/69807
4829 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
4831 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
4833 PR target/108521
4834 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
4835 from x86 Windows Options.
4837 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4839 PR c/107942
4840 * doc/extend.texi (C Extensions): Add new section to menu.
4841 (Function Attributes): Move dangling index entries to....
4842 (Const and Volatile Functions): New section.
4844 2024-01-18 David Malcolm <dmalcolm@redhat.com>
4846 PR middle-end/112684
4847 * toplev.cc (toplev::main): Don't ICE in
4848 -fdiagnostics-generate-patch when exiting after options,
4849 since no edit context will have been created.
4851 2024-01-18 Richard Biener <rguenther@suse.de>
4853 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
4854 operands vector.
4856 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4858 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
4859 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
4861 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4862 Jin Ma <jinma@linux.alibaba.com>
4863 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4864 Christoph Müllner <christoph.muellner@vrull.eu>
4866 * config/riscv/thead.cc
4867 (th_asm_output_opcode): Rewrite some instructions.
4869 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4870 Jin Ma <jinma@linux.alibaba.com>
4871 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4872 Christoph Müllner <christoph.muellner@vrull.eu>
4874 * config/riscv/riscv.md (none,thv,rvv): New attribute.
4875 (no,yes): Add an attribute to disable alternative
4876 for xtheadvector or RVV1.0.
4877 * config/riscv/vector.md:
4878 Disable alternatives that destination register overlaps
4879 source register group for xtheadvector.
4881 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4882 Jin Ma <jinma@linux.alibaba.com>
4883 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4884 Christoph Müllner <christoph.muellner@vrull.eu>
4886 * config/riscv/riscv-vector-builtins-bases.cc
4887 (class th_loadstore_width): Define new builtin bases.
4888 (class th_extract): Define new builtin bases.
4889 (BASE): Define new builtin bases.
4890 * config/riscv/riscv-vector-builtins-bases.h:
4891 Define new builtin class.
4892 * config/riscv/riscv-vector-builtins-shapes.cc
4893 (struct th_loadstore_width_def): Define new builtin shapes.
4894 (struct th_indexed_loadstore_width_def):
4895 Define new builtin shapes.
4896 (struct th_extract_def): Define new builtin shapes.
4897 (SHAPE): Define new builtin shapes.
4898 * config/riscv/riscv-vector-builtins-shapes.h:
4899 Define new builtin shapes.
4900 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
4901 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
4902 * config/riscv/riscv-vector-builtins.h
4903 (enum required_ext): Add new XTheadVector member.
4904 (struct function_group_info): Likewise.
4905 * config/riscv/t-riscv:
4906 Add thead-vector-builtins-functions.def
4907 * config/riscv/thead-vector.md
4908 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
4909 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
4910 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
4911 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
4912 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
4913 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
4914 (@pred_th_extract<mode>): Likewise.
4915 (*pred_th_extract<mode>): Likewise.
4916 * config/riscv/thead-vector-builtins-functions.def: New file.
4918 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4919 Jin Ma <jinma@linux.alibaba.com>
4920 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4921 Christoph Müllner <christoph.muellner@vrull.eu>
4923 * config.gcc: Add files for XTheadVector intrinsics.
4924 * config/riscv/autovec.md: Guard XTheadVector.
4925 * config/riscv/predicates.md: Disable immediate vl
4926 for XTheadVector.
4927 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
4928 Add pragma for XTheadVector.
4929 * config/riscv/riscv-string.cc (riscv_expand_block_move):
4930 Guard XTheadVector.
4931 * config/riscv/riscv-v.cc (vls_mode_valid_p):
4932 Avoid autovec.
4933 * config/riscv/riscv-vector-builtins-bases.cc:
4934 Do not normalize vsetvl instructions for XTheadVector.
4935 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
4936 New check type function.
4937 (build_one): Adjust for XTheadVector.
4938 * config/riscv/riscv-vector-switch.def (ENTRY):
4939 Disable fractional mode for the XTheadVector extension.
4940 (TUPLE_ENTRY): Likewise.
4941 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
4942 Guard XTheadVector.
4943 (riscv_preferred_simd_mode): Likewsie.
4944 (riscv_autovectorize_vector_modes): Likewise.
4945 (riscv_vector_mode_supported_any_target_p): Likewise.
4946 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
4947 * config/riscv/thead.cc (th_asm_output_opcode):
4948 Rewrite vsetvl instructions.
4949 * config/riscv/vector.md:
4950 Include thead-vector.md and change fractional LMUL
4951 into 1 for vbool.
4952 * config/riscv/riscv_th_vector.h: New file.
4953 * config/riscv/thead-vector.md: New file.
4955 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4956 Jin Ma <jinma@linux.alibaba.com>
4957 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4958 Christoph Müllner <christoph.muellner@vrull.eu>
4960 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
4961 Add new function to add assembler insn code prefix/suffix.
4962 (th_asm_output_opcode):
4963 Add Thead function to add assembler insn code prefix/suffix.
4964 * config/riscv/riscv.cc (riscv_asm_output_opcode):
4965 Implement function to add assembler insn code prefix/suffix.
4966 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
4967 Add new function to add assembler insn code prefix/suffix.
4968 * config/riscv/thead.cc (th_asm_output_opcode):
4969 Implement Thead function to add assembler insn code
4970 prefix/suffix.
4972 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4973 Jin Ma <jinma@linux.alibaba.com>
4974 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4975 Christoph Müllner <christoph.muellner@vrull.eu>
4977 * common/config/riscv/riscv-common.cc
4978 (riscv_subset_list::parse): Add new vendor extension.
4979 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
4980 Add test marco.
4981 * config/riscv/riscv.opt: Add new mask.
4983 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4985 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
4986 to be conditional on macosx-version-min.
4988 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4990 * config/darwin.cc (darwin_objc1_section): Use the correct
4991 meta-data version for constant strings.
4992 (machopic_select_section): Assert if we fail to handle CFString
4993 sections as Obejctive-C meta-data or drectly.
4995 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4997 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
4998 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
4999 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5000 versions when the object format is Mach-O.
5002 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5004 PR target/105522
5005 * config/darwin.cc (machopic_select_section): Handle C and C++
5006 CFStrings.
5007 (darwin_rename_builtins): Move this out of the CFString code.
5008 (darwin_libc_has_function): Likewise.
5009 (darwin_build_constant_cfstring): Create an anonymous var to
5010 hold each CFString.
5011 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5012 CFstrings.
5014 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5016 PR bootstrap/113445
5017 * haifa-sched.cc (dep_list_size): Make global.
5018 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5019 * sched-int.h (dep_list_size): Declare.
5021 2024-01-18 Martin Jambor <mjambor@suse.cz>
5023 PR tree-optimization/110422
5024 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5025 gotos.
5027 2024-01-18 Richard Biener <rguenther@suse.de>
5029 PR tree-optimization/113475
5030 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5031 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5032 (phi_analyzer::~phi_analyzer): Deallocate and free collected
5033 phi_grous.
5034 (phi_analyzer::process_phi): Record allocated phi_groups.
5036 2024-01-18 Richard Biener <rguenther@suse.de>
5038 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5039 storage for gvec_oprnds elements.
5041 2024-01-18 Richard Biener <rguenther@suse.de>
5043 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5044 prefer all later exits we can handle.
5045 (vect_analyze_loop_form): Free the allocated loop body.
5046 Adjust comments.
5048 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5050 * config/avr/avr-log.cc: Tabify.
5052 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5054 * config/riscv/autovec.md: Support vi variant.
5056 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5058 * config/avr/avr-devices.cc: Tabify.
5060 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5062 * config/avr/avr-c.cc: Tabify.
5064 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5066 * config/avr/driver-avr.cc: Tabify.
5068 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5070 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5072 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5074 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5076 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5078 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5079 minline-strcmp, minline-strncmp, minline-strlen,
5080 -param=riscv-vector-abi): Remove Bool keywords.
5082 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5084 PR target/113122
5085 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5086 support. Add missing space after , in emitted assembly in some
5087 cases. Formatting fixes.
5089 2024-01-18 Xi Ruoyao <xry111@xry111.site>
5091 * config/loongarch/loongarch.md (movsi_internal): Remove
5092 constraint z.
5094 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5096 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5097 in the diagnostic, and capitalize the device name.
5098 (print_mcu): Generate specs such that:
5099 <*check_rodata_in_ram>: New.
5100 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5101 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5102 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5104 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5106 PR other/113399
5107 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5108 Common and Optimization.
5110 2024-01-18 Richard Biener <rguenther@suse.de>
5112 PR tree-optimization/113431
5113 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5114 When there is an invariant load we might not preserve
5115 scalar order.
5117 2024-01-18 Richard Biener <rguenther@suse.de>
5119 PR tree-optimization/113374
5120 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5121 * tree-vect-loop.cc (move_early_exit_stmts): Update
5122 virtual LC PHIs.
5123 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5124 Refactor. Preserve virtual LC PHIs on all exits.
5126 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
5128 * config/loongarch/loongarch.cc (loongarch_split_symbol):
5129 Assign the '/u' attribute to the mem.
5131 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5133 PR middle-end/110847
5134 * doc/invoke.texi (Option Summary): Document negative forms of
5135 -Wtsan and -Wxor-used-as-pow.
5136 (Warning Options): Likewise.
5138 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5140 PR target/113429
5141 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5143 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5145 * doc/extend.texi (Common Function Attributes): Re-alphabetize
5146 the table.
5147 (Common Variable Attributes): Likewise.
5148 (Common Type Attributes): Likewise.
5150 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5152 PR middle-end/111659
5153 * doc/extend.texi (Common Variable Attributes): Fix long lines
5154 in documentation of strict_flex_array + other minor copy-editing.
5155 Add a cross-reference to -Wstrict-flex-arrays.
5156 * doc/invoke.texi (Option Summary): Fix whitespace in tables
5157 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5158 (C Dialect Options): Combine the docs for the two
5159 -fstrict-flex-arrays forms into a single entry. Note this option
5160 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
5161 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5162 Minor copy-editing. Add cross references to the strict_flex_array
5163 attribute and -fstrict-flex-arrays option. Add note that this
5164 option depends on -ftree-vrp.
5166 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
5168 PR target/113221
5169 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5170 only allow REG operands instead of allowing all.
5172 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5174 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5175 Remove redundant checks in else condition for readablity.
5176 (earliest_fuse_vsetvl_info) Print iteration count in debug
5177 prints.
5178 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5179 dump details in certain cases.
5181 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5183 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5184 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5185 * config/riscv/riscv-vsetvl.cc
5186 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5187 (pass_vsetvl::execute): Use vsetvl_strategy.
5189 2024-01-17 Jan Hubicka <jh@suse.cz>
5191 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5192 accidental hack reseting offset.
5194 2024-01-17 Jan Hubicka <jh@suse.cz>
5196 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5197 handling of X86_TUNE_AVOID_512FMA_CHAINS.
5199 2024-01-17 Jan Hubicka <jh@suse.cz>
5200 Jakub Jelinek <jakub@redhat.com>
5202 PR tree-optimization/110852
5203 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5204 binary operations
5205 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5206 PRED_COMBINED_VALUE_PREDICTIONS_PHI
5207 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5208 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5210 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5212 PR tree-optimization/113421
5213 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5214 comment.
5215 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5216 formatting. Start at vop rather than cvop even if stmt is a store
5217 and needs_operand_addr.
5219 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5221 PR middle-end/113410
5222 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5223 If access_nelts is integral with larger precision than sizetype,
5224 fold_convert it to sizetype.
5226 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5228 PR tree-optimization/113408
5229 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5230 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5231 to handle_cast.
5233 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5235 PR middle-end/113406
5236 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5237 regardless of whether is_gimple_reg_type (restype) or not.
5239 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5241 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5242 funcions -> functions, and use were instead of was.
5243 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5244 and guaranteee -> guarantee.
5245 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5247 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5249 PR middle-end/113409
5250 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5251 INTEGER_TYPE.
5252 (omp_extract_for_data): Use build_bitint_type rather than
5253 build_nonstandard_integer_type if either iter_type or loop->v type
5254 is BITINT_TYPE.
5255 * omp-expand.cc (expand_omp_for_generic,
5256 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5257 BITINT_TYPE like INTEGER_TYPE.
5259 2024-01-17 Richard Biener <rguenther@suse.de>
5261 PR tree-optimization/113371
5262 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5263 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5264 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5265 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5267 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5269 PR rtl-optimization/96388
5270 PR rtl-optimization/111554
5271 * sched-deps.cc (find_inc): Avoid exponential behavior.
5273 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5275 PR c/111693
5276 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5277 from C++ Language Options to Warning Options. Add entry for
5278 -Wuse-after-free.
5279 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5280 from here....
5281 (Warning Options): ...to here. Minor copy-editing to fix typo
5282 and grammar.
5284 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
5286 * config/mips/mips.cc (mips_compute_frame_info): If another
5287 register is used as global_pointer, mark $GP live false.
5289 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5291 PR target/112973
5292 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5293 give the section a light copy-editing pass.
5295 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5297 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5298 * config/aarch64/aarch64-tune.md: Regenerated.
5299 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5301 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5303 PR target/112573
5304 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5305 badly formed CONST expressions.
5307 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5309 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5311 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5313 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5314 * config/sparc/sync.md (membar_storeload): Turn into named insn
5315 and add GR712RC errata workaround.
5316 (membar_v8): Add GR712RC errata workaround.
5318 2024-01-16 Andreas Larsson <andreas@gaisler.com>
5320 * config/sparc/sync.md (*membar_storeload_leon3): Remove
5321 (*membar_storeload): Enable for LEON
5323 2024-01-16 Jakub Jelinek <jakub@redhat.com>
5325 PR tree-optimization/113372
5326 PR middle-end/90348
5327 PR middle-end/110115
5328 PR middle-end/111422
5329 * cfgexpand.cc (add_scope_conflicts_2): New function.
5330 (add_scope_conflicts_1): Use it.
5332 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
5334 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5335 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5336 * doc/avr-mmcu.texi: Regenerate.
5338 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
5340 PR tree-optimization/113091
5341 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5342 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5343 scalar use with new function.
5344 (vect_bb_slp_mark_live_stmts): New function as entry to existing
5345 overriden functions with same name.
5346 (vect_slp_analyze_operations): Call new entry function to mark
5347 live statements.
5349 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5351 PR target/113404
5352 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5353 for RVV in big-endian mode.
5355 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
5357 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5358 (riscv_pass_in_vector_p): Delete.
5359 (riscv_init_cumulative_args): Delete the checking.
5360 (riscv_get_arg_info): Delete the checking.
5361 (riscv_function_value): Delete the checking.
5362 * config/riscv/riscv.h: Delete the member for checking.
5364 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5366 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5368 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5370 * config.gcc: Include riscv_bitmanip.h.
5371 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5372 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5373 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5374 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5375 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5376 * config/riscv/riscv-ftypes.def (2): New ftypes.
5377 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5378 (RISCV_BUILTIN_NO_PREFIX): Likewise.
5379 * config/riscv/riscv_bitmanip.h: New file.
5381 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5383 * config.gcc: Include riscv_crypto.h.
5384 * config/riscv/riscv_crypto.h: New file.
5386 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
5388 PR middle-end/113354
5389 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5390 in the insn if the corresponding operand does not require hard
5391 register anymore.
5393 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5395 PR target/107201
5396 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5397 * config/avr/driver-avr.cc (avr_no_devlib): New function.
5398 (avr_devicespecs_file): Use it to remove -nodevicelib from the
5399 options for cores only.
5400 * config/avr/avr-arch.h (avr_get_parch): New prototype.
5401 * config/avr/avr-devices.cc (avr_get_parch): New function.
5403 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5405 PR target/113247
5406 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5407 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5408 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5410 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5412 PR target/113281
5413 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5414 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5415 * config/riscv/riscv-vector-costs.h: New function.
5417 2024-01-15 Richard Biener <rguenther@suse.de>
5419 PR tree-optimization/113385
5420 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5421 First redirect, then split the exit edge.
5423 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5425 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5426 Remove m_num_vector_iterations.
5427 * config/riscv/riscv-vector-costs.h: Ditto.
5429 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
5431 PR target/113156
5432 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5433 (-mbranch-cost): Set "Optimization" flag.
5435 2024-01-15 Jakub Jelinek <jakub@redhat.com>
5437 PR tree-optimization/113370
5438 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5439 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5440 set it to just prec % limb_prec.
5442 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5444 PR target/113393
5445 * config/riscv/vector.md: Fix ternary attributes.
5447 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
5449 PR target/112944
5450 * configure.ac [target=avr]: Check availability of emulations
5451 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5452 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5453 * configure: Regenerate.
5454 * config.in: Regenerate.
5455 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5456 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5457 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5458 * config/avr/avr-arch.h (enum avr_device_specific_features):
5459 Add AVR_ISA_FLMAP.
5460 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5461 AVR_ISA_FLMAP.
5462 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5463 (avr_set_core_architecture): Set avr_arch_index.
5464 (have_avrxmega2_flmap, have_avrxmega4_flmap)
5465 (have_avrxmega3_rodata_in_flash): Set new static const bool according
5466 to configure results.
5467 (avr_rodata_in_flash_p): New function using them.
5468 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5469 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5470 (avr_asm_named_section): Track avr_has_rodata_p.
5471 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5472 and not avr_rodata_in_flash_p ().
5473 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5474 (LINK_SPEC): Add %(link_rodata_in_ram).
5475 (LINK_ARCH_SPEC): Remove.
5476 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
5477 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
5478 const bool according to configure results.
5479 (diagnose_mrodata_in_ram): New function.
5480 (print_mcu): Generate specs with the following changes:
5481 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
5482 need to extend avr/specs.h each time we add a new bell or whistle.
5483 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
5484 -m[no-]rodata-in-ram.
5485 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
5486 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
5487 <*cpp>: Add %(cpp_rodata_in_ram).
5488 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
5489 requested.
5490 <*self_spec>: Add -mflmap or %<mflmap as needed.
5492 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
5494 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
5495 not the GPR iterator. Adjust pattern name and mode attribute
5496 accordingly.
5498 2024-01-13 Jakub Jelinek <jakub@redhat.com>
5500 PR tree-optimization/113361
5501 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5502 Fix up determination of the type for > limb_prec constants.
5504 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5506 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5507 Add web-link to the avr-gcc wiki.
5509 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5511 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5512 documentation for a version without argument, which is not supported.
5514 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5516 * config/arm/arm_neon.h
5517 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5518 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5519 (vld1_f16_x4, vld1_f32_x4): New.
5520 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5521 (vld1_bf16_x4): New.
5522 (vld1q_types_x4): Updated to use vld1q_x4
5523 from arm_neon_builtins.def
5524 * config/arm/arm_neon_builtins.def
5525 (vld1_x4): Updated entries.
5526 (vld1q_x4): New entries, but comes from the old vld1_x4
5527 * config/arm/neon.md
5528 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5530 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5532 * config/arm/arm_neon.h
5533 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5534 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5535 (vld1_f16_x3, vld1_f32_x3): New.
5536 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5537 (vld1_bf16_x3): New.
5538 (vld1q_types_x3): Updated to use vld1q_x3 from
5539 arm_neon_builtins.def
5540 * config/arm/arm_neon_builtins.def
5541 (vld1_x3): Updated entries.
5542 (vld1q_x3): New entries, but comes from the old vld1_x2
5543 * config/arm/neon.md
5544 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
5546 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5548 * config/arm/arm_neon.h
5549 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
5550 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
5551 (vld1_f16_x2, vld1_f32_x2): New.
5552 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
5553 (vld1_bf16_x2): New.
5554 (vld1q_types_x2): Updated to use vld1q_x2 from
5555 arm_neon_builtins.def
5556 * config/arm/arm_neon_builtins.def
5557 (vld1_x2): Updated entries.
5558 (vld1q_x2): New entries, but comes from the old vld1_x2
5559 * config/arm/neon.md
5560 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5561 neon_vld1_x2<mode>.
5563 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5565 * config/arm/arm_neon.h
5566 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
5567 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
5568 (vst1q_f16_x4, vst1q_f32_x4): New.
5569 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
5570 (vst1q_bf16_x4): New.
5571 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
5572 * config/arm/neon.md
5573 (neon_vst1q_x4<mode>): New.
5574 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
5575 * config/arm/unspecs.md
5576 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
5578 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5580 * config/arm/arm_neon.h
5581 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
5582 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
5583 (vst1q_f16_x3, vst1q_f32_x3): New.
5584 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
5585 (vst1q_bf16_x3): New.
5586 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
5587 * config/arm/neon.md
5588 (neon_vst1q_x3<mode>): New.
5589 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
5590 * config/arm/unspecs.md
5591 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
5593 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5595 * config/arm/arm_neon.h
5596 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
5597 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
5598 (vst1q_f16_x2, vst1q_f32_x2): New.
5599 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
5600 (vst1q_bf16_x2): New.
5601 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
5602 * config/arm/neon.md
5603 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5604 neon_vst1_x2<mode>.
5605 * config/arm/iterators.md
5606 (VMEMX2): New mode iterator.
5607 (VMEMX2_q): New mode attribute.
5609 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5611 * config/arm/arm_neon.h
5612 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
5613 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
5614 (vst1_f16_x4, vst1_f32_x4): New.
5615 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
5616 (vst1_bf16_x4): New.
5617 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
5618 * config/arm/neon.md (vst1_x4<mode>): New.
5620 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5622 * config/arm/arm_neon.h
5623 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
5624 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
5625 (vst1_f16_x3, vst1_f32_x3): New.
5626 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
5627 (vst1_bf16_x3): New.
5628 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
5629 * config/arm/neon.md (vst1_x3<mode>): New.
5631 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5633 * config/arm/arm_neon.h
5634 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
5635 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
5636 (vst1_f16_x2, vst1_f32_x2): New.
5637 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
5638 (vst1_bf16_x2): New.
5639 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
5640 * config/arm/neon.md (vst1_x2<mode>): New.
5642 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5644 * config/arm/arm_neon.h
5645 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
5646 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
5647 (vld1q_f16_x4, vld1q_f32_x4): New.
5648 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
5649 (vld1q_bf16_x4): New.
5650 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
5651 * config/arm/neon.md
5652 (neon_vld1_x4<mode>): New.
5653 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
5654 * config/arm/unspecs.md
5655 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
5657 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5659 * config/arm/arm_neon.h
5660 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
5661 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
5662 (vld1q_f16_x3, vld1q_f32_x3): New.
5663 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
5664 (vld1q_bf16_x3): New.
5665 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
5666 * config/arm/neon.md
5667 (neon_vld1_x3<mode>): New.
5668 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
5669 * config/arm/unspecs.md
5670 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
5672 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5674 * config/arm/arm_neon.h
5675 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
5676 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
5677 (vld1q_f16_x2, vld1q_f32_x2): New.
5678 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
5679 (vld1q_bf16_x2): New.
5680 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
5681 * config/arm/neon.md (vld1_x2<mode>): New.
5683 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5685 PR tree-optimization/113287
5686 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
5688 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5690 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
5691 * tree-vect-loop.cc (vect_transform_loop): Likewise.
5693 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5695 PR tree-optimization/113178
5696 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
5697 alternate exits.
5699 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5701 PR tree-optimization/113237
5702 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
5703 existing LCSSA variable for exit when all exits are early break.
5705 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5707 PR tree-optimization/113137
5708 PR tree-optimization/113136
5709 PR tree-optimization/113172
5710 PR tree-optimization/113178
5711 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5712 Maintain PHIs on inverted loops.
5713 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
5714 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
5715 latch.
5716 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
5718 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5720 PR tree-optimization/113135
5721 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
5722 dependency analysis.
5724 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
5726 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
5727 diagnostics class member name for abort of error.
5729 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5731 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
5732 format string to %s argument.
5734 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
5735 Jakub Jelinek <jakub@redhat.com>
5737 PR middle-end/113182
5738 * varasm.cc (process_pending_assemble_externals,
5739 assemble_external_libcall): Use targetm.strip_name_encoding
5740 before calling get_identifier.
5742 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5744 PR target/113196
5745 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
5746 New member variable.
5747 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
5748 Declare.
5749 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
5750 * config/aarch64/aarch64-simd.md
5751 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
5752 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
5753 zip2 for zero-extends to...
5754 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
5755 instruction. Fix big-endian handling.
5756 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
5757 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
5758 zip1 for zero-extends to...
5759 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
5760 Fix big-endian handling.
5761 (*aarch64_zip1_uxtl): New pattern.
5762 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
5763 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
5764 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
5765 (aarch64_gen_shareable_zero): Use it.
5766 (aarch64_split_simd_shift_p): New function.
5768 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5770 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
5771 (function_beg_insn): New macro.
5772 * function.cc (expand_function_start): Initialize function_beg_insn.
5774 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5776 PR target/112989
5777 * config/aarch64/aarch64-sve-builtins.h
5778 (function_builder::m_overload_names): Replace with...
5779 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
5780 new global.
5781 (add_overloaded_function): Update accordingly, using get_identifier
5782 to get a GGC-friendly record of the name.
5784 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5786 PR target/112989
5787 * config/aarch64/aarch64-sve-builtins.def: Don't include
5788 aarch64-sve-builtins-sme.def.
5789 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
5790 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
5791 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
5792 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
5793 requires AARCH64_FL_SME2.
5794 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
5795 AARCH64_FL_SME adjustment here.
5796 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
5797 include SME intrinsics.
5798 (sme_function_groups): New array.
5799 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
5800 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
5802 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5804 PR target/113281
5805 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
5806 (struct cpu_vector_cost): Add regmove struct.
5807 (get_vector_costs): Export as global.
5808 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
5809 (costs::add_stmt_cost): Ditto.
5810 * config/riscv/riscv.cc (get_common_costs): Export global function.
5812 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5814 PR tree-optimization/113334
5815 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
5816 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
5817 to determine if number should be extended by all ones rather than zero
5818 extended.
5820 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5822 PR tree-optimization/113330
5823 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
5824 too large size.
5826 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5828 PR tree-optimization/113323
5829 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
5830 check for lhs being large/huge _BitInt not in m_names.
5832 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5834 PR tree-optimization/113316
5835 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
5836 uninitialized large/huge _BitInt arguments to calls.
5838 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5840 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
5841 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
5842 CEIL (TYPE_PRECISION (t), limb_prec).
5843 (bitint_large_huge::handle_cast): Likewise.
5845 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
5847 PR sanitizer/113284
5848 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5849 Use assemble_function_label_final () for Power ELF V1 ABI.
5850 * output.h (assemble_function_label_final): New function.
5851 * varasm.cc (assemble_function_label_raw): Use
5852 assemble_function_label_final ().
5853 (assemble_function_label_final): New function.
5855 2024-01-12 Richard Biener <rguenther@suse.de>
5857 PR middle-end/113344
5858 * match.pd ((double)float CMP (double)float -> float CMP float):
5859 Perform result type check only for vectors.
5860 * fold-const.cc (fold_binary_loc): Likewise.
5862 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5864 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
5865 (usdot_prod<mode>): Ditto.
5866 (sdot_prod<mode>): Ditto.
5867 (udot_prod<mode>): Ditto.
5869 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5871 PR target/113288
5872 * config/i386/i386-c.cc (ix86_target_macros_internal):
5873 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
5875 2024-01-12 Richard Biener <rguenther@suse.de>
5877 PR target/112280
5878 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
5879 Do not generate code when d.testing_p.
5881 2024-01-12 liuhongt <hongtao.liu@intel.com>
5883 PR target/113039
5884 * doc/invoke.texi (fcf-protection=): Update documents.
5886 2024-01-12 Pan Li <pan2.li@intel.com>
5888 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
5889 comments of predicate func riscv_v_ext_mode_p.
5891 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
5893 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
5894 Modify ABI-name length of vfloat16m8_t
5896 2024-01-12 Li Wei <liwei@loongson.cn>
5898 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
5899 Adjust.
5901 2024-01-12 Li Wei <liwei@loongson.cn>
5903 * config/loongarch/loongarch.md (add<mode>3): Removed.
5904 (*addsi3): New.
5905 (addsi3): Ditto.
5906 (adddi3): Ditto.
5907 (*addsi3_extended): Removed.
5908 (addsi3_extended): New.
5910 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
5912 * config/riscv/thead.md: Add limits for splits.
5914 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
5916 PR middle-end/113322
5917 * expr.cc (do_store_flag): Don't try single bit tests with
5918 comparison on vector types.
5920 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
5922 PR tree-optimization/113301
5923 * match.pd (`1/x`): Delay signed case until late.
5925 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5927 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
5928 and -msp8 to...
5929 (AVR Internal Options): ...this new @subsubsection.
5931 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
5933 PR rtl-optimization/112918
5934 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
5935 (in_class_p): Restrict condition for narrowing class in case of
5936 allow_all_reload_class_changes_p.
5937 (process_alt_operands): Try to match operand without and with
5938 narrowing reg class. Discourage narrowing the class. Finish insn
5939 matching only if there is no class narrowing.
5940 (curr_insn_transform): Pass true to in_class_p for reg operand win.
5942 2024-01-11 Richard Biener <rguenther@suse.de>
5944 PR tree-optimization/112505
5945 * tree-vect-loop.cc (vectorizable_induction): Reject
5946 bit-precision induction.
5948 2024-01-11 Richard Biener <rguenther@suse.de>
5950 PR tree-optimization/113126
5951 * match.pd ((double)float CMP (double)float -> float CMP float):
5952 Make sure the boolean type is the same.
5953 * fold-const.cc (fold_binary_loc): Likewise.
5955 2024-01-11 Richard Biener <rguenther@suse.de>
5957 PR tree-optimization/112636
5958 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
5959 estimate_numbers_of_iterations before querying
5960 get_max_loop_iterations_int.
5961 (pass_ch::execute): Initialize SCEV and loops appropriately.
5963 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5965 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
5966 Reduced Tiny.
5967 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
5968 * doc/extend.texi (AVR Variable Attributes): Improve documentation
5969 of io, io_low and address attributes.
5970 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
5971 * doc/avr-mmcu.texi: Rebuild.
5973 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
5975 PR target/113233
5976 * config/loongarch/genopts/loongarch.opt.in: Mark options with
5977 the "Save" property.
5978 * config/loongarch/loongarch.opt: Same.
5979 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
5980 according to la_target.
5981 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
5982 RESTORE} for the la_target structure; Rename option conditions
5983 to have the same "la_" prefix.
5984 * config/loongarch/loongarch.h: Same.
5986 2024-01-11 Pan Li <pan2.li@intel.com>
5988 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
5989 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
5991 2024-01-11 Alex Coplan <alex.coplan@arm.com>
5993 PR target/113077
5994 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
5995 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
5996 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
5997 synthesize these if needed. Update caller ...
5998 (ldp_bb_info::fuse_pair): ... here.
5999 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6000 and either insn is frame-related.
6001 (find_trailing_add): Punt on frame-related insns.
6002 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6003 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6005 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
6007 * config/mips/mips.cc (mips_start_function_definition):
6008 Add ATTRIBUTE_UNUSED.
6010 2024-01-11 Richard Biener <rguenther@suse.de>
6012 PR middle-end/112740
6013 * expr.cc (store_constructor): Check the integer vector
6014 mask has a single bit per element before using sign-extension
6015 to expand an uniform vector.
6017 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6019 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6020 preempt VLS on unknown NITERS loop.
6022 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
6024 * doc/invoke.texi: Add -mevex512.
6026 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
6028 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6029 (*nor<mode>3): Likewise.
6030 (nor<mode>3): Likewise.
6031 (*negsi2_extended): New template.
6032 (*<optab>si3_internal): Likewise.
6033 (*one_cmplsi2_internal): Likewise.
6034 (*norsi3_internal): Likewise.
6035 (*<optab>nsi_internal): Likewise.
6036 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6037 modified bit operation to make the optimization work.
6039 2024-01-11 liuhongt <hongtao.liu@intel.com>
6041 PR target/104401
6042 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6044 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6046 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6047 (get_vector_costs): Ditto.
6048 (riscv_builtin_vectorization_cost): Ditto.
6050 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6052 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6054 2024-01-10 Antoni Boucher <bouanto@zoho.com>
6056 PR jit/111396
6057 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6058 ipa_free_size_summary.
6059 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6060 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6061 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6062 * ipa-prop.h (ipa_prop_cc_finalize): New function.
6063 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6064 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6065 ipa_sra_cc_finalize): New functions.
6066 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6067 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6068 ipa_sra_cc_finalize
6069 Include ipa-utils.h.
6071 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
6073 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6074 (th_int_get_save_adjustment): Likewise.
6075 (th_int_adjust_cfi_prologue): Likewise.
6076 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6077 (TH_INT_INTERRUPT): New macro.
6078 (riscv_expand_prologue): Add the processing of XTheadInt.
6079 (riscv_expand_epilogue): Likewise.
6080 * config/riscv/riscv.h (BITSET_P): Moved to here.
6081 * config/riscv/riscv.md: New unspec.
6082 * config/riscv/thead.cc (th_int_get_mask): New function.
6083 (th_int_get_save_adjustment): Likewise.
6084 (th_int_adjust_cfi_prologue): Likewise.
6085 * config/riscv/thead.md (th_int_push): New pattern.
6086 (th_int_pop): new pattern.
6088 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6090 PR tree-optimization/112468
6091 * doc/sourcebuild.texi: Document ifn_copysign.
6092 * match.pd: Only apply transformation if target supports the IFN.
6094 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
6096 PR tree-optimization/112581
6097 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6098 mark_ssa_maybe_undefs.
6099 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6100 variables can not be reassociated.
6101 (init_range_entry): Check for uninitialized variables too.
6102 (init_reassoc): Call mark_ssa_maybe_undefs.
6104 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
6106 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6107 Also handle sign extension.
6109 2024-01-10 Alex Coplan <alex.coplan@arm.com>
6111 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6112 to 0.
6113 (-mlate-ldp-fusion): Likewise.
6115 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6117 PR tree-optimization/113287
6118 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6119 instead of using BRANCH_EDGE to determine true edge.
6121 2024-01-10 Richard Biener <rguenther@suse.de>
6123 PR tree-optimization/113078
6124 * tree-vect-loop.cc (check_reduction_path): Canonicalize
6125 .COND_SUB to .COND_ADD.
6127 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6129 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6130 Handle prefix mappings before calling find_opt.
6131 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6132 "-fno-"-prefixed command-line option.
6133 * opts-common.cc (get_option_prefix_remapping): New.
6134 * opts.h (get_option_prefix_remapping): New decl.
6136 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6138 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6139 m_urlifier to pp_output_formatted_text.
6140 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6141 (obstack_append_string): New overload, taking a length.
6142 (urlify_quoted_string): Pass in an obstack ptr, rather than using
6143 that of the pp's buffer. Generalize to handle trailing text in
6144 the buffer beyond the run of quoted text.
6145 (class quoting_info): New.
6146 (on_begin_quote): New.
6147 (on_end_quote): New.
6148 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6149 it to calls to on_begin_quote and on_end_quote.
6150 (struct auto_obstack): New.
6151 (quoting_info::handle_phase_3): New.
6152 (pp_output_formatted_text): Add urlifier param. Use it if there
6153 is deferred urlification. Delete m_quotes.
6154 (selftest::pp_printf_with_urlifier): Pass urlifier to
6155 pp_output_formatted_text.
6156 (selftest::test_urlification): Update results for the existing
6157 case of quoted text stradding chunks; add more such test cases.
6158 * pretty-print.h (class quoting_info): New forward decl.
6159 (chunk_info::m_quotes): New field.
6160 (pp_output_formatted_text): Add optional urlifier param.
6162 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6164 * pretty-print.cc (selftest::test_pp_format): Add selftest
6165 coverage for numbered args.
6167 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6169 PR tree-optimization/113144
6170 PR tree-optimization/113145
6171 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6172 Update all BB that the original exits dominated.
6174 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
6176 * dwarf2out.cc (modified_type_die): Extend the support of reverse
6177 storage order to enumeration types if -gstrict-dwarf is not passed.
6178 (gen_enumeration_type_die): Add REVERSE parameter and generate the
6179 DIE immediately after the existing one if it is true.
6180 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6181 call to gen_enumeration_type_die.
6182 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6183 first recursive call as well as the call to gen_tagged_type_die.
6184 (gen_type_die): Add REVERSE parameter and pass it in the call to
6185 gen_type_die_with_usage.
6187 2024-01-10 Jakub Jelinek <jakub@redhat.com>
6189 PR tree-optimization/113120
6190 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6191 with root->size TYPE_PRECISION don't build anything new.
6192 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6193 rather than build_nonstandard_integer_type.
6195 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
6197 * config/i386/i386.opt: Adjust document.
6198 * doc/invoke.texi: Add description for
6199 -mapx-inline-asm-use-gpr32.
6201 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6203 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6204 (avg<v_double_trunc>3_floor): New pattern.
6205 (<u>avg<v_double_trunc>3_ceil): Remove.
6206 (avg<v_double_trunc>3_ceil): New pattern.
6207 (uavg<mode>3_floor): Ditto.
6208 (uavg<mode>3_ceil): Ditto.
6209 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6210 (enum insn_type): Ditto.
6211 * config/riscv/riscv-v.cc: Ditto.
6212 * config/riscv/vector-iterators.md (ashiftrt): Remove.
6213 (ASHIFTRT): Ditto.
6214 * config/riscv/vector.md: Add VLS modes.
6216 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6218 PR target/111480
6219 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6220 (vczlsbb_char): New int attribute.
6221 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6222 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6223 (*vctzlsbb_zext_<mode>): Rename to ...
6224 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6225 cover vclzlsbb.
6227 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6229 PR target/112606
6230 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6231 of the last argument from altivec_register_operand to any_operand. If
6232 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6233 otherwise if it doesn't satisfy altivec_register_operand, force it to
6234 REG using copy_to_mode_reg.
6236 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6238 PR middle-end/113100
6239 * builtins.cc (expand_builtin_stack_address): Guard stack point
6240 adjustment with SPARC_STACK_BOUNDARY_HACK.
6242 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6244 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6245 argument string definitions.
6246 * config/loongarch/loongarch-str.h: Same.
6247 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6248 as aliases to -mexplicit-relocs={always,none}
6249 * config/loongarch/loongarch.opt: Regenerate.
6250 * config/loongarch/loongarch.cc: Same.
6252 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6254 * config/loongarch/loongarch-def.h: Define constants with
6255 enums instead of Macros.
6257 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6259 * config/loongarch/genopts/loongarch-strings: Rename.
6260 * config/loongarch/genopts/loongarch.opt.in: Same.
6261 * config/loongarch/loongarch-cpu.cc: Same.
6262 * config/loongarch/loongarch-def.cc: Same.
6263 * config/loongarch/loongarch-def.h: Same.
6264 * config/loongarch/loongarch-opts.cc: Same.
6265 * config/loongarch/loongarch-opts.h: Same.
6266 * config/loongarch/loongarch-str.h: Same.
6267 * config/loongarch/loongarch.opt: Same.
6269 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6271 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6272 variable with the common la_ prefix.
6273 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6274 flags as saved using TargetVariable.
6275 * config/loongarch/loongarch.opt: Same.
6276 * config/loongarch/loongarch-def.h: Define evolution_set to
6277 mark changes to the -march default.
6278 * config/loongarch/loongarch-driver.cc: Same.
6279 * config/loongarch/loongarch-opts.cc: Same.
6280 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6281 conditions around the la_target structure.
6282 * config/loongarch/loongarch.cc: Same.
6283 * config/loongarch/loongarch.md: Same.
6284 * config/loongarch/loongarch-builtins.cc: Same.
6285 * config/loongarch/loongarch-c.cc: Same.
6286 * config/loongarch/lasx.md: Same.
6287 * config/loongarch/lsx.md: Same.
6288 * config/loongarch/sync.md: Same.
6290 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
6292 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6293 no less.
6295 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
6297 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6299 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6301 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6302 restart_loop.
6303 (vectorizable_live_operation): Likewise.
6305 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6307 PR tree-optimization/113199
6308 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6309 BIT_FIELD_REF.
6311 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6313 PR target/113270
6314 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6315 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6316 GTY(()) declaration before the definition, drop GTY(()) drom the
6317 definition.
6319 2024-01-09 Richard Biener <rguenther@suse.de>
6321 PR tree-optimization/113026
6322 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6323 redundant and wrong niter bound setting. Move niter
6324 bound adjustment down.
6326 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6328 PR middle-end/113163
6329 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6330 Reject non-linear inductions that aren't supported.
6332 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6334 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6335 left shift implementation strategies.
6336 (arc_shift_info): Type for each entry of the shift strategy table.
6337 (arc_shift_context_idx): Return a integer value for each code
6338 generation context, used as an index
6339 (arc_ashl_alg): Table indexed by context and shifted bit count.
6340 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6341 left shift implementation.
6342 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6343 provide accurate costs, when optimizing for speed or size.
6345 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6347 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6349 2024-01-09 Julian Brown <julian@codesourcery.com>
6351 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6352 processed out before gimplification.
6353 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6354 * tree.def (OMP_ARRAY_SECTION): New tree code.
6356 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6358 PR tree-optimization/113210
6359 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6360 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6361 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6362 minus 1.
6364 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
6366 PR rtl-optimization/113140
6367 * reorg.cc (fill_slots_from_thread): If we are to branch after the
6368 last instruction of the function, create an end label.
6370 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6371 Hongtao Liu <hongtao.liu@intel.com>
6373 PR target/112992
6374 * config/i386/i386-expand.cc
6375 (ix86_convert_const_wide_int_to_broadcast): Allow call to
6376 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6377 (ix86_broadcast_from_constant): Revert recent change; Return a
6378 suitable MEMREF independently of mode/target combinations.
6379 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6380 to decide whether expansion is possible/preferrable. Only try
6381 forcing DImode constants to memory (and trying again) if calling
6382 ix86_expand_vector_init_duplicate fails with an DImode immediate
6383 constant.
6384 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6385 V4SImode for suitable immediate constants.
6386 <case E_V4DImode>: Try using V8SImode for suitable constants.
6387 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6388 <case E_V2HImode>: Likewise.
6389 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6390 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6391 <label widen>: Handle CONT_INTs via simplify_binary_operation.
6392 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6393 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6394 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6395 (ix86_expand_vector_init): Move try using a broadcast for all_same
6396 with ix86_expand_vector_init_duplicate before using constant pool.
6398 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6400 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6402 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6404 * config/arm/arm-cpus.in (cortex-m52): New cpu.
6405 * config/arm/arm-tables.opt: Regenerate.
6406 * config/arm/arm-tune.md: Regenerate.
6408 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
6410 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6411 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6412 (@vec_concatz<mode>): New insn pattern.
6413 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6414 Handle VALS containing two vectors.
6416 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6418 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6419 (vundefined): Ditto.
6421 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
6423 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6424 Add new function_base for crypto vector.
6425 (class bitmanip): Ditto.
6426 (class b_reverse):Ditto.
6427 (class vwsll): Ditto.
6428 (class clmul): Ditto.
6429 (class vg_nhab): Ditto.
6430 (class crypto_vv):Ditto.
6431 (class crypto_vi):Ditto.
6432 (class vaeskf2_vsm3c):Ditto.
6433 (class vsm3me): Ditto.
6434 (BASE): Add BASE declaration for crypto vector.
6435 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6436 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6437 Add crypto vector intrinsic definition.
6438 (vbrev): Ditto.
6439 (vclz): Ditto.
6440 (vctz): Ditto.
6441 (vwsll): Ditto.
6442 (vandn): Ditto.
6443 (vbrev8): Ditto.
6444 (vrev8): Ditto.
6445 (vrol): Ditto.
6446 (vror): Ditto.
6447 (vclmul): Ditto.
6448 (vclmulh): Ditto.
6449 (vghsh): Ditto.
6450 (vgmul): Ditto.
6451 (vaesef): Ditto.
6452 (vaesem): Ditto.
6453 (vaesdf): Ditto.
6454 (vaesdm): Ditto.
6455 (vaesz): Ditto.
6456 (vaeskf1): Ditto.
6457 (vaeskf2): Ditto.
6458 (vsha2ms): Ditto.
6459 (vsha2ch): Ditto.
6460 (vsha2cl): Ditto.
6461 (vsm4k): Ditto.
6462 (vsm4r): Ditto.
6463 (vsm3me): Ditto.
6464 (vsm3c): Ditto.
6465 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6466 Add new function_shape for crypto vector.
6467 (struct crypto_vi_def): Ditto.
6468 (struct crypto_vv_no_op_type_def): Ditto.
6469 (SHAPE): Add SHAPE declaration of crypto vector.
6470 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6471 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6472 Add new data type for crypto vector.
6473 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6474 (vuint32mf2_t): Ditto.
6475 (vuint32m1_t): Ditto.
6476 (vuint32m2_t): Ditto.
6477 (vuint32m4_t): Ditto.
6478 (vuint32m8_t): Ditto.
6479 (vuint64m1_t): Ditto.
6480 (vuint64m2_t): Ditto.
6481 (vuint64m4_t): Ditto.
6482 (vuint64m8_t): Ditto.
6483 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6484 Add new data struct for crypto vector.
6485 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6486 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6487 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6489 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
6491 PR sanitizer/113251
6492 * varasm.cc (assemble_function_label_raw): Do not call
6493 asan_function_start () without the current function.
6495 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6497 PR target/113225
6498 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
6499 extern and kernel_helper attributed function decls.
6501 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6503 * btfout.cc (output_btf_strs): Changed.
6505 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6507 * config/gcn/mkoffload.cc (main): Handle gfx1100
6508 when setting the default XNACK.
6510 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6512 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6513 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6514 (ASM_SPEC): Handle gfx1100.
6515 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6516 (enum gcn_isa): Add ISA_RDNA3.
6517 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6518 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6519 * config/gcn/gcn.cc (gcn_option_override,
6520 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6521 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6522 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6523 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6524 with gfx1100.
6525 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6526 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6527 __gfx1100__.
6528 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6529 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6530 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6531 (isa_has_combined_avgprs, main): Handle gfx1100.
6532 * config/gcn/t-omp-device (isa): Add gfx1100.
6534 2024-01-08 Richard Biener <rguenther@suse.de>
6536 * doc/invoke.texi (-mmovbe): Clarify.
6538 2024-01-08 Richard Biener <rguenther@suse.de>
6540 PR tree-optimization/113026
6541 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6542 Avoid an epilog in more cases.
6543 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
6544 epilogues niter upper bounds and estimates.
6546 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6548 PR tree-optimization/113228
6549 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
6551 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6553 PR tree-optimization/113120
6554 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
6555 large _BitInt zero INTEGER_CST PHI argument.
6557 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6559 PR tree-optimization/113119
6560 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
6561 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
6562 is before REALPART_EXPR.
6564 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
6566 PR target/112952
6567 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
6568 range when diagnosing attribute "io" and "io_low" are out of range.
6569 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
6570 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
6571 in contexts other than static storage.
6572 (avr_asm_output_aligned_decl_common): Move output of decls with
6573 attribute "address", "io", and "io_low" to...
6574 (avr_output_addr_attrib): ...this new function.
6575 (avr_asm_asm_output_aligned_bss): Remove output for decls with
6576 attribute "address", "io", and "io_low".
6577 (avr_encode_section_info): Rectify handling of decls with attribute
6578 "address", "io", and "io_low".
6580 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6582 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
6583 (elf_flags): Remove XNACK from the default value.
6584 (main): Set a default XNACK according to the arch.
6586 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6588 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
6589 (process_asm): Don't count avgprs.
6591 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
6593 * config/i386/i386.opt: Add supported sub-features.
6594 * doc/extend.texi: Add description for target attribute.
6596 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
6598 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
6600 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
6601 Uros Bizjak <ubizjak@gmail.com>
6603 PR target/113231
6604 * config/i386/i386-features.cc (compute_convert_gain): Include
6605 the overhead of explicit load and store (movd) instructions when
6606 converting non-store scalar operations with memory destinations.
6607 Various indentation whitespace fixes.
6609 2024-01-07 Tamar Christina <tamar.christina@arm.com>
6611 * config/arm/neon.md (cbranch<mode>4): New.
6613 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6615 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
6617 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
6619 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
6621 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6623 PR target/113248
6624 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
6625 Update the MAX_SEW.
6627 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6629 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
6630 (variable_vectorized_p): Teach loop invariant.
6631 (has_unexpected_spills_p): Ditto.
6633 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6635 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
6636 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
6637 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
6639 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
6641 PR target/113104
6642 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
6643 (aarch64-vect-compare-costs): ...this.
6644 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
6645 Replace with...
6646 (-param=aarch64-vect-compare-costs=): ...this new param.
6647 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
6648 Don't disable it when vectorizing for Advanced SIMD only.
6649 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
6650 whenever aarch64_vect_compare_costs is true.
6652 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
6654 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
6655 Modify the method of determining the memory offset of [x]vld/[x]vst.
6656 (lasx_mxst_<lasxfmt_f>): Likewise.
6657 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
6658 (loongarch_address_insns): Likewise.
6659 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
6660 (lsx_st_<lsxfmt_f>): Likewise.
6661 * config/loongarch/predicates.md (aq10b_operand): Likewise.
6662 (aq10h_operand): Likewise.
6663 (aq10w_operand): Likewise.
6664 (aq10d_operand): Likewise.
6666 2024-01-05 Alex Coplan <alex.coplan@arm.com>
6668 PR target/113217
6669 * config/aarch64/aarch64-ldp-fusion.cc
6670 (ldp_bb_info::try_fuse_pair): If the second access can throw,
6671 narrow the move range to exactly that insn.
6673 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6675 * asan.cc (asan_function_start): Drop switch_to_section ().
6676 (asan_emit_stack_protection): Set .LASANPC alignment.
6677 * config/i386/i386.cc: Use assemble_function_label_raw ()
6678 instead of ASM_OUTPUT_LABEL ().
6679 * config/s390/s390.cc (s390_asm_output_function_label):
6680 Likewise.
6681 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
6682 * final.cc (final_start_function_1): Drop
6683 asan_function_start ().
6684 * output.h (assemble_function_label_raw): New function.
6685 * varasm.cc (assemble_function_label_raw): Likewise.
6687 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6689 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
6690 Use ASM_OUTPUT_FUNCTION_LABEL ().
6691 * config/alpha/alpha.cc (alpha_start_function): Likewise.
6692 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6693 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
6694 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6695 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6696 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
6697 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6698 * config/ia64/ia64.cc (ia64_start_function): Likewise.
6699 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
6700 Likewise.
6701 * config/microblaze/microblaze.cc (microblaze_function_prologue):
6702 Likewise.
6703 * config/mips/mips.cc (mips_start_unique_function): Return the
6704 tree.
6705 (mips_start_function_definition): Use
6706 ASM_OUTPUT_FUNCTION_LABEL ().
6707 (mips_finish_stub): Pass the tree to
6708 mips_start_function_definition ().
6709 (mips16_build_function_stub): Likewise.
6710 (mips16_build_call_stub): Likewise.
6711 (mips_output_function_prologue): Likewise.
6712 * config/pa/pa.cc (pa_output_function_label): Use
6713 ASM_OUTPUT_FUNCTION_LABEL ().
6714 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
6715 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6716 Likewise.
6717 (rs6000_xcoff_declare_function_name): Likewise.
6719 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6721 PR tree-optimization/113201
6722 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
6723 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
6725 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6727 PR tree-optimization/90693
6728 * tree-ssa-math-opts.cc (match_single_bit_test): If
6729 tree_expr_nonzero_p (arg), remember it in the second argument to
6730 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
6731 arg ^ (arg - 1) > arg - 1.
6732 * internal-fn.cc (expand_POPCOUNT): If second argument to
6733 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
6734 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
6736 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
6738 * config/riscv/riscv-v.cc (expand_load_store):
6739 Remove `value`.
6740 (expand_cond_len_op): Ditto.
6741 (expand_gather_scatter): Ditto.
6742 (expand_lanes_load_store): Ditto.
6743 (expand_fold_extract_last): Ditto.
6745 2024-01-05 Pan Li <pan2.li@intel.com>
6747 Revert:
6748 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6750 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6751 Add new function_base for crypto vector.
6752 (class bitmanip): Ditto.
6753 (class b_reverse):Ditto.
6754 (class vwsll): Ditto.
6755 (class clmul): Ditto.
6756 (class vg_nhab): Ditto.
6757 (class crypto_vv):Ditto.
6758 (class crypto_vi):Ditto.
6759 (class vaeskf2_vsm3c):Ditto.
6760 (class vsm3me): Ditto.
6761 (BASE): Add BASE declaration for crypto vector.
6762 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6763 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6764 Add crypto vector intrinsic definition.
6765 (vbrev): Ditto.
6766 (vclz): Ditto.
6767 (vctz): Ditto.
6768 (vwsll): Ditto.
6769 (vandn): Ditto.
6770 (vbrev8): Ditto.
6771 (vrev8): Ditto.
6772 (vrol): Ditto.
6773 (vror): Ditto.
6774 (vclmul): Ditto.
6775 (vclmulh): Ditto.
6776 (vghsh): Ditto.
6777 (vgmul): Ditto.
6778 (vaesef): Ditto.
6779 (vaesem): Ditto.
6780 (vaesdf): Ditto.
6781 (vaesdm): Ditto.
6782 (vaesz): Ditto.
6783 (vaeskf1): Ditto.
6784 (vaeskf2): Ditto.
6785 (vsha2ms): Ditto.
6786 (vsha2ch): Ditto.
6787 (vsha2cl): Ditto.
6788 (vsm4k): Ditto.
6789 (vsm4r): Ditto.
6790 (vsm3me): Ditto.
6791 (vsm3c): Ditto.
6792 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6793 Add new function_shape for crypto vector.
6794 (struct crypto_vi_def): Ditto.
6795 (struct crypto_vv_no_op_type_def): Ditto.
6796 (SHAPE): Add SHAPE declaration of crypto vector.
6797 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6798 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6799 Add new data type for crypto vector.
6800 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6801 (vuint32mf2_t): Ditto.
6802 (vuint32m1_t): Ditto.
6803 (vuint32m2_t): Ditto.
6804 (vuint32m4_t): Ditto.
6805 (vuint32m8_t): Ditto.
6806 (vuint64m1_t): Ditto.
6807 (vuint64m2_t): Ditto.
6808 (vuint64m4_t): Ditto.
6809 (vuint64m8_t): Ditto.
6810 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6811 Add new data struct for crypto vector.
6812 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6813 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6814 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6816 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6818 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6819 Add new function_base for crypto vector.
6820 (class bitmanip): Ditto.
6821 (class b_reverse):Ditto.
6822 (class vwsll): Ditto.
6823 (class clmul): Ditto.
6824 (class vg_nhab): Ditto.
6825 (class crypto_vv):Ditto.
6826 (class crypto_vi):Ditto.
6827 (class vaeskf2_vsm3c):Ditto.
6828 (class vsm3me): Ditto.
6829 (BASE): Add BASE declaration for crypto vector.
6830 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6831 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6832 Add crypto vector intrinsic definition.
6833 (vbrev): Ditto.
6834 (vclz): Ditto.
6835 (vctz): Ditto.
6836 (vwsll): Ditto.
6837 (vandn): Ditto.
6838 (vbrev8): Ditto.
6839 (vrev8): Ditto.
6840 (vrol): Ditto.
6841 (vror): Ditto.
6842 (vclmul): Ditto.
6843 (vclmulh): Ditto.
6844 (vghsh): Ditto.
6845 (vgmul): Ditto.
6846 (vaesef): Ditto.
6847 (vaesem): Ditto.
6848 (vaesdf): Ditto.
6849 (vaesdm): Ditto.
6850 (vaesz): Ditto.
6851 (vaeskf1): Ditto.
6852 (vaeskf2): Ditto.
6853 (vsha2ms): Ditto.
6854 (vsha2ch): Ditto.
6855 (vsha2cl): Ditto.
6856 (vsm4k): Ditto.
6857 (vsm4r): Ditto.
6858 (vsm3me): Ditto.
6859 (vsm3c): Ditto.
6860 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6861 Add new function_shape for crypto vector.
6862 (struct crypto_vi_def): Ditto.
6863 (struct crypto_vv_no_op_type_def): Ditto.
6864 (SHAPE): Add SHAPE declaration of crypto vector.
6865 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6866 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6867 Add new data type for crypto vector.
6868 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6869 (vuint32mf2_t): Ditto.
6870 (vuint32m1_t): Ditto.
6871 (vuint32m2_t): Ditto.
6872 (vuint32m4_t): Ditto.
6873 (vuint32m8_t): Ditto.
6874 (vuint64m1_t): Ditto.
6875 (vuint64m2_t): Ditto.
6876 (vuint64m4_t): Ditto.
6877 (vuint64m8_t): Ditto.
6878 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6879 Add new data struct for crypto vector.
6880 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6881 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6882 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6884 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6886 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6888 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
6890 PR tree-optimization/113186
6891 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
6892 Match `^` with the `==` for 1bit integral types.
6893 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
6894 integral types.
6896 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6898 * toplev.cc (general_init): Pass lang_mask to urlifier.
6900 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6902 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
6903 param.
6904 (diagnostic_context::make_option_url): Update for lang_mask param.
6905 * gcc-urlifier.cc: Include "opts.h" and "options.h".
6906 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
6907 (gcc_urlifier::m_lang_mask): New field.
6908 (doc_urls): Make static.
6909 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
6910 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6911 Look for an option by name before trying a binary search in
6912 doc_urls.
6913 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6914 (gcc_urlifier::get_url_suffix_for_option): New.
6915 (make_gcc_urlifier): Add lang_mask param.
6916 (selftest::gcc_urlifier_cc_tests): Update for above changes.
6917 Verify that a URL is found for "-fpack-struct".
6918 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
6919 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
6920 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
6921 to make_gcc_urlifier.
6922 * opts-diagnostic.h (get_option_url): Add lang_mask param.
6923 * opts.cc (get_option_html_page): Remove special-casing for
6924 analyzer and LTO.
6925 (get_option_url_suffix): New.
6926 (get_option_url): Reimplement.
6927 (selftest::test_get_option_html_page): Rename to...
6928 (selftest::test_get_option_url_suffix): ...this and update for
6929 above changes.
6930 (selftest::opts_cc_tests): Update for renaming.
6931 * opts.h: Include "rich-location.h".
6932 (get_option_url_suffix): New decl.
6934 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6936 * Makefile.in (ALL_OPT_URL_FILES): New.
6937 (GCC_OBJS): Add options-urls.o.
6938 (OBJS): Likewise.
6939 (OBJS-libcommon): Likewise.
6940 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
6941 inputs to opt-gather.awk.
6942 (options-urls.cc): New Makefile target.
6943 * opt-functions.awk (url_suffix): New function.
6944 (lang_url_suffix): New function.
6945 * options-urls-cc-gen.awk: New file.
6946 * opts.h (get_opt_url_suffix): New decl.
6948 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6950 * params.opt.urls: New file, autogenerated by
6951 regenerate-opt-urls.py.
6953 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6955 * common.opt.urls: New file, autogenerated by
6956 regenerate-opt-urls.py.
6957 * config/aarch64/aarch64.opt.urls: Likewise.
6958 * config/alpha/alpha.opt.urls: Likewise.
6959 * config/alpha/elf.opt.urls: Likewise.
6960 * config/arc/arc-tables.opt.urls: Likewise.
6961 * config/arc/arc.opt.urls: Likewise.
6962 * config/arm/arm-tables.opt.urls: Likewise.
6963 * config/arm/arm.opt.urls: Likewise.
6964 * config/arm/vxworks.opt.urls: Likewise.
6965 * config/avr/avr.opt.urls: Likewise.
6966 * config/bpf/bpf.opt.urls: Likewise.
6967 * config/c6x/c6x-tables.opt.urls: Likewise.
6968 * config/c6x/c6x.opt.urls: Likewise.
6969 * config/cris/cris.opt.urls: Likewise.
6970 * config/cris/elf.opt.urls: Likewise.
6971 * config/csky/csky.opt.urls: Likewise.
6972 * config/csky/csky_tables.opt.urls: Likewise.
6973 * config/darwin.opt.urls: Likewise.
6974 * config/dragonfly.opt.urls: Likewise.
6975 * config/epiphany/epiphany.opt.urls: Likewise.
6976 * config/fr30/fr30.opt.urls: Likewise.
6977 * config/freebsd.opt.urls: Likewise.
6978 * config/frv/frv.opt.urls: Likewise.
6979 * config/ft32/ft32.opt.urls: Likewise.
6980 * config/fused-madd.opt.urls: Likewise.
6981 * config/g.opt.urls: Likewise.
6982 * config/gcn/gcn.opt.urls: Likewise.
6983 * config/gnu-user.opt.urls: Likewise.
6984 * config/h8300/h8300.opt.urls: Likewise.
6985 * config/hpux11.opt.urls: Likewise.
6986 * config/i386/cygming.opt.urls: Likewise.
6987 * config/i386/cygwin.opt.urls: Likewise.
6988 * config/i386/djgpp.opt.urls: Likewise.
6989 * config/i386/i386.opt.urls: Likewise.
6990 * config/i386/mingw-w64.opt.urls: Likewise.
6991 * config/i386/mingw.opt.urls: Likewise.
6992 * config/i386/nto.opt.urls: Likewise.
6993 * config/ia64/ia64.opt.urls: Likewise.
6994 * config/ia64/ilp32.opt.urls: Likewise.
6995 * config/ia64/vms.opt.urls: Likewise.
6996 * config/iq2000/iq2000.opt.urls: Likewise.
6997 * config/linux-android.opt.urls: Likewise.
6998 * config/linux.opt.urls: Likewise.
6999 * config/lm32/lm32.opt.urls: Likewise.
7000 * config/loongarch/loongarch.opt.urls: Likewise.
7001 * config/lynx.opt.urls: Likewise.
7002 * config/m32c/m32c.opt.urls: Likewise.
7003 * config/m32r/m32r.opt.urls: Likewise.
7004 * config/m68k/ieee.opt.urls: Likewise.
7005 * config/m68k/m68k-tables.opt.urls: Likewise.
7006 * config/m68k/m68k.opt.urls: Likewise.
7007 * config/m68k/uclinux.opt.urls: Likewise.
7008 * config/mcore/mcore.opt.urls: Likewise.
7009 * config/microblaze/microblaze.opt.urls: Likewise.
7010 * config/mips/mips-tables.opt.urls: Likewise.
7011 * config/mips/mips.opt.urls: Likewise.
7012 * config/mips/sde.opt.urls: Likewise.
7013 * config/mmix/mmix.opt.urls: Likewise.
7014 * config/mn10300/mn10300.opt.urls: Likewise.
7015 * config/moxie/moxie.opt.urls: Likewise.
7016 * config/msp430/msp430.opt.urls: Likewise.
7017 * config/nds32/nds32-elf.opt.urls: Likewise.
7018 * config/nds32/nds32-linux.opt.urls: Likewise.
7019 * config/nds32/nds32.opt.urls: Likewise.
7020 * config/netbsd-elf.opt.urls: Likewise.
7021 * config/netbsd.opt.urls: Likewise.
7022 * config/nios2/elf.opt.urls: Likewise.
7023 * config/nios2/nios2.opt.urls: Likewise.
7024 * config/nvptx/nvptx-gen.opt.urls: Likewise.
7025 * config/nvptx/nvptx.opt.urls: Likewise.
7026 * config/openbsd.opt.urls: Likewise.
7027 * config/or1k/elf.opt.urls: Likewise.
7028 * config/or1k/or1k.opt.urls: Likewise.
7029 * config/pa/pa-hpux.opt.urls: Likewise.
7030 * config/pa/pa-hpux1010.opt.urls: Likewise.
7031 * config/pa/pa-hpux1111.opt.urls: Likewise.
7032 * config/pa/pa-hpux1131.opt.urls: Likewise.
7033 * config/pa/pa.opt.urls: Likewise.
7034 * config/pa/pa64-hpux.opt.urls: Likewise.
7035 * config/pdp11/pdp11.opt.urls: Likewise.
7036 * config/pru/pru.opt.urls: Likewise.
7037 * config/riscv/riscv.opt.urls: Likewise.
7038 * config/rl78/rl78.opt.urls: Likewise.
7039 * config/rpath.opt.urls: Likewise.
7040 * config/rs6000/476.opt.urls: Likewise.
7041 * config/rs6000/aix64.opt.urls: Likewise.
7042 * config/rs6000/darwin.opt.urls: Likewise.
7043 * config/rs6000/linux64.opt.urls: Likewise.
7044 * config/rs6000/rs6000-tables.opt.urls: Likewise.
7045 * config/rs6000/rs6000.opt.urls: Likewise.
7046 * config/rs6000/sysv4.opt.urls: Likewise.
7047 * config/rtems.opt.urls: Likewise.
7048 * config/rx/elf.opt.urls: Likewise.
7049 * config/rx/rx.opt.urls: Likewise.
7050 * config/s390/s390.opt.urls: Likewise.
7051 * config/s390/tpf.opt.urls: Likewise.
7052 * config/sh/sh.opt.urls: Likewise.
7053 * config/sh/superh.opt.urls: Likewise.
7054 * config/sol2.opt.urls: Likewise.
7055 * config/sparc/long-double-switch.opt.urls: Likewise.
7056 * config/sparc/sparc.opt.urls: Likewise.
7057 * config/stormy16/stormy16.opt.urls: Likewise.
7058 * config/v850/v850.opt.urls: Likewise.
7059 * config/vax/elf.opt.urls: Likewise.
7060 * config/vax/vax.opt.urls: Likewise.
7061 * config/visium/visium.opt.urls: Likewise.
7062 * config/vms/vms.opt.urls: Likewise.
7063 * config/vxworks-smp.opt.urls: Likewise.
7064 * config/vxworks.opt.urls: Likewise.
7065 * config/xtensa/elf.opt.urls: Likewise.
7066 * config/xtensa/uclinux.opt.urls: Likewise.
7067 * config/xtensa/xtensa.opt.urls: Likewise.
7068 * config/bfin/bfin.opt.urls: New file.
7070 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7072 * Makefile.in (OPT_URLS_HTML_DEPS): New.
7073 (regenerate-opt-urls): New target.
7074 (regenerate-opt-urls-unit-test): New target.
7075 * doc/options.texi (Option properties): Add UrlSuffix and
7076 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
7077 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7078 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7079 and Makefile.in's OPT_URLS_HTML_DEPS.
7080 (Anatomy of a Target Back End): Add
7081 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7082 * regenerate-opt-urls.py: New file.
7084 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7086 * diagnostic-format-sarif.cc
7087 (sarif_builder::make_logical_location_object): Convert to...
7088 (make_sarif_logical_location_object): ...this.
7089 (sarif_builder::set_any_logical_locs_arr): Update for above
7090 change.
7091 (sarif_builder::make_thread_flow_location_object): Call
7092 maybe_add_sarif_properties on each diagnostic_event.
7093 * diagnostic-format-sarif.h (class logical_location): New forward
7094 decl.
7095 (make_sarif_logical_location_object): New decl.
7096 * diagnostic-path.h (class sarif_object): New forward decl.
7097 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7099 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
7100 Patrick Lin <patrick@andestech.com>
7101 Rufus Chen <rufus@andestech.com>
7102 Monk Chiang <monk.chiang@sifive.com>
7104 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7105 with Nan-boxing value.
7106 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7108 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
7109 Jeff Law <jlaw@ventanamicro.com>
7111 PR rtl-optimization/104914
7112 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7113 a sign or zero extension is only required if the modified field
7114 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
7115 targets, don't refer to the temporarily incorrectly extended value
7116 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7118 2024-01-04 Pan Li <pan2.li@intel.com>
7120 Revert:
7121 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7123 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7125 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7127 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7129 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
7131 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7132 offset of fcsr.
7134 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7136 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7137 (compute_nregs_for_mode): Refine LMUL.
7138 (max_number_of_live_regs): Ditto.
7139 (compute_estimated_lmul): Ditto.
7140 (has_unexpected_spills_p): Ditto.
7142 2024-01-04 Li Wei <liwei@loongson.cn>
7144 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7145 Remove useless forward declaration.
7146 (loongarch_is_even_extraction): Remove useless forward declaration.
7147 (loongarch_try_expand_lsx_vshuf_const): Removed.
7148 (loongarch_expand_vec_perm_const_1): Merged.
7149 (loongarch_is_double_duplicate): Removed.
7150 (loongarch_is_center_extraction): Ditto.
7151 (loongarch_is_reversing_permutation): Ditto.
7152 (loongarch_is_di_misalign_extract): Ditto.
7153 (loongarch_is_si_misalign_extract): Ditto.
7154 (loongarch_is_lasx_lowpart_extract): Ditto.
7155 (loongarch_is_op_reverse_perm): Ditto.
7156 (loongarch_is_single_op_perm): Ditto.
7157 (loongarch_is_divisible_perm): Ditto.
7158 (loongarch_is_triple_stride_extract): Ditto.
7159 (loongarch_expand_vec_perm_const_2): Merged.
7160 (loongarch_expand_vec_perm_const): New.
7161 (loongarch_vectorize_vec_perm_const): Adjust.
7163 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
7165 * omp-general.cc: Fix comment typos and misplaced/confusing
7166 comments. Delete redundant include of omp-general.h.
7168 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7170 PR rtl-optimization/104914
7171 * config/mips/mips.md (insqisi_extended): New patterns.
7172 (inshisi_extended): Ditto.
7174 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7176 * config/mips/mips.cc (mips_insn_cost): New function.
7178 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7180 * config/mips/mips.md (perf_ratio): New attribute.
7182 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7184 PR target/113206
7185 PR target/113209
7186 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7187 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7188 blocks belong to infinite loop.
7189 (pre_vsetvl::emit_vsetvl): Remove fake edges.
7190 * config/riscv/t-riscv: Add a new include file.
7192 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7194 * config/riscv/vector.md: Fix indent.
7196 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7198 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7199 OMP_CLAUSE__SIMDUID_.
7200 * tree.cc (omp_clause_num_ops): Update position of entry for
7201 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7202 (omp_clause_code_name): Likewise.
7204 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7206 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7207 printing of FUNC_MAP/IND_FUNC_MAP labels.
7209 2024-01-03 Jakub Jelinek <jakub@redhat.com>
7211 * gcc.cc (process_command): Update copyright notice dates.
7212 * gcov-dump.cc (print_version): Ditto.
7213 * gcov.cc (print_version): Ditto.
7214 * gcov-tool.cc (print_version): Ditto.
7215 * gengtype.cc (create_file): Ditto.
7216 * doc/cpp.texi: Bump @copying's copyright year.
7217 * doc/cppinternals.texi: Ditto.
7218 * doc/gcc.texi: Ditto.
7219 * doc/gccint.texi: Ditto.
7220 * doc/gcov.texi: Ditto.
7221 * doc/install.texi: Ditto.
7222 * doc/invoke.texi: Ditto.
7224 2024-01-03 Xi Ruoyao <xry111@xry111.site>
7226 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7227 (fmin<mode>3): Likewise.
7228 (reduc_fmax_scal_<mode>3): New define_expand.
7229 (reduc_fmin_scal_<mode>3): Likewise.
7231 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7233 PR target/113112
7234 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7235 (max_number_of_live_regs): Ditto.
7236 (has_unexpected_spills_p): Ditto.
7238 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
7239 Jin Ma <jinma@linux.alibaba.com>
7240 Xianmiao Qu <cooper.qu@linux.alibaba.com>
7241 Christoph Müllner <christoph.muellner@vrull.eu>
7243 * config/riscv/vector.md:
7244 Use vector_length_operand for vsetvl patterns.
7246 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7248 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7249 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7251 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
7253 * config/aarch64/aarch64-tuning-flags.def
7254 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7255 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7256 * config/aarch64/aarch64.cc
7257 (aarch64_override_options_internal): Set
7258 param_fully_pipelined_fma according to tuning option.
7259 * config/aarch64/tuning_models/ampere1.h: Add
7260 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7261 * config/aarch64/tuning_models/ampere1a.h: Likewise.
7262 * config/aarch64/tuning_models/ampere1b.h: Likewise.
7264 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7266 * config/riscv/vector-crypto.md: Modify copyright year.
7268 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7270 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7272 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
7274 * config.in: Regenerate.
7275 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7276 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7277 Added TLS Le Relax support.
7278 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7279 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7280 * configure: Regenerate.
7281 * configure.ac: Check if binutils supports TLS le relax.
7283 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7285 * config/riscv/iterators.md: Add rotate insn name.
7286 * config/riscv/riscv.md: Add new insns name for crypto vector.
7287 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7288 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7289 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7291 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7293 PR target/113112
7294 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7295 pointer type liveness count.
7296 \f
7297 Copyright (C) 2024 Free Software Foundation, Inc.
7299 Copying and distribution of this file, with or without modification,
7300 are permitted in any medium without royalty provided the copyright
7301 notice and this notice are preserved.