| blob | bdf19f8df471af0e5b3ebb99311115729c85293b |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2013 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
57 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
58 (TOC_SAVE_OFFSET_32BIT 20)
59 (TOC_SAVE_OFFSET_64BIT 40)
61 ; Function TOC offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_TOC_32BIT 4)
63 (AIX_FUNC_DESC_TOC_64BIT 8)
65 ; Static chain offset in the AIX function descriptor.
66 (AIX_FUNC_DESC_SC_32BIT 8)
67 (AIX_FUNC_DESC_SC_64BIT 16)
68 ])
70 ;;
71 ;; UNSPEC usage
72 ;;
74 (define_c_enum "unspec"
75 [UNSPEC_FRSP ; frsp for POWER machines
76 UNSPEC_PROBE_STACK ; probe stack memory reference
77 UNSPEC_TOCPTR ; address of a word pointing to the TOC
78 UNSPEC_TOC ; address of the TOC (more-or-less)
79 UNSPEC_MOVSI_GOT
80 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
81 UNSPEC_FCTIWZ
82 UNSPEC_FRIM
83 UNSPEC_FRIN
84 UNSPEC_FRIP
85 UNSPEC_FRIZ
86 UNSPEC_LD_MPIC ; load_macho_picbase
87 UNSPEC_MPIC_CORRECT ; macho_correct_pic
88 UNSPEC_TLSGD
89 UNSPEC_TLSLD
90 UNSPEC_MOVESI_FROM_CR
91 UNSPEC_MOVESI_TO_CR
92 UNSPEC_TLSDTPREL
93 UNSPEC_TLSDTPRELHA
94 UNSPEC_TLSDTPRELLO
95 UNSPEC_TLSGOTDTPREL
96 UNSPEC_TLSTPREL
97 UNSPEC_TLSTPRELHA
98 UNSPEC_TLSTPRELLO
99 UNSPEC_TLSGOTTPREL
100 UNSPEC_TLSTLS
101 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
102 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
103 UNSPEC_STFIWX
104 UNSPEC_POPCNTB
105 UNSPEC_FRES
106 UNSPEC_SP_SET
107 UNSPEC_SP_TEST
108 UNSPEC_SYNC
109 UNSPEC_LWSYNC
110 UNSPEC_SYNC_OP
111 UNSPEC_ATOMIC
112 UNSPEC_CMPXCHG
113 UNSPEC_XCHG
114 UNSPEC_AND
115 UNSPEC_DLMZB
116 UNSPEC_DLMZB_CR
117 UNSPEC_DLMZB_STRLEN
118 UNSPEC_RSQRT
119 UNSPEC_TOCREL
120 UNSPEC_MACHOPIC_OFFSET
121 UNSPEC_BPERM
122 UNSPEC_COPYSIGN
123 UNSPEC_PARITY
124 UNSPEC_FCTIW
125 UNSPEC_FCTID
126 UNSPEC_LFIWAX
127 UNSPEC_LFIWZX
128 UNSPEC_FCTIWUZ
129 UNSPEC_GRP_END_NOP
130 ])
132 ;;
133 ;; UNSPEC_VOLATILE usage
134 ;;
136 (define_c_enum "unspecv"
137 [UNSPECV_BLOCK
138 UNSPECV_LL ; load-locked
139 UNSPECV_SC ; store-conditional
140 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
141 UNSPECV_EH_RR ; eh_reg_restore
142 UNSPECV_ISYNC ; isync instruction
143 UNSPECV_MFTB ; move from time base
144 ])
146 \f
147 ;; Define an insn type attribute. This is used in function unit delay
148 ;; computations.
149 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
150 (const_string "integer"))
152 ;; Define floating point instruction sub-types for use with Xfpu.md
153 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
155 ;; Length (in bytes).
156 ; '(pc)' in the following doesn't include the instruction itself; it is
157 ; calculated as if the instruction had zero size.
158 (define_attr "length" ""
159 (if_then_else (eq_attr "type" "branch")
160 (if_then_else (and (ge (minus (match_dup 0) (pc))
161 (const_int -32768))
162 (lt (minus (match_dup 0) (pc))
163 (const_int 32764)))
164 (const_int 4)
165 (const_int 8))
166 (const_int 4)))
168 ;; Processor type -- this attribute must exactly match the processor_type
169 ;; enumeration in rs6000.h.
171 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
172 (const (symbol_ref "rs6000_cpu_attr")))
175 ;; If this instruction is microcoded on the CELL processor
176 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
177 (define_attr "cell_micro" "not,conditional,always"
178 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
179 (const_string "always")
180 (const_string "not")))
182 (automata_option "ndfa")
184 (include "rs64.md")
185 (include "mpc.md")
186 (include "40x.md")
187 (include "440.md")
188 (include "476.md")
189 (include "601.md")
190 (include "603.md")
191 (include "6xx.md")
192 (include "7xx.md")
193 (include "7450.md")
194 (include "8540.md")
195 (include "e300c2c3.md")
196 (include "e500mc.md")
197 (include "e500mc64.md")
198 (include "e5500.md")
199 (include "e6500.md")
200 (include "power4.md")
201 (include "power5.md")
202 (include "power6.md")
203 (include "power7.md")
204 (include "cell.md")
205 (include "xfpu.md")
206 (include "a2.md")
207 (include "titan.md")
209 (include "predicates.md")
210 (include "constraints.md")
212 (include "darwin.md")
214 \f
215 ;; Mode iterators
217 ; This mode iterator allows :GPR to be used to indicate the allowable size
218 ; of whole values in GPRs.
219 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
221 ; Any supported integer mode.
222 (define_mode_iterator INT [QI HI SI DI TI PTI])
224 ; Any supported integer mode that fits in one register.
225 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
227 ; extend modes for DImode
228 (define_mode_iterator QHSI [QI HI SI])
230 ; SImode or DImode, even if DImode doesn't fit in GPRs.
231 (define_mode_iterator SDI [SI DI])
233 ; The size of a pointer. Also, the size of the value that a record-condition
234 ; (one with a '.') will compare; and the size used for arithmetic carries.
235 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
237 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
238 ; PTImode is GPR only)
239 (define_mode_iterator TI2 [TI PTI])
241 ; Any hardware-supported floating-point mode
242 (define_mode_iterator FP [
243 (SF "TARGET_HARD_FLOAT
244 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
245 (DF "TARGET_HARD_FLOAT
246 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
247 (TF "!TARGET_IEEEQUAD
248 && TARGET_HARD_FLOAT
249 && (TARGET_FPRS || TARGET_E500_DOUBLE)
250 && TARGET_LONG_DOUBLE_128")
251 (DD "TARGET_DFP")
252 (TD "TARGET_DFP")])
254 ; Any fma capable floating-point mode.
255 (define_mode_iterator FMA_F [
256 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
257 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
258 || VECTOR_UNIT_VSX_P (DFmode)")
259 (V2SF "TARGET_PAIRED_FLOAT")
260 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
261 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
262 ])
264 ; Floating point move iterators to combine binary and decimal moves
265 (define_mode_iterator FMOVE32 [SF SD])
266 (define_mode_iterator FMOVE64 [DF DD])
267 (define_mode_iterator FMOVE64X [DI DF DD])
268 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
269 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
271 ; Whether a floating point move is ok, don't allow SD without hardware FP
272 (define_mode_attr fmove_ok [(SF "")
273 (DF "")
274 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
275 (DD "")])
277 ; Convert REAL_VALUE to the appropriate bits
278 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
279 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
280 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
281 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
283 ; Definitions for load to 32-bit fpr register
284 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
285 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
286 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
288 ; Definitions for store from 32-bit fpr register
289 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
290 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
291 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
293 ; These modes do not fit in integer registers in 32-bit mode.
294 ; but on e500v2, the gpr are 64 bit registers
295 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
297 ; Iterator for reciprocal estimate instructions
298 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
300 ; Iterator for just SF/DF
301 (define_mode_iterator SFDF [SF DF])
303 ; Conditional returns.
304 (define_code_iterator any_return [return simple_return])
305 (define_code_attr return_pred [(return "direct_return ()")
306 (simple_return "1")])
307 (define_code_attr return_str [(return "") (simple_return "simple_")])
309 ; Various instructions that come in SI and DI forms.
310 ; A generic w/d attribute, for things like cmpw/cmpd.
311 (define_mode_attr wd [(QI "b")
312 (HI "h")
313 (SI "w")
314 (DI "d")
315 (V16QI "b")
316 (V8HI "h")
317 (V4SI "w")
318 (V2DI "d")])
320 ; DImode bits
321 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
323 ;; ISEL/ISEL64 target selection
324 (define_mode_attr sel [(SI "") (DI "64")])
326 ;; Suffix for reload patterns
327 (define_mode_attr ptrsize [(SI "32bit")
328 (DI "64bit")])
330 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
331 (DI "TARGET_64BIT")])
333 (define_mode_attr mptrsize [(SI "si")
334 (DI "di")])
336 (define_mode_attr ptrload [(SI "lwz")
337 (DI "ld")])
339 (define_mode_attr ptrm [(SI "m")
340 (DI "Y")])
342 (define_mode_attr rreg [(SF "f")
343 (DF "ws")
344 (V4SF "wf")
345 (V2DF "wd")])
347 (define_mode_attr rreg2 [(SF "f")
348 (DF "d")])
350 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
351 (DF "TARGET_FCFID")])
353 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
354 (DF "TARGET_E500_DOUBLE")])
356 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
357 (DF "TARGET_DOUBLE_FLOAT")])
358 \f
359 ;; Start with fixed-point load and store insns. Here we put only the more
360 ;; complex forms. Basic data transfer is done later.
362 (define_expand "zero_extend<mode>di2"
363 [(set (match_operand:DI 0 "gpc_reg_operand" "")
364 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
365 "TARGET_POWERPC64"
366 "")
368 (define_insn "*zero_extend<mode>di2_internal1"
369 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
370 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
371 "TARGET_POWERPC64"
372 "@
373 l<wd>z%U1%X1 %0,%1
374 rldicl %0,%1,0,<dbits>"
375 [(set_attr_alternative "type"
376 [(if_then_else
377 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
378 (const_string "load_ux")
379 (if_then_else
380 (match_test "update_address_mem (operands[1], VOIDmode)")
381 (const_string "load_u")
382 (const_string "load")))
383 (const_string "*")])])
385 (define_insn "*zero_extend<mode>di2_internal2"
386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
387 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
388 (const_int 0)))
389 (clobber (match_scratch:DI 2 "=r,r"))]
390 "TARGET_64BIT"
391 "@
392 rldicl. %2,%1,0,<dbits>
393 #"
394 [(set_attr "type" "compare")
395 (set_attr "length" "4,8")])
397 (define_split
398 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
399 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
400 (const_int 0)))
401 (clobber (match_scratch:DI 2 ""))]
402 "TARGET_POWERPC64 && reload_completed"
403 [(set (match_dup 2)
404 (zero_extend:DI (match_dup 1)))
405 (set (match_dup 0)
406 (compare:CC (match_dup 2)
407 (const_int 0)))]
408 "")
410 (define_insn "*zero_extend<mode>di2_internal3"
411 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
412 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
413 (const_int 0)))
414 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
415 (zero_extend:DI (match_dup 1)))]
416 "TARGET_64BIT"
417 "@
418 rldicl. %0,%1,0,<dbits>
419 #"
420 [(set_attr "type" "compare")
421 (set_attr "length" "4,8")])
423 (define_split
424 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
425 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
426 (const_int 0)))
427 (set (match_operand:DI 0 "gpc_reg_operand" "")
428 (zero_extend:DI (match_dup 1)))]
429 "TARGET_POWERPC64 && reload_completed"
430 [(set (match_dup 0)
431 (zero_extend:DI (match_dup 1)))
432 (set (match_dup 2)
433 (compare:CC (match_dup 0)
434 (const_int 0)))]
435 "")
437 (define_insn "extendqidi2"
438 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
439 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
440 "TARGET_POWERPC64"
441 "extsb %0,%1"
442 [(set_attr "type" "exts")])
444 (define_insn ""
445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
446 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
447 (const_int 0)))
448 (clobber (match_scratch:DI 2 "=r,r"))]
449 "TARGET_64BIT"
450 "@
451 extsb. %2,%1
452 #"
453 [(set_attr "type" "compare")
454 (set_attr "length" "4,8")])
456 (define_split
457 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
458 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
459 (const_int 0)))
460 (clobber (match_scratch:DI 2 ""))]
461 "TARGET_POWERPC64 && reload_completed"
462 [(set (match_dup 2)
463 (sign_extend:DI (match_dup 1)))
464 (set (match_dup 0)
465 (compare:CC (match_dup 2)
466 (const_int 0)))]
467 "")
469 (define_insn ""
470 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
471 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
472 (const_int 0)))
473 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
474 (sign_extend:DI (match_dup 1)))]
475 "TARGET_64BIT"
476 "@
477 extsb. %0,%1
478 #"
479 [(set_attr "type" "compare")
480 (set_attr "length" "4,8")])
482 (define_split
483 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
484 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
485 (const_int 0)))
486 (set (match_operand:DI 0 "gpc_reg_operand" "")
487 (sign_extend:DI (match_dup 1)))]
488 "TARGET_POWERPC64 && reload_completed"
489 [(set (match_dup 0)
490 (sign_extend:DI (match_dup 1)))
491 (set (match_dup 2)
492 (compare:CC (match_dup 0)
493 (const_int 0)))]
494 "")
496 (define_expand "extendhidi2"
497 [(set (match_operand:DI 0 "gpc_reg_operand" "")
498 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
499 "TARGET_POWERPC64"
500 "")
502 (define_insn ""
503 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
504 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
505 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
506 "@
507 lha%U1%X1 %0,%1
508 extsh %0,%1"
509 [(set_attr_alternative "type"
510 [(if_then_else
511 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
512 (const_string "load_ext_ux")
513 (if_then_else
514 (match_test "update_address_mem (operands[1], VOIDmode)")
515 (const_string "load_ext_u")
516 (const_string "load_ext")))
517 (const_string "exts")])])
519 (define_insn ""
520 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
521 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
522 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
523 "extsh %0,%1"
524 [(set_attr "type" "exts")])
526 (define_insn ""
527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
528 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
529 (const_int 0)))
530 (clobber (match_scratch:DI 2 "=r,r"))]
531 "TARGET_64BIT"
532 "@
533 extsh. %2,%1
534 #"
535 [(set_attr "type" "compare")
536 (set_attr "length" "4,8")])
538 (define_split
539 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
540 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
541 (const_int 0)))
542 (clobber (match_scratch:DI 2 ""))]
543 "TARGET_POWERPC64 && reload_completed"
544 [(set (match_dup 2)
545 (sign_extend:DI (match_dup 1)))
546 (set (match_dup 0)
547 (compare:CC (match_dup 2)
548 (const_int 0)))]
549 "")
551 (define_insn ""
552 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
553 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
554 (const_int 0)))
555 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
556 (sign_extend:DI (match_dup 1)))]
557 "TARGET_64BIT"
558 "@
559 extsh. %0,%1
560 #"
561 [(set_attr "type" "compare")
562 (set_attr "length" "4,8")])
564 (define_split
565 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
566 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
567 (const_int 0)))
568 (set (match_operand:DI 0 "gpc_reg_operand" "")
569 (sign_extend:DI (match_dup 1)))]
570 "TARGET_POWERPC64 && reload_completed"
571 [(set (match_dup 0)
572 (sign_extend:DI (match_dup 1)))
573 (set (match_dup 2)
574 (compare:CC (match_dup 0)
575 (const_int 0)))]
576 "")
578 (define_expand "extendsidi2"
579 [(set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
581 "TARGET_POWERPC64"
582 "")
584 (define_insn ""
585 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
586 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
587 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
588 "@
589 lwa%U1%X1 %0,%1
590 extsw %0,%1"
591 [(set_attr_alternative "type"
592 [(if_then_else
593 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
594 (const_string "load_ext_ux")
595 (if_then_else
596 (match_test "update_address_mem (operands[1], VOIDmode)")
597 (const_string "load_ext_u")
598 (const_string "load_ext")))
599 (const_string "exts")])])
601 (define_insn ""
602 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
603 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
604 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
605 "extsw %0,%1"
606 [(set_attr "type" "exts")])
608 (define_insn ""
609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
610 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
611 (const_int 0)))
612 (clobber (match_scratch:DI 2 "=r,r"))]
613 "TARGET_64BIT"
614 "@
615 extsw. %2,%1
616 #"
617 [(set_attr "type" "compare")
618 (set_attr "length" "4,8")])
620 (define_split
621 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
622 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
623 (const_int 0)))
624 (clobber (match_scratch:DI 2 ""))]
625 "TARGET_POWERPC64 && reload_completed"
626 [(set (match_dup 2)
627 (sign_extend:DI (match_dup 1)))
628 (set (match_dup 0)
629 (compare:CC (match_dup 2)
630 (const_int 0)))]
631 "")
633 (define_insn ""
634 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
635 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
636 (const_int 0)))
637 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
638 (sign_extend:DI (match_dup 1)))]
639 "TARGET_64BIT"
640 "@
641 extsw. %0,%1
642 #"
643 [(set_attr "type" "compare")
644 (set_attr "length" "4,8")])
646 (define_split
647 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
648 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
649 (const_int 0)))
650 (set (match_operand:DI 0 "gpc_reg_operand" "")
651 (sign_extend:DI (match_dup 1)))]
652 "TARGET_POWERPC64 && reload_completed"
653 [(set (match_dup 0)
654 (sign_extend:DI (match_dup 1)))
655 (set (match_dup 2)
656 (compare:CC (match_dup 0)
657 (const_int 0)))]
658 "")
660 (define_expand "zero_extendqisi2"
661 [(set (match_operand:SI 0 "gpc_reg_operand" "")
662 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
663 ""
664 "")
666 (define_insn ""
667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
668 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
669 ""
670 "@
671 lbz%U1%X1 %0,%1
672 rlwinm %0,%1,0,0xff"
673 [(set_attr_alternative "type"
674 [(if_then_else
675 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
676 (const_string "load_ux")
677 (if_then_else
678 (match_test "update_address_mem (operands[1], VOIDmode)")
679 (const_string "load_u")
680 (const_string "load")))
681 (const_string "*")])])
683 (define_insn ""
684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
686 (const_int 0)))
687 (clobber (match_scratch:SI 2 "=r,r"))]
688 ""
689 "@
690 andi. %2,%1,0xff
691 #"
692 [(set_attr "type" "fast_compare,compare")
693 (set_attr "length" "4,8")])
695 (define_split
696 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
697 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
698 (const_int 0)))
699 (clobber (match_scratch:SI 2 ""))]
700 "reload_completed"
701 [(set (match_dup 2)
702 (zero_extend:SI (match_dup 1)))
703 (set (match_dup 0)
704 (compare:CC (match_dup 2)
705 (const_int 0)))]
706 "")
708 (define_insn ""
709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
710 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
711 (const_int 0)))
712 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:SI (match_dup 1)))]
714 ""
715 "@
716 andi. %0,%1,0xff
717 #"
718 [(set_attr "type" "fast_compare,compare")
719 (set_attr "length" "4,8")])
721 (define_split
722 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
723 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
724 (const_int 0)))
725 (set (match_operand:SI 0 "gpc_reg_operand" "")
726 (zero_extend:SI (match_dup 1)))]
727 "reload_completed"
728 [(set (match_dup 0)
729 (zero_extend:SI (match_dup 1)))
730 (set (match_dup 2)
731 (compare:CC (match_dup 0)
732 (const_int 0)))]
733 "")
735 (define_insn "extendqisi2"
736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
737 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
738 ""
739 "extsb %0,%1"
740 [(set_attr "type" "exts")])
742 (define_insn ""
743 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
744 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
745 (const_int 0)))
746 (clobber (match_scratch:SI 2 "=r,r"))]
747 ""
748 "@
749 extsb. %2,%1
750 #"
751 [(set_attr "type" "compare")
752 (set_attr "length" "4,8")])
754 (define_split
755 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
756 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
757 (const_int 0)))
758 (clobber (match_scratch:SI 2 ""))]
759 "reload_completed"
760 [(set (match_dup 2)
761 (sign_extend:SI (match_dup 1)))
762 (set (match_dup 0)
763 (compare:CC (match_dup 2)
764 (const_int 0)))]
765 "")
767 (define_insn ""
768 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
769 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
770 (const_int 0)))
771 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
772 (sign_extend:SI (match_dup 1)))]
773 ""
774 "@
775 extsb. %0,%1
776 #"
777 [(set_attr "type" "compare")
778 (set_attr "length" "4,8")])
780 (define_split
781 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
782 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
783 (const_int 0)))
784 (set (match_operand:SI 0 "gpc_reg_operand" "")
785 (sign_extend:SI (match_dup 1)))]
786 "reload_completed"
787 [(set (match_dup 0)
788 (sign_extend:SI (match_dup 1)))
789 (set (match_dup 2)
790 (compare:CC (match_dup 0)
791 (const_int 0)))]
792 "")
794 (define_insn ""
795 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
796 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
797 ""
798 "@
799 lbz%U1%X1 %0,%1
800 rlwinm %0,%1,0,0xff"
801 [(set_attr_alternative "type"
802 [(if_then_else
803 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
804 (const_string "load_ux")
805 (if_then_else
806 (match_test "update_address_mem (operands[1], VOIDmode)")
807 (const_string "load_u")
808 (const_string "load")))
809 (const_string "*")])])
811 (define_insn ""
812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
813 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
814 (const_int 0)))
815 (clobber (match_scratch:HI 2 "=r,r"))]
816 ""
817 "@
818 andi. %2,%1,0xff
819 #"
820 [(set_attr "type" "fast_compare,compare")
821 (set_attr "length" "4,8")])
823 (define_split
824 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
825 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
826 (const_int 0)))
827 (clobber (match_scratch:HI 2 ""))]
828 "reload_completed"
829 [(set (match_dup 2)
830 (zero_extend:HI (match_dup 1)))
831 (set (match_dup 0)
832 (compare:CC (match_dup 2)
833 (const_int 0)))]
834 "")
836 (define_insn ""
837 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
838 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
839 (const_int 0)))
840 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
841 (zero_extend:HI (match_dup 1)))]
842 ""
843 "@
844 andi. %0,%1,0xff
845 #"
846 [(set_attr "type" "fast_compare,compare")
847 (set_attr "length" "4,8")])
849 (define_split
850 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
851 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
852 (const_int 0)))
853 (set (match_operand:HI 0 "gpc_reg_operand" "")
854 (zero_extend:HI (match_dup 1)))]
855 "reload_completed"
856 [(set (match_dup 0)
857 (zero_extend:HI (match_dup 1)))
858 (set (match_dup 2)
859 (compare:CC (match_dup 0)
860 (const_int 0)))]
861 "")
863 (define_insn "extendqihi2"
864 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
865 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
866 ""
867 "extsb %0,%1"
868 [(set_attr "type" "exts")])
870 (define_insn ""
871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
872 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
873 (const_int 0)))
874 (clobber (match_scratch:HI 2 "=r,r"))]
875 ""
876 "@
877 extsb. %2,%1
878 #"
879 [(set_attr "type" "compare")
880 (set_attr "length" "4,8")])
882 (define_split
883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
884 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
885 (const_int 0)))
886 (clobber (match_scratch:HI 2 ""))]
887 "reload_completed"
888 [(set (match_dup 2)
889 (sign_extend:HI (match_dup 1)))
890 (set (match_dup 0)
891 (compare:CC (match_dup 2)
892 (const_int 0)))]
893 "")
895 (define_insn ""
896 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
897 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
898 (const_int 0)))
899 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
900 (sign_extend:HI (match_dup 1)))]
901 ""
902 "@
903 extsb. %0,%1
904 #"
905 [(set_attr "type" "compare")
906 (set_attr "length" "4,8")])
908 (define_split
909 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
910 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
911 (const_int 0)))
912 (set (match_operand:HI 0 "gpc_reg_operand" "")
913 (sign_extend:HI (match_dup 1)))]
914 "reload_completed"
915 [(set (match_dup 0)
916 (sign_extend:HI (match_dup 1)))
917 (set (match_dup 2)
918 (compare:CC (match_dup 0)
919 (const_int 0)))]
920 "")
922 (define_expand "zero_extendhisi2"
923 [(set (match_operand:SI 0 "gpc_reg_operand" "")
924 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
925 ""
926 "")
928 (define_insn ""
929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
930 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
931 ""
932 "@
933 lhz%U1%X1 %0,%1
934 rlwinm %0,%1,0,0xffff"
935 [(set_attr_alternative "type"
936 [(if_then_else
937 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
938 (const_string "load_ux")
939 (if_then_else
940 (match_test "update_address_mem (operands[1], VOIDmode)")
941 (const_string "load_u")
942 (const_string "load")))
943 (const_string "*")])])
945 (define_insn ""
946 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
947 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
948 (const_int 0)))
949 (clobber (match_scratch:SI 2 "=r,r"))]
950 ""
951 "@
952 andi. %2,%1,0xffff
953 #"
954 [(set_attr "type" "fast_compare,compare")
955 (set_attr "length" "4,8")])
957 (define_split
958 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
959 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
960 (const_int 0)))
961 (clobber (match_scratch:SI 2 ""))]
962 "reload_completed"
963 [(set (match_dup 2)
964 (zero_extend:SI (match_dup 1)))
965 (set (match_dup 0)
966 (compare:CC (match_dup 2)
967 (const_int 0)))]
968 "")
970 (define_insn ""
971 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
972 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
973 (const_int 0)))
974 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
975 (zero_extend:SI (match_dup 1)))]
976 ""
977 "@
978 andi. %0,%1,0xffff
979 #"
980 [(set_attr "type" "fast_compare,compare")
981 (set_attr "length" "4,8")])
983 (define_split
984 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
985 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "")
988 (zero_extend:SI (match_dup 1)))]
989 "reload_completed"
990 [(set (match_dup 0)
991 (zero_extend:SI (match_dup 1)))
992 (set (match_dup 2)
993 (compare:CC (match_dup 0)
994 (const_int 0)))]
995 "")
997 (define_expand "extendhisi2"
998 [(set (match_operand:SI 0 "gpc_reg_operand" "")
999 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1000 ""
1001 "")
1003 (define_insn ""
1004 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1005 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1006 "rs6000_gen_cell_microcode"
1007 "@
1008 lha%U1%X1 %0,%1
1009 extsh %0,%1"
1010 [(set_attr_alternative "type"
1011 [(if_then_else
1012 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1013 (const_string "load_ext_ux")
1014 (if_then_else
1015 (match_test "update_address_mem (operands[1], VOIDmode)")
1016 (const_string "load_ext_u")
1017 (const_string "load_ext")))
1018 (const_string "exts")])])
1020 (define_insn ""
1021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1023 "!rs6000_gen_cell_microcode"
1024 "extsh %0,%1"
1025 [(set_attr "type" "exts")])
1027 (define_insn ""
1028 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1029 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1030 (const_int 0)))
1031 (clobber (match_scratch:SI 2 "=r,r"))]
1032 ""
1033 "@
1034 extsh. %2,%1
1035 #"
1036 [(set_attr "type" "compare")
1037 (set_attr "length" "4,8")])
1039 (define_split
1040 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1041 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1042 (const_int 0)))
1043 (clobber (match_scratch:SI 2 ""))]
1044 "reload_completed"
1045 [(set (match_dup 2)
1046 (sign_extend:SI (match_dup 1)))
1047 (set (match_dup 0)
1048 (compare:CC (match_dup 2)
1049 (const_int 0)))]
1050 "")
1052 (define_insn ""
1053 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1054 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1055 (const_int 0)))
1056 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1057 (sign_extend:SI (match_dup 1)))]
1058 ""
1059 "@
1060 extsh. %0,%1
1061 #"
1062 [(set_attr "type" "compare")
1063 (set_attr "length" "4,8")])
1065 (define_split
1066 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1067 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1068 (const_int 0)))
1069 (set (match_operand:SI 0 "gpc_reg_operand" "")
1070 (sign_extend:SI (match_dup 1)))]
1071 "reload_completed"
1072 [(set (match_dup 0)
1073 (sign_extend:SI (match_dup 1)))
1074 (set (match_dup 2)
1075 (compare:CC (match_dup 0)
1076 (const_int 0)))]
1077 "")
1078 \f
1079 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1081 (define_insn "*macchwc"
1082 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1083 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1085 (const_int 16))
1086 (sign_extend:SI
1087 (match_operand:HI 1 "gpc_reg_operand" "r")))
1088 (match_operand:SI 4 "gpc_reg_operand" "0"))
1089 (const_int 0)))
1090 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1091 (plus:SI (mult:SI (ashiftrt:SI
1092 (match_dup 2)
1093 (const_int 16))
1094 (sign_extend:SI
1095 (match_dup 1)))
1096 (match_dup 4)))]
1097 "TARGET_MULHW"
1098 "macchw. %0,%1,%2"
1099 [(set_attr "type" "imul3")])
1101 (define_insn "*macchw"
1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (plus:SI (mult:SI (ashiftrt:SI
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1105 (const_int 16))
1106 (sign_extend:SI
1107 (match_operand:HI 1 "gpc_reg_operand" "r")))
1108 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1109 "TARGET_MULHW"
1110 "macchw %0,%1,%2"
1111 [(set_attr "type" "imul3")])
1113 (define_insn "*macchwuc"
1114 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1115 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1116 (match_operand:SI 2 "gpc_reg_operand" "r")
1117 (const_int 16))
1118 (zero_extend:SI
1119 (match_operand:HI 1 "gpc_reg_operand" "r")))
1120 (match_operand:SI 4 "gpc_reg_operand" "0"))
1121 (const_int 0)))
1122 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1123 (plus:SI (mult:SI (lshiftrt:SI
1124 (match_dup 2)
1125 (const_int 16))
1126 (zero_extend:SI
1127 (match_dup 1)))
1128 (match_dup 4)))]
1129 "TARGET_MULHW"
1130 "macchwu. %0,%1,%2"
1131 [(set_attr "type" "imul3")])
1133 (define_insn "*macchwu"
1134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1135 (plus:SI (mult:SI (lshiftrt:SI
1136 (match_operand:SI 2 "gpc_reg_operand" "r")
1137 (const_int 16))
1138 (zero_extend:SI
1139 (match_operand:HI 1 "gpc_reg_operand" "r")))
1140 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1141 "TARGET_MULHW"
1142 "macchwu %0,%1,%2"
1143 [(set_attr "type" "imul3")])
1145 (define_insn "*machhwc"
1146 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1147 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1148 (match_operand:SI 1 "gpc_reg_operand" "%r")
1149 (const_int 16))
1150 (ashiftrt:SI
1151 (match_operand:SI 2 "gpc_reg_operand" "r")
1152 (const_int 16)))
1153 (match_operand:SI 4 "gpc_reg_operand" "0"))
1154 (const_int 0)))
1155 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1156 (plus:SI (mult:SI (ashiftrt:SI
1157 (match_dup 1)
1158 (const_int 16))
1159 (ashiftrt:SI
1160 (match_dup 2)
1161 (const_int 16)))
1162 (match_dup 4)))]
1163 "TARGET_MULHW"
1164 "machhw. %0,%1,%2"
1165 [(set_attr "type" "imul3")])
1167 (define_insn "*machhw"
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1169 (plus:SI (mult:SI (ashiftrt:SI
1170 (match_operand:SI 1 "gpc_reg_operand" "%r")
1171 (const_int 16))
1172 (ashiftrt:SI
1173 (match_operand:SI 2 "gpc_reg_operand" "r")
1174 (const_int 16)))
1175 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1176 "TARGET_MULHW"
1177 "machhw %0,%1,%2"
1178 [(set_attr "type" "imul3")])
1180 (define_insn "*machhwuc"
1181 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1182 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1183 (match_operand:SI 1 "gpc_reg_operand" "%r")
1184 (const_int 16))
1185 (lshiftrt:SI
1186 (match_operand:SI 2 "gpc_reg_operand" "r")
1187 (const_int 16)))
1188 (match_operand:SI 4 "gpc_reg_operand" "0"))
1189 (const_int 0)))
1190 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (plus:SI (mult:SI (lshiftrt:SI
1192 (match_dup 1)
1193 (const_int 16))
1194 (lshiftrt:SI
1195 (match_dup 2)
1196 (const_int 16)))
1197 (match_dup 4)))]
1198 "TARGET_MULHW"
1199 "machhwu. %0,%1,%2"
1200 [(set_attr "type" "imul3")])
1202 (define_insn "*machhwu"
1203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1204 (plus:SI (mult:SI (lshiftrt:SI
1205 (match_operand:SI 1 "gpc_reg_operand" "%r")
1206 (const_int 16))
1207 (lshiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1209 (const_int 16)))
1210 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1211 "TARGET_MULHW"
1212 "machhwu %0,%1,%2"
1213 [(set_attr "type" "imul3")])
1215 (define_insn "*maclhwc"
1216 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1217 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1218 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1219 (sign_extend:SI
1220 (match_operand:HI 2 "gpc_reg_operand" "r")))
1221 (match_operand:SI 4 "gpc_reg_operand" "0"))
1222 (const_int 0)))
1223 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1224 (plus:SI (mult:SI (sign_extend:SI
1225 (match_dup 1))
1226 (sign_extend:SI
1227 (match_dup 2)))
1228 (match_dup 4)))]
1229 "TARGET_MULHW"
1230 "maclhw. %0,%1,%2"
1231 [(set_attr "type" "imul3")])
1233 (define_insn "*maclhw"
1234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1235 (plus:SI (mult:SI (sign_extend:SI
1236 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1237 (sign_extend:SI
1238 (match_operand:HI 2 "gpc_reg_operand" "r")))
1239 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1240 "TARGET_MULHW"
1241 "maclhw %0,%1,%2"
1242 [(set_attr "type" "imul3")])
1244 (define_insn "*maclhwuc"
1245 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1246 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1247 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1248 (zero_extend:SI
1249 (match_operand:HI 2 "gpc_reg_operand" "r")))
1250 (match_operand:SI 4 "gpc_reg_operand" "0"))
1251 (const_int 0)))
1252 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1253 (plus:SI (mult:SI (zero_extend:SI
1254 (match_dup 1))
1255 (zero_extend:SI
1256 (match_dup 2)))
1257 (match_dup 4)))]
1258 "TARGET_MULHW"
1259 "maclhwu. %0,%1,%2"
1260 [(set_attr "type" "imul3")])
1262 (define_insn "*maclhwu"
1263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1264 (plus:SI (mult:SI (zero_extend:SI
1265 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1266 (zero_extend:SI
1267 (match_operand:HI 2 "gpc_reg_operand" "r")))
1268 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1269 "TARGET_MULHW"
1270 "maclhwu %0,%1,%2"
1271 [(set_attr "type" "imul3")])
1273 (define_insn "*nmacchwc"
1274 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1275 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1276 (mult:SI (ashiftrt:SI
1277 (match_operand:SI 2 "gpc_reg_operand" "r")
1278 (const_int 16))
1279 (sign_extend:SI
1280 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1281 (const_int 0)))
1282 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1283 (minus:SI (match_dup 4)
1284 (mult:SI (ashiftrt:SI
1285 (match_dup 2)
1286 (const_int 16))
1287 (sign_extend:SI
1288 (match_dup 1)))))]
1289 "TARGET_MULHW"
1290 "nmacchw. %0,%1,%2"
1291 [(set_attr "type" "imul3")])
1293 (define_insn "*nmacchw"
1294 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1295 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1296 (mult:SI (ashiftrt:SI
1297 (match_operand:SI 2 "gpc_reg_operand" "r")
1298 (const_int 16))
1299 (sign_extend:SI
1300 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1301 "TARGET_MULHW"
1302 "nmacchw %0,%1,%2"
1303 [(set_attr "type" "imul3")])
1305 (define_insn "*nmachhwc"
1306 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1307 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1308 (mult:SI (ashiftrt:SI
1309 (match_operand:SI 1 "gpc_reg_operand" "%r")
1310 (const_int 16))
1311 (ashiftrt:SI
1312 (match_operand:SI 2 "gpc_reg_operand" "r")
1313 (const_int 16))))
1314 (const_int 0)))
1315 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (minus:SI (match_dup 4)
1317 (mult:SI (ashiftrt:SI
1318 (match_dup 1)
1319 (const_int 16))
1320 (ashiftrt:SI
1321 (match_dup 2)
1322 (const_int 16)))))]
1323 "TARGET_MULHW"
1324 "nmachhw. %0,%1,%2"
1325 [(set_attr "type" "imul3")])
1327 (define_insn "*nmachhw"
1328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1330 (mult:SI (ashiftrt:SI
1331 (match_operand:SI 1 "gpc_reg_operand" "%r")
1332 (const_int 16))
1333 (ashiftrt:SI
1334 (match_operand:SI 2 "gpc_reg_operand" "r")
1335 (const_int 16)))))]
1336 "TARGET_MULHW"
1337 "nmachhw %0,%1,%2"
1338 [(set_attr "type" "imul3")])
1340 (define_insn "*nmaclhwc"
1341 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1342 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1343 (mult:SI (sign_extend:SI
1344 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1345 (sign_extend:SI
1346 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1347 (const_int 0)))
1348 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1349 (minus:SI (match_dup 4)
1350 (mult:SI (sign_extend:SI
1351 (match_dup 1))
1352 (sign_extend:SI
1353 (match_dup 2)))))]
1354 "TARGET_MULHW"
1355 "nmaclhw. %0,%1,%2"
1356 [(set_attr "type" "imul3")])
1358 (define_insn "*nmaclhw"
1359 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1360 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1361 (mult:SI (sign_extend:SI
1362 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1363 (sign_extend:SI
1364 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1365 "TARGET_MULHW"
1366 "nmaclhw %0,%1,%2"
1367 [(set_attr "type" "imul3")])
1369 (define_insn "*mulchwc"
1370 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1371 (compare:CC (mult:SI (ashiftrt:SI
1372 (match_operand:SI 2 "gpc_reg_operand" "r")
1373 (const_int 16))
1374 (sign_extend:SI
1375 (match_operand:HI 1 "gpc_reg_operand" "r")))
1376 (const_int 0)))
1377 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1378 (mult:SI (ashiftrt:SI
1379 (match_dup 2)
1380 (const_int 16))
1381 (sign_extend:SI
1382 (match_dup 1))))]
1383 "TARGET_MULHW"
1384 "mulchw. %0,%1,%2"
1385 [(set_attr "type" "imul3")])
1387 (define_insn "*mulchw"
1388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1389 (mult:SI (ashiftrt:SI
1390 (match_operand:SI 2 "gpc_reg_operand" "r")
1391 (const_int 16))
1392 (sign_extend:SI
1393 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1394 "TARGET_MULHW"
1395 "mulchw %0,%1,%2"
1396 [(set_attr "type" "imul3")])
1398 (define_insn "*mulchwuc"
1399 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1400 (compare:CC (mult:SI (lshiftrt:SI
1401 (match_operand:SI 2 "gpc_reg_operand" "r")
1402 (const_int 16))
1403 (zero_extend:SI
1404 (match_operand:HI 1 "gpc_reg_operand" "r")))
1405 (const_int 0)))
1406 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407 (mult:SI (lshiftrt:SI
1408 (match_dup 2)
1409 (const_int 16))
1410 (zero_extend:SI
1411 (match_dup 1))))]
1412 "TARGET_MULHW"
1413 "mulchwu. %0,%1,%2"
1414 [(set_attr "type" "imul3")])
1416 (define_insn "*mulchwu"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1418 (mult:SI (lshiftrt:SI
1419 (match_operand:SI 2 "gpc_reg_operand" "r")
1420 (const_int 16))
1421 (zero_extend:SI
1422 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1423 "TARGET_MULHW"
1424 "mulchwu %0,%1,%2"
1425 [(set_attr "type" "imul3")])
1427 (define_insn "*mulhhwc"
1428 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1429 (compare:CC (mult:SI (ashiftrt:SI
1430 (match_operand:SI 1 "gpc_reg_operand" "%r")
1431 (const_int 16))
1432 (ashiftrt:SI
1433 (match_operand:SI 2 "gpc_reg_operand" "r")
1434 (const_int 16)))
1435 (const_int 0)))
1436 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1437 (mult:SI (ashiftrt:SI
1438 (match_dup 1)
1439 (const_int 16))
1440 (ashiftrt:SI
1441 (match_dup 2)
1442 (const_int 16))))]
1443 "TARGET_MULHW"
1444 "mulhhw. %0,%1,%2"
1445 [(set_attr "type" "imul3")])
1447 (define_insn "*mulhhw"
1448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1449 (mult:SI (ashiftrt:SI
1450 (match_operand:SI 1 "gpc_reg_operand" "%r")
1451 (const_int 16))
1452 (ashiftrt:SI
1453 (match_operand:SI 2 "gpc_reg_operand" "r")
1454 (const_int 16))))]
1455 "TARGET_MULHW"
1456 "mulhhw %0,%1,%2"
1457 [(set_attr "type" "imul3")])
1459 (define_insn "*mulhhwuc"
1460 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1461 (compare:CC (mult:SI (lshiftrt:SI
1462 (match_operand:SI 1 "gpc_reg_operand" "%r")
1463 (const_int 16))
1464 (lshiftrt:SI
1465 (match_operand:SI 2 "gpc_reg_operand" "r")
1466 (const_int 16)))
1467 (const_int 0)))
1468 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1469 (mult:SI (lshiftrt:SI
1470 (match_dup 1)
1471 (const_int 16))
1472 (lshiftrt:SI
1473 (match_dup 2)
1474 (const_int 16))))]
1475 "TARGET_MULHW"
1476 "mulhhwu. %0,%1,%2"
1477 [(set_attr "type" "imul3")])
1479 (define_insn "*mulhhwu"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (mult:SI (lshiftrt:SI
1482 (match_operand:SI 1 "gpc_reg_operand" "%r")
1483 (const_int 16))
1484 (lshiftrt:SI
1485 (match_operand:SI 2 "gpc_reg_operand" "r")
1486 (const_int 16))))]
1487 "TARGET_MULHW"
1488 "mulhhwu %0,%1,%2"
1489 [(set_attr "type" "imul3")])
1491 (define_insn "*mullhwc"
1492 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1493 (compare:CC (mult:SI (sign_extend:SI
1494 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1495 (sign_extend:SI
1496 (match_operand:HI 2 "gpc_reg_operand" "r")))
1497 (const_int 0)))
1498 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1499 (mult:SI (sign_extend:SI
1500 (match_dup 1))
1501 (sign_extend:SI
1502 (match_dup 2))))]
1503 "TARGET_MULHW"
1504 "mullhw. %0,%1,%2"
1505 [(set_attr "type" "imul3")])
1507 (define_insn "*mullhw"
1508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1509 (mult:SI (sign_extend:SI
1510 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1511 (sign_extend:SI
1512 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1513 "TARGET_MULHW"
1514 "mullhw %0,%1,%2"
1515 [(set_attr "type" "imul3")])
1517 (define_insn "*mullhwuc"
1518 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1519 (compare:CC (mult:SI (zero_extend:SI
1520 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1521 (zero_extend:SI
1522 (match_operand:HI 2 "gpc_reg_operand" "r")))
1523 (const_int 0)))
1524 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1525 (mult:SI (zero_extend:SI
1526 (match_dup 1))
1527 (zero_extend:SI
1528 (match_dup 2))))]
1529 "TARGET_MULHW"
1530 "mullhwu. %0,%1,%2"
1531 [(set_attr "type" "imul3")])
1533 (define_insn "*mullhwu"
1534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1535 (mult:SI (zero_extend:SI
1536 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1537 (zero_extend:SI
1538 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1539 "TARGET_MULHW"
1540 "mullhwu %0,%1,%2"
1541 [(set_attr "type" "imul3")])
1542 \f
1543 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1544 (define_insn "dlmzb"
1545 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1546 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1547 (match_operand:SI 2 "gpc_reg_operand" "r")]
1548 UNSPEC_DLMZB_CR))
1549 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1550 (unspec:SI [(match_dup 1)
1551 (match_dup 2)]
1552 UNSPEC_DLMZB))]
1553 "TARGET_DLMZB"
1554 "dlmzb. %0,%1,%2")
1556 (define_expand "strlensi"
1557 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1558 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1559 (match_operand:QI 2 "const_int_operand" "")
1560 (match_operand 3 "const_int_operand" "")]
1561 UNSPEC_DLMZB_STRLEN))
1562 (clobber (match_scratch:CC 4 "=x"))]
1563 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1564 {
1565 rtx result = operands[0];
1566 rtx src = operands[1];
1567 rtx search_char = operands[2];
1568 rtx align = operands[3];
1569 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1570 rtx loop_label, end_label, mem, cr0, cond;
1571 if (search_char != const0_rtx
1572 || GET_CODE (align) != CONST_INT
1573 || INTVAL (align) < 8)
1574 FAIL;
1575 word1 = gen_reg_rtx (SImode);
1576 word2 = gen_reg_rtx (SImode);
1577 scratch_dlmzb = gen_reg_rtx (SImode);
1578 scratch_string = gen_reg_rtx (Pmode);
1579 loop_label = gen_label_rtx ();
1580 end_label = gen_label_rtx ();
1581 addr = force_reg (Pmode, XEXP (src, 0));
1582 emit_move_insn (scratch_string, addr);
1583 emit_label (loop_label);
1584 mem = change_address (src, SImode, scratch_string);
1585 emit_move_insn (word1, mem);
1586 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1587 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1588 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1589 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1590 emit_jump_insn (gen_rtx_SET (VOIDmode,
1591 pc_rtx,
1592 gen_rtx_IF_THEN_ELSE (VOIDmode,
1593 cond,
1594 gen_rtx_LABEL_REF
1595 (VOIDmode,
1596 end_label),
1597 pc_rtx)));
1598 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1599 emit_jump_insn (gen_rtx_SET (VOIDmode,
1600 pc_rtx,
1601 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1602 emit_barrier ();
1603 emit_label (end_label);
1604 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1605 emit_insn (gen_subsi3 (result, scratch_string, addr));
1606 emit_insn (gen_subsi3 (result, result, const1_rtx));
1607 DONE;
1608 })
1609 \f
1610 ;; Fixed-point arithmetic insns.
1612 (define_expand "add<mode>3"
1613 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1614 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1615 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1616 ""
1617 {
1618 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1619 {
1620 if (non_short_cint_operand (operands[2], DImode))
1621 FAIL;
1622 }
1623 else if (GET_CODE (operands[2]) == CONST_INT
1624 && ! add_operand (operands[2], <MODE>mode))
1625 {
1626 rtx tmp = ((!can_create_pseudo_p ()
1627 || rtx_equal_p (operands[0], operands[1]))
1628 ? operands[0] : gen_reg_rtx (<MODE>mode));
1630 HOST_WIDE_INT val = INTVAL (operands[2]);
1631 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1632 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1634 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1635 FAIL;
1637 /* The ordering here is important for the prolog expander.
1638 When space is allocated from the stack, adding 'low' first may
1639 produce a temporary deallocation (which would be bad). */
1640 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1641 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1642 DONE;
1643 }
1644 })
1646 ;; Discourage ai/addic because of carry but provide it in an alternative
1647 ;; allowing register zero as source.
1648 (define_insn "*add<mode>3_internal1"
1649 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1650 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1651 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1652 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1653 "@
1654 add %0,%1,%2
1655 addi %0,%1,%2
1656 addic %0,%1,%2
1657 addis %0,%1,%v2"
1658 [(set_attr "length" "4,4,4,4")])
1660 (define_insn "addsi3_high"
1661 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1662 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1663 (high:SI (match_operand 2 "" ""))))]
1664 "TARGET_MACHO && !TARGET_64BIT"
1665 "addis %0,%1,ha16(%2)"
1666 [(set_attr "length" "4")])
1668 (define_insn "*add<mode>3_internal2"
1669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1670 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1671 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1672 (const_int 0)))
1673 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1674 ""
1675 "@
1676 add. %3,%1,%2
1677 addic. %3,%1,%2
1678 #
1679 #"
1680 [(set_attr "type" "fast_compare,compare,compare,compare")
1681 (set_attr "length" "4,4,8,8")])
1683 (define_split
1684 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1685 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1686 (match_operand:GPR 2 "reg_or_short_operand" ""))
1687 (const_int 0)))
1688 (clobber (match_scratch:GPR 3 ""))]
1689 "reload_completed"
1690 [(set (match_dup 3)
1691 (plus:GPR (match_dup 1)
1692 (match_dup 2)))
1693 (set (match_dup 0)
1694 (compare:CC (match_dup 3)
1695 (const_int 0)))]
1696 "")
1698 (define_insn "*add<mode>3_internal3"
1699 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1700 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1701 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1702 (const_int 0)))
1703 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1704 (plus:P (match_dup 1)
1705 (match_dup 2)))]
1706 ""
1707 "@
1708 add. %0,%1,%2
1709 addic. %0,%1,%2
1710 #
1711 #"
1712 [(set_attr "type" "fast_compare,compare,compare,compare")
1713 (set_attr "length" "4,4,8,8")])
1715 (define_split
1716 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1717 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1718 (match_operand:P 2 "reg_or_short_operand" ""))
1719 (const_int 0)))
1720 (set (match_operand:P 0 "gpc_reg_operand" "")
1721 (plus:P (match_dup 1) (match_dup 2)))]
1722 "reload_completed"
1723 [(set (match_dup 0)
1724 (plus:P (match_dup 1)
1725 (match_dup 2)))
1726 (set (match_dup 3)
1727 (compare:CC (match_dup 0)
1728 (const_int 0)))]
1729 "")
1731 ;; Split an add that we can't do in one insn into two insns, each of which
1732 ;; does one 16-bit part. This is used by combine. Note that the low-order
1733 ;; add should be last in case the result gets used in an address.
1735 (define_split
1736 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1737 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1738 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1739 ""
1740 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1741 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1742 {
1743 HOST_WIDE_INT val = INTVAL (operands[2]);
1744 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1745 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1747 operands[4] = GEN_INT (low);
1748 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1749 operands[3] = GEN_INT (rest);
1750 else if (can_create_pseudo_p ())
1751 {
1752 operands[3] = gen_reg_rtx (DImode);
1753 emit_move_insn (operands[3], operands[2]);
1754 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1755 DONE;
1756 }
1757 else
1758 FAIL;
1759 })
1761 (define_insn "one_cmpl<mode>2"
1762 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1763 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1764 ""
1765 "nor %0,%1,%1")
1767 (define_insn ""
1768 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1769 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1770 (const_int 0)))
1771 (clobber (match_scratch:P 2 "=r,r"))]
1772 ""
1773 "@
1774 nor. %2,%1,%1
1775 #"
1776 [(set_attr "type" "fast_compare,compare")
1777 (set_attr "length" "4,8")])
1779 (define_split
1780 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1781 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1782 (const_int 0)))
1783 (clobber (match_scratch:P 2 ""))]
1784 "reload_completed"
1785 [(set (match_dup 2)
1786 (not:P (match_dup 1)))
1787 (set (match_dup 0)
1788 (compare:CC (match_dup 2)
1789 (const_int 0)))]
1790 "")
1792 (define_insn ""
1793 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1794 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1795 (const_int 0)))
1796 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1797 (not:P (match_dup 1)))]
1798 ""
1799 "@
1800 nor. %0,%1,%1
1801 #"
1802 [(set_attr "type" "fast_compare,compare")
1803 (set_attr "length" "4,8")])
1805 (define_split
1806 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1807 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1808 (const_int 0)))
1809 (set (match_operand:P 0 "gpc_reg_operand" "")
1810 (not:P (match_dup 1)))]
1811 "reload_completed"
1812 [(set (match_dup 0)
1813 (not:P (match_dup 1)))
1814 (set (match_dup 2)
1815 (compare:CC (match_dup 0)
1816 (const_int 0)))]
1817 "")
1819 (define_insn ""
1820 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1821 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1822 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1823 ""
1824 "@
1825 subf %0,%2,%1
1826 subfic %0,%2,%1")
1828 (define_insn ""
1829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1830 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1831 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1832 (const_int 0)))
1833 (clobber (match_scratch:P 3 "=r,r"))]
1834 ""
1835 "@
1836 subf. %3,%2,%1
1837 #"
1838 [(set_attr "type" "fast_compare")
1839 (set_attr "length" "4,8")])
1841 (define_split
1842 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1843 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1844 (match_operand:P 2 "gpc_reg_operand" ""))
1845 (const_int 0)))
1846 (clobber (match_scratch:P 3 ""))]
1847 "reload_completed"
1848 [(set (match_dup 3)
1849 (minus:P (match_dup 1)
1850 (match_dup 2)))
1851 (set (match_dup 0)
1852 (compare:CC (match_dup 3)
1853 (const_int 0)))]
1854 "")
1856 (define_insn ""
1857 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1858 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1859 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1860 (const_int 0)))
1861 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1862 (minus:P (match_dup 1)
1863 (match_dup 2)))]
1864 ""
1865 "@
1866 subf. %0,%2,%1
1867 #"
1868 [(set_attr "type" "fast_compare")
1869 (set_attr "length" "4,8")])
1871 (define_split
1872 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1873 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1874 (match_operand:P 2 "gpc_reg_operand" ""))
1875 (const_int 0)))
1876 (set (match_operand:P 0 "gpc_reg_operand" "")
1877 (minus:P (match_dup 1)
1878 (match_dup 2)))]
1879 "reload_completed"
1880 [(set (match_dup 0)
1881 (minus:P (match_dup 1)
1882 (match_dup 2)))
1883 (set (match_dup 3)
1884 (compare:CC (match_dup 0)
1885 (const_int 0)))]
1886 "")
1888 (define_expand "sub<mode>3"
1889 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1890 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1891 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1892 ""
1893 "
1894 {
1895 if (GET_CODE (operands[2]) == CONST_INT)
1896 {
1897 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1898 negate_rtx (<MODE>mode, operands[2])));
1899 DONE;
1900 }
1901 }")
1903 (define_expand "neg<mode>2"
1904 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1905 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1906 ""
1907 "")
1909 (define_insn "*neg<mode>2_internal"
1910 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1911 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1912 ""
1913 "neg %0,%1")
1915 (define_insn ""
1916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1917 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1918 (const_int 0)))
1919 (clobber (match_scratch:P 2 "=r,r"))]
1920 ""
1921 "@
1922 neg. %2,%1
1923 #"
1924 [(set_attr "type" "fast_compare")
1925 (set_attr "length" "4,8")])
1927 (define_split
1928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1929 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1930 (const_int 0)))
1931 (clobber (match_scratch:P 2 ""))]
1932 "reload_completed"
1933 [(set (match_dup 2)
1934 (neg:P (match_dup 1)))
1935 (set (match_dup 0)
1936 (compare:CC (match_dup 2)
1937 (const_int 0)))]
1938 "")
1940 (define_insn ""
1941 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1942 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1943 (const_int 0)))
1944 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1945 (neg:P (match_dup 1)))]
1946 ""
1947 "@
1948 neg. %0,%1
1949 #"
1950 [(set_attr "type" "fast_compare")
1951 (set_attr "length" "4,8")])
1953 (define_split
1954 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1955 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1956 (const_int 0)))
1957 (set (match_operand:P 0 "gpc_reg_operand" "")
1958 (neg:P (match_dup 1)))]
1959 "reload_completed"
1960 [(set (match_dup 0)
1961 (neg:P (match_dup 1)))
1962 (set (match_dup 2)
1963 (compare:CC (match_dup 0)
1964 (const_int 0)))]
1965 "")
1967 (define_insn "clz<mode>2"
1968 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1969 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1970 ""
1971 "cntlz<wd> %0,%1"
1972 [(set_attr "type" "cntlz")])
1974 (define_expand "ctz<mode>2"
1975 [(set (match_dup 2)
1976 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1977 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1978 (match_dup 2)))
1979 (clobber (scratch:CC))])
1980 (set (match_dup 4) (clz:GPR (match_dup 3)))
1981 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1982 (minus:GPR (match_dup 5) (match_dup 4)))]
1983 ""
1984 {
1985 operands[2] = gen_reg_rtx (<MODE>mode);
1986 operands[3] = gen_reg_rtx (<MODE>mode);
1987 operands[4] = gen_reg_rtx (<MODE>mode);
1988 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1989 })
1991 (define_expand "ffs<mode>2"
1992 [(set (match_dup 2)
1993 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1994 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1995 (match_dup 2)))
1996 (clobber (scratch:CC))])
1997 (set (match_dup 4) (clz:GPR (match_dup 3)))
1998 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1999 (minus:GPR (match_dup 5) (match_dup 4)))]
2000 ""
2001 {
2002 operands[2] = gen_reg_rtx (<MODE>mode);
2003 operands[3] = gen_reg_rtx (<MODE>mode);
2004 operands[4] = gen_reg_rtx (<MODE>mode);
2005 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2006 })
2008 (define_insn "popcntb<mode>2"
2009 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2010 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2011 UNSPEC_POPCNTB))]
2012 "TARGET_POPCNTB"
2013 "popcntb %0,%1"
2014 [(set_attr "length" "4")
2015 (set_attr "type" "popcnt")])
2017 (define_insn "popcntd<mode>2"
2018 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2019 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2020 "TARGET_POPCNTD"
2021 "popcnt<wd> %0,%1"
2022 [(set_attr "length" "4")
2023 (set_attr "type" "popcnt")])
2025 (define_expand "popcount<mode>2"
2026 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2027 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2028 "TARGET_POPCNTB || TARGET_POPCNTD"
2029 {
2030 rs6000_emit_popcount (operands[0], operands[1]);
2031 DONE;
2032 })
2034 (define_insn "parity<mode>2_cmpb"
2035 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2036 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2037 "TARGET_CMPB && TARGET_POPCNTB"
2038 "prty<wd> %0,%1")
2040 (define_expand "parity<mode>2"
2041 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2042 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2043 "TARGET_POPCNTB"
2044 {
2045 rs6000_emit_parity (operands[0], operands[1]);
2046 DONE;
2047 })
2049 ;; Since the hardware zeros the upper part of the register, save generating the
2050 ;; AND immediate if we are converting to unsigned
2051 (define_insn "*bswaphi2_extenddi"
2052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2053 (zero_extend:DI
2054 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2055 "TARGET_POWERPC64"
2056 "lhbrx %0,%y1"
2057 [(set_attr "length" "4")
2058 (set_attr "type" "load")])
2060 (define_insn "*bswaphi2_extendsi"
2061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2062 (zero_extend:SI
2063 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2064 ""
2065 "lhbrx %0,%y1"
2066 [(set_attr "length" "4")
2067 (set_attr "type" "load")])
2069 (define_expand "bswaphi2"
2070 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2071 (bswap:HI
2072 (match_operand:HI 1 "reg_or_mem_operand" "")))
2073 (clobber (match_scratch:SI 2 ""))])]
2074 ""
2075 {
2076 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2077 operands[1] = force_reg (HImode, operands[1]);
2078 })
2080 (define_insn "bswaphi2_internal"
2081 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2082 (bswap:HI
2083 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2084 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2085 ""
2086 "@
2087 lhbrx %0,%y1
2088 sthbrx %1,%y0
2089 #"
2090 [(set_attr "length" "4,4,12")
2091 (set_attr "type" "load,store,*")])
2093 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2094 ;; correct for -mlittle as well as -mbig.
2095 (define_split
2096 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2097 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2098 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2099 "reload_completed"
2100 [(set (match_dup 3)
2101 (zero_extract:SI (match_dup 4)
2102 (const_int 8)
2103 (const_int 16)))
2104 (set (match_dup 2)
2105 (and:SI (ashift:SI (match_dup 4)
2106 (const_int 8))
2107 (const_int 65280))) ;; 0xff00
2108 (set (match_dup 3)
2109 (ior:SI (match_dup 3)
2110 (match_dup 2)))]
2111 "
2112 {
2113 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2114 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2115 }")
2117 (define_insn "*bswapsi2_extenddi"
2118 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2119 (zero_extend:DI
2120 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2121 "TARGET_POWERPC64"
2122 "lwbrx %0,%y1"
2123 [(set_attr "length" "4")
2124 (set_attr "type" "load")])
2126 (define_expand "bswapsi2"
2127 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2128 (bswap:SI
2129 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2130 ""
2131 {
2132 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2133 operands[1] = force_reg (SImode, operands[1]);
2134 })
2136 (define_insn "*bswapsi2_internal"
2137 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2138 (bswap:SI
2139 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2140 ""
2141 "@
2142 lwbrx %0,%y1
2143 stwbrx %1,%y0
2144 #"
2145 [(set_attr "length" "4,4,12")
2146 (set_attr "type" "load,store,*")])
2148 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2149 ;; zero_extract insns do not change for -mlittle.
2150 (define_split
2151 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2152 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2153 "reload_completed"
2154 [(set (match_dup 0)
2155 (rotate:SI (match_dup 1) (const_int 8)))
2156 (set (zero_extract:SI (match_dup 0)
2157 (const_int 8)
2158 (const_int 0))
2159 (match_dup 1))
2160 (set (zero_extract:SI (match_dup 0)
2161 (const_int 8)
2162 (const_int 16))
2163 (rotate:SI (match_dup 1)
2164 (const_int 16)))]
2165 "")
2167 (define_expand "bswapdi2"
2168 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2169 (bswap:DI
2170 (match_operand:DI 1 "reg_or_mem_operand" "")))
2171 (clobber (match_scratch:DI 2 ""))
2172 (clobber (match_scratch:DI 3 ""))
2173 (clobber (match_scratch:DI 4 ""))])]
2174 ""
2175 {
2176 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2177 operands[1] = force_reg (DImode, operands[1]);
2179 if (!TARGET_POWERPC64)
2180 {
2181 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2182 that uses 64-bit registers needs the same scratch registers as 64-bit
2183 mode. */
2184 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2185 DONE;
2186 }
2187 })
2189 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2190 (define_insn "*bswapdi2_ldbrx"
2191 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2192 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2193 (clobber (match_scratch:DI 2 "=X,X,&r"))
2194 (clobber (match_scratch:DI 3 "=X,X,&r"))
2195 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2196 "TARGET_POWERPC64 && TARGET_LDBRX
2197 && (REG_P (operands[0]) || REG_P (operands[1]))"
2198 "@
2199 ldbrx %0,%y1
2200 stdbrx %1,%y0
2201 #"
2202 [(set_attr "length" "4,4,36")
2203 (set_attr "type" "load,store,*")])
2205 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2206 (define_insn "*bswapdi2_64bit"
2207 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2208 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2209 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2210 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2211 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2212 "TARGET_POWERPC64 && !TARGET_LDBRX
2213 && (REG_P (operands[0]) || REG_P (operands[1]))"
2214 "#"
2215 [(set_attr "length" "16,12,36")])
2217 (define_split
2218 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2219 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2220 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2221 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2222 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2223 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2224 [(const_int 0)]
2225 "
2226 {
2227 rtx dest = operands[0];
2228 rtx src = operands[1];
2229 rtx op2 = operands[2];
2230 rtx op3 = operands[3];
2231 rtx op4 = operands[4];
2232 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2233 BYTES_BIG_ENDIAN ? 4 : 0);
2234 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2235 BYTES_BIG_ENDIAN ? 4 : 0);
2236 rtx addr1;
2237 rtx addr2;
2238 rtx word_high;
2239 rtx word_low;
2241 addr1 = XEXP (src, 0);
2242 if (GET_CODE (addr1) == PLUS)
2243 {
2244 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2245 if (TARGET_AVOID_XFORM)
2246 {
2247 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2248 addr2 = op2;
2249 }
2250 else
2251 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2252 }
2253 else if (TARGET_AVOID_XFORM)
2254 {
2255 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2256 addr2 = op2;
2257 }
2258 else
2259 {
2260 emit_move_insn (op2, GEN_INT (4));
2261 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2262 }
2264 if (BYTES_BIG_ENDIAN)
2265 {
2266 word_high = change_address (src, SImode, addr1);
2267 word_low = change_address (src, SImode, addr2);
2268 }
2269 else
2270 {
2271 word_high = change_address (src, SImode, addr2);
2272 word_low = change_address (src, SImode, addr1);
2273 }
2275 emit_insn (gen_bswapsi2 (op3_32, word_low));
2276 emit_insn (gen_bswapsi2 (op4_32, word_high));
2277 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2278 emit_insn (gen_iordi3 (dest, dest, op4));
2279 }")
2281 (define_split
2282 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2283 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2284 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2285 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2286 (clobber (match_operand:DI 4 "" ""))]
2287 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2288 [(const_int 0)]
2289 "
2290 {
2291 rtx dest = operands[0];
2292 rtx src = operands[1];
2293 rtx op2 = operands[2];
2294 rtx op3 = operands[3];
2295 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2296 BYTES_BIG_ENDIAN ? 4 : 0);
2297 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2298 BYTES_BIG_ENDIAN ? 4 : 0);
2299 rtx addr1;
2300 rtx addr2;
2301 rtx word_high;
2302 rtx word_low;
2304 addr1 = XEXP (dest, 0);
2305 if (GET_CODE (addr1) == PLUS)
2306 {
2307 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2308 if (TARGET_AVOID_XFORM)
2309 {
2310 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2311 addr2 = op2;
2312 }
2313 else
2314 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2315 }
2316 else if (TARGET_AVOID_XFORM)
2317 {
2318 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2319 addr2 = op2;
2320 }
2321 else
2322 {
2323 emit_move_insn (op2, GEN_INT (4));
2324 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2325 }
2327 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2328 if (BYTES_BIG_ENDIAN)
2329 {
2330 word_high = change_address (dest, SImode, addr1);
2331 word_low = change_address (dest, SImode, addr2);
2332 emit_insn (gen_bswapsi2 (word_high, src_si));
2333 emit_insn (gen_bswapsi2 (word_low, op3_si));
2334 }
2335 else
2336 {
2337 word_high = change_address (dest, SImode, addr2);
2338 word_low = change_address (dest, SImode, addr1);
2339 emit_insn (gen_bswapsi2 (word_low, src_si));
2340 emit_insn (gen_bswapsi2 (word_high, op3_si));
2341 }
2342 }")
2344 (define_split
2345 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2346 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2347 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2348 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2349 (clobber (match_operand:DI 4 "" ""))]
2350 "TARGET_POWERPC64 && reload_completed"
2351 [(const_int 0)]
2352 "
2353 {
2354 rtx dest = operands[0];
2355 rtx src = operands[1];
2356 rtx op2 = operands[2];
2357 rtx op3 = operands[3];
2358 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2359 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2360 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2361 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2362 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2364 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2365 emit_insn (gen_bswapsi2 (dest_si, src_si));
2366 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2367 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2368 emit_insn (gen_iordi3 (dest, dest, op3));
2369 }")
2371 (define_insn "bswapdi2_32bit"
2372 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2373 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2374 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2375 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2376 "#"
2377 [(set_attr "length" "16,12,36")])
2379 (define_split
2380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2381 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2382 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2383 "!TARGET_POWERPC64 && reload_completed"
2384 [(const_int 0)]
2385 "
2386 {
2387 rtx dest = operands[0];
2388 rtx src = operands[1];
2389 rtx op2 = operands[2];
2390 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2391 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2392 rtx addr1;
2393 rtx addr2;
2394 rtx word1;
2395 rtx word2;
2397 addr1 = XEXP (src, 0);
2398 if (GET_CODE (addr1) == PLUS)
2399 {
2400 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2401 if (TARGET_AVOID_XFORM)
2402 {
2403 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2404 addr2 = op2;
2405 }
2406 else
2407 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2408 }
2409 else if (TARGET_AVOID_XFORM)
2410 {
2411 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2412 addr2 = op2;
2413 }
2414 else
2415 {
2416 emit_move_insn (op2, GEN_INT (4));
2417 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2418 }
2420 word1 = change_address (src, SImode, addr1);
2421 word2 = change_address (src, SImode, addr2);
2423 emit_insn (gen_bswapsi2 (dest2, word1));
2424 emit_insn (gen_bswapsi2 (dest1, word2));
2425 }")
2427 (define_split
2428 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2429 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2430 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2431 "!TARGET_POWERPC64 && reload_completed"
2432 [(const_int 0)]
2433 "
2434 {
2435 rtx dest = operands[0];
2436 rtx src = operands[1];
2437 rtx op2 = operands[2];
2438 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2439 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2440 rtx addr1;
2441 rtx addr2;
2442 rtx word1;
2443 rtx word2;
2445 addr1 = XEXP (dest, 0);
2446 if (GET_CODE (addr1) == PLUS)
2447 {
2448 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2449 if (TARGET_AVOID_XFORM)
2450 {
2451 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2452 addr2 = op2;
2453 }
2454 else
2455 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2456 }
2457 else if (TARGET_AVOID_XFORM)
2458 {
2459 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2460 addr2 = op2;
2461 }
2462 else
2463 {
2464 emit_move_insn (op2, GEN_INT (4));
2465 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2466 }
2468 word1 = change_address (dest, SImode, addr1);
2469 word2 = change_address (dest, SImode, addr2);
2471 emit_insn (gen_bswapsi2 (word2, src1));
2472 emit_insn (gen_bswapsi2 (word1, src2));
2473 }")
2475 (define_split
2476 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2477 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2478 (clobber (match_operand:SI 2 "" ""))]
2479 "!TARGET_POWERPC64 && reload_completed"
2480 [(const_int 0)]
2481 "
2482 {
2483 rtx dest = operands[0];
2484 rtx src = operands[1];
2485 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2486 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2487 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2488 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2490 emit_insn (gen_bswapsi2 (dest1, src2));
2491 emit_insn (gen_bswapsi2 (dest2, src1));
2492 }")
2494 (define_insn "mulsi3"
2495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2496 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2497 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2498 ""
2499 "@
2500 mullw %0,%1,%2
2501 mulli %0,%1,%2"
2502 [(set (attr "type")
2503 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2504 (const_string "imul3")
2505 (match_operand:SI 2 "short_cint_operand" "")
2506 (const_string "imul2")]
2507 (const_string "imul")))])
2509 (define_insn "*mulsi3_internal1"
2510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2511 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2512 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2513 (const_int 0)))
2514 (clobber (match_scratch:SI 3 "=r,r"))]
2515 ""
2516 "@
2517 mullw. %3,%1,%2
2518 #"
2519 [(set_attr "type" "imul_compare")
2520 (set_attr "length" "4,8")])
2522 (define_split
2523 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2524 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2525 (match_operand:SI 2 "gpc_reg_operand" ""))
2526 (const_int 0)))
2527 (clobber (match_scratch:SI 3 ""))]
2528 "reload_completed"
2529 [(set (match_dup 3)
2530 (mult:SI (match_dup 1) (match_dup 2)))
2531 (set (match_dup 0)
2532 (compare:CC (match_dup 3)
2533 (const_int 0)))]
2534 "")
2536 (define_insn "*mulsi3_internal2"
2537 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2538 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2539 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2540 (const_int 0)))
2541 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2542 (mult:SI (match_dup 1) (match_dup 2)))]
2543 ""
2544 "@
2545 mullw. %0,%1,%2
2546 #"
2547 [(set_attr "type" "imul_compare")
2548 (set_attr "length" "4,8")])
2550 (define_split
2551 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2552 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2553 (match_operand:SI 2 "gpc_reg_operand" ""))
2554 (const_int 0)))
2555 (set (match_operand:SI 0 "gpc_reg_operand" "")
2556 (mult:SI (match_dup 1) (match_dup 2)))]
2557 "reload_completed"
2558 [(set (match_dup 0)
2559 (mult:SI (match_dup 1) (match_dup 2)))
2560 (set (match_dup 3)
2561 (compare:CC (match_dup 0)
2562 (const_int 0)))]
2563 "")
2566 (define_insn "udiv<mode>3"
2567 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2568 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2569 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2570 ""
2571 "div<wd>u %0,%1,%2"
2572 [(set (attr "type")
2573 (cond [(match_operand:SI 0 "" "")
2574 (const_string "idiv")]
2575 (const_string "ldiv")))])
2578 ;; For powers of two we can do srai/aze for divide and then adjust for
2579 ;; modulus. If it isn't a power of two, force operands into register and do
2580 ;; a normal divide.
2581 (define_expand "div<mode>3"
2582 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2583 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2584 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2585 ""
2586 {
2587 if (GET_CODE (operands[2]) != CONST_INT
2588 || INTVAL (operands[2]) <= 0
2589 || exact_log2 (INTVAL (operands[2])) < 0)
2590 operands[2] = force_reg (<MODE>mode, operands[2]);
2591 })
2593 (define_insn "*div<mode>3"
2594 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2595 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2596 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2597 ""
2598 "div<wd> %0,%1,%2"
2599 [(set (attr "type")
2600 (cond [(match_operand:SI 0 "" "")
2601 (const_string "idiv")]
2602 (const_string "ldiv")))])
2604 (define_expand "mod<mode>3"
2605 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2606 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2607 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2608 ""
2609 "
2610 {
2611 int i;
2612 rtx temp1;
2613 rtx temp2;
2615 if (GET_CODE (operands[2]) != CONST_INT
2616 || INTVAL (operands[2]) <= 0
2617 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2618 FAIL;
2620 temp1 = gen_reg_rtx (<MODE>mode);
2621 temp2 = gen_reg_rtx (<MODE>mode);
2623 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2624 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2625 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2626 DONE;
2627 }")
2629 (define_insn ""
2630 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2631 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2632 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2633 ""
2634 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2635 [(set_attr "type" "two")
2636 (set_attr "length" "8")])
2638 (define_insn ""
2639 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2640 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2641 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2642 (const_int 0)))
2643 (clobber (match_scratch:P 3 "=r,r"))]
2644 ""
2645 "@
2646 sra<wd>i %3,%1,%p2\;addze. %3,%3
2647 #"
2648 [(set_attr "type" "compare")
2649 (set_attr "length" "8,12")
2650 (set_attr "cell_micro" "not")])
2652 (define_split
2653 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2654 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2655 (match_operand:GPR 2 "exact_log2_cint_operand"
2656 ""))
2657 (const_int 0)))
2658 (clobber (match_scratch:GPR 3 ""))]
2659 "reload_completed"
2660 [(set (match_dup 3)
2661 (div:<MODE> (match_dup 1) (match_dup 2)))
2662 (set (match_dup 0)
2663 (compare:CC (match_dup 3)
2664 (const_int 0)))]
2665 "")
2667 (define_insn ""
2668 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2669 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2670 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2671 (const_int 0)))
2672 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2673 (div:P (match_dup 1) (match_dup 2)))]
2674 ""
2675 "@
2676 sra<wd>i %0,%1,%p2\;addze. %0,%0
2677 #"
2678 [(set_attr "type" "compare")
2679 (set_attr "length" "8,12")
2680 (set_attr "cell_micro" "not")])
2682 (define_split
2683 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2684 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2685 (match_operand:GPR 2 "exact_log2_cint_operand"
2686 ""))
2687 (const_int 0)))
2688 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2689 (div:GPR (match_dup 1) (match_dup 2)))]
2690 "reload_completed"
2691 [(set (match_dup 0)
2692 (div:<MODE> (match_dup 1) (match_dup 2)))
2693 (set (match_dup 3)
2694 (compare:CC (match_dup 0)
2695 (const_int 0)))]
2696 "")
2697 \f
2698 ;; Logical instructions
2699 ;; The logical instructions are mostly combined by using match_operator,
2700 ;; but the plain AND insns are somewhat different because there is no
2701 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2702 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2704 (define_expand "andsi3"
2705 [(parallel
2706 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2707 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2708 (match_operand:SI 2 "and_operand" "")))
2709 (clobber (match_scratch:CC 3 ""))])]
2710 ""
2711 "")
2713 (define_insn "andsi3_mc"
2714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2715 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2716 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2717 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2718 "rs6000_gen_cell_microcode"
2719 "@
2720 and %0,%1,%2
2721 rlwinm %0,%1,0,%m2,%M2
2722 andi. %0,%1,%b2
2723 andis. %0,%1,%u2"
2724 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2726 (define_insn "andsi3_nomc"
2727 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2728 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2729 (match_operand:SI 2 "and_operand" "?r,T")))
2730 (clobber (match_scratch:CC 3 "=X,X"))]
2731 "!rs6000_gen_cell_microcode"
2732 "@
2733 and %0,%1,%2
2734 rlwinm %0,%1,0,%m2,%M2")
2736 (define_insn "andsi3_internal0_nomc"
2737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2738 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2739 (match_operand:SI 2 "and_operand" "?r,T")))]
2740 "!rs6000_gen_cell_microcode"
2741 "@
2742 and %0,%1,%2
2743 rlwinm %0,%1,0,%m2,%M2")
2746 ;; Note to set cr's other than cr0 we do the and immediate and then
2747 ;; the test again -- this avoids a mfcr which on the higher end
2748 ;; machines causes an execution serialization
2750 (define_insn "*andsi3_internal2_mc"
2751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2752 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2753 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2754 (const_int 0)))
2755 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2756 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2757 "TARGET_32BIT && rs6000_gen_cell_microcode"
2758 "@
2759 and. %3,%1,%2
2760 andi. %3,%1,%b2
2761 andis. %3,%1,%u2
2762 rlwinm. %3,%1,0,%m2,%M2
2763 #
2764 #
2765 #
2766 #"
2767 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2768 compare,compare,compare,compare")
2769 (set_attr "length" "4,4,4,4,8,8,8,8")])
2771 (define_insn "*andsi3_internal3_mc"
2772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2773 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2774 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2775 (const_int 0)))
2776 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2777 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2778 "TARGET_64BIT && rs6000_gen_cell_microcode"
2779 "@
2780 #
2781 andi. %3,%1,%b2
2782 andis. %3,%1,%u2
2783 rlwinm. %3,%1,0,%m2,%M2
2784 #
2785 #
2786 #
2787 #"
2788 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2789 compare,compare,compare")
2790 (set_attr "length" "8,4,4,4,8,8,8,8")])
2792 (define_split
2793 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2794 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2795 (match_operand:GPR 2 "and_operand" ""))
2796 (const_int 0)))
2797 (clobber (match_scratch:GPR 3 ""))
2798 (clobber (match_scratch:CC 4 ""))]
2799 "reload_completed"
2800 [(parallel [(set (match_dup 3)
2801 (and:<MODE> (match_dup 1)
2802 (match_dup 2)))
2803 (clobber (match_dup 4))])
2804 (set (match_dup 0)
2805 (compare:CC (match_dup 3)
2806 (const_int 0)))]
2807 "")
2809 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2810 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2812 (define_split
2813 [(set (match_operand:CC 0 "cc_reg_operand" "")
2814 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2815 (match_operand:SI 2 "gpc_reg_operand" ""))
2816 (const_int 0)))
2817 (clobber (match_scratch:SI 3 ""))
2818 (clobber (match_scratch:CC 4 ""))]
2819 "TARGET_POWERPC64 && reload_completed"
2820 [(parallel [(set (match_dup 3)
2821 (and:SI (match_dup 1)
2822 (match_dup 2)))
2823 (clobber (match_dup 4))])
2824 (set (match_dup 0)
2825 (compare:CC (match_dup 3)
2826 (const_int 0)))]
2827 "")
2829 (define_insn "*andsi3_internal4"
2830 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2831 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2832 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2833 (const_int 0)))
2834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2835 (and:SI (match_dup 1)
2836 (match_dup 2)))
2837 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2838 "TARGET_32BIT && rs6000_gen_cell_microcode"
2839 "@
2840 and. %0,%1,%2
2841 andi. %0,%1,%b2
2842 andis. %0,%1,%u2
2843 rlwinm. %0,%1,0,%m2,%M2
2844 #
2845 #
2846 #
2847 #"
2848 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2849 compare,compare,compare,compare")
2850 (set_attr "length" "4,4,4,4,8,8,8,8")])
2852 (define_insn "*andsi3_internal5_mc"
2853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2854 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2855 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2856 (const_int 0)))
2857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2858 (and:SI (match_dup 1)
2859 (match_dup 2)))
2860 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2861 "TARGET_64BIT && rs6000_gen_cell_microcode"
2862 "@
2863 #
2864 andi. %0,%1,%b2
2865 andis. %0,%1,%u2
2866 rlwinm. %0,%1,0,%m2,%M2
2867 #
2868 #
2869 #
2870 #"
2871 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2872 compare,compare,compare")
2873 (set_attr "length" "8,4,4,4,8,8,8,8")])
2875 (define_split
2876 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2877 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2878 (match_operand:SI 2 "and_operand" ""))
2879 (const_int 0)))
2880 (set (match_operand:SI 0 "gpc_reg_operand" "")
2881 (and:SI (match_dup 1)
2882 (match_dup 2)))
2883 (clobber (match_scratch:CC 4 ""))]
2884 "reload_completed"
2885 [(parallel [(set (match_dup 0)
2886 (and:SI (match_dup 1)
2887 (match_dup 2)))
2888 (clobber (match_dup 4))])
2889 (set (match_dup 3)
2890 (compare:CC (match_dup 0)
2891 (const_int 0)))]
2892 "")
2894 (define_split
2895 [(set (match_operand:CC 3 "cc_reg_operand" "")
2896 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2897 (match_operand:SI 2 "gpc_reg_operand" ""))
2898 (const_int 0)))
2899 (set (match_operand:SI 0 "gpc_reg_operand" "")
2900 (and:SI (match_dup 1)
2901 (match_dup 2)))
2902 (clobber (match_scratch:CC 4 ""))]
2903 "TARGET_POWERPC64 && reload_completed"
2904 [(parallel [(set (match_dup 0)
2905 (and:SI (match_dup 1)
2906 (match_dup 2)))
2907 (clobber (match_dup 4))])
2908 (set (match_dup 3)
2909 (compare:CC (match_dup 0)
2910 (const_int 0)))]
2911 "")
2913 ;; Handle the PowerPC64 rlwinm corner case
2915 (define_insn_and_split "*andsi3_internal6"
2916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2917 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2918 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2919 "TARGET_POWERPC64"
2920 "#"
2921 "TARGET_POWERPC64"
2922 [(set (match_dup 0)
2923 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2924 (match_dup 4)))
2925 (set (match_dup 0)
2926 (rotate:SI (match_dup 0) (match_dup 5)))]
2927 "
2928 {
2929 int mb = extract_MB (operands[2]);
2930 int me = extract_ME (operands[2]);
2931 operands[3] = GEN_INT (me + 1);
2932 operands[5] = GEN_INT (32 - (me + 1));
2933 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2934 }"
2935 [(set_attr "length" "8")])
2937 (define_expand "iorsi3"
2938 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2939 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2940 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2941 ""
2942 "
2943 {
2944 if (GET_CODE (operands[2]) == CONST_INT
2945 && ! logical_operand (operands[2], SImode))
2946 {
2947 HOST_WIDE_INT value = INTVAL (operands[2]);
2948 rtx tmp = ((!can_create_pseudo_p ()
2949 || rtx_equal_p (operands[0], operands[1]))
2950 ? operands[0] : gen_reg_rtx (SImode));
2952 emit_insn (gen_iorsi3 (tmp, operands[1],
2953 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2954 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2955 DONE;
2956 }
2957 }")
2959 (define_expand "xorsi3"
2960 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2961 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2962 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2963 ""
2964 "
2965 {
2966 if (GET_CODE (operands[2]) == CONST_INT
2967 && ! logical_operand (operands[2], SImode))
2968 {
2969 HOST_WIDE_INT value = INTVAL (operands[2]);
2970 rtx tmp = ((!can_create_pseudo_p ()
2971 || rtx_equal_p (operands[0], operands[1]))
2972 ? operands[0] : gen_reg_rtx (SImode));
2974 emit_insn (gen_xorsi3 (tmp, operands[1],
2975 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2976 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2977 DONE;
2978 }
2979 }")
2981 (define_insn "*boolsi3_internal1"
2982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2983 (match_operator:SI 3 "boolean_or_operator"
2984 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2985 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2986 ""
2987 "@
2988 %q3 %0,%1,%2
2989 %q3i %0,%1,%b2
2990 %q3is %0,%1,%u2")
2992 (define_insn "*boolsi3_internal2"
2993 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2994 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2995 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2996 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2997 (const_int 0)))
2998 (clobber (match_scratch:SI 3 "=r,r"))]
2999 "TARGET_32BIT"
3000 "@
3001 %q4. %3,%1,%2
3002 #"
3003 [(set_attr "type" "fast_compare,compare")
3004 (set_attr "length" "4,8")])
3006 (define_split
3007 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3008 (compare:CC (match_operator:SI 4 "boolean_operator"
3009 [(match_operand:SI 1 "gpc_reg_operand" "")
3010 (match_operand:SI 2 "gpc_reg_operand" "")])
3011 (const_int 0)))
3012 (clobber (match_scratch:SI 3 ""))]
3013 "TARGET_32BIT && reload_completed"
3014 [(set (match_dup 3) (match_dup 4))
3015 (set (match_dup 0)
3016 (compare:CC (match_dup 3)
3017 (const_int 0)))]
3018 "")
3020 (define_insn "*boolsi3_internal3"
3021 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3022 (compare:CC (match_operator:SI 4 "boolean_operator"
3023 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3024 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3025 (const_int 0)))
3026 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3027 (match_dup 4))]
3028 "TARGET_32BIT"
3029 "@
3030 %q4. %0,%1,%2
3031 #"
3032 [(set_attr "type" "fast_compare,compare")
3033 (set_attr "length" "4,8")])
3035 (define_split
3036 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3037 (compare:CC (match_operator:SI 4 "boolean_operator"
3038 [(match_operand:SI 1 "gpc_reg_operand" "")
3039 (match_operand:SI 2 "gpc_reg_operand" "")])
3040 (const_int 0)))
3041 (set (match_operand:SI 0 "gpc_reg_operand" "")
3042 (match_dup 4))]
3043 "TARGET_32BIT && reload_completed"
3044 [(set (match_dup 0) (match_dup 4))
3045 (set (match_dup 3)
3046 (compare:CC (match_dup 0)
3047 (const_int 0)))]
3048 "")
3050 ;; Split a logical operation that we can't do in one insn into two insns,
3051 ;; each of which does one 16-bit part. This is used by combine.
3053 (define_split
3054 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3055 (match_operator:SI 3 "boolean_or_operator"
3056 [(match_operand:SI 1 "gpc_reg_operand" "")
3057 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3058 ""
3059 [(set (match_dup 0) (match_dup 4))
3060 (set (match_dup 0) (match_dup 5))]
3061 "
3062 {
3063 rtx i;
3064 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3065 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3066 operands[1], i);
3067 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3068 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3069 operands[0], i);
3070 }")
3072 (define_insn "*boolcsi3_internal1"
3073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3074 (match_operator:SI 3 "boolean_operator"
3075 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3076 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3077 ""
3078 "%q3 %0,%2,%1")
3080 (define_insn "*boolcsi3_internal2"
3081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3082 (compare:CC (match_operator:SI 4 "boolean_operator"
3083 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3084 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3085 (const_int 0)))
3086 (clobber (match_scratch:SI 3 "=r,r"))]
3087 "TARGET_32BIT"
3088 "@
3089 %q4. %3,%2,%1
3090 #"
3091 [(set_attr "type" "compare")
3092 (set_attr "length" "4,8")])
3094 (define_split
3095 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3096 (compare:CC (match_operator:SI 4 "boolean_operator"
3097 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3098 (match_operand:SI 2 "gpc_reg_operand" "")])
3099 (const_int 0)))
3100 (clobber (match_scratch:SI 3 ""))]
3101 "TARGET_32BIT && reload_completed"
3102 [(set (match_dup 3) (match_dup 4))
3103 (set (match_dup 0)
3104 (compare:CC (match_dup 3)
3105 (const_int 0)))]
3106 "")
3108 (define_insn "*boolcsi3_internal3"
3109 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3110 (compare:CC (match_operator:SI 4 "boolean_operator"
3111 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3112 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3113 (const_int 0)))
3114 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3115 (match_dup 4))]
3116 "TARGET_32BIT"
3117 "@
3118 %q4. %0,%2,%1
3119 #"
3120 [(set_attr "type" "compare")
3121 (set_attr "length" "4,8")])
3123 (define_split
3124 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3125 (compare:CC (match_operator:SI 4 "boolean_operator"
3126 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3127 (match_operand:SI 2 "gpc_reg_operand" "")])
3128 (const_int 0)))
3129 (set (match_operand:SI 0 "gpc_reg_operand" "")
3130 (match_dup 4))]
3131 "TARGET_32BIT && reload_completed"
3132 [(set (match_dup 0) (match_dup 4))
3133 (set (match_dup 3)
3134 (compare:CC (match_dup 0)
3135 (const_int 0)))]
3136 "")
3138 (define_insn "*boolccsi3_internal1"
3139 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3140 (match_operator:SI 3 "boolean_operator"
3141 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3142 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3143 ""
3144 "%q3 %0,%1,%2")
3146 (define_insn "*boolccsi3_internal2"
3147 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3148 (compare:CC (match_operator:SI 4 "boolean_operator"
3149 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3150 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3151 (const_int 0)))
3152 (clobber (match_scratch:SI 3 "=r,r"))]
3153 "TARGET_32BIT"
3154 "@
3155 %q4. %3,%1,%2
3156 #"
3157 [(set_attr "type" "fast_compare,compare")
3158 (set_attr "length" "4,8")])
3160 (define_split
3161 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3162 (compare:CC (match_operator:SI 4 "boolean_operator"
3163 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3164 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3165 (const_int 0)))
3166 (clobber (match_scratch:SI 3 ""))]
3167 "TARGET_32BIT && reload_completed"
3168 [(set (match_dup 3) (match_dup 4))
3169 (set (match_dup 0)
3170 (compare:CC (match_dup 3)
3171 (const_int 0)))]
3172 "")
3174 (define_insn "*boolccsi3_internal3"
3175 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3176 (compare:CC (match_operator:SI 4 "boolean_operator"
3177 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3178 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3179 (const_int 0)))
3180 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3181 (match_dup 4))]
3182 "TARGET_32BIT"
3183 "@
3184 %q4. %0,%1,%2
3185 #"
3186 [(set_attr "type" "fast_compare,compare")
3187 (set_attr "length" "4,8")])
3189 (define_split
3190 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3191 (compare:CC (match_operator:SI 4 "boolean_operator"
3192 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3193 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3194 (const_int 0)))
3195 (set (match_operand:SI 0 "gpc_reg_operand" "")
3196 (match_dup 4))]
3197 "TARGET_32BIT && reload_completed"
3198 [(set (match_dup 0) (match_dup 4))
3199 (set (match_dup 3)
3200 (compare:CC (match_dup 0)
3201 (const_int 0)))]
3202 "")
3203 \f
3204 ;; Rotate and shift insns, in all their variants. These support shifts,
3205 ;; field inserts and extracts, and various combinations thereof.
3206 (define_expand "insv"
3207 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3208 (match_operand:SI 1 "const_int_operand" "")
3209 (match_operand:SI 2 "const_int_operand" ""))
3210 (match_operand 3 "gpc_reg_operand" ""))]
3211 ""
3212 "
3213 {
3214 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3215 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3216 compiler if the address of the structure is taken later. Likewise, do
3217 not handle invalid E500 subregs. */
3218 if (GET_CODE (operands[0]) == SUBREG
3219 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3220 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3221 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3222 FAIL;
3224 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3225 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3226 operands[3]));
3227 else
3228 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3229 operands[3]));
3230 DONE;
3231 }")
3233 (define_insn "insvsi_internal"
3234 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3235 (match_operand:SI 1 "const_int_operand" "i")
3236 (match_operand:SI 2 "const_int_operand" "i"))
3237 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3238 ""
3239 "*
3240 {
3241 int start = INTVAL (operands[2]) & 31;
3242 int size = INTVAL (operands[1]) & 31;
3244 operands[4] = GEN_INT (32 - start - size);
3245 operands[1] = GEN_INT (start + size - 1);
3246 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3247 }"
3248 [(set_attr "type" "insert_word")])
3250 (define_insn "*insvsi_internal1"
3251 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3252 (match_operand:SI 1 "const_int_operand" "i")
3253 (match_operand:SI 2 "const_int_operand" "i"))
3254 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3255 (match_operand:SI 4 "const_int_operand" "i")))]
3256 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3257 "*
3258 {
3259 int shift = INTVAL (operands[4]) & 31;
3260 int start = INTVAL (operands[2]) & 31;
3261 int size = INTVAL (operands[1]) & 31;
3263 operands[4] = GEN_INT (shift - start - size);
3264 operands[1] = GEN_INT (start + size - 1);
3265 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3266 }"
3267 [(set_attr "type" "insert_word")])
3269 (define_insn "*insvsi_internal2"
3270 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3271 (match_operand:SI 1 "const_int_operand" "i")
3272 (match_operand:SI 2 "const_int_operand" "i"))
3273 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3274 (match_operand:SI 4 "const_int_operand" "i")))]
3275 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3276 "*
3277 {
3278 int shift = INTVAL (operands[4]) & 31;
3279 int start = INTVAL (operands[2]) & 31;
3280 int size = INTVAL (operands[1]) & 31;
3282 operands[4] = GEN_INT (32 - shift - start - size);
3283 operands[1] = GEN_INT (start + size - 1);
3284 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3285 }"
3286 [(set_attr "type" "insert_word")])
3288 (define_insn "*insvsi_internal3"
3289 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3290 (match_operand:SI 1 "const_int_operand" "i")
3291 (match_operand:SI 2 "const_int_operand" "i"))
3292 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3293 (match_operand:SI 4 "const_int_operand" "i")))]
3294 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3295 "*
3296 {
3297 int shift = INTVAL (operands[4]) & 31;
3298 int start = INTVAL (operands[2]) & 31;
3299 int size = INTVAL (operands[1]) & 31;
3301 operands[4] = GEN_INT (32 - shift - start - size);
3302 operands[1] = GEN_INT (start + size - 1);
3303 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3304 }"
3305 [(set_attr "type" "insert_word")])
3307 (define_insn "*insvsi_internal4"
3308 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3309 (match_operand:SI 1 "const_int_operand" "i")
3310 (match_operand:SI 2 "const_int_operand" "i"))
3311 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3312 (match_operand:SI 4 "const_int_operand" "i")
3313 (match_operand:SI 5 "const_int_operand" "i")))]
3314 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3315 "*
3316 {
3317 int extract_start = INTVAL (operands[5]) & 31;
3318 int extract_size = INTVAL (operands[4]) & 31;
3319 int insert_start = INTVAL (operands[2]) & 31;
3320 int insert_size = INTVAL (operands[1]) & 31;
3322 /* Align extract field with insert field */
3323 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3324 operands[1] = GEN_INT (insert_start + insert_size - 1);
3325 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3326 }"
3327 [(set_attr "type" "insert_word")])
3329 ;; combine patterns for rlwimi
3330 (define_insn "*insvsi_internal5"
3331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3332 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3333 (match_operand:SI 1 "mask_operand" "i"))
3334 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3335 (match_operand:SI 2 "const_int_operand" "i"))
3336 (match_operand:SI 5 "mask_operand" "i"))))]
3337 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3338 "*
3339 {
3340 int me = extract_ME(operands[5]);
3341 int mb = extract_MB(operands[5]);
3342 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3343 operands[2] = GEN_INT(mb);
3344 operands[1] = GEN_INT(me);
3345 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3346 }"
3347 [(set_attr "type" "insert_word")])
3349 (define_insn "*insvsi_internal6"
3350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3351 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3352 (match_operand:SI 2 "const_int_operand" "i"))
3353 (match_operand:SI 5 "mask_operand" "i"))
3354 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3355 (match_operand:SI 1 "mask_operand" "i"))))]
3356 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3357 "*
3358 {
3359 int me = extract_ME(operands[5]);
3360 int mb = extract_MB(operands[5]);
3361 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3362 operands[2] = GEN_INT(mb);
3363 operands[1] = GEN_INT(me);
3364 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3365 }"
3366 [(set_attr "type" "insert_word")])
3368 (define_insn "insvdi_internal"
3369 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3370 (match_operand:SI 1 "const_int_operand" "i")
3371 (match_operand:SI 2 "const_int_operand" "i"))
3372 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3373 "TARGET_POWERPC64"
3374 "*
3375 {
3376 int start = INTVAL (operands[2]) & 63;
3377 int size = INTVAL (operands[1]) & 63;
3379 operands[1] = GEN_INT (64 - start - size);
3380 return \"rldimi %0,%3,%H1,%H2\";
3381 }"
3382 [(set_attr "type" "insert_dword")])
3384 (define_insn "*insvdi_internal2"
3385 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3386 (match_operand:SI 1 "const_int_operand" "i")
3387 (match_operand:SI 2 "const_int_operand" "i"))
3388 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3389 (match_operand:SI 4 "const_int_operand" "i")))]
3390 "TARGET_POWERPC64
3391 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3392 "*
3393 {
3394 int shift = INTVAL (operands[4]) & 63;
3395 int start = (INTVAL (operands[2]) & 63) - 32;
3396 int size = INTVAL (operands[1]) & 63;
3398 operands[4] = GEN_INT (64 - shift - start - size);
3399 operands[2] = GEN_INT (start);
3400 operands[1] = GEN_INT (start + size - 1);
3401 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3402 }")
3404 (define_insn "*insvdi_internal3"
3405 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3406 (match_operand:SI 1 "const_int_operand" "i")
3407 (match_operand:SI 2 "const_int_operand" "i"))
3408 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3409 (match_operand:SI 4 "const_int_operand" "i")))]
3410 "TARGET_POWERPC64
3411 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3412 "*
3413 {
3414 int shift = INTVAL (operands[4]) & 63;
3415 int start = (INTVAL (operands[2]) & 63) - 32;
3416 int size = INTVAL (operands[1]) & 63;
3418 operands[4] = GEN_INT (64 - shift - start - size);
3419 operands[2] = GEN_INT (start);
3420 operands[1] = GEN_INT (start + size - 1);
3421 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3422 }")
3424 (define_expand "extzv"
3425 [(set (match_operand 0 "gpc_reg_operand" "")
3426 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3427 (match_operand:SI 2 "const_int_operand" "")
3428 (match_operand:SI 3 "const_int_operand" "")))]
3429 ""
3430 "
3431 {
3432 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3433 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3434 compiler if the address of the structure is taken later. */
3435 if (GET_CODE (operands[0]) == SUBREG
3436 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3437 FAIL;
3439 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3440 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3441 operands[3]));
3442 else
3443 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3444 operands[3]));
3445 DONE;
3446 }")
3448 (define_insn "extzvsi_internal"
3449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3450 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3451 (match_operand:SI 2 "const_int_operand" "i")
3452 (match_operand:SI 3 "const_int_operand" "i")))]
3453 ""
3454 "*
3455 {
3456 int start = INTVAL (operands[3]) & 31;
3457 int size = INTVAL (operands[2]) & 31;
3459 if (start + size >= 32)
3460 operands[3] = const0_rtx;
3461 else
3462 operands[3] = GEN_INT (start + size);
3463 return \"rlwinm %0,%1,%3,%s2,31\";
3464 }")
3466 (define_insn "*extzvsi_internal1"
3467 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3468 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3469 (match_operand:SI 2 "const_int_operand" "i,i")
3470 (match_operand:SI 3 "const_int_operand" "i,i"))
3471 (const_int 0)))
3472 (clobber (match_scratch:SI 4 "=r,r"))]
3473 ""
3474 "*
3475 {
3476 int start = INTVAL (operands[3]) & 31;
3477 int size = INTVAL (operands[2]) & 31;
3479 /* Force split for non-cc0 compare. */
3480 if (which_alternative == 1)
3481 return \"#\";
3483 /* If the bit-field being tested fits in the upper or lower half of a
3484 word, it is possible to use andiu. or andil. to test it. This is
3485 useful because the condition register set-use delay is smaller for
3486 andi[ul]. than for rlinm. This doesn't work when the starting bit
3487 position is 0 because the LT and GT bits may be set wrong. */
3489 if ((start > 0 && start + size <= 16) || start >= 16)
3490 {
3491 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3492 - (1 << (16 - (start & 15) - size))));
3493 if (start < 16)
3494 return \"andis. %4,%1,%3\";
3495 else
3496 return \"andi. %4,%1,%3\";
3497 }
3499 if (start + size >= 32)
3500 operands[3] = const0_rtx;
3501 else
3502 operands[3] = GEN_INT (start + size);
3503 return \"rlwinm. %4,%1,%3,%s2,31\";
3504 }"
3505 [(set_attr "type" "delayed_compare")
3506 (set_attr "length" "4,8")])
3508 (define_split
3509 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3510 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3511 (match_operand:SI 2 "const_int_operand" "")
3512 (match_operand:SI 3 "const_int_operand" ""))
3513 (const_int 0)))
3514 (clobber (match_scratch:SI 4 ""))]
3515 "reload_completed"
3516 [(set (match_dup 4)
3517 (zero_extract:SI (match_dup 1) (match_dup 2)
3518 (match_dup 3)))
3519 (set (match_dup 0)
3520 (compare:CC (match_dup 4)
3521 (const_int 0)))]
3522 "")
3524 (define_insn "*extzvsi_internal2"
3525 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3526 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3527 (match_operand:SI 2 "const_int_operand" "i,i")
3528 (match_operand:SI 3 "const_int_operand" "i,i"))
3529 (const_int 0)))
3530 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3531 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3532 ""
3533 "*
3534 {
3535 int start = INTVAL (operands[3]) & 31;
3536 int size = INTVAL (operands[2]) & 31;
3538 /* Force split for non-cc0 compare. */
3539 if (which_alternative == 1)
3540 return \"#\";
3542 /* Since we are using the output value, we can't ignore any need for
3543 a shift. The bit-field must end at the LSB. */
3544 if (start >= 16 && start + size == 32)
3545 {
3546 operands[3] = GEN_INT ((1 << size) - 1);
3547 return \"andi. %0,%1,%3\";
3548 }
3550 if (start + size >= 32)
3551 operands[3] = const0_rtx;
3552 else
3553 operands[3] = GEN_INT (start + size);
3554 return \"rlwinm. %0,%1,%3,%s2,31\";
3555 }"
3556 [(set_attr "type" "delayed_compare")
3557 (set_attr "length" "4,8")])
3559 (define_split
3560 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3561 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3562 (match_operand:SI 2 "const_int_operand" "")
3563 (match_operand:SI 3 "const_int_operand" ""))
3564 (const_int 0)))
3565 (set (match_operand:SI 0 "gpc_reg_operand" "")
3566 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3567 "reload_completed"
3568 [(set (match_dup 0)
3569 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3570 (set (match_dup 4)
3571 (compare:CC (match_dup 0)
3572 (const_int 0)))]
3573 "")
3575 (define_insn "extzvdi_internal"
3576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3577 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3578 (match_operand:SI 2 "const_int_operand" "i")
3579 (match_operand:SI 3 "const_int_operand" "i")))]
3580 "TARGET_POWERPC64"
3581 "*
3582 {
3583 int start = INTVAL (operands[3]) & 63;
3584 int size = INTVAL (operands[2]) & 63;
3586 if (start + size >= 64)
3587 operands[3] = const0_rtx;
3588 else
3589 operands[3] = GEN_INT (start + size);
3590 operands[2] = GEN_INT (64 - size);
3591 return \"rldicl %0,%1,%3,%2\";
3592 }")
3594 (define_insn "*extzvdi_internal1"
3595 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3596 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3597 (match_operand:SI 2 "const_int_operand" "i")
3598 (match_operand:SI 3 "const_int_operand" "i"))
3599 (const_int 0)))
3600 (clobber (match_scratch:DI 4 "=r"))]
3601 "TARGET_64BIT && rs6000_gen_cell_microcode"
3602 "*
3603 {
3604 int start = INTVAL (operands[3]) & 63;
3605 int size = INTVAL (operands[2]) & 63;
3607 if (start + size >= 64)
3608 operands[3] = const0_rtx;
3609 else
3610 operands[3] = GEN_INT (start + size);
3611 operands[2] = GEN_INT (64 - size);
3612 return \"rldicl. %4,%1,%3,%2\";
3613 }"
3614 [(set_attr "type" "compare")])
3616 (define_insn "*extzvdi_internal2"
3617 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3618 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3619 (match_operand:SI 2 "const_int_operand" "i")
3620 (match_operand:SI 3 "const_int_operand" "i"))
3621 (const_int 0)))
3622 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3623 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3624 "TARGET_64BIT && rs6000_gen_cell_microcode"
3625 "*
3626 {
3627 int start = INTVAL (operands[3]) & 63;
3628 int size = INTVAL (operands[2]) & 63;
3630 if (start + size >= 64)
3631 operands[3] = const0_rtx;
3632 else
3633 operands[3] = GEN_INT (start + size);
3634 operands[2] = GEN_INT (64 - size);
3635 return \"rldicl. %0,%1,%3,%2\";
3636 }"
3637 [(set_attr "type" "compare")])
3639 (define_insn "rotlsi3"
3640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3641 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3642 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3643 ""
3644 "@
3645 rlwnm %0,%1,%2,0xffffffff
3646 rlwinm %0,%1,%h2,0xffffffff"
3647 [(set_attr "type" "var_shift_rotate,integer")])
3649 (define_insn "*rotlsi3_64"
3650 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3651 (zero_extend:DI
3652 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3653 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3654 "TARGET_64BIT"
3655 "@
3656 rlwnm %0,%1,%2,0xffffffff
3657 rlwinm %0,%1,%h2,0xffffffff"
3658 [(set_attr "type" "var_shift_rotate,integer")])
3660 (define_insn "*rotlsi3_internal2"
3661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3662 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3663 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3664 (const_int 0)))
3665 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3666 ""
3667 "@
3668 rlwnm. %3,%1,%2,0xffffffff
3669 rlwinm. %3,%1,%h2,0xffffffff
3670 #
3671 #"
3672 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3673 (set_attr "length" "4,4,8,8")])
3675 (define_split
3676 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3677 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3678 (match_operand:SI 2 "reg_or_cint_operand" ""))
3679 (const_int 0)))
3680 (clobber (match_scratch:SI 3 ""))]
3681 "reload_completed"
3682 [(set (match_dup 3)
3683 (rotate:SI (match_dup 1) (match_dup 2)))
3684 (set (match_dup 0)
3685 (compare:CC (match_dup 3)
3686 (const_int 0)))]
3687 "")
3689 (define_insn "*rotlsi3_internal3"
3690 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3691 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3692 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3693 (const_int 0)))
3694 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3695 (rotate:SI (match_dup 1) (match_dup 2)))]
3696 ""
3697 "@
3698 rlwnm. %0,%1,%2,0xffffffff
3699 rlwinm. %0,%1,%h2,0xffffffff
3700 #
3701 #"
3702 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3703 (set_attr "length" "4,4,8,8")])
3705 (define_split
3706 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3707 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3708 (match_operand:SI 2 "reg_or_cint_operand" ""))
3709 (const_int 0)))
3710 (set (match_operand:SI 0 "gpc_reg_operand" "")
3711 (rotate:SI (match_dup 1) (match_dup 2)))]
3712 "reload_completed"
3713 [(set (match_dup 0)
3714 (rotate:SI (match_dup 1) (match_dup 2)))
3715 (set (match_dup 3)
3716 (compare:CC (match_dup 0)
3717 (const_int 0)))]
3718 "")
3720 (define_insn "*rotlsi3_internal4"
3721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3722 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3723 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3724 (match_operand:SI 3 "mask_operand" "n,n")))]
3725 ""
3726 "@
3727 rlwnm %0,%1,%2,%m3,%M3
3728 rlwinm %0,%1,%h2,%m3,%M3"
3729 [(set_attr "type" "var_shift_rotate,integer")])
3731 (define_insn "*rotlsi3_internal5"
3732 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3733 (compare:CC (and:SI
3734 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3735 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3736 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3737 (const_int 0)))
3738 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3739 ""
3740 "@
3741 rlwnm. %4,%1,%2,%m3,%M3
3742 rlwinm. %4,%1,%h2,%m3,%M3
3743 #
3744 #"
3745 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3746 (set_attr "length" "4,4,8,8")])
3748 (define_split
3749 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3750 (compare:CC (and:SI
3751 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3752 (match_operand:SI 2 "reg_or_cint_operand" ""))
3753 (match_operand:SI 3 "mask_operand" ""))
3754 (const_int 0)))
3755 (clobber (match_scratch:SI 4 ""))]
3756 "reload_completed"
3757 [(set (match_dup 4)
3758 (and:SI (rotate:SI (match_dup 1)
3759 (match_dup 2))
3760 (match_dup 3)))
3761 (set (match_dup 0)
3762 (compare:CC (match_dup 4)
3763 (const_int 0)))]
3764 "")
3766 (define_insn "*rotlsi3_internal6"
3767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3768 (compare:CC (and:SI
3769 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3770 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3771 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3772 (const_int 0)))
3773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3774 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3775 ""
3776 "@
3777 rlwnm. %0,%1,%2,%m3,%M3
3778 rlwinm. %0,%1,%h2,%m3,%M3
3779 #
3780 #"
3781 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3782 (set_attr "length" "4,4,8,8")])
3784 (define_split
3785 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3786 (compare:CC (and:SI
3787 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3788 (match_operand:SI 2 "reg_or_cint_operand" ""))
3789 (match_operand:SI 3 "mask_operand" ""))
3790 (const_int 0)))
3791 (set (match_operand:SI 0 "gpc_reg_operand" "")
3792 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3793 "reload_completed"
3794 [(set (match_dup 0)
3795 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3796 (set (match_dup 4)
3797 (compare:CC (match_dup 0)
3798 (const_int 0)))]
3799 "")
3801 (define_insn "*rotlsi3_internal7le"
3802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3803 (zero_extend:SI
3804 (subreg:QI
3805 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3806 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3807 "!BYTES_BIG_ENDIAN"
3808 "rlw%I2nm %0,%1,%h2,0xff"
3809 [(set (attr "cell_micro")
3810 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3811 (const_string "not")
3812 (const_string "always")))])
3814 (define_insn "*rotlsi3_internal7be"
3815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3816 (zero_extend:SI
3817 (subreg:QI
3818 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3819 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3820 "BYTES_BIG_ENDIAN"
3821 "rlw%I2nm %0,%1,%h2,0xff"
3822 [(set (attr "cell_micro")
3823 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3824 (const_string "not")
3825 (const_string "always")))])
3827 (define_insn "*rotlsi3_internal8le"
3828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3829 (compare:CC (zero_extend:SI
3830 (subreg:QI
3831 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3832 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3833 (const_int 0)))
3834 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3835 "!BYTES_BIG_ENDIAN"
3836 "@
3837 rlwnm. %3,%1,%2,0xff
3838 rlwinm. %3,%1,%h2,0xff
3839 #
3840 #"
3841 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3842 (set_attr "length" "4,4,8,8")])
3844 (define_insn "*rotlsi3_internal8be"
3845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3846 (compare:CC (zero_extend:SI
3847 (subreg:QI
3848 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3849 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3850 (const_int 0)))
3851 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3852 "BYTES_BIG_ENDIAN"
3853 "@
3854 rlwnm. %3,%1,%2,0xff
3855 rlwinm. %3,%1,%h2,0xff
3856 #
3857 #"
3858 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3859 (set_attr "length" "4,4,8,8")])
3861 (define_split
3862 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3863 (compare:CC (zero_extend:SI
3864 (subreg:QI
3865 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3866 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3867 (const_int 0)))
3868 (clobber (match_scratch:SI 3 ""))]
3869 "!BYTES_BIG_ENDIAN && reload_completed"
3870 [(set (match_dup 3)
3871 (zero_extend:SI (subreg:QI
3872 (rotate:SI (match_dup 1)
3873 (match_dup 2)) 0)))
3874 (set (match_dup 0)
3875 (compare:CC (match_dup 3)
3876 (const_int 0)))]
3877 "")
3879 (define_split
3880 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3881 (compare:CC (zero_extend:SI
3882 (subreg:QI
3883 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3884 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3885 (const_int 0)))
3886 (clobber (match_scratch:SI 3 ""))]
3887 "BYTES_BIG_ENDIAN && reload_completed"
3888 [(set (match_dup 3)
3889 (zero_extend:SI (subreg:QI
3890 (rotate:SI (match_dup 1)
3891 (match_dup 2)) 3)))
3892 (set (match_dup 0)
3893 (compare:CC (match_dup 3)
3894 (const_int 0)))]
3895 "")
3897 (define_insn "*rotlsi3_internal9le"
3898 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3899 (compare:CC (zero_extend:SI
3900 (subreg:QI
3901 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3902 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3903 (const_int 0)))
3904 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3905 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3906 "!BYTES_BIG_ENDIAN"
3907 "@
3908 rlwnm. %0,%1,%2,0xff
3909 rlwinm. %0,%1,%h2,0xff
3910 #
3911 #"
3912 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3913 (set_attr "length" "4,4,8,8")])
3915 (define_insn "*rotlsi3_internal9be"
3916 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3917 (compare:CC (zero_extend:SI
3918 (subreg:QI
3919 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3920 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3921 (const_int 0)))
3922 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3923 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3924 "BYTES_BIG_ENDIAN"
3925 "@
3926 rlwnm. %0,%1,%2,0xff
3927 rlwinm. %0,%1,%h2,0xff
3928 #
3929 #"
3930 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3931 (set_attr "length" "4,4,8,8")])
3933 (define_split
3934 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3935 (compare:CC (zero_extend:SI
3936 (subreg:QI
3937 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3938 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3939 (const_int 0)))
3940 (set (match_operand:SI 0 "gpc_reg_operand" "")
3941 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3942 "!BYTES_BIG_ENDIAN && reload_completed"
3943 [(set (match_dup 0)
3944 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3945 (set (match_dup 3)
3946 (compare:CC (match_dup 0)
3947 (const_int 0)))]
3948 "")
3950 (define_split
3951 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3952 (compare:CC (zero_extend:SI
3953 (subreg:QI
3954 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3955 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3956 (const_int 0)))
3957 (set (match_operand:SI 0 "gpc_reg_operand" "")
3958 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3959 "BYTES_BIG_ENDIAN && reload_completed"
3960 [(set (match_dup 0)
3961 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3962 (set (match_dup 3)
3963 (compare:CC (match_dup 0)
3964 (const_int 0)))]
3965 "")
3967 (define_insn "*rotlsi3_internal10le"
3968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3969 (zero_extend:SI
3970 (subreg:HI
3971 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3972 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
3973 "!BYTES_BIG_ENDIAN"
3974 "@
3975 rlwnm %0,%1,%2,0xffff
3976 rlwinm %0,%1,%h2,0xffff"
3977 [(set_attr "type" "var_shift_rotate,integer")])
3979 (define_insn "*rotlsi3_internal10be"
3980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3981 (zero_extend:SI
3982 (subreg:HI
3983 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3984 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
3985 "BYTES_BIG_ENDIAN"
3986 "@
3987 rlwnm %0,%1,%2,0xffff
3988 rlwinm %0,%1,%h2,0xffff"
3989 [(set_attr "type" "var_shift_rotate,integer")])
3991 (define_insn "*rotlsi3_internal11le"
3992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3993 (compare:CC (zero_extend:SI
3994 (subreg:HI
3995 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3996 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3997 (const_int 0)))
3998 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3999 "!BYTES_BIG_ENDIAN"
4000 "@
4001 rlwnm. %3,%1,%2,0xffff
4002 rlwinm. %3,%1,%h2,0xffff
4003 #
4004 #"
4005 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4006 (set_attr "length" "4,4,8,8")])
4008 (define_insn "*rotlsi3_internal11be"
4009 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4010 (compare:CC (zero_extend:SI
4011 (subreg:HI
4012 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4013 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4014 (const_int 0)))
4015 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4016 "BYTES_BIG_ENDIAN"
4017 "@
4018 rlwnm. %3,%1,%2,0xffff
4019 rlwinm. %3,%1,%h2,0xffff
4020 #
4021 #"
4022 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4023 (set_attr "length" "4,4,8,8")])
4025 (define_split
4026 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4027 (compare:CC (zero_extend:SI
4028 (subreg:HI
4029 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4030 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4031 (const_int 0)))
4032 (clobber (match_scratch:SI 3 ""))]
4033 "!BYTES_BIG_ENDIAN && reload_completed"
4034 [(set (match_dup 3)
4035 (zero_extend:SI (subreg:HI
4036 (rotate:SI (match_dup 1)
4037 (match_dup 2)) 0)))
4038 (set (match_dup 0)
4039 (compare:CC (match_dup 3)
4040 (const_int 0)))]
4041 "")
4043 (define_split
4044 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4045 (compare:CC (zero_extend:SI
4046 (subreg:HI
4047 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4048 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4049 (const_int 0)))
4050 (clobber (match_scratch:SI 3 ""))]
4051 "BYTES_BIG_ENDIAN && reload_completed"
4052 [(set (match_dup 3)
4053 (zero_extend:SI (subreg:HI
4054 (rotate:SI (match_dup 1)
4055 (match_dup 2)) 2)))
4056 (set (match_dup 0)
4057 (compare:CC (match_dup 3)
4058 (const_int 0)))]
4059 "")
4061 (define_insn "*rotlsi3_internal12le"
4062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4063 (compare:CC (zero_extend:SI
4064 (subreg:HI
4065 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4066 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4067 (const_int 0)))
4068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4069 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4070 "!BYTES_BIG_ENDIAN"
4071 "@
4072 rlwnm. %0,%1,%2,0xffff
4073 rlwinm. %0,%1,%h2,0xffff
4074 #
4075 #"
4076 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4077 (set_attr "length" "4,4,8,8")])
4079 (define_insn "*rotlsi3_internal12be"
4080 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4081 (compare:CC (zero_extend:SI
4082 (subreg:HI
4083 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4084 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4085 (const_int 0)))
4086 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4087 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4088 "BYTES_BIG_ENDIAN"
4089 "@
4090 rlwnm. %0,%1,%2,0xffff
4091 rlwinm. %0,%1,%h2,0xffff
4092 #
4093 #"
4094 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4095 (set_attr "length" "4,4,8,8")])
4097 (define_split
4098 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4099 (compare:CC (zero_extend:SI
4100 (subreg:HI
4101 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4102 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4103 (const_int 0)))
4104 (set (match_operand:SI 0 "gpc_reg_operand" "")
4105 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4106 "!BYTES_BIG_ENDIAN && reload_completed"
4107 [(set (match_dup 0)
4108 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4109 (set (match_dup 3)
4110 (compare:CC (match_dup 0)
4111 (const_int 0)))]
4112 "")
4114 (define_split
4115 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4116 (compare:CC (zero_extend:SI
4117 (subreg:HI
4118 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4119 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4120 (const_int 0)))
4121 (set (match_operand:SI 0 "gpc_reg_operand" "")
4122 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4123 "BYTES_BIG_ENDIAN && reload_completed"
4124 [(set (match_dup 0)
4125 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4126 (set (match_dup 3)
4127 (compare:CC (match_dup 0)
4128 (const_int 0)))]
4129 "")
4131 (define_insn "ashlsi3"
4132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4133 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4134 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4135 ""
4136 "@
4137 slw %0,%1,%2
4138 slwi %0,%1,%h2"
4139 [(set_attr "type" "var_shift_rotate,shift")])
4141 (define_insn "*ashlsi3_64"
4142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4143 (zero_extend:DI
4144 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4145 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4146 "TARGET_POWERPC64"
4147 "@
4148 slw %0,%1,%2
4149 slwi %0,%1,%h2"
4150 [(set_attr "type" "var_shift_rotate,shift")])
4152 (define_insn ""
4153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4154 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4155 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4156 (const_int 0)))
4157 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4158 "TARGET_32BIT"
4159 "@
4160 slw. %3,%1,%2
4161 slwi. %3,%1,%h2
4162 #
4163 #"
4164 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4165 (set_attr "length" "4,4,8,8")])
4167 (define_split
4168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4169 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "reg_or_cint_operand" ""))
4171 (const_int 0)))
4172 (clobber (match_scratch:SI 3 ""))]
4173 "TARGET_32BIT && reload_completed"
4174 [(set (match_dup 3)
4175 (ashift:SI (match_dup 1) (match_dup 2)))
4176 (set (match_dup 0)
4177 (compare:CC (match_dup 3)
4178 (const_int 0)))]
4179 "")
4181 (define_insn ""
4182 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4183 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4184 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4185 (const_int 0)))
4186 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4187 (ashift:SI (match_dup 1) (match_dup 2)))]
4188 "TARGET_32BIT"
4189 "@
4190 slw. %0,%1,%2
4191 slwi. %0,%1,%h2
4192 #
4193 #"
4194 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4195 (set_attr "length" "4,4,8,8")])
4197 (define_split
4198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4199 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4200 (match_operand:SI 2 "reg_or_cint_operand" ""))
4201 (const_int 0)))
4202 (set (match_operand:SI 0 "gpc_reg_operand" "")
4203 (ashift:SI (match_dup 1) (match_dup 2)))]
4204 "TARGET_32BIT && reload_completed"
4205 [(set (match_dup 0)
4206 (ashift:SI (match_dup 1) (match_dup 2)))
4207 (set (match_dup 3)
4208 (compare:CC (match_dup 0)
4209 (const_int 0)))]
4210 "")
4212 (define_insn "rlwinm"
4213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4214 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4215 (match_operand:SI 2 "const_int_operand" "i"))
4216 (match_operand:SI 3 "mask_operand" "n")))]
4217 "includes_lshift_p (operands[2], operands[3])"
4218 "rlwinm %0,%1,%h2,%m3,%M3")
4220 (define_insn ""
4221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4222 (compare:CC
4223 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4224 (match_operand:SI 2 "const_int_operand" "i,i"))
4225 (match_operand:SI 3 "mask_operand" "n,n"))
4226 (const_int 0)))
4227 (clobber (match_scratch:SI 4 "=r,r"))]
4228 "includes_lshift_p (operands[2], operands[3])"
4229 "@
4230 rlwinm. %4,%1,%h2,%m3,%M3
4231 #"
4232 [(set_attr "type" "delayed_compare")
4233 (set_attr "length" "4,8")])
4235 (define_split
4236 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4237 (compare:CC
4238 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4239 (match_operand:SI 2 "const_int_operand" ""))
4240 (match_operand:SI 3 "mask_operand" ""))
4241 (const_int 0)))
4242 (clobber (match_scratch:SI 4 ""))]
4243 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4244 [(set (match_dup 4)
4245 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4246 (match_dup 3)))
4247 (set (match_dup 0)
4248 (compare:CC (match_dup 4)
4249 (const_int 0)))]
4250 "")
4252 (define_insn ""
4253 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4254 (compare:CC
4255 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4256 (match_operand:SI 2 "const_int_operand" "i,i"))
4257 (match_operand:SI 3 "mask_operand" "n,n"))
4258 (const_int 0)))
4259 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4260 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4261 "includes_lshift_p (operands[2], operands[3])"
4262 "@
4263 rlwinm. %0,%1,%h2,%m3,%M3
4264 #"
4265 [(set_attr "type" "delayed_compare")
4266 (set_attr "length" "4,8")])
4268 (define_split
4269 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4270 (compare:CC
4271 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4272 (match_operand:SI 2 "const_int_operand" ""))
4273 (match_operand:SI 3 "mask_operand" ""))
4274 (const_int 0)))
4275 (set (match_operand:SI 0 "gpc_reg_operand" "")
4276 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4277 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4278 [(set (match_dup 0)
4279 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4280 (set (match_dup 4)
4281 (compare:CC (match_dup 0)
4282 (const_int 0)))]
4283 "")
4285 (define_insn "lshrsi3"
4286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4287 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4288 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4289 ""
4290 "@
4291 mr %0,%1
4292 srw %0,%1,%2
4293 srwi %0,%1,%h2"
4294 [(set_attr "type" "integer,var_shift_rotate,shift")])
4296 (define_insn "*lshrsi3_64"
4297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4298 (zero_extend:DI
4299 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4301 "TARGET_POWERPC64"
4302 "@
4303 srw %0,%1,%2
4304 srwi %0,%1,%h2"
4305 [(set_attr "type" "var_shift_rotate,shift")])
4307 (define_insn ""
4308 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4309 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4310 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4311 (const_int 0)))
4312 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4313 "TARGET_32BIT"
4314 "@
4315 mr. %1,%1
4316 srw. %3,%1,%2
4317 srwi. %3,%1,%h2
4318 #
4319 #
4320 #"
4321 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4322 (set_attr "length" "4,4,4,8,8,8")])
4324 (define_split
4325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4326 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4327 (match_operand:SI 2 "reg_or_cint_operand" ""))
4328 (const_int 0)))
4329 (clobber (match_scratch:SI 3 ""))]
4330 "TARGET_32BIT && reload_completed"
4331 [(set (match_dup 3)
4332 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4333 (set (match_dup 0)
4334 (compare:CC (match_dup 3)
4335 (const_int 0)))]
4336 "")
4338 (define_insn ""
4339 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4340 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4341 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4342 (const_int 0)))
4343 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4344 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4345 "TARGET_32BIT"
4346 "@
4347 mr. %0,%1
4348 srw. %0,%1,%2
4349 srwi. %0,%1,%h2
4350 #
4351 #
4352 #"
4353 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4354 (set_attr "length" "4,4,4,8,8,8")])
4356 (define_split
4357 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4358 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4359 (match_operand:SI 2 "reg_or_cint_operand" ""))
4360 (const_int 0)))
4361 (set (match_operand:SI 0 "gpc_reg_operand" "")
4362 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4363 "TARGET_32BIT && reload_completed"
4364 [(set (match_dup 0)
4365 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4366 (set (match_dup 3)
4367 (compare:CC (match_dup 0)
4368 (const_int 0)))]
4369 "")
4371 (define_insn ""
4372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4373 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4374 (match_operand:SI 2 "const_int_operand" "i"))
4375 (match_operand:SI 3 "mask_operand" "n")))]
4376 "includes_rshift_p (operands[2], operands[3])"
4377 "rlwinm %0,%1,%s2,%m3,%M3")
4379 (define_insn ""
4380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4381 (compare:CC
4382 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4383 (match_operand:SI 2 "const_int_operand" "i,i"))
4384 (match_operand:SI 3 "mask_operand" "n,n"))
4385 (const_int 0)))
4386 (clobber (match_scratch:SI 4 "=r,r"))]
4387 "includes_rshift_p (operands[2], operands[3])"
4388 "@
4389 rlwinm. %4,%1,%s2,%m3,%M3
4390 #"
4391 [(set_attr "type" "delayed_compare")
4392 (set_attr "length" "4,8")])
4394 (define_split
4395 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4396 (compare:CC
4397 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4398 (match_operand:SI 2 "const_int_operand" ""))
4399 (match_operand:SI 3 "mask_operand" ""))
4400 (const_int 0)))
4401 (clobber (match_scratch:SI 4 ""))]
4402 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4403 [(set (match_dup 4)
4404 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4405 (match_dup 3)))
4406 (set (match_dup 0)
4407 (compare:CC (match_dup 4)
4408 (const_int 0)))]
4409 "")
4411 (define_insn ""
4412 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4413 (compare:CC
4414 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4415 (match_operand:SI 2 "const_int_operand" "i,i"))
4416 (match_operand:SI 3 "mask_operand" "n,n"))
4417 (const_int 0)))
4418 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4419 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4420 "includes_rshift_p (operands[2], operands[3])"
4421 "@
4422 rlwinm. %0,%1,%s2,%m3,%M3
4423 #"
4424 [(set_attr "type" "delayed_compare")
4425 (set_attr "length" "4,8")])
4427 (define_split
4428 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4429 (compare:CC
4430 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4431 (match_operand:SI 2 "const_int_operand" ""))
4432 (match_operand:SI 3 "mask_operand" ""))
4433 (const_int 0)))
4434 (set (match_operand:SI 0 "gpc_reg_operand" "")
4435 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4436 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4437 [(set (match_dup 0)
4438 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4439 (set (match_dup 4)
4440 (compare:CC (match_dup 0)
4441 (const_int 0)))]
4442 "")
4444 (define_insn "*lshiftrt_internal1le"
4445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4446 (zero_extend:SI
4447 (subreg:QI
4448 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4449 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4450 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4451 "rlwinm %0,%1,%s2,0xff")
4453 (define_insn "*lshiftrt_internal1be"
4454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4455 (zero_extend:SI
4456 (subreg:QI
4457 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4458 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4459 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4460 "rlwinm %0,%1,%s2,0xff")
4462 (define_insn "*lshiftrt_internal2le"
4463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4464 (compare:CC
4465 (zero_extend:SI
4466 (subreg:QI
4467 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4468 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4469 (const_int 0)))
4470 (clobber (match_scratch:SI 3 "=r,r"))]
4471 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4472 "@
4473 rlwinm. %3,%1,%s2,0xff
4474 #"
4475 [(set_attr "type" "delayed_compare")
4476 (set_attr "length" "4,8")])
4478 (define_insn "*lshiftrt_internal2be"
4479 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4480 (compare:CC
4481 (zero_extend:SI
4482 (subreg:QI
4483 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4484 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4485 (const_int 0)))
4486 (clobber (match_scratch:SI 3 "=r,r"))]
4487 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4488 "@
4489 rlwinm. %3,%1,%s2,0xff
4490 #"
4491 [(set_attr "type" "delayed_compare")
4492 (set_attr "length" "4,8")])
4494 (define_split
4495 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4496 (compare:CC
4497 (zero_extend:SI
4498 (subreg:QI
4499 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4500 (match_operand:SI 2 "const_int_operand" "")) 0))
4501 (const_int 0)))
4502 (clobber (match_scratch:SI 3 ""))]
4503 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4504 [(set (match_dup 3)
4505 (zero_extend:SI (subreg:QI
4506 (lshiftrt:SI (match_dup 1)
4507 (match_dup 2)) 0)))
4508 (set (match_dup 0)
4509 (compare:CC (match_dup 3)
4510 (const_int 0)))]
4511 "")
4513 (define_split
4514 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4515 (compare:CC
4516 (zero_extend:SI
4517 (subreg:QI
4518 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4519 (match_operand:SI 2 "const_int_operand" "")) 3))
4520 (const_int 0)))
4521 (clobber (match_scratch:SI 3 ""))]
4522 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4523 [(set (match_dup 3)
4524 (zero_extend:SI (subreg:QI
4525 (lshiftrt:SI (match_dup 1)
4526 (match_dup 2)) 3)))
4527 (set (match_dup 0)
4528 (compare:CC (match_dup 3)
4529 (const_int 0)))]
4530 "")
4532 (define_insn "*lshiftrt_internal3le"
4533 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4534 (compare:CC
4535 (zero_extend:SI
4536 (subreg:QI
4537 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4538 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4539 (const_int 0)))
4540 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4541 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4542 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4543 "@
4544 rlwinm. %0,%1,%s2,0xff
4545 #"
4546 [(set_attr "type" "delayed_compare")
4547 (set_attr "length" "4,8")])
4549 (define_insn "*lshiftrt_internal3be"
4550 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4551 (compare:CC
4552 (zero_extend:SI
4553 (subreg:QI
4554 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4555 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4556 (const_int 0)))
4557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4558 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4559 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4560 "@
4561 rlwinm. %0,%1,%s2,0xff
4562 #"
4563 [(set_attr "type" "delayed_compare")
4564 (set_attr "length" "4,8")])
4566 (define_split
4567 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4568 (compare:CC
4569 (zero_extend:SI
4570 (subreg:QI
4571 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4572 (match_operand:SI 2 "const_int_operand" "")) 0))
4573 (const_int 0)))
4574 (set (match_operand:SI 0 "gpc_reg_operand" "")
4575 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4576 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4577 [(set (match_dup 0)
4578 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4579 (set (match_dup 3)
4580 (compare:CC (match_dup 0)
4581 (const_int 0)))]
4582 "")
4584 (define_split
4585 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4586 (compare:CC
4587 (zero_extend:SI
4588 (subreg:QI
4589 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4590 (match_operand:SI 2 "const_int_operand" "")) 3))
4591 (const_int 0)))
4592 (set (match_operand:SI 0 "gpc_reg_operand" "")
4593 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4594 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4595 [(set (match_dup 0)
4596 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4597 (set (match_dup 3)
4598 (compare:CC (match_dup 0)
4599 (const_int 0)))]
4600 "")
4602 (define_insn "*lshiftrt_internal4le"
4603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4604 (zero_extend:SI
4605 (subreg:HI
4606 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4607 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4608 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4609 "rlwinm %0,%1,%s2,0xffff")
4611 (define_insn "*lshiftrt_internal4be"
4612 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4613 (zero_extend:SI
4614 (subreg:HI
4615 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4616 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4617 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4618 "rlwinm %0,%1,%s2,0xffff")
4620 (define_insn "*lshiftrt_internal5le"
4621 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4622 (compare:CC
4623 (zero_extend:SI
4624 (subreg:HI
4625 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4626 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4627 (const_int 0)))
4628 (clobber (match_scratch:SI 3 "=r,r"))]
4629 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4630 "@
4631 rlwinm. %3,%1,%s2,0xffff
4632 #"
4633 [(set_attr "type" "delayed_compare")
4634 (set_attr "length" "4,8")])
4636 (define_insn "*lshiftrt_internal5be"
4637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4638 (compare:CC
4639 (zero_extend:SI
4640 (subreg:HI
4641 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4642 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4643 (const_int 0)))
4644 (clobber (match_scratch:SI 3 "=r,r"))]
4645 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4646 "@
4647 rlwinm. %3,%1,%s2,0xffff
4648 #"
4649 [(set_attr "type" "delayed_compare")
4650 (set_attr "length" "4,8")])
4652 (define_split
4653 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4654 (compare:CC
4655 (zero_extend:SI
4656 (subreg:HI
4657 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4658 (match_operand:SI 2 "const_int_operand" "")) 0))
4659 (const_int 0)))
4660 (clobber (match_scratch:SI 3 ""))]
4661 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4662 [(set (match_dup 3)
4663 (zero_extend:SI (subreg:HI
4664 (lshiftrt:SI (match_dup 1)
4665 (match_dup 2)) 0)))
4666 (set (match_dup 0)
4667 (compare:CC (match_dup 3)
4668 (const_int 0)))]
4669 "")
4671 (define_split
4672 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4673 (compare:CC
4674 (zero_extend:SI
4675 (subreg:HI
4676 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4677 (match_operand:SI 2 "const_int_operand" "")) 2))
4678 (const_int 0)))
4679 (clobber (match_scratch:SI 3 ""))]
4680 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4681 [(set (match_dup 3)
4682 (zero_extend:SI (subreg:HI
4683 (lshiftrt:SI (match_dup 1)
4684 (match_dup 2)) 2)))
4685 (set (match_dup 0)
4686 (compare:CC (match_dup 3)
4687 (const_int 0)))]
4688 "")
4690 (define_insn "*lshiftrt_internal5le"
4691 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4692 (compare:CC
4693 (zero_extend:SI
4694 (subreg:HI
4695 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4696 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4697 (const_int 0)))
4698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4699 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4700 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4701 "@
4702 rlwinm. %0,%1,%s2,0xffff
4703 #"
4704 [(set_attr "type" "delayed_compare")
4705 (set_attr "length" "4,8")])
4707 (define_insn "*lshiftrt_internal5be"
4708 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4709 (compare:CC
4710 (zero_extend:SI
4711 (subreg:HI
4712 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4713 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4714 (const_int 0)))
4715 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4716 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4717 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4718 "@
4719 rlwinm. %0,%1,%s2,0xffff
4720 #"
4721 [(set_attr "type" "delayed_compare")
4722 (set_attr "length" "4,8")])
4724 (define_split
4725 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4726 (compare:CC
4727 (zero_extend:SI
4728 (subreg:HI
4729 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4730 (match_operand:SI 2 "const_int_operand" "")) 0))
4731 (const_int 0)))
4732 (set (match_operand:SI 0 "gpc_reg_operand" "")
4733 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4734 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4735 [(set (match_dup 0)
4736 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4737 (set (match_dup 3)
4738 (compare:CC (match_dup 0)
4739 (const_int 0)))]
4740 "")
4742 (define_split
4743 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4744 (compare:CC
4745 (zero_extend:SI
4746 (subreg:HI
4747 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4748 (match_operand:SI 2 "const_int_operand" "")) 2))
4749 (const_int 0)))
4750 (set (match_operand:SI 0 "gpc_reg_operand" "")
4751 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4752 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4753 [(set (match_dup 0)
4754 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4755 (set (match_dup 3)
4756 (compare:CC (match_dup 0)
4757 (const_int 0)))]
4758 "")
4760 (define_insn "ashrsi3"
4761 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4762 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4763 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4764 ""
4765 "@
4766 sraw %0,%1,%2
4767 srawi %0,%1,%h2"
4768 [(set_attr "type" "var_shift_rotate,shift")])
4770 (define_insn "*ashrsi3_64"
4771 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4772 (sign_extend:DI
4773 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4774 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4775 "TARGET_POWERPC64"
4776 "@
4777 sraw %0,%1,%2
4778 srawi %0,%1,%h2"
4779 [(set_attr "type" "var_shift_rotate,shift")])
4781 (define_insn ""
4782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4783 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4784 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4785 (const_int 0)))
4786 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4787 ""
4788 "@
4789 sraw. %3,%1,%2
4790 srawi. %3,%1,%h2
4791 #
4792 #"
4793 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4794 (set_attr "length" "4,4,8,8")])
4796 (define_split
4797 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4798 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4799 (match_operand:SI 2 "reg_or_cint_operand" ""))
4800 (const_int 0)))
4801 (clobber (match_scratch:SI 3 ""))]
4802 "reload_completed"
4803 [(set (match_dup 3)
4804 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4805 (set (match_dup 0)
4806 (compare:CC (match_dup 3)
4807 (const_int 0)))]
4808 "")
4810 (define_insn ""
4811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4812 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4813 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4814 (const_int 0)))
4815 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4816 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4817 ""
4818 "@
4819 sraw. %0,%1,%2
4820 srawi. %0,%1,%h2
4821 #
4822 #"
4823 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4824 (set_attr "length" "4,4,8,8")])
4825 \f
4826 ;; Builtins to replace a division to generate FRE reciprocal estimate
4827 ;; instructions and the necessary fixup instructions
4828 (define_expand "recip<mode>3"
4829 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4830 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4831 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4832 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4833 {
4834 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4835 DONE;
4836 })
4838 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4839 ;; hardware division. This is only done before register allocation and with
4840 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4841 (define_split
4842 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4843 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4844 (match_operand 2 "gpc_reg_operand" "")))]
4845 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4846 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4847 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4848 [(const_int 0)]
4849 {
4850 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4851 DONE;
4852 })
4854 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4855 ;; appropriate fixup.
4856 (define_expand "rsqrt<mode>2"
4857 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4858 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4859 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4860 {
4861 rs6000_emit_swrsqrt (operands[0], operands[1]);
4862 DONE;
4863 })
4864 \f
4865 (define_split
4866 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4867 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4868 (match_operand:SI 2 "reg_or_cint_operand" ""))
4869 (const_int 0)))
4870 (set (match_operand:SI 0 "gpc_reg_operand" "")
4871 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4872 "reload_completed"
4873 [(set (match_dup 0)
4874 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4875 (set (match_dup 3)
4876 (compare:CC (match_dup 0)
4877 (const_int 0)))]
4878 "")
4880 ;; Floating-point insns, excluding normal data motion.
4881 ;;
4882 ;; PowerPC has a full set of single-precision floating point instructions.
4883 ;;
4884 ;; For the POWER architecture, we pretend that we have both SFmode and
4885 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4886 ;; The only conversions we will do will be when storing to memory. In that
4887 ;; case, we will use the "frsp" instruction before storing.
4888 ;;
4889 ;; Note that when we store into a single-precision memory location, we need to
4890 ;; use the frsp insn first. If the register being stored isn't dead, we
4891 ;; need a scratch register for the frsp. But this is difficult when the store
4892 ;; is done by reload. It is not incorrect to do the frsp on the register in
4893 ;; this case, we just lose precision that we would have otherwise gotten but
4894 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4896 (define_expand "extendsfdf2"
4897 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4898 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4899 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4900 "")
4902 (define_insn_and_split "*extendsfdf2_fpr"
4903 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4904 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4905 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4906 "@
4907 #
4908 fmr %0,%1
4909 lfs%U1%X1 %0,%1"
4910 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4911 [(const_int 0)]
4912 {
4913 emit_note (NOTE_INSN_DELETED);
4914 DONE;
4915 }
4916 [(set_attr_alternative "type"
4917 [(const_string "fp")
4918 (const_string "fp")
4919 (if_then_else
4920 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
4921 (const_string "fpload_ux")
4922 (if_then_else
4923 (match_test "update_address_mem (operands[1], VOIDmode)")
4924 (const_string "fpload_u")
4925 (const_string "fpload")))])])
4927 (define_expand "truncdfsf2"
4928 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4929 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4930 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4931 "")
4933 (define_insn "*truncdfsf2_fpr"
4934 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4935 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4936 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4937 "frsp %0,%1"
4938 [(set_attr "type" "fp")])
4940 (define_expand "negsf2"
4941 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4942 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4943 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4944 "")
4946 (define_insn "*negsf2"
4947 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4948 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4949 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4950 "fneg %0,%1"
4951 [(set_attr "type" "fp")])
4953 (define_expand "abssf2"
4954 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4955 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4956 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4957 "")
4959 (define_insn "*abssf2"
4960 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4961 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4962 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4963 "fabs %0,%1"
4964 [(set_attr "type" "fp")])
4966 (define_insn ""
4967 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4968 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4970 "fnabs %0,%1"
4971 [(set_attr "type" "fp")])
4973 (define_expand "addsf3"
4974 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4975 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4976 (match_operand:SF 2 "gpc_reg_operand" "")))]
4977 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4978 "")
4980 (define_insn ""
4981 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4982 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4983 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4984 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4985 "fadds %0,%1,%2"
4986 [(set_attr "type" "fp")
4987 (set_attr "fp_type" "fp_addsub_s")])
4989 (define_expand "subsf3"
4990 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4991 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4992 (match_operand:SF 2 "gpc_reg_operand" "")))]
4993 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4994 "")
4996 (define_insn ""
4997 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4998 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4999 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5000 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5001 "fsubs %0,%1,%2"
5002 [(set_attr "type" "fp")
5003 (set_attr "fp_type" "fp_addsub_s")])
5005 (define_expand "mulsf3"
5006 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5007 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5008 (match_operand:SF 2 "gpc_reg_operand" "")))]
5009 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5010 "")
5012 (define_insn ""
5013 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5014 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5015 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5016 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5017 "fmuls %0,%1,%2"
5018 [(set_attr "type" "fp")
5019 (set_attr "fp_type" "fp_mul_s")])
5021 (define_expand "divsf3"
5022 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5023 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5024 (match_operand:SF 2 "gpc_reg_operand" "")))]
5025 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5026 "")
5028 (define_insn ""
5029 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5030 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5031 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5032 "TARGET_HARD_FLOAT && TARGET_FPRS
5033 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5034 "fdivs %0,%1,%2"
5035 [(set_attr "type" "sdiv")])
5037 (define_insn "fres"
5038 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5039 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5040 "TARGET_FRES"
5041 "fres %0,%1"
5042 [(set_attr "type" "fp")])
5044 ; builtin fmaf support
5045 (define_insn "*fmasf4_fpr"
5046 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5047 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5048 (match_operand:SF 2 "gpc_reg_operand" "f")
5049 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5050 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5051 "fmadds %0,%1,%2,%3"
5052 [(set_attr "type" "fp")
5053 (set_attr "fp_type" "fp_maddsub_s")])
5055 (define_insn "*fmssf4_fpr"
5056 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5057 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5058 (match_operand:SF 2 "gpc_reg_operand" "f")
5059 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5060 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5061 "fmsubs %0,%1,%2,%3"
5062 [(set_attr "type" "fp")
5063 (set_attr "fp_type" "fp_maddsub_s")])
5065 (define_insn "*nfmasf4_fpr"
5066 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5067 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5068 (match_operand:SF 2 "gpc_reg_operand" "f")
5069 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5070 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5071 "fnmadds %0,%1,%2,%3"
5072 [(set_attr "type" "fp")
5073 (set_attr "fp_type" "fp_maddsub_s")])
5075 (define_insn "*nfmssf4_fpr"
5076 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5077 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5078 (match_operand:SF 2 "gpc_reg_operand" "f")
5079 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5080 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5081 "fnmsubs %0,%1,%2,%3"
5082 [(set_attr "type" "fp")
5083 (set_attr "fp_type" "fp_maddsub_s")])
5085 (define_expand "sqrtsf2"
5086 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5087 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5088 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
5089 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5090 && !TARGET_SIMPLE_FPU"
5091 "")
5093 (define_insn ""
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5095 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5096 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5097 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5098 "fsqrts %0,%1"
5099 [(set_attr "type" "ssqrt")])
5101 (define_insn "*rsqrtsf_internal1"
5102 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5103 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5104 UNSPEC_RSQRT))]
5105 "TARGET_FRSQRTES"
5106 "frsqrtes %0,%1"
5107 [(set_attr "type" "fp")])
5109 (define_expand "copysign<mode>3"
5110 [(set (match_dup 3)
5111 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5112 (set (match_dup 4)
5113 (neg:SFDF (abs:SFDF (match_dup 1))))
5114 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5115 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5116 (match_dup 5))
5117 (match_dup 3)
5118 (match_dup 4)))]
5119 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5120 && ((TARGET_PPC_GFXOPT
5121 && !HONOR_NANS (<MODE>mode)
5122 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5123 || TARGET_CMPB
5124 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5125 {
5126 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5127 {
5128 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5129 operands[2]));
5130 DONE;
5131 }
5133 operands[3] = gen_reg_rtx (<MODE>mode);
5134 operands[4] = gen_reg_rtx (<MODE>mode);
5135 operands[5] = CONST0_RTX (<MODE>mode);
5136 })
5138 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5139 ;; compiler from optimizing -0.0
5140 (define_insn "copysign<mode>3_fcpsgn"
5141 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5142 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5143 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5144 UNSPEC_COPYSIGN))]
5145 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5146 "fcpsgn %0,%2,%1"
5147 [(set_attr "type" "fp")])
5149 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5150 ;; fsel instruction and some auxiliary computations. Then we just have a
5151 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5152 ;; combine.
5153 (define_expand "smaxsf3"
5154 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5155 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5156 (match_operand:SF 2 "gpc_reg_operand" ""))
5157 (match_dup 1)
5158 (match_dup 2)))]
5159 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5160 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5161 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5163 (define_expand "sminsf3"
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5165 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5166 (match_operand:SF 2 "gpc_reg_operand" ""))
5167 (match_dup 2)
5168 (match_dup 1)))]
5169 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5170 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5171 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5173 (define_split
5174 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5175 (match_operator:SF 3 "min_max_operator"
5176 [(match_operand:SF 1 "gpc_reg_operand" "")
5177 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5178 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5179 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5180 [(const_int 0)]
5181 "
5182 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5183 operands[1], operands[2]);
5184 DONE;
5185 }")
5187 (define_expand "mov<mode>cc"
5188 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5189 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5190 (match_operand:GPR 2 "gpc_reg_operand" "")
5191 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5192 "TARGET_ISEL<sel>"
5193 "
5194 {
5195 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5196 DONE;
5197 else
5198 FAIL;
5199 }")
5201 ;; We use the BASE_REGS for the isel input operands because, if rA is
5202 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5203 ;; because we may switch the operands and rB may end up being rA.
5204 ;;
5205 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5206 ;; leave out the mode in operand 4 and use one pattern, but reload can
5207 ;; change the mode underneath our feet and then gets confused trying
5208 ;; to reload the value.
5209 (define_insn "isel_signed_<mode>"
5210 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5211 (if_then_else:GPR
5212 (match_operator 1 "scc_comparison_operator"
5213 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5214 (const_int 0)])
5215 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5216 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5217 "TARGET_ISEL<sel>"
5218 "*
5219 { return output_isel (operands); }"
5220 [(set_attr "type" "isel")
5221 (set_attr "length" "4")])
5223 (define_insn "isel_unsigned_<mode>"
5224 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5225 (if_then_else:GPR
5226 (match_operator 1 "scc_comparison_operator"
5227 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5228 (const_int 0)])
5229 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5230 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5231 "TARGET_ISEL<sel>"
5232 "*
5233 { return output_isel (operands); }"
5234 [(set_attr "type" "isel")
5235 (set_attr "length" "4")])
5237 ;; These patterns can be useful for combine; they let combine know that
5238 ;; isel can handle reversed comparisons so long as the operands are
5239 ;; registers.
5241 (define_insn "*isel_reversed_signed_<mode>"
5242 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5243 (if_then_else:GPR
5244 (match_operator 1 "scc_rev_comparison_operator"
5245 [(match_operand:CC 4 "cc_reg_operand" "y")
5246 (const_int 0)])
5247 (match_operand:GPR 2 "gpc_reg_operand" "b")
5248 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5249 "TARGET_ISEL<sel>"
5250 "*
5251 { return output_isel (operands); }"
5252 [(set_attr "type" "isel")
5253 (set_attr "length" "4")])
5255 (define_insn "*isel_reversed_unsigned_<mode>"
5256 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5257 (if_then_else:GPR
5258 (match_operator 1 "scc_rev_comparison_operator"
5259 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5260 (const_int 0)])
5261 (match_operand:GPR 2 "gpc_reg_operand" "b")
5262 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5263 "TARGET_ISEL<sel>"
5264 "*
5265 { return output_isel (operands); }"
5266 [(set_attr "type" "isel")
5267 (set_attr "length" "4")])
5269 (define_expand "movsfcc"
5270 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5271 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5272 (match_operand:SF 2 "gpc_reg_operand" "")
5273 (match_operand:SF 3 "gpc_reg_operand" "")))]
5274 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5275 "
5276 {
5277 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5278 DONE;
5279 else
5280 FAIL;
5281 }")
5283 (define_insn "*fselsfsf4"
5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5286 (match_operand:SF 4 "zero_fp_constant" "F"))
5287 (match_operand:SF 2 "gpc_reg_operand" "f")
5288 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5289 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5290 "fsel %0,%1,%2,%3"
5291 [(set_attr "type" "fp")])
5293 (define_insn "*fseldfsf4"
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5295 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5296 (match_operand:DF 4 "zero_fp_constant" "F"))
5297 (match_operand:SF 2 "gpc_reg_operand" "f")
5298 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5299 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5300 "fsel %0,%1,%2,%3"
5301 [(set_attr "type" "fp")])
5303 (define_expand "negdf2"
5304 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5305 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5306 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5307 "")
5309 (define_insn "*negdf2_fpr"
5310 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5311 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5312 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5313 && !VECTOR_UNIT_VSX_P (DFmode)"
5314 "fneg %0,%1"
5315 [(set_attr "type" "fp")])
5317 (define_expand "absdf2"
5318 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5319 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5320 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5321 "")
5323 (define_insn "*absdf2_fpr"
5324 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5325 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5326 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5327 && !VECTOR_UNIT_VSX_P (DFmode)"
5328 "fabs %0,%1"
5329 [(set_attr "type" "fp")])
5331 (define_insn "*nabsdf2_fpr"
5332 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5333 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5334 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5335 && !VECTOR_UNIT_VSX_P (DFmode)"
5336 "fnabs %0,%1"
5337 [(set_attr "type" "fp")])
5339 (define_expand "adddf3"
5340 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5341 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5342 (match_operand:DF 2 "gpc_reg_operand" "")))]
5343 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5344 "")
5346 (define_insn "*adddf3_fpr"
5347 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5348 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5349 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5350 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5351 && !VECTOR_UNIT_VSX_P (DFmode)"
5352 "fadd %0,%1,%2"
5353 [(set_attr "type" "fp")
5354 (set_attr "fp_type" "fp_addsub_d")])
5356 (define_expand "subdf3"
5357 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5358 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5359 (match_operand:DF 2 "gpc_reg_operand" "")))]
5360 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5361 "")
5363 (define_insn "*subdf3_fpr"
5364 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5365 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5366 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5367 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5368 && !VECTOR_UNIT_VSX_P (DFmode)"
5369 "fsub %0,%1,%2"
5370 [(set_attr "type" "fp")
5371 (set_attr "fp_type" "fp_addsub_d")])
5373 (define_expand "muldf3"
5374 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5375 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5376 (match_operand:DF 2 "gpc_reg_operand" "")))]
5377 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5378 "")
5380 (define_insn "*muldf3_fpr"
5381 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5382 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5383 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5384 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5385 && !VECTOR_UNIT_VSX_P (DFmode)"
5386 "fmul %0,%1,%2"
5387 [(set_attr "type" "dmul")
5388 (set_attr "fp_type" "fp_mul_d")])
5390 (define_expand "divdf3"
5391 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5392 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5393 (match_operand:DF 2 "gpc_reg_operand" "")))]
5394 "TARGET_HARD_FLOAT
5395 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5396 && !TARGET_SIMPLE_FPU"
5397 "")
5399 (define_insn "*divdf3_fpr"
5400 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5401 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5402 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5403 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
5404 && !VECTOR_UNIT_VSX_P (DFmode)"
5405 "fdiv %0,%1,%2"
5406 [(set_attr "type" "ddiv")])
5408 (define_insn "*fred_fpr"
5409 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5410 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5411 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
5412 "fre %0,%1"
5413 [(set_attr "type" "fp")])
5415 (define_insn "*rsqrtdf_internal1"
5416 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5417 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
5418 UNSPEC_RSQRT))]
5419 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
5420 "frsqrte %0,%1"
5421 [(set_attr "type" "fp")])
5423 ; builtin fma support
5424 (define_insn "*fmadf4_fpr"
5425 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5426 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5427 (match_operand:DF 2 "gpc_reg_operand" "f")
5428 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5429 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5430 && VECTOR_UNIT_NONE_P (DFmode)"
5431 "fmadd %0,%1,%2,%3"
5432 [(set_attr "type" "fp")
5433 (set_attr "fp_type" "fp_maddsub_d")])
5435 (define_insn "*fmsdf4_fpr"
5436 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5437 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5438 (match_operand:DF 2 "gpc_reg_operand" "f")
5439 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5440 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5441 && VECTOR_UNIT_NONE_P (DFmode)"
5442 "fmsub %0,%1,%2,%3"
5443 [(set_attr "type" "fp")
5444 (set_attr "fp_type" "fp_maddsub_d")])
5446 (define_insn "*nfmadf4_fpr"
5447 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5448 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5449 (match_operand:DF 2 "gpc_reg_operand" "f")
5450 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5451 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5452 && VECTOR_UNIT_NONE_P (DFmode)"
5453 "fnmadd %0,%1,%2,%3"
5454 [(set_attr "type" "fp")
5455 (set_attr "fp_type" "fp_maddsub_d")])
5457 (define_insn "*nfmsdf4_fpr"
5458 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5459 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5460 (match_operand:DF 2 "gpc_reg_operand" "f")
5461 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5462 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5463 && VECTOR_UNIT_NONE_P (DFmode)"
5464 "fnmsub %0,%1,%2,%3"
5465 [(set_attr "type" "fp")
5466 (set_attr "fp_type" "fp_maddsub_d")])
5468 (define_expand "sqrtdf2"
5469 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5470 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5471 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5472 "")
5474 (define_insn "*sqrtdf2_fpr"
5475 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5476 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5477 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5478 && !VECTOR_UNIT_VSX_P (DFmode)"
5479 "fsqrt %0,%1"
5480 [(set_attr "type" "dsqrt")])
5482 ;; The conditional move instructions allow us to perform max and min
5483 ;; operations even when
5485 (define_expand "smaxdf3"
5486 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5487 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5488 (match_operand:DF 2 "gpc_reg_operand" ""))
5489 (match_dup 1)
5490 (match_dup 2)))]
5491 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5492 && !flag_trapping_math"
5493 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5495 (define_expand "smindf3"
5496 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5497 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5498 (match_operand:DF 2 "gpc_reg_operand" ""))
5499 (match_dup 2)
5500 (match_dup 1)))]
5501 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5502 && !flag_trapping_math"
5503 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5505 (define_split
5506 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5507 (match_operator:DF 3 "min_max_operator"
5508 [(match_operand:DF 1 "gpc_reg_operand" "")
5509 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5510 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5511 && !flag_trapping_math"
5512 [(const_int 0)]
5513 "
5514 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5515 operands[1], operands[2]);
5516 DONE;
5517 }")
5519 (define_expand "movdfcc"
5520 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5521 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5522 (match_operand:DF 2 "gpc_reg_operand" "")
5523 (match_operand:DF 3 "gpc_reg_operand" "")))]
5524 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5525 "
5526 {
5527 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5528 DONE;
5529 else
5530 FAIL;
5531 }")
5533 (define_insn "*fseldfdf4"
5534 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5535 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5536 (match_operand:DF 4 "zero_fp_constant" "F"))
5537 (match_operand:DF 2 "gpc_reg_operand" "d")
5538 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5539 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5540 "fsel %0,%1,%2,%3"
5541 [(set_attr "type" "fp")])
5543 (define_insn "*fselsfdf4"
5544 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5545 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5546 (match_operand:SF 4 "zero_fp_constant" "F"))
5547 (match_operand:DF 2 "gpc_reg_operand" "d")
5548 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5549 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5550 "fsel %0,%1,%2,%3"
5551 [(set_attr "type" "fp")])
5552 \f
5553 ;; Conversions to and from floating-point.
5555 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5556 ; don't want to support putting SImode in FPR registers.
5557 (define_insn "lfiwax"
5558 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5559 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5560 UNSPEC_LFIWAX))]
5561 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5562 "lfiwax %0,%y1"
5563 [(set_attr "type" "fpload")])
5565 ; This split must be run before register allocation because it allocates the
5566 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5567 ; it earlier to allow for the combiner to merge insns together where it might
5568 ; not be needed and also in case the insns are deleted as dead code.
5570 (define_insn_and_split "floatsi<mode>2_lfiwax"
5571 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5572 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5573 (clobber (match_scratch:DI 2 "=d"))]
5574 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5575 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5576 "#"
5577 ""
5578 [(pc)]
5579 "
5580 {
5581 rtx dest = operands[0];
5582 rtx src = operands[1];
5583 rtx tmp;
5585 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5586 tmp = convert_to_mode (DImode, src, false);
5587 else
5588 {
5589 tmp = operands[2];
5590 if (GET_CODE (tmp) == SCRATCH)
5591 tmp = gen_reg_rtx (DImode);
5592 if (MEM_P (src))
5593 {
5594 src = rs6000_address_for_fpconvert (src);
5595 emit_insn (gen_lfiwax (tmp, src));
5596 }
5597 else
5598 {
5599 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5600 emit_move_insn (stack, src);
5601 emit_insn (gen_lfiwax (tmp, stack));
5602 }
5603 }
5604 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5605 DONE;
5606 }"
5607 [(set_attr "length" "12")
5608 (set_attr "type" "fpload")])
5610 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5611 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5612 (float:SFDF
5613 (sign_extend:DI
5614 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5615 (clobber (match_scratch:DI 2 "=0,d"))]
5616 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5617 && <SI_CONVERT_FP>"
5618 "#"
5619 ""
5620 [(pc)]
5621 "
5622 {
5623 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5624 if (GET_CODE (operands[2]) == SCRATCH)
5625 operands[2] = gen_reg_rtx (DImode);
5626 emit_insn (gen_lfiwax (operands[2], operands[1]));
5627 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5628 DONE;
5629 }"
5630 [(set_attr "length" "8")
5631 (set_attr "type" "fpload")])
5633 (define_insn "lfiwzx"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5635 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5636 UNSPEC_LFIWZX))]
5637 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5638 "lfiwzx %0,%y1"
5639 [(set_attr "type" "fpload")])
5641 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5642 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5643 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5644 (clobber (match_scratch:DI 2 "=d"))]
5645 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5646 && <SI_CONVERT_FP>"
5647 "#"
5648 ""
5649 [(pc)]
5650 "
5651 {
5652 rtx dest = operands[0];
5653 rtx src = operands[1];
5654 rtx tmp;
5656 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5657 tmp = convert_to_mode (DImode, src, true);
5658 else
5659 {
5660 tmp = operands[2];
5661 if (GET_CODE (tmp) == SCRATCH)
5662 tmp = gen_reg_rtx (DImode);
5663 if (MEM_P (src))
5664 {
5665 src = rs6000_address_for_fpconvert (src);
5666 emit_insn (gen_lfiwzx (tmp, src));
5667 }
5668 else
5669 {
5670 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5671 emit_move_insn (stack, src);
5672 emit_insn (gen_lfiwzx (tmp, stack));
5673 }
5674 }
5675 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5676 DONE;
5677 }"
5678 [(set_attr "length" "12")
5679 (set_attr "type" "fpload")])
5681 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5682 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5683 (unsigned_float:SFDF
5684 (zero_extend:DI
5685 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5686 (clobber (match_scratch:DI 2 "=0,d"))]
5687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5688 && <SI_CONVERT_FP>"
5689 "#"
5690 ""
5691 [(pc)]
5692 "
5693 {
5694 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5695 if (GET_CODE (operands[2]) == SCRATCH)
5696 operands[2] = gen_reg_rtx (DImode);
5697 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5698 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5699 DONE;
5700 }"
5701 [(set_attr "length" "8")
5702 (set_attr "type" "fpload")])
5704 ; For each of these conversions, there is a define_expand, a define_insn
5705 ; with a '#' template, and a define_split (with C code). The idea is
5706 ; to allow constant folding with the template of the define_insn,
5707 ; then to have the insns split later (between sched1 and final).
5709 (define_expand "floatsidf2"
5710 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5711 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5712 (use (match_dup 2))
5713 (use (match_dup 3))
5714 (clobber (match_dup 4))
5715 (clobber (match_dup 5))
5716 (clobber (match_dup 6))])]
5717 "TARGET_HARD_FLOAT
5718 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5719 "
5720 {
5721 if (TARGET_E500_DOUBLE)
5722 {
5723 if (!REG_P (operands[1]))
5724 operands[1] = force_reg (SImode, operands[1]);
5725 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5726 DONE;
5727 }
5728 else if (TARGET_LFIWAX && TARGET_FCFID)
5729 {
5730 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5731 DONE;
5732 }
5733 else if (TARGET_FCFID)
5734 {
5735 rtx dreg = operands[1];
5736 if (!REG_P (dreg))
5737 dreg = force_reg (SImode, dreg);
5738 dreg = convert_to_mode (DImode, dreg, false);
5739 emit_insn (gen_floatdidf2 (operands[0], dreg));
5740 DONE;
5741 }
5743 if (!REG_P (operands[1]))
5744 operands[1] = force_reg (SImode, operands[1]);
5745 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5746 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5747 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5748 operands[5] = gen_reg_rtx (DFmode);
5749 operands[6] = gen_reg_rtx (SImode);
5750 }")
5752 (define_insn_and_split "*floatsidf2_internal"
5753 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5754 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5755 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5756 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5757 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5758 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5759 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5760 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5761 "#"
5762 ""
5763 [(pc)]
5764 "
5765 {
5766 rtx lowword, highword;
5767 gcc_assert (MEM_P (operands[4]));
5768 highword = adjust_address (operands[4], SImode, 0);
5769 lowword = adjust_address (operands[4], SImode, 4);
5770 if (! WORDS_BIG_ENDIAN)
5771 {
5772 rtx tmp;
5773 tmp = highword; highword = lowword; lowword = tmp;
5774 }
5776 emit_insn (gen_xorsi3 (operands[6], operands[1],
5777 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5778 emit_move_insn (lowword, operands[6]);
5779 emit_move_insn (highword, operands[2]);
5780 emit_move_insn (operands[5], operands[4]);
5781 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5782 DONE;
5783 }"
5784 [(set_attr "length" "24")
5785 (set_attr "type" "fp")])
5787 ;; If we don't have a direct conversion to single precision, don't enable this
5788 ;; conversion for 32-bit without fast math, because we don't have the insn to
5789 ;; generate the fixup swizzle to avoid double rounding problems.
5790 (define_expand "floatunssisf2"
5791 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5792 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5793 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5794 && (!TARGET_FPRS
5795 || (TARGET_FPRS
5796 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5797 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5798 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5799 "
5800 {
5801 if (!TARGET_FPRS)
5802 {
5803 if (!REG_P (operands[1]))
5804 operands[1] = force_reg (SImode, operands[1]);
5805 }
5806 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5807 {
5808 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5809 DONE;
5810 }
5811 else
5812 {
5813 rtx dreg = operands[1];
5814 if (!REG_P (dreg))
5815 dreg = force_reg (SImode, dreg);
5816 dreg = convert_to_mode (DImode, dreg, true);
5817 emit_insn (gen_floatdisf2 (operands[0], dreg));
5818 DONE;
5819 }
5820 }")
5822 (define_expand "floatunssidf2"
5823 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5824 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5825 (use (match_dup 2))
5826 (use (match_dup 3))
5827 (clobber (match_dup 4))
5828 (clobber (match_dup 5))])]
5829 "TARGET_HARD_FLOAT
5830 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5831 "
5832 {
5833 if (TARGET_E500_DOUBLE)
5834 {
5835 if (!REG_P (operands[1]))
5836 operands[1] = force_reg (SImode, operands[1]);
5837 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5838 DONE;
5839 }
5840 else if (TARGET_LFIWZX && TARGET_FCFID)
5841 {
5842 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5843 DONE;
5844 }
5845 else if (TARGET_FCFID)
5846 {
5847 rtx dreg = operands[1];
5848 if (!REG_P (dreg))
5849 dreg = force_reg (SImode, dreg);
5850 dreg = convert_to_mode (DImode, dreg, true);
5851 emit_insn (gen_floatdidf2 (operands[0], dreg));
5852 DONE;
5853 }
5855 if (!REG_P (operands[1]))
5856 operands[1] = force_reg (SImode, operands[1]);
5857 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5858 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5859 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5860 operands[5] = gen_reg_rtx (DFmode);
5861 }")
5863 (define_insn_and_split "*floatunssidf2_internal"
5864 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5865 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5866 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5867 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5868 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5869 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5870 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5871 && !(TARGET_FCFID && TARGET_POWERPC64)"
5872 "#"
5873 ""
5874 [(pc)]
5875 "
5876 {
5877 rtx lowword, highword;
5878 gcc_assert (MEM_P (operands[4]));
5879 highword = adjust_address (operands[4], SImode, 0);
5880 lowword = adjust_address (operands[4], SImode, 4);
5881 if (! WORDS_BIG_ENDIAN)
5882 {
5883 rtx tmp;
5884 tmp = highword; highword = lowword; lowword = tmp;
5885 }
5887 emit_move_insn (lowword, operands[1]);
5888 emit_move_insn (highword, operands[2]);
5889 emit_move_insn (operands[5], operands[4]);
5890 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5891 DONE;
5892 }"
5893 [(set_attr "length" "20")
5894 (set_attr "type" "fp")])
5896 (define_expand "fix_trunc<mode>si2"
5897 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5898 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5899 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5900 "
5901 {
5902 if (!<E500_CONVERT>)
5903 {
5904 rtx tmp, stack;
5906 if (TARGET_STFIWX)
5907 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5908 else
5909 {
5910 tmp = gen_reg_rtx (DImode);
5911 stack = rs6000_allocate_stack_temp (DImode, true, false);
5912 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5913 tmp, stack));
5914 }
5915 DONE;
5916 }
5917 }")
5919 ; Like the convert to float patterns, this insn must be split before
5920 ; register allocation so that it can allocate the memory slot if it
5921 ; needed
5922 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5923 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5924 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5925 (clobber (match_scratch:DI 2 "=d"))]
5926 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5927 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5928 && TARGET_STFIWX && can_create_pseudo_p ()"
5929 "#"
5930 ""
5931 [(pc)]
5932 {
5933 rtx dest = operands[0];
5934 rtx src = operands[1];
5935 rtx tmp = operands[2];
5937 if (GET_CODE (tmp) == SCRATCH)
5938 tmp = gen_reg_rtx (DImode);
5940 emit_insn (gen_fctiwz_<mode> (tmp, src));
5941 if (MEM_P (dest))
5942 {
5943 dest = rs6000_address_for_fpconvert (dest);
5944 emit_insn (gen_stfiwx (dest, tmp));
5945 DONE;
5946 }
5947 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5948 {
5949 dest = gen_lowpart (DImode, dest);
5950 emit_move_insn (dest, tmp);
5951 DONE;
5952 }
5953 else
5954 {
5955 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5956 emit_insn (gen_stfiwx (stack, tmp));
5957 emit_move_insn (dest, stack);
5958 DONE;
5959 }
5960 }
5961 [(set_attr "length" "12")
5962 (set_attr "type" "fp")])
5964 (define_insn_and_split "fix_trunc<mode>si2_internal"
5965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5966 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5967 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5968 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5970 "#"
5971 ""
5972 [(pc)]
5973 "
5974 {
5975 rtx lowword;
5976 gcc_assert (MEM_P (operands[3]));
5977 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5979 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5980 emit_move_insn (operands[3], operands[2]);
5981 emit_move_insn (operands[0], lowword);
5982 DONE;
5983 }"
5984 [(set_attr "length" "16")
5985 (set_attr "type" "fp")])
5987 (define_expand "fix_trunc<mode>di2"
5988 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5989 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5990 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5991 && TARGET_FCFID"
5992 "")
5994 (define_insn "*fix_trunc<mode>di2_fctidz"
5995 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5996 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5997 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5998 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5999 "fctidz %0,%1"
6000 [(set_attr "type" "fp")])
6002 (define_expand "fixuns_trunc<mode>si2"
6003 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6004 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6005 "TARGET_HARD_FLOAT
6006 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6007 || <E500_CONVERT>)"
6008 "
6009 {
6010 if (!<E500_CONVERT>)
6011 {
6012 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6013 DONE;
6014 }
6015 }")
6017 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6018 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6019 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6020 (clobber (match_scratch:DI 2 "=d"))]
6021 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6022 && TARGET_STFIWX && can_create_pseudo_p ()"
6023 "#"
6024 ""
6025 [(pc)]
6026 {
6027 rtx dest = operands[0];
6028 rtx src = operands[1];
6029 rtx tmp = operands[2];
6031 if (GET_CODE (tmp) == SCRATCH)
6032 tmp = gen_reg_rtx (DImode);
6034 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6035 if (MEM_P (dest))
6036 {
6037 dest = rs6000_address_for_fpconvert (dest);
6038 emit_insn (gen_stfiwx (dest, tmp));
6039 DONE;
6040 }
6041 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6042 {
6043 dest = gen_lowpart (DImode, dest);
6044 emit_move_insn (dest, tmp);
6045 DONE;
6046 }
6047 else
6048 {
6049 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6050 emit_insn (gen_stfiwx (stack, tmp));
6051 emit_move_insn (dest, stack);
6052 DONE;
6053 }
6054 }
6055 [(set_attr "length" "12")
6056 (set_attr "type" "fp")])
6058 (define_expand "fixuns_trunc<mode>di2"
6059 [(set (match_operand:DI 0 "register_operand" "")
6060 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6061 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6062 "")
6064 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6066 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6067 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6068 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6069 "fctiduz %0,%1"
6070 [(set_attr "type" "fp")])
6072 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6073 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6074 ; because the first makes it clear that operand 0 is not live
6075 ; before the instruction.
6076 (define_insn "fctiwz_<mode>"
6077 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6078 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6079 UNSPEC_FCTIWZ))]
6080 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6081 "fctiwz %0,%1"
6082 [(set_attr "type" "fp")])
6084 (define_insn "fctiwuz_<mode>"
6085 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6086 (unspec:DI [(unsigned_fix:SI
6087 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6088 UNSPEC_FCTIWUZ))]
6089 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6090 "fctiwuz %0,%1"
6091 [(set_attr "type" "fp")])
6093 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6094 ;; since the friz instruction does not truncate the value if the floating
6095 ;; point value is < LONG_MIN or > LONG_MAX.
6096 (define_insn "*friz"
6097 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6098 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6099 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6100 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6101 && !flag_trapping_math && TARGET_FRIZ"
6102 "friz %0,%1"
6103 [(set_attr "type" "fp")])
6105 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6106 ;; load to properly sign extend the value, but at least doing a store, load
6107 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6108 ;; if we have 32-bit memory ops
6109 (define_insn_and_split "*round32<mode>2_fprs"
6110 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6111 (float:SFDF
6112 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6113 (clobber (match_scratch:DI 2 "=d"))
6114 (clobber (match_scratch:DI 3 "=d"))]
6115 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6116 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6117 && can_create_pseudo_p ()"
6118 "#"
6119 ""
6120 [(pc)]
6121 {
6122 rtx dest = operands[0];
6123 rtx src = operands[1];
6124 rtx tmp1 = operands[2];
6125 rtx tmp2 = operands[3];
6126 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6128 if (GET_CODE (tmp1) == SCRATCH)
6129 tmp1 = gen_reg_rtx (DImode);
6130 if (GET_CODE (tmp2) == SCRATCH)
6131 tmp2 = gen_reg_rtx (DImode);
6133 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6134 emit_insn (gen_stfiwx (stack, tmp1));
6135 emit_insn (gen_lfiwax (tmp2, stack));
6136 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6137 DONE;
6138 }
6139 [(set_attr "type" "fpload")
6140 (set_attr "length" "16")])
6142 (define_insn_and_split "*roundu32<mode>2_fprs"
6143 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6144 (unsigned_float:SFDF
6145 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6146 (clobber (match_scratch:DI 2 "=d"))
6147 (clobber (match_scratch:DI 3 "=d"))]
6148 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6149 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6150 && can_create_pseudo_p ()"
6151 "#"
6152 ""
6153 [(pc)]
6154 {
6155 rtx dest = operands[0];
6156 rtx src = operands[1];
6157 rtx tmp1 = operands[2];
6158 rtx tmp2 = operands[3];
6159 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6161 if (GET_CODE (tmp1) == SCRATCH)
6162 tmp1 = gen_reg_rtx (DImode);
6163 if (GET_CODE (tmp2) == SCRATCH)
6164 tmp2 = gen_reg_rtx (DImode);
6166 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6167 emit_insn (gen_stfiwx (stack, tmp1));
6168 emit_insn (gen_lfiwzx (tmp2, stack));
6169 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6170 DONE;
6171 }
6172 [(set_attr "type" "fpload")
6173 (set_attr "length" "16")])
6175 ;; No VSX equivalent to fctid
6176 (define_insn "lrint<mode>di2"
6177 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6178 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6179 UNSPEC_FCTID))]
6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6181 "fctid %0,%1"
6182 [(set_attr "type" "fp")])
6184 (define_expand "btrunc<mode>2"
6185 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6186 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6187 UNSPEC_FRIZ))]
6188 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6189 "")
6191 (define_insn "*btrunc<mode>2_fpr"
6192 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6193 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6194 UNSPEC_FRIZ))]
6195 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6196 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6197 "friz %0,%1"
6198 [(set_attr "type" "fp")])
6200 (define_expand "ceil<mode>2"
6201 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6202 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6203 UNSPEC_FRIP))]
6204 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6205 "")
6207 (define_insn "*ceil<mode>2_fpr"
6208 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6209 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6210 UNSPEC_FRIP))]
6211 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6212 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6213 "frip %0,%1"
6214 [(set_attr "type" "fp")])
6216 (define_expand "floor<mode>2"
6217 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6218 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6219 UNSPEC_FRIM))]
6220 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6221 "")
6223 (define_insn "*floor<mode>2_fpr"
6224 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6225 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6226 UNSPEC_FRIM))]
6227 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6228 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6229 "frim %0,%1"
6230 [(set_attr "type" "fp")])
6232 ;; No VSX equivalent to frin
6233 (define_insn "round<mode>2"
6234 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6235 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6236 UNSPEC_FRIN))]
6237 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6238 "frin %0,%1"
6239 [(set_attr "type" "fp")])
6241 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6242 (define_insn "stfiwx"
6243 [(set (match_operand:SI 0 "memory_operand" "=Z")
6244 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6245 UNSPEC_STFIWX))]
6246 "TARGET_PPC_GFXOPT"
6247 "stfiwx %1,%y0"
6248 [(set_attr "type" "fpstore")])
6250 ;; If we don't have a direct conversion to single precision, don't enable this
6251 ;; conversion for 32-bit without fast math, because we don't have the insn to
6252 ;; generate the fixup swizzle to avoid double rounding problems.
6253 (define_expand "floatsisf2"
6254 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6255 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6256 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6257 && (!TARGET_FPRS
6258 || (TARGET_FPRS
6259 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6260 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6261 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6262 "
6263 {
6264 if (!TARGET_FPRS)
6265 {
6266 if (!REG_P (operands[1]))
6267 operands[1] = force_reg (SImode, operands[1]);
6268 }
6269 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6270 {
6271 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6272 DONE;
6273 }
6274 else if (TARGET_FCFID && TARGET_LFIWAX)
6275 {
6276 rtx dfreg = gen_reg_rtx (DFmode);
6277 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6278 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6279 DONE;
6280 }
6281 else
6282 {
6283 rtx dreg = operands[1];
6284 if (!REG_P (dreg))
6285 dreg = force_reg (SImode, dreg);
6286 dreg = convert_to_mode (DImode, dreg, false);
6287 emit_insn (gen_floatdisf2 (operands[0], dreg));
6288 DONE;
6289 }
6290 }")
6292 (define_expand "floatdidf2"
6293 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6294 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6295 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6296 "")
6298 (define_insn "*floatdidf2_fpr"
6299 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6300 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6301 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6302 && !VECTOR_UNIT_VSX_P (DFmode)"
6303 "fcfid %0,%1"
6304 [(set_attr "type" "fp")])
6306 ; Allow the combiner to merge source memory operands to the conversion so that
6307 ; the optimizer/register allocator doesn't try to load the value too early in a
6308 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6309 ; hit. We will split after reload to avoid the trip through the GPRs
6311 (define_insn_and_split "*floatdidf2_mem"
6312 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6313 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6314 (clobber (match_scratch:DI 2 "=d"))]
6315 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6316 "#"
6317 "&& reload_completed"
6318 [(set (match_dup 2) (match_dup 1))
6319 (set (match_dup 0) (float:DF (match_dup 2)))]
6320 ""
6321 [(set_attr "length" "8")
6322 (set_attr "type" "fpload")])
6324 (define_expand "floatunsdidf2"
6325 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6326 (unsigned_float:DF
6327 (match_operand:DI 1 "gpc_reg_operand" "")))]
6328 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6329 "")
6331 (define_insn "*floatunsdidf2_fcfidu"
6332 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6333 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6334 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6335 "fcfidu %0,%1"
6336 [(set_attr "type" "fp")
6337 (set_attr "length" "4")])
6339 (define_insn_and_split "*floatunsdidf2_mem"
6340 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6341 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6342 (clobber (match_scratch:DI 2 "=d"))]
6343 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6344 "#"
6345 "&& reload_completed"
6346 [(set (match_dup 2) (match_dup 1))
6347 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6348 ""
6349 [(set_attr "length" "8")
6350 (set_attr "type" "fpload")])
6352 (define_expand "floatdisf2"
6353 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6354 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6355 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6356 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6357 "
6358 {
6359 if (!TARGET_FCFIDS)
6360 {
6361 rtx val = operands[1];
6362 if (!flag_unsafe_math_optimizations)
6363 {
6364 rtx label = gen_label_rtx ();
6365 val = gen_reg_rtx (DImode);
6366 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6367 emit_label (label);
6368 }
6369 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6370 DONE;
6371 }
6372 }")
6374 (define_insn "floatdisf2_fcfids"
6375 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6376 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6377 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6378 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6379 "fcfids %0,%1"
6380 [(set_attr "type" "fp")])
6382 (define_insn_and_split "*floatdisf2_mem"
6383 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6384 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6385 (clobber (match_scratch:DI 2 "=f"))]
6386 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6387 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6388 "#"
6389 "&& reload_completed"
6390 [(pc)]
6391 "
6392 {
6393 emit_move_insn (operands[2], operands[1]);
6394 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6395 DONE;
6396 }"
6397 [(set_attr "length" "8")])
6399 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6400 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6401 ;; from double rounding.
6402 ;; Instead of creating a new cpu type for two FP operations, just use fp
6403 (define_insn_and_split "floatdisf2_internal1"
6404 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6405 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6406 (clobber (match_scratch:DF 2 "=d"))]
6407 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6408 "#"
6409 "&& reload_completed"
6410 [(set (match_dup 2)
6411 (float:DF (match_dup 1)))
6412 (set (match_dup 0)
6413 (float_truncate:SF (match_dup 2)))]
6414 ""
6415 [(set_attr "length" "8")
6416 (set_attr "type" "fp")])
6418 ;; Twiddles bits to avoid double rounding.
6419 ;; Bits that might be truncated when converting to DFmode are replaced
6420 ;; by a bit that won't be lost at that stage, but is below the SFmode
6421 ;; rounding position.
6422 (define_expand "floatdisf2_internal2"
6423 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6424 (const_int 53)))
6425 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6426 (const_int 2047)))
6427 (clobber (scratch:CC))])
6428 (set (match_dup 3) (plus:DI (match_dup 3)
6429 (const_int 1)))
6430 (set (match_dup 0) (plus:DI (match_dup 0)
6431 (const_int 2047)))
6432 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6433 (const_int 2)))
6434 (set (match_dup 0) (ior:DI (match_dup 0)
6435 (match_dup 1)))
6436 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6437 (const_int -2048)))
6438 (clobber (scratch:CC))])
6439 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6440 (label_ref (match_operand:DI 2 "" ""))
6441 (pc)))
6442 (set (match_dup 0) (match_dup 1))]
6443 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6444 "
6445 {
6446 operands[3] = gen_reg_rtx (DImode);
6447 operands[4] = gen_reg_rtx (CCUNSmode);
6448 }")
6450 (define_expand "floatunsdisf2"
6451 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6452 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6453 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6454 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6455 "")
6457 (define_insn "floatunsdisf2_fcfidus"
6458 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6459 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6460 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6461 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6462 "fcfidus %0,%1"
6463 [(set_attr "type" "fp")])
6465 (define_insn_and_split "*floatunsdisf2_mem"
6466 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6467 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6468 (clobber (match_scratch:DI 2 "=f"))]
6469 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6470 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6471 "#"
6472 "&& reload_completed"
6473 [(pc)]
6474 "
6475 {
6476 emit_move_insn (operands[2], operands[1]);
6477 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6478 DONE;
6479 }"
6480 [(set_attr "length" "8")
6481 (set_attr "type" "fpload")])
6482 \f
6483 ;; Define the DImode operations that can be done in a small number
6484 ;; of instructions. The & constraints are to prevent the register
6485 ;; allocator from allocating registers that overlap with the inputs
6486 ;; (for example, having an input in 7,8 and an output in 6,7). We
6487 ;; also allow for the output being the same as one of the inputs.
6489 (define_insn "*adddi3_noppc64"
6490 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6491 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6492 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6493 "! TARGET_POWERPC64"
6494 "*
6495 {
6496 if (WORDS_BIG_ENDIAN)
6497 return (GET_CODE (operands[2])) != CONST_INT
6498 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6499 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6500 else
6501 return (GET_CODE (operands[2])) != CONST_INT
6502 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6503 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6504 }"
6505 [(set_attr "type" "two")
6506 (set_attr "length" "8")])
6508 (define_insn "*subdi3_noppc64"
6509 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6510 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6511 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6512 "! TARGET_POWERPC64"
6513 "*
6514 {
6515 if (WORDS_BIG_ENDIAN)
6516 return (GET_CODE (operands[1]) != CONST_INT)
6517 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6518 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6519 else
6520 return (GET_CODE (operands[1]) != CONST_INT)
6521 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6522 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6523 }"
6524 [(set_attr "type" "two")
6525 (set_attr "length" "8")])
6527 (define_insn "*negdi2_noppc64"
6528 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6529 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6530 "! TARGET_POWERPC64"
6531 "*
6532 {
6533 return (WORDS_BIG_ENDIAN)
6534 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6535 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6536 }"
6537 [(set_attr "type" "two")
6538 (set_attr "length" "8")])
6540 (define_insn "mulsidi3"
6541 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6542 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6543 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6544 "! TARGET_POWERPC64"
6545 {
6546 return (WORDS_BIG_ENDIAN)
6547 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6548 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6549 }
6550 [(set_attr "type" "imul")
6551 (set_attr "length" "8")])
6553 (define_split
6554 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6555 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6556 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6557 "! TARGET_POWERPC64 && reload_completed"
6558 [(set (match_dup 3)
6559 (truncate:SI
6560 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6561 (sign_extend:DI (match_dup 2)))
6562 (const_int 32))))
6563 (set (match_dup 4)
6564 (mult:SI (match_dup 1)
6565 (match_dup 2)))]
6566 "
6567 {
6568 int endian = (WORDS_BIG_ENDIAN == 0);
6569 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6570 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6571 }")
6573 (define_insn "umulsidi3"
6574 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6575 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6576 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6577 "! TARGET_POWERPC64"
6578 "*
6579 {
6580 return (WORDS_BIG_ENDIAN)
6581 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6582 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6583 }"
6584 [(set_attr "type" "imul")
6585 (set_attr "length" "8")])
6587 (define_split
6588 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6589 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6590 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6591 "! TARGET_POWERPC64 && reload_completed"
6592 [(set (match_dup 3)
6593 (truncate:SI
6594 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6595 (zero_extend:DI (match_dup 2)))
6596 (const_int 32))))
6597 (set (match_dup 4)
6598 (mult:SI (match_dup 1)
6599 (match_dup 2)))]
6600 "
6601 {
6602 int endian = (WORDS_BIG_ENDIAN == 0);
6603 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6604 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6605 }")
6607 (define_insn "smulsi3_highpart"
6608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6609 (truncate:SI
6610 (lshiftrt:DI (mult:DI (sign_extend:DI
6611 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6612 (sign_extend:DI
6613 (match_operand:SI 2 "gpc_reg_operand" "r")))
6614 (const_int 32))))]
6615 ""
6616 "mulhw %0,%1,%2"
6617 [(set_attr "type" "imul")])
6619 (define_insn "umulsi3_highpart"
6620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6621 (truncate:SI
6622 (lshiftrt:DI (mult:DI (zero_extend:DI
6623 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6624 (zero_extend:DI
6625 (match_operand:SI 2 "gpc_reg_operand" "r")))
6626 (const_int 32))))]
6627 ""
6628 "mulhwu %0,%1,%2"
6629 [(set_attr "type" "imul")])
6631 ;; Shift by a variable amount is too complex to be worth open-coding. We
6632 ;; just handle shifts by constants.
6633 (define_insn "ashrdi3_no_power"
6634 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6635 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6636 (match_operand:SI 2 "const_int_operand" "M,i")))]
6637 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6638 "@
6639 srawi %0,%1,31\;srawi %L0,%1,%h2
6640 srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2"
6641 [(set_attr "type" "two,three")
6642 (set_attr "length" "8,12")])
6644 (define_insn "*ashrdisi3_noppc64be"
6645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6646 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6647 (const_int 32)) 4))]
6648 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6649 "*
6650 {
6651 if (REGNO (operands[0]) == REGNO (operands[1]))
6652 return \"\";
6653 else
6654 return \"mr %0,%1\";
6655 }"
6656 [(set_attr "length" "4")])
6658 \f
6659 ;; PowerPC64 DImode operations.
6661 (define_insn "muldi3"
6662 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6663 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6664 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6665 "TARGET_POWERPC64"
6666 "@
6667 mulld %0,%1,%2
6668 mulli %0,%1,%2"
6669 [(set (attr "type")
6670 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6671 (const_string "imul3")
6672 (match_operand:SI 2 "short_cint_operand" "")
6673 (const_string "imul2")]
6674 (const_string "lmul")))])
6676 (define_insn "*muldi3_internal1"
6677 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6678 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6679 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6680 (const_int 0)))
6681 (clobber (match_scratch:DI 3 "=r,r"))]
6682 "TARGET_POWERPC64"
6683 "@
6684 mulld. %3,%1,%2
6685 #"
6686 [(set_attr "type" "lmul_compare")
6687 (set_attr "length" "4,8")])
6689 (define_split
6690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6691 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6692 (match_operand:DI 2 "gpc_reg_operand" ""))
6693 (const_int 0)))
6694 (clobber (match_scratch:DI 3 ""))]
6695 "TARGET_POWERPC64 && reload_completed"
6696 [(set (match_dup 3)
6697 (mult:DI (match_dup 1) (match_dup 2)))
6698 (set (match_dup 0)
6699 (compare:CC (match_dup 3)
6700 (const_int 0)))]
6701 "")
6703 (define_insn "*muldi3_internal2"
6704 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6705 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6706 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6707 (const_int 0)))
6708 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6709 (mult:DI (match_dup 1) (match_dup 2)))]
6710 "TARGET_POWERPC64"
6711 "@
6712 mulld. %0,%1,%2
6713 #"
6714 [(set_attr "type" "lmul_compare")
6715 (set_attr "length" "4,8")])
6717 (define_split
6718 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6719 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6720 (match_operand:DI 2 "gpc_reg_operand" ""))
6721 (const_int 0)))
6722 (set (match_operand:DI 0 "gpc_reg_operand" "")
6723 (mult:DI (match_dup 1) (match_dup 2)))]
6724 "TARGET_POWERPC64 && reload_completed"
6725 [(set (match_dup 0)
6726 (mult:DI (match_dup 1) (match_dup 2)))
6727 (set (match_dup 3)
6728 (compare:CC (match_dup 0)
6729 (const_int 0)))]
6730 "")
6732 (define_insn "smuldi3_highpart"
6733 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6734 (truncate:DI
6735 (lshiftrt:TI (mult:TI (sign_extend:TI
6736 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6737 (sign_extend:TI
6738 (match_operand:DI 2 "gpc_reg_operand" "r")))
6739 (const_int 64))))]
6740 "TARGET_POWERPC64"
6741 "mulhd %0,%1,%2"
6742 [(set_attr "type" "lmul")])
6744 (define_insn "umuldi3_highpart"
6745 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6746 (truncate:DI
6747 (lshiftrt:TI (mult:TI (zero_extend:TI
6748 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6749 (zero_extend:TI
6750 (match_operand:DI 2 "gpc_reg_operand" "r")))
6751 (const_int 64))))]
6752 "TARGET_POWERPC64"
6753 "mulhdu %0,%1,%2"
6754 [(set_attr "type" "lmul")])
6756 (define_expand "mulditi3"
6757 [(set (match_operand:TI 0 "gpc_reg_operand")
6758 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6759 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6760 "TARGET_POWERPC64"
6761 {
6762 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6763 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6764 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6765 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6766 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6767 DONE;
6768 })
6770 (define_expand "umulditi3"
6771 [(set (match_operand:TI 0 "gpc_reg_operand")
6772 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6773 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6774 "TARGET_POWERPC64"
6775 {
6776 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6777 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6778 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6779 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6780 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6781 DONE;
6782 })
6784 (define_insn "rotldi3"
6785 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6786 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6787 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6788 "TARGET_POWERPC64"
6789 "@
6790 rldcl %0,%1,%2,0
6791 rldicl %0,%1,%H2,0"
6792 [(set_attr "type" "var_shift_rotate,integer")])
6794 (define_insn "*rotldi3_internal2"
6795 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6796 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6797 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6798 (const_int 0)))
6799 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6800 "TARGET_64BIT"
6801 "@
6802 rldcl. %3,%1,%2,0
6803 rldicl. %3,%1,%H2,0
6804 #
6805 #"
6806 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6807 (set_attr "length" "4,4,8,8")])
6809 (define_split
6810 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6811 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6812 (match_operand:DI 2 "reg_or_cint_operand" ""))
6813 (const_int 0)))
6814 (clobber (match_scratch:DI 3 ""))]
6815 "TARGET_POWERPC64 && reload_completed"
6816 [(set (match_dup 3)
6817 (rotate:DI (match_dup 1) (match_dup 2)))
6818 (set (match_dup 0)
6819 (compare:CC (match_dup 3)
6820 (const_int 0)))]
6821 "")
6823 (define_insn "*rotldi3_internal3"
6824 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6825 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6826 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6827 (const_int 0)))
6828 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6829 (rotate:DI (match_dup 1) (match_dup 2)))]
6830 "TARGET_64BIT"
6831 "@
6832 rldcl. %0,%1,%2,0
6833 rldicl. %0,%1,%H2,0
6834 #
6835 #"
6836 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6837 (set_attr "length" "4,4,8,8")])
6839 (define_split
6840 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6841 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6842 (match_operand:DI 2 "reg_or_cint_operand" ""))
6843 (const_int 0)))
6844 (set (match_operand:DI 0 "gpc_reg_operand" "")
6845 (rotate:DI (match_dup 1) (match_dup 2)))]
6846 "TARGET_POWERPC64 && reload_completed"
6847 [(set (match_dup 0)
6848 (rotate:DI (match_dup 1) (match_dup 2)))
6849 (set (match_dup 3)
6850 (compare:CC (match_dup 0)
6851 (const_int 0)))]
6852 "")
6854 (define_insn "*rotldi3_internal4"
6855 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6856 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6857 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6858 (match_operand:DI 3 "mask64_operand" "n,n")))]
6859 "TARGET_POWERPC64"
6860 "@
6861 rldc%B3 %0,%1,%2,%S3
6862 rldic%B3 %0,%1,%H2,%S3"
6863 [(set_attr "type" "var_shift_rotate,integer")])
6865 (define_insn "*rotldi3_internal5"
6866 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6867 (compare:CC (and:DI
6868 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6869 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6870 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6871 (const_int 0)))
6872 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6873 "TARGET_64BIT"
6874 "@
6875 rldc%B3. %4,%1,%2,%S3
6876 rldic%B3. %4,%1,%H2,%S3
6877 #
6878 #"
6879 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6880 (set_attr "length" "4,4,8,8")])
6882 (define_split
6883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6884 (compare:CC (and:DI
6885 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6886 (match_operand:DI 2 "reg_or_cint_operand" ""))
6887 (match_operand:DI 3 "mask64_operand" ""))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 4 ""))]
6890 "TARGET_POWERPC64 && reload_completed"
6891 [(set (match_dup 4)
6892 (and:DI (rotate:DI (match_dup 1)
6893 (match_dup 2))
6894 (match_dup 3)))
6895 (set (match_dup 0)
6896 (compare:CC (match_dup 4)
6897 (const_int 0)))]
6898 "")
6900 (define_insn "*rotldi3_internal6"
6901 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6902 (compare:CC (and:DI
6903 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6904 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6905 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6906 (const_int 0)))
6907 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6908 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6909 "TARGET_64BIT"
6910 "@
6911 rldc%B3. %0,%1,%2,%S3
6912 rldic%B3. %0,%1,%H2,%S3
6913 #
6914 #"
6915 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6916 (set_attr "length" "4,4,8,8")])
6918 (define_split
6919 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6920 (compare:CC (and:DI
6921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6922 (match_operand:DI 2 "reg_or_cint_operand" ""))
6923 (match_operand:DI 3 "mask64_operand" ""))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "")
6926 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6927 "TARGET_POWERPC64 && reload_completed"
6928 [(set (match_dup 0)
6929 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6930 (set (match_dup 4)
6931 (compare:CC (match_dup 0)
6932 (const_int 0)))]
6933 "")
6935 (define_insn "*rotldi3_internal7le"
6936 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6937 (zero_extend:DI
6938 (subreg:QI
6939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6940 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6941 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6942 "@
6943 rldcl %0,%1,%2,56
6944 rldicl %0,%1,%H2,56"
6945 [(set_attr "type" "var_shift_rotate,integer")])
6947 (define_insn "*rotldi3_internal7be"
6948 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6949 (zero_extend:DI
6950 (subreg:QI
6951 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6952 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
6953 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6954 "@
6955 rldcl %0,%1,%2,56
6956 rldicl %0,%1,%H2,56"
6957 [(set_attr "type" "var_shift_rotate,integer")])
6959 (define_insn "*rotldi3_internal8le"
6960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6961 (compare:CC (zero_extend:DI
6962 (subreg:QI
6963 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6964 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6965 (const_int 0)))
6966 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6967 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6968 "@
6969 rldcl. %3,%1,%2,56
6970 rldicl. %3,%1,%H2,56
6971 #
6972 #"
6973 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6974 (set_attr "length" "4,4,8,8")])
6976 (define_insn "*rotldi3_internal8be"
6977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6978 (compare:CC (zero_extend:DI
6979 (subreg:QI
6980 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6981 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
6982 (const_int 0)))
6983 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6984 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6985 "@
6986 rldcl. %3,%1,%2,56
6987 rldicl. %3,%1,%H2,56
6988 #
6989 #"
6990 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6991 (set_attr "length" "4,4,8,8")])
6993 (define_split
6994 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6995 (compare:CC (zero_extend:DI
6996 (subreg:QI
6997 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6998 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6999 (const_int 0)))
7000 (clobber (match_scratch:DI 3 ""))]
7001 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7002 [(set (match_dup 3)
7003 (zero_extend:DI (subreg:QI
7004 (rotate:DI (match_dup 1)
7005 (match_dup 2)) 0)))
7006 (set (match_dup 0)
7007 (compare:CC (match_dup 3)
7008 (const_int 0)))]
7009 "")
7011 (define_split
7012 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7013 (compare:CC (zero_extend:DI
7014 (subreg:QI
7015 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7016 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7017 (const_int 0)))
7018 (clobber (match_scratch:DI 3 ""))]
7019 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7020 [(set (match_dup 3)
7021 (zero_extend:DI (subreg:QI
7022 (rotate:DI (match_dup 1)
7023 (match_dup 2)) 7)))
7024 (set (match_dup 0)
7025 (compare:CC (match_dup 3)
7026 (const_int 0)))]
7027 "")
7029 (define_insn "*rotldi3_internal9le"
7030 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7031 (compare:CC (zero_extend:DI
7032 (subreg:QI
7033 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7034 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7035 (const_int 0)))
7036 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7037 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7038 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7039 "@
7040 rldcl. %0,%1,%2,56
7041 rldicl. %0,%1,%H2,56
7042 #
7043 #"
7044 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7045 (set_attr "length" "4,4,8,8")])
7047 (define_insn "*rotldi3_internal9be"
7048 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7049 (compare:CC (zero_extend:DI
7050 (subreg:QI
7051 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7052 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7053 (const_int 0)))
7054 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7055 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7056 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7057 "@
7058 rldcl. %0,%1,%2,56
7059 rldicl. %0,%1,%H2,56
7060 #
7061 #"
7062 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7063 (set_attr "length" "4,4,8,8")])
7065 (define_split
7066 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7067 (compare:CC (zero_extend:DI
7068 (subreg:QI
7069 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7070 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7071 (const_int 0)))
7072 (set (match_operand:DI 0 "gpc_reg_operand" "")
7073 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7074 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7075 [(set (match_dup 0)
7076 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7077 (set (match_dup 3)
7078 (compare:CC (match_dup 0)
7079 (const_int 0)))]
7080 "")
7082 (define_split
7083 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7084 (compare:CC (zero_extend:DI
7085 (subreg:QI
7086 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7087 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7088 (const_int 0)))
7089 (set (match_operand:DI 0 "gpc_reg_operand" "")
7090 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7091 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7092 [(set (match_dup 0)
7093 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7094 (set (match_dup 3)
7095 (compare:CC (match_dup 0)
7096 (const_int 0)))]
7097 "")
7099 (define_insn "*rotldi3_internal10le"
7100 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7101 (zero_extend:DI
7102 (subreg:HI
7103 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7104 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7105 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7106 "@
7107 rldcl %0,%1,%2,48
7108 rldicl %0,%1,%H2,48"
7109 [(set_attr "type" "var_shift_rotate,integer")])
7111 (define_insn "*rotldi3_internal10be"
7112 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7113 (zero_extend:DI
7114 (subreg:HI
7115 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7116 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7117 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7118 "@
7119 rldcl %0,%1,%2,48
7120 rldicl %0,%1,%H2,48"
7121 [(set_attr "type" "var_shift_rotate,integer")])
7123 (define_insn "*rotldi3_internal11le"
7124 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7125 (compare:CC (zero_extend:DI
7126 (subreg:HI
7127 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7128 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7129 (const_int 0)))
7130 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7131 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7132 "@
7133 rldcl. %3,%1,%2,48
7134 rldicl. %3,%1,%H2,48
7135 #
7136 #"
7137 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7138 (set_attr "length" "4,4,8,8")])
7140 (define_insn "*rotldi3_internal11be"
7141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7142 (compare:CC (zero_extend:DI
7143 (subreg:HI
7144 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7145 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7146 (const_int 0)))
7147 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7148 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7149 "@
7150 rldcl. %3,%1,%2,48
7151 rldicl. %3,%1,%H2,48
7152 #
7153 #"
7154 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7155 (set_attr "length" "4,4,8,8")])
7157 (define_split
7158 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7159 (compare:CC (zero_extend:DI
7160 (subreg:HI
7161 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7162 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7163 (const_int 0)))
7164 (clobber (match_scratch:DI 3 ""))]
7165 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7166 [(set (match_dup 3)
7167 (zero_extend:DI (subreg:HI
7168 (rotate:DI (match_dup 1)
7169 (match_dup 2)) 0)))
7170 (set (match_dup 0)
7171 (compare:CC (match_dup 3)
7172 (const_int 0)))]
7173 "")
7175 (define_split
7176 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7177 (compare:CC (zero_extend:DI
7178 (subreg:HI
7179 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7180 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7181 (const_int 0)))
7182 (clobber (match_scratch:DI 3 ""))]
7183 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7184 [(set (match_dup 3)
7185 (zero_extend:DI (subreg:HI
7186 (rotate:DI (match_dup 1)
7187 (match_dup 2)) 6)))
7188 (set (match_dup 0)
7189 (compare:CC (match_dup 3)
7190 (const_int 0)))]
7191 "")
7193 (define_insn "*rotldi3_internal12le"
7194 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7195 (compare:CC (zero_extend:DI
7196 (subreg:HI
7197 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7198 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7199 (const_int 0)))
7200 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7201 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7202 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7203 "@
7204 rldcl. %0,%1,%2,48
7205 rldicl. %0,%1,%H2,48
7206 #
7207 #"
7208 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7209 (set_attr "length" "4,4,8,8")])
7211 (define_insn "*rotldi3_internal12be"
7212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7213 (compare:CC (zero_extend:DI
7214 (subreg:HI
7215 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7216 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7217 (const_int 0)))
7218 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7219 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7220 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7221 "@
7222 rldcl. %0,%1,%2,48
7223 rldicl. %0,%1,%H2,48
7224 #
7225 #"
7226 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7227 (set_attr "length" "4,4,8,8")])
7229 (define_split
7230 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7231 (compare:CC (zero_extend:DI
7232 (subreg:HI
7233 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7234 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7235 (const_int 0)))
7236 (set (match_operand:DI 0 "gpc_reg_operand" "")
7237 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7238 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7239 [(set (match_dup 0)
7240 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7241 (set (match_dup 3)
7242 (compare:CC (match_dup 0)
7243 (const_int 0)))]
7244 "")
7246 (define_split
7247 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7248 (compare:CC (zero_extend:DI
7249 (subreg:HI
7250 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7251 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7252 (const_int 0)))
7253 (set (match_operand:DI 0 "gpc_reg_operand" "")
7254 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7255 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7256 [(set (match_dup 0)
7257 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7258 (set (match_dup 3)
7259 (compare:CC (match_dup 0)
7260 (const_int 0)))]
7261 "")
7263 (define_insn "*rotldi3_internal13le"
7264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7265 (zero_extend:DI
7266 (subreg:SI
7267 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7268 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7269 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7270 "@
7271 rldcl %0,%1,%2,32
7272 rldicl %0,%1,%H2,32"
7273 [(set_attr "type" "var_shift_rotate,integer")])
7275 (define_insn "*rotldi3_internal13be"
7276 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7277 (zero_extend:DI
7278 (subreg:SI
7279 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7280 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7281 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7282 "@
7283 rldcl %0,%1,%2,32
7284 rldicl %0,%1,%H2,32"
7285 [(set_attr "type" "var_shift_rotate,integer")])
7287 (define_insn "*rotldi3_internal14le"
7288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7289 (compare:CC (zero_extend:DI
7290 (subreg:SI
7291 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7292 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7293 (const_int 0)))
7294 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7295 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7296 "@
7297 rldcl. %3,%1,%2,32
7298 rldicl. %3,%1,%H2,32
7299 #
7300 #"
7301 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7302 (set_attr "length" "4,4,8,8")])
7304 (define_insn "*rotldi3_internal14be"
7305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7306 (compare:CC (zero_extend:DI
7307 (subreg:SI
7308 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7309 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7310 (const_int 0)))
7311 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7312 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7313 "@
7314 rldcl. %3,%1,%2,32
7315 rldicl. %3,%1,%H2,32
7316 #
7317 #"
7318 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7319 (set_attr "length" "4,4,8,8")])
7321 (define_split
7322 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7323 (compare:CC (zero_extend:DI
7324 (subreg:SI
7325 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7326 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7327 (const_int 0)))
7328 (clobber (match_scratch:DI 3 ""))]
7329 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7330 [(set (match_dup 3)
7331 (zero_extend:DI (subreg:SI
7332 (rotate:DI (match_dup 1)
7333 (match_dup 2)) 0)))
7334 (set (match_dup 0)
7335 (compare:CC (match_dup 3)
7336 (const_int 0)))]
7337 "")
7339 (define_split
7340 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7341 (compare:CC (zero_extend:DI
7342 (subreg:SI
7343 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7344 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7345 (const_int 0)))
7346 (clobber (match_scratch:DI 3 ""))]
7347 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7348 [(set (match_dup 3)
7349 (zero_extend:DI (subreg:SI
7350 (rotate:DI (match_dup 1)
7351 (match_dup 2)) 4)))
7352 (set (match_dup 0)
7353 (compare:CC (match_dup 3)
7354 (const_int 0)))]
7355 "")
7357 (define_insn "*rotldi3_internal15le"
7358 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7359 (compare:CC (zero_extend:DI
7360 (subreg:SI
7361 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7362 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7363 (const_int 0)))
7364 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7365 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7366 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7367 "@
7368 rldcl. %0,%1,%2,32
7369 rldicl. %0,%1,%H2,32
7370 #
7371 #"
7372 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7373 (set_attr "length" "4,4,8,8")])
7375 (define_insn "*rotldi3_internal15be"
7376 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7377 (compare:CC (zero_extend:DI
7378 (subreg:SI
7379 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7380 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7381 (const_int 0)))
7382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7383 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7384 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7385 "@
7386 rldcl. %0,%1,%2,32
7387 rldicl. %0,%1,%H2,32
7388 #
7389 #"
7390 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7391 (set_attr "length" "4,4,8,8")])
7393 (define_split
7394 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7395 (compare:CC (zero_extend:DI
7396 (subreg:SI
7397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7398 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7399 (const_int 0)))
7400 (set (match_operand:DI 0 "gpc_reg_operand" "")
7401 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7402 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7403 [(set (match_dup 0)
7404 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7405 (set (match_dup 3)
7406 (compare:CC (match_dup 0)
7407 (const_int 0)))]
7408 "")
7410 (define_split
7411 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7412 (compare:CC (zero_extend:DI
7413 (subreg:SI
7414 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7415 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7416 (const_int 0)))
7417 (set (match_operand:DI 0 "gpc_reg_operand" "")
7418 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7419 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7420 [(set (match_dup 0)
7421 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7422 (set (match_dup 3)
7423 (compare:CC (match_dup 0)
7424 (const_int 0)))]
7425 "")
7427 (define_expand "ashldi3"
7428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7429 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7430 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7431 "TARGET_POWERPC64"
7432 "")
7434 (define_insn "*ashldi3_internal1"
7435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7436 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7437 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7438 "TARGET_POWERPC64"
7439 "@
7440 sld %0,%1,%2
7441 sldi %0,%1,%H2"
7442 [(set_attr "type" "var_shift_rotate,shift")])
7444 (define_insn "*ashldi3_internal2"
7445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7446 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7447 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7448 (const_int 0)))
7449 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7450 "TARGET_64BIT"
7451 "@
7452 sld. %3,%1,%2
7453 sldi. %3,%1,%H2
7454 #
7455 #"
7456 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7457 (set_attr "length" "4,4,8,8")])
7459 (define_split
7460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7461 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7462 (match_operand:SI 2 "reg_or_cint_operand" ""))
7463 (const_int 0)))
7464 (clobber (match_scratch:DI 3 ""))]
7465 "TARGET_POWERPC64 && reload_completed"
7466 [(set (match_dup 3)
7467 (ashift:DI (match_dup 1) (match_dup 2)))
7468 (set (match_dup 0)
7469 (compare:CC (match_dup 3)
7470 (const_int 0)))]
7471 "")
7473 (define_insn "*ashldi3_internal3"
7474 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7475 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7476 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7477 (const_int 0)))
7478 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7479 (ashift:DI (match_dup 1) (match_dup 2)))]
7480 "TARGET_64BIT"
7481 "@
7482 sld. %0,%1,%2
7483 sldi. %0,%1,%H2
7484 #
7485 #"
7486 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7487 (set_attr "length" "4,4,8,8")])
7489 (define_split
7490 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7491 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7492 (match_operand:SI 2 "reg_or_cint_operand" ""))
7493 (const_int 0)))
7494 (set (match_operand:DI 0 "gpc_reg_operand" "")
7495 (ashift:DI (match_dup 1) (match_dup 2)))]
7496 "TARGET_POWERPC64 && reload_completed"
7497 [(set (match_dup 0)
7498 (ashift:DI (match_dup 1) (match_dup 2)))
7499 (set (match_dup 3)
7500 (compare:CC (match_dup 0)
7501 (const_int 0)))]
7502 "")
7504 (define_insn "*ashldi3_internal4"
7505 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7506 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7507 (match_operand:SI 2 "const_int_operand" "i"))
7508 (match_operand:DI 3 "const_int_operand" "n")))]
7509 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7510 "rldic %0,%1,%H2,%W3")
7512 (define_insn "ashldi3_internal5"
7513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7514 (compare:CC
7515 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7516 (match_operand:SI 2 "const_int_operand" "i,i"))
7517 (match_operand:DI 3 "const_int_operand" "n,n"))
7518 (const_int 0)))
7519 (clobber (match_scratch:DI 4 "=r,r"))]
7520 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7521 "@
7522 rldic. %4,%1,%H2,%W3
7523 #"
7524 [(set_attr "type" "compare")
7525 (set_attr "length" "4,8")])
7527 (define_split
7528 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7529 (compare:CC
7530 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7531 (match_operand:SI 2 "const_int_operand" ""))
7532 (match_operand:DI 3 "const_int_operand" ""))
7533 (const_int 0)))
7534 (clobber (match_scratch:DI 4 ""))]
7535 "TARGET_POWERPC64 && reload_completed
7536 && includes_rldic_lshift_p (operands[2], operands[3])"
7537 [(set (match_dup 4)
7538 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7539 (match_dup 3)))
7540 (set (match_dup 0)
7541 (compare:CC (match_dup 4)
7542 (const_int 0)))]
7543 "")
7545 (define_insn "*ashldi3_internal6"
7546 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7547 (compare:CC
7548 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7549 (match_operand:SI 2 "const_int_operand" "i,i"))
7550 (match_operand:DI 3 "const_int_operand" "n,n"))
7551 (const_int 0)))
7552 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7553 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7554 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7555 "@
7556 rldic. %0,%1,%H2,%W3
7557 #"
7558 [(set_attr "type" "compare")
7559 (set_attr "length" "4,8")])
7561 (define_split
7562 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7563 (compare:CC
7564 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7565 (match_operand:SI 2 "const_int_operand" ""))
7566 (match_operand:DI 3 "const_int_operand" ""))
7567 (const_int 0)))
7568 (set (match_operand:DI 0 "gpc_reg_operand" "")
7569 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7570 "TARGET_POWERPC64 && reload_completed
7571 && includes_rldic_lshift_p (operands[2], operands[3])"
7572 [(set (match_dup 0)
7573 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7574 (match_dup 3)))
7575 (set (match_dup 4)
7576 (compare:CC (match_dup 0)
7577 (const_int 0)))]
7578 "")
7580 (define_insn "*ashldi3_internal7"
7581 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7582 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7583 (match_operand:SI 2 "const_int_operand" "i"))
7584 (match_operand:DI 3 "mask64_operand" "n")))]
7585 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7586 "rldicr %0,%1,%H2,%S3")
7588 (define_insn "ashldi3_internal8"
7589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7590 (compare:CC
7591 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7592 (match_operand:SI 2 "const_int_operand" "i,i"))
7593 (match_operand:DI 3 "mask64_operand" "n,n"))
7594 (const_int 0)))
7595 (clobber (match_scratch:DI 4 "=r,r"))]
7596 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7597 "@
7598 rldicr. %4,%1,%H2,%S3
7599 #"
7600 [(set_attr "type" "compare")
7601 (set_attr "length" "4,8")])
7603 (define_split
7604 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7605 (compare:CC
7606 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7607 (match_operand:SI 2 "const_int_operand" ""))
7608 (match_operand:DI 3 "mask64_operand" ""))
7609 (const_int 0)))
7610 (clobber (match_scratch:DI 4 ""))]
7611 "TARGET_POWERPC64 && reload_completed
7612 && includes_rldicr_lshift_p (operands[2], operands[3])"
7613 [(set (match_dup 4)
7614 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7615 (match_dup 3)))
7616 (set (match_dup 0)
7617 (compare:CC (match_dup 4)
7618 (const_int 0)))]
7619 "")
7621 (define_insn "*ashldi3_internal9"
7622 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7623 (compare:CC
7624 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7625 (match_operand:SI 2 "const_int_operand" "i,i"))
7626 (match_operand:DI 3 "mask64_operand" "n,n"))
7627 (const_int 0)))
7628 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7629 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7630 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7631 "@
7632 rldicr. %0,%1,%H2,%S3
7633 #"
7634 [(set_attr "type" "compare")
7635 (set_attr "length" "4,8")])
7637 (define_split
7638 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7639 (compare:CC
7640 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7641 (match_operand:SI 2 "const_int_operand" ""))
7642 (match_operand:DI 3 "mask64_operand" ""))
7643 (const_int 0)))
7644 (set (match_operand:DI 0 "gpc_reg_operand" "")
7645 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7646 "TARGET_POWERPC64 && reload_completed
7647 && includes_rldicr_lshift_p (operands[2], operands[3])"
7648 [(set (match_dup 0)
7649 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7650 (match_dup 3)))
7651 (set (match_dup 4)
7652 (compare:CC (match_dup 0)
7653 (const_int 0)))]
7654 "")
7656 (define_expand "lshrdi3"
7657 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7658 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7659 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7660 "TARGET_POWERPC64"
7661 "")
7663 (define_insn "*lshrdi3_internal1"
7664 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7665 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7666 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7667 "TARGET_POWERPC64"
7668 "@
7669 srd %0,%1,%2
7670 srdi %0,%1,%H2"
7671 [(set_attr "type" "var_shift_rotate,shift")])
7673 (define_insn "*lshrdi3_internal2"
7674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7675 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7676 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7677 (const_int 0)))
7678 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7679 "TARGET_64BIT "
7680 "@
7681 srd. %3,%1,%2
7682 srdi. %3,%1,%H2
7683 #
7684 #"
7685 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7686 (set_attr "length" "4,4,8,8")])
7688 (define_split
7689 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7690 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7691 (match_operand:SI 2 "reg_or_cint_operand" ""))
7692 (const_int 0)))
7693 (clobber (match_scratch:DI 3 ""))]
7694 "TARGET_POWERPC64 && reload_completed"
7695 [(set (match_dup 3)
7696 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7697 (set (match_dup 0)
7698 (compare:CC (match_dup 3)
7699 (const_int 0)))]
7700 "")
7702 (define_insn "*lshrdi3_internal3"
7703 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7704 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7705 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7706 (const_int 0)))
7707 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7708 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7709 "TARGET_64BIT"
7710 "@
7711 srd. %0,%1,%2
7712 srdi. %0,%1,%H2
7713 #
7714 #"
7715 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7716 (set_attr "length" "4,4,8,8")])
7718 (define_split
7719 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7720 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7721 (match_operand:SI 2 "reg_or_cint_operand" ""))
7722 (const_int 0)))
7723 (set (match_operand:DI 0 "gpc_reg_operand" "")
7724 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7725 "TARGET_POWERPC64 && reload_completed"
7726 [(set (match_dup 0)
7727 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7728 (set (match_dup 3)
7729 (compare:CC (match_dup 0)
7730 (const_int 0)))]
7731 "")
7733 (define_expand "ashrdi3"
7734 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7735 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7736 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7737 "WORDS_BIG_ENDIAN"
7738 "
7739 {
7740 if (TARGET_POWERPC64)
7741 ;
7742 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7743 && WORDS_BIG_ENDIAN)
7744 {
7745 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7746 DONE;
7747 }
7748 else
7749 FAIL;
7750 }")
7752 (define_insn "*ashrdi3_internal1"
7753 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7754 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7755 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7756 "TARGET_POWERPC64"
7757 "@
7758 srad %0,%1,%2
7759 sradi %0,%1,%H2"
7760 [(set_attr "type" "var_shift_rotate,shift")])
7762 (define_insn "*ashrdi3_internal2"
7763 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7764 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7765 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7766 (const_int 0)))
7767 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7768 "TARGET_64BIT"
7769 "@
7770 srad. %3,%1,%2
7771 sradi. %3,%1,%H2
7772 #
7773 #"
7774 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7775 (set_attr "length" "4,4,8,8")])
7777 (define_split
7778 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7779 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7780 (match_operand:SI 2 "reg_or_cint_operand" ""))
7781 (const_int 0)))
7782 (clobber (match_scratch:DI 3 ""))]
7783 "TARGET_POWERPC64 && reload_completed"
7784 [(set (match_dup 3)
7785 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7786 (set (match_dup 0)
7787 (compare:CC (match_dup 3)
7788 (const_int 0)))]
7789 "")
7791 (define_insn "*ashrdi3_internal3"
7792 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7793 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7794 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7795 (const_int 0)))
7796 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7797 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7798 "TARGET_64BIT"
7799 "@
7800 srad. %0,%1,%2
7801 sradi. %0,%1,%H2
7802 #
7803 #"
7804 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7805 (set_attr "length" "4,4,8,8")])
7807 (define_split
7808 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7809 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7810 (match_operand:SI 2 "reg_or_cint_operand" ""))
7811 (const_int 0)))
7812 (set (match_operand:DI 0 "gpc_reg_operand" "")
7813 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7814 "TARGET_POWERPC64 && reload_completed"
7815 [(set (match_dup 0)
7816 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7817 (set (match_dup 3)
7818 (compare:CC (match_dup 0)
7819 (const_int 0)))]
7820 "")
7822 (define_expand "anddi3"
7823 [(parallel
7824 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7825 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7826 (match_operand:DI 2 "and64_2_operand" "")))
7827 (clobber (match_scratch:CC 3 ""))])]
7828 "TARGET_POWERPC64"
7829 "")
7831 (define_insn "anddi3_mc"
7832 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7833 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7834 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7835 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7836 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7837 "@
7838 and %0,%1,%2
7839 rldic%B2 %0,%1,0,%S2
7840 rlwinm %0,%1,0,%m2,%M2
7841 andi. %0,%1,%b2
7842 andis. %0,%1,%u2
7843 #"
7844 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7845 (set_attr "length" "4,4,4,4,4,8")])
7847 (define_insn "anddi3_nomc"
7848 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7849 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7850 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7851 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7852 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7853 "@
7854 and %0,%1,%2
7855 rldic%B2 %0,%1,0,%S2
7856 rlwinm %0,%1,0,%m2,%M2
7857 #"
7858 [(set_attr "length" "4,4,4,8")])
7860 (define_split
7861 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7862 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7863 (match_operand:DI 2 "mask64_2_operand" "")))
7864 (clobber (match_scratch:CC 3 ""))]
7865 "TARGET_POWERPC64
7866 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7867 && !mask_operand (operands[2], DImode)
7868 && !mask64_operand (operands[2], DImode)"
7869 [(set (match_dup 0)
7870 (and:DI (rotate:DI (match_dup 1)
7871 (match_dup 4))
7872 (match_dup 5)))
7873 (set (match_dup 0)
7874 (and:DI (rotate:DI (match_dup 0)
7875 (match_dup 6))
7876 (match_dup 7)))]
7877 {
7878 build_mask64_2_operands (operands[2], &operands[4]);
7879 })
7881 (define_insn "*anddi3_internal2_mc"
7882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7883 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7884 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7885 (const_int 0)))
7886 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7887 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7888 "TARGET_64BIT && rs6000_gen_cell_microcode"
7889 "@
7890 and. %3,%1,%2
7891 rldic%B2. %3,%1,0,%S2
7892 rlwinm. %3,%1,0,%m2,%M2
7893 andi. %3,%1,%b2
7894 andis. %3,%1,%u2
7895 #
7896 #
7897 #
7898 #
7899 #
7900 #
7901 #"
7902 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7903 fast_compare,compare,compare,compare,compare,compare,\
7904 compare,compare")
7905 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7907 (define_split
7908 [(set (match_operand:CC 0 "cc_reg_operand" "")
7909 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7910 (match_operand:DI 2 "mask64_2_operand" ""))
7911 (const_int 0)))
7912 (clobber (match_scratch:DI 3 ""))
7913 (clobber (match_scratch:CC 4 ""))]
7914 "TARGET_64BIT && reload_completed
7915 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7916 && !mask_operand (operands[2], DImode)
7917 && !mask64_operand (operands[2], DImode)"
7918 [(set (match_dup 3)
7919 (and:DI (rotate:DI (match_dup 1)
7920 (match_dup 5))
7921 (match_dup 6)))
7922 (parallel [(set (match_dup 0)
7923 (compare:CC (and:DI (rotate:DI (match_dup 3)
7924 (match_dup 7))
7925 (match_dup 8))
7926 (const_int 0)))
7927 (clobber (match_dup 3))])]
7928 "
7929 {
7930 build_mask64_2_operands (operands[2], &operands[5]);
7931 }")
7933 (define_insn "*anddi3_internal3_mc"
7934 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7935 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7936 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7937 (const_int 0)))
7938 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7939 (and:DI (match_dup 1) (match_dup 2)))
7940 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7941 "TARGET_64BIT && rs6000_gen_cell_microcode"
7942 "@
7943 and. %0,%1,%2
7944 rldic%B2. %0,%1,0,%S2
7945 rlwinm. %0,%1,0,%m2,%M2
7946 andi. %0,%1,%b2
7947 andis. %0,%1,%u2
7948 #
7949 #
7950 #
7951 #
7952 #
7953 #
7954 #"
7955 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7956 fast_compare,compare,compare,compare,compare,compare,\
7957 compare,compare")
7958 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7960 (define_split
7961 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7962 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7963 (match_operand:DI 2 "and64_2_operand" ""))
7964 (const_int 0)))
7965 (set (match_operand:DI 0 "gpc_reg_operand" "")
7966 (and:DI (match_dup 1) (match_dup 2)))
7967 (clobber (match_scratch:CC 4 ""))]
7968 "TARGET_64BIT && reload_completed"
7969 [(parallel [(set (match_dup 0)
7970 (and:DI (match_dup 1) (match_dup 2)))
7971 (clobber (match_dup 4))])
7972 (set (match_dup 3)
7973 (compare:CC (match_dup 0)
7974 (const_int 0)))]
7975 "")
7977 (define_split
7978 [(set (match_operand:CC 3 "cc_reg_operand" "")
7979 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7980 (match_operand:DI 2 "mask64_2_operand" ""))
7981 (const_int 0)))
7982 (set (match_operand:DI 0 "gpc_reg_operand" "")
7983 (and:DI (match_dup 1) (match_dup 2)))
7984 (clobber (match_scratch:CC 4 ""))]
7985 "TARGET_64BIT && reload_completed
7986 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7987 && !mask_operand (operands[2], DImode)
7988 && !mask64_operand (operands[2], DImode)"
7989 [(set (match_dup 0)
7990 (and:DI (rotate:DI (match_dup 1)
7991 (match_dup 5))
7992 (match_dup 6)))
7993 (parallel [(set (match_dup 3)
7994 (compare:CC (and:DI (rotate:DI (match_dup 0)
7995 (match_dup 7))
7996 (match_dup 8))
7997 (const_int 0)))
7998 (set (match_dup 0)
7999 (and:DI (rotate:DI (match_dup 0)
8000 (match_dup 7))
8001 (match_dup 8)))])]
8002 "
8003 {
8004 build_mask64_2_operands (operands[2], &operands[5]);
8005 }")
8007 (define_expand "iordi3"
8008 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8009 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8010 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8011 "TARGET_POWERPC64"
8012 "
8013 {
8014 if (non_logical_cint_operand (operands[2], DImode))
8015 {
8016 HOST_WIDE_INT value;
8017 rtx tmp = ((!can_create_pseudo_p ()
8018 || rtx_equal_p (operands[0], operands[1]))
8019 ? operands[0] : gen_reg_rtx (DImode));
8021 value = INTVAL (operands[2]);
8022 emit_insn (gen_iordi3 (tmp, operands[1],
8023 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8025 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8026 DONE;
8027 }
8028 }")
8030 (define_expand "xordi3"
8031 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8032 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8033 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8034 "TARGET_POWERPC64"
8035 "
8036 {
8037 if (non_logical_cint_operand (operands[2], DImode))
8038 {
8039 HOST_WIDE_INT value;
8040 rtx tmp = ((!can_create_pseudo_p ()
8041 || rtx_equal_p (operands[0], operands[1]))
8042 ? operands[0] : gen_reg_rtx (DImode));
8044 value = INTVAL (operands[2]);
8045 emit_insn (gen_xordi3 (tmp, operands[1],
8046 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8048 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8049 DONE;
8050 }
8051 }")
8053 (define_insn "*booldi3_internal1"
8054 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8055 (match_operator:DI 3 "boolean_or_operator"
8056 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8057 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8058 "TARGET_POWERPC64"
8059 "@
8060 %q3 %0,%1,%2
8061 %q3i %0,%1,%b2
8062 %q3is %0,%1,%u2")
8064 (define_insn "*booldi3_internal2"
8065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8066 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8067 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8068 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8069 (const_int 0)))
8070 (clobber (match_scratch:DI 3 "=r,r"))]
8071 "TARGET_64BIT"
8072 "@
8073 %q4. %3,%1,%2
8074 #"
8075 [(set_attr "type" "fast_compare,compare")
8076 (set_attr "length" "4,8")])
8078 (define_split
8079 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8080 (compare:CC (match_operator:DI 4 "boolean_operator"
8081 [(match_operand:DI 1 "gpc_reg_operand" "")
8082 (match_operand:DI 2 "gpc_reg_operand" "")])
8083 (const_int 0)))
8084 (clobber (match_scratch:DI 3 ""))]
8085 "TARGET_POWERPC64 && reload_completed"
8086 [(set (match_dup 3) (match_dup 4))
8087 (set (match_dup 0)
8088 (compare:CC (match_dup 3)
8089 (const_int 0)))]
8090 "")
8092 (define_insn "*booldi3_internal3"
8093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8094 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8095 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8096 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8097 (const_int 0)))
8098 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8099 (match_dup 4))]
8100 "TARGET_64BIT"
8101 "@
8102 %q4. %0,%1,%2
8103 #"
8104 [(set_attr "type" "fast_compare,compare")
8105 (set_attr "length" "4,8")])
8107 (define_split
8108 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8109 (compare:CC (match_operator:DI 4 "boolean_operator"
8110 [(match_operand:DI 1 "gpc_reg_operand" "")
8111 (match_operand:DI 2 "gpc_reg_operand" "")])
8112 (const_int 0)))
8113 (set (match_operand:DI 0 "gpc_reg_operand" "")
8114 (match_dup 4))]
8115 "TARGET_POWERPC64 && reload_completed"
8116 [(set (match_dup 0) (match_dup 4))
8117 (set (match_dup 3)
8118 (compare:CC (match_dup 0)
8119 (const_int 0)))]
8120 "")
8122 ;; Split a logical operation that we can't do in one insn into two insns,
8123 ;; each of which does one 16-bit part. This is used by combine.
8125 (define_split
8126 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8127 (match_operator:DI 3 "boolean_or_operator"
8128 [(match_operand:DI 1 "gpc_reg_operand" "")
8129 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8130 "TARGET_POWERPC64"
8131 [(set (match_dup 0) (match_dup 4))
8132 (set (match_dup 0) (match_dup 5))]
8133 "
8134 {
8135 rtx i3,i4;
8137 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8138 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8139 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8140 operands[1], i3);
8141 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8142 operands[0], i4);
8143 }")
8145 (define_insn "*boolcdi3_internal1"
8146 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8147 (match_operator:DI 3 "boolean_operator"
8148 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8149 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8150 "TARGET_POWERPC64"
8151 "%q3 %0,%2,%1")
8153 (define_insn "*boolcdi3_internal2"
8154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8155 (compare:CC (match_operator:DI 4 "boolean_operator"
8156 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8157 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8158 (const_int 0)))
8159 (clobber (match_scratch:DI 3 "=r,r"))]
8160 "TARGET_64BIT"
8161 "@
8162 %q4. %3,%2,%1
8163 #"
8164 [(set_attr "type" "fast_compare,compare")
8165 (set_attr "length" "4,8")])
8167 (define_split
8168 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8169 (compare:CC (match_operator:DI 4 "boolean_operator"
8170 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8171 (match_operand:DI 2 "gpc_reg_operand" "")])
8172 (const_int 0)))
8173 (clobber (match_scratch:DI 3 ""))]
8174 "TARGET_POWERPC64 && reload_completed"
8175 [(set (match_dup 3) (match_dup 4))
8176 (set (match_dup 0)
8177 (compare:CC (match_dup 3)
8178 (const_int 0)))]
8179 "")
8181 (define_insn "*boolcdi3_internal3"
8182 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8183 (compare:CC (match_operator:DI 4 "boolean_operator"
8184 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8185 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8186 (const_int 0)))
8187 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8188 (match_dup 4))]
8189 "TARGET_64BIT"
8190 "@
8191 %q4. %0,%2,%1
8192 #"
8193 [(set_attr "type" "fast_compare,compare")
8194 (set_attr "length" "4,8")])
8196 (define_split
8197 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8198 (compare:CC (match_operator:DI 4 "boolean_operator"
8199 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8200 (match_operand:DI 2 "gpc_reg_operand" "")])
8201 (const_int 0)))
8202 (set (match_operand:DI 0 "gpc_reg_operand" "")
8203 (match_dup 4))]
8204 "TARGET_POWERPC64 && reload_completed"
8205 [(set (match_dup 0) (match_dup 4))
8206 (set (match_dup 3)
8207 (compare:CC (match_dup 0)
8208 (const_int 0)))]
8209 "")
8211 (define_insn "*boolccdi3_internal1"
8212 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8213 (match_operator:DI 3 "boolean_operator"
8214 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8215 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8216 "TARGET_POWERPC64"
8217 "%q3 %0,%1,%2")
8219 (define_insn "*boolccdi3_internal2"
8220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8221 (compare:CC (match_operator:DI 4 "boolean_operator"
8222 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8223 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8224 (const_int 0)))
8225 (clobber (match_scratch:DI 3 "=r,r"))]
8226 "TARGET_64BIT"
8227 "@
8228 %q4. %3,%1,%2
8229 #"
8230 [(set_attr "type" "fast_compare,compare")
8231 (set_attr "length" "4,8")])
8233 (define_split
8234 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8235 (compare:CC (match_operator:DI 4 "boolean_operator"
8236 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8237 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8238 (const_int 0)))
8239 (clobber (match_scratch:DI 3 ""))]
8240 "TARGET_POWERPC64 && reload_completed"
8241 [(set (match_dup 3) (match_dup 4))
8242 (set (match_dup 0)
8243 (compare:CC (match_dup 3)
8244 (const_int 0)))]
8245 "")
8247 (define_insn "*boolccdi3_internal3"
8248 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8249 (compare:CC (match_operator:DI 4 "boolean_operator"
8250 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8251 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8252 (const_int 0)))
8253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8254 (match_dup 4))]
8255 "TARGET_64BIT"
8256 "@
8257 %q4. %0,%1,%2
8258 #"
8259 [(set_attr "type" "fast_compare,compare")
8260 (set_attr "length" "4,8")])
8262 (define_split
8263 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8264 (compare:CC (match_operator:DI 4 "boolean_operator"
8265 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8266 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8267 (const_int 0)))
8268 (set (match_operand:DI 0 "gpc_reg_operand" "")
8269 (match_dup 4))]
8270 "TARGET_POWERPC64 && reload_completed"
8271 [(set (match_dup 0) (match_dup 4))
8272 (set (match_dup 3)
8273 (compare:CC (match_dup 0)
8274 (const_int 0)))]
8275 "")
8276 \f
8277 ;; Now define ways of moving data around.
8279 ;; Set up a register with a value from the GOT table
8281 (define_expand "movsi_got"
8282 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8283 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8284 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8285 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8286 "
8287 {
8288 if (GET_CODE (operands[1]) == CONST)
8289 {
8290 rtx offset = const0_rtx;
8291 HOST_WIDE_INT value;
8293 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8294 value = INTVAL (offset);
8295 if (value != 0)
8296 {
8297 rtx tmp = (!can_create_pseudo_p ()
8298 ? operands[0]
8299 : gen_reg_rtx (Pmode));
8300 emit_insn (gen_movsi_got (tmp, operands[1]));
8301 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8302 DONE;
8303 }
8304 }
8306 operands[2] = rs6000_got_register (operands[1]);
8307 }")
8309 (define_insn "*movsi_got_internal"
8310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8311 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8312 (match_operand:SI 2 "gpc_reg_operand" "b")]
8313 UNSPEC_MOVSI_GOT))]
8314 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8315 "lwz %0,%a1@got(%2)"
8316 [(set_attr "type" "load")])
8318 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8319 ;; didn't get allocated to a hard register.
8320 (define_split
8321 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8322 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8323 (match_operand:SI 2 "memory_operand" "")]
8324 UNSPEC_MOVSI_GOT))]
8325 "DEFAULT_ABI == ABI_V4
8326 && flag_pic == 1
8327 && (reload_in_progress || reload_completed)"
8328 [(set (match_dup 0) (match_dup 2))
8329 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8330 UNSPEC_MOVSI_GOT))]
8331 "")
8333 ;; For SI, we special-case integers that can't be loaded in one insn. We
8334 ;; do the load 16-bits at a time. We could do this by loading from memory,
8335 ;; and this is even supposed to be faster, but it is simpler not to get
8336 ;; integers in the TOC.
8337 (define_insn "movsi_low"
8338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8339 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8340 (match_operand 2 "" ""))))]
8341 "TARGET_MACHO && ! TARGET_64BIT"
8342 "lwz %0,lo16(%2)(%1)"
8343 [(set_attr "type" "load")
8344 (set_attr "length" "4")])
8346 (define_insn "*movsi_internal1"
8347 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8348 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8349 "!TARGET_SINGLE_FPU &&
8350 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8351 "@
8352 mr %0,%1
8353 la %0,%a1
8354 lwz%U1%X1 %0,%1
8355 stw%U0%X0 %1,%0
8356 li %0,%1
8357 lis %0,%v1
8358 #
8359 mf%1 %0
8360 mt%0 %1
8361 mt%0 %1
8362 nop"
8363 [(set_attr_alternative "type"
8364 [(const_string "*")
8365 (const_string "*")
8366 (if_then_else
8367 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8368 (const_string "load_ux")
8369 (if_then_else
8370 (match_test "update_address_mem (operands[1], VOIDmode)")
8371 (const_string "load_u")
8372 (const_string "load")))
8373 (if_then_else
8374 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8375 (const_string "store_ux")
8376 (if_then_else
8377 (match_test "update_address_mem (operands[0], VOIDmode)")
8378 (const_string "store_u")
8379 (const_string "store")))
8380 (const_string "*")
8381 (const_string "*")
8382 (const_string "*")
8383 (const_string "mfjmpr")
8384 (const_string "mtjmpr")
8385 (const_string "*")
8386 (const_string "*")])
8388 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8390 (define_insn "*movsi_internal1_single"
8391 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8392 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8393 "TARGET_SINGLE_FPU &&
8394 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8395 "@
8396 mr %0,%1
8397 la %0,%a1
8398 lwz%U1%X1 %0,%1
8399 stw%U0%X0 %1,%0
8400 li %0,%1
8401 lis %0,%v1
8402 #
8403 mf%1 %0
8404 mt%0 %1
8405 mt%0 %1
8406 nop
8407 stfs%U0%X0 %1,%0
8408 lfs%U1%X1 %0,%1"
8409 [(set_attr_alternative "type"
8410 [(const_string "*")
8411 (const_string "*")
8412 (if_then_else
8413 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8414 (const_string "load_ux")
8415 (if_then_else
8416 (match_test "update_address_mem (operands[1], VOIDmode)")
8417 (const_string "load_u")
8418 (const_string "load")))
8419 (if_then_else
8420 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8421 (const_string "store_ux")
8422 (if_then_else
8423 (match_test "update_address_mem (operands[0], VOIDmode)")
8424 (const_string "store_u")
8425 (const_string "store")))
8426 (const_string "*")
8427 (const_string "*")
8428 (const_string "*")
8429 (const_string "mfjmpr")
8430 (const_string "mtjmpr")
8431 (const_string "*")
8432 (const_string "*")
8433 (if_then_else
8434 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8435 (const_string "fpstore_ux")
8436 (if_then_else
8437 (match_test "update_address_mem (operands[0], VOIDmode)")
8438 (const_string "fpstore_u")
8439 (const_string "fpstore")))
8440 (if_then_else
8441 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8442 (const_string "fpload_ux")
8443 (if_then_else
8444 (match_test "update_address_mem (operands[1], VOIDmode)")
8445 (const_string "fpload_u")
8446 (const_string "fpload")))])
8447 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8449 ;; Split a load of a large constant into the appropriate two-insn
8450 ;; sequence.
8452 (define_split
8453 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8454 (match_operand:SI 1 "const_int_operand" ""))]
8455 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8456 && (INTVAL (operands[1]) & 0xffff) != 0"
8457 [(set (match_dup 0)
8458 (match_dup 2))
8459 (set (match_dup 0)
8460 (ior:SI (match_dup 0)
8461 (match_dup 3)))]
8462 "
8463 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8465 if (tem == operands[0])
8466 DONE;
8467 else
8468 FAIL;
8469 }")
8471 (define_insn "*mov<mode>_internal2"
8472 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8473 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8474 (const_int 0)))
8475 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8476 ""
8477 "@
8478 cmp<wd>i %2,%0,0
8479 mr. %0,%1
8480 #"
8481 [(set_attr "type" "cmp,compare,cmp")
8482 (set_attr "length" "4,4,8")])
8484 (define_split
8485 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8486 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8487 (const_int 0)))
8488 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8489 "reload_completed"
8490 [(set (match_dup 0) (match_dup 1))
8491 (set (match_dup 2)
8492 (compare:CC (match_dup 0)
8493 (const_int 0)))]
8494 "")
8495 \f
8496 (define_insn "*movhi_internal"
8497 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8498 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8499 "gpc_reg_operand (operands[0], HImode)
8500 || gpc_reg_operand (operands[1], HImode)"
8501 "@
8502 mr %0,%1
8503 lhz%U1%X1 %0,%1
8504 sth%U0%X0 %1,%0
8505 li %0,%w1
8506 mf%1 %0
8507 mt%0 %1
8508 nop"
8509 [(set_attr_alternative "type"
8510 [(const_string "*")
8511 (if_then_else
8512 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8513 (const_string "load_ux")
8514 (if_then_else
8515 (match_test "update_address_mem (operands[1], VOIDmode)")
8516 (const_string "load_u")
8517 (const_string "load")))
8518 (if_then_else
8519 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8520 (const_string "store_ux")
8521 (if_then_else
8522 (match_test "update_address_mem (operands[0], VOIDmode)")
8523 (const_string "store_u")
8524 (const_string "store")))
8525 (const_string "*")
8526 (const_string "mfjmpr")
8527 (const_string "mtjmpr")
8528 (const_string "*")])])
8530 (define_expand "mov<mode>"
8531 [(set (match_operand:INT 0 "general_operand" "")
8532 (match_operand:INT 1 "any_operand" ""))]
8533 ""
8534 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8536 (define_insn "*movqi_internal"
8537 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8538 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8539 "gpc_reg_operand (operands[0], QImode)
8540 || gpc_reg_operand (operands[1], QImode)"
8541 "@
8542 mr %0,%1
8543 lbz%U1%X1 %0,%1
8544 stb%U0%X0 %1,%0
8545 li %0,%1
8546 mf%1 %0
8547 mt%0 %1
8548 nop"
8549 [(set_attr_alternative "type"
8550 [(const_string "*")
8551 (if_then_else
8552 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8553 (const_string "load_ux")
8554 (if_then_else
8555 (match_test "update_address_mem (operands[1], VOIDmode)")
8556 (const_string "load_u")
8557 (const_string "load")))
8558 (if_then_else
8559 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8560 (const_string "store_ux")
8561 (if_then_else
8562 (match_test "update_address_mem (operands[0], VOIDmode)")
8563 (const_string "store_u")
8564 (const_string "store")))
8565 (const_string "*")
8566 (const_string "mfjmpr")
8567 (const_string "mtjmpr")
8568 (const_string "*")])])
8569 \f
8570 ;; Here is how to move condition codes around. When we store CC data in
8571 ;; an integer register or memory, we store just the high-order 4 bits.
8572 ;; This lets us not shift in the most common case of CR0.
8573 (define_expand "movcc"
8574 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8575 (match_operand:CC 1 "nonimmediate_operand" ""))]
8576 ""
8577 "")
8579 (define_insn "*movcc_internal1"
8580 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
8581 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
8582 "register_operand (operands[0], CCmode)
8583 || register_operand (operands[1], CCmode)"
8584 "@
8585 mcrf %0,%1
8586 mtcrf 128,%1
8587 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
8588 crxor %0,%0,%0
8589 mfcr %0%Q1
8590 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
8591 mr %0,%1
8592 li %0,%1
8593 mf%1 %0
8594 mt%0 %1
8595 lwz%U1%X1 %0,%1
8596 stw%U0%X0 %1,%0"
8597 [(set (attr "type")
8598 (cond [(eq_attr "alternative" "0,3")
8599 (const_string "cr_logical")
8600 (eq_attr "alternative" "1,2")
8601 (const_string "mtcr")
8602 (eq_attr "alternative" "6,7")
8603 (const_string "integer")
8604 (eq_attr "alternative" "8")
8605 (const_string "mfjmpr")
8606 (eq_attr "alternative" "9")
8607 (const_string "mtjmpr")
8608 (eq_attr "alternative" "10")
8609 (if_then_else
8610 (match_test "update_indexed_address_mem (operands[1],
8611 VOIDmode)")
8612 (const_string "load_ux")
8613 (if_then_else
8614 (match_test "update_address_mem (operands[1], VOIDmode)")
8615 (const_string "load_u")
8616 (const_string "load")))
8617 (eq_attr "alternative" "11")
8618 (if_then_else
8619 (match_test "update_indexed_address_mem (operands[0],
8620 VOIDmode)")
8621 (const_string "store_ux")
8622 (if_then_else
8623 (match_test "update_address_mem (operands[0], VOIDmode)")
8624 (const_string "store_u")
8625 (const_string "store")))
8626 (match_test "TARGET_MFCRF")
8627 (const_string "mfcrf")
8628 ]
8629 (const_string "mfcr")))
8630 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8631 \f
8632 ;; For floating-point, we normally deal with the floating-point registers
8633 ;; unless -msoft-float is used. The sole exception is that parameter passing
8634 ;; can produce floating-point values in fixed-point registers. Unless the
8635 ;; value is a simple constant or already in memory, we deal with this by
8636 ;; allocating memory and copying the value explicitly via that memory location.
8638 ;; Move 32-bit binary/decimal floating point
8639 (define_expand "mov<mode>"
8640 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8641 (match_operand:FMOVE32 1 "any_operand" ""))]
8642 "<fmove_ok>"
8643 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8645 (define_split
8646 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8647 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8648 "reload_completed
8649 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8650 || (GET_CODE (operands[0]) == SUBREG
8651 && GET_CODE (SUBREG_REG (operands[0])) == REG
8652 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8653 [(set (match_dup 2) (match_dup 3))]
8654 "
8655 {
8656 long l;
8657 REAL_VALUE_TYPE rv;
8659 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8660 <real_value_to_target> (rv, l);
8662 if (! TARGET_POWERPC64)
8663 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
8664 else
8665 operands[2] = gen_lowpart (SImode, operands[0]);
8667 operands[3] = gen_int_mode (l, SImode);
8668 }")
8670 (define_insn "mov<mode>_hardfloat"
8671 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,*c*l,!r,*h,!r,!r")
8672 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,r,h,0,G,Fn"))]
8673 "(gpc_reg_operand (operands[0], <MODE>mode)
8674 || gpc_reg_operand (operands[1], <MODE>mode))
8675 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8676 "@
8677 mr %0,%1
8678 lwz%U1%X1 %0,%1
8679 stw%U0%X0 %1,%0
8680 fmr %0,%1
8681 xxlor %x0,%x1,%x1
8682 xxlxor %x0,%x0,%x0
8683 <f32_li>
8684 <f32_si>
8685 mt%0 %1
8686 mf%1 %0
8687 nop
8688 #
8689 #"
8690 [(set_attr_alternative "type"
8691 [(const_string "*")
8692 (if_then_else
8693 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8694 (const_string "load_ux")
8695 (if_then_else
8696 (match_test "update_address_mem (operands[1], VOIDmode)")
8697 (const_string "load_u")
8698 (const_string "load")))
8699 (if_then_else
8700 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8701 (const_string "store_ux")
8702 (if_then_else
8703 (match_test "update_address_mem (operands[0], VOIDmode)")
8704 (const_string "store_u")
8705 (const_string "store")))
8706 (const_string "fp")
8707 (const_string "vecsimple")
8708 (const_string "vecsimple")
8709 (if_then_else
8710 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8711 (const_string "fpload_ux")
8712 (if_then_else
8713 (match_test "update_address_mem (operands[1], VOIDmode)")
8714 (const_string "fpload_u")
8715 (const_string "fpload")))
8716 (if_then_else
8717 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8718 (const_string "fpstore_ux")
8719 (if_then_else
8720 (match_test "update_address_mem (operands[0], VOIDmode)")
8721 (const_string "fpstore_u")
8722 (const_string "fpstore")))
8723 (const_string "mtjmpr")
8724 (const_string "mfjmpr")
8725 (const_string "*")
8726 (const_string "*")
8727 (const_string "*")])
8728 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8")])
8730 (define_insn "*mov<mode>_softfloat"
8731 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
8732 (match_operand:FMOVE32 1 "input_operand" "r, r,h,m,r,I,L,G,Fn,0"))]
8733 "(gpc_reg_operand (operands[0], <MODE>mode)
8734 || gpc_reg_operand (operands[1], <MODE>mode))
8735 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8736 "@
8737 mr %0,%1
8738 mt%0 %1
8739 mf%1 %0
8740 lwz%U1%X1 %0,%1
8741 stw%U0%X0 %1,%0
8742 li %0,%1
8743 lis %0,%v1
8744 #
8745 #
8746 nop"
8747 [(set_attr_alternative "type"
8748 [(const_string "*")
8749 (const_string "mtjmpr")
8750 (const_string "mfjmpr")
8751 (if_then_else
8752 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8753 (const_string "load_ux")
8754 (if_then_else
8755 (match_test "update_address_mem (operands[1], VOIDmode)")
8756 (const_string "load_u")
8757 (const_string "load")))
8758 (if_then_else
8759 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8760 (const_string "store_ux")
8761 (if_then_else
8762 (match_test "update_address_mem (operands[0], VOIDmode)")
8763 (const_string "store_u")
8764 (const_string "store")))
8765 (const_string "*")
8766 (const_string "*")
8767 (const_string "*")
8768 (const_string "*")
8769 (const_string "*")])
8770 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
8772 \f
8773 ;; Move 64-bit binary/decimal floating point
8774 (define_expand "mov<mode>"
8775 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
8776 (match_operand:FMOVE64 1 "any_operand" ""))]
8777 ""
8778 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8780 (define_split
8781 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8782 (match_operand:FMOVE64 1 "const_int_operand" ""))]
8783 "! TARGET_POWERPC64 && reload_completed
8784 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8785 || (GET_CODE (operands[0]) == SUBREG
8786 && GET_CODE (SUBREG_REG (operands[0])) == REG
8787 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8788 [(set (match_dup 2) (match_dup 4))
8789 (set (match_dup 3) (match_dup 1))]
8790 "
8791 {
8792 int endian = (WORDS_BIG_ENDIAN == 0);
8793 HOST_WIDE_INT value = INTVAL (operands[1]);
8795 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8796 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8797 operands[4] = GEN_INT (value >> 32);
8798 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8799 }")
8801 (define_split
8802 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8803 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8804 "! TARGET_POWERPC64 && reload_completed
8805 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8806 || (GET_CODE (operands[0]) == SUBREG
8807 && GET_CODE (SUBREG_REG (operands[0])) == REG
8808 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8809 [(set (match_dup 2) (match_dup 4))
8810 (set (match_dup 3) (match_dup 5))]
8811 "
8812 {
8813 int endian = (WORDS_BIG_ENDIAN == 0);
8814 long l[2];
8815 REAL_VALUE_TYPE rv;
8817 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8818 <real_value_to_target> (rv, l);
8820 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8821 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8822 operands[4] = gen_int_mode (l[endian], SImode);
8823 operands[5] = gen_int_mode (l[1 - endian], SImode);
8824 }")
8826 (define_split
8827 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8828 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8829 "TARGET_POWERPC64 && reload_completed
8830 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8831 || (GET_CODE (operands[0]) == SUBREG
8832 && GET_CODE (SUBREG_REG (operands[0])) == REG
8833 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8834 [(set (match_dup 2) (match_dup 3))]
8835 "
8836 {
8837 int endian = (WORDS_BIG_ENDIAN == 0);
8838 long l[2];
8839 REAL_VALUE_TYPE rv;
8840 HOST_WIDE_INT val;
8842 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8843 <real_value_to_target> (rv, l);
8845 operands[2] = gen_lowpart (DImode, operands[0]);
8846 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8847 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8848 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8850 operands[3] = gen_int_mode (val, DImode);
8851 }")
8853 ;; Don't have reload use general registers to load a constant. It is
8854 ;; less efficient than loading the constant into an FP register, since
8855 ;; it will probably be used there.
8857 ;; The move constraints are ordered to prefer floating point registers before
8858 ;; general purpose registers to avoid doing a store and a load to get the value
8859 ;; into a floating point register when it is needed for a floating point
8860 ;; operation. Prefer traditional floating point registers over VSX registers,
8861 ;; since the D-form version of the memory instructions does not need a GPR for
8862 ;; reloading.
8864 (define_insn "*mov<mode>_hardfloat32"
8865 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
8866 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
8867 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8868 && (gpc_reg_operand (operands[0], <MODE>mode)
8869 || gpc_reg_operand (operands[1], <MODE>mode))"
8870 "@
8871 stfd%U0%X0 %1,%0
8872 lfd%U1%X1 %0,%1
8873 fmr %0,%1
8874 lxsd%U1x %x0,%y1
8875 lxsd%U1x %x0,%y1
8876 stxsd%U0x %x1,%y0
8877 stxsd%U0x %x1,%y0
8878 xxlor %x0,%x1,%x1
8879 xxlor %x0,%x1,%x1
8880 xxlxor %x0,%x0,%x0
8881 #
8882 #
8883 #
8884 #
8885 #
8886 #"
8887 [(set_attr_alternative "type"
8888 [(if_then_else
8889 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8890 (const_string "fpstore_ux")
8891 (if_then_else
8892 (match_test "update_address_mem (operands[0], VOIDmode)")
8893 (const_string "fpstore_u")
8894 (const_string "fpstore")))
8895 (if_then_else
8896 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8897 (const_string "fpload_ux")
8898 (if_then_else
8899 (match_test "update_address_mem (operands[1], VOIDmode)")
8900 (const_string "fpload_u")
8901 (const_string "fpload")))
8902 (const_string "fp")
8903 (if_then_else
8904 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8905 (const_string "fpload_ux")
8906 (const_string "fpload"))
8907 (if_then_else
8908 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8909 (const_string "fpload_ux")
8910 (const_string "fpload"))
8911 (if_then_else
8912 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8913 (const_string "fpstore_ux")
8914 (const_string "fpstore"))
8915 (if_then_else
8916 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8917 (const_string "fpstore_ux")
8918 (const_string "fpstore"))
8919 (const_string "vecsimple")
8920 (const_string "vecsimple")
8921 (const_string "vecsimple")
8922 (const_string "store")
8923 (const_string "load")
8924 (const_string "two")
8925 (const_string "fp")
8926 (const_string "fp")
8927 (const_string "*")])
8928 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
8930 (define_insn "*mov<mode>_softfloat32"
8931 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8932 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8933 "! TARGET_POWERPC64
8934 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8935 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8936 && (gpc_reg_operand (operands[0], <MODE>mode)
8937 || gpc_reg_operand (operands[1], <MODE>mode))"
8938 "#"
8939 [(set_attr "type" "store,load,two,*,*,*")
8940 (set_attr "length" "8,8,8,8,12,16")])
8942 ; ld/std require word-aligned displacements -> 'Y' constraint.
8943 ; List Y->r and r->Y before r->r for reload.
8944 (define_insn "*mov<mode>_hardfloat64"
8945 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg")
8946 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,r,h,0,G,H,F,wg,r"))]
8947 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8948 && (gpc_reg_operand (operands[0], <MODE>mode)
8949 || gpc_reg_operand (operands[1], <MODE>mode))"
8950 "@
8951 stfd%U0%X0 %1,%0
8952 lfd%U1%X1 %0,%1
8953 fmr %0,%1
8954 lxsd%U1x %x0,%y1
8955 lxsd%U1x %x0,%y1
8956 stxsd%U0x %x1,%y0
8957 stxsd%U0x %x1,%y0
8958 xxlor %x0,%x1,%x1
8959 xxlor %x0,%x1,%x1
8960 xxlxor %x0,%x0,%x0
8961 std%U0%X0 %1,%0
8962 ld%U1%X1 %0,%1
8963 mr %0,%1
8964 mt%0 %1
8965 mf%1 %0
8966 nop
8967 #
8968 #
8969 #
8970 mftgpr %0,%1
8971 mffgpr %0,%1"
8972 [(set_attr_alternative "type"
8973 [(if_then_else
8974 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8975 (const_string "fpstore_ux")
8976 (if_then_else
8977 (match_test "update_address_mem (operands[0], VOIDmode)")
8978 (const_string "fpstore_u")
8979 (const_string "fpstore")))
8980 (if_then_else
8981 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8982 (const_string "fpload_ux")
8983 (if_then_else
8984 (match_test "update_address_mem (operands[1], VOIDmode)")
8985 (const_string "fpload_u")
8986 (const_string "fpload")))
8987 (const_string "fp")
8988 (if_then_else
8989 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8990 (const_string "fpload_ux")
8991 (const_string "fpload"))
8992 (if_then_else
8993 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8994 (const_string "fpload_ux")
8995 (const_string "fpload"))
8996 (if_then_else
8997 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8998 (const_string "fpstore_ux")
8999 (const_string "fpstore"))
9000 (if_then_else
9001 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9002 (const_string "fpstore_ux")
9003 (const_string "fpstore"))
9004 (const_string "vecsimple")
9005 (const_string "vecsimple")
9006 (const_string "vecsimple")
9007 (if_then_else
9008 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9009 (const_string "store_ux")
9010 (if_then_else
9011 (match_test "update_address_mem (operands[0], VOIDmode)")
9012 (const_string "store_u")
9013 (const_string "store")))
9014 (if_then_else
9015 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9016 (const_string "load_ux")
9017 (if_then_else
9018 (match_test "update_address_mem (operands[1], VOIDmode)")
9019 (const_string "load_u")
9020 (const_string "load")))
9021 (const_string "*")
9022 (const_string "mtjmpr")
9023 (const_string "mfjmpr")
9024 (const_string "*")
9025 (const_string "*")
9026 (const_string "*")
9027 (const_string "*")
9028 (const_string "mftgpr")
9029 (const_string "mffgpr")])
9030 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9032 (define_insn "*mov<mode>_softfloat64"
9033 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9034 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9035 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9036 && (gpc_reg_operand (operands[0], <MODE>mode)
9037 || gpc_reg_operand (operands[1], <MODE>mode))"
9038 "@
9039 std%U0%X0 %1,%0
9040 ld%U1%X1 %0,%1
9041 mr %0,%1
9042 mt%0 %1
9043 mf%1 %0
9044 #
9045 #
9046 #
9047 nop"
9048 [(set_attr_alternative "type"
9049 [(if_then_else
9050 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9051 (const_string "store_ux")
9052 (if_then_else
9053 (match_test "update_address_mem (operands[0], VOIDmode)")
9054 (const_string "store_u")
9055 (const_string "store")))
9056 (if_then_else
9057 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9058 (const_string "load_ux")
9059 (if_then_else
9060 (match_test "update_address_mem (operands[1], VOIDmode)")
9061 (const_string "load_u")
9062 (const_string "load")))
9063 (const_string "*")
9064 (const_string "mtjmpr")
9065 (const_string "mfjmpr")
9066 (const_string "*")
9067 (const_string "*")
9068 (const_string "*")
9069 (const_string "*")])
9070 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9071 \f
9072 (define_expand "mov<mode>"
9073 [(set (match_operand:FMOVE128 0 "general_operand" "")
9074 (match_operand:FMOVE128 1 "any_operand" ""))]
9075 ""
9076 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9078 ;; It's important to list Y->r and r->Y before r->r because otherwise
9079 ;; reload, given m->r, will try to pick r->r and reload it, which
9080 ;; doesn't make progress.
9081 (define_insn_and_split "*mov<mode>_internal"
9082 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9083 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9084 "TARGET_HARD_FLOAT && TARGET_FPRS
9085 && (gpc_reg_operand (operands[0], <MODE>mode)
9086 || gpc_reg_operand (operands[1], <MODE>mode))"
9087 "#"
9088 "&& reload_completed"
9089 [(pc)]
9090 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9091 [(set_attr "length" "8,8,8,20,20,16")])
9093 (define_insn_and_split "*mov<mode>_softfloat"
9094 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9095 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9096 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9097 && (gpc_reg_operand (operands[0], <MODE>mode)
9098 || gpc_reg_operand (operands[1], <MODE>mode))"
9099 "#"
9100 "&& reload_completed"
9101 [(pc)]
9102 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9103 [(set_attr "length" "20,20,16")])
9105 (define_expand "extenddftf2"
9106 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9107 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9108 "!TARGET_IEEEQUAD
9109 && TARGET_HARD_FLOAT
9110 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9111 && TARGET_LONG_DOUBLE_128"
9112 {
9113 if (TARGET_E500_DOUBLE)
9114 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9115 else
9116 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9117 DONE;
9118 })
9120 (define_expand "extenddftf2_fprs"
9121 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9122 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9123 (use (match_dup 2))])]
9124 "!TARGET_IEEEQUAD
9125 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9126 && TARGET_LONG_DOUBLE_128"
9127 {
9128 operands[2] = CONST0_RTX (DFmode);
9129 /* Generate GOT reference early for SVR4 PIC. */
9130 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9131 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9132 })
9134 (define_insn_and_split "*extenddftf2_internal"
9135 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9136 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9137 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9138 "!TARGET_IEEEQUAD
9139 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9140 && TARGET_LONG_DOUBLE_128"
9141 "#"
9142 "&& reload_completed"
9143 [(pc)]
9144 {
9145 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9146 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9147 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9148 operands[1]);
9149 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9150 operands[2]);
9151 DONE;
9152 })
9154 (define_expand "extendsftf2"
9155 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9156 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9157 "!TARGET_IEEEQUAD
9158 && TARGET_HARD_FLOAT
9159 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9160 && TARGET_LONG_DOUBLE_128"
9161 {
9162 rtx tmp = gen_reg_rtx (DFmode);
9163 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9164 emit_insn (gen_extenddftf2 (operands[0], tmp));
9165 DONE;
9166 })
9168 (define_expand "trunctfdf2"
9169 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9170 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9171 "!TARGET_IEEEQUAD
9172 && TARGET_HARD_FLOAT
9173 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9174 && TARGET_LONG_DOUBLE_128"
9175 "")
9177 (define_insn_and_split "trunctfdf2_internal1"
9178 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9179 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9180 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9181 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9182 "@
9183 #
9184 fmr %0,%1"
9185 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9186 [(const_int 0)]
9187 {
9188 emit_note (NOTE_INSN_DELETED);
9189 DONE;
9190 }
9191 [(set_attr "type" "fp")])
9193 (define_insn "trunctfdf2_internal2"
9194 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9195 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9196 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9197 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9198 && TARGET_LONG_DOUBLE_128"
9199 "fadd %0,%1,%L1"
9200 [(set_attr "type" "fp")
9201 (set_attr "fp_type" "fp_addsub_d")])
9203 (define_expand "trunctfsf2"
9204 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9205 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9206 "!TARGET_IEEEQUAD
9207 && TARGET_HARD_FLOAT
9208 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9209 && TARGET_LONG_DOUBLE_128"
9210 {
9211 if (TARGET_E500_DOUBLE)
9212 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9213 else
9214 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9215 DONE;
9216 })
9218 (define_insn_and_split "trunctfsf2_fprs"
9219 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9220 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9221 (clobber (match_scratch:DF 2 "=d"))]
9222 "!TARGET_IEEEQUAD
9223 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9224 && TARGET_LONG_DOUBLE_128"
9225 "#"
9226 "&& reload_completed"
9227 [(set (match_dup 2)
9228 (float_truncate:DF (match_dup 1)))
9229 (set (match_dup 0)
9230 (float_truncate:SF (match_dup 2)))]
9231 "")
9233 (define_expand "floatsitf2"
9234 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9235 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9236 "!TARGET_IEEEQUAD
9237 && TARGET_HARD_FLOAT
9238 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9239 && TARGET_LONG_DOUBLE_128"
9240 {
9241 rtx tmp = gen_reg_rtx (DFmode);
9242 expand_float (tmp, operands[1], false);
9243 emit_insn (gen_extenddftf2 (operands[0], tmp));
9244 DONE;
9245 })
9247 ; fadd, but rounding towards zero.
9248 ; This is probably not the optimal code sequence.
9249 (define_insn "fix_trunc_helper"
9250 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9251 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9252 UNSPEC_FIX_TRUNC_TF))
9253 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9254 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9255 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9256 [(set_attr "type" "fp")
9257 (set_attr "length" "20")])
9259 (define_expand "fix_trunctfsi2"
9260 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9261 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9262 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9263 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9264 {
9265 if (TARGET_E500_DOUBLE)
9266 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9267 else
9268 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9269 DONE;
9270 })
9272 (define_expand "fix_trunctfsi2_fprs"
9273 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9274 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9275 (clobber (match_dup 2))
9276 (clobber (match_dup 3))
9277 (clobber (match_dup 4))
9278 (clobber (match_dup 5))])]
9279 "!TARGET_IEEEQUAD
9280 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9281 {
9282 operands[2] = gen_reg_rtx (DFmode);
9283 operands[3] = gen_reg_rtx (DFmode);
9284 operands[4] = gen_reg_rtx (DImode);
9285 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9286 })
9288 (define_insn_and_split "*fix_trunctfsi2_internal"
9289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9290 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9291 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9292 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9293 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9294 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9295 "!TARGET_IEEEQUAD
9296 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9297 "#"
9298 ""
9299 [(pc)]
9300 {
9301 rtx lowword;
9302 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9304 gcc_assert (MEM_P (operands[5]));
9305 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9307 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9308 emit_move_insn (operands[5], operands[4]);
9309 emit_move_insn (operands[0], lowword);
9310 DONE;
9311 })
9313 (define_expand "negtf2"
9314 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9315 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9316 "!TARGET_IEEEQUAD
9317 && TARGET_HARD_FLOAT
9318 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9319 && TARGET_LONG_DOUBLE_128"
9320 "")
9322 (define_insn "negtf2_internal"
9323 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9324 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9325 "!TARGET_IEEEQUAD
9326 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9327 "*
9328 {
9329 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9330 return \"fneg %L0,%L1\;fneg %0,%1\";
9331 else
9332 return \"fneg %0,%1\;fneg %L0,%L1\";
9333 }"
9334 [(set_attr "type" "fp")
9335 (set_attr "length" "8")])
9337 (define_expand "abstf2"
9338 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9339 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9340 "!TARGET_IEEEQUAD
9341 && TARGET_HARD_FLOAT
9342 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9343 && TARGET_LONG_DOUBLE_128"
9344 "
9345 {
9346 rtx label = gen_label_rtx ();
9347 if (TARGET_E500_DOUBLE)
9348 {
9349 if (flag_finite_math_only && !flag_trapping_math)
9350 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9351 else
9352 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9353 }
9354 else
9355 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9356 emit_label (label);
9357 DONE;
9358 }")
9360 (define_expand "abstf2_internal"
9361 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9362 (match_operand:TF 1 "gpc_reg_operand" ""))
9363 (set (match_dup 3) (match_dup 5))
9364 (set (match_dup 5) (abs:DF (match_dup 5)))
9365 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9366 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9367 (label_ref (match_operand 2 "" ""))
9368 (pc)))
9369 (set (match_dup 6) (neg:DF (match_dup 6)))]
9370 "!TARGET_IEEEQUAD
9371 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9372 && TARGET_LONG_DOUBLE_128"
9373 "
9374 {
9375 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9376 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9377 operands[3] = gen_reg_rtx (DFmode);
9378 operands[4] = gen_reg_rtx (CCFPmode);
9379 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9380 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9381 }")
9382 \f
9383 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9384 ;; must have 3 arguments, and scratch register constraint must be a single
9385 ;; constraint.
9387 ;; Reload patterns to support gpr load/store with misaligned mem.
9388 ;; and multiple gpr load/store at offset >= 0xfffc
9389 (define_expand "reload_<mode>_store"
9390 [(parallel [(match_operand 0 "memory_operand" "=m")
9391 (match_operand 1 "gpc_reg_operand" "r")
9392 (match_operand:GPR 2 "register_operand" "=&b")])]
9393 ""
9394 {
9395 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9396 DONE;
9397 })
9399 (define_expand "reload_<mode>_load"
9400 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9401 (match_operand 1 "memory_operand" "m")
9402 (match_operand:GPR 2 "register_operand" "=b")])]
9403 ""
9404 {
9405 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9406 DONE;
9407 })
9409 \f
9410 ;; Next come the multi-word integer load and store and the load and store
9411 ;; multiple insns.
9413 ;; List r->r after r->Y, otherwise reload will try to reload a
9414 ;; non-offsettable address by using r->r which won't make progress.
9415 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9416 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9417 (define_insn "*movdi_internal32"
9418 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
9419 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
9420 "! TARGET_POWERPC64
9421 && (gpc_reg_operand (operands[0], DImode)
9422 || gpc_reg_operand (operands[1], DImode))"
9423 "@
9424 #
9425 #
9426 #
9427 stfd%U0%X0 %1,%0
9428 lfd%U1%X1 %0,%1
9429 fmr %0,%1
9430 #
9431 xxlxor %x0,%x0,%x0"
9432 [(set_attr_alternative "type"
9433 [(const_string "store")
9434 (const_string "load")
9435 (const_string "*")
9436 (if_then_else
9437 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9438 (const_string "fpstore_ux")
9439 (if_then_else
9440 (match_test "update_address_mem (operands[0], VOIDmode)")
9441 (const_string "fpstore_u")
9442 (const_string "fpstore")))
9443 (if_then_else
9444 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9445 (const_string "fpload_ux")
9446 (if_then_else
9447 (match_test "update_address_mem (operands[1], VOIDmode)")
9448 (const_string "fpload_u")
9449 (const_string "fpload")))
9450 (const_string "fp")
9451 (const_string "*")
9452 (const_string "vecsimple")])])
9454 (define_split
9455 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9456 (match_operand:DI 1 "const_int_operand" ""))]
9457 "! TARGET_POWERPC64 && reload_completed
9458 && gpr_or_gpr_p (operands[0], operands[1])"
9459 [(set (match_dup 2) (match_dup 4))
9460 (set (match_dup 3) (match_dup 1))]
9461 "
9462 {
9463 HOST_WIDE_INT value = INTVAL (operands[1]);
9464 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9465 DImode);
9466 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9467 DImode);
9468 operands[4] = GEN_INT (value >> 32);
9469 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9470 }")
9472 (define_split
9473 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9474 (match_operand:DIFD 1 "input_operand" ""))]
9475 "reload_completed && !TARGET_POWERPC64
9476 && gpr_or_gpr_p (operands[0], operands[1])"
9477 [(pc)]
9478 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9480 (define_insn "*movdi_internal64"
9481 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wa,?wa,r,*h,*h,?wa,r,?*wg")
9482 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wa,Z,wa,*h,r,0,O,*wg,r"))]
9483 "TARGET_POWERPC64
9484 && (gpc_reg_operand (operands[0], DImode)
9485 || gpc_reg_operand (operands[1], DImode))"
9486 "@
9487 std%U0%X0 %1,%0
9488 ld%U1%X1 %0,%1
9489 mr %0,%1
9490 li %0,%1
9491 lis %0,%v1
9492 #
9493 stfd%U0%X0 %1,%0
9494 lfd%U1%X1 %0,%1
9495 fmr %0,%1
9496 stxsd%U0x %x1,%y0
9497 lxsd%U1x %x0,%y1
9498 xxlor %x0,%x1,%x1
9499 mf%1 %0
9500 mt%0 %1
9501 nop
9502 xxlxor %x0,%x0,%x0
9503 mftgpr %0,%1
9504 mffgpr %0,%1"
9505 [(set_attr_alternative "type"
9506 [(if_then_else
9507 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9508 (const_string "store_ux")
9509 (if_then_else
9510 (match_test "update_address_mem (operands[0], VOIDmode)")
9511 (const_string "store_u")
9512 (const_string "store")))
9513 (if_then_else
9514 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9515 (const_string "load_ux")
9516 (if_then_else
9517 (match_test "update_address_mem (operands[1], VOIDmode)")
9518 (const_string "load_u")
9519 (const_string "load")))
9520 (const_string "*")
9521 (const_string "*")
9522 (const_string "*")
9523 (const_string "*")
9524 (if_then_else
9525 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9526 (const_string "fpstore_ux")
9527 (if_then_else
9528 (match_test "update_address_mem (operands[0], VOIDmode)")
9529 (const_string "fpstore_u")
9530 (const_string "fpstore")))
9531 (if_then_else
9532 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9533 (const_string "fpload_ux")
9534 (if_then_else
9535 (match_test "update_address_mem (operands[1], VOIDmode)")
9536 (const_string "fpload_u")
9537 (const_string "fpload")))
9538 (const_string "fp")
9539 (if_then_else
9540 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9541 (const_string "fpstore_ux")
9542 (const_string "fpstore"))
9543 (if_then_else
9544 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9545 (const_string "fpload_ux")
9546 (const_string "fpload"))
9547 (const_string "vecsimple")
9548 (const_string "mfjmpr")
9549 (const_string "mtjmpr")
9550 (const_string "*")
9551 (const_string "vecsimple")
9552 (const_string "mftgpr")
9553 (const_string "mffgpr")])
9554 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4")])
9556 ;; Generate all one-bits and clear left or right.
9557 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9558 (define_split
9559 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9560 (match_operand:DI 1 "mask64_operand" ""))]
9561 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9562 [(set (match_dup 0) (const_int -1))
9563 (set (match_dup 0)
9564 (and:DI (rotate:DI (match_dup 0)
9565 (const_int 0))
9566 (match_dup 1)))]
9567 "")
9569 ;; Split a load of a large constant into the appropriate five-instruction
9570 ;; sequence. Handle anything in a constant number of insns.
9571 ;; When non-easy constants can go in the TOC, this should use
9572 ;; easy_fp_constant predicate.
9573 (define_split
9574 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9575 (match_operand:DI 1 "const_int_operand" ""))]
9576 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9577 [(set (match_dup 0) (match_dup 2))
9578 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9579 "
9580 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9582 if (tem == operands[0])
9583 DONE;
9584 else
9585 FAIL;
9586 }")
9588 (define_split
9589 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9590 (match_operand:DI 1 "const_double_operand" ""))]
9591 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9592 [(set (match_dup 0) (match_dup 2))
9593 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9594 "
9595 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9597 if (tem == operands[0])
9598 DONE;
9599 else
9600 FAIL;
9601 }")
9602 \f
9603 ;; TImode/PTImode is similar, except that we usually want to compute the
9604 ;; address into a register and use lsi/stsi (the exception is during reload).
9606 (define_insn "*mov<mode>_string"
9607 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9608 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9609 "! TARGET_POWERPC64
9610 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9611 && (gpc_reg_operand (operands[0], <MODE>mode)
9612 || gpc_reg_operand (operands[1], <MODE>mode))"
9613 "*
9614 {
9615 switch (which_alternative)
9616 {
9617 default:
9618 gcc_unreachable ();
9619 case 0:
9620 if (TARGET_STRING)
9621 return \"stswi %1,%P0,16\";
9622 case 1:
9623 return \"#\";
9624 case 2:
9625 /* If the address is not used in the output, we can use lsi. Otherwise,
9626 fall through to generating four loads. */
9627 if (TARGET_STRING
9628 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9629 return \"lswi %0,%P1,16\";
9630 /* ... fall through ... */
9631 case 3:
9632 case 4:
9633 case 5:
9634 return \"#\";
9635 }
9636 }"
9637 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
9638 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9639 (const_string "always")
9640 (const_string "conditional")))])
9642 (define_insn "*mov<mode>_ppc64"
9643 [(set (match_operand:TI2 0 "nonimmediate_operand" "=Y,r,r")
9644 (match_operand:TI2 1 "input_operand" "r,Y,r"))]
9645 "(TARGET_POWERPC64
9646 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9647 && (gpc_reg_operand (operands[0], <MODE>mode)
9648 || gpc_reg_operand (operands[1], <MODE>mode)))"
9649 "#"
9650 [(set_attr "type" "store,load,*")])
9652 (define_split
9653 [(set (match_operand:TI2 0 "gpc_reg_operand" "")
9654 (match_operand:TI2 1 "const_double_operand" ""))]
9655 "TARGET_POWERPC64"
9656 [(set (match_dup 2) (match_dup 4))
9657 (set (match_dup 3) (match_dup 5))]
9658 "
9659 {
9660 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9661 <MODE>mode);
9662 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9663 <MODE>mode);
9664 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9665 {
9666 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9667 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9668 }
9669 else if (GET_CODE (operands[1]) == CONST_INT)
9670 {
9671 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9672 operands[5] = operands[1];
9673 }
9674 else
9675 FAIL;
9676 }")
9678 (define_split
9679 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
9680 (match_operand:TI2 1 "input_operand" ""))]
9681 "reload_completed
9682 && gpr_or_gpr_p (operands[0], operands[1])"
9683 [(pc)]
9684 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9685 \f
9686 (define_expand "load_multiple"
9687 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9688 (match_operand:SI 1 "" ""))
9689 (use (match_operand:SI 2 "" ""))])]
9690 "TARGET_STRING && !TARGET_POWERPC64"
9691 "
9692 {
9693 int regno;
9694 int count;
9695 rtx op1;
9696 int i;
9698 /* Support only loading a constant number of fixed-point registers from
9699 memory and only bother with this if more than two; the machine
9700 doesn't support more than eight. */
9701 if (GET_CODE (operands[2]) != CONST_INT
9702 || INTVAL (operands[2]) <= 2
9703 || INTVAL (operands[2]) > 8
9704 || GET_CODE (operands[1]) != MEM
9705 || GET_CODE (operands[0]) != REG
9706 || REGNO (operands[0]) >= 32)
9707 FAIL;
9709 count = INTVAL (operands[2]);
9710 regno = REGNO (operands[0]);
9712 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9713 op1 = replace_equiv_address (operands[1],
9714 force_reg (SImode, XEXP (operands[1], 0)));
9716 for (i = 0; i < count; i++)
9717 XVECEXP (operands[3], 0, i)
9718 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9719 adjust_address_nv (op1, SImode, i * 4));
9720 }")
9722 (define_insn "*ldmsi8"
9723 [(match_parallel 0 "load_multiple_operation"
9724 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9725 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9726 (set (match_operand:SI 3 "gpc_reg_operand" "")
9727 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9728 (set (match_operand:SI 4 "gpc_reg_operand" "")
9729 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9730 (set (match_operand:SI 5 "gpc_reg_operand" "")
9731 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9732 (set (match_operand:SI 6 "gpc_reg_operand" "")
9733 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9734 (set (match_operand:SI 7 "gpc_reg_operand" "")
9735 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9736 (set (match_operand:SI 8 "gpc_reg_operand" "")
9737 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9738 (set (match_operand:SI 9 "gpc_reg_operand" "")
9739 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9740 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9741 "*
9742 { return rs6000_output_load_multiple (operands); }"
9743 [(set_attr "type" "load_ux")
9744 (set_attr "length" "32")])
9746 (define_insn "*ldmsi7"
9747 [(match_parallel 0 "load_multiple_operation"
9748 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9749 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9750 (set (match_operand:SI 3 "gpc_reg_operand" "")
9751 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9752 (set (match_operand:SI 4 "gpc_reg_operand" "")
9753 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9754 (set (match_operand:SI 5 "gpc_reg_operand" "")
9755 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9756 (set (match_operand:SI 6 "gpc_reg_operand" "")
9757 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9758 (set (match_operand:SI 7 "gpc_reg_operand" "")
9759 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9760 (set (match_operand:SI 8 "gpc_reg_operand" "")
9761 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9762 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9763 "*
9764 { return rs6000_output_load_multiple (operands); }"
9765 [(set_attr "type" "load_ux")
9766 (set_attr "length" "32")])
9768 (define_insn "*ldmsi6"
9769 [(match_parallel 0 "load_multiple_operation"
9770 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9771 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9772 (set (match_operand:SI 3 "gpc_reg_operand" "")
9773 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9774 (set (match_operand:SI 4 "gpc_reg_operand" "")
9775 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9776 (set (match_operand:SI 5 "gpc_reg_operand" "")
9777 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9778 (set (match_operand:SI 6 "gpc_reg_operand" "")
9779 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9780 (set (match_operand:SI 7 "gpc_reg_operand" "")
9781 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9782 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9783 "*
9784 { return rs6000_output_load_multiple (operands); }"
9785 [(set_attr "type" "load_ux")
9786 (set_attr "length" "32")])
9788 (define_insn "*ldmsi5"
9789 [(match_parallel 0 "load_multiple_operation"
9790 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9791 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9792 (set (match_operand:SI 3 "gpc_reg_operand" "")
9793 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9794 (set (match_operand:SI 4 "gpc_reg_operand" "")
9795 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9796 (set (match_operand:SI 5 "gpc_reg_operand" "")
9797 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9798 (set (match_operand:SI 6 "gpc_reg_operand" "")
9799 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9800 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9801 "*
9802 { return rs6000_output_load_multiple (operands); }"
9803 [(set_attr "type" "load_ux")
9804 (set_attr "length" "32")])
9806 (define_insn "*ldmsi4"
9807 [(match_parallel 0 "load_multiple_operation"
9808 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9809 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9810 (set (match_operand:SI 3 "gpc_reg_operand" "")
9811 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9812 (set (match_operand:SI 4 "gpc_reg_operand" "")
9813 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9814 (set (match_operand:SI 5 "gpc_reg_operand" "")
9815 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9816 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9817 "*
9818 { return rs6000_output_load_multiple (operands); }"
9819 [(set_attr "type" "load_ux")
9820 (set_attr "length" "32")])
9822 (define_insn "*ldmsi3"
9823 [(match_parallel 0 "load_multiple_operation"
9824 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9825 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9826 (set (match_operand:SI 3 "gpc_reg_operand" "")
9827 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9828 (set (match_operand:SI 4 "gpc_reg_operand" "")
9829 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9830 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9831 "*
9832 { return rs6000_output_load_multiple (operands); }"
9833 [(set_attr "type" "load_ux")
9834 (set_attr "length" "32")])
9836 (define_expand "store_multiple"
9837 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9838 (match_operand:SI 1 "" ""))
9839 (clobber (scratch:SI))
9840 (use (match_operand:SI 2 "" ""))])]
9841 "TARGET_STRING && !TARGET_POWERPC64"
9842 "
9843 {
9844 int regno;
9845 int count;
9846 rtx to;
9847 rtx op0;
9848 int i;
9850 /* Support only storing a constant number of fixed-point registers to
9851 memory and only bother with this if more than two; the machine
9852 doesn't support more than eight. */
9853 if (GET_CODE (operands[2]) != CONST_INT
9854 || INTVAL (operands[2]) <= 2
9855 || INTVAL (operands[2]) > 8
9856 || GET_CODE (operands[0]) != MEM
9857 || GET_CODE (operands[1]) != REG
9858 || REGNO (operands[1]) >= 32)
9859 FAIL;
9861 count = INTVAL (operands[2]);
9862 regno = REGNO (operands[1]);
9864 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9865 to = force_reg (SImode, XEXP (operands[0], 0));
9866 op0 = replace_equiv_address (operands[0], to);
9868 XVECEXP (operands[3], 0, 0)
9869 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9870 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9871 gen_rtx_SCRATCH (SImode));
9873 for (i = 1; i < count; i++)
9874 XVECEXP (operands[3], 0, i + 1)
9875 = gen_rtx_SET (VOIDmode,
9876 adjust_address_nv (op0, SImode, i * 4),
9877 gen_rtx_REG (SImode, regno + i));
9878 }")
9880 (define_insn "*stmsi8"
9881 [(match_parallel 0 "store_multiple_operation"
9882 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9883 (match_operand:SI 2 "gpc_reg_operand" "r"))
9884 (clobber (match_scratch:SI 3 "=X"))
9885 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9886 (match_operand:SI 4 "gpc_reg_operand" "r"))
9887 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9888 (match_operand:SI 5 "gpc_reg_operand" "r"))
9889 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9890 (match_operand:SI 6 "gpc_reg_operand" "r"))
9891 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9892 (match_operand:SI 7 "gpc_reg_operand" "r"))
9893 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9894 (match_operand:SI 8 "gpc_reg_operand" "r"))
9895 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9896 (match_operand:SI 9 "gpc_reg_operand" "r"))
9897 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9898 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9899 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9900 "stswi %2,%1,%O0"
9901 [(set_attr "type" "store_ux")
9902 (set_attr "cell_micro" "always")])
9904 (define_insn "*stmsi7"
9905 [(match_parallel 0 "store_multiple_operation"
9906 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9907 (match_operand:SI 2 "gpc_reg_operand" "r"))
9908 (clobber (match_scratch:SI 3 "=X"))
9909 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9910 (match_operand:SI 4 "gpc_reg_operand" "r"))
9911 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9912 (match_operand:SI 5 "gpc_reg_operand" "r"))
9913 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9914 (match_operand:SI 6 "gpc_reg_operand" "r"))
9915 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9916 (match_operand:SI 7 "gpc_reg_operand" "r"))
9917 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9918 (match_operand:SI 8 "gpc_reg_operand" "r"))
9919 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9920 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9921 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9922 "stswi %2,%1,%O0"
9923 [(set_attr "type" "store_ux")
9924 (set_attr "cell_micro" "always")])
9926 (define_insn "*stmsi6"
9927 [(match_parallel 0 "store_multiple_operation"
9928 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9929 (match_operand:SI 2 "gpc_reg_operand" "r"))
9930 (clobber (match_scratch:SI 3 "=X"))
9931 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9932 (match_operand:SI 4 "gpc_reg_operand" "r"))
9933 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9934 (match_operand:SI 5 "gpc_reg_operand" "r"))
9935 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9936 (match_operand:SI 6 "gpc_reg_operand" "r"))
9937 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9938 (match_operand:SI 7 "gpc_reg_operand" "r"))
9939 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9940 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9941 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9942 "stswi %2,%1,%O0"
9943 [(set_attr "type" "store_ux")
9944 (set_attr "cell_micro" "always")])
9946 (define_insn "*stmsi5"
9947 [(match_parallel 0 "store_multiple_operation"
9948 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9949 (match_operand:SI 2 "gpc_reg_operand" "r"))
9950 (clobber (match_scratch:SI 3 "=X"))
9951 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9952 (match_operand:SI 4 "gpc_reg_operand" "r"))
9953 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9954 (match_operand:SI 5 "gpc_reg_operand" "r"))
9955 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9956 (match_operand:SI 6 "gpc_reg_operand" "r"))
9957 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9958 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9959 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9960 "stswi %2,%1,%O0"
9961 [(set_attr "type" "store_ux")
9962 (set_attr "cell_micro" "always")])
9964 (define_insn "*stmsi4"
9965 [(match_parallel 0 "store_multiple_operation"
9966 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9967 (match_operand:SI 2 "gpc_reg_operand" "r"))
9968 (clobber (match_scratch:SI 3 "=X"))
9969 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9970 (match_operand:SI 4 "gpc_reg_operand" "r"))
9971 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9972 (match_operand:SI 5 "gpc_reg_operand" "r"))
9973 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9974 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9975 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9976 "stswi %2,%1,%O0"
9977 [(set_attr "type" "store_ux")
9978 (set_attr "cell_micro" "always")])
9980 (define_insn "*stmsi3"
9981 [(match_parallel 0 "store_multiple_operation"
9982 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9983 (match_operand:SI 2 "gpc_reg_operand" "r"))
9984 (clobber (match_scratch:SI 3 "=X"))
9985 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9986 (match_operand:SI 4 "gpc_reg_operand" "r"))
9987 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9988 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9989 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9990 "stswi %2,%1,%O0"
9991 [(set_attr "type" "store_ux")
9992 (set_attr "cell_micro" "always")])
9993 \f
9994 (define_expand "setmemsi"
9995 [(parallel [(set (match_operand:BLK 0 "" "")
9996 (match_operand 2 "const_int_operand" ""))
9997 (use (match_operand:SI 1 "" ""))
9998 (use (match_operand:SI 3 "" ""))])]
9999 ""
10000 "
10001 {
10002 /* If value to set is not zero, use the library routine. */
10003 if (operands[2] != const0_rtx)
10004 FAIL;
10006 if (expand_block_clear (operands))
10007 DONE;
10008 else
10009 FAIL;
10010 }")
10012 ;; String/block move insn.
10013 ;; Argument 0 is the destination
10014 ;; Argument 1 is the source
10015 ;; Argument 2 is the length
10016 ;; Argument 3 is the alignment
10018 (define_expand "movmemsi"
10019 [(parallel [(set (match_operand:BLK 0 "" "")
10020 (match_operand:BLK 1 "" ""))
10021 (use (match_operand:SI 2 "" ""))
10022 (use (match_operand:SI 3 "" ""))])]
10023 ""
10024 "
10025 {
10026 if (expand_block_move (operands))
10027 DONE;
10028 else
10029 FAIL;
10030 }")
10032 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10033 ;; register allocator doesn't have a clue about allocating 8 word registers.
10034 ;; rD/rS = r5 is preferred, efficient form.
10035 (define_expand "movmemsi_8reg"
10036 [(parallel [(set (match_operand 0 "" "")
10037 (match_operand 1 "" ""))
10038 (use (match_operand 2 "" ""))
10039 (use (match_operand 3 "" ""))
10040 (clobber (reg:SI 5))
10041 (clobber (reg:SI 6))
10042 (clobber (reg:SI 7))
10043 (clobber (reg:SI 8))
10044 (clobber (reg:SI 9))
10045 (clobber (reg:SI 10))
10046 (clobber (reg:SI 11))
10047 (clobber (reg:SI 12))
10048 (clobber (match_scratch:SI 4 ""))])]
10049 "TARGET_STRING"
10050 "")
10052 (define_insn ""
10053 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10054 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10055 (use (match_operand:SI 2 "immediate_operand" "i"))
10056 (use (match_operand:SI 3 "immediate_operand" "i"))
10057 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10058 (clobber (reg:SI 6))
10059 (clobber (reg:SI 7))
10060 (clobber (reg:SI 8))
10061 (clobber (reg:SI 9))
10062 (clobber (reg:SI 10))
10063 (clobber (reg:SI 11))
10064 (clobber (reg:SI 12))
10065 (clobber (match_scratch:SI 5 "=X"))]
10066 "TARGET_STRING
10067 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10068 || INTVAL (operands[2]) == 0)
10069 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10070 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10071 && REGNO (operands[4]) == 5"
10072 "lswi %4,%1,%2\;stswi %4,%0,%2"
10073 [(set_attr "type" "store_ux")
10074 (set_attr "cell_micro" "always")
10075 (set_attr "length" "8")])
10077 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10078 ;; register allocator doesn't have a clue about allocating 6 word registers.
10079 ;; rD/rS = r5 is preferred, efficient form.
10080 (define_expand "movmemsi_6reg"
10081 [(parallel [(set (match_operand 0 "" "")
10082 (match_operand 1 "" ""))
10083 (use (match_operand 2 "" ""))
10084 (use (match_operand 3 "" ""))
10085 (clobber (reg:SI 5))
10086 (clobber (reg:SI 6))
10087 (clobber (reg:SI 7))
10088 (clobber (reg:SI 8))
10089 (clobber (reg:SI 9))
10090 (clobber (reg:SI 10))
10091 (clobber (match_scratch:SI 4 ""))])]
10092 "TARGET_STRING"
10093 "")
10095 (define_insn ""
10096 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10097 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10098 (use (match_operand:SI 2 "immediate_operand" "i"))
10099 (use (match_operand:SI 3 "immediate_operand" "i"))
10100 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10101 (clobber (reg:SI 6))
10102 (clobber (reg:SI 7))
10103 (clobber (reg:SI 8))
10104 (clobber (reg:SI 9))
10105 (clobber (reg:SI 10))
10106 (clobber (match_scratch:SI 5 "=X"))]
10107 "TARGET_STRING
10108 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10109 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10110 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10111 && REGNO (operands[4]) == 5"
10112 "lswi %4,%1,%2\;stswi %4,%0,%2"
10113 [(set_attr "type" "store_ux")
10114 (set_attr "cell_micro" "always")
10115 (set_attr "length" "8")])
10117 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10118 ;; problems with TImode.
10119 ;; rD/rS = r5 is preferred, efficient form.
10120 (define_expand "movmemsi_4reg"
10121 [(parallel [(set (match_operand 0 "" "")
10122 (match_operand 1 "" ""))
10123 (use (match_operand 2 "" ""))
10124 (use (match_operand 3 "" ""))
10125 (clobber (reg:SI 5))
10126 (clobber (reg:SI 6))
10127 (clobber (reg:SI 7))
10128 (clobber (reg:SI 8))
10129 (clobber (match_scratch:SI 4 ""))])]
10130 "TARGET_STRING"
10131 "")
10133 (define_insn ""
10134 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10135 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10136 (use (match_operand:SI 2 "immediate_operand" "i"))
10137 (use (match_operand:SI 3 "immediate_operand" "i"))
10138 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10139 (clobber (reg:SI 6))
10140 (clobber (reg:SI 7))
10141 (clobber (reg:SI 8))
10142 (clobber (match_scratch:SI 5 "=X"))]
10143 "TARGET_STRING
10144 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10145 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10146 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10147 && REGNO (operands[4]) == 5"
10148 "lswi %4,%1,%2\;stswi %4,%0,%2"
10149 [(set_attr "type" "store_ux")
10150 (set_attr "cell_micro" "always")
10151 (set_attr "length" "8")])
10153 ;; Move up to 8 bytes at a time.
10154 (define_expand "movmemsi_2reg"
10155 [(parallel [(set (match_operand 0 "" "")
10156 (match_operand 1 "" ""))
10157 (use (match_operand 2 "" ""))
10158 (use (match_operand 3 "" ""))
10159 (clobber (match_scratch:DI 4 ""))
10160 (clobber (match_scratch:SI 5 ""))])]
10161 "TARGET_STRING && ! TARGET_POWERPC64"
10162 "")
10164 (define_insn ""
10165 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10166 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10167 (use (match_operand:SI 2 "immediate_operand" "i"))
10168 (use (match_operand:SI 3 "immediate_operand" "i"))
10169 (clobber (match_scratch:DI 4 "=&r"))
10170 (clobber (match_scratch:SI 5 "=X"))]
10171 "TARGET_STRING && ! TARGET_POWERPC64
10172 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10173 "lswi %4,%1,%2\;stswi %4,%0,%2"
10174 [(set_attr "type" "store_ux")
10175 (set_attr "cell_micro" "always")
10176 (set_attr "length" "8")])
10178 ;; Move up to 4 bytes at a time.
10179 (define_expand "movmemsi_1reg"
10180 [(parallel [(set (match_operand 0 "" "")
10181 (match_operand 1 "" ""))
10182 (use (match_operand 2 "" ""))
10183 (use (match_operand 3 "" ""))
10184 (clobber (match_scratch:SI 4 ""))
10185 (clobber (match_scratch:SI 5 ""))])]
10186 "TARGET_STRING"
10187 "")
10189 (define_insn ""
10190 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10191 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10192 (use (match_operand:SI 2 "immediate_operand" "i"))
10193 (use (match_operand:SI 3 "immediate_operand" "i"))
10194 (clobber (match_scratch:SI 4 "=&r"))
10195 (clobber (match_scratch:SI 5 "=X"))]
10196 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10197 "lswi %4,%1,%2\;stswi %4,%0,%2"
10198 [(set_attr "type" "store_ux")
10199 (set_attr "cell_micro" "always")
10200 (set_attr "length" "8")])
10201 \f
10202 ;; Define insns that do load or store with update. Some of these we can
10203 ;; get by using pre-decrement or pre-increment, but the hardware can also
10204 ;; do cases where the increment is not the size of the object.
10205 ;;
10206 ;; In all these cases, we use operands 0 and 1 for the register being
10207 ;; incremented because those are the operands that local-alloc will
10208 ;; tie and these are the pair most likely to be tieable (and the ones
10209 ;; that will benefit the most).
10211 (define_insn "*movdi_update1"
10212 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10213 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10214 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10215 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10216 (plus:DI (match_dup 1) (match_dup 2)))]
10217 "TARGET_POWERPC64 && TARGET_UPDATE
10218 && (!avoiding_indexed_address_p (DImode)
10219 || !gpc_reg_operand (operands[2], DImode))"
10220 "@
10221 ldux %3,%0,%2
10222 ldu %3,%2(%0)"
10223 [(set_attr "type" "load_ux,load_u")])
10225 (define_insn "movdi_<mode>_update"
10226 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10227 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10228 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10229 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10230 (plus:P (match_dup 1) (match_dup 2)))]
10231 "TARGET_POWERPC64 && TARGET_UPDATE
10232 && (!avoiding_indexed_address_p (Pmode)
10233 || !gpc_reg_operand (operands[2], Pmode)
10234 || (REG_P (operands[0])
10235 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10236 "@
10237 stdux %3,%0,%2
10238 stdu %3,%2(%0)"
10239 [(set_attr "type" "store_ux,store_u")])
10241 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10242 ;; needed for stack allocation, even if the user passes -mno-update.
10243 (define_insn "movdi_<mode>_update_stack"
10244 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10245 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10246 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10247 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10248 (plus:P (match_dup 1) (match_dup 2)))]
10249 "TARGET_POWERPC64"
10250 "@
10251 stdux %3,%0,%2
10252 stdu %3,%2(%0)"
10253 [(set_attr "type" "store_ux,store_u")])
10255 (define_insn "*movsi_update1"
10256 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10257 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10258 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10259 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10260 (plus:SI (match_dup 1) (match_dup 2)))]
10261 "TARGET_UPDATE
10262 && (!avoiding_indexed_address_p (SImode)
10263 || !gpc_reg_operand (operands[2], SImode))"
10264 "@
10265 lwzux %3,%0,%2
10266 lwzu %3,%2(%0)"
10267 [(set_attr "type" "load_ux,load_u")])
10269 (define_insn "*movsi_update2"
10270 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10271 (sign_extend:DI
10272 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10273 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10274 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10275 (plus:DI (match_dup 1) (match_dup 2)))]
10276 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10277 && !avoiding_indexed_address_p (DImode)"
10278 "lwaux %3,%0,%2"
10279 [(set_attr "type" "load_ext_ux")])
10281 (define_insn "movsi_update"
10282 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10283 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10284 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10285 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10286 (plus:SI (match_dup 1) (match_dup 2)))]
10287 "TARGET_UPDATE
10288 && (!avoiding_indexed_address_p (SImode)
10289 || !gpc_reg_operand (operands[2], SImode)
10290 || (REG_P (operands[0])
10291 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10292 "@
10293 stwux %3,%0,%2
10294 stwu %3,%2(%0)"
10295 [(set_attr "type" "store_ux,store_u")])
10297 ;; This is an unconditional pattern; needed for stack allocation, even
10298 ;; if the user passes -mno-update.
10299 (define_insn "movsi_update_stack"
10300 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10301 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10302 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10303 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10304 (plus:SI (match_dup 1) (match_dup 2)))]
10305 ""
10306 "@
10307 stwux %3,%0,%2
10308 stwu %3,%2(%0)"
10309 [(set_attr "type" "store_ux,store_u")])
10311 (define_insn "*movhi_update1"
10312 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10313 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10314 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10315 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10316 (plus:SI (match_dup 1) (match_dup 2)))]
10317 "TARGET_UPDATE
10318 && (!avoiding_indexed_address_p (SImode)
10319 || !gpc_reg_operand (operands[2], SImode))"
10320 "@
10321 lhzux %3,%0,%2
10322 lhzu %3,%2(%0)"
10323 [(set_attr "type" "load_ux,load_u")])
10325 (define_insn "*movhi_update2"
10326 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10327 (zero_extend:SI
10328 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10329 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10330 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10331 (plus:SI (match_dup 1) (match_dup 2)))]
10332 "TARGET_UPDATE
10333 && (!avoiding_indexed_address_p (SImode)
10334 || !gpc_reg_operand (operands[2], SImode))"
10335 "@
10336 lhzux %3,%0,%2
10337 lhzu %3,%2(%0)"
10338 [(set_attr "type" "load_ux,load_u")])
10340 (define_insn "*movhi_update3"
10341 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10342 (sign_extend:SI
10343 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10344 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10345 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10346 (plus:SI (match_dup 1) (match_dup 2)))]
10347 "TARGET_UPDATE && rs6000_gen_cell_microcode
10348 && (!avoiding_indexed_address_p (SImode)
10349 || !gpc_reg_operand (operands[2], SImode))"
10350 "@
10351 lhaux %3,%0,%2
10352 lhau %3,%2(%0)"
10353 [(set_attr "type" "load_ext_ux,load_ext_u")])
10355 (define_insn "*movhi_update4"
10356 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10357 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10358 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10359 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10360 (plus:SI (match_dup 1) (match_dup 2)))]
10361 "TARGET_UPDATE
10362 && (!avoiding_indexed_address_p (SImode)
10363 || !gpc_reg_operand (operands[2], SImode))"
10364 "@
10365 sthux %3,%0,%2
10366 sthu %3,%2(%0)"
10367 [(set_attr "type" "store_ux,store_u")])
10369 (define_insn "*movqi_update1"
10370 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10371 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10372 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10373 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10374 (plus:SI (match_dup 1) (match_dup 2)))]
10375 "TARGET_UPDATE
10376 && (!avoiding_indexed_address_p (SImode)
10377 || !gpc_reg_operand (operands[2], SImode))"
10378 "@
10379 lbzux %3,%0,%2
10380 lbzu %3,%2(%0)"
10381 [(set_attr "type" "load_ux,load_u")])
10383 (define_insn "*movqi_update2"
10384 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10385 (zero_extend:SI
10386 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10387 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10388 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10389 (plus:SI (match_dup 1) (match_dup 2)))]
10390 "TARGET_UPDATE
10391 && (!avoiding_indexed_address_p (SImode)
10392 || !gpc_reg_operand (operands[2], SImode))"
10393 "@
10394 lbzux %3,%0,%2
10395 lbzu %3,%2(%0)"
10396 [(set_attr "type" "load_ux,load_u")])
10398 (define_insn "*movqi_update3"
10399 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10400 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10401 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10402 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10403 (plus:SI (match_dup 1) (match_dup 2)))]
10404 "TARGET_UPDATE
10405 && (!avoiding_indexed_address_p (SImode)
10406 || !gpc_reg_operand (operands[2], SImode))"
10407 "@
10408 stbux %3,%0,%2
10409 stbu %3,%2(%0)"
10410 [(set_attr "type" "store_ux,store_u")])
10412 (define_insn "*movsf_update1"
10413 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10414 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10415 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10416 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10417 (plus:SI (match_dup 1) (match_dup 2)))]
10418 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10419 && (!avoiding_indexed_address_p (SImode)
10420 || !gpc_reg_operand (operands[2], SImode))"
10421 "@
10422 lfsux %3,%0,%2
10423 lfsu %3,%2(%0)"
10424 [(set_attr "type" "fpload_ux,fpload_u")])
10426 (define_insn "*movsf_update2"
10427 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10428 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10429 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10430 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10431 (plus:SI (match_dup 1) (match_dup 2)))]
10432 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10433 && (!avoiding_indexed_address_p (SImode)
10434 || !gpc_reg_operand (operands[2], SImode))"
10435 "@
10436 stfsux %3,%0,%2
10437 stfsu %3,%2(%0)"
10438 [(set_attr "type" "fpstore_ux,fpstore_u")])
10440 (define_insn "*movsf_update3"
10441 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10442 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10443 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10444 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10445 (plus:SI (match_dup 1) (match_dup 2)))]
10446 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10447 && (!avoiding_indexed_address_p (SImode)
10448 || !gpc_reg_operand (operands[2], SImode))"
10449 "@
10450 lwzux %3,%0,%2
10451 lwzu %3,%2(%0)"
10452 [(set_attr "type" "load_ux,load_u")])
10454 (define_insn "*movsf_update4"
10455 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10456 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10457 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10458 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10459 (plus:SI (match_dup 1) (match_dup 2)))]
10460 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10461 && (!avoiding_indexed_address_p (SImode)
10462 || !gpc_reg_operand (operands[2], SImode))"
10463 "@
10464 stwux %3,%0,%2
10465 stwu %3,%2(%0)"
10466 [(set_attr "type" "store_ux,store_u")])
10468 (define_insn "*movdf_update1"
10469 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10470 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10471 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10472 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10473 (plus:SI (match_dup 1) (match_dup 2)))]
10474 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10475 && (!avoiding_indexed_address_p (SImode)
10476 || !gpc_reg_operand (operands[2], SImode))"
10477 "@
10478 lfdux %3,%0,%2
10479 lfdu %3,%2(%0)"
10480 [(set_attr "type" "fpload_ux,fpload_u")])
10482 (define_insn "*movdf_update2"
10483 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10484 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10485 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10486 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10487 (plus:SI (match_dup 1) (match_dup 2)))]
10488 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10489 && (!avoiding_indexed_address_p (SImode)
10490 || !gpc_reg_operand (operands[2], SImode))"
10491 "@
10492 stfdux %3,%0,%2
10493 stfdu %3,%2(%0)"
10494 [(set_attr "type" "fpstore_ux,fpstore_u")])
10497 ;; After inserting conditional returns we can sometimes have
10498 ;; unnecessary register moves. Unfortunately we cannot have a
10499 ;; modeless peephole here, because some single SImode sets have early
10500 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10501 ;; sequences, using get_attr_length here will smash the operands
10502 ;; array. Neither is there an early_cobbler_p predicate.
10503 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10504 (define_peephole2
10505 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10506 (match_operand:DF 1 "any_operand" ""))
10507 (set (match_operand:DF 2 "gpc_reg_operand" "")
10508 (match_dup 0))]
10509 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10510 && peep2_reg_dead_p (2, operands[0])"
10511 [(set (match_dup 2) (match_dup 1))])
10513 (define_peephole2
10514 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10515 (match_operand:SF 1 "any_operand" ""))
10516 (set (match_operand:SF 2 "gpc_reg_operand" "")
10517 (match_dup 0))]
10518 "peep2_reg_dead_p (2, operands[0])"
10519 [(set (match_dup 2) (match_dup 1))])
10521 \f
10522 ;; TLS support.
10524 ;; Mode attributes for different ABIs.
10525 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10526 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10527 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10528 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10530 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10531 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10532 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10533 (match_operand 4 "" "g")))
10534 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10535 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10536 UNSPEC_TLSGD)
10537 (clobber (reg:SI LR_REGNO))]
10538 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10539 {
10540 if (TARGET_CMODEL != CMODEL_SMALL)
10541 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10542 "bl %z3\;nop";
10543 else
10544 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10545 }
10546 "&& TARGET_TLS_MARKERS"
10547 [(set (match_dup 0)
10548 (unspec:TLSmode [(match_dup 1)
10549 (match_dup 2)]
10550 UNSPEC_TLSGD))
10551 (parallel [(set (match_dup 0)
10552 (call (mem:TLSmode (match_dup 3))
10553 (match_dup 4)))
10554 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10555 (clobber (reg:SI LR_REGNO))])]
10556 ""
10557 [(set_attr "type" "two")
10558 (set (attr "length")
10559 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10560 (const_int 16)
10561 (const_int 12)))])
10563 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10564 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10565 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10566 (match_operand 4 "" "g")))
10567 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10568 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10569 UNSPEC_TLSGD)
10570 (clobber (reg:SI LR_REGNO))]
10571 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10572 {
10573 if (flag_pic)
10574 {
10575 if (TARGET_SECURE_PLT && flag_pic == 2)
10576 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10577 else
10578 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10579 }
10580 else
10581 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10582 }
10583 "&& TARGET_TLS_MARKERS"
10584 [(set (match_dup 0)
10585 (unspec:TLSmode [(match_dup 1)
10586 (match_dup 2)]
10587 UNSPEC_TLSGD))
10588 (parallel [(set (match_dup 0)
10589 (call (mem:TLSmode (match_dup 3))
10590 (match_dup 4)))
10591 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10592 (clobber (reg:SI LR_REGNO))])]
10593 ""
10594 [(set_attr "type" "two")
10595 (set_attr "length" "8")])
10597 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10598 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10599 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10600 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10601 UNSPEC_TLSGD))]
10602 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10603 "addi %0,%1,%2@got@tlsgd"
10604 "&& TARGET_CMODEL != CMODEL_SMALL"
10605 [(set (match_dup 3)
10606 (high:TLSmode
10607 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10608 (set (match_dup 0)
10609 (lo_sum:TLSmode (match_dup 3)
10610 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
10611 "
10612 {
10613 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10614 }"
10615 [(set (attr "length")
10616 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10617 (const_int 8)
10618 (const_int 4)))])
10620 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10621 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10622 (high:TLSmode
10623 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10624 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10625 UNSPEC_TLSGD)))]
10626 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10627 "addis %0,%1,%2@got@tlsgd@ha"
10628 [(set_attr "length" "4")])
10630 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10631 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10632 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10633 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10634 UNSPEC_TLSGD)))]
10635 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10636 "addi %0,%1,%2@got@tlsgd@l"
10637 [(set_attr "length" "4")])
10639 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10640 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10641 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10642 (match_operand 2 "" "g")))
10643 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10644 UNSPEC_TLSGD)
10645 (clobber (reg:SI LR_REGNO))]
10646 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10647 "bl %z1(%3@tlsgd)\;nop"
10648 [(set_attr "type" "branch")
10649 (set_attr "length" "8")])
10651 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10652 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10653 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10654 (match_operand 2 "" "g")))
10655 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10656 UNSPEC_TLSGD)
10657 (clobber (reg:SI LR_REGNO))]
10658 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10659 {
10660 if (flag_pic)
10661 {
10662 if (TARGET_SECURE_PLT && flag_pic == 2)
10663 return "bl %z1+32768(%3@tlsgd)@plt";
10664 return "bl %z1(%3@tlsgd)@plt";
10665 }
10666 return "bl %z1(%3@tlsgd)";
10667 }
10668 [(set_attr "type" "branch")
10669 (set_attr "length" "4")])
10671 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10672 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10673 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10674 (match_operand 3 "" "g")))
10675 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10676 UNSPEC_TLSLD)
10677 (clobber (reg:SI LR_REGNO))]
10678 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10679 {
10680 if (TARGET_CMODEL != CMODEL_SMALL)
10681 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10682 "bl %z2\;nop";
10683 else
10684 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10685 }
10686 "&& TARGET_TLS_MARKERS"
10687 [(set (match_dup 0)
10688 (unspec:TLSmode [(match_dup 1)]
10689 UNSPEC_TLSLD))
10690 (parallel [(set (match_dup 0)
10691 (call (mem:TLSmode (match_dup 2))
10692 (match_dup 3)))
10693 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10694 (clobber (reg:SI LR_REGNO))])]
10695 ""
10696 [(set_attr "type" "two")
10697 (set (attr "length")
10698 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10699 (const_int 16)
10700 (const_int 12)))])
10702 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10703 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10704 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10705 (match_operand 3 "" "g")))
10706 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10707 UNSPEC_TLSLD)
10708 (clobber (reg:SI LR_REGNO))]
10709 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10710 {
10711 if (flag_pic)
10712 {
10713 if (TARGET_SECURE_PLT && flag_pic == 2)
10714 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10715 else
10716 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10717 }
10718 else
10719 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10720 }
10721 "&& TARGET_TLS_MARKERS"
10722 [(set (match_dup 0)
10723 (unspec:TLSmode [(match_dup 1)]
10724 UNSPEC_TLSLD))
10725 (parallel [(set (match_dup 0)
10726 (call (mem:TLSmode (match_dup 2))
10727 (match_dup 3)))
10728 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10729 (clobber (reg:SI LR_REGNO))])]
10730 ""
10731 [(set_attr "length" "8")])
10733 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10734 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10735 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10736 UNSPEC_TLSLD))]
10737 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10738 "addi %0,%1,%&@got@tlsld"
10739 "&& TARGET_CMODEL != CMODEL_SMALL"
10740 [(set (match_dup 2)
10741 (high:TLSmode
10742 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10743 (set (match_dup 0)
10744 (lo_sum:TLSmode (match_dup 2)
10745 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
10746 "
10747 {
10748 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10749 }"
10750 [(set (attr "length")
10751 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10752 (const_int 8)
10753 (const_int 4)))])
10755 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10756 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10757 (high:TLSmode
10758 (unspec:TLSmode [(const_int 0)
10759 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10760 UNSPEC_TLSLD)))]
10761 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10762 "addis %0,%1,%&@got@tlsld@ha"
10763 [(set_attr "length" "4")])
10765 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10766 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10767 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10768 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
10769 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10770 "addi %0,%1,%&@got@tlsld@l"
10771 [(set_attr "length" "4")])
10773 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10774 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10775 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10776 (match_operand 2 "" "g")))
10777 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10778 (clobber (reg:SI LR_REGNO))]
10779 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10780 "bl %z1(%&@tlsld)\;nop"
10781 [(set_attr "type" "branch")
10782 (set_attr "length" "8")])
10784 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10785 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10786 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10787 (match_operand 2 "" "g")))
10788 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10789 (clobber (reg:SI LR_REGNO))]
10790 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10791 {
10792 if (flag_pic)
10793 {
10794 if (TARGET_SECURE_PLT && flag_pic == 2)
10795 return "bl %z1+32768(%&@tlsld)@plt";
10796 return "bl %z1(%&@tlsld)@plt";
10797 }
10798 return "bl %z1(%&@tlsld)";
10799 }
10800 [(set_attr "type" "branch")
10801 (set_attr "length" "4")])
10803 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10804 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10805 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10806 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10807 UNSPEC_TLSDTPREL))]
10808 "HAVE_AS_TLS"
10809 "addi %0,%1,%2@dtprel")
10811 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10812 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10813 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10814 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10815 UNSPEC_TLSDTPRELHA))]
10816 "HAVE_AS_TLS"
10817 "addis %0,%1,%2@dtprel@ha")
10819 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10820 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10821 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10822 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10823 UNSPEC_TLSDTPRELLO))]
10824 "HAVE_AS_TLS"
10825 "addi %0,%1,%2@dtprel@l")
10827 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10828 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10829 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10830 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10831 UNSPEC_TLSGOTDTPREL))]
10832 "HAVE_AS_TLS"
10833 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10834 "&& TARGET_CMODEL != CMODEL_SMALL"
10835 [(set (match_dup 3)
10836 (high:TLSmode
10837 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10838 (set (match_dup 0)
10839 (lo_sum:TLSmode (match_dup 3)
10840 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10841 "
10842 {
10843 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10844 }"
10845 [(set (attr "length")
10846 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10847 (const_int 8)
10848 (const_int 4)))])
10850 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10851 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10852 (high:TLSmode
10853 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10854 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10855 UNSPEC_TLSGOTDTPREL)))]
10856 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10857 "addis %0,%1,%2@got@dtprel@ha"
10858 [(set_attr "length" "4")])
10860 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10861 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10862 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10863 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10864 UNSPEC_TLSGOTDTPREL)))]
10865 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10866 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10867 [(set_attr "length" "4")])
10869 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10870 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10871 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10872 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10873 UNSPEC_TLSTPREL))]
10874 "HAVE_AS_TLS"
10875 "addi %0,%1,%2@tprel")
10877 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10878 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10879 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10880 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10881 UNSPEC_TLSTPRELHA))]
10882 "HAVE_AS_TLS"
10883 "addis %0,%1,%2@tprel@ha")
10885 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10886 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10887 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10888 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10889 UNSPEC_TLSTPRELLO))]
10890 "HAVE_AS_TLS"
10891 "addi %0,%1,%2@tprel@l")
10893 ;; "b" output constraint here and on tls_tls input to support linker tls
10894 ;; optimization. The linker may edit the instructions emitted by a
10895 ;; tls_got_tprel/tls_tls pair to addis,addi.
10896 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10897 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10898 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10899 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10900 UNSPEC_TLSGOTTPREL))]
10901 "HAVE_AS_TLS"
10902 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10903 "&& TARGET_CMODEL != CMODEL_SMALL"
10904 [(set (match_dup 3)
10905 (high:TLSmode
10906 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10907 (set (match_dup 0)
10908 (lo_sum:TLSmode (match_dup 3)
10909 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10910 "
10911 {
10912 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10913 }"
10914 [(set (attr "length")
10915 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10916 (const_int 8)
10917 (const_int 4)))])
10919 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10920 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10921 (high:TLSmode
10922 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10923 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10924 UNSPEC_TLSGOTTPREL)))]
10925 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10926 "addis %0,%1,%2@got@tprel@ha"
10927 [(set_attr "length" "4")])
10929 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10930 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10931 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10932 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10933 UNSPEC_TLSGOTTPREL)))]
10934 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10935 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10936 [(set_attr "length" "4")])
10938 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10939 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10940 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10941 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10942 UNSPEC_TLSTLS))]
10943 "TARGET_ELF && HAVE_AS_TLS"
10944 "add %0,%1,%2@tls")
10946 (define_expand "tls_get_tpointer"
10947 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10948 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10949 "TARGET_XCOFF && HAVE_AS_TLS"
10950 "
10951 {
10952 emit_insn (gen_tls_get_tpointer_internal ());
10953 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10954 DONE;
10955 }")
10957 (define_insn "tls_get_tpointer_internal"
10958 [(set (reg:SI 3)
10959 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10960 (clobber (reg:SI LR_REGNO))]
10961 "TARGET_XCOFF && HAVE_AS_TLS"
10962 "bla __get_tpointer")
10964 (define_expand "tls_get_addr<mode>"
10965 [(set (match_operand:P 0 "gpc_reg_operand" "")
10966 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10967 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10968 "TARGET_XCOFF && HAVE_AS_TLS"
10969 "
10970 {
10971 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10972 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10973 emit_insn (gen_tls_get_addr_internal<mode> ());
10974 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10975 DONE;
10976 }")
10978 (define_insn "tls_get_addr_internal<mode>"
10979 [(set (reg:P 3)
10980 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10981 (clobber (reg:P 0))
10982 (clobber (reg:P 4))
10983 (clobber (reg:P 5))
10984 (clobber (reg:P 11))
10985 (clobber (reg:CC CR0_REGNO))
10986 (clobber (reg:P LR_REGNO))]
10987 "TARGET_XCOFF && HAVE_AS_TLS"
10988 "bla __tls_get_addr")
10989 \f
10990 ;; Next come insns related to the calling sequence.
10991 ;;
10992 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10993 ;; We move the back-chain and decrement the stack pointer.
10995 (define_expand "allocate_stack"
10996 [(set (match_operand 0 "gpc_reg_operand" "")
10997 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10998 (set (reg 1)
10999 (minus (reg 1) (match_dup 1)))]
11000 ""
11001 "
11002 { rtx chain = gen_reg_rtx (Pmode);
11003 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11004 rtx neg_op0;
11005 rtx insn, par, set, mem;
11007 emit_move_insn (chain, stack_bot);
11009 /* Check stack bounds if necessary. */
11010 if (crtl->limit_stack)
11011 {
11012 rtx available;
11013 available = expand_binop (Pmode, sub_optab,
11014 stack_pointer_rtx, stack_limit_rtx,
11015 NULL_RTX, 1, OPTAB_WIDEN);
11016 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11017 }
11019 if (GET_CODE (operands[1]) != CONST_INT
11020 || INTVAL (operands[1]) < -32767
11021 || INTVAL (operands[1]) > 32768)
11022 {
11023 neg_op0 = gen_reg_rtx (Pmode);
11024 if (TARGET_32BIT)
11025 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11026 else
11027 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11028 }
11029 else
11030 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11032 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11033 : gen_movdi_di_update_stack))
11034 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11035 chain));
11036 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11037 it now and set the alias set/attributes. The above gen_*_update
11038 calls will generate a PARALLEL with the MEM set being the first
11039 operation. */
11040 par = PATTERN (insn);
11041 gcc_assert (GET_CODE (par) == PARALLEL);
11042 set = XVECEXP (par, 0, 0);
11043 gcc_assert (GET_CODE (set) == SET);
11044 mem = SET_DEST (set);
11045 gcc_assert (MEM_P (mem));
11046 MEM_NOTRAP_P (mem) = 1;
11047 set_mem_alias_set (mem, get_frame_alias_set ());
11049 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11050 DONE;
11051 }")
11053 ;; These patterns say how to save and restore the stack pointer. We need not
11054 ;; save the stack pointer at function level since we are careful to
11055 ;; preserve the backchain. At block level, we have to restore the backchain
11056 ;; when we restore the stack pointer.
11057 ;;
11058 ;; For nonlocal gotos, we must save both the stack pointer and its
11059 ;; backchain and restore both. Note that in the nonlocal case, the
11060 ;; save area is a memory location.
11062 (define_expand "save_stack_function"
11063 [(match_operand 0 "any_operand" "")
11064 (match_operand 1 "any_operand" "")]
11065 ""
11066 "DONE;")
11068 (define_expand "restore_stack_function"
11069 [(match_operand 0 "any_operand" "")
11070 (match_operand 1 "any_operand" "")]
11071 ""
11072 "DONE;")
11074 ;; Adjust stack pointer (op0) to a new value (op1).
11075 ;; First copy old stack backchain to new location, and ensure that the
11076 ;; scheduler won't reorder the sp assignment before the backchain write.
11077 (define_expand "restore_stack_block"
11078 [(set (match_dup 2) (match_dup 3))
11079 (set (match_dup 4) (match_dup 2))
11080 (match_dup 5)
11081 (set (match_operand 0 "register_operand" "")
11082 (match_operand 1 "register_operand" ""))]
11083 ""
11084 "
11085 {
11086 rtvec p;
11088 operands[1] = force_reg (Pmode, operands[1]);
11089 operands[2] = gen_reg_rtx (Pmode);
11090 operands[3] = gen_frame_mem (Pmode, operands[0]);
11091 operands[4] = gen_frame_mem (Pmode, operands[1]);
11092 p = rtvec_alloc (1);
11093 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11094 gen_frame_mem (BLKmode, operands[0]),
11095 const0_rtx);
11096 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11097 }")
11099 (define_expand "save_stack_nonlocal"
11100 [(set (match_dup 3) (match_dup 4))
11101 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11102 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11103 ""
11104 "
11105 {
11106 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11108 /* Copy the backchain to the first word, sp to the second. */
11109 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11110 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11111 operands[3] = gen_reg_rtx (Pmode);
11112 operands[4] = gen_frame_mem (Pmode, operands[1]);
11113 }")
11115 (define_expand "restore_stack_nonlocal"
11116 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11117 (set (match_dup 3) (match_dup 4))
11118 (set (match_dup 5) (match_dup 2))
11119 (match_dup 6)
11120 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11121 ""
11122 "
11123 {
11124 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11125 rtvec p;
11127 /* Restore the backchain from the first word, sp from the second. */
11128 operands[2] = gen_reg_rtx (Pmode);
11129 operands[3] = gen_reg_rtx (Pmode);
11130 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11131 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11132 operands[5] = gen_frame_mem (Pmode, operands[3]);
11133 p = rtvec_alloc (1);
11134 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11135 gen_frame_mem (BLKmode, operands[0]),
11136 const0_rtx);
11137 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11138 }")
11139 \f
11140 ;; TOC register handling.
11142 ;; Code to initialize the TOC register...
11144 (define_insn "load_toc_aix_si"
11145 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11146 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11147 (use (reg:SI 2))])]
11148 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11149 "*
11150 {
11151 char buf[30];
11152 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11153 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11154 operands[2] = gen_rtx_REG (Pmode, 2);
11155 return \"lwz %0,%1(%2)\";
11156 }"
11157 [(set_attr "type" "load")])
11159 (define_insn "load_toc_aix_di"
11160 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11161 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11162 (use (reg:DI 2))])]
11163 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11164 "*
11165 {
11166 char buf[30];
11167 #ifdef TARGET_RELOCATABLE
11168 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11169 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11170 #else
11171 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11172 #endif
11173 if (TARGET_ELF)
11174 strcat (buf, \"@toc\");
11175 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11176 operands[2] = gen_rtx_REG (Pmode, 2);
11177 return \"ld %0,%1(%2)\";
11178 }"
11179 [(set_attr "type" "load")])
11181 (define_insn "load_toc_v4_pic_si"
11182 [(set (reg:SI LR_REGNO)
11183 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11184 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11185 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11186 [(set_attr "type" "branch")
11187 (set_attr "length" "4")])
11189 (define_expand "load_toc_v4_PIC_1"
11190 [(parallel [(set (reg:SI LR_REGNO)
11191 (match_operand:SI 0 "immediate_operand" "s"))
11192 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11193 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11194 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11195 "")
11197 (define_insn "load_toc_v4_PIC_1_normal"
11198 [(set (reg:SI LR_REGNO)
11199 (match_operand:SI 0 "immediate_operand" "s"))
11200 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11201 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
11202 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11203 "bcl 20,31,%0\\n%0:"
11204 [(set_attr "type" "branch")
11205 (set_attr "length" "4")])
11207 (define_insn "load_toc_v4_PIC_1_476"
11208 [(set (reg:SI LR_REGNO)
11209 (match_operand:SI 0 "immediate_operand" "s"))
11210 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11211 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
11212 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11213 "*
11214 {
11215 char name[32];
11216 static char templ[32];
11218 get_ppc476_thunk_name (name);
11219 sprintf (templ, \"bl %s\\n%%0:\", name);
11220 return templ;
11221 }"
11222 [(set_attr "type" "branch")
11223 (set_attr "length" "4")])
11225 (define_expand "load_toc_v4_PIC_1b"
11226 [(parallel [(set (reg:SI LR_REGNO)
11227 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11228 (label_ref (match_operand 1 "" ""))]
11229 UNSPEC_TOCPTR))
11230 (match_dup 1)])]
11231 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11232 "")
11234 (define_insn "load_toc_v4_PIC_1b_normal"
11235 [(set (reg:SI LR_REGNO)
11236 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11237 (label_ref (match_operand 1 "" ""))]
11238 UNSPEC_TOCPTR))
11239 (match_dup 1)]
11240 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11241 "bcl 20,31,$+8\;.long %0-$"
11242 [(set_attr "type" "branch")
11243 (set_attr "length" "8")])
11245 (define_insn "load_toc_v4_PIC_1b_476"
11246 [(set (reg:SI LR_REGNO)
11247 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11248 (label_ref (match_operand 1 "" ""))]
11249 UNSPEC_TOCPTR))
11250 (match_dup 1)]
11251 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11252 "*
11253 {
11254 char name[32];
11255 static char templ[32];
11257 get_ppc476_thunk_name (name);
11258 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11259 return templ;
11260 }"
11261 [(set_attr "type" "branch")
11262 (set_attr "length" "16")])
11264 (define_insn "load_toc_v4_PIC_2"
11265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11266 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11267 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11268 (match_operand:SI 3 "immediate_operand" "s")))))]
11269 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11270 "lwz %0,%2-%3(%1)"
11271 [(set_attr "type" "load")])
11273 (define_insn "load_toc_v4_PIC_3b"
11274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11275 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11276 (high:SI
11277 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11278 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11279 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11280 "addis %0,%1,%2-%3@ha")
11282 (define_insn "load_toc_v4_PIC_3c"
11283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11284 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11285 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11286 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11287 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11288 "addi %0,%1,%2-%3@l")
11290 ;; If the TOC is shared over a translation unit, as happens with all
11291 ;; the kinds of PIC that we support, we need to restore the TOC
11292 ;; pointer only when jumping over units of translation.
11293 ;; On Darwin, we need to reload the picbase.
11295 (define_expand "builtin_setjmp_receiver"
11296 [(use (label_ref (match_operand 0 "" "")))]
11297 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11298 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11299 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11300 "
11301 {
11302 #if TARGET_MACHO
11303 if (DEFAULT_ABI == ABI_DARWIN)
11304 {
11305 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11306 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11307 rtx tmplabrtx;
11308 char tmplab[20];
11310 crtl->uses_pic_offset_table = 1;
11311 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11312 CODE_LABEL_NUMBER (operands[0]));
11313 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11315 emit_insn (gen_load_macho_picbase (tmplabrtx));
11316 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11317 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11318 }
11319 else
11320 #endif
11321 rs6000_emit_load_toc_table (FALSE);
11322 DONE;
11323 }")
11325 ;; Largetoc support
11326 (define_insn "*largetoc_high"
11327 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11328 (high:DI
11329 (unspec [(match_operand:DI 1 "" "")
11330 (match_operand:DI 2 "gpc_reg_operand" "b")]
11331 UNSPEC_TOCREL)))]
11332 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11333 "addis %0,%2,%1@toc@ha")
11335 (define_insn "*largetoc_high_aix<mode>"
11336 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11337 (high:P
11338 (unspec [(match_operand:P 1 "" "")
11339 (match_operand:P 2 "gpc_reg_operand" "b")]
11340 UNSPEC_TOCREL)))]
11341 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11342 "addis %0,%1@u(%2)")
11344 (define_insn "*largetoc_high_plus"
11345 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11346 (high:DI
11347 (plus:DI
11348 (unspec [(match_operand:DI 1 "" "")
11349 (match_operand:DI 2 "gpc_reg_operand" "b")]
11350 UNSPEC_TOCREL)
11351 (match_operand 3 "const_int_operand" "n"))))]
11352 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11353 "addis %0,%2,%1+%3@toc@ha")
11355 (define_insn "*largetoc_high_plus_aix<mode>"
11356 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11357 (high:P
11358 (plus:P
11359 (unspec [(match_operand:P 1 "" "")
11360 (match_operand:P 2 "gpc_reg_operand" "b")]
11361 UNSPEC_TOCREL)
11362 (match_operand 3 "const_int_operand" "n"))))]
11363 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11364 "addis %0,%1+%3@u(%2)")
11366 (define_insn "*largetoc_low"
11367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11368 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
11369 (match_operand:DI 2 "" "")))]
11370 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11371 "@
11372 addi %0,%1,%2@l
11373 addic %0,%1,%2@l")
11375 (define_insn "*largetoc_low_aix<mode>"
11376 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11377 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
11378 (match_operand:P 2 "" "")))]
11379 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11380 "la %0,%2@l(%1)")
11382 (define_insn_and_split "*tocref<mode>"
11383 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11384 (match_operand:P 1 "small_toc_ref" "R"))]
11385 "TARGET_TOC"
11386 "la %0,%a1"
11387 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11388 [(set (match_dup 0) (high:P (match_dup 1)))
11389 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
11391 ;; Elf specific ways of loading addresses for non-PIC code.
11392 ;; The output of this could be r0, but we make a very strong
11393 ;; preference for a base register because it will usually
11394 ;; be needed there.
11395 (define_insn "elf_high"
11396 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11397 (high:SI (match_operand 1 "" "")))]
11398 "TARGET_ELF && ! TARGET_64BIT"
11399 "lis %0,%1@ha")
11401 (define_insn "elf_low"
11402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11403 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11404 (match_operand 2 "" "")))]
11405 "TARGET_ELF && ! TARGET_64BIT"
11406 "@
11407 la %0,%2@l(%1)
11408 addic %0,%1,%K2")
11409 \f
11410 ;; Call and call_value insns
11411 (define_expand "call"
11412 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11413 (match_operand 1 "" ""))
11414 (use (match_operand 2 "" ""))
11415 (clobber (reg:SI LR_REGNO))])]
11416 ""
11417 "
11418 {
11419 #if TARGET_MACHO
11420 if (MACHOPIC_INDIRECT)
11421 operands[0] = machopic_indirect_call_target (operands[0]);
11422 #endif
11424 gcc_assert (GET_CODE (operands[0]) == MEM);
11425 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11427 operands[0] = XEXP (operands[0], 0);
11429 if (GET_CODE (operands[0]) != SYMBOL_REF
11430 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11431 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11432 {
11433 if (INTVAL (operands[2]) & CALL_LONG)
11434 operands[0] = rs6000_longcall_ref (operands[0]);
11436 switch (DEFAULT_ABI)
11437 {
11438 case ABI_V4:
11439 case ABI_DARWIN:
11440 operands[0] = force_reg (Pmode, operands[0]);
11441 break;
11443 case ABI_AIX:
11444 /* AIX function pointers are really pointers to a three word
11445 area. */
11446 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
11447 DONE;
11449 default:
11450 gcc_unreachable ();
11451 }
11452 }
11453 }")
11455 (define_expand "call_value"
11456 [(parallel [(set (match_operand 0 "" "")
11457 (call (mem:SI (match_operand 1 "address_operand" ""))
11458 (match_operand 2 "" "")))
11459 (use (match_operand 3 "" ""))
11460 (clobber (reg:SI LR_REGNO))])]
11461 ""
11462 "
11463 {
11464 #if TARGET_MACHO
11465 if (MACHOPIC_INDIRECT)
11466 operands[1] = machopic_indirect_call_target (operands[1]);
11467 #endif
11469 gcc_assert (GET_CODE (operands[1]) == MEM);
11470 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11472 operands[1] = XEXP (operands[1], 0);
11474 if (GET_CODE (operands[1]) != SYMBOL_REF
11475 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11476 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11477 {
11478 if (INTVAL (operands[3]) & CALL_LONG)
11479 operands[1] = rs6000_longcall_ref (operands[1]);
11481 switch (DEFAULT_ABI)
11482 {
11483 case ABI_V4:
11484 case ABI_DARWIN:
11485 operands[1] = force_reg (Pmode, operands[1]);
11486 break;
11488 case ABI_AIX:
11489 /* AIX function pointers are really pointers to a three word
11490 area. */
11491 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
11492 DONE;
11494 default:
11495 gcc_unreachable ();
11496 }
11497 }
11498 }")
11500 ;; Call to function in current module. No TOC pointer reload needed.
11501 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11502 ;; either the function was not prototyped, or it was prototyped as a
11503 ;; variable argument function. It is > 0 if FP registers were passed
11504 ;; and < 0 if they were not.
11506 (define_insn "*call_local32"
11507 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11508 (match_operand 1 "" "g,g"))
11509 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11510 (clobber (reg:SI LR_REGNO))]
11511 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11512 "*
11513 {
11514 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11515 output_asm_insn (\"crxor 6,6,6\", operands);
11517 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11518 output_asm_insn (\"creqv 6,6,6\", operands);
11520 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11521 }"
11522 [(set_attr "type" "branch")
11523 (set_attr "length" "4,8")])
11525 (define_insn "*call_local64"
11526 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11527 (match_operand 1 "" "g,g"))
11528 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11529 (clobber (reg:SI LR_REGNO))]
11530 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11531 "*
11532 {
11533 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11534 output_asm_insn (\"crxor 6,6,6\", operands);
11536 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11537 output_asm_insn (\"creqv 6,6,6\", operands);
11539 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11540 }"
11541 [(set_attr "type" "branch")
11542 (set_attr "length" "4,8")])
11544 (define_insn "*call_value_local32"
11545 [(set (match_operand 0 "" "")
11546 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11547 (match_operand 2 "" "g,g")))
11548 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11549 (clobber (reg:SI LR_REGNO))]
11550 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11551 "*
11552 {
11553 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11554 output_asm_insn (\"crxor 6,6,6\", operands);
11556 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11557 output_asm_insn (\"creqv 6,6,6\", operands);
11559 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11560 }"
11561 [(set_attr "type" "branch")
11562 (set_attr "length" "4,8")])
11565 (define_insn "*call_value_local64"
11566 [(set (match_operand 0 "" "")
11567 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11568 (match_operand 2 "" "g,g")))
11569 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11570 (clobber (reg:SI LR_REGNO))]
11571 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11572 "*
11573 {
11574 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11575 output_asm_insn (\"crxor 6,6,6\", operands);
11577 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11578 output_asm_insn (\"creqv 6,6,6\", operands);
11580 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11581 }"
11582 [(set_attr "type" "branch")
11583 (set_attr "length" "4,8")])
11585 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11586 ;; Operand0 is the addresss of the function to call
11587 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11588 ;; Operand2 is the location in the function descriptor to load r2 from
11589 ;; Operand3 is the stack location to hold the current TOC pointer
11591 (define_insn "call_indirect_aix<ptrsize>"
11592 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11593 (match_operand 1 "" "g,g"))
11594 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11595 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11596 (use (reg:P STATIC_CHAIN_REGNUM))
11597 (clobber (reg:P LR_REGNO))]
11598 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11599 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11600 [(set_attr "type" "jmpreg")
11601 (set_attr "length" "12")])
11603 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
11604 ;; Operand0 is the addresss of the function to call
11605 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11606 ;; Operand2 is the location in the function descriptor to load r2 from
11607 ;; Operand3 is the stack location to hold the current TOC pointer
11609 (define_insn "call_indirect_aix<ptrsize>_nor11"
11610 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11611 (match_operand 1 "" "g,g"))
11612 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11613 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11614 (clobber (reg:P LR_REGNO))]
11615 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11616 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11617 [(set_attr "type" "jmpreg")
11618 (set_attr "length" "12")])
11620 ;; Operand0 is the return result of the function
11621 ;; Operand1 is the addresss of the function to call
11622 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11623 ;; Operand3 is the location in the function descriptor to load r2 from
11624 ;; Operand4 is the stack location to hold the current TOC pointer
11626 (define_insn "call_value_indirect_aix<ptrsize>"
11627 [(set (match_operand 0 "" "")
11628 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11629 (match_operand 2 "" "g,g")))
11630 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11631 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11632 (use (reg:P STATIC_CHAIN_REGNUM))
11633 (clobber (reg:P LR_REGNO))]
11634 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11635 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11636 [(set_attr "type" "jmpreg")
11637 (set_attr "length" "12")])
11639 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
11640 ;; Operand0 is the return result of the function
11641 ;; Operand1 is the addresss of the function to call
11642 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11643 ;; Operand3 is the location in the function descriptor to load r2 from
11644 ;; Operand4 is the stack location to hold the current TOC pointer
11646 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
11647 [(set (match_operand 0 "" "")
11648 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11649 (match_operand 2 "" "g,g")))
11650 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11651 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11652 (clobber (reg:P LR_REGNO))]
11653 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11654 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11655 [(set_attr "type" "jmpreg")
11656 (set_attr "length" "12")])
11658 ;; Call to function which may be in another module. Restore the TOC
11659 ;; pointer (r2) after the call unless this is System V.
11660 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11661 ;; either the function was not prototyped, or it was prototyped as a
11662 ;; variable argument function. It is > 0 if FP registers were passed
11663 ;; and < 0 if they were not.
11665 (define_insn "*call_nonlocal_aix32"
11666 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11667 (match_operand 1 "" "g"))
11668 (use (match_operand:SI 2 "immediate_operand" "O"))
11669 (clobber (reg:SI LR_REGNO))]
11670 "TARGET_32BIT
11671 && DEFAULT_ABI == ABI_AIX
11672 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11673 "bl %z0\;nop"
11674 [(set_attr "type" "branch")
11675 (set_attr "length" "8")])
11677 (define_insn "*call_nonlocal_aix64"
11678 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11679 (match_operand 1 "" "g"))
11680 (use (match_operand:SI 2 "immediate_operand" "O"))
11681 (clobber (reg:SI LR_REGNO))]
11682 "TARGET_64BIT
11683 && DEFAULT_ABI == ABI_AIX
11684 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11685 "bl %z0\;nop"
11686 [(set_attr "type" "branch")
11687 (set_attr "length" "8")])
11689 (define_insn "*call_value_nonlocal_aix32"
11690 [(set (match_operand 0 "" "")
11691 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11692 (match_operand 2 "" "g")))
11693 (use (match_operand:SI 3 "immediate_operand" "O"))
11694 (clobber (reg:SI LR_REGNO))]
11695 "TARGET_32BIT
11696 && DEFAULT_ABI == ABI_AIX
11697 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11698 "bl %z1\;nop"
11699 [(set_attr "type" "branch")
11700 (set_attr "length" "8")])
11702 (define_insn "*call_value_nonlocal_aix64"
11703 [(set (match_operand 0 "" "")
11704 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11705 (match_operand 2 "" "g")))
11706 (use (match_operand:SI 3 "immediate_operand" "O"))
11707 (clobber (reg:SI LR_REGNO))]
11708 "TARGET_64BIT
11709 && DEFAULT_ABI == ABI_AIX
11710 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11711 "bl %z1\;nop"
11712 [(set_attr "type" "branch")
11713 (set_attr "length" "8")])
11715 ;; A function pointer under System V is just a normal pointer
11716 ;; operands[0] is the function pointer
11717 ;; operands[1] is the stack size to clean up
11718 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11719 ;; which indicates how to set cr1
11721 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11722 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11723 (match_operand 1 "" "g,g,g,g"))
11724 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11725 (clobber (reg:SI LR_REGNO))]
11726 "DEFAULT_ABI == ABI_V4
11727 || DEFAULT_ABI == ABI_DARWIN"
11728 {
11729 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11730 output_asm_insn ("crxor 6,6,6", operands);
11732 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11733 output_asm_insn ("creqv 6,6,6", operands);
11735 return "b%T0l";
11736 }
11737 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11738 (set_attr "length" "4,4,8,8")])
11740 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11741 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11742 (match_operand 1 "" "g,g"))
11743 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11744 (clobber (reg:SI LR_REGNO))]
11745 "(DEFAULT_ABI == ABI_DARWIN
11746 || (DEFAULT_ABI == ABI_V4
11747 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11748 {
11749 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11750 output_asm_insn ("crxor 6,6,6", operands);
11752 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11753 output_asm_insn ("creqv 6,6,6", operands);
11755 #if TARGET_MACHO
11756 return output_call(insn, operands, 0, 2);
11757 #else
11758 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11759 {
11760 gcc_assert (!TARGET_SECURE_PLT);
11761 return "bl %z0@plt";
11762 }
11763 else
11764 return "bl %z0";
11765 #endif
11766 }
11767 "DEFAULT_ABI == ABI_V4
11768 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11769 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11770 [(parallel [(call (mem:SI (match_dup 0))
11771 (match_dup 1))
11772 (use (match_dup 2))
11773 (use (match_dup 3))
11774 (clobber (reg:SI LR_REGNO))])]
11775 {
11776 operands[3] = pic_offset_table_rtx;
11777 }
11778 [(set_attr "type" "branch,branch")
11779 (set_attr "length" "4,8")])
11781 (define_insn "*call_nonlocal_sysv_secure<mode>"
11782 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11783 (match_operand 1 "" "g,g"))
11784 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11785 (use (match_operand:SI 3 "register_operand" "r,r"))
11786 (clobber (reg:SI LR_REGNO))]
11787 "(DEFAULT_ABI == ABI_V4
11788 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11789 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11790 {
11791 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11792 output_asm_insn ("crxor 6,6,6", operands);
11794 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11795 output_asm_insn ("creqv 6,6,6", operands);
11797 if (flag_pic == 2)
11798 /* The magic 32768 offset here and in the other sysv call insns
11799 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11800 See sysv4.h:toc_section. */
11801 return "bl %z0+32768@plt";
11802 else
11803 return "bl %z0@plt";
11804 }
11805 [(set_attr "type" "branch,branch")
11806 (set_attr "length" "4,8")])
11808 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11809 [(set (match_operand 0 "" "")
11810 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11811 (match_operand 2 "" "g,g,g,g")))
11812 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11813 (clobber (reg:SI LR_REGNO))]
11814 "DEFAULT_ABI == ABI_V4
11815 || DEFAULT_ABI == ABI_DARWIN"
11816 {
11817 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11818 output_asm_insn ("crxor 6,6,6", operands);
11820 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11821 output_asm_insn ("creqv 6,6,6", operands);
11823 return "b%T1l";
11824 }
11825 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11826 (set_attr "length" "4,4,8,8")])
11828 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11829 [(set (match_operand 0 "" "")
11830 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11831 (match_operand 2 "" "g,g")))
11832 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11833 (clobber (reg:SI LR_REGNO))]
11834 "(DEFAULT_ABI == ABI_DARWIN
11835 || (DEFAULT_ABI == ABI_V4
11836 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11837 {
11838 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11839 output_asm_insn ("crxor 6,6,6", operands);
11841 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11842 output_asm_insn ("creqv 6,6,6", operands);
11844 #if TARGET_MACHO
11845 return output_call(insn, operands, 1, 3);
11846 #else
11847 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11848 {
11849 gcc_assert (!TARGET_SECURE_PLT);
11850 return "bl %z1@plt";
11851 }
11852 else
11853 return "bl %z1";
11854 #endif
11855 }
11856 "DEFAULT_ABI == ABI_V4
11857 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11858 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11859 [(parallel [(set (match_dup 0)
11860 (call (mem:SI (match_dup 1))
11861 (match_dup 2)))
11862 (use (match_dup 3))
11863 (use (match_dup 4))
11864 (clobber (reg:SI LR_REGNO))])]
11865 {
11866 operands[4] = pic_offset_table_rtx;
11867 }
11868 [(set_attr "type" "branch,branch")
11869 (set_attr "length" "4,8")])
11871 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11872 [(set (match_operand 0 "" "")
11873 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11874 (match_operand 2 "" "g,g")))
11875 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11876 (use (match_operand:SI 4 "register_operand" "r,r"))
11877 (clobber (reg:SI LR_REGNO))]
11878 "(DEFAULT_ABI == ABI_V4
11879 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11880 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11881 {
11882 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11883 output_asm_insn ("crxor 6,6,6", operands);
11885 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11886 output_asm_insn ("creqv 6,6,6", operands);
11888 if (flag_pic == 2)
11889 return "bl %z1+32768@plt";
11890 else
11891 return "bl %z1@plt";
11892 }
11893 [(set_attr "type" "branch,branch")
11894 (set_attr "length" "4,8")])
11896 ;; Call subroutine returning any type.
11897 (define_expand "untyped_call"
11898 [(parallel [(call (match_operand 0 "" "")
11899 (const_int 0))
11900 (match_operand 1 "" "")
11901 (match_operand 2 "" "")])]
11902 ""
11903 "
11904 {
11905 int i;
11907 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11909 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11910 {
11911 rtx set = XVECEXP (operands[2], 0, i);
11912 emit_move_insn (SET_DEST (set), SET_SRC (set));
11913 }
11915 /* The optimizer does not know that the call sets the function value
11916 registers we stored in the result block. We avoid problems by
11917 claiming that all hard registers are used and clobbered at this
11918 point. */
11919 emit_insn (gen_blockage ());
11921 DONE;
11922 }")
11924 ;; sibling call patterns
11925 (define_expand "sibcall"
11926 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11927 (match_operand 1 "" ""))
11928 (use (match_operand 2 "" ""))
11929 (use (reg:SI LR_REGNO))
11930 (simple_return)])]
11931 ""
11932 "
11933 {
11934 #if TARGET_MACHO
11935 if (MACHOPIC_INDIRECT)
11936 operands[0] = machopic_indirect_call_target (operands[0]);
11937 #endif
11939 gcc_assert (GET_CODE (operands[0]) == MEM);
11940 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11942 operands[0] = XEXP (operands[0], 0);
11943 }")
11945 ;; this and similar patterns must be marked as using LR, otherwise
11946 ;; dataflow will try to delete the store into it. This is true
11947 ;; even when the actual reg to jump to is in CTR, when LR was
11948 ;; saved and restored around the PIC-setting BCL.
11949 (define_insn "*sibcall_local32"
11950 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11951 (match_operand 1 "" "g,g"))
11952 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11953 (use (reg:SI LR_REGNO))
11954 (simple_return)]
11955 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11956 "*
11957 {
11958 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11959 output_asm_insn (\"crxor 6,6,6\", operands);
11961 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11962 output_asm_insn (\"creqv 6,6,6\", operands);
11964 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11965 }"
11966 [(set_attr "type" "branch")
11967 (set_attr "length" "4,8")])
11969 (define_insn "*sibcall_local64"
11970 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11971 (match_operand 1 "" "g,g"))
11972 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11973 (use (reg:SI LR_REGNO))
11974 (simple_return)]
11975 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11976 "*
11977 {
11978 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11979 output_asm_insn (\"crxor 6,6,6\", operands);
11981 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11982 output_asm_insn (\"creqv 6,6,6\", operands);
11984 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11985 }"
11986 [(set_attr "type" "branch")
11987 (set_attr "length" "4,8")])
11989 (define_insn "*sibcall_value_local32"
11990 [(set (match_operand 0 "" "")
11991 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11992 (match_operand 2 "" "g,g")))
11993 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11994 (use (reg:SI LR_REGNO))
11995 (simple_return)]
11996 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11997 "*
11998 {
11999 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12000 output_asm_insn (\"crxor 6,6,6\", operands);
12002 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12003 output_asm_insn (\"creqv 6,6,6\", operands);
12005 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12006 }"
12007 [(set_attr "type" "branch")
12008 (set_attr "length" "4,8")])
12011 (define_insn "*sibcall_value_local64"
12012 [(set (match_operand 0 "" "")
12013 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12014 (match_operand 2 "" "g,g")))
12015 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12016 (use (reg:SI LR_REGNO))
12017 (simple_return)]
12018 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12019 "*
12020 {
12021 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12022 output_asm_insn (\"crxor 6,6,6\", operands);
12024 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12025 output_asm_insn (\"creqv 6,6,6\", operands);
12027 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12028 }"
12029 [(set_attr "type" "branch")
12030 (set_attr "length" "4,8")])
12032 (define_insn "*sibcall_nonlocal_aix<mode>"
12033 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12034 (match_operand 1 "" "g,g"))
12035 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12036 (use (reg:SI LR_REGNO))
12037 (simple_return)]
12038 "DEFAULT_ABI == ABI_AIX
12039 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12040 "@
12041 b %z0
12042 b%T0"
12043 [(set_attr "type" "branch")
12044 (set_attr "length" "4")])
12046 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12047 [(set (match_operand 0 "" "")
12048 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12049 (match_operand 2 "" "g,g")))
12050 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12051 (use (reg:SI LR_REGNO))
12052 (simple_return)]
12053 "DEFAULT_ABI == ABI_AIX
12054 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12055 "@
12056 b %z1
12057 b%T1"
12058 [(set_attr "type" "branch")
12059 (set_attr "length" "4")])
12061 (define_insn "*sibcall_nonlocal_sysv<mode>"
12062 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12063 (match_operand 1 "" ""))
12064 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12065 (use (reg:SI LR_REGNO))
12066 (simple_return)]
12067 "(DEFAULT_ABI == ABI_DARWIN
12068 || DEFAULT_ABI == ABI_V4)
12069 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12070 "*
12071 {
12072 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12073 output_asm_insn (\"crxor 6,6,6\", operands);
12075 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12076 output_asm_insn (\"creqv 6,6,6\", operands);
12078 if (which_alternative >= 2)
12079 return \"b%T0\";
12080 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12081 {
12082 gcc_assert (!TARGET_SECURE_PLT);
12083 return \"b %z0@plt\";
12084 }
12085 else
12086 return \"b %z0\";
12087 }"
12088 [(set_attr "type" "branch")
12089 (set_attr "length" "4,8,4,8")])
12091 (define_expand "sibcall_value"
12092 [(parallel [(set (match_operand 0 "register_operand" "")
12093 (call (mem:SI (match_operand 1 "address_operand" ""))
12094 (match_operand 2 "" "")))
12095 (use (match_operand 3 "" ""))
12096 (use (reg:SI LR_REGNO))
12097 (simple_return)])]
12098 ""
12099 "
12100 {
12101 #if TARGET_MACHO
12102 if (MACHOPIC_INDIRECT)
12103 operands[1] = machopic_indirect_call_target (operands[1]);
12104 #endif
12106 gcc_assert (GET_CODE (operands[1]) == MEM);
12107 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12109 operands[1] = XEXP (operands[1], 0);
12110 }")
12112 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12113 [(set (match_operand 0 "" "")
12114 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12115 (match_operand 2 "" "")))
12116 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12117 (use (reg:SI LR_REGNO))
12118 (simple_return)]
12119 "(DEFAULT_ABI == ABI_DARWIN
12120 || DEFAULT_ABI == ABI_V4)
12121 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12122 "*
12123 {
12124 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12125 output_asm_insn (\"crxor 6,6,6\", operands);
12127 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12128 output_asm_insn (\"creqv 6,6,6\", operands);
12130 if (which_alternative >= 2)
12131 return \"b%T1\";
12132 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12133 {
12134 gcc_assert (!TARGET_SECURE_PLT);
12135 return \"b %z1@plt\";
12136 }
12137 else
12138 return \"b %z1\";
12139 }"
12140 [(set_attr "type" "branch")
12141 (set_attr "length" "4,8,4,8")])
12143 (define_expand "sibcall_epilogue"
12144 [(use (const_int 0))]
12145 ""
12146 {
12147 if (!TARGET_SCHED_PROLOG)
12148 emit_insn (gen_blockage ());
12149 rs6000_emit_epilogue (TRUE);
12150 DONE;
12151 })
12153 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12154 ;; all of memory. This blocks insns from being moved across this point.
12156 (define_insn "blockage"
12157 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12158 ""
12159 "")
12161 (define_expand "probe_stack"
12162 [(set (match_operand 0 "memory_operand" "=m")
12163 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12164 ""
12165 {
12166 if (TARGET_64BIT)
12167 emit_insn (gen_probe_stack_di (operands[0]));
12168 else
12169 emit_insn (gen_probe_stack_si (operands[0]));
12170 DONE;
12171 })
12173 (define_insn "probe_stack_<mode>"
12174 [(set (match_operand:P 0 "memory_operand" "=m")
12175 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12176 ""
12177 {
12178 operands[1] = gen_rtx_REG (Pmode, 0);
12179 return "st<wd>%U0%X0 %1,%0";
12180 }
12181 [(set (attr "type")
12182 (if_then_else
12183 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
12184 (const_string "store_ux")
12185 (if_then_else
12186 (match_test "update_address_mem (operands[0], VOIDmode)")
12187 (const_string "store_u")
12188 (const_string "store"))))
12189 (set_attr "length" "4")])
12191 (define_insn "probe_stack_range<P:mode>"
12192 [(set (match_operand:P 0 "register_operand" "=r")
12193 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12194 (match_operand:P 2 "register_operand" "r")]
12195 UNSPECV_PROBE_STACK_RANGE))]
12196 ""
12197 "* return output_probe_stack_range (operands[0], operands[2]);"
12198 [(set_attr "type" "three")])
12199 \f
12200 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12201 ;; signed & unsigned, and one type of branch.
12202 ;;
12203 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12204 ;; insns, and branches.
12206 (define_expand "cbranch<mode>4"
12207 [(use (match_operator 0 "rs6000_cbranch_operator"
12208 [(match_operand:GPR 1 "gpc_reg_operand" "")
12209 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12210 (use (match_operand 3 ""))]
12211 ""
12212 "
12213 {
12214 /* Take care of the possibility that operands[2] might be negative but
12215 this might be a logical operation. That insn doesn't exist. */
12216 if (GET_CODE (operands[2]) == CONST_INT
12217 && INTVAL (operands[2]) < 0)
12218 {
12219 operands[2] = force_reg (<MODE>mode, operands[2]);
12220 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12221 GET_MODE (operands[0]),
12222 operands[1], operands[2]);
12223 }
12225 rs6000_emit_cbranch (<MODE>mode, operands);
12226 DONE;
12227 }")
12229 (define_expand "cbranch<mode>4"
12230 [(use (match_operator 0 "rs6000_cbranch_operator"
12231 [(match_operand:FP 1 "gpc_reg_operand" "")
12232 (match_operand:FP 2 "gpc_reg_operand" "")]))
12233 (use (match_operand 3 ""))]
12234 ""
12235 "
12236 {
12237 rs6000_emit_cbranch (<MODE>mode, operands);
12238 DONE;
12239 }")
12241 (define_expand "cstore<mode>4"
12242 [(use (match_operator 1 "rs6000_cbranch_operator"
12243 [(match_operand:GPR 2 "gpc_reg_operand" "")
12244 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12245 (clobber (match_operand:SI 0 "register_operand"))]
12246 ""
12247 "
12248 {
12249 /* Take care of the possibility that operands[3] might be negative but
12250 this might be a logical operation. That insn doesn't exist. */
12251 if (GET_CODE (operands[3]) == CONST_INT
12252 && INTVAL (operands[3]) < 0)
12253 {
12254 operands[3] = force_reg (<MODE>mode, operands[3]);
12255 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12256 GET_MODE (operands[1]),
12257 operands[2], operands[3]);
12258 }
12260 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12261 For SEQ, likewise, except that comparisons with zero should be done
12262 with an scc insns. However, due to the order that combine see the
12263 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12264 the cases we don't want to handle or are best handled by portable
12265 code. */
12266 if (GET_CODE (operands[1]) == NE)
12267 FAIL;
12268 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12269 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12270 && operands[3] == const0_rtx)
12271 FAIL;
12272 rs6000_emit_sCOND (<MODE>mode, operands);
12273 DONE;
12274 }")
12276 (define_expand "cstore<mode>4"
12277 [(use (match_operator 1 "rs6000_cbranch_operator"
12278 [(match_operand:FP 2 "gpc_reg_operand" "")
12279 (match_operand:FP 3 "gpc_reg_operand" "")]))
12280 (clobber (match_operand:SI 0 "register_operand"))]
12281 ""
12282 "
12283 {
12284 rs6000_emit_sCOND (<MODE>mode, operands);
12285 DONE;
12286 }")
12289 (define_expand "stack_protect_set"
12290 [(match_operand 0 "memory_operand" "")
12291 (match_operand 1 "memory_operand" "")]
12292 ""
12293 {
12294 #ifdef TARGET_THREAD_SSP_OFFSET
12295 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12296 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12297 operands[1] = gen_rtx_MEM (Pmode, addr);
12298 #endif
12299 if (TARGET_64BIT)
12300 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12301 else
12302 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12303 DONE;
12304 })
12306 (define_insn "stack_protect_setsi"
12307 [(set (match_operand:SI 0 "memory_operand" "=m")
12308 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12309 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12310 "TARGET_32BIT"
12311 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12312 [(set_attr "type" "three")
12313 (set_attr "length" "12")])
12315 (define_insn "stack_protect_setdi"
12316 [(set (match_operand:DI 0 "memory_operand" "=Y")
12317 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12318 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12319 "TARGET_64BIT"
12320 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12321 [(set_attr "type" "three")
12322 (set_attr "length" "12")])
12324 (define_expand "stack_protect_test"
12325 [(match_operand 0 "memory_operand" "")
12326 (match_operand 1 "memory_operand" "")
12327 (match_operand 2 "" "")]
12328 ""
12329 {
12330 rtx test, op0, op1;
12331 #ifdef TARGET_THREAD_SSP_OFFSET
12332 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12333 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12334 operands[1] = gen_rtx_MEM (Pmode, addr);
12335 #endif
12336 op0 = operands[0];
12337 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12338 test = gen_rtx_EQ (VOIDmode, op0, op1);
12339 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12340 DONE;
12341 })
12343 (define_insn "stack_protect_testsi"
12344 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12345 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12346 (match_operand:SI 2 "memory_operand" "m,m")]
12347 UNSPEC_SP_TEST))
12348 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12349 (clobber (match_scratch:SI 3 "=&r,&r"))]
12350 "TARGET_32BIT"
12351 "@
12352 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12353 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12354 [(set_attr "length" "16,20")])
12356 (define_insn "stack_protect_testdi"
12357 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12358 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12359 (match_operand:DI 2 "memory_operand" "Y,Y")]
12360 UNSPEC_SP_TEST))
12361 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12362 (clobber (match_scratch:DI 3 "=&r,&r"))]
12363 "TARGET_64BIT"
12364 "@
12365 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12366 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12367 [(set_attr "length" "16,20")])
12369 \f
12370 ;; Here are the actual compare insns.
12371 (define_insn "*cmp<mode>_internal1"
12372 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12373 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12374 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12375 ""
12376 "cmp<wd>%I2 %0,%1,%2"
12377 [(set_attr "type" "cmp")])
12379 ;; If we are comparing a register for equality with a large constant,
12380 ;; we can do this with an XOR followed by a compare. But this is profitable
12381 ;; only if the large constant is only used for the comparison (and in this
12382 ;; case we already have a register to reuse as scratch).
12383 ;;
12384 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12385 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12387 (define_peephole2
12388 [(set (match_operand:SI 0 "register_operand")
12389 (match_operand:SI 1 "logical_const_operand" ""))
12390 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12391 [(match_dup 0)
12392 (match_operand:SI 2 "logical_const_operand" "")]))
12393 (set (match_operand:CC 4 "cc_reg_operand" "")
12394 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12395 (match_dup 0)))
12396 (set (pc)
12397 (if_then_else (match_operator 6 "equality_operator"
12398 [(match_dup 4) (const_int 0)])
12399 (match_operand 7 "" "")
12400 (match_operand 8 "" "")))]
12401 "peep2_reg_dead_p (3, operands[0])
12402 && peep2_reg_dead_p (4, operands[4])"
12403 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12404 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12405 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12407 {
12408 /* Get the constant we are comparing against, and see what it looks like
12409 when sign-extended from 16 to 32 bits. Then see what constant we could
12410 XOR with SEXTC to get the sign-extended value. */
12411 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12412 SImode,
12413 operands[1], operands[2]);
12414 HOST_WIDE_INT c = INTVAL (cnst);
12415 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12416 HOST_WIDE_INT xorv = c ^ sextc;
12418 operands[9] = GEN_INT (xorv);
12419 operands[10] = GEN_INT (sextc);
12420 })
12422 (define_insn "*cmpsi_internal2"
12423 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12424 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12425 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12426 ""
12427 "cmplw%I2 %0,%1,%b2"
12428 [(set_attr "type" "cmp")])
12430 (define_insn "*cmpdi_internal2"
12431 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12432 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12433 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12434 ""
12435 "cmpld%I2 %0,%1,%b2"
12436 [(set_attr "type" "cmp")])
12438 ;; The following two insns don't exist as single insns, but if we provide
12439 ;; them, we can swap an add and compare, which will enable us to overlap more
12440 ;; of the required delay between a compare and branch. We generate code for
12441 ;; them by splitting.
12443 (define_insn ""
12444 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12445 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12446 (match_operand:SI 2 "short_cint_operand" "i")))
12447 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12448 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12449 ""
12450 "#"
12451 [(set_attr "length" "8")])
12453 (define_insn ""
12454 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12455 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12456 (match_operand:SI 2 "u_short_cint_operand" "i")))
12457 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12458 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12459 ""
12460 "#"
12461 [(set_attr "length" "8")])
12463 (define_split
12464 [(set (match_operand:CC 3 "cc_reg_operand" "")
12465 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12466 (match_operand:SI 2 "short_cint_operand" "")))
12467 (set (match_operand:SI 0 "gpc_reg_operand" "")
12468 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12469 ""
12470 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12471 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12473 (define_split
12474 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12475 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12476 (match_operand:SI 2 "u_short_cint_operand" "")))
12477 (set (match_operand:SI 0 "gpc_reg_operand" "")
12478 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12479 ""
12480 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12481 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12483 (define_insn "*cmpsf_internal1"
12484 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12485 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12486 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12487 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12488 "fcmpu %0,%1,%2"
12489 [(set_attr "type" "fpcompare")])
12491 (define_insn "*cmpdf_internal1"
12492 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12493 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12494 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12495 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12496 && !VECTOR_UNIT_VSX_P (DFmode)"
12497 "fcmpu %0,%1,%2"
12498 [(set_attr "type" "fpcompare")])
12500 ;; Only need to compare second words if first words equal
12501 (define_insn "*cmptf_internal1"
12502 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12503 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12504 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12505 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12506 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12507 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12508 [(set_attr "type" "fpcompare")
12509 (set_attr "length" "12")])
12511 (define_insn_and_split "*cmptf_internal2"
12512 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12513 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12514 (match_operand:TF 2 "gpc_reg_operand" "d")))
12515 (clobber (match_scratch:DF 3 "=d"))
12516 (clobber (match_scratch:DF 4 "=d"))
12517 (clobber (match_scratch:DF 5 "=d"))
12518 (clobber (match_scratch:DF 6 "=d"))
12519 (clobber (match_scratch:DF 7 "=d"))
12520 (clobber (match_scratch:DF 8 "=d"))
12521 (clobber (match_scratch:DF 9 "=d"))
12522 (clobber (match_scratch:DF 10 "=d"))
12523 (clobber (match_scratch:GPR 11 "=b"))]
12524 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12525 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12526 "#"
12527 "&& reload_completed"
12528 [(set (match_dup 3) (match_dup 14))
12529 (set (match_dup 4) (match_dup 15))
12530 (set (match_dup 9) (abs:DF (match_dup 5)))
12531 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12532 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12533 (label_ref (match_dup 12))
12534 (pc)))
12535 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12536 (set (pc) (label_ref (match_dup 13)))
12537 (match_dup 12)
12538 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12539 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12540 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12541 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12542 (match_dup 13)]
12543 {
12544 REAL_VALUE_TYPE rv;
12545 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12546 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12548 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12549 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12550 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12551 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12552 operands[12] = gen_label_rtx ();
12553 operands[13] = gen_label_rtx ();
12554 real_inf (&rv);
12555 operands[14] = force_const_mem (DFmode,
12556 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12557 operands[15] = force_const_mem (DFmode,
12558 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12559 DFmode));
12560 if (TARGET_TOC)
12561 {
12562 rtx tocref;
12563 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12564 operands[14] = gen_const_mem (DFmode, tocref);
12565 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12566 operands[15] = gen_const_mem (DFmode, tocref);
12567 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12568 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12569 }
12570 })
12571 \f
12572 ;; Now we have the scc insns. We can do some combinations because of the
12573 ;; way the machine works.
12574 ;;
12575 ;; Note that this is probably faster if we can put an insn between the
12576 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12577 ;; cases the insns below which don't use an intermediate CR field will
12578 ;; be used instead.
12579 (define_insn ""
12580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12581 (match_operator:SI 1 "scc_comparison_operator"
12582 [(match_operand 2 "cc_reg_operand" "y")
12583 (const_int 0)]))]
12584 ""
12585 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12586 [(set (attr "type")
12587 (cond [(match_test "TARGET_MFCRF")
12588 (const_string "mfcrf")
12589 ]
12590 (const_string "mfcr")))
12591 (set_attr "length" "8")])
12593 ;; Same as above, but get the GT bit.
12594 (define_insn "move_from_CR_gt_bit"
12595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12596 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12597 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12598 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12599 [(set_attr "type" "mfcr")
12600 (set_attr "length" "8")])
12602 ;; Same as above, but get the OV/ORDERED bit.
12603 (define_insn "move_from_CR_ov_bit"
12604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12605 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
12606 UNSPEC_MV_CR_OV))]
12607 "TARGET_ISEL"
12608 "mfcr %0\;rlwinm %0,%0,%t1,1"
12609 [(set_attr "type" "mfcr")
12610 (set_attr "length" "8")])
12612 (define_insn ""
12613 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12614 (match_operator:DI 1 "scc_comparison_operator"
12615 [(match_operand 2 "cc_reg_operand" "y")
12616 (const_int 0)]))]
12617 "TARGET_POWERPC64"
12618 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12619 [(set (attr "type")
12620 (cond [(match_test "TARGET_MFCRF")
12621 (const_string "mfcrf")
12622 ]
12623 (const_string "mfcr")))
12624 (set_attr "length" "8")])
12626 (define_insn ""
12627 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12628 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12629 [(match_operand 2 "cc_reg_operand" "y,y")
12630 (const_int 0)])
12631 (const_int 0)))
12632 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12633 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12634 "TARGET_32BIT"
12635 "@
12636 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
12637 #"
12638 [(set_attr "type" "delayed_compare")
12639 (set_attr "length" "8,16")])
12641 (define_split
12642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12643 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12644 [(match_operand 2 "cc_reg_operand" "")
12645 (const_int 0)])
12646 (const_int 0)))
12647 (set (match_operand:SI 3 "gpc_reg_operand" "")
12648 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12649 "TARGET_32BIT && reload_completed"
12650 [(set (match_dup 3)
12651 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12652 (set (match_dup 0)
12653 (compare:CC (match_dup 3)
12654 (const_int 0)))]
12655 "")
12657 (define_insn ""
12658 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12659 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12660 [(match_operand 2 "cc_reg_operand" "y")
12661 (const_int 0)])
12662 (match_operand:SI 3 "const_int_operand" "n")))]
12663 ""
12664 "*
12665 {
12666 int is_bit = ccr_bit (operands[1], 1);
12667 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12668 int count;
12670 if (is_bit >= put_bit)
12671 count = is_bit - put_bit;
12672 else
12673 count = 32 - (put_bit - is_bit);
12675 operands[4] = GEN_INT (count);
12676 operands[5] = GEN_INT (put_bit);
12678 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
12679 }"
12680 [(set (attr "type")
12681 (cond [(match_test "TARGET_MFCRF")
12682 (const_string "mfcrf")
12683 ]
12684 (const_string "mfcr")))
12685 (set_attr "length" "8")])
12687 (define_insn ""
12688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12689 (compare:CC
12690 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12691 [(match_operand 2 "cc_reg_operand" "y,y")
12692 (const_int 0)])
12693 (match_operand:SI 3 "const_int_operand" "n,n"))
12694 (const_int 0)))
12695 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12696 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12697 (match_dup 3)))]
12698 ""
12699 "*
12700 {
12701 int is_bit = ccr_bit (operands[1], 1);
12702 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12703 int count;
12705 /* Force split for non-cc0 compare. */
12706 if (which_alternative == 1)
12707 return \"#\";
12709 if (is_bit >= put_bit)
12710 count = is_bit - put_bit;
12711 else
12712 count = 32 - (put_bit - is_bit);
12714 operands[5] = GEN_INT (count);
12715 operands[6] = GEN_INT (put_bit);
12717 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12718 }"
12719 [(set_attr "type" "delayed_compare")
12720 (set_attr "length" "8,16")])
12722 (define_split
12723 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12724 (compare:CC
12725 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12726 [(match_operand 2 "cc_reg_operand" "")
12727 (const_int 0)])
12728 (match_operand:SI 3 "const_int_operand" ""))
12729 (const_int 0)))
12730 (set (match_operand:SI 4 "gpc_reg_operand" "")
12731 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12732 (match_dup 3)))]
12733 "reload_completed"
12734 [(set (match_dup 4)
12735 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12736 (match_dup 3)))
12737 (set (match_dup 0)
12738 (compare:CC (match_dup 4)
12739 (const_int 0)))]
12740 "")
12742 ;; There is a 3 cycle delay between consecutive mfcr instructions
12743 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12745 (define_peephole
12746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12747 (match_operator:SI 1 "scc_comparison_operator"
12748 [(match_operand 2 "cc_reg_operand" "y")
12749 (const_int 0)]))
12750 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12751 (match_operator:SI 4 "scc_comparison_operator"
12752 [(match_operand 5 "cc_reg_operand" "y")
12753 (const_int 0)]))]
12754 "REGNO (operands[2]) != REGNO (operands[5])"
12755 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12756 [(set_attr "type" "mfcr")
12757 (set_attr "length" "12")])
12759 (define_peephole
12760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12761 (match_operator:DI 1 "scc_comparison_operator"
12762 [(match_operand 2 "cc_reg_operand" "y")
12763 (const_int 0)]))
12764 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12765 (match_operator:DI 4 "scc_comparison_operator"
12766 [(match_operand 5 "cc_reg_operand" "y")
12767 (const_int 0)]))]
12768 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12769 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12770 [(set_attr "type" "mfcr")
12771 (set_attr "length" "12")])
12773 ;; There are some scc insns that can be done directly, without a compare.
12774 ;; These are faster because they don't involve the communications between
12775 ;; the FXU and branch units. In fact, we will be replacing all of the
12776 ;; integer scc insns here or in the portable methods in emit_store_flag.
12777 ;;
12778 ;; Also support (neg (scc ..)) since that construct is used to replace
12779 ;; branches, (plus (scc ..) ..) since that construct is common and
12780 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12781 ;; cases where it is no more expensive than (neg (scc ..)).
12783 ;; Have reload force a constant into a register for the simple insns that
12784 ;; otherwise won't accept constants. We do this because it is faster than
12785 ;; the cmp/mfcr sequence we would otherwise generate.
12787 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12788 (DI "rKJI")])
12790 (define_insn_and_split "*eq<mode>"
12791 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12792 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12793 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12794 ""
12795 "#"
12796 ""
12797 [(set (match_dup 0)
12798 (clz:GPR (match_dup 3)))
12799 (set (match_dup 0)
12800 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12801 {
12802 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12803 {
12804 /* Use output operand as intermediate. */
12805 operands[3] = operands[0];
12807 if (logical_operand (operands[2], <MODE>mode))
12808 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12809 gen_rtx_XOR (<MODE>mode,
12810 operands[1], operands[2])));
12811 else
12812 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12813 gen_rtx_PLUS (<MODE>mode, operands[1],
12814 negate_rtx (<MODE>mode,
12815 operands[2]))));
12816 }
12817 else
12818 operands[3] = operands[1];
12820 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12821 })
12823 (define_insn_and_split "*eq<mode>_compare"
12824 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12825 (compare:CC
12826 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12827 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12828 (const_int 0)))
12829 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12830 (eq:P (match_dup 1) (match_dup 2)))]
12831 "optimize_size"
12832 "#"
12833 "optimize_size"
12834 [(set (match_dup 0)
12835 (clz:P (match_dup 4)))
12836 (parallel [(set (match_dup 3)
12837 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12838 (const_int 0)))
12839 (set (match_dup 0)
12840 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12841 {
12842 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12843 {
12844 /* Use output operand as intermediate. */
12845 operands[4] = operands[0];
12847 if (logical_operand (operands[2], <MODE>mode))
12848 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12849 gen_rtx_XOR (<MODE>mode,
12850 operands[1], operands[2])));
12851 else
12852 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12853 gen_rtx_PLUS (<MODE>mode, operands[1],
12854 negate_rtx (<MODE>mode,
12855 operands[2]))));
12856 }
12857 else
12858 operands[4] = operands[1];
12860 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12861 })
12863 ;; We have insns of the form shown by the first define_insn below. If
12864 ;; there is something inside the comparison operation, we must split it.
12865 (define_split
12866 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12867 (plus:SI (match_operator 1 "comparison_operator"
12868 [(match_operand:SI 2 "" "")
12869 (match_operand:SI 3
12870 "reg_or_cint_operand" "")])
12871 (match_operand:SI 4 "gpc_reg_operand" "")))
12872 (clobber (match_operand:SI 5 "register_operand" ""))]
12873 "! gpc_reg_operand (operands[2], SImode)"
12874 [(set (match_dup 5) (match_dup 2))
12875 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12876 (match_dup 4)))])
12878 (define_insn "*plus_eqsi"
12879 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12880 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12881 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12882 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12883 "TARGET_32BIT"
12884 "@
12885 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12886 subfic %0,%1,0\;addze %0,%3
12887 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12888 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12889 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12890 [(set_attr "type" "three,two,three,three,three")
12891 (set_attr "length" "12,8,12,12,12")])
12893 (define_insn "*compare_plus_eqsi"
12894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12895 (compare:CC
12896 (plus:SI
12897 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12898 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12899 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12900 (const_int 0)))
12901 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12902 "TARGET_32BIT && optimize_size"
12903 "@
12904 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12905 subfic %4,%1,0\;addze. %4,%3
12906 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12907 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12908 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12909 #
12910 #
12911 #
12912 #
12913 #"
12914 [(set_attr "type" "compare")
12915 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12917 (define_split
12918 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12919 (compare:CC
12920 (plus:SI
12921 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12922 (match_operand:SI 2 "scc_eq_operand" ""))
12923 (match_operand:SI 3 "gpc_reg_operand" ""))
12924 (const_int 0)))
12925 (clobber (match_scratch:SI 4 ""))]
12926 "TARGET_32BIT && optimize_size && reload_completed"
12927 [(set (match_dup 4)
12928 (plus:SI (eq:SI (match_dup 1)
12929 (match_dup 2))
12930 (match_dup 3)))
12931 (set (match_dup 0)
12932 (compare:CC (match_dup 4)
12933 (const_int 0)))]
12934 "")
12936 (define_insn "*plus_eqsi_compare"
12937 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12938 (compare:CC
12939 (plus:SI
12940 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12941 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12942 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12943 (const_int 0)))
12944 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12945 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12946 "TARGET_32BIT && optimize_size"
12947 "@
12948 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12949 subfic %0,%1,0\;addze. %0,%3
12950 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12951 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12952 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12953 #
12954 #
12955 #
12956 #
12957 #"
12958 [(set_attr "type" "compare")
12959 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12961 (define_split
12962 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12963 (compare:CC
12964 (plus:SI
12965 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12966 (match_operand:SI 2 "scc_eq_operand" ""))
12967 (match_operand:SI 3 "gpc_reg_operand" ""))
12968 (const_int 0)))
12969 (set (match_operand:SI 0 "gpc_reg_operand" "")
12970 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12971 "TARGET_32BIT && optimize_size && reload_completed"
12972 [(set (match_dup 0)
12973 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12974 (set (match_dup 4)
12975 (compare:CC (match_dup 0)
12976 (const_int 0)))]
12977 "")
12979 (define_insn "*neg_eq0<mode>"
12980 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12981 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12982 (const_int 0))))]
12983 ""
12984 "addic %0,%1,-1\;subfe %0,%0,%0"
12985 [(set_attr "type" "two")
12986 (set_attr "length" "8")])
12988 (define_insn_and_split "*neg_eq<mode>"
12989 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12990 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12991 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12992 ""
12993 "#"
12994 ""
12995 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12996 {
12997 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12998 {
12999 /* Use output operand as intermediate. */
13000 operands[3] = operands[0];
13002 if (logical_operand (operands[2], <MODE>mode))
13003 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13004 gen_rtx_XOR (<MODE>mode,
13005 operands[1], operands[2])));
13006 else
13007 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13008 gen_rtx_PLUS (<MODE>mode, operands[1],
13009 negate_rtx (<MODE>mode,
13010 operands[2]))));
13011 }
13012 else
13013 operands[3] = operands[1];
13014 })
13016 (define_insn "*ne0_<mode>"
13017 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13018 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13019 (const_int 0)))
13020 (clobber (match_scratch:P 2 "=&r"))]
13021 "!(TARGET_32BIT && TARGET_ISEL)"
13022 "addic %2,%1,-1\;subfe %0,%2,%1"
13023 [(set_attr "type" "two")
13024 (set_attr "length" "8")])
13026 (define_insn "*plus_ne0_<mode>"
13027 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13028 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13029 (const_int 0))
13030 (match_operand:P 2 "gpc_reg_operand" "r")))
13031 (clobber (match_scratch:P 3 "=&r"))]
13032 ""
13033 "addic %3,%1,-1\;addze %0,%2"
13034 [(set_attr "type" "two")
13035 (set_attr "length" "8")])
13037 (define_insn "*compare_plus_ne0_<mode>"
13038 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13039 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13040 (const_int 0))
13041 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13042 (const_int 0)))
13043 (clobber (match_scratch:P 3 "=&r,&r"))
13044 (clobber (match_scratch:P 4 "=X,&r"))]
13045 ""
13046 "@
13047 addic %3,%1,-1\;addze. %3,%2
13048 #"
13049 [(set_attr "type" "compare")
13050 (set_attr "length" "8,12")])
13052 (define_split
13053 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13054 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13055 (const_int 0))
13056 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13057 (clobber (match_scratch:P 3 ""))
13058 (clobber (match_scratch:P 4 ""))]
13059 "reload_completed"
13060 [(parallel [(set (match_dup 3)
13061 (plus:P (ne:P (match_dup 1)
13062 (const_int 0))
13063 (match_dup 2)))
13064 (clobber (match_dup 4))])
13065 (set (match_dup 0)
13066 (compare:CC (match_dup 3)
13067 (const_int 0)))]
13068 "")
13070 ; For combine.
13071 (define_insn "*compare_plus_ne0_<mode>_1"
13072 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13073 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13074 (const_int 0))
13075 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13076 (clobber (match_scratch:P 3 "=&r,&r"))
13077 (clobber (match_scratch:P 4 "=X,&r"))]
13078 ""
13079 "@
13080 addic %3,%1,-1\;addze. %3,%2
13081 #"
13082 [(set_attr "type" "compare")
13083 (set_attr "length" "8,12")])
13085 (define_split
13086 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13087 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13088 (const_int 0))
13089 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13090 (clobber (match_scratch:P 3 ""))
13091 (clobber (match_scratch:P 4 ""))]
13092 "reload_completed"
13093 [(parallel [(set (match_dup 3)
13094 (plus:P (ne:P (match_dup 1)
13095 (const_int 0))
13096 (match_dup 2)))
13097 (clobber (match_dup 4))])
13098 (set (match_dup 0)
13099 (compare:CC (match_dup 3)
13100 (const_int 0)))]
13101 "")
13103 (define_insn "*plus_ne0_<mode>_compare"
13104 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13105 (compare:CC
13106 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13107 (const_int 0))
13108 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13109 (const_int 0)))
13110 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13111 (plus:P (ne:P (match_dup 1)
13112 (const_int 0))
13113 (match_dup 2)))
13114 (clobber (match_scratch:P 3 "=&r,&r"))]
13115 ""
13116 "@
13117 addic %3,%1,-1\;addze. %0,%2
13118 #"
13119 [(set_attr "type" "compare")
13120 (set_attr "length" "8,12")])
13122 (define_split
13123 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13124 (compare:CC
13125 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13126 (const_int 0))
13127 (match_operand:P 2 "gpc_reg_operand" ""))
13128 (const_int 0)))
13129 (set (match_operand:P 0 "gpc_reg_operand" "")
13130 (plus:P (ne:P (match_dup 1)
13131 (const_int 0))
13132 (match_dup 2)))
13133 (clobber (match_scratch:P 3 ""))]
13134 "reload_completed"
13135 [(parallel [(set (match_dup 0)
13136 (plus:P (ne:P (match_dup 1)
13137 (const_int 0))
13138 (match_dup 2)))
13139 (clobber (match_dup 3))])
13140 (set (match_dup 4)
13141 (compare:CC (match_dup 0)
13142 (const_int 0)))]
13143 "")
13145 (define_insn "*leu<mode>"
13146 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13147 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13148 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13149 ""
13150 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13151 [(set_attr "type" "three")
13152 (set_attr "length" "12")])
13154 (define_insn "*leu<mode>_compare"
13155 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13156 (compare:CC
13157 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13158 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13159 (const_int 0)))
13160 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13161 (leu:P (match_dup 1) (match_dup 2)))]
13162 ""
13163 "@
13164 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13165 #"
13166 [(set_attr "type" "compare")
13167 (set_attr "length" "12,16")])
13169 (define_split
13170 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13171 (compare:CC
13172 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13173 (match_operand:P 2 "reg_or_short_operand" ""))
13174 (const_int 0)))
13175 (set (match_operand:P 0 "gpc_reg_operand" "")
13176 (leu:P (match_dup 1) (match_dup 2)))]
13177 "reload_completed"
13178 [(set (match_dup 0)
13179 (leu:P (match_dup 1) (match_dup 2)))
13180 (set (match_dup 3)
13181 (compare:CC (match_dup 0)
13182 (const_int 0)))]
13183 "")
13185 (define_insn "*plus_leu<mode>"
13186 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13187 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13188 (match_operand:P 2 "reg_or_short_operand" "rI"))
13189 (match_operand:P 3 "gpc_reg_operand" "r")))]
13190 ""
13191 "subf%I2c %0,%1,%2\;addze %0,%3"
13192 [(set_attr "type" "two")
13193 (set_attr "length" "8")])
13195 (define_insn ""
13196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13197 (compare:CC
13198 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13199 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13200 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13201 (const_int 0)))
13202 (clobber (match_scratch:SI 4 "=&r,&r"))]
13203 "TARGET_32BIT"
13204 "@
13205 subf%I2c %4,%1,%2\;addze. %4,%3
13206 #"
13207 [(set_attr "type" "compare")
13208 (set_attr "length" "8,12")])
13210 (define_split
13211 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13212 (compare:CC
13213 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13214 (match_operand:SI 2 "reg_or_short_operand" ""))
13215 (match_operand:SI 3 "gpc_reg_operand" ""))
13216 (const_int 0)))
13217 (clobber (match_scratch:SI 4 ""))]
13218 "TARGET_32BIT && reload_completed"
13219 [(set (match_dup 4)
13220 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13221 (match_dup 3)))
13222 (set (match_dup 0)
13223 (compare:CC (match_dup 4)
13224 (const_int 0)))]
13225 "")
13227 (define_insn ""
13228 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13229 (compare:CC
13230 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13231 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13232 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13233 (const_int 0)))
13234 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13235 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13236 "TARGET_32BIT"
13237 "@
13238 subf%I2c %0,%1,%2\;addze. %0,%3
13239 #"
13240 [(set_attr "type" "compare")
13241 (set_attr "length" "8,12")])
13243 (define_split
13244 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13245 (compare:CC
13246 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13247 (match_operand:SI 2 "reg_or_short_operand" ""))
13248 (match_operand:SI 3 "gpc_reg_operand" ""))
13249 (const_int 0)))
13250 (set (match_operand:SI 0 "gpc_reg_operand" "")
13251 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13252 "TARGET_32BIT && reload_completed"
13253 [(set (match_dup 0)
13254 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13255 (set (match_dup 4)
13256 (compare:CC (match_dup 0)
13257 (const_int 0)))]
13258 "")
13260 (define_insn "*neg_leu<mode>"
13261 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13262 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13263 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13264 ""
13265 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13266 [(set_attr "type" "three")
13267 (set_attr "length" "12")])
13269 (define_insn "*and_neg_leu<mode>"
13270 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13271 (and:P (neg:P
13272 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13273 (match_operand:P 2 "reg_or_short_operand" "rI")))
13274 (match_operand:P 3 "gpc_reg_operand" "r")))]
13275 ""
13276 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13277 [(set_attr "type" "three")
13278 (set_attr "length" "12")])
13280 (define_insn ""
13281 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13282 (compare:CC
13283 (and:SI (neg:SI
13284 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13285 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13286 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13287 (const_int 0)))
13288 (clobber (match_scratch:SI 4 "=&r,&r"))]
13289 "TARGET_32BIT"
13290 "@
13291 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13292 #"
13293 [(set_attr "type" "compare")
13294 (set_attr "length" "12,16")])
13296 (define_split
13297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13298 (compare:CC
13299 (and:SI (neg:SI
13300 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13301 (match_operand:SI 2 "reg_or_short_operand" "")))
13302 (match_operand:SI 3 "gpc_reg_operand" ""))
13303 (const_int 0)))
13304 (clobber (match_scratch:SI 4 ""))]
13305 "TARGET_32BIT && reload_completed"
13306 [(set (match_dup 4)
13307 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13308 (match_dup 3)))
13309 (set (match_dup 0)
13310 (compare:CC (match_dup 4)
13311 (const_int 0)))]
13312 "")
13314 (define_insn ""
13315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13316 (compare:CC
13317 (and:SI (neg:SI
13318 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13319 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13320 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13321 (const_int 0)))
13322 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13323 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13324 "TARGET_32BIT"
13325 "@
13326 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13327 #"
13328 [(set_attr "type" "compare")
13329 (set_attr "length" "12,16")])
13331 (define_split
13332 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13333 (compare:CC
13334 (and:SI (neg:SI
13335 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13336 (match_operand:SI 2 "reg_or_short_operand" "")))
13337 (match_operand:SI 3 "gpc_reg_operand" ""))
13338 (const_int 0)))
13339 (set (match_operand:SI 0 "gpc_reg_operand" "")
13340 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13341 "TARGET_32BIT && reload_completed"
13342 [(set (match_dup 0)
13343 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13344 (match_dup 3)))
13345 (set (match_dup 4)
13346 (compare:CC (match_dup 0)
13347 (const_int 0)))]
13348 "")
13350 (define_insn_and_split "*ltu<mode>"
13351 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13352 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13353 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13354 ""
13355 "#"
13356 ""
13357 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13358 (set (match_dup 0) (neg:P (match_dup 0)))]
13359 "")
13361 (define_insn_and_split "*ltu<mode>_compare"
13362 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13363 (compare:CC
13364 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13365 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13366 (const_int 0)))
13367 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13368 (ltu:P (match_dup 1) (match_dup 2)))]
13369 ""
13370 "#"
13371 ""
13372 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13373 (parallel [(set (match_dup 3)
13374 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13375 (set (match_dup 0) (neg:P (match_dup 0)))])]
13376 "")
13378 (define_insn_and_split "*plus_ltu<mode>"
13379 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13380 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13381 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13382 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13383 ""
13384 "#"
13385 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13386 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13387 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13388 "")
13390 (define_insn_and_split "*plus_ltu<mode>_compare"
13391 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13392 (compare:CC
13393 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13394 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13395 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13396 (const_int 0)))
13397 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13398 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13399 ""
13400 "#"
13401 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13402 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13403 (parallel [(set (match_dup 4)
13404 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13405 (const_int 0)))
13406 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13407 "")
13409 (define_insn "*neg_ltu<mode>"
13410 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13411 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13412 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13413 ""
13414 "@
13415 subfc %0,%2,%1\;subfe %0,%0,%0
13416 addic %0,%1,%n2\;subfe %0,%0,%0"
13417 [(set_attr "type" "two")
13418 (set_attr "length" "8")])
13420 (define_insn "*geu<mode>"
13421 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13422 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13423 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13424 ""
13425 "@
13426 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13427 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13428 [(set_attr "type" "three")
13429 (set_attr "length" "12")])
13431 (define_insn "*geu<mode>_compare"
13432 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13433 (compare:CC
13434 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13435 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13436 (const_int 0)))
13437 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13438 (geu:P (match_dup 1) (match_dup 2)))]
13439 ""
13440 "@
13441 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13442 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13443 #
13444 #"
13445 [(set_attr "type" "compare")
13446 (set_attr "length" "12,12,16,16")])
13448 (define_split
13449 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13450 (compare:CC
13451 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13452 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13453 (const_int 0)))
13454 (set (match_operand:P 0 "gpc_reg_operand" "")
13455 (geu:P (match_dup 1) (match_dup 2)))]
13456 "reload_completed"
13457 [(set (match_dup 0)
13458 (geu:P (match_dup 1) (match_dup 2)))
13459 (set (match_dup 3)
13460 (compare:CC (match_dup 0)
13461 (const_int 0)))]
13462 "")
13464 (define_insn "*plus_geu<mode>"
13465 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13466 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13467 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13468 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13469 ""
13470 "@
13471 subfc %0,%2,%1\;addze %0,%3
13472 addic %0,%1,%n2\;addze %0,%3"
13473 [(set_attr "type" "two")
13474 (set_attr "length" "8")])
13476 (define_insn ""
13477 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13478 (compare:CC
13479 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13480 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13481 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13482 (const_int 0)))
13483 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13484 "TARGET_32BIT"
13485 "@
13486 subfc %4,%2,%1\;addze. %4,%3
13487 addic %4,%1,%n2\;addze. %4,%3
13488 #
13489 #"
13490 [(set_attr "type" "compare")
13491 (set_attr "length" "8,8,12,12")])
13493 (define_split
13494 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13495 (compare:CC
13496 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13497 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13498 (match_operand:SI 3 "gpc_reg_operand" ""))
13499 (const_int 0)))
13500 (clobber (match_scratch:SI 4 ""))]
13501 "TARGET_32BIT && reload_completed"
13502 [(set (match_dup 4)
13503 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13504 (match_dup 3)))
13505 (set (match_dup 0)
13506 (compare:CC (match_dup 4)
13507 (const_int 0)))]
13508 "")
13510 (define_insn ""
13511 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13512 (compare:CC
13513 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13514 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13515 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13516 (const_int 0)))
13517 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13518 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13519 "TARGET_32BIT"
13520 "@
13521 subfc %0,%2,%1\;addze. %0,%3
13522 addic %0,%1,%n2\;addze. %0,%3
13523 #
13524 #"
13525 [(set_attr "type" "compare")
13526 (set_attr "length" "8,8,12,12")])
13528 (define_split
13529 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13530 (compare:CC
13531 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13532 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13533 (match_operand:SI 3 "gpc_reg_operand" ""))
13534 (const_int 0)))
13535 (set (match_operand:SI 0 "gpc_reg_operand" "")
13536 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13537 "TARGET_32BIT && reload_completed"
13538 [(set (match_dup 0)
13539 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13540 (set (match_dup 4)
13541 (compare:CC (match_dup 0)
13542 (const_int 0)))]
13543 "")
13545 (define_insn "*neg_geu<mode>"
13546 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13547 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13548 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13549 ""
13550 "@
13551 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
13552 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
13553 [(set_attr "type" "three")
13554 (set_attr "length" "12")])
13556 (define_insn "*and_neg_geu<mode>"
13557 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13558 (and:P (neg:P
13559 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13560 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13561 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13562 ""
13563 "@
13564 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
13565 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
13566 [(set_attr "type" "three")
13567 (set_attr "length" "12")])
13569 (define_insn ""
13570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13571 (compare:CC
13572 (and:SI (neg:SI
13573 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13574 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13575 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13576 (const_int 0)))
13577 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13578 "TARGET_32BIT"
13579 "@
13580 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
13581 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
13582 #
13583 #"
13584 [(set_attr "type" "compare")
13585 (set_attr "length" "12,12,16,16")])
13587 (define_split
13588 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13589 (compare:CC
13590 (and:SI (neg:SI
13591 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13592 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13593 (match_operand:SI 3 "gpc_reg_operand" ""))
13594 (const_int 0)))
13595 (clobber (match_scratch:SI 4 ""))]
13596 "TARGET_32BIT && reload_completed"
13597 [(set (match_dup 4)
13598 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13599 (match_dup 3)))
13600 (set (match_dup 0)
13601 (compare:CC (match_dup 4)
13602 (const_int 0)))]
13603 "")
13605 (define_insn ""
13606 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13607 (compare:CC
13608 (and:SI (neg:SI
13609 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13610 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13611 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13612 (const_int 0)))
13613 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13614 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13615 "TARGET_32BIT"
13616 "@
13617 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
13618 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
13619 #
13620 #"
13621 [(set_attr "type" "compare")
13622 (set_attr "length" "12,12,16,16")])
13624 (define_split
13625 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13626 (compare:CC
13627 (and:SI (neg:SI
13628 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13629 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13630 (match_operand:SI 3 "gpc_reg_operand" ""))
13631 (const_int 0)))
13632 (set (match_operand:SI 0 "gpc_reg_operand" "")
13633 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13634 "TARGET_32BIT && reload_completed"
13635 [(set (match_dup 0)
13636 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13637 (set (match_dup 4)
13638 (compare:CC (match_dup 0)
13639 (const_int 0)))]
13640 "")
13642 (define_insn "*plus_gt0<mode>"
13643 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13644 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13645 (const_int 0))
13646 (match_operand:P 2 "gpc_reg_operand" "r")))]
13647 ""
13648 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13649 [(set_attr "type" "three")
13650 (set_attr "length" "12")])
13652 (define_insn ""
13653 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13654 (compare:CC
13655 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13656 (const_int 0))
13657 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13658 (const_int 0)))
13659 (clobber (match_scratch:SI 3 "=&r,&r"))]
13660 "TARGET_32BIT"
13661 "@
13662 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13663 #"
13664 [(set_attr "type" "compare")
13665 (set_attr "length" "12,16")])
13667 (define_split
13668 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13669 (compare:CC
13670 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13671 (const_int 0))
13672 (match_operand:SI 2 "gpc_reg_operand" ""))
13673 (const_int 0)))
13674 (clobber (match_scratch:SI 3 ""))]
13675 "TARGET_32BIT && reload_completed"
13676 [(set (match_dup 3)
13677 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13678 (match_dup 2)))
13679 (set (match_dup 0)
13680 (compare:CC (match_dup 3)
13681 (const_int 0)))]
13682 "")
13684 (define_insn ""
13685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13686 (compare:CC
13687 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13688 (const_int 0))
13689 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13690 (const_int 0)))
13691 (clobber (match_scratch:DI 3 "=&r,&r"))]
13692 "TARGET_64BIT"
13693 "@
13694 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13695 #"
13696 [(set_attr "type" "compare")
13697 (set_attr "length" "12,16")])
13699 (define_split
13700 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13701 (compare:CC
13702 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13703 (const_int 0))
13704 (match_operand:DI 2 "gpc_reg_operand" ""))
13705 (const_int 0)))
13706 (clobber (match_scratch:DI 3 ""))]
13707 "TARGET_64BIT && reload_completed"
13708 [(set (match_dup 3)
13709 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13710 (match_dup 2)))
13711 (set (match_dup 0)
13712 (compare:CC (match_dup 3)
13713 (const_int 0)))]
13714 "")
13716 (define_insn ""
13717 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13718 (compare:CC
13719 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13720 (const_int 0))
13721 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13722 (const_int 0)))
13723 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13724 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13725 "TARGET_32BIT"
13726 "@
13727 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13728 #"
13729 [(set_attr "type" "compare")
13730 (set_attr "length" "12,16")])
13732 (define_split
13733 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13734 (compare:CC
13735 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13736 (const_int 0))
13737 (match_operand:SI 2 "gpc_reg_operand" ""))
13738 (const_int 0)))
13739 (set (match_operand:SI 0 "gpc_reg_operand" "")
13740 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13741 "TARGET_32BIT && reload_completed"
13742 [(set (match_dup 0)
13743 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13744 (set (match_dup 3)
13745 (compare:CC (match_dup 0)
13746 (const_int 0)))]
13747 "")
13749 (define_insn ""
13750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13751 (compare:CC
13752 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13753 (const_int 0))
13754 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13755 (const_int 0)))
13756 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13757 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13758 "TARGET_64BIT"
13759 "@
13760 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13761 #"
13762 [(set_attr "type" "compare")
13763 (set_attr "length" "12,16")])
13765 (define_split
13766 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13767 (compare:CC
13768 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13769 (const_int 0))
13770 (match_operand:DI 2 "gpc_reg_operand" ""))
13771 (const_int 0)))
13772 (set (match_operand:DI 0 "gpc_reg_operand" "")
13773 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13774 "TARGET_64BIT && reload_completed"
13775 [(set (match_dup 0)
13776 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13777 (set (match_dup 3)
13778 (compare:CC (match_dup 0)
13779 (const_int 0)))]
13780 "")
13782 (define_insn_and_split "*gtu<mode>"
13783 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13784 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13785 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13786 ""
13787 "#"
13788 ""
13789 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13790 (set (match_dup 0) (neg:P (match_dup 0)))]
13791 "")
13793 (define_insn_and_split "*gtu<mode>_compare"
13794 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13795 (compare:CC
13796 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13797 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13798 (const_int 0)))
13799 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13800 (gtu:P (match_dup 1) (match_dup 2)))]
13801 ""
13802 "#"
13803 ""
13804 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13805 (parallel [(set (match_dup 3)
13806 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13807 (set (match_dup 0) (neg:P (match_dup 0)))])]
13808 "")
13810 (define_insn_and_split "*plus_gtu<mode>"
13811 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13812 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13813 (match_operand:P 2 "reg_or_short_operand" "rI"))
13814 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13815 ""
13816 "#"
13817 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13818 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13819 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13820 "")
13822 (define_insn_and_split "*plus_gtu<mode>_compare"
13823 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13824 (compare:CC
13825 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13826 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13827 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13828 (const_int 0)))
13829 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13830 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13831 ""
13832 "#"
13833 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13834 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13835 (parallel [(set (match_dup 4)
13836 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13837 (const_int 0)))
13838 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13839 "")
13841 (define_insn "*neg_gtu<mode>"
13842 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13843 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13844 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13845 ""
13846 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13847 [(set_attr "type" "two")
13848 (set_attr "length" "8")])
13850 \f
13851 ;; Define both directions of branch and return. If we need a reload
13852 ;; register, we'd rather use CR0 since it is much easier to copy a
13853 ;; register CC value to there.
13855 (define_insn ""
13856 [(set (pc)
13857 (if_then_else (match_operator 1 "branch_comparison_operator"
13858 [(match_operand 2
13859 "cc_reg_operand" "y")
13860 (const_int 0)])
13861 (label_ref (match_operand 0 "" ""))
13862 (pc)))]
13863 ""
13864 "*
13865 {
13866 return output_cbranch (operands[1], \"%l0\", 0, insn);
13867 }"
13868 [(set_attr "type" "branch")])
13870 (define_insn ""
13871 [(set (pc)
13872 (if_then_else (match_operator 0 "branch_comparison_operator"
13873 [(match_operand 1
13874 "cc_reg_operand" "y")
13875 (const_int 0)])
13876 (any_return)
13877 (pc)))]
13878 "<return_pred>"
13879 "*
13880 {
13881 return output_cbranch (operands[0], NULL, 0, insn);
13882 }"
13883 [(set_attr "type" "jmpreg")
13884 (set_attr "length" "4")])
13886 (define_insn ""
13887 [(set (pc)
13888 (if_then_else (match_operator 1 "branch_comparison_operator"
13889 [(match_operand 2
13890 "cc_reg_operand" "y")
13891 (const_int 0)])
13892 (pc)
13893 (label_ref (match_operand 0 "" ""))))]
13894 ""
13895 "*
13896 {
13897 return output_cbranch (operands[1], \"%l0\", 1, insn);
13898 }"
13899 [(set_attr "type" "branch")])
13901 (define_insn ""
13902 [(set (pc)
13903 (if_then_else (match_operator 0 "branch_comparison_operator"
13904 [(match_operand 1
13905 "cc_reg_operand" "y")
13906 (const_int 0)])
13907 (pc)
13908 (any_return)))]
13909 "<return_pred>"
13910 "*
13911 {
13912 return output_cbranch (operands[0], NULL, 1, insn);
13913 }"
13914 [(set_attr "type" "jmpreg")
13915 (set_attr "length" "4")])
13917 ;; Logic on condition register values.
13919 ; This pattern matches things like
13920 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13921 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13922 ; (const_int 1)))
13923 ; which are generated by the branch logic.
13924 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13926 (define_insn "*cceq_ior_compare"
13927 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13928 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13929 [(match_operator:SI 2
13930 "branch_positive_comparison_operator"
13931 [(match_operand 3
13932 "cc_reg_operand" "y,y")
13933 (const_int 0)])
13934 (match_operator:SI 4
13935 "branch_positive_comparison_operator"
13936 [(match_operand 5
13937 "cc_reg_operand" "0,y")
13938 (const_int 0)])])
13939 (const_int 1)))]
13940 ""
13941 "cr%q1 %E0,%j2,%j4"
13942 [(set_attr "type" "cr_logical,delayed_cr")])
13944 ; Why is the constant -1 here, but 1 in the previous pattern?
13945 ; Because ~1 has all but the low bit set.
13946 (define_insn ""
13947 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13948 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13949 [(not:SI (match_operator:SI 2
13950 "branch_positive_comparison_operator"
13951 [(match_operand 3
13952 "cc_reg_operand" "y,y")
13953 (const_int 0)]))
13954 (match_operator:SI 4
13955 "branch_positive_comparison_operator"
13956 [(match_operand 5
13957 "cc_reg_operand" "0,y")
13958 (const_int 0)])])
13959 (const_int -1)))]
13960 ""
13961 "cr%q1 %E0,%j2,%j4"
13962 [(set_attr "type" "cr_logical,delayed_cr")])
13964 (define_insn "*cceq_rev_compare"
13965 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13966 (compare:CCEQ (match_operator:SI 1
13967 "branch_positive_comparison_operator"
13968 [(match_operand 2
13969 "cc_reg_operand" "0,y")
13970 (const_int 0)])
13971 (const_int 0)))]
13972 ""
13973 "crnot %E0,%j1"
13974 [(set_attr "type" "cr_logical,delayed_cr")])
13976 ;; If we are comparing the result of two comparisons, this can be done
13977 ;; using creqv or crxor.
13979 (define_insn_and_split ""
13980 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13981 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13982 [(match_operand 2 "cc_reg_operand" "y")
13983 (const_int 0)])
13984 (match_operator 3 "branch_comparison_operator"
13985 [(match_operand 4 "cc_reg_operand" "y")
13986 (const_int 0)])))]
13987 ""
13988 "#"
13989 ""
13990 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13991 (match_dup 5)))]
13992 "
13993 {
13994 int positive_1, positive_2;
13996 positive_1 = branch_positive_comparison_operator (operands[1],
13997 GET_MODE (operands[1]));
13998 positive_2 = branch_positive_comparison_operator (operands[3],
13999 GET_MODE (operands[3]));
14001 if (! positive_1)
14002 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14003 GET_CODE (operands[1])),
14004 SImode,
14005 operands[2], const0_rtx);
14006 else if (GET_MODE (operands[1]) != SImode)
14007 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14008 operands[2], const0_rtx);
14010 if (! positive_2)
14011 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14012 GET_CODE (operands[3])),
14013 SImode,
14014 operands[4], const0_rtx);
14015 else if (GET_MODE (operands[3]) != SImode)
14016 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14017 operands[4], const0_rtx);
14019 if (positive_1 == positive_2)
14020 {
14021 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14022 operands[5] = constm1_rtx;
14023 }
14024 else
14025 {
14026 operands[5] = const1_rtx;
14027 }
14028 }")
14030 ;; Unconditional branch and return.
14032 (define_insn "jump"
14033 [(set (pc)
14034 (label_ref (match_operand 0 "" "")))]
14035 ""
14036 "b %l0"
14037 [(set_attr "type" "branch")])
14039 (define_insn "<return_str>return"
14040 [(any_return)]
14041 "<return_pred>"
14042 "blr"
14043 [(set_attr "type" "jmpreg")])
14045 (define_expand "indirect_jump"
14046 [(set (pc) (match_operand 0 "register_operand" ""))])
14048 (define_insn "*indirect_jump<mode>"
14049 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14050 ""
14051 "@
14052 bctr
14053 blr"
14054 [(set_attr "type" "jmpreg")])
14056 ;; Table jump for switch statements:
14057 (define_expand "tablejump"
14058 [(use (match_operand 0 "" ""))
14059 (use (label_ref (match_operand 1 "" "")))]
14060 ""
14061 "
14062 {
14063 if (TARGET_32BIT)
14064 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14065 else
14066 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14067 DONE;
14068 }")
14070 (define_expand "tablejumpsi"
14071 [(set (match_dup 3)
14072 (plus:SI (match_operand:SI 0 "" "")
14073 (match_dup 2)))
14074 (parallel [(set (pc) (match_dup 3))
14075 (use (label_ref (match_operand 1 "" "")))])]
14076 "TARGET_32BIT"
14077 "
14078 { operands[0] = force_reg (SImode, operands[0]);
14079 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14080 operands[3] = gen_reg_rtx (SImode);
14081 }")
14083 (define_expand "tablejumpdi"
14084 [(set (match_dup 4)
14085 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14086 (set (match_dup 3)
14087 (plus:DI (match_dup 4)
14088 (match_dup 2)))
14089 (parallel [(set (pc) (match_dup 3))
14090 (use (label_ref (match_operand 1 "" "")))])]
14091 "TARGET_64BIT"
14092 "
14093 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14094 operands[3] = gen_reg_rtx (DImode);
14095 operands[4] = gen_reg_rtx (DImode);
14096 }")
14098 (define_insn "*tablejump<mode>_internal1"
14099 [(set (pc)
14100 (match_operand:P 0 "register_operand" "c,*l"))
14101 (use (label_ref (match_operand 1 "" "")))]
14102 ""
14103 "@
14104 bctr
14105 blr"
14106 [(set_attr "type" "jmpreg")])
14108 (define_insn "nop"
14109 [(const_int 0)]
14110 ""
14111 "nop")
14113 (define_insn "group_ending_nop"
14114 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14115 ""
14116 "*
14117 {
14118 if (rs6000_cpu_attr == CPU_POWER6)
14119 return \"ori 1,1,0\";
14120 return \"ori 2,2,0\";
14121 }")
14122 \f
14123 ;; Define the subtract-one-and-jump insns, starting with the template
14124 ;; so loop.c knows what to generate.
14126 (define_expand "doloop_end"
14127 [(use (match_operand 0 "" "")) ; loop pseudo
14128 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14129 (use (match_operand 2 "" "")) ; max iterations
14130 (use (match_operand 3 "" "")) ; loop level
14131 (use (match_operand 4 "" "")) ; label
14132 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
14133 ""
14134 "
14135 {
14136 /* Only use this on innermost loops. */
14137 if (INTVAL (operands[3]) > 1)
14138 FAIL;
14139 if (TARGET_64BIT)
14140 {
14141 if (GET_MODE (operands[0]) != DImode)
14142 FAIL;
14143 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14144 }
14145 else
14146 {
14147 if (GET_MODE (operands[0]) != SImode)
14148 FAIL;
14149 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14150 }
14151 DONE;
14152 }")
14154 (define_expand "ctr<mode>"
14155 [(parallel [(set (pc)
14156 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14157 (const_int 1))
14158 (label_ref (match_operand 1 "" ""))
14159 (pc)))
14160 (set (match_dup 0)
14161 (plus:P (match_dup 0)
14162 (const_int -1)))
14163 (clobber (match_scratch:CC 2 ""))
14164 (clobber (match_scratch:P 3 ""))])]
14165 ""
14166 "")
14168 ;; We need to be able to do this for any operand, including MEM, or we
14169 ;; will cause reload to blow up since we don't allow output reloads on
14170 ;; JUMP_INSNs.
14171 ;; For the length attribute to be calculated correctly, the
14172 ;; label MUST be operand 0.
14174 (define_insn "*ctr<mode>_internal1"
14175 [(set (pc)
14176 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14177 (const_int 1))
14178 (label_ref (match_operand 0 "" ""))
14179 (pc)))
14180 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14181 (plus:P (match_dup 1)
14182 (const_int -1)))
14183 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14184 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14185 ""
14186 "*
14187 {
14188 if (which_alternative != 0)
14189 return \"#\";
14190 else if (get_attr_length (insn) == 4)
14191 return \"bdnz %l0\";
14192 else
14193 return \"bdz $+8\;b %l0\";
14194 }"
14195 [(set_attr "type" "branch")
14196 (set_attr "length" "*,12,16,16")])
14198 (define_insn "*ctr<mode>_internal2"
14199 [(set (pc)
14200 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14201 (const_int 1))
14202 (pc)
14203 (label_ref (match_operand 0 "" ""))))
14204 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14205 (plus:P (match_dup 1)
14206 (const_int -1)))
14207 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14208 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14209 ""
14210 "*
14211 {
14212 if (which_alternative != 0)
14213 return \"#\";
14214 else if (get_attr_length (insn) == 4)
14215 return \"bdz %l0\";
14216 else
14217 return \"bdnz $+8\;b %l0\";
14218 }"
14219 [(set_attr "type" "branch")
14220 (set_attr "length" "*,12,16,16")])
14222 ;; Similar but use EQ
14224 (define_insn "*ctr<mode>_internal5"
14225 [(set (pc)
14226 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14227 (const_int 1))
14228 (label_ref (match_operand 0 "" ""))
14229 (pc)))
14230 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14231 (plus:P (match_dup 1)
14232 (const_int -1)))
14233 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14234 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14235 ""
14236 "*
14237 {
14238 if (which_alternative != 0)
14239 return \"#\";
14240 else if (get_attr_length (insn) == 4)
14241 return \"bdz %l0\";
14242 else
14243 return \"bdnz $+8\;b %l0\";
14244 }"
14245 [(set_attr "type" "branch")
14246 (set_attr "length" "*,12,16,16")])
14248 (define_insn "*ctr<mode>_internal6"
14249 [(set (pc)
14250 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14251 (const_int 1))
14252 (pc)
14253 (label_ref (match_operand 0 "" ""))))
14254 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14255 (plus:P (match_dup 1)
14256 (const_int -1)))
14257 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14258 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14259 ""
14260 "*
14261 {
14262 if (which_alternative != 0)
14263 return \"#\";
14264 else if (get_attr_length (insn) == 4)
14265 return \"bdnz %l0\";
14266 else
14267 return \"bdz $+8\;b %l0\";
14268 }"
14269 [(set_attr "type" "branch")
14270 (set_attr "length" "*,12,16,16")])
14272 ;; Now the splitters if we could not allocate the CTR register
14274 (define_split
14275 [(set (pc)
14276 (if_then_else (match_operator 2 "comparison_operator"
14277 [(match_operand:P 1 "gpc_reg_operand" "")
14278 (const_int 1)])
14279 (match_operand 5 "" "")
14280 (match_operand 6 "" "")))
14281 (set (match_operand:P 0 "gpc_reg_operand" "")
14282 (plus:P (match_dup 1) (const_int -1)))
14283 (clobber (match_scratch:CC 3 ""))
14284 (clobber (match_scratch:P 4 ""))]
14285 "reload_completed"
14286 [(parallel [(set (match_dup 3)
14287 (compare:CC (plus:P (match_dup 1)
14288 (const_int -1))
14289 (const_int 0)))
14290 (set (match_dup 0)
14291 (plus:P (match_dup 1)
14292 (const_int -1)))])
14293 (set (pc) (if_then_else (match_dup 7)
14294 (match_dup 5)
14295 (match_dup 6)))]
14296 "
14297 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14298 operands[3], const0_rtx); }")
14300 (define_split
14301 [(set (pc)
14302 (if_then_else (match_operator 2 "comparison_operator"
14303 [(match_operand:P 1 "gpc_reg_operand" "")
14304 (const_int 1)])
14305 (match_operand 5 "" "")
14306 (match_operand 6 "" "")))
14307 (set (match_operand:P 0 "nonimmediate_operand" "")
14308 (plus:P (match_dup 1) (const_int -1)))
14309 (clobber (match_scratch:CC 3 ""))
14310 (clobber (match_scratch:P 4 ""))]
14311 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14312 [(parallel [(set (match_dup 3)
14313 (compare:CC (plus:P (match_dup 1)
14314 (const_int -1))
14315 (const_int 0)))
14316 (set (match_dup 4)
14317 (plus:P (match_dup 1)
14318 (const_int -1)))])
14319 (set (match_dup 0)
14320 (match_dup 4))
14321 (set (pc) (if_then_else (match_dup 7)
14322 (match_dup 5)
14323 (match_dup 6)))]
14324 "
14325 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14326 operands[3], const0_rtx); }")
14327 \f
14328 (define_insn "trap"
14329 [(trap_if (const_int 1) (const_int 0))]
14330 ""
14331 "trap"
14332 [(set_attr "type" "trap")])
14334 (define_expand "ctrap<mode>4"
14335 [(trap_if (match_operator 0 "ordered_comparison_operator"
14336 [(match_operand:GPR 1 "register_operand")
14337 (match_operand:GPR 2 "reg_or_short_operand")])
14338 (match_operand 3 "zero_constant" ""))]
14339 ""
14340 "")
14342 (define_insn ""
14343 [(trap_if (match_operator 0 "ordered_comparison_operator"
14344 [(match_operand:GPR 1 "register_operand" "r")
14345 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14346 (const_int 0))]
14347 ""
14348 "t<wd>%V0%I2 %1,%2"
14349 [(set_attr "type" "trap")])
14350 \f
14351 ;; Insns related to generating the function prologue and epilogue.
14353 (define_expand "prologue"
14354 [(use (const_int 0))]
14355 ""
14356 {
14357 rs6000_emit_prologue ();
14358 if (!TARGET_SCHED_PROLOG)
14359 emit_insn (gen_blockage ());
14360 DONE;
14361 })
14363 (define_insn "*movesi_from_cr_one"
14364 [(match_parallel 0 "mfcr_operation"
14365 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14366 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14367 (match_operand 3 "immediate_operand" "n")]
14368 UNSPEC_MOVESI_FROM_CR))])]
14369 "TARGET_MFCRF"
14370 "*
14371 {
14372 int mask = 0;
14373 int i;
14374 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14375 {
14376 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14377 operands[4] = GEN_INT (mask);
14378 output_asm_insn (\"mfcr %1,%4\", operands);
14379 }
14380 return \"\";
14381 }"
14382 [(set_attr "type" "mfcrf")])
14384 (define_insn "movesi_from_cr"
14385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14386 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14387 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14388 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14389 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14390 UNSPEC_MOVESI_FROM_CR))]
14391 ""
14392 "mfcr %0"
14393 [(set_attr "type" "mfcr")])
14395 (define_insn "*stmw"
14396 [(match_parallel 0 "stmw_operation"
14397 [(set (match_operand:SI 1 "memory_operand" "=m")
14398 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14399 "TARGET_MULTIPLE"
14400 "stmw %2,%1"
14401 [(set_attr "type" "store_ux")])
14403 ; The following comment applies to:
14404 ; save_gpregs_*
14405 ; save_fpregs_*
14406 ; restore_gpregs*
14407 ; return_and_restore_gpregs*
14408 ; return_and_restore_fpregs*
14409 ; return_and_restore_fpregs_aix*
14410 ;
14411 ; The out-of-line save / restore functions expects one input argument.
14412 ; Since those are not standard call_insn's, we must avoid using
14413 ; MATCH_OPERAND for that argument. That way the register rename
14414 ; optimization will not try to rename this register.
14415 ; Each pattern is repeated for each possible register number used in
14416 ; various ABIs (r11, r1, and for some functions r12)
14418 (define_insn "*save_gpregs_<mode>_r11"
14419 [(match_parallel 0 "any_parallel_operand"
14420 [(clobber (reg:P 65))
14421 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14422 (use (reg:P 11))
14423 (set (match_operand:P 2 "memory_operand" "=m")
14424 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14425 ""
14426 "bl %1"
14427 [(set_attr "type" "branch")
14428 (set_attr "length" "4")])
14430 (define_insn "*save_gpregs_<mode>_r12"
14431 [(match_parallel 0 "any_parallel_operand"
14432 [(clobber (reg:P 65))
14433 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14434 (use (reg:P 12))
14435 (set (match_operand:P 2 "memory_operand" "=m")
14436 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14437 ""
14438 "bl %1"
14439 [(set_attr "type" "branch")
14440 (set_attr "length" "4")])
14442 (define_insn "*save_gpregs_<mode>_r1"
14443 [(match_parallel 0 "any_parallel_operand"
14444 [(clobber (reg:P 65))
14445 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14446 (use (reg:P 1))
14447 (set (match_operand:P 2 "memory_operand" "=m")
14448 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14449 ""
14450 "bl %1"
14451 [(set_attr "type" "branch")
14452 (set_attr "length" "4")])
14454 (define_insn "*save_fpregs_<mode>_r11"
14455 [(match_parallel 0 "any_parallel_operand"
14456 [(clobber (reg:P 65))
14457 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14458 (use (reg:P 11))
14459 (set (match_operand:DF 2 "memory_operand" "=m")
14460 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14461 ""
14462 "bl %1"
14463 [(set_attr "type" "branch")
14464 (set_attr "length" "4")])
14466 (define_insn "*save_fpregs_<mode>_r12"
14467 [(match_parallel 0 "any_parallel_operand"
14468 [(clobber (reg:P 65))
14469 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14470 (use (reg:P 12))
14471 (set (match_operand:DF 2 "memory_operand" "=m")
14472 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14473 ""
14474 "bl %1"
14475 [(set_attr "type" "branch")
14476 (set_attr "length" "4")])
14478 (define_insn "*save_fpregs_<mode>_r1"
14479 [(match_parallel 0 "any_parallel_operand"
14480 [(clobber (reg:P 65))
14481 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14482 (use (reg:P 1))
14483 (set (match_operand:DF 2 "memory_operand" "=m")
14484 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14485 ""
14486 "bl %1"
14487 [(set_attr "type" "branch")
14488 (set_attr "length" "4")])
14490 ; This is to explain that changes to the stack pointer should
14491 ; not be moved over loads from or stores to stack memory.
14492 (define_insn "stack_tie"
14493 [(match_parallel 0 "tie_operand"
14494 [(set (mem:BLK (reg 1)) (const_int 0))])]
14495 ""
14496 ""
14497 [(set_attr "length" "0")])
14499 (define_expand "epilogue"
14500 [(use (const_int 0))]
14501 ""
14502 {
14503 if (!TARGET_SCHED_PROLOG)
14504 emit_insn (gen_blockage ());
14505 rs6000_emit_epilogue (FALSE);
14506 DONE;
14507 })
14509 ; On some processors, doing the mtcrf one CC register at a time is
14510 ; faster (like on the 604e). On others, doing them all at once is
14511 ; faster; for instance, on the 601 and 750.
14513 (define_expand "movsi_to_cr_one"
14514 [(set (match_operand:CC 0 "cc_reg_operand" "")
14515 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14516 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14517 ""
14518 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14520 (define_insn "*movsi_to_cr"
14521 [(match_parallel 0 "mtcrf_operation"
14522 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14523 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14524 (match_operand 3 "immediate_operand" "n")]
14525 UNSPEC_MOVESI_TO_CR))])]
14526 ""
14527 "*
14528 {
14529 int mask = 0;
14530 int i;
14531 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14532 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14533 operands[4] = GEN_INT (mask);
14534 return \"mtcrf %4,%2\";
14535 }"
14536 [(set_attr "type" "mtcr")])
14538 (define_insn "*mtcrfsi"
14539 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14540 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14541 (match_operand 2 "immediate_operand" "n")]
14542 UNSPEC_MOVESI_TO_CR))]
14543 "GET_CODE (operands[0]) == REG
14544 && CR_REGNO_P (REGNO (operands[0]))
14545 && GET_CODE (operands[2]) == CONST_INT
14546 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14547 "mtcrf %R0,%1"
14548 [(set_attr "type" "mtcr")])
14550 ; The load-multiple instructions have similar properties.
14551 ; Note that "load_multiple" is a name known to the machine-independent
14552 ; code that actually corresponds to the PowerPC load-string.
14554 (define_insn "*lmw"
14555 [(match_parallel 0 "lmw_operation"
14556 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14557 (match_operand:SI 2 "memory_operand" "m"))])]
14558 "TARGET_MULTIPLE"
14559 "lmw %1,%2"
14560 [(set_attr "type" "load_ux")
14561 (set_attr "cell_micro" "always")])
14563 (define_insn "*return_internal_<mode>"
14564 [(simple_return)
14565 (use (match_operand:P 0 "register_operand" "lc"))]
14566 ""
14567 "b%T0"
14568 [(set_attr "type" "jmpreg")])
14570 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14571 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14573 ; The following comment applies to:
14574 ; save_gpregs_*
14575 ; save_fpregs_*
14576 ; restore_gpregs*
14577 ; return_and_restore_gpregs*
14578 ; return_and_restore_fpregs*
14579 ; return_and_restore_fpregs_aix*
14580 ;
14581 ; The out-of-line save / restore functions expects one input argument.
14582 ; Since those are not standard call_insn's, we must avoid using
14583 ; MATCH_OPERAND for that argument. That way the register rename
14584 ; optimization will not try to rename this register.
14585 ; Each pattern is repeated for each possible register number used in
14586 ; various ABIs (r11, r1, and for some functions r12)
14588 (define_insn "*restore_gpregs_<mode>_r11"
14589 [(match_parallel 0 "any_parallel_operand"
14590 [(clobber (match_operand:P 1 "register_operand" "=l"))
14591 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14592 (use (reg:P 11))
14593 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14594 (match_operand:P 4 "memory_operand" "m"))])]
14595 ""
14596 "bl %2"
14597 [(set_attr "type" "branch")
14598 (set_attr "length" "4")])
14600 (define_insn "*restore_gpregs_<mode>_r12"
14601 [(match_parallel 0 "any_parallel_operand"
14602 [(clobber (match_operand:P 1 "register_operand" "=l"))
14603 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14604 (use (reg:P 12))
14605 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14606 (match_operand:P 4 "memory_operand" "m"))])]
14607 ""
14608 "bl %2"
14609 [(set_attr "type" "branch")
14610 (set_attr "length" "4")])
14612 (define_insn "*restore_gpregs_<mode>_r1"
14613 [(match_parallel 0 "any_parallel_operand"
14614 [(clobber (match_operand:P 1 "register_operand" "=l"))
14615 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14616 (use (reg:P 1))
14617 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14618 (match_operand:P 4 "memory_operand" "m"))])]
14619 ""
14620 "bl %2"
14621 [(set_attr "type" "branch")
14622 (set_attr "length" "4")])
14624 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14625 [(match_parallel 0 "any_parallel_operand"
14626 [(return)
14627 (clobber (match_operand:P 1 "register_operand" "=l"))
14628 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14629 (use (reg:P 11))
14630 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14631 (match_operand:P 4 "memory_operand" "m"))])]
14632 ""
14633 "b %2"
14634 [(set_attr "type" "branch")
14635 (set_attr "length" "4")])
14637 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14638 [(match_parallel 0 "any_parallel_operand"
14639 [(return)
14640 (clobber (match_operand:P 1 "register_operand" "=l"))
14641 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14642 (use (reg:P 12))
14643 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14644 (match_operand:P 4 "memory_operand" "m"))])]
14645 ""
14646 "b %2"
14647 [(set_attr "type" "branch")
14648 (set_attr "length" "4")])
14650 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14651 [(match_parallel 0 "any_parallel_operand"
14652 [(return)
14653 (clobber (match_operand:P 1 "register_operand" "=l"))
14654 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14655 (use (reg:P 1))
14656 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14657 (match_operand:P 4 "memory_operand" "m"))])]
14658 ""
14659 "b %2"
14660 [(set_attr "type" "branch")
14661 (set_attr "length" "4")])
14663 (define_insn "*return_and_restore_fpregs_<mode>_r11"
14664 [(match_parallel 0 "any_parallel_operand"
14665 [(return)
14666 (clobber (match_operand:P 1 "register_operand" "=l"))
14667 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14668 (use (reg:P 11))
14669 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14670 (match_operand:DF 4 "memory_operand" "m"))])]
14671 ""
14672 "b %2"
14673 [(set_attr "type" "branch")
14674 (set_attr "length" "4")])
14676 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14677 [(match_parallel 0 "any_parallel_operand"
14678 [(return)
14679 (clobber (match_operand:P 1 "register_operand" "=l"))
14680 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14681 (use (reg:P 12))
14682 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14683 (match_operand:DF 4 "memory_operand" "m"))])]
14684 ""
14685 "b %2"
14686 [(set_attr "type" "branch")
14687 (set_attr "length" "4")])
14689 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14690 [(match_parallel 0 "any_parallel_operand"
14691 [(return)
14692 (clobber (match_operand:P 1 "register_operand" "=l"))
14693 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14694 (use (reg:P 1))
14695 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14696 (match_operand:DF 4 "memory_operand" "m"))])]
14697 ""
14698 "b %2"
14699 [(set_attr "type" "branch")
14700 (set_attr "length" "4")])
14702 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14703 [(match_parallel 0 "any_parallel_operand"
14704 [(return)
14705 (use (match_operand:P 1 "register_operand" "l"))
14706 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14707 (use (reg:P 11))
14708 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14709 (match_operand:DF 4 "memory_operand" "m"))])]
14710 ""
14711 "b %2"
14712 [(set_attr "type" "branch")
14713 (set_attr "length" "4")])
14715 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14716 [(match_parallel 0 "any_parallel_operand"
14717 [(return)
14718 (use (match_operand:P 1 "register_operand" "l"))
14719 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14720 (use (reg:P 1))
14721 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14722 (match_operand:DF 4 "memory_operand" "m"))])]
14723 ""
14724 "b %2"
14725 [(set_attr "type" "branch")
14726 (set_attr "length" "4")])
14728 ; This is used in compiling the unwind routines.
14729 (define_expand "eh_return"
14730 [(use (match_operand 0 "general_operand" ""))]
14731 ""
14732 "
14733 {
14734 if (TARGET_32BIT)
14735 emit_insn (gen_eh_set_lr_si (operands[0]));
14736 else
14737 emit_insn (gen_eh_set_lr_di (operands[0]));
14738 DONE;
14739 }")
14741 ; We can't expand this before we know where the link register is stored.
14742 (define_insn "eh_set_lr_<mode>"
14743 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14744 UNSPECV_EH_RR)
14745 (clobber (match_scratch:P 1 "=&b"))]
14746 ""
14747 "#")
14749 (define_split
14750 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14751 (clobber (match_scratch 1 ""))]
14752 "reload_completed"
14753 [(const_int 0)]
14754 "
14755 {
14756 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14757 DONE;
14758 }")
14760 (define_insn "prefetch"
14761 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14762 (match_operand:SI 1 "const_int_operand" "n")
14763 (match_operand:SI 2 "const_int_operand" "n"))]
14764 ""
14765 "*
14766 {
14767 if (GET_CODE (operands[0]) == REG)
14768 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14769 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14770 }"
14771 [(set_attr "type" "load")])
14772 \f
14773 (define_insn "bpermd_<mode>"
14774 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14775 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14776 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14777 "TARGET_POPCNTD"
14778 "bpermd %0,%1,%2"
14779 [(set_attr "type" "integer")])
14781 \f
14782 ;; Builtin fma support. Handle
14783 ;; Note that the conditions for expansion are in the FMA_F iterator.
14785 (define_expand "fma<mode>4"
14786 [(set (match_operand:FMA_F 0 "register_operand" "")
14787 (fma:FMA_F
14788 (match_operand:FMA_F 1 "register_operand" "")
14789 (match_operand:FMA_F 2 "register_operand" "")
14790 (match_operand:FMA_F 3 "register_operand" "")))]
14791 ""
14792 "")
14794 ; Altivec only has fma and nfms.
14795 (define_expand "fms<mode>4"
14796 [(set (match_operand:FMA_F 0 "register_operand" "")
14797 (fma:FMA_F
14798 (match_operand:FMA_F 1 "register_operand" "")
14799 (match_operand:FMA_F 2 "register_operand" "")
14800 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14801 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14802 "")
14804 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14805 (define_expand "fnma<mode>4"
14806 [(set (match_operand:FMA_F 0 "register_operand" "")
14807 (neg:FMA_F
14808 (fma:FMA_F
14809 (match_operand:FMA_F 1 "register_operand" "")
14810 (match_operand:FMA_F 2 "register_operand" "")
14811 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14812 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14813 "")
14815 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14816 (define_expand "fnms<mode>4"
14817 [(set (match_operand:FMA_F 0 "register_operand" "")
14818 (neg:FMA_F
14819 (fma:FMA_F
14820 (match_operand:FMA_F 1 "register_operand" "")
14821 (match_operand:FMA_F 2 "register_operand" "")
14822 (match_operand:FMA_F 3 "register_operand" ""))))]
14823 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14824 "")
14826 ; Not an official optab name, but used from builtins.
14827 (define_expand "nfma<mode>4"
14828 [(set (match_operand:FMA_F 0 "register_operand" "")
14829 (neg:FMA_F
14830 (fma:FMA_F
14831 (match_operand:FMA_F 1 "register_operand" "")
14832 (match_operand:FMA_F 2 "register_operand" "")
14833 (match_operand:FMA_F 3 "register_operand" ""))))]
14834 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14835 "")
14837 ; Not an official optab name, but used from builtins.
14838 (define_expand "nfms<mode>4"
14839 [(set (match_operand:FMA_F 0 "register_operand" "")
14840 (neg:FMA_F
14841 (fma:FMA_F
14842 (match_operand:FMA_F 1 "register_operand" "")
14843 (match_operand:FMA_F 2 "register_operand" "")
14844 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14845 ""
14846 "")
14848 (define_expand "rs6000_get_timebase"
14849 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14850 ""
14851 {
14852 if (TARGET_POWERPC64)
14853 emit_insn (gen_rs6000_mftb_di (operands[0]));
14854 else
14855 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14856 DONE;
14857 })
14859 (define_insn "rs6000_get_timebase_ppc32"
14860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14861 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14862 (clobber (match_scratch:SI 1 "=r"))
14863 (clobber (match_scratch:CC 2 "=y"))]
14864 "!TARGET_POWERPC64"
14865 {
14866 if (WORDS_BIG_ENDIAN)
14867 if (TARGET_MFCRF)
14868 {
14869 return "mfspr %0,269\;"
14870 "mfspr %L0,268\;"
14871 "mfspr %1,269\;"
14872 "cmpw %2,%0,%1\;"
14873 "bne- %2,$-16";
14874 }
14875 else
14876 {
14877 return "mftbu %0\;"
14878 "mftb %L0\;"
14879 "mftbu %1\;"
14880 "cmpw %2,%0,%1\;"
14881 "bne- %2,$-16";
14882 }
14883 else
14884 if (TARGET_MFCRF)
14885 {
14886 return "mfspr %L0,269\;"
14887 "mfspr %0,268\;"
14888 "mfspr %1,269\;"
14889 "cmpw %2,%L0,%1\;"
14890 "bne- %2,$-16";
14891 }
14892 else
14893 {
14894 return "mftbu %L0\;"
14895 "mftb %0\;"
14896 "mftbu %1\;"
14897 "cmpw %2,%L0,%1\;"
14898 "bne- %2,$-16";
14899 }
14900 })
14902 (define_insn "rs6000_mftb_<mode>"
14903 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14904 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
14905 ""
14906 {
14907 if (TARGET_MFCRF)
14908 return "mfspr %0,268";
14909 else
14910 return "mftb %0";
14911 })
14913 \f
14915 (include "sync.md")
14916 (include "vector.md")
14917 (include "vsx.md")
14918 (include "altivec.md")
14919 (include "spe.md")
14920 (include "dfp.md")
14921 (include "paired.md")