1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (and (match_code "reg")
120 (match_test "CA_REGNO_P (REGNO (op))")))
122 ;; Return 1 if op is a signed 5-bit constant integer.
123 (define_predicate "s5bit_cint_operand"
124 (and (match_code "const_int")
125 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
127 ;; Return 1 if op is a unsigned 5-bit constant integer.
128 (define_predicate "u5bit_cint_operand"
129 (and (match_code "const_int")
130 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
132 ;; Return 1 if op is a signed 8-bit constant integer.
133 ;; Integer multiplication complete more quickly
134 (define_predicate "s8bit_cint_operand"
135 (and (match_code "const_int")
136 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
138 ;; Return 1 if op is a constant integer that can fit in a D field.
139 (define_predicate "short_cint_operand"
140 (and (match_code "const_int")
141 (match_test "satisfies_constraint_I (op)")))
143 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
144 (define_predicate "u_short_cint_operand"
145 (and (match_code "const_int")
146 (match_test "satisfies_constraint_K (op)")))
148 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
149 (define_predicate "non_short_cint_operand"
150 (and (match_code "const_int")
151 (match_test "(unsigned HOST_WIDE_INT)
152 (INTVAL (op) + 0x8000) >= 0x10000")))
154 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
155 (define_predicate "exact_log2_cint_operand"
156 (and (match_code "const_int")
157 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
159 ;; Match op = 0 or op = 1.
160 (define_predicate "const_0_to_1_operand"
161 (and (match_code "const_int")
162 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
164 ;; Match op = 2 or op = 3.
165 (define_predicate "const_2_to_3_operand"
166 (and (match_code "const_int")
167 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
169 ;; Return 1 if op is a register that is not special.
170 (define_predicate "gpc_reg_operand"
171 (match_operand 0 "register_operand")
173 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
176 if (GET_CODE (op) == SUBREG)
177 op = SUBREG_REG (op);
182 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
185 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
188 ;; Return 1 if op is a register that is a condition register field.
189 (define_predicate "cc_reg_operand"
190 (match_operand 0 "register_operand")
192 if (GET_CODE (op) == SUBREG)
193 op = SUBREG_REG (op);
198 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
201 return CR_REGNO_P (REGNO (op));
204 ;; Return 1 if op is a register that is a condition register field not cr0.
205 (define_predicate "cc_reg_not_cr0_operand"
206 (match_operand 0 "register_operand")
208 if (GET_CODE (op) == SUBREG)
209 op = SUBREG_REG (op);
214 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
217 return CR_REGNO_NOT_CR0_P (REGNO (op));
220 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
221 (define_predicate "cc_reg_not_micro_cr0_operand"
222 (match_operand 0 "register_operand")
224 if (GET_CODE (op) == SUBREG)
225 op = SUBREG_REG (op);
230 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
233 if (rs6000_gen_cell_microcode)
234 return CR_REGNO_NOT_CR0_P (REGNO (op));
236 return CR_REGNO_P (REGNO (op));
239 ;; Return 1 if op is a constant integer valid for D field
240 ;; or non-special register register.
241 (define_predicate "reg_or_short_operand"
242 (if_then_else (match_code "const_int")
243 (match_operand 0 "short_cint_operand")
244 (match_operand 0 "gpc_reg_operand")))
246 ;; Return 1 if op is a constant integer valid whose negation is valid for
247 ;; D field or non-special register register.
248 ;; Do not allow a constant zero because all patterns that call this
249 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
250 ;; or equal to const, which does not work for zero.
251 (define_predicate "reg_or_neg_short_operand"
252 (if_then_else (match_code "const_int")
253 (match_test "satisfies_constraint_P (op)
254 && INTVAL (op) != 0")
255 (match_operand 0 "gpc_reg_operand")))
257 ;; Return 1 if op is a constant integer valid for DS field
258 ;; or non-special register.
259 (define_predicate "reg_or_aligned_short_operand"
260 (if_then_else (match_code "const_int")
261 (and (match_operand 0 "short_cint_operand")
262 (match_test "!(INTVAL (op) & 3)"))
263 (match_operand 0 "gpc_reg_operand")))
265 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
266 ;; or non-special register.
267 (define_predicate "reg_or_u_short_operand"
268 (if_then_else (match_code "const_int")
269 (match_operand 0 "u_short_cint_operand")
270 (match_operand 0 "gpc_reg_operand")))
272 ;; Return 1 if op is any constant integer
273 ;; or non-special register.
274 (define_predicate "reg_or_cint_operand"
275 (ior (match_code "const_int")
276 (match_operand 0 "gpc_reg_operand")))
278 ;; Return 1 if op is a constant integer valid for addition
279 ;; or non-special register.
280 (define_predicate "reg_or_add_cint_operand"
281 (if_then_else (match_code "const_int")
282 (match_test "(unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
283 < (unsigned HOST_WIDE_INT) 0x100000000ll")
284 (match_operand 0 "gpc_reg_operand")))
286 ;; Return 1 if op is a constant integer valid for subtraction
287 ;; or non-special register.
288 (define_predicate "reg_or_sub_cint_operand"
289 (if_then_else (match_code "const_int")
290 (match_test "(unsigned HOST_WIDE_INT)
291 (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
292 < (unsigned HOST_WIDE_INT) 0x100000000ll")
293 (match_operand 0 "gpc_reg_operand")))
295 ;; Return 1 if op is any 32-bit unsigned constant integer
296 ;; or non-special register.
297 (define_predicate "reg_or_logical_cint_operand"
298 (if_then_else (match_code "const_int")
299 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
301 || ((INTVAL (op) & GET_MODE_MASK (mode)
302 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
303 (match_operand 0 "gpc_reg_operand")))
305 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
306 ;; with no more than one instruction per word.
307 (define_predicate "easy_fp_constant"
308 (match_code "const_double")
313 if (GET_MODE (op) != mode
314 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
317 /* Consider all constants with -msoft-float to be easy. */
318 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
319 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
323 /* The constant 0.0 is easy under VSX. */
324 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
325 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
328 if (DECIMAL_FLOAT_MODE_P (mode))
331 /* If we are using V.4 style PIC, consider all constants to be hard. */
332 if (flag_pic && DEFAULT_ABI == ABI_V4)
335 #ifdef TARGET_RELOCATABLE
336 /* Similarly if we are using -mrelocatable, consider all constants
338 if (TARGET_RELOCATABLE)
345 if (TARGET_E500_DOUBLE)
348 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
349 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
351 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
352 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
353 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
354 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
357 /* The constant 0.f is easy under VSX. */
358 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
361 /* Force constants to memory before reload to utilize
362 compress_float_constant.
363 Avoid this when flag_unsafe_math_optimizations is enabled
364 because RDIV division to reciprocal optimization is not able
365 to regenerate the division. */
366 if (TARGET_E500_DOUBLE
367 || (!reload_in_progress && !reload_completed
368 && !flag_unsafe_math_optimizations))
371 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
372 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
374 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
375 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
378 /* The constant 0.f is easy. */
379 if (op == CONST0_RTX (SFmode))
382 /* Force constants to memory before reload to utilize
383 compress_float_constant.
384 Avoid this when flag_unsafe_math_optimizations is enabled
385 because RDIV division to reciprocal optimization is not able
386 to regenerate the division. */
387 if (!reload_in_progress && !reload_completed
388 && !flag_unsafe_math_optimizations)
391 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
392 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
394 return num_insns_constant_wide (k[0]) == 1;
397 return (num_insns_constant (op, DImode) <= 2);
407 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
408 ;; vector register without using memory.
409 (define_predicate "easy_vector_constant"
410 (match_code "const_vector")
412 /* As the paired vectors are actually FPRs it seems that there is
413 no easy way to load a CONST_VECTOR without using memory. */
414 if (TARGET_PAIRED_FLOAT)
417 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
419 if (zero_constant (op, mode))
422 return easy_altivec_constant (op, mode);
425 if (SPE_VECTOR_MODE (mode))
428 if (zero_constant (op, mode))
430 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
433 /* Limit SPE vectors to 15 bits signed. These we can generate with:
438 I don't know how efficient it would be to allow bigger constants,
439 considering we'll have an extra 'ori' for every 'li'. I doubt 5
440 instructions is better than a 64-bit memory load, but I don't
441 have the e500 timing specs. */
442 if (mode == V2SImode)
444 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
445 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
446 return cst >= -0x7fff && cst <= 0x7fff
447 && cst2 >= -0x7fff && cst2 <= 0x7fff;
454 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
455 (define_predicate "easy_vector_constant_add_self"
456 (and (match_code "const_vector")
457 (and (match_test "TARGET_ALTIVEC")
458 (match_test "easy_altivec_constant (op, mode)")))
461 if (mode == V2DImode || mode == V2DFmode)
463 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
464 val = ((val & 0xff) ^ 0x80) - 0x80;
465 return EASY_VECTOR_15_ADD_SELF (val);
468 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
469 (define_predicate "easy_vector_constant_msb"
470 (and (match_code "const_vector")
471 (and (match_test "TARGET_ALTIVEC")
472 (match_test "easy_altivec_constant (op, mode)")))
475 if (mode == V2DImode || mode == V2DFmode)
477 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
478 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
481 ;; Return 1 if operand is constant zero (scalars and vectors).
482 (define_predicate "zero_constant"
483 (and (match_code "const_int,const_double,const_vector")
484 (match_test "op == CONST0_RTX (mode)")))
486 ;; Return 1 if operand is 0.0.
487 (define_predicate "zero_fp_constant"
488 (and (match_code "const_double")
489 (match_test "SCALAR_FLOAT_MODE_P (mode)
490 && op == CONST0_RTX (mode)")))
492 ;; Return 1 if the operand is in volatile memory. Note that during the
493 ;; RTL generation phase, memory_operand does not return TRUE for volatile
494 ;; memory references. So this function allows us to recognize volatile
495 ;; references where it's safe.
496 (define_predicate "volatile_mem_operand"
497 (and (and (match_code "mem")
498 (match_test "MEM_VOLATILE_P (op)"))
499 (if_then_else (match_test "reload_completed")
500 (match_operand 0 "memory_operand")
501 (if_then_else (match_test "reload_in_progress")
502 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
503 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
505 ;; Return 1 if the operand is an offsettable memory operand.
506 (define_predicate "offsettable_mem_operand"
507 (and (match_operand 0 "memory_operand")
508 (match_test "offsettable_nonstrict_memref_p (op)")))
510 ;; Return 1 if the operand is an indexed or indirect memory operand.
511 (define_predicate "indexed_or_indirect_operand"
515 if (VECTOR_MEM_ALTIVEC_P (mode)
516 && GET_CODE (op) == AND
517 && GET_CODE (XEXP (op, 1)) == CONST_INT
518 && INTVAL (XEXP (op, 1)) == -16)
521 return indexed_or_indirect_address (op, mode);
524 ;; Return 1 if the operand is an indexed or indirect memory operand with an
525 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
526 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
527 ;; while VSX uses the full address and traps)
528 (define_predicate "altivec_indexed_or_indirect_operand"
532 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
533 && GET_CODE (op) == AND
534 && GET_CODE (XEXP (op, 1)) == CONST_INT
535 && INTVAL (XEXP (op, 1)) == -16)
536 return indexed_or_indirect_address (XEXP (op, 0), mode);
541 ;; Return 1 if the operand is an indexed or indirect address.
542 (define_special_predicate "indexed_or_indirect_address"
543 (and (match_test "REG_P (op)
544 || (GET_CODE (op) == PLUS
545 /* Omit testing REG_P (XEXP (op, 0)). */
546 && REG_P (XEXP (op, 1)))")
547 (match_operand 0 "address_operand")))
549 ;; Return 1 if the operand is an index-form address.
550 (define_special_predicate "indexed_address"
551 (match_test "(GET_CODE (op) == PLUS
552 && REG_P (XEXP (op, 0))
553 && REG_P (XEXP (op, 1)))"))
555 ;; Return 1 if the operand is a MEM with an update-form address. This may
556 ;; also include update-indexed form.
557 (define_special_predicate "update_address_mem"
558 (match_test "(MEM_P (op)
559 && (GET_CODE (XEXP (op, 0)) == PRE_INC
560 || GET_CODE (XEXP (op, 0)) == PRE_DEC
561 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
563 ;; Return 1 if the operand is a MEM with an update-indexed-form address. Note
564 ;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the
565 ;; increment is based on the mode size and will therefor always be a const.
566 (define_special_predicate "update_indexed_address_mem"
567 (match_test "(MEM_P (op)
568 && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
569 && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
571 ;; Used for the destination of the fix_truncdfsi2 expander.
572 ;; If stfiwx will be used, the result goes to memory; otherwise,
573 ;; we're going to emit a store and a load of a subreg, so the dest is a
575 (define_predicate "fix_trunc_dest_operand"
576 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
577 (match_operand 0 "memory_operand")
578 (match_operand 0 "gpc_reg_operand")))
580 ;; Return 1 if the operand is either a non-special register or can be used
581 ;; as the operand of a `mode' add insn.
582 (define_predicate "add_operand"
583 (if_then_else (match_code "const_int")
584 (match_test "satisfies_constraint_I (op)
585 || satisfies_constraint_L (op)")
586 (match_operand 0 "gpc_reg_operand")))
588 ;; Return 1 if OP is a constant but not a valid add_operand.
589 (define_predicate "non_add_cint_operand"
590 (and (match_code "const_int")
591 (match_test "!satisfies_constraint_I (op)
592 && !satisfies_constraint_L (op)")))
594 ;; Return 1 if the operand is a constant that can be used as the operand
596 (define_predicate "logical_const_operand"
597 (match_code "const_int")
601 opl = INTVAL (op) & GET_MODE_MASK (mode);
603 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
604 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
607 ;; Return 1 if the operand is a non-special register or a constant that
608 ;; can be used as the operand of an OR or XOR.
609 (define_predicate "logical_operand"
610 (ior (match_operand 0 "gpc_reg_operand")
611 (match_operand 0 "logical_const_operand")))
613 ;; Return 1 if op is a constant that is not a logical operand, but could
614 ;; be split into one.
615 (define_predicate "non_logical_cint_operand"
616 (and (match_code "const_int,const_double")
617 (and (not (match_operand 0 "logical_operand"))
618 (match_operand 0 "reg_or_logical_cint_operand"))))
620 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
621 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
622 ;; transitions). Reject all ones and all zeros, since these should have
623 ;; been optimized away and confuse the making of MB and ME.
624 (define_predicate "mask_operand"
625 (match_code "const_int")
627 HOST_WIDE_INT c, lsb;
631 if (TARGET_POWERPC64)
633 /* Fail if the mask is not 32-bit. */
634 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
637 /* Fail if the mask wraps around because the upper 32-bits of the
638 mask will all be 1s, contrary to GCC's internal view. */
639 if ((c & 0x80000001) == 0x80000001)
643 /* We don't change the number of transitions by inverting,
644 so make sure we start with the LS bit zero. */
648 /* Reject all zeros or all ones. */
652 /* Find the first transition. */
655 /* Invert to look for a second transition. */
658 /* Erase first transition. */
661 /* Find the second transition (if any). */
664 /* Match if all the bits above are 1's (or c is zero). */
668 ;; Return 1 for the PowerPC64 rlwinm corner case.
669 (define_predicate "mask_operand_wrap"
670 (match_code "const_int")
672 HOST_WIDE_INT c, lsb;
676 if ((c & 0x80000001) != 0x80000001)
690 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
691 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
692 ;; transition). Reject all zeros, since zero should have been
693 ;; optimized away and confuses the making of MB and ME.
694 (define_predicate "mask64_operand"
695 (match_code "const_int")
697 HOST_WIDE_INT c, lsb;
701 /* Reject all zeros. */
705 /* We don't change the number of transitions by inverting,
706 so make sure we start with the LS bit zero. */
710 /* Find the first transition. */
713 /* Match if all the bits above are 1's (or c is zero). */
717 ;; Like mask64_operand, but allow up to three transitions. This
718 ;; predicate is used by insn patterns that generate two rldicl or
719 ;; rldicr machine insns.
720 (define_predicate "mask64_2_operand"
721 (match_code "const_int")
723 HOST_WIDE_INT c, lsb;
727 /* Disallow all zeros. */
731 /* We don't change the number of transitions by inverting,
732 so make sure we start with the LS bit zero. */
736 /* Find the first transition. */
739 /* Invert to look for a second transition. */
742 /* Erase first transition. */
745 /* Find the second transition. */
748 /* Invert to look for a third transition. */
751 /* Erase second transition. */
754 /* Find the third transition (if any). */
757 /* Match if all the bits above are 1's (or c is zero). */
761 ;; Like and_operand, but also match constants that can be implemented
762 ;; with two rldicl or rldicr insns.
763 (define_predicate "and64_2_operand"
764 (ior (match_operand 0 "mask64_2_operand")
765 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
766 (match_operand 0 "gpc_reg_operand")
767 (match_operand 0 "logical_operand"))))
769 ;; Return 1 if the operand is either a non-special register or a
770 ;; constant that can be used as the operand of a logical AND.
771 (define_predicate "and_operand"
772 (ior (match_operand 0 "mask_operand")
773 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
774 (match_operand 0 "mask64_operand"))
775 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
776 (match_operand 0 "gpc_reg_operand")
777 (match_operand 0 "logical_operand")))))
779 ;; Return 1 if the operand is either a logical operand or a short cint operand.
780 (define_predicate "scc_eq_operand"
781 (ior (match_operand 0 "logical_operand")
782 (match_operand 0 "short_cint_operand")))
784 ;; Return 1 if the operand is a general non-special register or memory operand.
785 (define_predicate "reg_or_mem_operand"
786 (ior (match_operand 0 "memory_operand")
787 (ior (and (match_code "mem")
788 (match_test "macho_lo_sum_memory_operand (op, mode)"))
789 (ior (match_operand 0 "volatile_mem_operand")
790 (match_operand 0 "gpc_reg_operand")))))
792 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
793 (define_predicate "reg_or_none500mem_operand"
794 (if_then_else (match_code "mem")
795 (and (match_test "!TARGET_E500_DOUBLE")
796 (ior (match_operand 0 "memory_operand")
797 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
798 (match_operand 0 "volatile_mem_operand"))))
799 (match_operand 0 "gpc_reg_operand")))
801 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
802 (define_predicate "zero_reg_mem_operand"
803 (ior (match_operand 0 "zero_fp_constant")
804 (match_operand 0 "reg_or_mem_operand")))
806 ;; Return 1 if the operand is a general register or memory operand without
807 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
809 (define_predicate "lwa_operand"
810 (match_code "reg,subreg,mem")
812 rtx inner, addr, offset;
815 if (reload_completed && GET_CODE (inner) == SUBREG)
816 inner = SUBREG_REG (inner);
818 if (gpc_reg_operand (inner, mode))
820 if (!memory_operand (inner, mode))
822 addr = XEXP (inner, 0);
823 if (GET_CODE (addr) == PRE_INC
824 || GET_CODE (addr) == PRE_DEC
825 || (GET_CODE (addr) == PRE_MODIFY
826 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
828 if (GET_CODE (addr) == LO_SUM
829 && GET_CODE (XEXP (addr, 0)) == REG
830 && GET_CODE (XEXP (addr, 1)) == CONST)
831 addr = XEXP (XEXP (addr, 1), 0);
832 if (GET_CODE (addr) != PLUS)
834 offset = XEXP (addr, 1);
835 if (GET_CODE (offset) != CONST_INT)
837 return INTVAL (offset) % 4 == 0;
840 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
841 (define_predicate "symbol_ref_operand"
842 (and (match_code "symbol_ref")
843 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
844 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
846 ;; Return 1 if op is an operand that can be loaded via the GOT.
847 ;; or non-special register register field no cr0
848 (define_predicate "got_operand"
849 (match_code "symbol_ref,const,label_ref"))
851 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
852 ;; excluding labels involving addition.
853 (define_predicate "got_no_const_operand"
854 (match_code "symbol_ref,label_ref"))
856 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
857 (define_predicate "rs6000_tls_symbol_ref"
858 (and (match_code "symbol_ref")
859 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
861 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
862 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
863 (define_predicate "call_operand"
864 (if_then_else (match_code "reg")
865 (match_test "REGNO (op) == LR_REGNO
866 || REGNO (op) == CTR_REGNO
867 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
868 (match_code "symbol_ref")))
870 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
872 (define_predicate "current_file_function_operand"
873 (and (match_code "symbol_ref")
874 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
875 && ((SYMBOL_REF_LOCAL_P (op)
876 && (DEFAULT_ABI != ABI_AIX
877 || !SYMBOL_REF_EXTERNAL_P (op)))
878 || (op == XEXP (DECL_RTL (current_function_decl),
881 ;; Return 1 if this operand is a valid input for a move insn.
882 (define_predicate "input_operand"
883 (match_code "symbol_ref,const,reg,subreg,mem,
884 const_double,const_vector,const_int")
886 /* Memory is always valid. */
887 if (memory_operand (op, mode))
890 /* For floating-point, easy constants are valid. */
891 if (SCALAR_FLOAT_MODE_P (mode)
892 && easy_fp_constant (op, mode))
895 /* Allow any integer constant. */
896 if (GET_MODE_CLASS (mode) == MODE_INT
897 && (GET_CODE (op) == CONST_INT
898 || GET_CODE (op) == CONST_DOUBLE))
901 /* Allow easy vector constants. */
902 if (GET_CODE (op) == CONST_VECTOR
903 && easy_vector_constant (op, mode))
906 /* Do not allow invalid E500 subregs. */
907 if ((TARGET_E500_DOUBLE || TARGET_SPE)
908 && GET_CODE (op) == SUBREG
909 && invalid_e500_subreg (op, mode))
912 /* For floating-point or multi-word mode, the only remaining valid type
914 if (SCALAR_FLOAT_MODE_P (mode)
915 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
916 return register_operand (op, mode);
918 /* The only cases left are integral modes one word or smaller (we
919 do not get called for MODE_CC values). These can be in any
921 if (register_operand (op, mode))
924 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
926 if (DEFAULT_ABI == ABI_V4
927 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
928 && small_data_operand (op, Pmode))
934 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
935 (define_predicate "splat_input_operand"
936 (match_code "symbol_ref,const,reg,subreg,mem,
937 const_double,const_vector,const_int")
941 if (! volatile_ok && MEM_VOLATILE_P (op))
945 else if (mode == DImode)
949 return memory_address_addr_space_p (mode, XEXP (op, 0),
950 MEM_ADDR_SPACE (op));
952 return input_operand (op, mode);
955 ;; Return true if OP is a non-immediate operand and not an invalid
956 ;; SUBREG operation on the e500.
957 (define_predicate "rs6000_nonimmediate_operand"
958 (match_code "reg,subreg,mem")
960 if ((TARGET_E500_DOUBLE || TARGET_SPE)
961 && GET_CODE (op) == SUBREG
962 && invalid_e500_subreg (op, mode))
965 return nonimmediate_operand (op, mode);
968 ;; Return true if operand is boolean operator.
969 (define_predicate "boolean_operator"
970 (match_code "and,ior,xor"))
972 ;; Return true if operand is OR-form of boolean operator.
973 (define_predicate "boolean_or_operator"
974 (match_code "ior,xor"))
976 ;; Return true if operand is an equality operator.
977 (define_special_predicate "equality_operator"
978 (match_code "eq,ne"))
980 ;; Return true if operand is MIN or MAX operator.
981 (define_predicate "min_max_operator"
982 (match_code "smin,smax,umin,umax"))
984 ;; Return 1 if OP is a comparison operation that is valid for a branch
985 ;; instruction. We check the opcode against the mode of the CC value.
986 ;; validate_condition_mode is an assertion.
987 (define_predicate "branch_comparison_operator"
988 (and (match_operand 0 "comparison_operator")
989 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
990 (match_test "validate_condition_mode (GET_CODE (op),
991 GET_MODE (XEXP (op, 0))),
994 (define_predicate "rs6000_cbranch_operator"
995 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
996 (match_operand 0 "ordered_comparison_operator")
997 (match_operand 0 "comparison_operator")))
999 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1000 ;; it must be a positive comparison.
1001 (define_predicate "scc_comparison_operator"
1002 (and (match_operand 0 "branch_comparison_operator")
1003 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1005 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1007 (define_predicate "scc_rev_comparison_operator"
1008 (and (match_operand 0 "branch_comparison_operator")
1009 (match_code "ne,le,ge,leu,geu,ordered")))
1011 ;; Return 1 if OP is a comparison operation that is valid for a branch
1012 ;; insn, which is true if the corresponding bit in the CC register is set.
1013 (define_predicate "branch_positive_comparison_operator"
1014 (and (match_operand 0 "branch_comparison_operator")
1015 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1017 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1018 (define_predicate "load_multiple_operation"
1019 (match_code "parallel")
1021 int count = XVECLEN (op, 0);
1022 unsigned int dest_regno;
1026 /* Perform a quick check so we don't blow up below. */
1028 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1029 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1030 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1033 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1034 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1036 for (i = 1; i < count; i++)
1038 rtx elt = XVECEXP (op, 0, i);
1040 if (GET_CODE (elt) != SET
1041 || GET_CODE (SET_DEST (elt)) != REG
1042 || GET_MODE (SET_DEST (elt)) != SImode
1043 || REGNO (SET_DEST (elt)) != dest_regno + i
1044 || GET_CODE (SET_SRC (elt)) != MEM
1045 || GET_MODE (SET_SRC (elt)) != SImode
1046 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1047 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1048 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1049 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1056 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1057 ;; The second vector element is a CLOBBER.
1058 (define_predicate "store_multiple_operation"
1059 (match_code "parallel")
1061 int count = XVECLEN (op, 0) - 1;
1062 unsigned int src_regno;
1066 /* Perform a quick check so we don't blow up below. */
1068 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1069 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1070 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1073 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1074 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1076 for (i = 1; i < count; i++)
1078 rtx elt = XVECEXP (op, 0, i + 1);
1080 if (GET_CODE (elt) != SET
1081 || GET_CODE (SET_SRC (elt)) != REG
1082 || GET_MODE (SET_SRC (elt)) != SImode
1083 || REGNO (SET_SRC (elt)) != src_regno + i
1084 || GET_CODE (SET_DEST (elt)) != MEM
1085 || GET_MODE (SET_DEST (elt)) != SImode
1086 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1087 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1088 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1089 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1096 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1098 (define_predicate "save_world_operation"
1099 (match_code "parallel")
1104 int count = XVECLEN (op, 0);
1110 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1111 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1114 for (i=1; i <= 18; i++)
1116 elt = XVECEXP (op, 0, index++);
1117 if (GET_CODE (elt) != SET
1118 || GET_CODE (SET_DEST (elt)) != MEM
1119 || ! memory_operand (SET_DEST (elt), DFmode)
1120 || GET_CODE (SET_SRC (elt)) != REG
1121 || GET_MODE (SET_SRC (elt)) != DFmode)
1125 for (i=1; i <= 12; i++)
1127 elt = XVECEXP (op, 0, index++);
1128 if (GET_CODE (elt) != SET
1129 || GET_CODE (SET_DEST (elt)) != MEM
1130 || GET_CODE (SET_SRC (elt)) != REG
1131 || GET_MODE (SET_SRC (elt)) != V4SImode)
1135 for (i=1; i <= 19; i++)
1137 elt = XVECEXP (op, 0, index++);
1138 if (GET_CODE (elt) != SET
1139 || GET_CODE (SET_DEST (elt)) != MEM
1140 || ! memory_operand (SET_DEST (elt), Pmode)
1141 || GET_CODE (SET_SRC (elt)) != REG
1142 || GET_MODE (SET_SRC (elt)) != Pmode)
1146 elt = XVECEXP (op, 0, index++);
1147 if (GET_CODE (elt) != SET
1148 || GET_CODE (SET_DEST (elt)) != MEM
1149 || ! memory_operand (SET_DEST (elt), Pmode)
1150 || GET_CODE (SET_SRC (elt)) != REG
1151 || REGNO (SET_SRC (elt)) != CR2_REGNO
1152 || GET_MODE (SET_SRC (elt)) != Pmode)
1155 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1156 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1161 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1163 (define_predicate "restore_world_operation"
1164 (match_code "parallel")
1169 int count = XVECLEN (op, 0);
1175 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1176 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1177 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1178 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1181 elt = XVECEXP (op, 0, index++);
1182 if (GET_CODE (elt) != SET
1183 || GET_CODE (SET_SRC (elt)) != MEM
1184 || ! memory_operand (SET_SRC (elt), Pmode)
1185 || GET_CODE (SET_DEST (elt)) != REG
1186 || REGNO (SET_DEST (elt)) != CR2_REGNO
1187 || GET_MODE (SET_DEST (elt)) != Pmode)
1190 for (i=1; i <= 19; i++)
1192 elt = XVECEXP (op, 0, index++);
1193 if (GET_CODE (elt) != SET
1194 || GET_CODE (SET_SRC (elt)) != MEM
1195 || ! memory_operand (SET_SRC (elt), Pmode)
1196 || GET_CODE (SET_DEST (elt)) != REG
1197 || GET_MODE (SET_DEST (elt)) != Pmode)
1201 for (i=1; i <= 12; i++)
1203 elt = XVECEXP (op, 0, index++);
1204 if (GET_CODE (elt) != SET
1205 || GET_CODE (SET_SRC (elt)) != MEM
1206 || GET_CODE (SET_DEST (elt)) != REG
1207 || GET_MODE (SET_DEST (elt)) != V4SImode)
1211 for (i=1; i <= 18; i++)
1213 elt = XVECEXP (op, 0, index++);
1214 if (GET_CODE (elt) != SET
1215 || GET_CODE (SET_SRC (elt)) != MEM
1216 || ! memory_operand (SET_SRC (elt), DFmode)
1217 || GET_CODE (SET_DEST (elt)) != REG
1218 || GET_MODE (SET_DEST (elt)) != DFmode)
1222 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1223 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1224 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1225 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1226 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1231 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1232 (define_predicate "vrsave_operation"
1233 (match_code "parallel")
1235 int count = XVECLEN (op, 0);
1236 unsigned int dest_regno, src_regno;
1240 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1241 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1242 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1243 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1246 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1247 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1249 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1252 for (i = 1; i < count; i++)
1254 rtx elt = XVECEXP (op, 0, i);
1256 if (GET_CODE (elt) != CLOBBER
1257 && GET_CODE (elt) != SET)
1264 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1265 (define_predicate "mfcr_operation"
1266 (match_code "parallel")
1268 int count = XVECLEN (op, 0);
1271 /* Perform a quick check so we don't blow up below. */
1273 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1274 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1275 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1278 for (i = 0; i < count; i++)
1280 rtx exp = XVECEXP (op, 0, i);
1285 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1287 if (GET_CODE (src_reg) != REG
1288 || GET_MODE (src_reg) != CCmode
1289 || ! CR_REGNO_P (REGNO (src_reg)))
1292 if (GET_CODE (exp) != SET
1293 || GET_CODE (SET_DEST (exp)) != REG
1294 || GET_MODE (SET_DEST (exp)) != SImode
1295 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1297 unspec = SET_SRC (exp);
1298 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1300 if (GET_CODE (unspec) != UNSPEC
1301 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1302 || XVECLEN (unspec, 0) != 2
1303 || XVECEXP (unspec, 0, 0) != src_reg
1304 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1305 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1311 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1312 (define_predicate "mtcrf_operation"
1313 (match_code "parallel")
1315 int count = XVECLEN (op, 0);
1319 /* Perform a quick check so we don't blow up below. */
1321 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1322 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1323 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1325 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1327 if (GET_CODE (src_reg) != REG
1328 || GET_MODE (src_reg) != SImode
1329 || ! INT_REGNO_P (REGNO (src_reg)))
1332 for (i = 0; i < count; i++)
1334 rtx exp = XVECEXP (op, 0, i);
1338 if (GET_CODE (exp) != SET
1339 || GET_CODE (SET_DEST (exp)) != REG
1340 || GET_MODE (SET_DEST (exp)) != CCmode
1341 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1343 unspec = SET_SRC (exp);
1344 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1346 if (GET_CODE (unspec) != UNSPEC
1347 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1348 || XVECLEN (unspec, 0) != 2
1349 || XVECEXP (unspec, 0, 0) != src_reg
1350 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1351 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1357 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1358 (define_predicate "lmw_operation"
1359 (match_code "parallel")
1361 int count = XVECLEN (op, 0);
1362 unsigned int dest_regno;
1364 unsigned int base_regno;
1365 HOST_WIDE_INT offset;
1368 /* Perform a quick check so we don't blow up below. */
1370 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1371 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1372 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1375 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1376 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1379 || count != 32 - (int) dest_regno)
1382 if (legitimate_indirect_address_p (src_addr, 0))
1385 base_regno = REGNO (src_addr);
1386 if (base_regno == 0)
1389 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1391 offset = INTVAL (XEXP (src_addr, 1));
1392 base_regno = REGNO (XEXP (src_addr, 0));
1397 for (i = 0; i < count; i++)
1399 rtx elt = XVECEXP (op, 0, i);
1402 HOST_WIDE_INT newoffset;
1404 if (GET_CODE (elt) != SET
1405 || GET_CODE (SET_DEST (elt)) != REG
1406 || GET_MODE (SET_DEST (elt)) != SImode
1407 || REGNO (SET_DEST (elt)) != dest_regno + i
1408 || GET_CODE (SET_SRC (elt)) != MEM
1409 || GET_MODE (SET_SRC (elt)) != SImode)
1411 newaddr = XEXP (SET_SRC (elt), 0);
1412 if (legitimate_indirect_address_p (newaddr, 0))
1417 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1419 addr_reg = XEXP (newaddr, 0);
1420 newoffset = INTVAL (XEXP (newaddr, 1));
1424 if (REGNO (addr_reg) != base_regno
1425 || newoffset != offset + 4 * i)
1432 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1433 (define_predicate "stmw_operation"
1434 (match_code "parallel")
1436 int count = XVECLEN (op, 0);
1437 unsigned int src_regno;
1439 unsigned int base_regno;
1440 HOST_WIDE_INT offset;
1443 /* Perform a quick check so we don't blow up below. */
1445 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1446 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1447 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1450 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1451 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1454 || count != 32 - (int) src_regno)
1457 if (legitimate_indirect_address_p (dest_addr, 0))
1460 base_regno = REGNO (dest_addr);
1461 if (base_regno == 0)
1464 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1466 offset = INTVAL (XEXP (dest_addr, 1));
1467 base_regno = REGNO (XEXP (dest_addr, 0));
1472 for (i = 0; i < count; i++)
1474 rtx elt = XVECEXP (op, 0, i);
1477 HOST_WIDE_INT newoffset;
1479 if (GET_CODE (elt) != SET
1480 || GET_CODE (SET_SRC (elt)) != REG
1481 || GET_MODE (SET_SRC (elt)) != SImode
1482 || REGNO (SET_SRC (elt)) != src_regno + i
1483 || GET_CODE (SET_DEST (elt)) != MEM
1484 || GET_MODE (SET_DEST (elt)) != SImode)
1486 newaddr = XEXP (SET_DEST (elt), 0);
1487 if (legitimate_indirect_address_p (newaddr, 0))
1492 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1494 addr_reg = XEXP (newaddr, 0);
1495 newoffset = INTVAL (XEXP (newaddr, 1));
1499 if (REGNO (addr_reg) != base_regno
1500 || newoffset != offset + 4 * i)
1507 ;; Return 1 if OP is a stack tie operand.
1508 (define_predicate "tie_operand"
1509 (match_code "parallel")
1511 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1512 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1513 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1514 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1517 ;; Match a small code model toc reference (or medium and large
1518 ;; model toc references before reload).
1519 (define_predicate "small_toc_ref"
1520 (match_code "unspec,plus")
1522 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
1525 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;