?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
(INITIAL_ELIMINATION_OFFSET): Check frame_pointer_needed when eliminating
[official-gcc.git] / gcc / config / arm / arm.h
blob51437543c8279a175e59c79a80a671651ee5708d
1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
23 /* Sometimes the directive `riscos' is checked. This does not imply that this
24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
27 extern void output_func_prologue ();
28 extern void output_func_epilogue ();
29 extern char *output_add_immediate ();
30 extern char *output_call ();
31 extern char *output_call_mem ();
32 extern char *output_move_double ();
33 extern char *output_mov_double_fpu_from_arm ();
34 extern char *output_mov_double_arm_from_fpu ();
35 extern char *output_mov_long_double_fpu_from_arm ();
36 extern char *output_mov_long_double_arm_from_fpu ();
37 extern char *output_mov_long_double_arm_from_arm ();
38 extern char *output_mov_immediate ();
39 extern char *output_multi_immediate ();
40 extern char *output_return_instruction ();
41 extern char *output_load_symbol ();
42 extern char *fp_immediate_constant ();
43 extern struct rtx_def *gen_compare_reg ();
44 extern struct rtx_def *arm_gen_store_multiple ();
45 extern struct rtx_def *arm_gen_load_multiple ();
46
47 extern char *arm_condition_codes[];
48
49 /* This is needed by the tail-calling peepholes */
50 extern int frame_pointer_needed;
51
52 \f
53 #ifndef CPP_PREDEFINES
54 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55 #endif
56
57 #ifndef CPP_SPEC
58 #define CPP_SPEC "%{m6:-D__arm6__}"
59 #endif
60 \f
61 /* Run-time Target Specification. */
62 #ifndef TARGET_VERSION
63 #define TARGET_VERSION \
64 fputs (" (ARM/generic)", stderr);
65 #endif
66
67 /* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69 extern int target_flags;
70
71 /* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73 #define TARGET_APCS (target_flags & 1)
74
75 /* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81 /* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83 #define TARGET_FPE (target_flags & 4)
84
85 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87 #define TARGET_6 (target_flags & 8)
88
89 /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
90 are passed to the preprocessor and the assembler post-processor. They
91 aren't needed in the main pass of the compiler, but if we don't define
92 them in target switches cc1 complains about them. For the sake of
93 argument lets allocate bit 31 of target flags for such options. */
94
95 #ifndef ARM_EXTRA_TARGET_SWITCHES
96 #define ARM_EXTRA_TARGET_SWITCHES
97 #endif
98
99 #define TARGET_SWITCHES \
100 { \
101 {"apcs", 1}, \
102 {"poke-function-name", 2}, \
103 {"fpe", 4}, \
104 {"6", 8}, \
105 {"2", -8}, \
106 {"3", -8}, \
107 ARM_EXTRA_TARGET_SWITCHES \
108 {"", TARGET_DEFAULT } \
109 }
110
111 /* Which processor we are running on. Currently this is only used to
112 get the condition code clobbering attribute right when we are running on
113 an arm 6 */
114
115 enum processor_type
116 {
117 PROCESSOR_ARM2,
118 PROCESSOR_ARM3,
119 PROCESSOR_ARM6
120 };
121
122 /* Recast the cpu class to be the cpu attribute. */
123
124 /* Recast the cpu class to be the cpu attribute. */
125 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
126
127 extern enum processor_type arm_cpu;
128
129 /* What sort of floating point unit do we have? Hardware or software. */
130 enum floating_point_type
131 {
132 FP_HARD,
133 FP_SOFT
134 };
135
136 /* Recast the floating point class to be the floating point attribute. */
137 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
138
139 extern enum floating_point_type arm_fpu;
140
141 #define TARGET_DEFAULT 0
142
143 #define TARGET_MEM_FUNCTIONS 1
144
145 /* OVERRIDE_OPTIONS takes care of the following:
146 - if -mpoke-function-name, then -mapcs.
147 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
148 - if floating point is done by emulation, forget about instruction
149 scheduling. Note that this only saves compilation time; it doesn't
150 matter for the final code. */
151
152 #define OVERRIDE_OPTIONS \
153 { \
154 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
155 warning ("-g without a frame pointer may not give sensible debugging");\
156 if (TARGET_POKE_FUNCTION_NAME) \
157 target_flags |= 1; \
158 if (TARGET_FPE) \
159 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
160 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
161 }
162 \f
163 /* Target machine storage Layout. */
164
165
166 /* Define this macro if it is advisable to hold scalars in registers
167 in a wider mode than that declared by the program. In such cases,
168 the value is constrained to be within the bounds of the declared
169 type, but kept valid in the wider mode. The signedness of the
170 extension may differ from that of the type. */
171
172 /* It is far faster to zero extend chars than to sign extend them */
173
174 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
175 if (GET_MODE_CLASS (MODE) == MODE_INT \
176 && GET_MODE_SIZE (MODE) < 4) \
177 { \
178 if (MODE == QImode) \
179 UNSIGNEDP = 1; \
180 else if (MODE == HImode) \
181 UNSIGNEDP = 0; \
182 (MODE) = SImode; \
183 }
184
185 /* Define for XFmode extended real floating point support.
186 This will automatically cause REAL_ARITHMETIC to be defined. */
187 /* For the ARM:
188 I think I have added all the code to make this work. Unfortunately,
189 early releases of the floating point emulation code on RISCiX used a
190 different format for extended precision numbers. On my RISCiX box there
191 is a bug somewhere which causes the machine to lock up when running enquire
192 with long doubles. There is the additional aspect that Norcroft C
193 treats long doubles as doubles and we ought to remain compatible.
194 Perhaps someone with an FPA coprocessor and not running RISCiX would like
195 to try this someday. */
196 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
197
198 /* Disable XFmode patterns in md file */
199 #define ENABLE_XF_PATTERNS 0
200
201 /* Define if you don't want extended real, but do want to use the
202 software floating point emulator for REAL_ARITHMETIC and
203 decimal <-> binary conversion. */
204 /* See comment above */
205 #define REAL_ARITHMETIC
206
207 /* Define this if most significant bit is lowest numbered
208 in instructions that operate on numbered bit-fields. */
209 #define BITS_BIG_ENDIAN 0
210
211 /* Define this if most significant byte of a word is the lowest numbered.
212 Most ARM processors are run in little endian mode, but it should now be
213 possible to build the compiler to support big endian code. (Note: This
214 is currently a compiler-build-time option, not a run-time one. */
215 #ifndef BYTES_BIG_ENDIAN
216 #define BYTES_BIG_ENDIAN 0
217 #endif
218
219 /* Define this if most significant word of a multiword number is the lowest
220 numbered. */
221 #define WORDS_BIG_ENDIAN 0
222
223 /* Define this if most significant word of doubles is the lowest numbered */
224 #define FLOAT_WORDS_BIG_ENDIAN 1
225
226 /* Number of bits in an addressable storage unit */
227 #define BITS_PER_UNIT 8
228
229 #define BITS_PER_WORD 32
230
231 #define UNITS_PER_WORD 4
232
233 #define POINTER_SIZE 32
234
235 #define PARM_BOUNDARY 32
236
237 #define STACK_BOUNDARY 32
238
239 #define FUNCTION_BOUNDARY 32
240
241 #define EMPTY_FIELD_BOUNDARY 32
242
243 #define BIGGEST_ALIGNMENT 32
244
245 /* Make strings word-aligned so strcpy from constants will be faster. */
246 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
247 (TREE_CODE (EXP) == STRING_CST \
248 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
249
250 /* Every structures size must be a multiple of 32 bits. */
251 #define STRUCTURE_SIZE_BOUNDARY 32
252
253 /* Non-zero if move instructions will actually fail to work
254 when given unaligned data. */
255 #define STRICT_ALIGNMENT 1
256
257 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
258
259 /* Define number of bits in most basic integer type.
260 (If undefined, default is BITS_PER_WORD). */
261 /* #define INT_TYPE_SIZE */
262 \f
263 /* Standard register usage. */
264
265 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
266 (S - saved over call).
267
268 r0 * argument word/integer result
269 r1-r3 argument word
270
271 r4-r8 S register variable
272 r9 S (rfp) register variable (real frame pointer)
273
274 r10 F S (sl) stack limit (not currently used)
275 r11 F S (fp) argument pointer
276 r12 (ip) temp workspace
277 r13 F S (sp) lower end of current stack frame
278 r14 (lr) link address/workspace
279 r15 F (pc) program counter
280
281 f0 floating point result
282 f1-f3 floating point scratch
283
284 f4-f7 S floating point variable
285
286 cc This is NOT a real register, but is used internally
287 to represent things that use or set the condition
288 codes.
289 sfp This isn't either. It is used during rtl generation
290 since the offset between the frame pointer and the
291 auto's isn't known until after register allocation.
292 afp Nor this, we only need this because of non-local
293 goto. Without it fp appears to be used and the
294 elimination code won't get rid of sfp. It tracks
295 fp exactly at all times.
296
297 *: See CONDITIONAL_REGISTER_USAGE */
298
299 /* The stack backtrace structure is as follows:
300 fp points to here: | save code pointer | [fp]
301 | return link value | [fp, #-4]
302 | return sp value | [fp, #-8]
303 | return fp value | [fp, #-12]
304 [| saved r10 value |]
305 [| saved r9 value |]
306 [| saved r8 value |]
307 [| saved r7 value |]
308 [| saved r6 value |]
309 [| saved r5 value |]
310 [| saved r4 value |]
311 [| saved r3 value |]
312 [| saved r2 value |]
313 [| saved r1 value |]
314 [| saved r0 value |]
315 [| saved f7 value |] three words
316 [| saved f6 value |] three words
317 [| saved f5 value |] three words
318 [| saved f4 value |] three words
319 r0-r3 are not normally saved in a C function. */
320
321 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
322 #define FIRST_PSEUDO_REGISTER 27
323
324 /* 1 for registers that have pervasive standard uses
325 and are not available for the register allocator. */
326 #define FIXED_REGISTERS \
327 { \
328 0,0,0,0,0,0,0,0, \
329 0,0,1,1,0,1,0,1, \
330 0,0,0,0,0,0,0,0, \
331 1,1,1 \
332 }
333
334 /* 1 for registers not available across function calls.
335 These must include the FIXED_REGISTERS and also any
336 registers that can be used without being saved.
337 The latter must include the registers where values are returned
338 and the register where structure-value addresses are passed.
339 Aside from that, you can include as many other registers as you like.
340 The CC is not preserved over function calls on the ARM 6, so it is
341 easier to assume this for all. SFP is preserved, since FP is. */
342 #define CALL_USED_REGISTERS \
343 { \
344 1,1,1,1,0,0,0,0, \
345 0,0,1,1,1,1,1,1, \
346 1,1,1,1,0,0,0,0, \
347 1,1,1 \
348 }
349
350 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
351 trampled. This effectively reduces the number of available registers by 1.
352 XXX It is a hack, I know.
353 XXX Is this still needed? */
354 #define CONDITIONAL_REGISTER_USAGE \
355 { \
356 if (obey_regdecls) \
357 fixed_regs[0] = 1; \
358 }
359
360 /* Return number of consecutive hard regs needed starting at reg REGNO
361 to hold something of mode MODE.
362 This is ordinarily the length in words of a value of mode MODE
363 but can be less for certain modes in special long registers.
364
365 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
366 mode. */
367 #define HARD_REGNO_NREGS(REGNO, MODE) \
368 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
369 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
370 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
371
372 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
373 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
374 regs holding FP. */
375 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
376 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
377 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
378 || REGNO == ARG_POINTER_REGNUM \
379 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
380
381 /* Value is 1 if it is a good idea to tie two pseudo registers
382 when one has mode MODE1 and one has mode MODE2.
383 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
384 for any hard reg, then this must be 0 for correct output. */
385 #define MODES_TIEABLE_P(MODE1, MODE2) \
386 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
387
388 /* Specify the registers used for certain standard purposes.
389 The values of these macros are register numbers. */
390
391 /* Define this if the program counter is overloaded on a register. */
392 #define PC_REGNUM 15
393
394 /* Register to use for pushing function arguments. */
395 #define STACK_POINTER_REGNUM 13
396
397 /* Base register for access to local variables of the function. */
398 #define FRAME_POINTER_REGNUM 25
399
400 /* Define this to be where the real frame pointer is if it is not possible to
401 work out the offset between the frame pointer and the automatic variables
402 until after register allocation has taken place. FRAME_POINTER_REGNUM
403 should point to a special register that we will make sure is eliminated. */
404 #define HARD_FRAME_POINTER_REGNUM 11
405
406 /* Value should be nonzero if functions must have frame pointers.
407 Zero means the frame pointer need not be set up (and parms may be accessed
408 via the stack pointer) in functions that seem suitable.
409 If we have to have a frame pointer we might as well make use of it.
410 APCS says that the frame pointer does not need to be pushed in leaf
411 functions. */
412 #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
413
414 /* Base register for access to arguments of the function. */
415 #define ARG_POINTER_REGNUM 26
416
417 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
418 as an invisible last argument (possible since varargs don't exist in
419 Pascal), so the following is not true. */
420 #define STATIC_CHAIN_REGNUM 8
421
422 /* Register in which address to store a structure value
423 is passed to a function. */
424 #define STRUCT_VALUE_REGNUM 0
425
426 /* Internal, so that we don't need to refer to a raw number */
427 #define CC_REGNUM 24
428
429 /* The order in which register should be allocated. It is good to use ip
430 since no saving is required (though calls clobber it) and it never contains
431 function parameters. It is quite good to use lr since other calls may
432 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
433 least likely to contain a function parameter; in addition results are
434 returned in r0.
435 */
436 #define REG_ALLOC_ORDER \
437 { \
438 3, 2, 1, 0, 12, 14, 4, 5, \
439 6, 7, 8, 10, 9, 11, 13, 15, \
440 16, 17, 18, 19, 20, 21, 22, 23, \
441 24, 25 \
442 }
443 \f
444 /* Register and constant classes. */
445
446 /* Register classes: all ARM regs or all FPU regs---simple! */
447 enum reg_class
448 {
449 NO_REGS,
450 FPU_REGS,
451 GENERAL_REGS,
452 ALL_REGS,
453 LIM_REG_CLASSES
454 };
455
456 #define N_REG_CLASSES (int) LIM_REG_CLASSES
457
458 /* Give names of register classes as strings for dump file. */
459 #define REG_CLASS_NAMES \
460 { \
461 "NO_REGS", \
462 "FPU_REGS", \
463 "GENERAL_REGS", \
464 "ALL_REGS", \
465 }
466
467 /* Define which registers fit in which classes.
468 This is an initializer for a vector of HARD_REG_SET
469 of length N_REG_CLASSES. */
470 #define REG_CLASS_CONTENTS \
471 { \
472 0x0000000, /* NO_REGS */ \
473 0x0FF0000, /* FPU_REGS */ \
474 0x200FFFF, /* GENERAL_REGS */ \
475 0x2FFFFFF /* ALL_REGS */ \
476 }
477
478 /* The same information, inverted:
479 Return the class number of the smallest class containing
480 reg number REGNO. This could be a conditional expression
481 or could index an array. */
482 #define REGNO_REG_CLASS(REGNO) \
483 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
484 || REGNO == ARG_POINTER_REGNUM) \
485 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
486 ? NO_REGS : FPU_REGS)
487
488 /* The class value for index registers, and the one for base regs. */
489 #define INDEX_REG_CLASS GENERAL_REGS
490 #define BASE_REG_CLASS GENERAL_REGS
491
492 /* Get reg_class from a letter such as appears in the machine description.
493 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
494 #define REG_CLASS_FROM_LETTER(C) \
495 ((C)=='f' ? FPU_REGS : NO_REGS)
496
497 /* The letters I, J, K, L and M in a register constraint string
498 can be used to stand for particular ranges of immediate operands.
499 This macro defines what the ranges are.
500 C is the letter, and VALUE is a constant value.
501 Return 1 if VALUE is in the range specified by C.
502 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
503 J: valid indexing constants.
504 K: ~value ok in rhs argument of data operand.
505 L: -value ok in rhs argument of data operand.
506 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
507 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
508 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
509 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
510 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
511 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
512 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
513 || (((VALUE) & ((VALUE) - 1)) == 0)) \
514 : 0)
515
516 /* For the ARM, `Q' means that this is a memory operand that is just
517 an offset from a register.
518 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
519 address. This means that the symbol is in the text segment and can be
520 accessed without using a load. */
521
522 #define EXTRA_CONSTRAINT(OP, C) \
523 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
524 : (C) == 'R' ? (GET_CODE (OP) == MEM \
525 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
526 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
527 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
528
529 /* Constant letter 'G' for the FPU immediate constants.
530 'H' means the same constant negated. */
531 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
532 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
533 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
534
535 /* Given an rtx X being reloaded into a reg required to be
536 in class CLASS, return the class of reg to actually use.
537 In general this is just CLASS; but on some machines
538 in some cases it is preferable to use a more restrictive class. */
539 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
540
541 /* Return the register class of a scratch register needed to copy IN into
542 or out of a register in CLASS in MODE. If it can be done directly,
543 NO_REGS is returned. */
544 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
545 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
546 && true_regnum (X) == -1) ? GENERAL_REGS \
547 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
548
549 /* Return the maximum number of consecutive registers
550 needed to represent mode MODE in a register of class CLASS.
551 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
552 #define CLASS_MAX_NREGS(CLASS, MODE) \
553 ((CLASS) == FPU_REGS ? 1 \
554 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
555
556 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
557 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
558 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
559 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
560 ? 20 : 2)
561 \f
562 /* Stack layout; function entry, exit and calling. */
563
564 /* Define this if pushing a word on the stack
565 makes the stack pointer a smaller address. */
566 #define STACK_GROWS_DOWNWARD 1
567
568 /* Define this if the nominal address of the stack frame
569 is at the high-address end of the local variables;
570 that is, each additional local variable allocated
571 goes at a more negative offset in the frame. */
572 #define FRAME_GROWS_DOWNWARD 1
573
574 /* Offset within stack frame to start allocating local variables at.
575 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
576 first local allocated. Otherwise, it is the offset to the BEGINNING
577 of the first local allocated. */
578 #define STARTING_FRAME_OFFSET 0
579
580 /* If we generate an insn to push BYTES bytes,
581 this says how many the stack pointer really advances by. */
582 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
583
584 /* Offset of first parameter from the argument pointer register value. */
585 #define FIRST_PARM_OFFSET(FNDECL) 4
586
587 /* Value is the number of byte of arguments automatically
588 popped when returning from a subroutine call.
589 FUNTYPE is the data type of the function (as a tree),
590 or for a library call it is an identifier node for the subroutine name.
591 SIZE is the number of bytes of arguments passed on the stack.
592
593 On the ARM, the caller does not pop any of its arguments that were passed
594 on the stack. */
595 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
596
597 /* Define how to find the value returned by a function.
598 VALTYPE is the data type of the value (as a tree).
599 If the precise function being called is known, FUNC is its FUNCTION_DECL;
600 otherwise, FUNC is 0. */
601 #define FUNCTION_VALUE(VALTYPE, FUNC) \
602 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
603 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
604 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
605
606 /* Define how to find the value returned by a library function
607 assuming the value has mode MODE. */
608 #define LIBCALL_VALUE(MODE) \
609 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
610 ? gen_rtx (REG, MODE, 16) \
611 : gen_rtx (REG, MODE, 0))
612
613 /* 1 if N is a possible register number for a function value.
614 On the ARM, only r0 and f0 can return results. */
615 #define FUNCTION_VALUE_REGNO_P(REGNO) \
616 ((REGNO) == 0 || (REGNO) == 16)
617
618 /* Define where to put the arguments to a function.
619 Value is zero to push the argument on the stack,
620 or a hard register in which to store the argument.
621
622 MODE is the argument's machine mode.
623 TYPE is the data type of the argument (as a tree).
624 This is null for libcalls where that information may
625 not be available.
626 CUM is a variable of type CUMULATIVE_ARGS which gives info about
627 the preceding args and about the function being called.
628 NAMED is nonzero if this argument is a named parameter
629 (otherwise it is an extra parameter matching an ellipsis).
630
631 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
632 other arguments are passed on the stack. If (NAMED == 0) (which happens
633 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
634 passed in the stack (function_prologue will indeed make it pass in the
635 stack if necessary). */
636 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
637 ((NAMED) \
638 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
639 : 0)
640
641 /* For an arg passed partly in registers and partly in memory,
642 this is the number of registers used.
643 For args passed entirely in registers or entirely in memory, zero. */
644 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
645 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
646 ? GET_MODE_SIZE (MODE) \
647 : int_size_in_bytes (TYPE)) \
648 ? 4 - (CUM) / 4 : 0)
649
650 /* A C type for declaring a variable that is used as the first argument of
651 `FUNCTION_ARG' and other related values. For some target machines, the
652 type `int' suffices and can hold the number of bytes of argument so far.
653
654 On the ARM, this is the number of bytes of arguments scanned so far. */
655 #define CUMULATIVE_ARGS int
656
657 /* Initialize a variable CUM of type CUMULATIVE_ARGS
658 for a call to a function whose data type is FNTYPE.
659 For a library call, FNTYPE is 0.
660 On the ARM, the offset starts at 0. */
661 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
662 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
663
664 /* Update the data in CUM to advance over an argument
665 of mode MODE and data type TYPE.
666 (TYPE is null for libcalls where that information may not be available.) */
667 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
668 (CUM) += ((MODE) != BLKmode \
669 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
670 : (int_size_in_bytes (TYPE) + 3) & ~3) \
671
672 /* 1 if N is a possible register number for function argument passing.
673 On the ARM, r0-r3 are used to pass args. */
674 #define FUNCTION_ARG_REGNO_P(REGNO) \
675 ((REGNO) >= 0 && (REGNO) <= 3)
676
677 /* Perform any actions needed for a function that is receiving a variable
678 number of arguments. CUM is as above. MODE and TYPE are the mode and type
679 of the current parameter. PRETEND_SIZE is a variable that should be set to
680 the amount of stack that must be pushed by the prolog to pretend that our
681 caller pushed it.
682
683 Normally, this macro will push all remaining incoming registers on the
684 stack and set PRETEND_SIZE to the length of the registers pushed.
685
686 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
687 named arg and all anonymous args onto the stack.
688 XXX I know the prologue shouldn't be pushing registers, but it is faster
689 that way. */
690 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
691 { \
692 extern int current_function_anonymous_args; \
693 current_function_anonymous_args = 1; \
694 if ((CUM) < 16) \
695 (PRETEND_SIZE) = 16 - (CUM); \
696 }
697
698 /* Generate assembly output for the start of a function. */
699 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
700 output_func_prologue ((STREAM), (SIZE))
701
702 /* Call the function profiler with a given profile label. The Acorn compiler
703 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
704 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
705 to mind about this! */
706 #define FUNCTION_PROFILER(STREAM,LABELNO) \
707 { \
708 fprintf(STREAM, "\tmov\t%sip, %slr\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
709 fprintf(STREAM, "\tbl\tmcount\n"); \
710 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
711 }
712
713 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
714 the stack pointer does not matter. The value is tested only in
715 functions that have frame pointers.
716 No definition is equivalent to always zero.
717
718 On the ARM, the function epilogue recovers the stack pointer from the
719 frame. */
720 #define EXIT_IGNORE_STACK 1
721
722 /* Generate the assembly code for function exit. */
723 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
724 output_func_epilogue ((STREAM), (SIZE))
725
726 /* Determine if the epilogue should be output as RTL.
727 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
728 #define USE_RETURN_INSN use_return_insn ()
729
730 /* Definitions for register eliminations.
731
732 This is an array of structures. Each structure initializes one pair
733 of eliminable registers. The "from" register number is given first,
734 followed by "to". Eliminations of the same "from" register are listed
735 in order of preference.
736
737 We have two registers that can be eliminated on the ARM. First, the
738 arg pointer register can often be eliminated in favor of the stack
739 pointer register. Secondly, the pseudo frame pointer register can always
740 be eliminated; it is replaced with either the stack or the real frame
741 pointer. */
742
743 #define ELIMINABLE_REGS \
744 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
745 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
746 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
747 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
748
749 /* Given FROM and TO register numbers, say whether this elimination is allowed.
750 Frame pointer elimination is automatically handled.
751
752 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
753 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
754 pointer, we must eliminate FRAME_POINTER_REGNUM into
755 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
756 #define CAN_ELIMINATE(FROM, TO) \
757 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
758
759 /* Define the offset between two registers, one to be eliminated, and the other
760 its replacement, at the start of a routine. */
761 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
762 { \
763 int volatile_func = arm_volatile_func (); \
764 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
765 (OFFSET) = 0; \
766 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
767 (OFFSET) = (get_frame_size () + 3 & ~3); \
768 else \
769 { \
770 int regno; \
771 int offset = 12; \
772 int saved_hard_reg = 0; \
773 \
774 if (! volatile_func) \
775 { \
776 for (regno = 0; regno <= 10; regno++) \
777 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
778 saved_hard_reg = 1, offset += 4; \
779 for (regno = 16; regno <=23; regno++) \
780 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
781 offset += 12; \
782 } \
783 if ((FROM) == FRAME_POINTER_REGNUM) \
784 (OFFSET) = -offset; \
785 else \
786 { \
787 if (! frame_pointer_needed) \
788 offset -= 16; \
789 if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \
790 offset += 4; \
791 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
792 } \
793 } \
794 }
795
796 /* Output assembler code for a block containing the constant parts
797 of a trampoline, leaving space for the variable parts.
798
799 On the ARM, (if r8 is the static chain regnum, and remembering that
800 referencing pc adds an offset of 8) the trampoline looks like:
801 ldr r8, [pc, #0]
802 ldr pc, [pc]
803 .word static chain value
804 .word function's address */
805 #define TRAMPOLINE_TEMPLATE(FILE) \
806 { \
807 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", ARM_REG_PREFIX, \
808 ARM_REG_PREFIX); \
809 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", ARM_REG_PREFIX, \
810 ARM_REG_PREFIX); \
811 fprintf ((FILE), "\t.word\t0\n"); \
812 fprintf ((FILE), "\t.word\t0\n"); \
813 }
814
815 /* Length in units of the trampoline for entering a nested function. */
816 #define TRAMPOLINE_SIZE 16
817
818 /* Alignment required for a trampoline in units. */
819 #define TRAMPOLINE_ALIGN 4
820
821 /* Emit RTL insns to initialize the variable parts of a trampoline.
822 FNADDR is an RTX for the address of the function's pure code.
823 CXT is an RTX for the static chain value for the function. */
824 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
825 { \
826 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
827 (CXT)); \
828 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
829 (FNADDR)); \
830 }
831
832 \f
833 /* Addressing modes, and classification of registers for them. */
834
835 #define HAVE_POST_INCREMENT 1
836 #define HAVE_PRE_INCREMENT 1
837 #define HAVE_POST_DECREMENT 1
838 #define HAVE_PRE_DECREMENT 1
839
840 /* Macros to check register numbers against specific register classes. */
841
842 /* These assume that REGNO is a hard or pseudo reg number.
843 They give nonzero only if REGNO is a hard reg of the suitable class
844 or a pseudo reg currently allocated to a suitable hard reg.
845 Since they use reg_renumber, they are safe only once reg_renumber
846 has been allocated, which happens in local-alloc.c.
847
848 On the ARM, don't allow the pc to be used. */
849 #define REGNO_OK_FOR_BASE_P(REGNO) \
850 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
851 || (REGNO) == ARG_POINTER_REGNUM \
852 || (unsigned) reg_renumber[(REGNO)] < 15 \
853 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
854 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
855 #define REGNO_OK_FOR_INDEX_P(REGNO) \
856 REGNO_OK_FOR_BASE_P(REGNO)
857
858 /* Maximum number of registers that can appear in a valid memory address.
859 Shifts in addresses can't be by a register. */
860
861 #define MAX_REGS_PER_ADDRESS 2
862
863 /* Recognize any constant value that is a valid address. */
864 /* XXX We can address any constant, eventually... */
865 #if 0
866 #define CONSTANT_ADDRESS_P(X) \
867 ( GET_CODE(X) == LABEL_REF \
868 || GET_CODE(X) == SYMBOL_REF \
869 || GET_CODE(X) == CONST_INT \
870 || GET_CODE(X) == CONST )
871 #endif
872
873 #define CONSTANT_ADDRESS_P(X) \
874 (GET_CODE (X) == SYMBOL_REF \
875 && (CONSTANT_POOL_ADDRESS_P (X) \
876 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
877
878 /* Nonzero if the constant value X is a legitimate general operand.
879 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
880
881 On the ARM, allow any integer (invalid ones are removed later by insn
882 patterns), nice doubles and symbol_refs which refer to the function's
883 constant pool XXX. */
884 #define LEGITIMATE_CONSTANT_P(X) \
885 (GET_CODE (X) == CONST_INT \
886 || (GET_CODE (X) == CONST_DOUBLE \
887 && (const_double_rtx_ok_for_fpu (X) \
888 || neg_const_double_rtx_ok_for_fpu (X))) \
889 || CONSTANT_ADDRESS_P (X))
890
891 /* Symbols in the text segment can be accessed without indirecting via the
892 constant pool; it may take an extra binary operation, but this is still
893 faster than indirecting via memory. Don't do this when not optimizing,
894 since we won't be calculating al of the offsets necessary to do this
895 simplification. */
896
897 #define ENCODE_SECTION_INFO(decl) \
898 { \
899 if (optimize > 0 && TREE_CONSTANT (decl) \
900 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
901 { \
902 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
903 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
904 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
905 } \
906 }
907
908 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
909 and check its validity for a certain class.
910 We have two alternate definitions for each of them.
911 The usual definition accepts all pseudo regs; the other rejects
912 them unless they have been allocated suitable hard regs.
913 The symbol REG_OK_STRICT causes the latter definition to be used. */
914 #ifndef REG_OK_STRICT
915
916 /* Nonzero if X is a hard reg that can be used as a base reg
917 or if it is a pseudo reg. */
918 #define REG_OK_FOR_BASE_P(X) \
919 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
920 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
921
922 /* Nonzero if X is a hard reg that can be used as an index
923 or if it is a pseudo reg. */
924 #define REG_OK_FOR_INDEX_P(X) \
925 REG_OK_FOR_BASE_P(X)
926
927 #define REG_OK_FOR_PRE_POST_P(X) \
928 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
929 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
930
931 #else
932
933 /* Nonzero if X is a hard reg that can be used as a base reg. */
934 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
935
936 /* Nonzero if X is a hard reg that can be used as an index. */
937 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
938
939 #define REG_OK_FOR_PRE_POST_P(X) \
940 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
941 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
942 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
943 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
944
945 #endif
946 \f
947 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
948 that is a valid memory address for an instruction.
949 The MODE argument is the machine mode for the MEM expression
950 that wants to use this address.
951
952 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
953 #define BASE_REGISTER_RTX_P(X) \
954 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
955
956 #define INDEX_REGISTER_RTX_P(X) \
957 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
958
959 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
960 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
961 only be small constants. */
962 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
963 do \
964 { \
965 HOST_WIDE_INT range; \
966 enum rtx_code code = GET_CODE (INDEX); \
967 \
968 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
969 { \
970 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
971 && INTVAL (INDEX) > -1024 \
972 && (INTVAL (INDEX) & 3) == 0) \
973 goto LABEL; \
974 } \
975 else \
976 { \
977 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
978 goto LABEL; \
979 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
980 { \
981 rtx xiop0 = XEXP (INDEX, 0); \
982 rtx xiop1 = XEXP (INDEX, 1); \
983 if (INDEX_REGISTER_RTX_P (xiop0) \
984 && power_of_two_operand (xiop1, SImode)) \
985 goto LABEL; \
986 if (INDEX_REGISTER_RTX_P (xiop1) \
987 && power_of_two_operand (xiop0, SImode)) \
988 goto LABEL; \
989 } \
990 if (GET_MODE_SIZE (MODE) <= 4 \
991 && (code == LSHIFTRT || code == ASHIFTRT \
992 || code == ASHIFT || code == ROTATERT)) \
993 { \
994 rtx op = XEXP (INDEX, 1); \
995 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
996 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
997 && INTVAL (op) <= 31) \
998 goto LABEL; \
999 } \
1000 range = (MODE) == HImode ? 4095 : 4096; \
1001 if (code == CONST_INT && INTVAL (INDEX) < range \
1002 && INTVAL (INDEX) > -range) \
1003 goto LABEL; \
1004 } \
1005 } while (0)
1006
1007 /* Jump to LABEL if X is a valid address RTX. This must also take
1008 REG_OK_STRICT into account when deciding about valid registers, but it uses
1009 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1010 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1011 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1012 refs must be forced though a static cell to ensure addressability. */
1013 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1014 { \
1015 if (BASE_REGISTER_RTX_P (X)) \
1016 goto LABEL; \
1017 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1018 && GET_CODE (XEXP (X, 0)) == REG \
1019 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1020 goto LABEL; \
1021 else if ((MODE) == TImode) \
1022 ; \
1023 else if (GET_CODE (X) == PLUS) \
1024 { \
1025 rtx xop0 = XEXP(X,0); \
1026 rtx xop1 = XEXP(X,1); \
1027 \
1028 if (BASE_REGISTER_RTX_P (xop0)) \
1029 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1030 else if (BASE_REGISTER_RTX_P (xop1)) \
1031 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1032 } \
1033 else if (GET_CODE (X) == MINUS) \
1034 { \
1035 rtx xop0 = XEXP (X,0); \
1036 rtx xop1 = XEXP (X,1); \
1037 \
1038 if (BASE_REGISTER_RTX_P (xop0)) \
1039 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1040 } \
1041 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1042 && GET_CODE (X) == SYMBOL_REF \
1043 && CONSTANT_POOL_ADDRESS_P (X)) \
1044 goto LABEL; \
1045 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1046 && GET_CODE (XEXP (X, 0)) == REG \
1047 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1048 goto LABEL; \
1049 }
1050 \f
1051 /* Try machine-dependent ways of modifying an illegitimate address
1052 to be legitimate. If we find one, return the new, valid address.
1053 This macro is used in only one place: `memory_address' in explow.c.
1054
1055 OLDX is the address as it was before break_out_memory_refs was called.
1056 In some cases it is useful to look at this to decide what needs to be done.
1057
1058 MODE and WIN are passed so that this macro can use
1059 GO_IF_LEGITIMATE_ADDRESS.
1060
1061 It is always safe for this macro to do nothing. It exists to recognize
1062 opportunities to optimize the output.
1063
1064 On the ARM, try to convert [REG, #BIGCONST]
1065 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1066 where VALIDCONST == 0 in case of TImode. */
1067 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1068 { \
1069 if (GET_CODE (X) == PLUS) \
1070 { \
1071 rtx xop0 = XEXP (X, 0); \
1072 rtx xop1 = XEXP (X, 1); \
1073 \
1074 if (CONSTANT_P (xop0) && ! LEGITIMATE_CONSTANT_P (xop0)) \
1075 xop0 = force_reg (SImode, xop0); \
1076 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1077 xop1 = force_reg (SImode, xop1); \
1078 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1079 { \
1080 HOST_WIDE_INT n, low_n; \
1081 rtx base_reg, val; \
1082 n = INTVAL (xop1); \
1083 \
1084 if (MODE == DImode) \
1085 { \
1086 low_n = n & 0x0f; \
1087 n &= ~0x0f; \
1088 if (low_n > 4) \
1089 { \
1090 n += 16; \
1091 low_n -= 16; \
1092 } \
1093 } \
1094 else \
1095 { \
1096 low_n = ((MODE) == TImode ? 0 \
1097 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1098 n -= low_n; \
1099 } \
1100 base_reg = gen_reg_rtx (SImode); \
1101 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1102 GEN_INT (n)), NULL_RTX); \
1103 emit_move_insn (base_reg, val); \
1104 (X) = (low_n == 0 ? base_reg \
1105 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1106 } \
1107 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1108 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1109 } \
1110 else if (GET_CODE (X) == MINUS) \
1111 { \
1112 rtx xop0 = XEXP (X, 0); \
1113 rtx xop1 = XEXP (X, 1); \
1114 \
1115 if (CONSTANT_P (xop0)) \
1116 xop0 = force_reg (SImode, xop0); \
1117 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1118 xop1 = force_reg (SImode, xop1); \
1119 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1120 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1121 } \
1122 if (memory_address_p (MODE, X)) \
1123 goto WIN; \
1124 }
1125
1126
1127 /* Go to LABEL if ADDR (a legitimate address expression)
1128 has an effect that depends on the machine mode it is used for. */
1129 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1130 { \
1131 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1132 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1133 goto LABEL; \
1134 }
1135 \f
1136 /* Specify the machine mode that this machine uses
1137 for the index in the tablejump instruction. */
1138 #define CASE_VECTOR_MODE SImode
1139
1140 /* Define this if the tablejump instruction expects the table
1141 to contain offsets from the address of the table.
1142 Do not define this if the table should contain absolute addresses. */
1143 /* #define CASE_VECTOR_PC_RELATIVE */
1144
1145 /* Specify the tree operation to be used to convert reals to integers. */
1146 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1147
1148 /* This is the kind of divide that is easiest to do in the general case. */
1149 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1150
1151 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1152 unsigned is probably best, but may break some code. */
1153 #ifndef DEFAULT_SIGNED_CHAR
1154 #define DEFAULT_SIGNED_CHAR 0
1155 #endif
1156
1157 /* Don't cse the address of the function being compiled. */
1158 #define NO_RECURSIVE_FUNCTION_CSE 1
1159
1160 /* Max number of bytes we can move from memory to memory
1161 in one reasonably fast instruction. */
1162 #define MOVE_MAX 4
1163
1164 /* Define if operations between registers always perform the operation
1165 on the full register even if a narrower mode is specified. */
1166 #define WORD_REGISTER_OPERATIONS
1167
1168 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1169 will either zero-extend or sign-extend. The value of this macro should
1170 be the code that says which one of the two operations is implicitly
1171 done, NIL if none. */
1172 #define LOAD_EXTEND_OP(MODE) \
1173 ((MODE) == QImode ? ZERO_EXTEND \
1174 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1175
1176 /* Define this if zero-extension is slow (more than one real instruction).
1177 On the ARM, it is more than one instruction only if not fetching from
1178 memory. */
1179 /* #define SLOW_ZERO_EXTEND */
1180
1181 /* Nonzero if access to memory by bytes is slow and undesirable. */
1182 #define SLOW_BYTE_ACCESS 0
1183
1184 /* Immediate shift counts are truncated by the output routines (or was it
1185 the assembler?). Shift counts in a register are truncated by ARM. Note
1186 that the native compiler puts too large (> 32) immediate shift counts
1187 into a register and shifts by the register, letting the ARM decide what
1188 to do instead of doing that itself. */
1189 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1190 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1191 On the arm, Y in a register is used modulo 256 for the shift. Only for
1192 rotates is modulo 32 used. */
1193 /* #define SHIFT_COUNT_TRUNCATED 1 */
1194
1195 /* XX This is not true, is it? */
1196 /* All integers have the same format so truncation is easy. */
1197 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1198
1199 /* Calling from registers is a massive pain. */
1200 #define NO_FUNCTION_CSE 1
1201
1202 /* Chars and shorts should be passed as ints. */
1203 #define PROMOTE_PROTOTYPES 1
1204
1205 /* The machine modes of pointers and functions */
1206 #define Pmode SImode
1207 #define FUNCTION_MODE Pmode
1208
1209 /* The structure type of the machine dependent info field of insns
1210 No uses for this yet. */
1211 /* #define INSN_MACHINE_INFO struct machine_info */
1212
1213 /* The relative costs of various types of constants. Note that cse.c defines
1214 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1215 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1216 case CONST_INT: \
1217 if (const_ok_for_arm (INTVAL (RTX))) \
1218 return (OUTER_CODE) == SET ? 2 : -1; \
1219 else if (OUTER_CODE == AND \
1220 && const_ok_for_arm (~INTVAL (RTX))) \
1221 return -1; \
1222 else if ((OUTER_CODE == COMPARE \
1223 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1224 && const_ok_for_arm (-INTVAL (RTX))) \
1225 return -1; \
1226 else \
1227 return 5; \
1228 case CONST: \
1229 case LABEL_REF: \
1230 case SYMBOL_REF: \
1231 return 6; \
1232 case CONST_DOUBLE: \
1233 if (const_double_rtx_ok_for_fpu (RTX)) \
1234 return (OUTER_CODE) == SET ? 2 : -1; \
1235 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1236 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1237 return -1; \
1238 return(7);
1239
1240 #define ARM_FRAME_RTX(X) \
1241 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1242 || (X) == arg_pointer_rtx)
1243
1244 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1245 default: \
1246 return arm_rtx_costs (X, CODE, OUTER_CODE);
1247
1248 /* Moves to and from memory are quite expensive */
1249 #define MEMORY_MOVE_COST(MODE) 10
1250
1251 /* All address computations that can be done are free, but rtx cost returns
1252 the same for practically all of them. So we weight the differnt types
1253 of address here in the order (most pref first):
1254 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1255 #define ADDRESS_COST(X) \
1256 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1257 || GET_CODE (X) == SYMBOL_REF) \
1258 ? 0 \
1259 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1260 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1261 ? 10 \
1262 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1263 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1264 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1265 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1266 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1267 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1268 ? 1 : 0)) \
1269 : 4)))))
1270
1271
1272
1273 /* Try to generate sequences that don't involve branches, we can then use
1274 conditional instructions */
1275 #define BRANCH_COST 4
1276 \f
1277 /* Condition code information. */
1278 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1279 return the mode to be used for the comparison.
1280 CCFPEmode should be used with floating inequalites,
1281 CCFPmode should be used with floating equalities.
1282 CC_NOOVmode should be used with SImode integer equalites
1283 CCmode should be used otherwise. */
1284
1285 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1286
1287 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1288
1289 #define SELECT_CC_MODE(OP,X,Y) \
1290 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1291 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1292 : ((GET_MODE (X) == SImode) \
1293 && ((OP) == EQ || (OP) == NE) \
1294 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1295 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1296 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1297 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1298 || GET_CODE (X) == LSHIFTRT \
1299 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1300 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1301 ? CC_NOOVmode \
1302 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1303
1304 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1305
1306 #define STORE_FLAG_VALUE 1
1307
1308 /* Define the information needed to generate branch insns. This is
1309 stored from the compare operation. Note that we can't use "rtx" here
1310 since it hasn't been defined! */
1311
1312 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1313 extern int arm_compare_fp;
1314
1315 /* Define the codes that are matched by predicates in arm.c */
1316 #define PREDICATE_CODES \
1317 {"s_register_operand", {SUBREG, REG}}, \
1318 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1319 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1320 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1321 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1322 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1323 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1324 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1325 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1326 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1327 {"load_multiple_operation", {PARALLEL}}, \
1328 {"store_multiple_operation", {PARALLEL}}, \
1329 {"equality_operator", {EQ, NE}}, \
1330 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1331 {"const_shift_operand", {CONST_INT}}, \
1332 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1333 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1334 {"multi_register_push", {PARALLEL}}, \
1335 {"cc_register", {REG}},
1336
1337 \f
1338 /* Assembler output control */
1339
1340 #ifndef ARM_OS_NAME
1341 #define ARM_OS_NAME "(generic)"
1342 #endif
1343
1344 /* The text to go at the start of the assembler file */
1345 #define ASM_FILE_START(STREAM) \
1346 { \
1347 extern char *version_string; \
1348 fprintf (STREAM,"%c Generated by gcc %s for ARM/%s\n", \
1349 ARM_COMMENT_CHAR, version_string, ARM_OS_NAME); \
1350 fprintf (STREAM,"%srfp\t.req\t%sr9\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1351 fprintf (STREAM,"%ssl\t.req\t%sr10\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1352 fprintf (STREAM,"%sfp\t.req\t%sr11\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1353 fprintf (STREAM,"%sip\t.req\t%sr12\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1354 fprintf (STREAM,"%ssp\t.req\t%sr13\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1355 fprintf (STREAM,"%slr\t.req\t%sr14\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1356 fprintf (STREAM,"%spc\t.req\t%sr15\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1357 }
1358
1359 #define ASM_APP_ON ""
1360 #define ASM_APP_OFF ""
1361
1362 /* Switch to the text or data segment. */
1363 #define TEXT_SECTION_ASM_OP ".text"
1364 #define DATA_SECTION_ASM_OP ".data"
1365
1366 /* The assembler's names for the registers. */
1367 #ifndef REGISTER_NAMES
1368 #define REGISTER_NAMES \
1369 { \
1370 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1371 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
1372 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1373 "cc", "sfp", "afp" \
1374 }
1375 #endif
1376
1377 #ifndef ADDITIONAL_REGISTER_NAMES
1378 #define ADDITIONAL_REGISTER_NAMES \
1379 { \
1380 {"a1", 0}, \
1381 {"a2", 1}, \
1382 {"a3", 2}, \
1383 {"a4", 3}, \
1384 {"v1", 4}, \
1385 {"v2", 5}, \
1386 {"v3", 6}, \
1387 {"v4", 7}, \
1388 {"v5", 8}, \
1389 {"v6", 9}, \
1390 {"rfp", 9}, /* Gcc used to call it this */ \
1391 {"sb", 9}, \
1392 {"v7", 10}, \
1393 {"r10", 10}, \
1394 {"r11", 11}, /* fp */ \
1395 {"r12", 12}, /* ip */ \
1396 {"r13", 13}, /* sp */ \
1397 {"r14", 14}, /* lr */ \
1398 {"r15", 15} /* pc */ \
1399 }
1400 #endif
1401
1402 /* Arm Assembler barfs on dollars */
1403 #define DOLLARS_IN_IDENTIFIERS 0
1404
1405 #define NO_DOLLAR_IN_LABEL
1406
1407 /* DBX register number for a given compiler register number */
1408 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1409
1410 /* Generate DBX debugging information. riscix.h will undefine this because
1411 the native assembler does not support stabs. */
1412 #define DBX_DEBUGGING_INFO 1
1413
1414 /* Acorn dbx moans about continuation chars, so don't use any. */
1415 #ifndef DBX_CONTIN_LENGTH
1416 #define DBX_CONTIN_LENGTH 0
1417 #endif
1418
1419 /* Output a source filename for the debugger. RISCiX dbx insists that the
1420 ``desc'' field is set to compiler version number >= 315 (sic). */
1421 #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1422 do { \
1423 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1424 &ltext_label_name[1]); \
1425 text_section (); \
1426 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1427 } while (0)
1428
1429 /* Output a label definition. */
1430 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1431 arm_asm_output_label ((STREAM), (NAME))
1432
1433 /* Output a function label definition. */
1434 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1435 ASM_OUTPUT_LABEL(STREAM, NAME)
1436
1437 /* Output a globalising directive for a label. */
1438 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1439 (fprintf (STREAM, "\t.global\t"), \
1440 assemble_name (STREAM, NAME), \
1441 fputc ('\n',STREAM)) \
1442
1443 /* Output a reference to a label. */
1444 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1445 fprintf (STREAM, "_%s", NAME)
1446
1447 /* Make an internal label into a string. */
1448 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1449 sprintf (STRING, "*%s%d", PREFIX, NUM)
1450
1451 /* Output an internal label definition. */
1452 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1453 do \
1454 { \
1455 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1456 extern int arm_target_label, arm_ccfsm_state; \
1457 extern rtx arm_target_insn; \
1458 \
1459 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1460 && !strcmp (PREFIX, "L")) \
1461 { \
1462 arm_ccfsm_state = 0; \
1463 arm_target_insn = NULL; \
1464 } \
1465 strcpy (s, "*"); \
1466 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1467 arm_asm_output_label (STREAM, s); \
1468 } while (0)
1469
1470 /* Nothing special is done about jump tables */
1471 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1472 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1473
1474 /* Construct a private name. */
1475 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1476 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1477 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1478
1479 /* Output a push or a pop instruction (only used when profiling). */
1480 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1481 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1482 reg_names[REGNO])
1483
1484 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1485 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1486 reg_names[REGNO])
1487
1488 /* Output a relative address. Not needed since jump tables are absolute
1489 but we must define it anyway. */
1490 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1491 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1492
1493 /* Output an element of a dispatch table. */
1494 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1495 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
1496
1497 /* Output various types of constants. For real numbers we output hex, with
1498 a comment containing the "human" value, this allows us to pass NaN's which
1499 the riscix assembler doesn't understand (it also makes cross-assembling
1500 less likely to fail). */
1501
1502 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
1503 do { char dstr[30]; \
1504 long l[3]; \
1505 arm_increase_location (12); \
1506 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1507 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1508 if (sizeof (int) == sizeof (long)) \
1509 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%c long double %s\n", \
1510 l[2], l[1], l[0], ARM_COMMENT_CHAR, dstr); \
1511 else \
1512 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%c long double %s\n",\
1513 l[0], l[1], l[2], ARM_COMMENT_CHAR, dstr); \
1514 } while (0)
1515
1516
1517 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1518 do { char dstr[30]; \
1519 long l[2]; \
1520 arm_increase_location (8); \
1521 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1522 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1523 if (sizeof (int) == sizeof (long)) \
1524 fprintf (STREAM, "\t.long 0x%x, 0x%x\t%c double %s\n", l[0], \
1525 l[1], ARM_COMMENT_CHAR, dstr); \
1526 else \
1527 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%c double %s\n", l[0], \
1528 l[1], ARM_COMMENT_CHAR, dstr); \
1529 } while (0)
1530
1531 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1532 do { char dstr[30]; \
1533 long l; \
1534 arm_increase_location (4); \
1535 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1536 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1537 if (sizeof (int) == sizeof (long)) \
1538 fprintf (STREAM, "\t.word 0x%x\t%c float %s\n", l, \
1539 ARM_COMMENT_CHAR, dstr); \
1540 else \
1541 fprintf (STREAM, "\t.word 0x%lx\t%c float %s\n", l, \
1542 ARM_COMMENT_CHAR, dstr); \
1543 } while (0);
1544
1545 #define ASM_OUTPUT_INT(STREAM, EXP) \
1546 (fprintf (STREAM, "\t.word\t"), \
1547 output_addr_const (STREAM, (EXP)), \
1548 arm_increase_location (4), \
1549 fputc ('\n', STREAM))
1550
1551 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1552 (fprintf (STREAM, "\t.short\t"), \
1553 output_addr_const (STREAM, (EXP)), \
1554 arm_increase_location (2), \
1555 fputc ('\n', STREAM))
1556
1557 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1558 (fprintf (STREAM, "\t.byte\t"), \
1559 output_addr_const (STREAM, (EXP)), \
1560 arm_increase_location (1), \
1561 fputc ('\n', STREAM))
1562
1563 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1564 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1565 arm_increase_location (1))
1566
1567 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1568 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
1569
1570 /* Output a gap. In fact we fill it with nulls. */
1571 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1572 (arm_increase_location (NBYTES), \
1573 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1574
1575 /* Align output to a power of two. Horrible /bin/as. */
1576 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1577 do \
1578 { \
1579 register int amount = 1 << (POWER); \
1580 extern int arm_text_location; \
1581 \
1582 if (amount == 2) \
1583 fprintf (STREAM, "\t.even\n"); \
1584 else \
1585 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1586 \
1587 if (in_text_section ()) \
1588 arm_text_location = ((arm_text_location + amount - 1) \
1589 & ~(amount - 1)); \
1590 } while (0)
1591
1592 /* Output a common block */
1593 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1594 (fprintf (STREAM, "\t.comm\t"), \
1595 assemble_name ((STREAM), (NAME)), \
1596 fprintf(STREAM, ", %d\t%c%d\n", ROUNDED, ARM_COMMENT_CHAR, SIZE))
1597
1598 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1599 the bss segment. Note that this is *bad* practice. */
1600 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1601 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1602
1603 /* Output a source line for the debugger. */
1604 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1605
1606 /* Output a #ident directive. */
1607 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1608 fprintf (STREAM,"- - - ident %s\n",STRING)
1609
1610 /* The assembler's parentheses characters. */
1611 #define ASM_OPEN_PAREN "("
1612 #define ASM_CLOSE_PAREN ")"
1613
1614 /* Target characters. */
1615 #define TARGET_BELL 007
1616 #define TARGET_BS 010
1617 #define TARGET_TAB 011
1618 #define TARGET_NEWLINE 012
1619 #define TARGET_VT 013
1620 #define TARGET_FF 014
1621 #define TARGET_CR 015
1622 \f
1623 /* Only perform branch elimination (by making instructions conditional) if
1624 we're optimising. Otherwise it's of no use anyway. */
1625 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1626 if (optimize) \
1627 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1628
1629 #ifndef ARM_COMMENT_CHAR
1630 #define ARM_COMMENT_CHAR '@'
1631 #endif
1632
1633 /* Default is for register names not to have a prefix. */
1634 #ifndef ARM_REG_PREFIX
1635 #define ARM_REG_PREFIX ""
1636 #endif
1637
1638 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1639 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1640 /* Output an operand of an instruction. */
1641 #define PRINT_OPERAND(STREAM, X, CODE) \
1642 arm_print_operand (STREAM, X, CODE)
1643
1644 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1645 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1646 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1647 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1648 ? ((~ (HOST_WIDE_INT) 0) \
1649 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1650 : 0))))
1651
1652 /* Output the address of an operand. */
1653 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1654 { \
1655 int is_minus = GET_CODE (X) == MINUS; \
1656 \
1657 if (GET_CODE (X) == REG) \
1658 fprintf (STREAM, "[%s%s, #0]", ARM_REG_PREFIX, \
1659 reg_names[REGNO (X)]); \
1660 else if (GET_CODE (X) == PLUS || is_minus) \
1661 { \
1662 rtx base = XEXP (X, 0); \
1663 rtx index = XEXP (X, 1); \
1664 char *base_reg_name; \
1665 HOST_WIDE_INT offset = 0; \
1666 if (GET_CODE (base) != REG) \
1667 { \
1668 /* Ensure that BASE is a register (one of them must be). */ \
1669 rtx temp = base; \
1670 base = index; \
1671 index = temp; \
1672 } \
1673 base_reg_name = reg_names[REGNO (base)]; \
1674 switch (GET_CODE (index)) \
1675 { \
1676 case CONST_INT: \
1677 offset = INTVAL (index); \
1678 if (is_minus) \
1679 offset = -offset; \
1680 fprintf (STREAM, "[%s%s, #%d]", ARM_REG_PREFIX, \
1681 base_reg_name, offset); \
1682 break; \
1683 \
1684 case REG: \
1685 fprintf (STREAM, "[%s%s, %s%s%s]", ARM_REG_PREFIX, \
1686 base_reg_name, is_minus ? "-" : "", \
1687 ARM_REG_PREFIX, reg_names[REGNO (index)] ); \
1688 break; \
1689 \
1690 case MULT: \
1691 case ASHIFTRT: \
1692 case LSHIFTRT: \
1693 case ASHIFT: \
1694 case ROTATERT: \
1695 { \
1696 fprintf (STREAM, "[%s%s, %s%s%s", ARM_REG_PREFIX, \
1697 base_reg_name, is_minus ? "-" : "", ARM_REG_PREFIX,\
1698 reg_names[REGNO (XEXP (index, 0))]); \
1699 arm_print_operand (STREAM, index, 'S'); \
1700 fputs ("]", STREAM); \
1701 break; \
1702 } \
1703 \
1704 default: \
1705 abort(); \
1706 } \
1707 } \
1708 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1709 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1710 { \
1711 extern int output_memory_reference_mode; \
1712 \
1713 if (GET_CODE (XEXP (X, 0)) != REG) \
1714 abort (); \
1715 \
1716 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1717 fprintf (STREAM, "[%s%s, #%s%d]!", ARM_REG_PREFIX, \
1718 reg_names[REGNO (XEXP (X, 0))], \
1719 GET_CODE (X) == PRE_DEC ? "-" : "", \
1720 GET_MODE_SIZE (output_memory_reference_mode)); \
1721 else \
1722 fprintf (STREAM, "[%s%s], #%s%d", ARM_REG_PREFIX, \
1723 reg_names[REGNO (XEXP (X, 0))], \
1724 GET_CODE (X) == POST_DEC ? "-" : "", \
1725 GET_MODE_SIZE (output_memory_reference_mode)); \
1726 } \
1727 else output_addr_const(STREAM, X); \
1728 }
Mirror of the offical gcc git repository hosted at gcc.gnu.org