gcc/config/arm/arm-protos.h

   1 /* Prototypes for exported functions defined in arm.c and pe.c
   2    Copyright (C) 1999-2016 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rearnsha@arm.com)
   4    Minor hacks by Nick Clifton (nickc@cygnus.com)
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    GCC is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_ARM_PROTOS_H
  23 #define GCC_ARM_PROTOS_H
  24
  25 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
  26 extern int use_return_insn (int, rtx);
  27 extern bool use_simple_return_p (void);
  28 extern enum reg_class arm_regno_class (int);
  29 extern void arm_load_pic_register (unsigned long);
  30 extern int arm_volatile_func (void);
  31 extern void arm_expand_prologue (void);
  32 extern void arm_expand_epilogue (bool);
  33 extern void arm_declare_function_name (FILE *, const char *, tree);
  34 extern void thumb2_expand_return (bool);
  35 extern const char *arm_strip_name_encoding (const char *);
  36 extern void arm_asm_output_labelref (FILE *, const char *);
  37 extern void thumb2_asm_output_opcode (FILE *);
  38 extern unsigned long arm_current_func_type (void);
  39 extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
  40                                                              unsigned int);
  41 extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
  42                                                                unsigned int);
  43 extern unsigned int arm_dbx_register_number (unsigned int);
  44 extern void arm_output_fn_unwind (FILE *, bool);
  45
  46 extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
  47                                ATTRIBUTE_UNUSED, enum machine_mode mode
  48                                ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
  49 extern tree arm_builtin_decl (unsigned code, bool initialize_p
  50                               ATTRIBUTE_UNUSED);
  51 extern void arm_init_builtins (void);
  52 extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
  53 extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
  54 extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
  55                                                  bool high);
  56 #ifdef RTX_CODE
  57 extern bool arm_vector_mode_supported_p (machine_mode);
  58 extern bool arm_small_register_classes_for_mode_p (machine_mode);
  59 extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
  60 extern bool arm_modes_tieable_p (machine_mode, machine_mode);
  61 extern int const_ok_for_arm (HOST_WIDE_INT);
  62 extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
  63 extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
  64 extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
  65                                HOST_WIDE_INT, rtx, rtx, int);
  66 extern int legitimate_pic_operand_p (rtx);
  67 extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
  68 extern rtx legitimize_tls_address (rtx, rtx);
  69 extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
  70 extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
  71 extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
  72 extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
  73 extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
  74                                  bool, bool);
  75 extern int arm_const_double_rtx (rtx);
  76 extern int vfp3_const_double_rtx (rtx);
  77 extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
  78 extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
  79                                            int *);
  80 extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
  81                                            int *, bool);
  82 extern char *neon_output_logic_immediate (const char *, rtx *,
  83                                           machine_mode, int, int);
  84 extern char *neon_output_shift_immediate (const char *, char, rtx *,
  85                                           machine_mode, int, bool);
  86 extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
  87                                   rtx (*) (rtx, rtx, rtx));
  88 extern rtx neon_make_constant (rtx);
  89 extern tree arm_builtin_vectorized_function (unsigned int, tree, tree);
  90 extern void neon_expand_vector_init (rtx, rtx);
  91 extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
  92 extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
  93 extern HOST_WIDE_INT neon_element_bits (machine_mode);
  94 extern void neon_emit_pair_result_insn (machine_mode,
  95                                         rtx (*) (rtx, rtx, rtx, rtx),
  96                                         rtx, rtx, rtx);
  97 extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
  98 extern void neon_split_vcombine (rtx op[3]);
  99 extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
 100                                                      bool);
 101 extern bool arm_tls_referenced_p (rtx);
 102
 103 extern int arm_coproc_mem_operand (rtx, bool);
 104 extern int neon_vector_mem_operand (rtx, int, bool);
 105 extern int neon_struct_mem_operand (rtx);
 106
 107 extern int tls_mentioned_p (rtx);
 108 extern int symbol_mentioned_p (rtx);
 109 extern int label_mentioned_p (rtx);
 110 extern RTX_CODE minmax_code (rtx);
 111 extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
 112 extern int adjacent_mem_locations (rtx, rtx);
 113 extern bool gen_ldm_seq (rtx *, int, bool);
 114 extern bool gen_stm_seq (rtx *, int);
 115 extern bool gen_const_stm_seq (rtx *, int);
 116 extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
 117 extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
 118 extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
 119 extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
 120 extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
 121 extern int arm_gen_movmemqi (rtx *);
 122 extern bool gen_movmem_ldrd_strd (rtx *);
 123 extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
 124 extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
 125                                                        HOST_WIDE_INT);
 126 extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
 127 extern rtx arm_gen_return_addr_mask (void);
 128 extern void arm_reload_in_hi (rtx *);
 129 extern void arm_reload_out_hi (rtx *);
 130 extern int arm_max_const_double_inline_cost (void);
 131 extern int arm_const_double_inline_cost (rtx);
 132 extern bool arm_const_double_by_parts (rtx);
 133 extern bool arm_const_double_by_immediates (rtx);
 134 extern void arm_emit_call_insn (rtx, rtx, bool);
 135 extern const char *output_call (rtx *);
 136 void arm_emit_movpair (rtx, rtx);
 137 extern const char *output_mov_long_double_arm_from_arm (rtx *);
 138 extern const char *output_move_double (rtx *, bool, int *count);
 139 extern const char *output_move_quad (rtx *);
 140 extern int arm_count_output_move_double_insns (rtx *);
 141 extern const char *output_move_vfp (rtx *operands);
 142 extern const char *output_move_neon (rtx *operands);
 143 extern int arm_attr_length_move_neon (rtx_insn *);
 144 extern int arm_address_offset_is_imm (rtx_insn *);
 145 extern const char *output_add_immediate (rtx *);
 146 extern const char *arithmetic_instr (rtx, int);
 147 extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
 148 extern const char *output_return_instruction (rtx, bool, bool, bool);
 149 extern const char *output_probe_stack_range (rtx, rtx);
 150 extern void arm_poke_function_name (FILE *, const char *);
 151 extern void arm_final_prescan_insn (rtx_insn *);
 152 extern int arm_debugger_arg_offset (int, rtx);
 153 extern bool arm_is_long_call_p (tree);
 154 extern int    arm_emit_vector_const (FILE *, rtx);
 155 extern void arm_emit_fp16_const (rtx c);
 156 extern const char * arm_output_load_gr (rtx *);
 157 extern const char *vfp_output_vstmd (rtx *);
 158 extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
 159 extern void arm_set_return_address (rtx, rtx);
 160 extern int arm_eliminable_register (rtx);
 161 extern const char *arm_output_shift(rtx *, int);
 162 extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
 163 extern const char *arm_output_iwmmxt_tinsr (rtx *);
 164 extern unsigned int arm_sync_loop_insns (rtx , rtx *);
 165 extern int arm_attr_length_push_multi(rtx, rtx);
 166 extern int arm_attr_length_pop_multi(rtx *, bool, bool);
 167 extern void arm_expand_compare_and_swap (rtx op[]);
 168 extern void arm_split_compare_and_swap (rtx op[]);
 169 extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 170 extern rtx arm_load_tp (rtx);
 171
 172 #if defined TREE_CODE
 173 extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
 174 extern bool arm_pad_arg_upward (machine_mode, const_tree);
 175 extern bool arm_pad_reg_upward (machine_mode, tree, int);
 176 #endif
 177 extern int arm_apply_result_size (void);
 178
 179 #endif /* RTX_CODE */
 180
 181 /* Thumb functions.  */
 182 extern void arm_init_expanders (void);
 183 extern const char *thumb1_unexpanded_epilogue (void);
 184 extern void thumb1_expand_prologue (void);
 185 extern void thumb1_expand_epilogue (void);
 186 extern const char *thumb1_output_interwork (void);
 187 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
 188 #ifdef RTX_CODE
 189 extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
 190 extern void thumb1_final_prescan_insn (rtx_insn *);
 191 extern void thumb2_final_prescan_insn (rtx_insn *);
 192 extern const char *thumb_load_double_from_address (rtx *);
 193 extern const char *thumb_output_move_mem_multiple (int, rtx *);
 194 extern const char *thumb_call_via_reg (rtx);
 195 extern void thumb_expand_movmemqi (rtx *);
 196 extern rtx arm_return_addr (int, rtx);
 197 extern void thumb_reload_out_hi (rtx *);
 198 extern void thumb_set_return_address (rtx, rtx);
 199 extern const char *thumb1_output_casesi (rtx *);
 200 extern const char *thumb2_output_casesi (rtx *);
 201 #endif
 202
 203 /* Defined in pe.c.  */
 204 extern int arm_dllexport_name_p (const char *);
 205 extern int arm_dllimport_name_p (const char *);
 206
 207 #ifdef TREE_CODE
 208 extern void arm_pe_unique_section (tree, int);
 209 extern void arm_pe_encode_section_info (tree, rtx, int);
 210 extern int arm_dllexport_p (tree);
 211 extern int arm_dllimport_p (tree);
 212 extern void arm_mark_dllexport (tree);
 213 extern void arm_mark_dllimport (tree);
 214 extern bool arm_change_mode_p (tree);
 215 #endif
 216
 217 extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
 218                                              struct gcc_options *);
 219 extern void arm_pr_long_calls (struct cpp_reader *);
 220 extern void arm_pr_no_long_calls (struct cpp_reader *);
 221 extern void arm_pr_long_calls_off (struct cpp_reader *);
 222
 223 extern const char *arm_mangle_type (const_tree);
 224 extern const char *arm_mangle_builtin_type (const_tree);
 225
 226 extern void arm_order_regs_for_local_alloc (void);
 227
 228 extern int arm_max_conditional_execute ();
 229
 230 /* Vectorizer cost model implementation.  */
 231 struct cpu_vec_costs {
 232   const int scalar_stmt_cost;   /* Cost of any scalar operation, excluding
 233                                    load and store.  */
 234   const int scalar_load_cost;   /* Cost of scalar load.  */
 235   const int scalar_store_cost;  /* Cost of scalar store.  */
 236   const int vec_stmt_cost;      /* Cost of any vector operation, excluding
 237                                    load, store, vector-to-scalar and
 238                                    scalar-to-vector operation.  */
 239   const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */
 240   const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */
 241   const int vec_align_load_cost;   /* Cost of aligned vector load.  */
 242   const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */
 243   const int vec_unalign_store_cost; /* Cost of unaligned vector load.  */
 244   const int vec_store_cost;        /* Cost of vector store.  */
 245   const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer
 246                                           cost model.  */
 247   const int cond_not_taken_branch_cost;/* Cost of not taken branch for
 248                                           vectorizer cost model.  */
 249 };
 250
 251 #ifdef RTX_CODE
 252 /* This needs to be here because we need RTX_CODE and similar.  */
 253
 254 struct cpu_cost_table;
 255
 256 /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
 257    structure is modified.  */
 258
 259 struct tune_params
 260 {
 261   bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
 262   const struct cpu_cost_table *insn_extra_cost;
 263   bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
 264   int (*branch_cost) (bool, bool);
 265   /* Vectorizer costs.  */
 266   const struct cpu_vec_costs* vec_costs;
 267   int constant_limit;
 268   /* Maximum number of instructions to conditionalise.  */
 269   int max_insns_skipped;
 270   /* Maximum number of instructions to inline calls to memset.  */
 271   int max_insns_inline_memset;
 272   /* Issue rate of the processor.  */
 273   unsigned int issue_rate;
 274   /* Explicit prefetch data.  */
 275   struct
 276     {
 277       int num_slots;
 278       int l1_cache_size;
 279       int l1_cache_line_size;
 280     } prefetch;
 281   enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
 282     prefer_constant_pool: 1;
 283   /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM.  */
 284   enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
 285   /* The preference for non short cirtcuit operation when optimizing for
 286      performance. The first element covers Thumb state and the second one
 287      is for ARM state.  */
 288   enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE,
 289                                  LOG_OP_NON_SHORT_CIRCUIT_TRUE};
 290   log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1;
 291   log_op_non_short_circuit logical_op_non_short_circuit_arm: 1;
 292   /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding.  */
 293   enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
 294     disparage_flag_setting_t16_encodings: 2;
 295   enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
 296   /* Prefer to inline string operations like memset by using Neon.  */
 297   enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
 298     string_ops_prefer_neon: 1;
 299   /* Bitfield encoding the fusible pairs of instructions.  Use FUSE_OPS
 300      in an initializer if multiple fusion operations are supported on a
 301      target.  */
 302   enum fuse_ops
 303   {
 304     FUSE_NOTHING   = 0,
 305     FUSE_MOVW_MOVT = 1 << 0,
 306     FUSE_AES_AESMC = 1 << 1
 307   } fusible_ops: 2;
 308   /* Depth of scheduling queue to check for L2 autoprefetcher.  */
 309   enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
 310     sched_autopref: 2;
 311 };
 312
 313 /* Smash multiple fusion operations into a type that can be used for an
 314    initializer.  */
 315 #define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
 316
 317 extern const struct tune_params *current_tune;
 318 extern int vfp3_const_double_for_fract_bits (rtx);
 319 /* return power of two from operand, otherwise 0.  */
 320 extern int vfp3_const_double_for_bits (rtx);
 321
 322 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
 323                                            rtx);
 324 extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
 325 extern bool arm_valid_symbolic_address_p (rtx);
 326 extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
 327 #endif /* RTX_CODE */
 328
 329 extern bool arm_gen_setmem (rtx *);
 330 extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
 331 extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
 332
 333 extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
 334
 335 extern void arm_emit_eabi_attribute (const char *, int, int);
 336
 337 extern void arm_reset_previous_fndecl (void);
 338 extern void save_restore_target_globals (tree);
 339
 340 /* Defined in gcc/common/config/arm-common.c.  */
 341 extern const char *arm_rewrite_selected_cpu (const char *name);
 342
 343 /* Defined in gcc/common/config/arm-c.c.  */
 344 extern void arm_lang_object_attributes_init (void);
 345 extern void arm_register_target_pragmas (void);
 346 extern void arm_cpu_cpp_builtins (struct cpp_reader *);
 347
 348 extern bool arm_is_constant_pool_ref (rtx);
 349
 350 /* Flags used to identify the presence of processor capabilities.  */
 351
 352 /* Bit values used to identify processor capabilities.  */
 353 #define FL_NONE       (0)             /* No flags.  */
 354 #define FL_ANY        (0xffffffff)    /* All flags.  */
 355 #define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
 356 #define FL_ARCH3M     (1 << 1)        /* Extended multiply */
 357 #define FL_MODE26     (1 << 2)        /* 26-bit mode support */
 358 #define FL_MODE32     (1 << 3)        /* 32-bit mode support */
 359 #define FL_ARCH4      (1 << 4)        /* Architecture rel 4 */
 360 #define FL_ARCH5      (1 << 5)        /* Architecture rel 5 */
 361 #define FL_THUMB      (1 << 6)        /* Thumb aware */
 362 #define FL_LDSCHED    (1 << 7)        /* Load scheduling necessary */
 363 #define FL_STRONG     (1 << 8)        /* StrongARM */
 364 #define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
 365 #define FL_XSCALE     (1 << 10)       /* XScale */
 366 /* spare              (1 << 11) */
 367 #define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
 368                                          media instructions.  */
 369 #define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
 370 #define FL_WBUF       (1 << 14)       /* Schedule for write buffer ops.
 371                                          Note: ARM6 & 7 derivatives only.  */
 372 #define FL_ARCH6K     (1 << 15)       /* Architecture rel 6 K extensions.  */
 373 #define FL_THUMB2     (1 << 16)       /* Thumb-2.  */
 374 #define FL_NOTM       (1 << 17)       /* Instructions not present in the 'M'
 375                                          profile.  */
 376 #define FL_THUMB_DIV  (1 << 18)       /* Hardware divide (Thumb mode).  */
 377 #define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */
 378 #define FL_NEON       (1 << 20)       /* Neon instructions.  */
 379 #define FL_ARCH7EM    (1 << 21)       /* Instructions present in the ARMv7E-M
 380                                          architecture.  */
 381 #define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
 382 #define FL_ARM_DIV    (1 << 23)       /* Hardware divide (ARM mode).  */
 383 #define FL_ARCH8      (1 << 24)       /* Architecture 8.  */
 384 #define FL_CRC32      (1 << 25)       /* ARMv8 CRC32 instructions.  */
 385
 386 #define FL_SMALLMUL   (1 << 26)       /* Small multiply supported.  */
 387 #define FL_NO_VOLATILE_CE   (1 << 27) /* No volatile memory in IT block.  */
 388
 389 #define FL_IWMMXT     (1 << 29)       /* XScale v2 or "Intel Wireless MMX technology".  */
 390 #define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
 391 #define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
 392
 393 #define FL2_ARCH8_1   (1 << 0)        /* Architecture 8.1.  */
 394
 395 /* Flags that only effect tuning, not available instructions.  */
 396 #define FL_TUNE         (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
 397                          | FL_CO_PROC)
 398
 399 #define FL_FOR_ARCH2            FL_NOTM
 400 #define FL_FOR_ARCH3            (FL_FOR_ARCH2 | FL_MODE32)
 401 #define FL_FOR_ARCH3M           (FL_FOR_ARCH3 | FL_ARCH3M)
 402 #define FL_FOR_ARCH4            (FL_FOR_ARCH3M | FL_ARCH4)
 403 #define FL_FOR_ARCH4T           (FL_FOR_ARCH4 | FL_THUMB)
 404 #define FL_FOR_ARCH5            (FL_FOR_ARCH4 | FL_ARCH5)
 405 #define FL_FOR_ARCH5T           (FL_FOR_ARCH5 | FL_THUMB)
 406 #define FL_FOR_ARCH5E           (FL_FOR_ARCH5 | FL_ARCH5E)
 407 #define FL_FOR_ARCH5TE          (FL_FOR_ARCH5E | FL_THUMB)
 408 #define FL_FOR_ARCH5TEJ         FL_FOR_ARCH5TE
 409 #define FL_FOR_ARCH6            (FL_FOR_ARCH5TE | FL_ARCH6)
 410 #define FL_FOR_ARCH6J           FL_FOR_ARCH6
 411 #define FL_FOR_ARCH6K           (FL_FOR_ARCH6 | FL_ARCH6K)
 412 #define FL_FOR_ARCH6Z           FL_FOR_ARCH6
 413 #define FL_FOR_ARCH6ZK          FL_FOR_ARCH6K
 414 #define FL_FOR_ARCH6KZ          (FL_FOR_ARCH6K | FL_ARCH6KZ)
 415 #define FL_FOR_ARCH6T2          (FL_FOR_ARCH6 | FL_THUMB2)
 416 #define FL_FOR_ARCH6M           (FL_FOR_ARCH6 & ~FL_NOTM)
 417 #define FL_FOR_ARCH7            ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
 418 #define FL_FOR_ARCH7A           (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
 419 #define FL_FOR_ARCH7VE          (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
 420 #define FL_FOR_ARCH7R           (FL_FOR_ARCH7A | FL_THUMB_DIV)
 421 #define FL_FOR_ARCH7M           (FL_FOR_ARCH7 | FL_THUMB_DIV)
 422 #define FL_FOR_ARCH7EM          (FL_FOR_ARCH7M | FL_ARCH7EM)
 423 #define FL_FOR_ARCH8A           (FL_FOR_ARCH7VE | FL_ARCH8)
 424 #define FL2_FOR_ARCH8_1A        FL2_ARCH8_1
 425 #define FL_FOR_ARCH8M_BASE      (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
 426 #define FL_FOR_ARCH8M_MAIN      (FL_FOR_ARCH7M | FL_ARCH8)
 427
 428 /* There are too many feature bits to fit in a single word so the set of cpu and
 429    fpu capabilities is a structure.  A feature set is created and manipulated
 430    with the ARM_FSET macros.  */
 431
 432 typedef struct
 433 {
 434   unsigned long cpu[2];
 435 } arm_feature_set;
 436
 437
 438 /* Initialize a feature set.  */
 439
 440 #define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
 441
 442 #define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
 443 #define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
 444
 445 /* Accessors.  */
 446
 447 #define ARM_FSET_CPU1(S) ((S).cpu[0])
 448 #define ARM_FSET_CPU2(S) ((S).cpu[1])
 449
 450 /* Useful combinations.  */
 451
 452 #define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
 453 #define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
 454
 455 /* Tests for a specific CPU feature.  */
 456
 457 #define ARM_FSET_HAS_CPU1(A, F)  \
 458   (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
 459 #define ARM_FSET_HAS_CPU2(A, F)  \
 460   (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
 461 #define ARM_FSET_HAS_CPU(A, F1, F2)                             \
 462   (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
 463
 464 /* Add a feature to a feature set.  */
 465
 466 #define ARM_FSET_ADD_CPU1(DST, F)               \
 467   do {                                          \
 468     (DST).cpu[0] |= (F);                        \
 469   } while (0)
 470
 471 #define ARM_FSET_ADD_CPU2(DST, F)               \
 472   do {                                          \
 473     (DST).cpu[1] |= (F);                        \
 474   } while (0)
 475
 476 /* Remove a feature from a feature set.  */
 477
 478 #define ARM_FSET_DEL_CPU1(DST, F)               \
 479   do {                                          \
 480     (DST).cpu[0] &= ~(F);                       \
 481   } while (0)
 482
 483 #define ARM_FSET_DEL_CPU2(DST, F)               \
 484   do {                                          \
 485     (DST).cpu[1] &= ~(F);                       \
 486   } while (0)
 487
 488 /* Union of feature sets.  */
 489
 490 #define ARM_FSET_UNION(DST,F1,F2)               \
 491   do {                                          \
 492     (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];   \
 493     (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];   \
 494   } while (0)
 495
 496 /* Intersection of feature sets.  */
 497
 498 #define ARM_FSET_INTER(DST,F1,F2)               \
 499   do {                                          \
 500     (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];   \
 501     (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];   \
 502   } while (0)
 503
 504 /* Exclusive disjunction.  */
 505
 506 #define ARM_FSET_XOR(DST,F1,F2)                         \
 507   do {                                                  \
 508     (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];           \
 509     (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];           \
 510   } while (0)
 511
 512 /* Difference of feature sets: F1 excluding the elements of F2.  */
 513
 514 #define ARM_FSET_EXCLUDE(DST,F1,F2)             \
 515   do {                                          \
 516     (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];  \
 517     (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];  \
 518   } while (0)
 519
 520 /* Test for an empty feature set.  */
 521
 522 #define ARM_FSET_IS_EMPTY(A)            \
 523   (!((A).cpu[0]) && !((A).cpu[1]))
 524
 525 /* Tests whether the cpu features of A are a subset of B.  */
 526
 527 #define ARM_FSET_CPU_SUBSET(A,B)                                        \
 528   ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])                            \
 529    && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
 530
 531 /* The bits in this mask specify which
 532    instructions we are allowed to generate.  */
 533 extern arm_feature_set insn_flags;
 534
 535 /* The bits in this mask specify which instruction scheduling options should
 536    be used.  */
 537 extern arm_feature_set tune_flags;
 538
 539 /* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
 540 extern int arm_arch3m;
 541
 542 /* Nonzero if this chip supports the ARM Architecture 4 extensions.  */
 543 extern int arm_arch4;
 544
 545 /* Nonzero if this chip supports the ARM Architecture 4t extensions.  */
 546 extern int arm_arch4t;
 547
 548 /* Nonzero if this chip supports the ARM Architecture 5 extensions.  */
 549 extern int arm_arch5;
 550
 551 /* Nonzero if this chip supports the ARM Architecture 5E extensions.  */
 552 extern int arm_arch5e;
 553
 554 /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
 555 extern int arm_arch6;
 556
 557 /* Nonzero if this chip supports the ARM 6K extensions.  */
 558 extern int arm_arch6k;
 559
 560 /* Nonzero if this chip supports the ARM 6KZ extensions.  */
 561 extern int arm_arch6kz;
 562
 563 /* Nonzero if instructions present in ARMv6-M can be used.  */
 564 extern int arm_arch6m;
 565
 566 /* Nonzero if this chip supports the ARM 7 extensions.  */
 567 extern int arm_arch7;
 568
 569 /* Nonzero if instructions not present in the 'M' profile can be used.  */
 570 extern int arm_arch_notm;
 571
 572 /* Nonzero if instructions present in ARMv7E-M can be used.  */
 573 extern int arm_arch7em;
 574
 575 /* Nonzero if instructions present in ARMv8 can be used.  */
 576 extern int arm_arch8;
 577
 578 /* Nonzero if this chip can benefit from load scheduling.  */
 579 extern int arm_ld_sched;
 580
 581 /* Nonzero if this chip is a StrongARM.  */
 582 extern int arm_tune_strongarm;
 583
 584 /* Nonzero if this chip supports Intel Wireless MMX technology.  */
 585 extern int arm_arch_iwmmxt;
 586
 587 /* Nonzero if this chip supports Intel Wireless MMX2 technology.  */
 588 extern int arm_arch_iwmmxt2;
 589
 590 /* Nonzero if this chip is an XScale.  */
 591 extern int arm_arch_xscale;
 592
 593 /* Nonzero if tuning for XScale  */
 594 extern int arm_tune_xscale;
 595
 596 /* Nonzero if we want to tune for stores that access the write-buffer.
 597    This typically means an ARM6 or ARM7 with MMU or MPU.  */
 598 extern int arm_tune_wbuf;
 599
 600 /* Nonzero if tuning for Cortex-A9.  */
 601 extern int arm_tune_cortex_a9;
 602
 603 /* Nonzero if we should define __THUMB_INTERWORK__ in the
 604    preprocessor.
 605    XXX This is a bit of a hack, it's intended to help work around
 606    problems in GLD which doesn't understand that armv5t code is
 607    interworking clean.  */
 608 extern int arm_cpp_interwork;
 609
 610 /* Nonzero if chip supports Thumb 1.  */
 611 extern int arm_arch_thumb1;
 612
 613 /* Nonzero if chip supports Thumb 2.  */
 614 extern int arm_arch_thumb2;
 615
 616 /* Nonzero if chip supports integer division instruction.  */
 617 extern int arm_arch_arm_hwdiv;
 618 extern int arm_arch_thumb_hwdiv;
 619
 620 /* Nonzero if chip disallows volatile memory access in IT block.  */
 621 extern int arm_arch_no_volatile_ce;
 622
 623 /* Nonzero if we should use Neon to handle 64-bits operations rather
 624    than core registers.  */
 625 extern int prefer_neon_for_64bits;
 626
 627
 628
 629 #endif /* ! GCC_ARM_PROTOS_H */