gcc/config/nds32/nds32-intrinsic.md

   1 ;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler
   2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3 ;; Contributed by Andes Technology Corporation.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; ------------------------------------------------------------------------
  22
  23 ;; Register Transfer.
  24
  25 (define_insn "unspec_volatile_mfsr"
  26   [(set (match_operand:SI 0 "register_operand" "=r")
  27         (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFSR))]
  28   ""
  29   "mfsr\t%0, %V1"
  30   [(set_attr "type"   "misc")
  31    (set_attr "length"    "4")]
  32 )
  33
  34 (define_insn "unspec_volatile_mfusr"
  35   [(set (match_operand:SI 0 "register_operand" "=r")
  36         (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFUSR))]
  37   ""
  38   "mfusr\t%0, %V1"
  39   [(set_attr "type"   "misc")
  40    (set_attr "length"    "4")]
  41 )
  42
  43 (define_insn "unspec_volatile_mtsr"
  44   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
  45                         (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTSR)]
  46   ""
  47   "mtsr\t%0, %V1"
  48   [(set_attr "type"   "misc")
  49    (set_attr "length"    "4")]
  50 )
  51
  52 (define_insn "unspec_volatile_mtusr"
  53   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
  54                         (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTUSR)]
  55   ""
  56   "mtusr\t%0, %V1"
  57   [(set_attr "type"   "misc")
  58    (set_attr "length"    "4")]
  59 )
  60
  61 ;; ------------------------------------------------------------------------
  62
  63 ;; Interrupt Instructions.
  64
  65 (define_insn "unspec_volatile_setgie_en"
  66   [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_EN)]
  67   ""
  68   "setgie.e"
  69   [(set_attr "type" "misc")]
  70 )
  71
  72 (define_insn "unspec_volatile_setgie_dis"
  73   [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_DIS)]
  74   ""
  75   "setgie.d"
  76   [(set_attr "type" "misc")]
  77 )
  78
  79 ;; ------------------------------------------------------------------------
  80
  81 ;; Cache Synchronization Instructions
  82
  83 (define_insn "unspec_volatile_isync"
  84   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_ISYNC)]
  85   ""
  86   "isync\t%0"
  87   [(set_attr "type" "misc")]
  88 )
  89
  90 (define_insn "unspec_volatile_isb"
  91   [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_ISB)]
  92   ""
  93   "isb"
  94   [(set_attr "type" "misc")]
  95 )
  96
  97 ;; String Extension
  98
  99 (define_insn "unspec_ffb"
 100   [(set (match_operand:SI 0 "register_operand" "=r, r")
 101         (unspec:SI [(match_operand:SI 1 "register_operand" "r, r")
 102                     (match_operand:SI 2 "nonmemory_operand" "Iu08, r")] UNSPEC_FFB))]
 103   ""
 104   "@
 105   ffbi\t%0, %1, %2
 106   ffb\t%0, %1, %2"
 107   [(set_attr "type" "alu")
 108    (set_attr "length" "4")]
 109 )
 110
 111 (define_insn "unspec_ffmism"
 112   [(set (match_operand:SI 0 "register_operand" "=r")
 113         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
 114                     (match_operand:SI 2 "register_operand" "r")] UNSPEC_FFMISM))]
 115   ""
 116   "ffmism\t%0, %1, %2"
 117   [(set_attr "type" "alu")
 118    (set_attr "length" "4")]
 119 )
 120
 121 (define_insn "unspec_flmism"
 122   [(set (match_operand:SI 0 "register_operand" "=r")
 123         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
 124                     (match_operand:SI 2 "register_operand" "r")] UNSPEC_FLMISM))]
 125   ""
 126   "flmism\t%0, %1, %2"
 127   [(set_attr "type" "alu")
 128    (set_attr "length" "4")]
 129 )
 130
 131 ;;Unaligned Load/Store
 132
 133 (define_expand "unaligned_load_hw"
 134   [(set (match_operand:HI 0 "register_operand" "")
 135         (unspec:HI [(mem:HI (match_operand:SI 1 "register_operand" ""))] UNSPEC_UALOAD_HW))]
 136   ""
 137 {
 138   operands[0] = simplify_gen_subreg (SImode, operands[0],
 139                                      GET_MODE (operands[0]), 0);
 140   if (TARGET_ISA_V3M)
 141     {
 142       nds32_expand_unaligned_load (operands, HImode);
 143     }
 144   else
 145     {
 146       emit_insn (gen_unaligned_load_w (operands[0],
 147                                        gen_rtx_MEM (SImode, operands[1])));
 148
 149       if (WORDS_BIG_ENDIAN)
 150         emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT(16)));
 151       else
 152         emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (0xffff)));
 153     }
 154
 155   DONE;
 156 })
 157
 158 (define_expand "unaligned_loadsi"
 159   [(set (match_operand:SI 0 "register_operand" "=r")
 160         (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))]
 161   ""
 162 {
 163   if (TARGET_ISA_V3M)
 164     nds32_expand_unaligned_load (operands, SImode);
 165   else
 166     emit_insn (gen_unaligned_load_w (operands[0],
 167                                      gen_rtx_MEM (SImode, (operands[1]))));
 168   DONE;
 169 })
 170
 171 (define_insn "unaligned_load_w"
 172   [(set (match_operand:SI 0 "register_operand"                       "=  r")
 173         (unspec:SI [(match_operand:SI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))]
 174   ""
 175 {
 176   return nds32_output_lmw_single_word (operands);
 177 }
 178   [(set_attr "type"   "load")
 179    (set_attr "length"    "4")]
 180 )
 181
 182 (define_expand "unaligned_loaddi"
 183   [(set (match_operand:DI 0 "register_operand" "=r")
 184         (unspec:DI [(mem:DI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_DW))]
 185   ""
 186 {
 187   if (TARGET_ISA_V3M)
 188     {
 189       nds32_expand_unaligned_load (operands, DImode);
 190     }
 191   else
 192     emit_insn (gen_unaligned_load_dw (operands[0], operands[1]));
 193   DONE;
 194 })
 195
 196 (define_insn "unaligned_load_dw"
 197   [(set (match_operand:DI 0 "register_operand" "=r")
 198         (unspec:DI [(mem:DI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_DW))]
 199   ""
 200 {
 201   rtx otherops[3];
 202   otherops[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
 203   otherops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
 204   otherops[2] = operands[1];
 205
 206   output_asm_insn ("lmw.bi\t%0, [%2], %1, 0", otherops);
 207   return "";
 208 }
 209   [(set_attr "type"   "load")
 210    (set_attr "length"    "4")]
 211 )
 212
 213 (define_expand "unaligned_store_hw"
 214   [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
 215         (unspec:HI [(match_operand:HI 1 "register_operand" "")] UNSPEC_UASTORE_HW))]
 216   ""
 217 {
 218   operands[1] = simplify_gen_subreg (SImode, operands[1],
 219                                      GET_MODE (operands[1]), 0);
 220   nds32_expand_unaligned_store (operands, HImode);
 221   DONE;
 222 })
 223
 224 (define_expand "unaligned_storesi"
 225   [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
 226         (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_UASTORE_W))]
 227   ""
 228 {
 229   if (TARGET_ISA_V3M)
 230     nds32_expand_unaligned_store (operands, SImode);
 231   else
 232     emit_insn (gen_unaligned_store_w (gen_rtx_MEM (SImode, operands[0]),
 233                                       operands[1]));
 234   DONE;
 235 })
 236
 237 (define_insn "unaligned_store_w"
 238   [(set (match_operand:SI 0 "nds32_lmw_smw_base_operand"   "=Umw")
 239         (unspec:SI [(match_operand:SI 1 "register_operand" "   r")] UNSPEC_UASTORE_W))]
 240   ""
 241 {
 242   return nds32_output_smw_single_word (operands);
 243 }
 244   [(set_attr "type"   "store")
 245    (set_attr "length"     "4")]
 246 )
 247
 248 (define_expand "unaligned_storedi"
 249   [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
 250         (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
 251   ""
 252 {
 253   if (TARGET_ISA_V3M)
 254     nds32_expand_unaligned_store (operands, DImode);
 255   else
 256     emit_insn (gen_unaligned_store_dw (operands[0], operands[1]));
 257   DONE;
 258 })
 259
 260 (define_insn "unaligned_store_dw"
 261   [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
 262         (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
 263   ""
 264 {
 265   rtx otherops[3];
 266   otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
 267   otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
 268   otherops[2] = operands[0];
 269
 270   output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
 271   return "";
 272 }
 273   [(set_attr "type"   "store")
 274    (set_attr "length"     "4")]
 275 )
 276
 277 ;; ------------------------------------------------------------------------