| blob | dfebf5ab87c16f1ce23c8635132a5f604b0a6a4b |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 UNSPEC_FUSION_GPR
141 ])
143 ;;
144 ;; UNSPEC_VOLATILE usage
145 ;;
147 (define_c_enum "unspecv"
148 [UNSPECV_BLOCK
149 UNSPECV_LL ; load-locked
150 UNSPECV_SC ; store-conditional
151 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
152 UNSPECV_EH_RR ; eh_reg_restore
153 UNSPECV_ISYNC ; isync instruction
154 UNSPECV_MFTB ; move from time base
155 UNSPECV_NLGR ; non-local goto receiver
156 UNSPECV_MFFS ; Move from FPSCR
157 UNSPECV_MTFSF ; Move to FPSCR Fields
158 ])
160 \f
161 ;; Define an insn type attribute. This is used in function unit delay
162 ;; computations.
163 (define_attr "type"
164 "integer,two,three,
165 add,logical,shift,insert,
166 mul,halfmul,div,
167 exts,cntlz,popcnt,isel,
168 load,store,fpload,fpstore,vecload,vecstore,
169 cmp,
170 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
171 compare,
172 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
173 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
174 brinc,
175 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
176 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
177 htm"
178 (const_string "integer"))
180 ;; What data size does this instruction work on?
181 ;; This is used for insert, mul.
182 (define_attr "size" "8,16,32,64" (const_string "32"))
184 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
185 ;; This is used for add, logical, shift, exts, mul.
186 (define_attr "dot" "no,yes" (const_string "no"))
188 ;; Does this instruction sign-extend its result?
189 ;; This is used for load insns.
190 (define_attr "sign_extend" "no,yes" (const_string "no"))
192 ;; Does this instruction use indexed (that is, reg+reg) addressing?
193 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
194 ;; it is automatically set based on that. If a load or store instruction
195 ;; has fewer than two operands it needs to set this attribute manually
196 ;; or the compiler will crash.
197 (define_attr "indexed" "no,yes"
198 (if_then_else (ior (match_operand 0 "indexed_address_mem")
199 (match_operand 1 "indexed_address_mem"))
200 (const_string "yes")
201 (const_string "no")))
203 ;; Does this instruction use update addressing?
204 ;; This is used for load and store insns. See the comments for "indexed".
205 (define_attr "update" "no,yes"
206 (if_then_else (ior (match_operand 0 "update_address_mem")
207 (match_operand 1 "update_address_mem"))
208 (const_string "yes")
209 (const_string "no")))
211 ;; Is this instruction using operands[2] as shift amount, and can that be a
212 ;; register?
213 ;; This is used for shift insns.
214 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
216 ;; Is this instruction using a shift amount from a register?
217 ;; This is used for shift insns.
218 (define_attr "var_shift" "no,yes"
219 (if_then_else (and (eq_attr "type" "shift")
220 (eq_attr "maybe_var_shift" "yes"))
221 (if_then_else (match_operand 2 "gpc_reg_operand")
222 (const_string "yes")
223 (const_string "no"))
224 (const_string "no")))
226 ;; Define floating point instruction sub-types for use with Xfpu.md
227 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
229 ;; Length (in bytes).
230 ; '(pc)' in the following doesn't include the instruction itself; it is
231 ; calculated as if the instruction had zero size.
232 (define_attr "length" ""
233 (if_then_else (eq_attr "type" "branch")
234 (if_then_else (and (ge (minus (match_dup 0) (pc))
235 (const_int -32768))
236 (lt (minus (match_dup 0) (pc))
237 (const_int 32764)))
238 (const_int 4)
239 (const_int 8))
240 (const_int 4)))
242 ;; Processor type -- this attribute must exactly match the processor_type
243 ;; enumeration in rs6000-opts.h.
244 (define_attr "cpu"
245 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
246 ppc750,ppc7400,ppc7450,
247 ppc403,ppc405,ppc440,ppc476,
248 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
249 power4,power5,power6,power7,power8,
250 rs64a,mpccore,cell,ppca2,titan"
251 (const (symbol_ref "rs6000_cpu_attr")))
254 ;; If this instruction is microcoded on the CELL processor
255 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
256 (define_attr "cell_micro" "not,conditional,always"
257 (if_then_else (ior (eq_attr "type" "compare")
258 (and (eq_attr "type" "shift,exts,mul")
259 (eq_attr "dot" "yes"))
260 (and (eq_attr "type" "load")
261 (eq_attr "sign_extend" "yes"))
262 (and (eq_attr "type" "shift")
263 (eq_attr "var_shift" "yes")))
264 (const_string "always")
265 (const_string "not")))
267 (automata_option "ndfa")
269 (include "rs64.md")
270 (include "mpc.md")
271 (include "40x.md")
272 (include "440.md")
273 (include "476.md")
274 (include "601.md")
275 (include "603.md")
276 (include "6xx.md")
277 (include "7xx.md")
278 (include "7450.md")
279 (include "8540.md")
280 (include "e300c2c3.md")
281 (include "e500mc.md")
282 (include "e500mc64.md")
283 (include "e5500.md")
284 (include "e6500.md")
285 (include "power4.md")
286 (include "power5.md")
287 (include "power6.md")
288 (include "power7.md")
289 (include "power8.md")
290 (include "cell.md")
291 (include "xfpu.md")
292 (include "a2.md")
293 (include "titan.md")
295 (include "predicates.md")
296 (include "constraints.md")
298 (include "darwin.md")
300 \f
301 ;; Mode iterators
303 ; This mode iterator allows :GPR to be used to indicate the allowable size
304 ; of whole values in GPRs.
305 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
307 ; Any supported integer mode.
308 (define_mode_iterator INT [QI HI SI DI TI PTI])
310 ; Any supported integer mode that fits in one register.
311 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
313 ; Everything we can extend QImode to.
314 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
316 ; Everything we can extend HImode to.
317 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
319 ; Everything we can extend SImode to.
320 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
322 ; QImode or HImode for small atomic ops
323 (define_mode_iterator QHI [QI HI])
325 ; HImode or SImode for sign extended fusion ops
326 (define_mode_iterator HSI [HI SI])
328 ; SImode or DImode, even if DImode doesn't fit in GPRs.
329 (define_mode_iterator SDI [SI DI])
331 ; The size of a pointer. Also, the size of the value that a record-condition
332 ; (one with a '.') will compare; and the size used for arithmetic carries.
333 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
335 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
336 ; PTImode is GPR only)
337 (define_mode_iterator TI2 [TI PTI])
339 ; Any hardware-supported floating-point mode
340 (define_mode_iterator FP [
341 (SF "TARGET_HARD_FLOAT
342 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
343 (DF "TARGET_HARD_FLOAT
344 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
345 (TF "!TARGET_IEEEQUAD
346 && TARGET_HARD_FLOAT
347 && (TARGET_FPRS || TARGET_E500_DOUBLE)
348 && TARGET_LONG_DOUBLE_128")
349 (DD "TARGET_DFP")
350 (TD "TARGET_DFP")])
352 ; Any fma capable floating-point mode.
353 (define_mode_iterator FMA_F [
354 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
355 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
356 || VECTOR_UNIT_VSX_P (DFmode)")
357 (V2SF "TARGET_PAIRED_FLOAT")
358 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
359 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
360 ])
362 ; Floating point move iterators to combine binary and decimal moves
363 (define_mode_iterator FMOVE32 [SF SD])
364 (define_mode_iterator FMOVE64 [DF DD])
365 (define_mode_iterator FMOVE64X [DI DF DD])
366 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
367 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
369 ; Iterators for 128 bit types for direct move
370 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
371 (V16QI "")
372 (V8HI "")
373 (V4SI "")
374 (V4SF "")
375 (V2DI "")
376 (V2DF "")
377 (V1TI "")])
379 ; Whether a floating point move is ok, don't allow SD without hardware FP
380 (define_mode_attr fmove_ok [(SF "")
381 (DF "")
382 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
383 (DD "")])
385 ; Convert REAL_VALUE to the appropriate bits
386 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
387 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
388 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
389 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
391 ; Definitions for load to 32-bit fpr register
392 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
393 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
394 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
395 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
397 ; Definitions for store from 32-bit fpr register
398 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
399 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
400 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
401 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
403 ; Definitions for 32-bit fpr direct move
404 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
406 ; These modes do not fit in integer registers in 32-bit mode.
407 ; but on e500v2, the gpr are 64 bit registers
408 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
410 ; Iterator for reciprocal estimate instructions
411 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
413 ; Iterator for just SF/DF
414 (define_mode_iterator SFDF [SF DF])
416 ; SF/DF suffix for traditional floating instructions
417 (define_mode_attr Ftrad [(SF "s") (DF "")])
419 ; SF/DF suffix for VSX instructions
420 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
422 ; SF/DF constraint for arithmetic on traditional floating point registers
423 (define_mode_attr Ff [(SF "f") (DF "d")])
425 ; SF/DF constraint for arithmetic on VSX registers
426 (define_mode_attr Fv [(SF "wy") (DF "ws")])
428 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
429 (define_mode_attr Fs [(SF "s") (DF "d")])
431 ; FRE/FRES support
432 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
433 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
435 ; Conditional returns.
436 (define_code_iterator any_return [return simple_return])
437 (define_code_attr return_pred [(return "direct_return ()")
438 (simple_return "1")])
439 (define_code_attr return_str [(return "") (simple_return "simple_")])
441 ; Logical operators.
442 (define_code_iterator iorxor [ior xor])
443 (define_code_attr iorxor [(ior "ior") (xor "xor")])
444 (define_code_attr IORXOR [(ior "IOR") (xor "XOR")])
446 ; Signed/unsigned variants of ops.
447 (define_code_iterator any_extend [sign_extend zero_extend])
448 (define_code_attr u [(sign_extend "") (zero_extend "u")])
449 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
451 ; Various instructions that come in SI and DI forms.
452 ; A generic w/d attribute, for things like cmpw/cmpd.
453 (define_mode_attr wd [(QI "b")
454 (HI "h")
455 (SI "w")
456 (DI "d")
457 (V16QI "b")
458 (V8HI "h")
459 (V4SI "w")
460 (V2DI "d")])
462 ;; How many bits in this mode?
463 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
465 ; DImode bits
466 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
468 ;; ISEL/ISEL64 target selection
469 (define_mode_attr sel [(SI "") (DI "64")])
471 ;; Bitmask for shift instructions
472 (define_mode_attr hH [(SI "h") (DI "H")])
474 ;; A mode twice the size of the given mode
475 (define_mode_attr dmode [(SI "di") (DI "ti")])
476 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
478 ;; Suffix for reload patterns
479 (define_mode_attr ptrsize [(SI "32bit")
480 (DI "64bit")])
482 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
483 (DI "TARGET_64BIT")])
485 (define_mode_attr mptrsize [(SI "si")
486 (DI "di")])
488 (define_mode_attr ptrload [(SI "lwz")
489 (DI "ld")])
491 (define_mode_attr ptrm [(SI "m")
492 (DI "Y")])
494 (define_mode_attr rreg [(SF "f")
495 (DF "ws")
496 (TF "f")
497 (TD "f")
498 (V4SF "wf")
499 (V2DF "wd")])
501 (define_mode_attr rreg2 [(SF "f")
502 (DF "d")])
504 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
505 (DF "TARGET_FCFID")])
507 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
508 (DF "TARGET_E500_DOUBLE")])
510 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
511 (DF "TARGET_DOUBLE_FLOAT")])
513 ;; Mode iterator for logical operations on 128-bit types
514 (define_mode_iterator BOOL_128 [TI
515 PTI
516 (V16QI "TARGET_ALTIVEC")
517 (V8HI "TARGET_ALTIVEC")
518 (V4SI "TARGET_ALTIVEC")
519 (V4SF "TARGET_ALTIVEC")
520 (V2DI "TARGET_ALTIVEC")
521 (V2DF "TARGET_ALTIVEC")
522 (V1TI "TARGET_ALTIVEC")])
524 ;; For the GPRs we use 3 constraints for register outputs, two that are the
525 ;; same as the output register, and a third where the output register is an
526 ;; early clobber, so we don't have to deal with register overlaps. For the
527 ;; vector types, we prefer to use the vector registers. For TI mode, allow
528 ;; either.
530 ;; Mode attribute for boolean operation register constraints for output
531 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
532 (PTI "&r,r,r")
533 (V16QI "wa,v,&?r,?r,?r")
534 (V8HI "wa,v,&?r,?r,?r")
535 (V4SI "wa,v,&?r,?r,?r")
536 (V4SF "wa,v,&?r,?r,?r")
537 (V2DI "wa,v,&?r,?r,?r")
538 (V2DF "wa,v,&?r,?r,?r")
539 (V1TI "wa,v,&?r,?r,?r")])
541 ;; Mode attribute for boolean operation register constraints for operand1
542 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
543 (PTI "r,0,r")
544 (V16QI "wa,v,r,0,r")
545 (V8HI "wa,v,r,0,r")
546 (V4SI "wa,v,r,0,r")
547 (V4SF "wa,v,r,0,r")
548 (V2DI "wa,v,r,0,r")
549 (V2DF "wa,v,r,0,r")
550 (V1TI "wa,v,r,0,r")])
552 ;; Mode attribute for boolean operation register constraints for operand2
553 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
554 (PTI "r,r,0")
555 (V16QI "wa,v,r,r,0")
556 (V8HI "wa,v,r,r,0")
557 (V4SI "wa,v,r,r,0")
558 (V4SF "wa,v,r,r,0")
559 (V2DI "wa,v,r,r,0")
560 (V2DF "wa,v,r,r,0")
561 (V1TI "wa,v,r,r,0")])
563 ;; Mode attribute for boolean operation register constraints for operand1
564 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
565 ;; is used for operand1 or operand2
566 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
567 (PTI "r,0,0")
568 (V16QI "wa,v,r,0,0")
569 (V8HI "wa,v,r,0,0")
570 (V4SI "wa,v,r,0,0")
571 (V4SF "wa,v,r,0,0")
572 (V2DI "wa,v,r,0,0")
573 (V2DF "wa,v,r,0,0")
574 (V1TI "wa,v,r,0,0")])
575 \f
576 ;; Start with fixed-point load and store insns. Here we put only the more
577 ;; complex forms. Basic data transfer is done later.
579 (define_insn "zero_extendqi<mode>2"
580 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
581 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
582 ""
583 "@
584 lbz%U1%X1 %0,%1
585 rlwinm %0,%1,0,0xff"
586 [(set_attr "type" "load,shift")])
588 (define_insn_and_split "*zero_extendqi<mode>2_dot"
589 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
590 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
591 (const_int 0)))
592 (clobber (match_scratch:EXTQI 0 "=r,r"))]
593 "rs6000_gen_cell_microcode"
594 "@
595 andi. %0,%1,0xff
596 #"
597 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
598 [(set (match_dup 0)
599 (zero_extend:EXTQI (match_dup 1)))
600 (set (match_dup 2)
601 (compare:CC (match_dup 0)
602 (const_int 0)))]
603 ""
604 [(set_attr "type" "logical")
605 (set_attr "dot" "yes")
606 (set_attr "length" "4,8")])
608 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
609 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
610 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
611 (const_int 0)))
612 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
613 (zero_extend:EXTQI (match_dup 1)))]
614 "rs6000_gen_cell_microcode"
615 "@
616 andi. %0,%1,0xff
617 #"
618 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
619 [(set (match_dup 0)
620 (zero_extend:EXTQI (match_dup 1)))
621 (set (match_dup 2)
622 (compare:CC (match_dup 0)
623 (const_int 0)))]
624 ""
625 [(set_attr "type" "logical")
626 (set_attr "dot" "yes")
627 (set_attr "length" "4,8")])
630 (define_insn "zero_extendhi<mode>2"
631 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
632 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
633 ""
634 "@
635 lhz%U1%X1 %0,%1
636 rlwinm %0,%1,0,0xffff"
637 [(set_attr "type" "load,shift")])
639 (define_insn_and_split "*zero_extendhi<mode>2_dot"
640 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
641 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
642 (const_int 0)))
643 (clobber (match_scratch:EXTHI 0 "=r,r"))]
644 "rs6000_gen_cell_microcode"
645 "@
646 andi. %0,%1,0xffff
647 #"
648 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
649 [(set (match_dup 0)
650 (zero_extend:EXTHI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 ""
655 [(set_attr "type" "logical")
656 (set_attr "dot" "yes")
657 (set_attr "length" "4,8")])
659 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
660 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
661 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
662 (const_int 0)))
663 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
664 (zero_extend:EXTHI (match_dup 1)))]
665 "rs6000_gen_cell_microcode"
666 "@
667 andi. %0,%1,0xffff
668 #"
669 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
670 [(set (match_dup 0)
671 (zero_extend:EXTHI (match_dup 1)))
672 (set (match_dup 2)
673 (compare:CC (match_dup 0)
674 (const_int 0)))]
675 ""
676 [(set_attr "type" "logical")
677 (set_attr "dot" "yes")
678 (set_attr "length" "4,8")])
681 (define_insn "zero_extendsi<mode>2"
682 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
683 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
684 ""
685 "@
686 lwz%U1%X1 %0,%1
687 rldicl %0,%1,0,32
688 mtvsrwz %x0,%1
689 lfiwzx %0,%y1
690 lxsiwzx %x0,%y1"
691 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
693 (define_insn_and_split "*zero_extendsi<mode>2_dot"
694 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
695 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
696 (const_int 0)))
697 (clobber (match_scratch:EXTSI 0 "=r,r"))]
698 "rs6000_gen_cell_microcode"
699 "@
700 rldicl. %0,%1,0,32
701 #"
702 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
703 [(set (match_dup 0)
704 (zero_extend:DI (match_dup 1)))
705 (set (match_dup 2)
706 (compare:CC (match_dup 0)
707 (const_int 0)))]
708 ""
709 [(set_attr "type" "shift")
710 (set_attr "dot" "yes")
711 (set_attr "length" "4,8")])
713 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
714 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
715 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
716 (const_int 0)))
717 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
718 (zero_extend:EXTSI (match_dup 1)))]
719 "rs6000_gen_cell_microcode"
720 "@
721 rldicl. %0,%1,0,32
722 #"
723 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
724 [(set (match_dup 0)
725 (zero_extend:EXTSI (match_dup 1)))
726 (set (match_dup 2)
727 (compare:CC (match_dup 0)
728 (const_int 0)))]
729 ""
730 [(set_attr "type" "shift")
731 (set_attr "dot" "yes")
732 (set_attr "length" "4,8")])
735 (define_insn "extendqi<mode>2"
736 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
737 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
738 ""
739 "extsb %0,%1"
740 [(set_attr "type" "exts")])
742 (define_insn_and_split "*extendqi<mode>2_dot"
743 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
744 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
745 (const_int 0)))
746 (clobber (match_scratch:EXTQI 0 "=r,r"))]
747 "rs6000_gen_cell_microcode"
748 "@
749 extsb. %0,%1
750 #"
751 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
752 [(set (match_dup 0)
753 (sign_extend:EXTQI (match_dup 1)))
754 (set (match_dup 2)
755 (compare:CC (match_dup 0)
756 (const_int 0)))]
757 ""
758 [(set_attr "type" "exts")
759 (set_attr "dot" "yes")
760 (set_attr "length" "4,8")])
762 (define_insn_and_split "*extendqi<mode>2_dot2"
763 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
764 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
765 (const_int 0)))
766 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
767 (sign_extend:EXTQI (match_dup 1)))]
768 "rs6000_gen_cell_microcode"
769 "@
770 extsb. %0,%1
771 #"
772 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
773 [(set (match_dup 0)
774 (sign_extend:EXTQI (match_dup 1)))
775 (set (match_dup 2)
776 (compare:CC (match_dup 0)
777 (const_int 0)))]
778 ""
779 [(set_attr "type" "exts")
780 (set_attr "dot" "yes")
781 (set_attr "length" "4,8")])
784 (define_expand "extendhi<mode>2"
785 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
786 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
787 ""
788 "")
790 (define_insn "*extendhi<mode>2"
791 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
792 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
793 "rs6000_gen_cell_microcode"
794 "@
795 lha%U1%X1 %0,%1
796 extsh %0,%1"
797 [(set_attr "type" "load,exts")
798 (set_attr "sign_extend" "yes")])
800 (define_insn "*extendhi<mode>2_noload"
801 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
802 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
803 "!rs6000_gen_cell_microcode"
804 "extsh %0,%1"
805 [(set_attr "type" "exts")])
807 (define_insn_and_split "*extendhi<mode>2_dot"
808 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
809 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
810 (const_int 0)))
811 (clobber (match_scratch:EXTHI 0 "=r,r"))]
812 "rs6000_gen_cell_microcode"
813 "@
814 extsh. %0,%1
815 #"
816 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
817 [(set (match_dup 0)
818 (sign_extend:EXTHI (match_dup 1)))
819 (set (match_dup 2)
820 (compare:CC (match_dup 0)
821 (const_int 0)))]
822 ""
823 [(set_attr "type" "exts")
824 (set_attr "dot" "yes")
825 (set_attr "length" "4,8")])
827 (define_insn_and_split "*extendhi<mode>2_dot2"
828 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
829 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
830 (const_int 0)))
831 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
832 (sign_extend:EXTHI (match_dup 1)))]
833 "rs6000_gen_cell_microcode"
834 "@
835 extsh. %0,%1
836 #"
837 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
838 [(set (match_dup 0)
839 (sign_extend:EXTHI (match_dup 1)))
840 (set (match_dup 2)
841 (compare:CC (match_dup 0)
842 (const_int 0)))]
843 ""
844 [(set_attr "type" "exts")
845 (set_attr "dot" "yes")
846 (set_attr "length" "4,8")])
849 (define_insn "extendsi<mode>2"
850 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
851 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
852 ""
853 "@
854 lwa%U1%X1 %0,%1
855 extsw %0,%1
856 mtvsrwa %x0,%1
857 lfiwax %0,%y1
858 lxsiwax %x0,%y1"
859 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
860 (set_attr "sign_extend" "yes")])
862 (define_insn_and_split "*extendsi<mode>2_dot"
863 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
864 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
865 (const_int 0)))
866 (clobber (match_scratch:EXTSI 0 "=r,r"))]
867 "rs6000_gen_cell_microcode"
868 "@
869 extsw. %0,%1
870 #"
871 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
872 [(set (match_dup 0)
873 (sign_extend:EXTSI (match_dup 1)))
874 (set (match_dup 2)
875 (compare:CC (match_dup 0)
876 (const_int 0)))]
877 ""
878 [(set_attr "type" "exts")
879 (set_attr "dot" "yes")
880 (set_attr "length" "4,8")])
882 (define_insn_and_split "*extendsi<mode>2_dot2"
883 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
884 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
885 (const_int 0)))
886 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
887 (sign_extend:EXTSI (match_dup 1)))]
888 "rs6000_gen_cell_microcode"
889 "@
890 extsw. %0,%1
891 #"
892 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
893 [(set (match_dup 0)
894 (sign_extend:EXTSI (match_dup 1)))
895 (set (match_dup 2)
896 (compare:CC (match_dup 0)
897 (const_int 0)))]
898 ""
899 [(set_attr "type" "exts")
900 (set_attr "dot" "yes")
901 (set_attr "length" "4,8")])
902 \f
903 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
905 (define_insn "*macchwc"
906 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
907 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
908 (match_operand:SI 2 "gpc_reg_operand" "r")
909 (const_int 16))
910 (sign_extend:SI
911 (match_operand:HI 1 "gpc_reg_operand" "r")))
912 (match_operand:SI 4 "gpc_reg_operand" "0"))
913 (const_int 0)))
914 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
915 (plus:SI (mult:SI (ashiftrt:SI
916 (match_dup 2)
917 (const_int 16))
918 (sign_extend:SI
919 (match_dup 1)))
920 (match_dup 4)))]
921 "TARGET_MULHW"
922 "macchw. %0,%1,%2"
923 [(set_attr "type" "halfmul")])
925 (define_insn "*macchw"
926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
927 (plus:SI (mult:SI (ashiftrt:SI
928 (match_operand:SI 2 "gpc_reg_operand" "r")
929 (const_int 16))
930 (sign_extend:SI
931 (match_operand:HI 1 "gpc_reg_operand" "r")))
932 (match_operand:SI 3 "gpc_reg_operand" "0")))]
933 "TARGET_MULHW"
934 "macchw %0,%1,%2"
935 [(set_attr "type" "halfmul")])
937 (define_insn "*macchwuc"
938 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
939 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
940 (match_operand:SI 2 "gpc_reg_operand" "r")
941 (const_int 16))
942 (zero_extend:SI
943 (match_operand:HI 1 "gpc_reg_operand" "r")))
944 (match_operand:SI 4 "gpc_reg_operand" "0"))
945 (const_int 0)))
946 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
947 (plus:SI (mult:SI (lshiftrt:SI
948 (match_dup 2)
949 (const_int 16))
950 (zero_extend:SI
951 (match_dup 1)))
952 (match_dup 4)))]
953 "TARGET_MULHW"
954 "macchwu. %0,%1,%2"
955 [(set_attr "type" "halfmul")])
957 (define_insn "*macchwu"
958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
959 (plus:SI (mult:SI (lshiftrt:SI
960 (match_operand:SI 2 "gpc_reg_operand" "r")
961 (const_int 16))
962 (zero_extend:SI
963 (match_operand:HI 1 "gpc_reg_operand" "r")))
964 (match_operand:SI 3 "gpc_reg_operand" "0")))]
965 "TARGET_MULHW"
966 "macchwu %0,%1,%2"
967 [(set_attr "type" "halfmul")])
969 (define_insn "*machhwc"
970 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
971 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
972 (match_operand:SI 1 "gpc_reg_operand" "%r")
973 (const_int 16))
974 (ashiftrt:SI
975 (match_operand:SI 2 "gpc_reg_operand" "r")
976 (const_int 16)))
977 (match_operand:SI 4 "gpc_reg_operand" "0"))
978 (const_int 0)))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
980 (plus:SI (mult:SI (ashiftrt:SI
981 (match_dup 1)
982 (const_int 16))
983 (ashiftrt:SI
984 (match_dup 2)
985 (const_int 16)))
986 (match_dup 4)))]
987 "TARGET_MULHW"
988 "machhw. %0,%1,%2"
989 [(set_attr "type" "halfmul")])
991 (define_insn "*machhw"
992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
993 (plus:SI (mult:SI (ashiftrt:SI
994 (match_operand:SI 1 "gpc_reg_operand" "%r")
995 (const_int 16))
996 (ashiftrt:SI
997 (match_operand:SI 2 "gpc_reg_operand" "r")
998 (const_int 16)))
999 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1000 "TARGET_MULHW"
1001 "machhw %0,%1,%2"
1002 [(set_attr "type" "halfmul")])
1004 (define_insn "*machhwuc"
1005 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1006 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1007 (match_operand:SI 1 "gpc_reg_operand" "%r")
1008 (const_int 16))
1009 (lshiftrt:SI
1010 (match_operand:SI 2 "gpc_reg_operand" "r")
1011 (const_int 16)))
1012 (match_operand:SI 4 "gpc_reg_operand" "0"))
1013 (const_int 0)))
1014 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1015 (plus:SI (mult:SI (lshiftrt:SI
1016 (match_dup 1)
1017 (const_int 16))
1018 (lshiftrt:SI
1019 (match_dup 2)
1020 (const_int 16)))
1021 (match_dup 4)))]
1022 "TARGET_MULHW"
1023 "machhwu. %0,%1,%2"
1024 [(set_attr "type" "halfmul")])
1026 (define_insn "*machhwu"
1027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1028 (plus:SI (mult:SI (lshiftrt:SI
1029 (match_operand:SI 1 "gpc_reg_operand" "%r")
1030 (const_int 16))
1031 (lshiftrt:SI
1032 (match_operand:SI 2 "gpc_reg_operand" "r")
1033 (const_int 16)))
1034 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1035 "TARGET_MULHW"
1036 "machhwu %0,%1,%2"
1037 [(set_attr "type" "halfmul")])
1039 (define_insn "*maclhwc"
1040 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1041 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1042 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1043 (sign_extend:SI
1044 (match_operand:HI 2 "gpc_reg_operand" "r")))
1045 (match_operand:SI 4 "gpc_reg_operand" "0"))
1046 (const_int 0)))
1047 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1048 (plus:SI (mult:SI (sign_extend:SI
1049 (match_dup 1))
1050 (sign_extend:SI
1051 (match_dup 2)))
1052 (match_dup 4)))]
1053 "TARGET_MULHW"
1054 "maclhw. %0,%1,%2"
1055 [(set_attr "type" "halfmul")])
1057 (define_insn "*maclhw"
1058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1059 (plus:SI (mult:SI (sign_extend:SI
1060 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1061 (sign_extend:SI
1062 (match_operand:HI 2 "gpc_reg_operand" "r")))
1063 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1064 "TARGET_MULHW"
1065 "maclhw %0,%1,%2"
1066 [(set_attr "type" "halfmul")])
1068 (define_insn "*maclhwuc"
1069 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1070 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1071 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1072 (zero_extend:SI
1073 (match_operand:HI 2 "gpc_reg_operand" "r")))
1074 (match_operand:SI 4 "gpc_reg_operand" "0"))
1075 (const_int 0)))
1076 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1077 (plus:SI (mult:SI (zero_extend:SI
1078 (match_dup 1))
1079 (zero_extend:SI
1080 (match_dup 2)))
1081 (match_dup 4)))]
1082 "TARGET_MULHW"
1083 "maclhwu. %0,%1,%2"
1084 [(set_attr "type" "halfmul")])
1086 (define_insn "*maclhwu"
1087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1088 (plus:SI (mult:SI (zero_extend:SI
1089 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1090 (zero_extend:SI
1091 (match_operand:HI 2 "gpc_reg_operand" "r")))
1092 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1093 "TARGET_MULHW"
1094 "maclhwu %0,%1,%2"
1095 [(set_attr "type" "halfmul")])
1097 (define_insn "*nmacchwc"
1098 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1099 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1100 (mult:SI (ashiftrt:SI
1101 (match_operand:SI 2 "gpc_reg_operand" "r")
1102 (const_int 16))
1103 (sign_extend:SI
1104 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1105 (const_int 0)))
1106 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1107 (minus:SI (match_dup 4)
1108 (mult:SI (ashiftrt:SI
1109 (match_dup 2)
1110 (const_int 16))
1111 (sign_extend:SI
1112 (match_dup 1)))))]
1113 "TARGET_MULHW"
1114 "nmacchw. %0,%1,%2"
1115 [(set_attr "type" "halfmul")])
1117 (define_insn "*nmacchw"
1118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1119 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1120 (mult:SI (ashiftrt:SI
1121 (match_operand:SI 2 "gpc_reg_operand" "r")
1122 (const_int 16))
1123 (sign_extend:SI
1124 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1125 "TARGET_MULHW"
1126 "nmacchw %0,%1,%2"
1127 [(set_attr "type" "halfmul")])
1129 (define_insn "*nmachhwc"
1130 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1131 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1132 (mult:SI (ashiftrt:SI
1133 (match_operand:SI 1 "gpc_reg_operand" "%r")
1134 (const_int 16))
1135 (ashiftrt:SI
1136 (match_operand:SI 2 "gpc_reg_operand" "r")
1137 (const_int 16))))
1138 (const_int 0)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (minus:SI (match_dup 4)
1141 (mult:SI (ashiftrt:SI
1142 (match_dup 1)
1143 (const_int 16))
1144 (ashiftrt:SI
1145 (match_dup 2)
1146 (const_int 16)))))]
1147 "TARGET_MULHW"
1148 "nmachhw. %0,%1,%2"
1149 [(set_attr "type" "halfmul")])
1151 (define_insn "*nmachhw"
1152 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1153 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1154 (mult:SI (ashiftrt:SI
1155 (match_operand:SI 1 "gpc_reg_operand" "%r")
1156 (const_int 16))
1157 (ashiftrt:SI
1158 (match_operand:SI 2 "gpc_reg_operand" "r")
1159 (const_int 16)))))]
1160 "TARGET_MULHW"
1161 "nmachhw %0,%1,%2"
1162 [(set_attr "type" "halfmul")])
1164 (define_insn "*nmaclhwc"
1165 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1166 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1167 (mult:SI (sign_extend:SI
1168 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1169 (sign_extend:SI
1170 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1171 (const_int 0)))
1172 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1173 (minus:SI (match_dup 4)
1174 (mult:SI (sign_extend:SI
1175 (match_dup 1))
1176 (sign_extend:SI
1177 (match_dup 2)))))]
1178 "TARGET_MULHW"
1179 "nmaclhw. %0,%1,%2"
1180 [(set_attr "type" "halfmul")])
1182 (define_insn "*nmaclhw"
1183 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1184 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1185 (mult:SI (sign_extend:SI
1186 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1187 (sign_extend:SI
1188 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1189 "TARGET_MULHW"
1190 "nmaclhw %0,%1,%2"
1191 [(set_attr "type" "halfmul")])
1193 (define_insn "*mulchwc"
1194 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1195 (compare:CC (mult:SI (ashiftrt:SI
1196 (match_operand:SI 2 "gpc_reg_operand" "r")
1197 (const_int 16))
1198 (sign_extend:SI
1199 (match_operand:HI 1 "gpc_reg_operand" "r")))
1200 (const_int 0)))
1201 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1202 (mult:SI (ashiftrt:SI
1203 (match_dup 2)
1204 (const_int 16))
1205 (sign_extend:SI
1206 (match_dup 1))))]
1207 "TARGET_MULHW"
1208 "mulchw. %0,%1,%2"
1209 [(set_attr "type" "halfmul")])
1211 (define_insn "*mulchw"
1212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (mult:SI (ashiftrt:SI
1214 (match_operand:SI 2 "gpc_reg_operand" "r")
1215 (const_int 16))
1216 (sign_extend:SI
1217 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1218 "TARGET_MULHW"
1219 "mulchw %0,%1,%2"
1220 [(set_attr "type" "halfmul")])
1222 (define_insn "*mulchwuc"
1223 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1224 (compare:CC (mult:SI (lshiftrt:SI
1225 (match_operand:SI 2 "gpc_reg_operand" "r")
1226 (const_int 16))
1227 (zero_extend:SI
1228 (match_operand:HI 1 "gpc_reg_operand" "r")))
1229 (const_int 0)))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (mult:SI (lshiftrt:SI
1232 (match_dup 2)
1233 (const_int 16))
1234 (zero_extend:SI
1235 (match_dup 1))))]
1236 "TARGET_MULHW"
1237 "mulchwu. %0,%1,%2"
1238 [(set_attr "type" "halfmul")])
1240 (define_insn "*mulchwu"
1241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1242 (mult:SI (lshiftrt:SI
1243 (match_operand:SI 2 "gpc_reg_operand" "r")
1244 (const_int 16))
1245 (zero_extend:SI
1246 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1247 "TARGET_MULHW"
1248 "mulchwu %0,%1,%2"
1249 [(set_attr "type" "halfmul")])
1251 (define_insn "*mulhhwc"
1252 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1253 (compare:CC (mult:SI (ashiftrt:SI
1254 (match_operand:SI 1 "gpc_reg_operand" "%r")
1255 (const_int 16))
1256 (ashiftrt:SI
1257 (match_operand:SI 2 "gpc_reg_operand" "r")
1258 (const_int 16)))
1259 (const_int 0)))
1260 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1261 (mult:SI (ashiftrt:SI
1262 (match_dup 1)
1263 (const_int 16))
1264 (ashiftrt:SI
1265 (match_dup 2)
1266 (const_int 16))))]
1267 "TARGET_MULHW"
1268 "mulhhw. %0,%1,%2"
1269 [(set_attr "type" "halfmul")])
1271 (define_insn "*mulhhw"
1272 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1273 (mult:SI (ashiftrt:SI
1274 (match_operand:SI 1 "gpc_reg_operand" "%r")
1275 (const_int 16))
1276 (ashiftrt:SI
1277 (match_operand:SI 2 "gpc_reg_operand" "r")
1278 (const_int 16))))]
1279 "TARGET_MULHW"
1280 "mulhhw %0,%1,%2"
1281 [(set_attr "type" "halfmul")])
1283 (define_insn "*mulhhwuc"
1284 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1285 (compare:CC (mult:SI (lshiftrt:SI
1286 (match_operand:SI 1 "gpc_reg_operand" "%r")
1287 (const_int 16))
1288 (lshiftrt:SI
1289 (match_operand:SI 2 "gpc_reg_operand" "r")
1290 (const_int 16)))
1291 (const_int 0)))
1292 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1293 (mult:SI (lshiftrt:SI
1294 (match_dup 1)
1295 (const_int 16))
1296 (lshiftrt:SI
1297 (match_dup 2)
1298 (const_int 16))))]
1299 "TARGET_MULHW"
1300 "mulhhwu. %0,%1,%2"
1301 [(set_attr "type" "halfmul")])
1303 (define_insn "*mulhhwu"
1304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1305 (mult:SI (lshiftrt:SI
1306 (match_operand:SI 1 "gpc_reg_operand" "%r")
1307 (const_int 16))
1308 (lshiftrt:SI
1309 (match_operand:SI 2 "gpc_reg_operand" "r")
1310 (const_int 16))))]
1311 "TARGET_MULHW"
1312 "mulhhwu %0,%1,%2"
1313 [(set_attr "type" "halfmul")])
1315 (define_insn "*mullhwc"
1316 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1317 (compare:CC (mult:SI (sign_extend:SI
1318 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1319 (sign_extend:SI
1320 (match_operand:HI 2 "gpc_reg_operand" "r")))
1321 (const_int 0)))
1322 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1323 (mult:SI (sign_extend:SI
1324 (match_dup 1))
1325 (sign_extend:SI
1326 (match_dup 2))))]
1327 "TARGET_MULHW"
1328 "mullhw. %0,%1,%2"
1329 [(set_attr "type" "halfmul")])
1331 (define_insn "*mullhw"
1332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1333 (mult:SI (sign_extend:SI
1334 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1335 (sign_extend:SI
1336 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1337 "TARGET_MULHW"
1338 "mullhw %0,%1,%2"
1339 [(set_attr "type" "halfmul")])
1341 (define_insn "*mullhwuc"
1342 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1343 (compare:CC (mult:SI (zero_extend:SI
1344 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1345 (zero_extend:SI
1346 (match_operand:HI 2 "gpc_reg_operand" "r")))
1347 (const_int 0)))
1348 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1349 (mult:SI (zero_extend:SI
1350 (match_dup 1))
1351 (zero_extend:SI
1352 (match_dup 2))))]
1353 "TARGET_MULHW"
1354 "mullhwu. %0,%1,%2"
1355 [(set_attr "type" "halfmul")])
1357 (define_insn "*mullhwu"
1358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1359 (mult:SI (zero_extend:SI
1360 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1361 (zero_extend:SI
1362 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1363 "TARGET_MULHW"
1364 "mullhwu %0,%1,%2"
1365 [(set_attr "type" "halfmul")])
1366 \f
1367 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1368 (define_insn "dlmzb"
1369 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1370 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1371 (match_operand:SI 2 "gpc_reg_operand" "r")]
1372 UNSPEC_DLMZB_CR))
1373 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1374 (unspec:SI [(match_dup 1)
1375 (match_dup 2)]
1376 UNSPEC_DLMZB))]
1377 "TARGET_DLMZB"
1378 "dlmzb. %0,%1,%2")
1380 (define_expand "strlensi"
1381 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1382 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1383 (match_operand:QI 2 "const_int_operand" "")
1384 (match_operand 3 "const_int_operand" "")]
1385 UNSPEC_DLMZB_STRLEN))
1386 (clobber (match_scratch:CC 4 "=x"))]
1387 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1388 {
1389 rtx result = operands[0];
1390 rtx src = operands[1];
1391 rtx search_char = operands[2];
1392 rtx align = operands[3];
1393 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1394 rtx loop_label, end_label, mem, cr0, cond;
1395 if (search_char != const0_rtx
1396 || GET_CODE (align) != CONST_INT
1397 || INTVAL (align) < 8)
1398 FAIL;
1399 word1 = gen_reg_rtx (SImode);
1400 word2 = gen_reg_rtx (SImode);
1401 scratch_dlmzb = gen_reg_rtx (SImode);
1402 scratch_string = gen_reg_rtx (Pmode);
1403 loop_label = gen_label_rtx ();
1404 end_label = gen_label_rtx ();
1405 addr = force_reg (Pmode, XEXP (src, 0));
1406 emit_move_insn (scratch_string, addr);
1407 emit_label (loop_label);
1408 mem = change_address (src, SImode, scratch_string);
1409 emit_move_insn (word1, mem);
1410 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1411 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1412 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1413 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1414 emit_jump_insn (gen_rtx_SET (VOIDmode,
1415 pc_rtx,
1416 gen_rtx_IF_THEN_ELSE (VOIDmode,
1417 cond,
1418 gen_rtx_LABEL_REF
1419 (VOIDmode,
1420 end_label),
1421 pc_rtx)));
1422 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1423 emit_jump_insn (gen_rtx_SET (VOIDmode,
1424 pc_rtx,
1425 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1426 emit_barrier ();
1427 emit_label (end_label);
1428 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1429 emit_insn (gen_subsi3 (result, scratch_string, addr));
1430 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1431 DONE;
1432 })
1433 \f
1434 ;; Fixed-point arithmetic insns.
1436 (define_expand "add<mode>3"
1437 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1438 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1439 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1440 ""
1441 {
1442 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1443 {
1444 if (non_short_cint_operand (operands[2], DImode))
1445 FAIL;
1446 }
1447 else if (GET_CODE (operands[2]) == CONST_INT
1448 && ! add_operand (operands[2], <MODE>mode))
1449 {
1450 rtx tmp = ((!can_create_pseudo_p ()
1451 || rtx_equal_p (operands[0], operands[1]))
1452 ? operands[0] : gen_reg_rtx (<MODE>mode));
1454 HOST_WIDE_INT val = INTVAL (operands[2]);
1455 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1456 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1458 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1459 FAIL;
1461 /* The ordering here is important for the prolog expander.
1462 When space is allocated from the stack, adding 'low' first may
1463 produce a temporary deallocation (which would be bad). */
1464 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1465 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1466 DONE;
1467 }
1468 })
1470 ;; Discourage ai/addic because of carry but provide it in an alternative
1471 ;; allowing register zero as source.
1472 (define_insn "*add<mode>3_internal1"
1473 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1474 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1475 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1476 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1477 "@
1478 add %0,%1,%2
1479 addi %0,%1,%2
1480 addic %0,%1,%2
1481 addis %0,%1,%v2"
1482 [(set_attr "type" "add")])
1484 (define_insn "addsi3_high"
1485 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1486 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1487 (high:SI (match_operand 2 "" ""))))]
1488 "TARGET_MACHO && !TARGET_64BIT"
1489 "addis %0,%1,ha16(%2)"
1490 [(set_attr "type" "add")])
1492 (define_insn "*add<mode>3_internal2"
1493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1494 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1495 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1496 (const_int 0)))
1497 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1498 ""
1499 "@
1500 add. %3,%1,%2
1501 addic. %3,%1,%2
1502 #
1503 #"
1504 [(set_attr "type" "add,compare,compare,compare")
1505 (set_attr "dot" "yes")
1506 (set_attr "length" "4,4,8,8")])
1508 (define_split
1509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1510 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1511 (match_operand:GPR 2 "reg_or_short_operand" ""))
1512 (const_int 0)))
1513 (clobber (match_scratch:GPR 3 ""))]
1514 "reload_completed"
1515 [(set (match_dup 3)
1516 (plus:GPR (match_dup 1)
1517 (match_dup 2)))
1518 (set (match_dup 0)
1519 (compare:CC (match_dup 3)
1520 (const_int 0)))]
1521 "")
1523 (define_insn "*add<mode>3_internal3"
1524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1525 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1526 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1527 (const_int 0)))
1528 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1529 (plus:P (match_dup 1)
1530 (match_dup 2)))]
1531 ""
1532 "@
1533 add. %0,%1,%2
1534 addic. %0,%1,%2
1535 #
1536 #"
1537 [(set_attr "type" "add,compare,compare,compare")
1538 (set_attr "dot" "yes")
1539 (set_attr "length" "4,4,8,8")])
1541 (define_split
1542 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1543 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1544 (match_operand:P 2 "reg_or_short_operand" ""))
1545 (const_int 0)))
1546 (set (match_operand:P 0 "gpc_reg_operand" "")
1547 (plus:P (match_dup 1) (match_dup 2)))]
1548 "reload_completed"
1549 [(set (match_dup 0)
1550 (plus:P (match_dup 1)
1551 (match_dup 2)))
1552 (set (match_dup 3)
1553 (compare:CC (match_dup 0)
1554 (const_int 0)))]
1555 "")
1557 ;; Split an add that we can't do in one insn into two insns, each of which
1558 ;; does one 16-bit part. This is used by combine. Note that the low-order
1559 ;; add should be last in case the result gets used in an address.
1561 (define_split
1562 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1563 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1564 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1565 ""
1566 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1567 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1568 {
1569 HOST_WIDE_INT val = INTVAL (operands[2]);
1570 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1571 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1573 operands[4] = GEN_INT (low);
1574 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1575 operands[3] = GEN_INT (rest);
1576 else if (can_create_pseudo_p ())
1577 {
1578 operands[3] = gen_reg_rtx (DImode);
1579 emit_move_insn (operands[3], operands[2]);
1580 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1581 DONE;
1582 }
1583 else
1584 FAIL;
1585 })
1587 (define_expand "one_cmpl<mode>2"
1588 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1589 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1590 ""
1591 {
1592 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1593 {
1594 rs6000_split_logical (operands, NOT, false, false, false);
1595 DONE;
1596 }
1597 })
1599 (define_insn "*one_cmpl<mode>2"
1600 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1601 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1602 ""
1603 "not %0,%1")
1605 (define_insn_and_split "*one_cmpl<mode>2_dot"
1606 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1607 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1608 (const_int 0)))
1609 (clobber (match_scratch:GPR 0 "=r,r"))]
1610 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1611 "@
1612 not. %0,%1
1613 #"
1614 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1615 [(set (match_dup 0)
1616 (not:GPR (match_dup 1)))
1617 (set (match_dup 2)
1618 (compare:CC (match_dup 0)
1619 (const_int 0)))]
1620 ""
1621 [(set_attr "type" "logical")
1622 (set_attr "dot" "yes")
1623 (set_attr "length" "4,8")])
1625 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1626 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1627 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1628 (const_int 0)))
1629 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1630 (not:GPR (match_dup 1)))]
1631 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1632 "@
1633 not. %0,%1
1634 #"
1635 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1636 [(set (match_dup 0)
1637 (not:GPR (match_dup 1)))
1638 (set (match_dup 2)
1639 (compare:CC (match_dup 0)
1640 (const_int 0)))]
1641 ""
1642 [(set_attr "type" "logical")
1643 (set_attr "dot" "yes")
1644 (set_attr "length" "4,8")])
1647 (define_expand "sub<mode>3"
1648 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1649 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1650 (match_operand:SDI 2 "gpc_reg_operand" "")))]
1651 ""
1652 {
1653 if (short_cint_operand (operands[1], <MODE>mode)
1654 && !(<MODE>mode == DImode && !TARGET_POWERPC64))
1655 {
1656 emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
1657 DONE;
1658 }
1659 })
1661 (define_insn "*subf<mode>3"
1662 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1663 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
1664 (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1665 ""
1666 "subf %0,%1,%2"
1667 [(set_attr "type" "add")])
1669 (define_insn_and_split "*subf<mode>3_dot"
1670 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1671 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1672 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1673 (const_int 0)))
1674 (clobber (match_scratch:GPR 0 "=r,r"))]
1675 "<MODE>mode == Pmode"
1676 "@
1677 subf. %0,%1,%2
1678 #"
1679 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1680 [(set (match_dup 0)
1681 (minus:GPR (match_dup 2)
1682 (match_dup 1)))
1683 (set (match_dup 3)
1684 (compare:CC (match_dup 0)
1685 (const_int 0)))]
1686 ""
1687 [(set_attr "type" "add")
1688 (set_attr "dot" "yes")
1689 (set_attr "length" "4,8")])
1691 (define_insn_and_split "*subf<mode>3_dot2"
1692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1693 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1694 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1695 (const_int 0)))
1696 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1697 (minus:GPR (match_dup 2)
1698 (match_dup 1)))]
1699 "<MODE>mode == Pmode"
1700 "@
1701 subf. %0,%1,%2
1702 #"
1703 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1704 [(set (match_dup 0)
1705 (minus:GPR (match_dup 2)
1706 (match_dup 1)))
1707 (set (match_dup 3)
1708 (compare:CC (match_dup 0)
1709 (const_int 0)))]
1710 ""
1711 [(set_attr "type" "add")
1712 (set_attr "dot" "yes")
1713 (set_attr "length" "4,8")])
1715 (define_insn "subf<mode>3_imm"
1716 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1717 (minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
1718 (match_operand:GPR 1 "gpc_reg_operand" "r")))
1719 (clobber (reg:GPR CA_REGNO))]
1720 ""
1721 "subfic %0,%1,%2"
1722 [(set_attr "type" "add")])
1725 (define_expand "neg<mode>2"
1726 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1727 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1728 ""
1729 "")
1731 (define_insn "*neg<mode>2"
1732 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1733 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1734 ""
1735 "neg %0,%1"
1736 [(set_attr "type" "add")])
1738 (define_insn_and_split "*neg<mode>2_dot"
1739 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1740 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1741 (const_int 0)))
1742 (clobber (match_scratch:GPR 0 "=r,r"))]
1743 "<MODE>mode == Pmode"
1744 "@
1745 neg. %0,%1
1746 #"
1747 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1748 [(set (match_dup 0)
1749 (neg:GPR (match_dup 1)))
1750 (set (match_dup 2)
1751 (compare:CC (match_dup 0)
1752 (const_int 0)))]
1753 ""
1754 [(set_attr "type" "add")
1755 (set_attr "dot" "yes")
1756 (set_attr "length" "4,8")])
1758 (define_insn_and_split "*neg<mode>2_dot2"
1759 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1760 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1761 (const_int 0)))
1762 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1763 (neg:GPR (match_dup 1)))]
1764 "<MODE>mode == Pmode"
1765 "@
1766 neg. %0,%1
1767 #"
1768 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1769 [(set (match_dup 0)
1770 (neg:GPR (match_dup 1)))
1771 (set (match_dup 2)
1772 (compare:CC (match_dup 0)
1773 (const_int 0)))]
1774 ""
1775 [(set_attr "type" "add")
1776 (set_attr "dot" "yes")
1777 (set_attr "length" "4,8")])
1780 (define_insn "clz<mode>2"
1781 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1782 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1783 ""
1784 "cntlz<wd> %0,%1"
1785 [(set_attr "type" "cntlz")])
1787 (define_expand "ctz<mode>2"
1788 [(set (match_dup 2)
1789 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1790 (set (match_dup 3)
1791 (and:GPR (match_dup 1)
1792 (match_dup 2)))
1793 (set (match_dup 4)
1794 (clz:GPR (match_dup 3)))
1795 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1796 (minus:GPR (match_dup 5)
1797 (match_dup 4)))
1798 (clobber (reg:GPR CA_REGNO))])]
1799 ""
1800 {
1801 operands[2] = gen_reg_rtx (<MODE>mode);
1802 operands[3] = gen_reg_rtx (<MODE>mode);
1803 operands[4] = gen_reg_rtx (<MODE>mode);
1804 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1805 })
1807 (define_expand "ffs<mode>2"
1808 [(set (match_dup 2)
1809 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1810 (set (match_dup 3)
1811 (and:GPR (match_dup 1)
1812 (match_dup 2)))
1813 (set (match_dup 4)
1814 (clz:GPR (match_dup 3)))
1815 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1816 (minus:GPR (match_dup 5)
1817 (match_dup 4)))
1818 (clobber (reg:GPR CA_REGNO))])]
1819 ""
1820 {
1821 operands[2] = gen_reg_rtx (<MODE>mode);
1822 operands[3] = gen_reg_rtx (<MODE>mode);
1823 operands[4] = gen_reg_rtx (<MODE>mode);
1824 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1825 })
1827 (define_insn "popcntb<mode>2"
1828 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1829 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1830 UNSPEC_POPCNTB))]
1831 "TARGET_POPCNTB"
1832 "popcntb %0,%1"
1833 [(set_attr "length" "4")
1834 (set_attr "type" "popcnt")])
1836 (define_insn "popcntd<mode>2"
1837 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1838 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1839 "TARGET_POPCNTD"
1840 "popcnt<wd> %0,%1"
1841 [(set_attr "length" "4")
1842 (set_attr "type" "popcnt")])
1844 (define_expand "popcount<mode>2"
1845 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1846 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1847 "TARGET_POPCNTB || TARGET_POPCNTD"
1848 {
1849 rs6000_emit_popcount (operands[0], operands[1]);
1850 DONE;
1851 })
1853 (define_insn "parity<mode>2_cmpb"
1854 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1855 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1856 "TARGET_CMPB && TARGET_POPCNTB"
1857 "prty<wd> %0,%1"
1858 [(set_attr "length" "4")
1859 (set_attr "type" "popcnt")])
1861 (define_expand "parity<mode>2"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1863 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1864 "TARGET_POPCNTB"
1865 {
1866 rs6000_emit_parity (operands[0], operands[1]);
1867 DONE;
1868 })
1870 ;; Since the hardware zeros the upper part of the register, save generating the
1871 ;; AND immediate if we are converting to unsigned
1872 (define_insn "*bswaphi2_extenddi"
1873 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1874 (zero_extend:DI
1875 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1876 "TARGET_POWERPC64"
1877 "lhbrx %0,%y1"
1878 [(set_attr "length" "4")
1879 (set_attr "type" "load")])
1881 (define_insn "*bswaphi2_extendsi"
1882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1883 (zero_extend:SI
1884 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1885 ""
1886 "lhbrx %0,%y1"
1887 [(set_attr "length" "4")
1888 (set_attr "type" "load")])
1890 (define_expand "bswaphi2"
1891 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1892 (bswap:HI
1893 (match_operand:HI 1 "reg_or_mem_operand" "")))
1894 (clobber (match_scratch:SI 2 ""))])]
1895 ""
1896 {
1897 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1898 operands[1] = force_reg (HImode, operands[1]);
1899 })
1901 (define_insn "bswaphi2_internal"
1902 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1903 (bswap:HI
1904 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1905 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1906 ""
1907 "@
1908 lhbrx %0,%y1
1909 sthbrx %1,%y0
1910 #"
1911 [(set_attr "length" "4,4,12")
1912 (set_attr "type" "load,store,*")])
1914 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1915 ;; correct for -mlittle as well as -mbig.
1916 (define_split
1917 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1918 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1919 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1920 "reload_completed"
1921 [(set (match_dup 3)
1922 (zero_extract:SI (match_dup 4)
1923 (const_int 8)
1924 (const_int 16)))
1925 (set (match_dup 2)
1926 (and:SI (ashift:SI (match_dup 4)
1927 (const_int 8))
1928 (const_int 65280))) ;; 0xff00
1929 (set (match_dup 3)
1930 (ior:SI (match_dup 3)
1931 (match_dup 2)))]
1932 "
1933 {
1934 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1935 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1936 }")
1938 (define_insn "*bswapsi2_extenddi"
1939 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1940 (zero_extend:DI
1941 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1942 "TARGET_POWERPC64"
1943 "lwbrx %0,%y1"
1944 [(set_attr "length" "4")
1945 (set_attr "type" "load")])
1947 (define_expand "bswapsi2"
1948 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1949 (bswap:SI
1950 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1951 ""
1952 {
1953 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1954 operands[1] = force_reg (SImode, operands[1]);
1955 })
1957 (define_insn "*bswapsi2_internal"
1958 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1959 (bswap:SI
1960 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1961 ""
1962 "@
1963 lwbrx %0,%y1
1964 stwbrx %1,%y0
1965 #"
1966 [(set_attr "length" "4,4,12")
1967 (set_attr "type" "load,store,*")])
1969 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1970 ;; zero_extract insns do not change for -mlittle.
1971 (define_split
1972 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1973 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1974 "reload_completed"
1975 [(set (match_dup 0)
1976 (rotate:SI (match_dup 1) (const_int 8)))
1977 (set (zero_extract:SI (match_dup 0)
1978 (const_int 8)
1979 (const_int 0))
1980 (match_dup 1))
1981 (set (zero_extract:SI (match_dup 0)
1982 (const_int 8)
1983 (const_int 16))
1984 (rotate:SI (match_dup 1)
1985 (const_int 16)))]
1986 "")
1988 (define_expand "bswapdi2"
1989 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
1990 (bswap:DI
1991 (match_operand:DI 1 "reg_or_mem_operand" "")))
1992 (clobber (match_scratch:DI 2 ""))
1993 (clobber (match_scratch:DI 3 ""))
1994 (clobber (match_scratch:DI 4 ""))])]
1995 ""
1996 {
1997 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1998 operands[1] = force_reg (DImode, operands[1]);
2000 if (!TARGET_POWERPC64)
2001 {
2002 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2003 that uses 64-bit registers needs the same scratch registers as 64-bit
2004 mode. */
2005 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2006 DONE;
2007 }
2008 })
2010 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2011 (define_insn "*bswapdi2_ldbrx"
2012 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2013 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2014 (clobber (match_scratch:DI 2 "=X,X,&r"))
2015 (clobber (match_scratch:DI 3 "=X,X,&r"))
2016 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2017 "TARGET_POWERPC64 && TARGET_LDBRX
2018 && (REG_P (operands[0]) || REG_P (operands[1]))"
2019 "@
2020 ldbrx %0,%y1
2021 stdbrx %1,%y0
2022 #"
2023 [(set_attr "length" "4,4,36")
2024 (set_attr "type" "load,store,*")])
2026 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2027 (define_insn "*bswapdi2_64bit"
2028 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2029 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2030 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2031 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2032 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2033 "TARGET_POWERPC64 && !TARGET_LDBRX
2034 && (REG_P (operands[0]) || REG_P (operands[1]))
2035 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2036 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2037 "#"
2038 [(set_attr "length" "16,12,36")])
2040 (define_split
2041 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2042 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2043 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2044 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2045 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2046 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2047 [(const_int 0)]
2048 "
2049 {
2050 rtx dest = operands[0];
2051 rtx src = operands[1];
2052 rtx op2 = operands[2];
2053 rtx op3 = operands[3];
2054 rtx op4 = operands[4];
2055 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2056 BYTES_BIG_ENDIAN ? 4 : 0);
2057 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2058 BYTES_BIG_ENDIAN ? 4 : 0);
2059 rtx addr1;
2060 rtx addr2;
2061 rtx word_high;
2062 rtx word_low;
2064 addr1 = XEXP (src, 0);
2065 if (GET_CODE (addr1) == PLUS)
2066 {
2067 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2068 if (TARGET_AVOID_XFORM)
2069 {
2070 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2071 addr2 = op2;
2072 }
2073 else
2074 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2075 }
2076 else if (TARGET_AVOID_XFORM)
2077 {
2078 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2079 addr2 = op2;
2080 }
2081 else
2082 {
2083 emit_move_insn (op2, GEN_INT (4));
2084 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2085 }
2087 if (BYTES_BIG_ENDIAN)
2088 {
2089 word_high = change_address (src, SImode, addr1);
2090 word_low = change_address (src, SImode, addr2);
2091 }
2092 else
2093 {
2094 word_high = change_address (src, SImode, addr2);
2095 word_low = change_address (src, SImode, addr1);
2096 }
2098 emit_insn (gen_bswapsi2 (op3_32, word_low));
2099 emit_insn (gen_bswapsi2 (op4_32, word_high));
2100 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2101 emit_insn (gen_iordi3 (dest, dest, op4));
2102 DONE;
2103 }")
2105 (define_split
2106 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2107 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2108 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2109 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2110 (clobber (match_operand:DI 4 "" ""))]
2111 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2112 [(const_int 0)]
2113 "
2114 {
2115 rtx dest = operands[0];
2116 rtx src = operands[1];
2117 rtx op2 = operands[2];
2118 rtx op3 = operands[3];
2119 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2120 BYTES_BIG_ENDIAN ? 4 : 0);
2121 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2122 BYTES_BIG_ENDIAN ? 4 : 0);
2123 rtx addr1;
2124 rtx addr2;
2125 rtx word_high;
2126 rtx word_low;
2128 addr1 = XEXP (dest, 0);
2129 if (GET_CODE (addr1) == PLUS)
2130 {
2131 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2132 if (TARGET_AVOID_XFORM)
2133 {
2134 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2135 addr2 = op2;
2136 }
2137 else
2138 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2139 }
2140 else if (TARGET_AVOID_XFORM)
2141 {
2142 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2143 addr2 = op2;
2144 }
2145 else
2146 {
2147 emit_move_insn (op2, GEN_INT (4));
2148 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2149 }
2151 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2152 if (BYTES_BIG_ENDIAN)
2153 {
2154 word_high = change_address (dest, SImode, addr1);
2155 word_low = change_address (dest, SImode, addr2);
2156 }
2157 else
2158 {
2159 word_high = change_address (dest, SImode, addr2);
2160 word_low = change_address (dest, SImode, addr1);
2161 }
2162 emit_insn (gen_bswapsi2 (word_high, src_si));
2163 emit_insn (gen_bswapsi2 (word_low, op3_si));
2164 DONE;
2165 }")
2167 (define_split
2168 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2169 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2170 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2171 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2172 (clobber (match_operand:DI 4 "" ""))]
2173 "TARGET_POWERPC64 && reload_completed"
2174 [(const_int 0)]
2175 "
2176 {
2177 rtx dest = operands[0];
2178 rtx src = operands[1];
2179 rtx op2 = operands[2];
2180 rtx op3 = operands[3];
2181 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2182 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2183 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2184 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2185 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2187 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2188 emit_insn (gen_bswapsi2 (dest_si, src_si));
2189 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2190 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2191 emit_insn (gen_iordi3 (dest, dest, op3));
2192 DONE;
2193 }")
2195 (define_insn "bswapdi2_32bit"
2196 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2197 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2198 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2199 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2200 "#"
2201 [(set_attr "length" "16,12,36")])
2203 (define_split
2204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2205 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2206 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2207 "!TARGET_POWERPC64 && reload_completed"
2208 [(const_int 0)]
2209 "
2210 {
2211 rtx dest = operands[0];
2212 rtx src = operands[1];
2213 rtx op2 = operands[2];
2214 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2215 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2216 rtx addr1;
2217 rtx addr2;
2218 rtx word1;
2219 rtx word2;
2221 addr1 = XEXP (src, 0);
2222 if (GET_CODE (addr1) == PLUS)
2223 {
2224 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2225 if (TARGET_AVOID_XFORM)
2226 {
2227 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2228 addr2 = op2;
2229 }
2230 else
2231 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2232 }
2233 else if (TARGET_AVOID_XFORM)
2234 {
2235 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2236 addr2 = op2;
2237 }
2238 else
2239 {
2240 emit_move_insn (op2, GEN_INT (4));
2241 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2242 }
2244 word1 = change_address (src, SImode, addr1);
2245 word2 = change_address (src, SImode, addr2);
2247 emit_insn (gen_bswapsi2 (dest2, word1));
2248 emit_insn (gen_bswapsi2 (dest1, word2));
2249 DONE;
2250 }")
2252 (define_split
2253 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2254 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2255 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2256 "!TARGET_POWERPC64 && reload_completed"
2257 [(const_int 0)]
2258 "
2259 {
2260 rtx dest = operands[0];
2261 rtx src = operands[1];
2262 rtx op2 = operands[2];
2263 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2264 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2265 rtx addr1;
2266 rtx addr2;
2267 rtx word1;
2268 rtx word2;
2270 addr1 = XEXP (dest, 0);
2271 if (GET_CODE (addr1) == PLUS)
2272 {
2273 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2274 if (TARGET_AVOID_XFORM)
2275 {
2276 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2277 addr2 = op2;
2278 }
2279 else
2280 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2281 }
2282 else if (TARGET_AVOID_XFORM)
2283 {
2284 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2285 addr2 = op2;
2286 }
2287 else
2288 {
2289 emit_move_insn (op2, GEN_INT (4));
2290 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2291 }
2293 word1 = change_address (dest, SImode, addr1);
2294 word2 = change_address (dest, SImode, addr2);
2296 emit_insn (gen_bswapsi2 (word2, src1));
2297 emit_insn (gen_bswapsi2 (word1, src2));
2298 DONE;
2299 }")
2301 (define_split
2302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2303 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2304 (clobber (match_operand:SI 2 "" ""))]
2305 "!TARGET_POWERPC64 && reload_completed"
2306 [(const_int 0)]
2307 "
2308 {
2309 rtx dest = operands[0];
2310 rtx src = operands[1];
2311 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2312 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2313 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2314 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2316 emit_insn (gen_bswapsi2 (dest1, src2));
2317 emit_insn (gen_bswapsi2 (dest2, src1));
2318 DONE;
2319 }")
2322 (define_insn "mul<mode>3"
2323 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2324 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2325 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2326 ""
2327 "@
2328 mull<wd> %0,%1,%2
2329 mulli %0,%1,%2"
2330 [(set_attr "type" "mul")
2331 (set (attr "size")
2332 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2333 (const_string "8")
2334 (match_operand:GPR 2 "short_cint_operand" "")
2335 (const_string "16")]
2336 (const_string "<bits>")))])
2338 (define_insn_and_split "*mul<mode>3_dot"
2339 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2340 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2341 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2342 (const_int 0)))
2343 (clobber (match_scratch:GPR 0 "=r,r"))]
2344 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2345 "@
2346 mull<wd>. %0,%1,%2
2347 #"
2348 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2349 [(set (match_dup 0)
2350 (mult:GPR (match_dup 1)
2351 (match_dup 2)))
2352 (set (match_dup 3)
2353 (compare:CC (match_dup 0)
2354 (const_int 0)))]
2355 ""
2356 [(set_attr "type" "mul")
2357 (set_attr "size" "<bits>")
2358 (set_attr "dot" "yes")
2359 (set_attr "length" "4,8")])
2361 (define_insn_and_split "*mul<mode>3_dot2"
2362 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2363 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2364 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2365 (const_int 0)))
2366 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2367 (mult:GPR (match_dup 1)
2368 (match_dup 2)))]
2369 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2370 "@
2371 mull<wd>. %0,%1,%2
2372 #"
2373 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2374 [(set (match_dup 0)
2375 (mult:GPR (match_dup 1)
2376 (match_dup 2)))
2377 (set (match_dup 3)
2378 (compare:CC (match_dup 0)
2379 (const_int 0)))]
2380 ""
2381 [(set_attr "type" "mul")
2382 (set_attr "size" "<bits>")
2383 (set_attr "dot" "yes")
2384 (set_attr "length" "4,8")])
2387 (define_expand "<su>mul<mode>3_highpart"
2388 [(set (match_operand:GPR 0 "gpc_reg_operand")
2389 (subreg:GPR
2390 (mult:<DMODE> (any_extend:<DMODE>
2391 (match_operand:GPR 1 "gpc_reg_operand"))
2392 (any_extend:<DMODE>
2393 (match_operand:GPR 2 "gpc_reg_operand")))
2394 0))]
2395 ""
2396 {
2397 if (<MODE>mode == SImode && TARGET_POWERPC64)
2398 {
2399 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2400 operands[2]));
2401 DONE;
2402 }
2404 if (!WORDS_BIG_ENDIAN)
2405 {
2406 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2407 operands[2]));
2408 DONE;
2409 }
2410 })
2412 (define_insn "*<su>mul<mode>3_highpart"
2413 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2414 (subreg:GPR
2415 (mult:<DMODE> (any_extend:<DMODE>
2416 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2417 (any_extend:<DMODE>
2418 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2419 0))]
2420 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2421 "mulh<wd><u> %0,%1,%2"
2422 [(set_attr "type" "mul")
2423 (set_attr "size" "<bits>")])
2425 (define_insn "<su>mulsi3_highpart_le"
2426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2427 (subreg:SI
2428 (mult:DI (any_extend:DI
2429 (match_operand:SI 1 "gpc_reg_operand" "r"))
2430 (any_extend:DI
2431 (match_operand:SI 2 "gpc_reg_operand" "r")))
2432 4))]
2433 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2434 "mulhw<u> %0,%1,%2"
2435 [(set_attr "type" "mul")])
2437 (define_insn "<su>muldi3_highpart_le"
2438 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2439 (subreg:DI
2440 (mult:TI (any_extend:TI
2441 (match_operand:DI 1 "gpc_reg_operand" "r"))
2442 (any_extend:TI
2443 (match_operand:DI 2 "gpc_reg_operand" "r")))
2444 8))]
2445 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2446 "mulhd<u> %0,%1,%2"
2447 [(set_attr "type" "mul")
2448 (set_attr "size" "64")])
2450 (define_insn "<su>mulsi3_highpart_64"
2451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2452 (truncate:SI
2453 (lshiftrt:DI
2454 (mult:DI (any_extend:DI
2455 (match_operand:SI 1 "gpc_reg_operand" "r"))
2456 (any_extend:DI
2457 (match_operand:SI 2 "gpc_reg_operand" "r")))
2458 (const_int 32))))]
2459 "TARGET_POWERPC64"
2460 "mulhw<u> %0,%1,%2"
2461 [(set_attr "type" "mul")])
2463 (define_expand "<u>mul<mode><dmode>3"
2464 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2465 (mult:<DMODE> (any_extend:<DMODE>
2466 (match_operand:GPR 1 "gpc_reg_operand"))
2467 (any_extend:<DMODE>
2468 (match_operand:GPR 2 "gpc_reg_operand"))))]
2469 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2470 {
2471 rtx l = gen_reg_rtx (<MODE>mode);
2472 rtx h = gen_reg_rtx (<MODE>mode);
2473 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2474 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2475 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2476 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2477 DONE;
2478 })
2481 (define_insn "udiv<mode>3"
2482 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2483 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2484 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2485 ""
2486 "div<wd>u %0,%1,%2"
2487 [(set_attr "type" "div")
2488 (set_attr "size" "<bits>")])
2491 ;; For powers of two we can do srai/aze for divide and then adjust for
2492 ;; modulus. If it isn't a power of two, force operands into register and do
2493 ;; a normal divide.
2494 (define_expand "div<mode>3"
2495 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2496 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2497 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2498 ""
2499 {
2500 if (GET_CODE (operands[2]) != CONST_INT
2501 || INTVAL (operands[2]) <= 0
2502 || exact_log2 (INTVAL (operands[2])) < 0)
2503 operands[2] = force_reg (<MODE>mode, operands[2]);
2504 })
2506 (define_insn "*div<mode>3"
2507 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2508 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2509 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2510 ""
2511 "div<wd> %0,%1,%2"
2512 [(set_attr "type" "div")
2513 (set_attr "size" "<bits>")])
2515 (define_expand "mod<mode>3"
2516 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2517 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2518 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2519 ""
2520 "
2521 {
2522 int i;
2523 rtx temp1;
2524 rtx temp2;
2526 if (GET_CODE (operands[2]) != CONST_INT
2527 || INTVAL (operands[2]) <= 0
2528 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2529 FAIL;
2531 temp1 = gen_reg_rtx (<MODE>mode);
2532 temp2 = gen_reg_rtx (<MODE>mode);
2534 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2535 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2536 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2537 DONE;
2538 }")
2540 (define_insn ""
2541 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2542 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2543 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2544 ""
2545 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2546 [(set_attr "type" "two")
2547 (set_attr "length" "8")])
2549 (define_insn ""
2550 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2551 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2552 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2553 (const_int 0)))
2554 (clobber (match_scratch:P 3 "=r,r"))]
2555 ""
2556 "@
2557 sra<wd>i %3,%1,%p2\;addze. %3,%3
2558 #"
2559 [(set_attr "type" "compare")
2560 (set_attr "length" "8,12")
2561 (set_attr "cell_micro" "not")])
2563 (define_split
2564 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2565 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2566 (match_operand:GPR 2 "exact_log2_cint_operand"
2567 ""))
2568 (const_int 0)))
2569 (clobber (match_scratch:GPR 3 ""))]
2570 "reload_completed"
2571 [(set (match_dup 3)
2572 (div:<MODE> (match_dup 1) (match_dup 2)))
2573 (set (match_dup 0)
2574 (compare:CC (match_dup 3)
2575 (const_int 0)))]
2576 "")
2578 (define_insn ""
2579 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2580 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2581 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2582 (const_int 0)))
2583 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2584 (div:P (match_dup 1) (match_dup 2)))]
2585 ""
2586 "@
2587 sra<wd>i %0,%1,%p2\;addze. %0,%0
2588 #"
2589 [(set_attr "type" "compare")
2590 (set_attr "length" "8,12")
2591 (set_attr "cell_micro" "not")])
2593 (define_split
2594 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2595 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2596 (match_operand:GPR 2 "exact_log2_cint_operand"
2597 ""))
2598 (const_int 0)))
2599 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2600 (div:GPR (match_dup 1) (match_dup 2)))]
2601 "reload_completed"
2602 [(set (match_dup 0)
2603 (div:<MODE> (match_dup 1) (match_dup 2)))
2604 (set (match_dup 3)
2605 (compare:CC (match_dup 0)
2606 (const_int 0)))]
2607 "")
2608 \f
2609 ;; Logical instructions
2610 ;; The logical instructions are mostly combined by using match_operator,
2611 ;; but the plain AND insns are somewhat different because there is no
2612 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2613 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2615 (define_expand "and<mode>3"
2616 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2617 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2618 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2619 ""
2620 {
2621 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2622 {
2623 rs6000_split_logical (operands, AND, false, false, false);
2624 DONE;
2625 }
2627 if (logical_const_operand (operands[2], <MODE>mode)
2628 && !any_mask_operand (operands[2], <MODE>mode))
2629 {
2630 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2631 DONE;
2632 }
2634 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2635 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2636 operands[2] = force_reg (<MODE>mode, operands[2]);
2637 })
2640 (define_insn "and<mode>3_imm"
2641 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2642 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2643 (match_operand:GPR 2 "logical_const_operand" "n")))
2644 (clobber (match_scratch:CC 3 "=x"))]
2645 "rs6000_gen_cell_microcode
2646 && !any_mask_operand (operands[2], <MODE>mode)"
2647 "andi%e2. %0,%1,%u2"
2648 [(set_attr "type" "logical")
2649 (set_attr "dot" "yes")])
2651 (define_insn_and_split "*and<mode>3_imm_dot"
2652 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2653 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2654 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2655 (const_int 0)))
2656 (clobber (match_scratch:GPR 0 "=r,r"))
2657 (clobber (match_scratch:CC 4 "=X,x"))]
2658 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2659 && rs6000_gen_cell_microcode
2660 && !any_mask_operand (operands[2], <MODE>mode)"
2661 "@
2662 andi%e2. %0,%1,%u2
2663 #"
2664 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2665 [(parallel [(set (match_dup 0)
2666 (and:GPR (match_dup 1)
2667 (match_dup 2)))
2668 (clobber (match_dup 4))])
2669 (set (match_dup 3)
2670 (compare:CC (match_dup 0)
2671 (const_int 0)))]
2672 ""
2673 [(set_attr "type" "logical")
2674 (set_attr "dot" "yes")
2675 (set_attr "length" "4,8")])
2677 (define_insn_and_split "*and<mode>3_imm_dot2"
2678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2679 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2680 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2681 (const_int 0)))
2682 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2683 (and:GPR (match_dup 1)
2684 (match_dup 2)))
2685 (clobber (match_scratch:CC 4 "=X,x"))]
2686 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2687 && rs6000_gen_cell_microcode
2688 && !any_mask_operand (operands[2], <MODE>mode)"
2689 "@
2690 andi%e2. %0,%1,%u2
2691 #"
2692 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2693 [(parallel [(set (match_dup 0)
2694 (and:GPR (match_dup 1)
2695 (match_dup 2)))
2696 (clobber (match_dup 4))])
2697 (set (match_dup 3)
2698 (compare:CC (match_dup 0)
2699 (const_int 0)))]
2700 ""
2701 [(set_attr "type" "logical")
2702 (set_attr "dot" "yes")
2703 (set_attr "length" "4,8")])
2705 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2706 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2707 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2708 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2709 (const_int 0)))
2710 (clobber (match_scratch:GPR 0 "=r,r"))]
2711 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2712 && rs6000_gen_cell_microcode
2713 && any_mask_operand (operands[2], <MODE>mode)"
2714 "@
2715 andi%e2. %0,%1,%u2
2716 #"
2717 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2718 [(set (match_dup 0)
2719 (and:GPR (match_dup 1)
2720 (match_dup 2)))
2721 (set (match_dup 3)
2722 (compare:CC (match_dup 0)
2723 (const_int 0)))]
2724 ""
2725 [(set_attr "type" "logical")
2726 (set_attr "dot" "yes")
2727 (set_attr "length" "4,8")])
2729 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
2730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2731 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2732 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2733 (const_int 0)))
2734 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2735 (and:GPR (match_dup 1)
2736 (match_dup 2)))]
2737 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2738 && rs6000_gen_cell_microcode
2739 && any_mask_operand (operands[2], <MODE>mode)"
2740 "@
2741 andi%e2. %0,%1,%u2
2742 #"
2743 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2744 [(set (match_dup 0)
2745 (and:GPR (match_dup 1)
2746 (match_dup 2)))
2747 (set (match_dup 3)
2748 (compare:CC (match_dup 0)
2749 (const_int 0)))]
2750 ""
2751 [(set_attr "type" "logical")
2752 (set_attr "dot" "yes")
2753 (set_attr "length" "4,8")])
2756 (define_insn "*and<mode>3_mask"
2757 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2758 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2759 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2760 ""
2761 "@
2762 rldic%B2 %0,%1,0,%S2
2763 rlwinm %0,%1,0,%m2,%M2"
2764 [(set_attr "type" "shift")])
2766 (define_insn_and_split "*and<mode>3_mask_dot"
2767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2768 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2769 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2770 (const_int 0)))
2771 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2772 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2773 && rs6000_gen_cell_microcode
2774 && !logical_const_operand (operands[2], <MODE>mode)"
2775 "@
2776 rldic%B2. %0,%1,0,%S2
2777 rlwinm. %0,%1,0,%m2,%M2
2778 #
2779 #"
2780 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2781 [(set (match_dup 0)
2782 (and:GPR (match_dup 1)
2783 (match_dup 2)))
2784 (set (match_dup 3)
2785 (compare:CC (match_dup 0)
2786 (const_int 0)))]
2787 ""
2788 [(set_attr "type" "shift")
2789 (set_attr "dot" "yes")
2790 (set_attr "length" "4,4,8,8")])
2792 (define_insn_and_split "*and<mode>3_mask_dot2"
2793 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2794 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2795 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2796 (const_int 0)))
2797 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2798 (and:GPR (match_dup 1)
2799 (match_dup 2)))]
2800 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2801 && rs6000_gen_cell_microcode
2802 && !logical_const_operand (operands[2], <MODE>mode)"
2803 "@
2804 rldic%B2. %0,%1,0,%S2
2805 rlwinm. %0,%1,0,%m2,%M2
2806 #
2807 #"
2808 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2809 [(set (match_dup 0)
2810 (and:GPR (match_dup 1)
2811 (match_dup 2)))
2812 (set (match_dup 3)
2813 (compare:CC (match_dup 0)
2814 (const_int 0)))]
2815 ""
2816 [(set_attr "type" "shift")
2817 (set_attr "dot" "yes")
2818 (set_attr "length" "4,4,8,8")])
2822 (define_insn "andsi3_internal0_nomc"
2823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2824 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2825 (match_operand:SI 2 "and_operand" "?r,T")))]
2826 "!rs6000_gen_cell_microcode"
2827 "@
2828 and %0,%1,%2
2829 rlwinm %0,%1,0,%m2,%M2"
2830 [(set_attr "type" "logical,shift")])
2833 ;; Handle the PowerPC64 rlwinm corner case
2835 (define_insn_and_split "*andsi3_internal6"
2836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2837 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2838 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2839 "TARGET_POWERPC64"
2840 "#"
2841 "TARGET_POWERPC64"
2842 [(set (match_dup 0)
2843 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2844 (match_dup 4)))
2845 (set (match_dup 0)
2846 (rotate:SI (match_dup 0) (match_dup 5)))]
2847 "
2848 {
2849 int mb = extract_MB (operands[2]);
2850 int me = extract_ME (operands[2]);
2851 operands[3] = GEN_INT (me + 1);
2852 operands[5] = GEN_INT (32 - (me + 1));
2853 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2854 }"
2855 [(set_attr "length" "8")])
2858 (define_expand "<iorxor><mode>3"
2859 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2860 (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2861 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2862 ""
2863 {
2864 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2865 {
2866 rs6000_split_logical (operands, <IORXOR>, false, false, false);
2867 DONE;
2868 }
2870 if (non_logical_cint_operand (operands[2], <MODE>mode))
2871 {
2872 rtx tmp = ((!can_create_pseudo_p ()
2873 || rtx_equal_p (operands[0], operands[1]))
2874 ? operands[0] : gen_reg_rtx (<MODE>mode));
2876 HOST_WIDE_INT value = INTVAL (operands[2]);
2877 HOST_WIDE_INT lo = value & 0xffff;
2878 HOST_WIDE_INT hi = value - lo;
2880 emit_insn (gen_<iorxor><mode>3 (tmp, operands[1], GEN_INT (hi)));
2881 emit_insn (gen_<iorxor><mode>3 (operands[0], tmp, GEN_INT (lo)));
2882 DONE;
2883 }
2885 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2886 operands[2] = force_reg (<MODE>mode, operands[2]);
2887 })
2889 (define_split
2890 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2891 (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2892 (match_operand:GPR 2 "non_logical_cint_operand" "")))]
2893 ""
2894 [(set (match_dup 3)
2895 (iorxor:GPR (match_dup 1)
2896 (match_dup 4)))
2897 (set (match_dup 0)
2898 (iorxor:GPR (match_dup 3)
2899 (match_dup 5)))]
2900 {
2901 operands[3] = ((!can_create_pseudo_p ()
2902 || rtx_equal_p (operands[0], operands[1]))
2903 ? operands[0] : gen_reg_rtx (<MODE>mode));
2905 HOST_WIDE_INT value = INTVAL (operands[2]);
2906 HOST_WIDE_INT lo = value & 0xffff;
2907 HOST_WIDE_INT hi = value - lo;
2909 operands[4] = GEN_INT (hi);
2910 operands[5] = GEN_INT (lo);
2911 })
2913 (define_insn "*bool<mode>3_imm"
2914 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2915 (match_operator:GPR 3 "boolean_or_operator"
2916 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
2917 (match_operand:GPR 2 "logical_const_operand" "n")]))]
2918 ""
2919 "%q3i%e2 %0,%1,%u2"
2920 [(set_attr "type" "logical")])
2922 (define_insn "*bool<mode>3"
2923 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2924 (match_operator:GPR 3 "boolean_operator"
2925 [(match_operand:GPR 1 "gpc_reg_operand" "r")
2926 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
2927 ""
2928 "%q3 %0,%1,%2"
2929 [(set_attr "type" "logical")])
2931 (define_insn_and_split "*bool<mode>3_dot"
2932 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2933 (compare:CC (match_operator:GPR 3 "boolean_operator"
2934 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2935 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2936 (const_int 0)))
2937 (clobber (match_scratch:GPR 0 "=r,r"))]
2938 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2939 "@
2940 %q3. %0,%1,%2
2941 #"
2942 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2943 [(set (match_dup 0)
2944 (match_dup 3))
2945 (set (match_dup 4)
2946 (compare:CC (match_dup 0)
2947 (const_int 0)))]
2948 ""
2949 [(set_attr "type" "logical")
2950 (set_attr "dot" "yes")
2951 (set_attr "length" "4,8")])
2953 (define_insn_and_split "*bool<mode>3_dot2"
2954 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2955 (compare:CC (match_operator:GPR 3 "boolean_operator"
2956 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2957 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2958 (const_int 0)))
2959 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2960 (match_dup 3))]
2961 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2962 "@
2963 %q3. %0,%1,%2
2964 #"
2965 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2966 [(set (match_dup 0)
2967 (match_dup 3))
2968 (set (match_dup 4)
2969 (compare:CC (match_dup 0)
2970 (const_int 0)))]
2971 ""
2972 [(set_attr "type" "logical")
2973 (set_attr "dot" "yes")
2974 (set_attr "length" "4,8")])
2977 (define_insn "*boolc<mode>3"
2978 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2979 (match_operator:GPR 3 "boolean_operator"
2980 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
2981 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
2982 ""
2983 "%q3 %0,%1,%2"
2984 [(set_attr "type" "logical")])
2986 (define_insn_and_split "*boolc<mode>3_dot"
2987 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2988 (compare:CC (match_operator:GPR 3 "boolean_operator"
2989 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2990 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
2991 (const_int 0)))
2992 (clobber (match_scratch:GPR 0 "=r,r"))]
2993 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2994 "@
2995 %q3. %0,%1,%2
2996 #"
2997 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2998 [(set (match_dup 0)
2999 (match_dup 3))
3000 (set (match_dup 4)
3001 (compare:CC (match_dup 0)
3002 (const_int 0)))]
3003 ""
3004 [(set_attr "type" "logical")
3005 (set_attr "dot" "yes")
3006 (set_attr "length" "4,8")])
3008 (define_insn_and_split "*boolc<mode>3_dot2"
3009 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3010 (compare:CC (match_operator:GPR 3 "boolean_operator"
3011 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3012 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3013 (const_int 0)))
3014 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3015 (match_dup 3))]
3016 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3017 "@
3018 %q3. %0,%1,%2
3019 #"
3020 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3021 [(set (match_dup 0)
3022 (match_dup 3))
3023 (set (match_dup 4)
3024 (compare:CC (match_dup 0)
3025 (const_int 0)))]
3026 ""
3027 [(set_attr "type" "logical")
3028 (set_attr "dot" "yes")
3029 (set_attr "length" "4,8")])
3032 (define_insn "*boolcc<mode>3"
3033 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3034 (match_operator:GPR 3 "boolean_operator"
3035 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3036 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3037 ""
3038 "%q3 %0,%1,%2"
3039 [(set_attr "type" "logical")])
3041 (define_insn_and_split "*boolcc<mode>3_dot"
3042 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3043 (compare:CC (match_operator:GPR 3 "boolean_operator"
3044 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3045 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3046 (const_int 0)))
3047 (clobber (match_scratch:GPR 0 "=r,r"))]
3048 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3049 "@
3050 %q3. %0,%1,%2
3051 #"
3052 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3053 [(set (match_dup 0)
3054 (match_dup 3))
3055 (set (match_dup 4)
3056 (compare:CC (match_dup 0)
3057 (const_int 0)))]
3058 ""
3059 [(set_attr "type" "logical")
3060 (set_attr "dot" "yes")
3061 (set_attr "length" "4,8")])
3063 (define_insn_and_split "*boolcc<mode>3_dot2"
3064 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3065 (compare:CC (match_operator:GPR 3 "boolean_operator"
3066 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3067 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3068 (const_int 0)))
3069 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3070 (match_dup 3))]
3071 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3072 "@
3073 %q3. %0,%1,%2
3074 #"
3075 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3076 [(set (match_dup 0)
3077 (match_dup 3))
3078 (set (match_dup 4)
3079 (compare:CC (match_dup 0)
3080 (const_int 0)))]
3081 ""
3082 [(set_attr "type" "logical")
3083 (set_attr "dot" "yes")
3084 (set_attr "length" "4,8")])
3087 ;; TODO: Should have dots of this as well.
3088 (define_insn "*eqv<mode>3"
3089 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3090 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3091 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3092 ""
3093 "eqv %0,%1,%2"
3094 [(set_attr "type" "logical")])
3095 \f
3096 ;; Rotate and shift insns, in all their variants. These support shifts,
3097 ;; field inserts and extracts, and various combinations thereof.
3098 (define_expand "insv"
3099 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3100 (match_operand:SI 1 "const_int_operand" "")
3101 (match_operand:SI 2 "const_int_operand" ""))
3102 (match_operand 3 "gpc_reg_operand" ""))]
3103 ""
3104 "
3105 {
3106 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3107 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3108 compiler if the address of the structure is taken later. Likewise, do
3109 not handle invalid E500 subregs. */
3110 if (GET_CODE (operands[0]) == SUBREG
3111 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3112 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3113 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3114 FAIL;
3116 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3117 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3118 operands[3]));
3119 else
3120 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3121 operands[3]));
3122 DONE;
3123 }")
3125 (define_insn "insvsi_internal"
3126 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3127 (match_operand:SI 1 "const_int_operand" "i")
3128 (match_operand:SI 2 "const_int_operand" "i"))
3129 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3130 ""
3131 "*
3132 {
3133 int start = INTVAL (operands[2]) & 31;
3134 int size = INTVAL (operands[1]) & 31;
3136 operands[4] = GEN_INT (32 - start - size);
3137 operands[1] = GEN_INT (start + size - 1);
3138 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3139 }"
3140 [(set_attr "type" "insert")])
3142 (define_insn "*insvsi_internal1"
3143 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3144 (match_operand:SI 1 "const_int_operand" "i")
3145 (match_operand:SI 2 "const_int_operand" "i"))
3146 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3147 (match_operand:SI 4 "const_int_operand" "i")))]
3148 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3149 "*
3150 {
3151 int shift = INTVAL (operands[4]) & 31;
3152 int start = INTVAL (operands[2]) & 31;
3153 int size = INTVAL (operands[1]) & 31;
3155 operands[4] = GEN_INT (shift - start - size);
3156 operands[1] = GEN_INT (start + size - 1);
3157 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3158 }"
3159 [(set_attr "type" "insert")])
3161 (define_insn "*insvsi_internal2"
3162 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3163 (match_operand:SI 1 "const_int_operand" "i")
3164 (match_operand:SI 2 "const_int_operand" "i"))
3165 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3166 (match_operand:SI 4 "const_int_operand" "i")))]
3167 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3168 "*
3169 {
3170 int shift = INTVAL (operands[4]) & 31;
3171 int start = INTVAL (operands[2]) & 31;
3172 int size = INTVAL (operands[1]) & 31;
3174 operands[4] = GEN_INT (32 - shift - start - size);
3175 operands[1] = GEN_INT (start + size - 1);
3176 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3177 }"
3178 [(set_attr "type" "insert")])
3180 (define_insn "*insvsi_internal3"
3181 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3182 (match_operand:SI 1 "const_int_operand" "i")
3183 (match_operand:SI 2 "const_int_operand" "i"))
3184 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3185 (match_operand:SI 4 "const_int_operand" "i")))]
3186 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3187 "*
3188 {
3189 int shift = INTVAL (operands[4]) & 31;
3190 int start = INTVAL (operands[2]) & 31;
3191 int size = INTVAL (operands[1]) & 31;
3193 operands[4] = GEN_INT (32 - shift - start - size);
3194 operands[1] = GEN_INT (start + size - 1);
3195 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3196 }"
3197 [(set_attr "type" "insert")])
3199 (define_insn "*insvsi_internal4"
3200 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3201 (match_operand:SI 1 "const_int_operand" "i")
3202 (match_operand:SI 2 "const_int_operand" "i"))
3203 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3204 (match_operand:SI 4 "const_int_operand" "i")
3205 (match_operand:SI 5 "const_int_operand" "i")))]
3206 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3207 "*
3208 {
3209 int extract_start = INTVAL (operands[5]) & 31;
3210 int extract_size = INTVAL (operands[4]) & 31;
3211 int insert_start = INTVAL (operands[2]) & 31;
3212 int insert_size = INTVAL (operands[1]) & 31;
3214 /* Align extract field with insert field */
3215 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3216 operands[1] = GEN_INT (insert_start + insert_size - 1);
3217 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3218 }"
3219 [(set_attr "type" "insert")])
3221 ;; combine patterns for rlwimi
3222 (define_insn "*insvsi_internal5"
3223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3224 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3225 (match_operand:SI 1 "mask_operand" "i"))
3226 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3227 (match_operand:SI 2 "const_int_operand" "i"))
3228 (match_operand:SI 5 "mask_operand" "i"))))]
3229 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3230 "*
3231 {
3232 int me = extract_ME(operands[5]);
3233 int mb = extract_MB(operands[5]);
3234 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3235 operands[2] = GEN_INT(mb);
3236 operands[1] = GEN_INT(me);
3237 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3238 }"
3239 [(set_attr "type" "insert")])
3241 (define_insn "*insvsi_internal6"
3242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3243 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3244 (match_operand:SI 2 "const_int_operand" "i"))
3245 (match_operand:SI 5 "mask_operand" "i"))
3246 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3247 (match_operand:SI 1 "mask_operand" "i"))))]
3248 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3249 "*
3250 {
3251 int me = extract_ME(operands[5]);
3252 int mb = extract_MB(operands[5]);
3253 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3254 operands[2] = GEN_INT(mb);
3255 operands[1] = GEN_INT(me);
3256 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3257 }"
3258 [(set_attr "type" "insert")])
3260 (define_insn "insvdi_internal"
3261 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3262 (match_operand:SI 1 "const_int_operand" "i")
3263 (match_operand:SI 2 "const_int_operand" "i"))
3264 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3265 "TARGET_POWERPC64"
3266 "*
3267 {
3268 int start = INTVAL (operands[2]) & 63;
3269 int size = INTVAL (operands[1]) & 63;
3271 operands[1] = GEN_INT (64 - start - size);
3272 return \"rldimi %0,%3,%H1,%H2\";
3273 }"
3274 [(set_attr "type" "insert")
3275 (set_attr "size" "64")])
3277 (define_insn "*insvdi_internal2"
3278 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3279 (match_operand:SI 1 "const_int_operand" "i")
3280 (match_operand:SI 2 "const_int_operand" "i"))
3281 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3282 (match_operand:SI 4 "const_int_operand" "i")))]
3283 "TARGET_POWERPC64
3284 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3285 "*
3286 {
3287 int shift = INTVAL (operands[4]) & 63;
3288 int start = (INTVAL (operands[2]) & 63) - 32;
3289 int size = INTVAL (operands[1]) & 63;
3291 operands[4] = GEN_INT (64 - shift - start - size);
3292 operands[2] = GEN_INT (start);
3293 operands[1] = GEN_INT (start + size - 1);
3294 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3295 }")
3297 (define_insn "*insvdi_internal3"
3298 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3299 (match_operand:SI 1 "const_int_operand" "i")
3300 (match_operand:SI 2 "const_int_operand" "i"))
3301 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3302 (match_operand:SI 4 "const_int_operand" "i")))]
3303 "TARGET_POWERPC64
3304 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3305 "*
3306 {
3307 int shift = INTVAL (operands[4]) & 63;
3308 int start = (INTVAL (operands[2]) & 63) - 32;
3309 int size = INTVAL (operands[1]) & 63;
3311 operands[4] = GEN_INT (64 - shift - start - size);
3312 operands[2] = GEN_INT (start);
3313 operands[1] = GEN_INT (start + size - 1);
3314 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3315 }")
3317 (define_expand "extzv"
3318 [(set (match_operand 0 "gpc_reg_operand" "")
3319 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3320 (match_operand:SI 2 "const_int_operand" "")
3321 (match_operand:SI 3 "const_int_operand" "")))]
3322 ""
3323 "
3324 {
3325 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3326 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3327 compiler if the address of the structure is taken later. */
3328 if (GET_CODE (operands[0]) == SUBREG
3329 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3330 FAIL;
3332 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3333 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3334 operands[3]));
3335 else
3336 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3337 operands[3]));
3338 DONE;
3339 }")
3341 (define_insn "extzvsi_internal"
3342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3343 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3344 (match_operand:SI 2 "const_int_operand" "i")
3345 (match_operand:SI 3 "const_int_operand" "i")))]
3346 ""
3347 "*
3348 {
3349 int start = INTVAL (operands[3]) & 31;
3350 int size = INTVAL (operands[2]) & 31;
3352 if (start + size >= 32)
3353 operands[3] = const0_rtx;
3354 else
3355 operands[3] = GEN_INT (start + size);
3356 return \"rlwinm %0,%1,%3,%s2,31\";
3357 }"
3358 [(set_attr "type" "shift")])
3360 (define_insn "*extzvsi_internal1"
3361 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3362 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3363 (match_operand:SI 2 "const_int_operand" "i,i")
3364 (match_operand:SI 3 "const_int_operand" "i,i"))
3365 (const_int 0)))
3366 (clobber (match_scratch:SI 4 "=r,r"))]
3367 ""
3368 "*
3369 {
3370 int start = INTVAL (operands[3]) & 31;
3371 int size = INTVAL (operands[2]) & 31;
3373 /* Force split for non-cc0 compare. */
3374 if (which_alternative == 1)
3375 return \"#\";
3377 /* If the bit-field being tested fits in the upper or lower half of a
3378 word, it is possible to use andiu. or andil. to test it. This is
3379 useful because the condition register set-use delay is smaller for
3380 andi[ul]. than for rlinm. This doesn't work when the starting bit
3381 position is 0 because the LT and GT bits may be set wrong. */
3383 if ((start > 0 && start + size <= 16) || start >= 16)
3384 {
3385 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3386 - (1 << (16 - (start & 15) - size))));
3387 if (start < 16)
3388 return \"andis. %4,%1,%3\";
3389 else
3390 return \"andi. %4,%1,%3\";
3391 }
3393 if (start + size >= 32)
3394 operands[3] = const0_rtx;
3395 else
3396 operands[3] = GEN_INT (start + size);
3397 return \"rlwinm. %4,%1,%3,%s2,31\";
3398 }"
3399 [(set_attr "type" "shift")
3400 (set_attr "dot" "yes")
3401 (set_attr "length" "4,8")])
3403 (define_split
3404 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3405 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3406 (match_operand:SI 2 "const_int_operand" "")
3407 (match_operand:SI 3 "const_int_operand" ""))
3408 (const_int 0)))
3409 (clobber (match_scratch:SI 4 ""))]
3410 "reload_completed"
3411 [(set (match_dup 4)
3412 (zero_extract:SI (match_dup 1) (match_dup 2)
3413 (match_dup 3)))
3414 (set (match_dup 0)
3415 (compare:CC (match_dup 4)
3416 (const_int 0)))]
3417 "")
3419 (define_insn "*extzvsi_internal2"
3420 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3421 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3422 (match_operand:SI 2 "const_int_operand" "i,i")
3423 (match_operand:SI 3 "const_int_operand" "i,i"))
3424 (const_int 0)))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3426 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3427 ""
3428 "*
3429 {
3430 int start = INTVAL (operands[3]) & 31;
3431 int size = INTVAL (operands[2]) & 31;
3433 /* Force split for non-cc0 compare. */
3434 if (which_alternative == 1)
3435 return \"#\";
3437 /* Since we are using the output value, we can't ignore any need for
3438 a shift. The bit-field must end at the LSB. */
3439 if (start >= 16 && start + size == 32)
3440 {
3441 operands[3] = GEN_INT ((1 << size) - 1);
3442 return \"andi. %0,%1,%3\";
3443 }
3445 if (start + size >= 32)
3446 operands[3] = const0_rtx;
3447 else
3448 operands[3] = GEN_INT (start + size);
3449 return \"rlwinm. %0,%1,%3,%s2,31\";
3450 }"
3451 [(set_attr "type" "shift")
3452 (set_attr "dot" "yes")
3453 (set_attr "length" "4,8")])
3455 (define_split
3456 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3457 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3458 (match_operand:SI 2 "const_int_operand" "")
3459 (match_operand:SI 3 "const_int_operand" ""))
3460 (const_int 0)))
3461 (set (match_operand:SI 0 "gpc_reg_operand" "")
3462 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3463 "reload_completed"
3464 [(set (match_dup 0)
3465 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3466 (set (match_dup 4)
3467 (compare:CC (match_dup 0)
3468 (const_int 0)))]
3469 "")
3471 (define_insn "extzvdi_internal"
3472 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3473 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3474 (match_operand:SI 2 "const_int_operand" "i")
3475 (match_operand:SI 3 "const_int_operand" "i")))]
3476 "TARGET_POWERPC64"
3477 "*
3478 {
3479 int start = INTVAL (operands[3]) & 63;
3480 int size = INTVAL (operands[2]) & 63;
3482 if (start + size >= 64)
3483 operands[3] = const0_rtx;
3484 else
3485 operands[3] = GEN_INT (start + size);
3486 operands[2] = GEN_INT (64 - size);
3487 return \"rldicl %0,%1,%3,%2\";
3488 }"
3489 [(set_attr "type" "shift")])
3491 (define_insn "*extzvdi_internal1"
3492 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3493 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3494 (match_operand:SI 2 "const_int_operand" "i")
3495 (match_operand:SI 3 "const_int_operand" "i"))
3496 (const_int 0)))
3497 (clobber (match_scratch:DI 4 "=r"))]
3498 "TARGET_64BIT && rs6000_gen_cell_microcode"
3499 "*
3500 {
3501 int start = INTVAL (operands[3]) & 63;
3502 int size = INTVAL (operands[2]) & 63;
3504 if (start + size >= 64)
3505 operands[3] = const0_rtx;
3506 else
3507 operands[3] = GEN_INT (start + size);
3508 operands[2] = GEN_INT (64 - size);
3509 return \"rldicl. %4,%1,%3,%2\";
3510 }"
3511 [(set_attr "type" "shift")
3512 (set_attr "dot" "yes")])
3514 (define_insn "*extzvdi_internal2"
3515 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3516 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3517 (match_operand:SI 2 "const_int_operand" "i")
3518 (match_operand:SI 3 "const_int_operand" "i"))
3519 (const_int 0)))
3520 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3521 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3522 "TARGET_64BIT && rs6000_gen_cell_microcode"
3523 "*
3524 {
3525 int start = INTVAL (operands[3]) & 63;
3526 int size = INTVAL (operands[2]) & 63;
3528 if (start + size >= 64)
3529 operands[3] = const0_rtx;
3530 else
3531 operands[3] = GEN_INT (start + size);
3532 operands[2] = GEN_INT (64 - size);
3533 return \"rldicl. %0,%1,%3,%2\";
3534 }"
3535 [(set_attr "type" "shift")
3536 (set_attr "dot" "yes")])
3539 (define_insn "rotl<mode>3"
3540 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3541 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3542 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3543 ""
3544 "rotl<wd>%I2 %0,%1,%<hH>2"
3545 [(set_attr "type" "shift")
3546 (set_attr "maybe_var_shift" "yes")])
3548 (define_insn "*rotlsi3_64"
3549 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3550 (zero_extend:DI
3551 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3552 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3553 "TARGET_POWERPC64"
3554 "rotlw%I2 %0,%1,%h2"
3555 [(set_attr "type" "shift")
3556 (set_attr "maybe_var_shift" "yes")])
3558 (define_insn_and_split "*rotl<mode>3_dot"
3559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3560 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3561 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3562 (const_int 0)))
3563 (clobber (match_scratch:GPR 0 "=r,r"))]
3564 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3565 "@
3566 rotl<wd>%I2. %0,%1,%<hH>2
3567 #"
3568 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3569 [(set (match_dup 0)
3570 (rotate:GPR (match_dup 1)
3571 (match_dup 2)))
3572 (set (match_dup 3)
3573 (compare:CC (match_dup 0)
3574 (const_int 0)))]
3575 ""
3576 [(set_attr "type" "shift")
3577 (set_attr "maybe_var_shift" "yes")
3578 (set_attr "dot" "yes")
3579 (set_attr "length" "4,8")])
3581 (define_insn_and_split "*rotl<mode>3_dot2"
3582 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3583 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3584 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3585 (const_int 0)))
3586 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3587 (rotate:GPR (match_dup 1)
3588 (match_dup 2)))]
3589 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3590 "@
3591 rotl<wd>%I2. %0,%1,%<hH>2
3592 #"
3593 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3594 [(set (match_dup 0)
3595 (rotate:GPR (match_dup 1)
3596 (match_dup 2)))
3597 (set (match_dup 3)
3598 (compare:CC (match_dup 0)
3599 (const_int 0)))]
3600 ""
3601 [(set_attr "type" "shift")
3602 (set_attr "maybe_var_shift" "yes")
3603 (set_attr "dot" "yes")
3604 (set_attr "length" "4,8")])
3607 (define_insn "*rotlsi3_internal4"
3608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3609 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3610 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3611 (match_operand:SI 3 "mask_operand" "n")))]
3612 ""
3613 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3614 [(set_attr "type" "shift")
3615 (set_attr "maybe_var_shift" "yes")])
3617 (define_insn "*rotlsi3_internal5"
3618 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3619 (compare:CC (and:SI
3620 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3621 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3622 (match_operand:SI 3 "mask_operand" "n,n"))
3623 (const_int 0)))
3624 (clobber (match_scratch:SI 4 "=r,r"))]
3625 ""
3626 "@
3627 rlw%I2nm. %4,%1,%h2,%m3,%M3
3628 #"
3629 [(set_attr "type" "shift")
3630 (set_attr "maybe_var_shift" "yes")
3631 (set_attr "dot" "yes")
3632 (set_attr "length" "4,8")])
3634 (define_split
3635 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3636 (compare:CC (and:SI
3637 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3639 (match_operand:SI 3 "mask_operand" ""))
3640 (const_int 0)))
3641 (clobber (match_scratch:SI 4 ""))]
3642 "reload_completed"
3643 [(set (match_dup 4)
3644 (and:SI (rotate:SI (match_dup 1)
3645 (match_dup 2))
3646 (match_dup 3)))
3647 (set (match_dup 0)
3648 (compare:CC (match_dup 4)
3649 (const_int 0)))]
3650 "")
3652 (define_insn "*rotlsi3_internal6"
3653 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3654 (compare:CC (and:SI
3655 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3656 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3657 (match_operand:SI 3 "mask_operand" "n,n"))
3658 (const_int 0)))
3659 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3660 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3661 ""
3662 "@
3663 rlw%I2nm. %0,%1,%h2,%m3,%M3
3664 #"
3665 [(set_attr "type" "shift")
3666 (set_attr "maybe_var_shift" "yes")
3667 (set_attr "dot" "yes")
3668 (set_attr "length" "4,8")])
3670 (define_split
3671 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3672 (compare:CC (and:SI
3673 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3674 (match_operand:SI 2 "reg_or_cint_operand" ""))
3675 (match_operand:SI 3 "mask_operand" ""))
3676 (const_int 0)))
3677 (set (match_operand:SI 0 "gpc_reg_operand" "")
3678 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3679 "reload_completed"
3680 [(set (match_dup 0)
3681 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3682 (set (match_dup 4)
3683 (compare:CC (match_dup 0)
3684 (const_int 0)))]
3685 "")
3687 (define_insn "*rotlsi3_internal7le"
3688 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3689 (zero_extend:SI
3690 (subreg:QI
3691 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3692 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3693 "!BYTES_BIG_ENDIAN"
3694 "rlw%I2nm %0,%1,%h2,0xff"
3695 [(set (attr "cell_micro")
3696 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3697 (const_string "not")
3698 (const_string "always")))
3699 (set_attr "type" "shift")])
3701 (define_insn "*rotlsi3_internal7be"
3702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3703 (zero_extend:SI
3704 (subreg:QI
3705 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3706 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3707 "BYTES_BIG_ENDIAN"
3708 "rlw%I2nm %0,%1,%h2,0xff"
3709 [(set (attr "cell_micro")
3710 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3711 (const_string "not")
3712 (const_string "always")))
3713 (set_attr "type" "shift")])
3715 (define_insn "*rotlsi3_internal8le"
3716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3717 (compare:CC (zero_extend:SI
3718 (subreg:QI
3719 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3720 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3721 (const_int 0)))
3722 (clobber (match_scratch:SI 3 "=r,r"))]
3723 "!BYTES_BIG_ENDIAN"
3724 "@
3725 rlw%I2nm. %3,%1,%h2,0xff
3726 #"
3727 [(set_attr "type" "shift")
3728 (set_attr "maybe_var_shift" "yes")
3729 (set_attr "dot" "yes")
3730 (set_attr "length" "4,8")])
3732 (define_insn "*rotlsi3_internal8be"
3733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3734 (compare:CC (zero_extend:SI
3735 (subreg:QI
3736 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3737 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3738 (const_int 0)))
3739 (clobber (match_scratch:SI 3 "=r,r"))]
3740 "BYTES_BIG_ENDIAN"
3741 "@
3742 rlw%I2nm. %3,%1,%h2,0xff
3743 #"
3744 [(set_attr "type" "shift")
3745 (set_attr "maybe_var_shift" "yes")
3746 (set_attr "dot" "yes")
3747 (set_attr "length" "4,8")])
3749 (define_split
3750 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3751 (compare:CC (zero_extend:SI
3752 (subreg:QI
3753 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3754 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3755 (const_int 0)))
3756 (clobber (match_scratch:SI 3 ""))]
3757 "!BYTES_BIG_ENDIAN && reload_completed"
3758 [(set (match_dup 3)
3759 (zero_extend:SI (subreg:QI
3760 (rotate:SI (match_dup 1)
3761 (match_dup 2)) 0)))
3762 (set (match_dup 0)
3763 (compare:CC (match_dup 3)
3764 (const_int 0)))]
3765 "")
3767 (define_split
3768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3769 (compare:CC (zero_extend:SI
3770 (subreg:QI
3771 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3773 (const_int 0)))
3774 (clobber (match_scratch:SI 3 ""))]
3775 "BYTES_BIG_ENDIAN && reload_completed"
3776 [(set (match_dup 3)
3777 (zero_extend:SI (subreg:QI
3778 (rotate:SI (match_dup 1)
3779 (match_dup 2)) 3)))
3780 (set (match_dup 0)
3781 (compare:CC (match_dup 3)
3782 (const_int 0)))]
3783 "")
3785 (define_insn "*rotlsi3_internal9le"
3786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3787 (compare:CC (zero_extend:SI
3788 (subreg:QI
3789 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3790 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3791 (const_int 0)))
3792 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3793 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3794 "!BYTES_BIG_ENDIAN"
3795 "@
3796 rlw%I2nm. %0,%1,%h2,0xff
3797 #"
3798 [(set_attr "type" "shift")
3799 (set_attr "maybe_var_shift" "yes")
3800 (set_attr "dot" "yes")
3801 (set_attr "length" "4,8")])
3803 (define_insn "*rotlsi3_internal9be"
3804 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3805 (compare:CC (zero_extend:SI
3806 (subreg:QI
3807 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3808 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3809 (const_int 0)))
3810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3811 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3812 "BYTES_BIG_ENDIAN"
3813 "@
3814 rlw%I2nm. %0,%1,%h2,0xff
3815 #"
3816 [(set_attr "type" "shift")
3817 (set_attr "maybe_var_shift" "yes")
3818 (set_attr "dot" "yes")
3819 (set_attr "length" "4,8")])
3821 (define_split
3822 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3823 (compare:CC (zero_extend:SI
3824 (subreg:QI
3825 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3826 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3827 (const_int 0)))
3828 (set (match_operand:SI 0 "gpc_reg_operand" "")
3829 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3830 "!BYTES_BIG_ENDIAN && reload_completed"
3831 [(set (match_dup 0)
3832 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3833 (set (match_dup 3)
3834 (compare:CC (match_dup 0)
3835 (const_int 0)))]
3836 "")
3838 (define_split
3839 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3840 (compare:CC (zero_extend:SI
3841 (subreg:QI
3842 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3843 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3844 (const_int 0)))
3845 (set (match_operand:SI 0 "gpc_reg_operand" "")
3846 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3847 "BYTES_BIG_ENDIAN && reload_completed"
3848 [(set (match_dup 0)
3849 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3850 (set (match_dup 3)
3851 (compare:CC (match_dup 0)
3852 (const_int 0)))]
3853 "")
3855 (define_insn "*rotlsi3_internal10le"
3856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3857 (zero_extend:SI
3858 (subreg:HI
3859 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3860 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3861 "!BYTES_BIG_ENDIAN"
3862 "rlw%I2nm %0,%1,%h2,0xffff"
3863 [(set_attr "type" "shift")
3864 (set_attr "maybe_var_shift" "yes")])
3866 (define_insn "*rotlsi3_internal10be"
3867 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3868 (zero_extend:SI
3869 (subreg:HI
3870 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3871 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3872 "BYTES_BIG_ENDIAN"
3873 "rlw%I2nm %0,%1,%h2,0xffff"
3874 [(set_attr "type" "shift")
3875 (set_attr "maybe_var_shift" "yes")])
3877 (define_insn "*rotlsi3_internal11le"
3878 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3879 (compare:CC (zero_extend:SI
3880 (subreg:HI
3881 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3882 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3883 (const_int 0)))
3884 (clobber (match_scratch:SI 3 "=r,r"))]
3885 "!BYTES_BIG_ENDIAN"
3886 "@
3887 rlw%I2nm. %3,%1,%h2,0xffff
3888 #"
3889 [(set_attr "type" "shift")
3890 (set_attr "maybe_var_shift" "yes")
3891 (set_attr "dot" "yes")
3892 (set_attr "length" "4,8")])
3894 (define_insn "*rotlsi3_internal11be"
3895 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3896 (compare:CC (zero_extend:SI
3897 (subreg:HI
3898 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3899 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3900 (const_int 0)))
3901 (clobber (match_scratch:SI 3 "=r,r"))]
3902 "BYTES_BIG_ENDIAN"
3903 "@
3904 rlw%I2nm. %3,%1,%h2,0xffff
3905 #"
3906 [(set_attr "type" "shift")
3907 (set_attr "maybe_var_shift" "yes")
3908 (set_attr "dot" "yes")
3909 (set_attr "length" "4,8")])
3911 (define_split
3912 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3913 (compare:CC (zero_extend:SI
3914 (subreg:HI
3915 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3916 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3917 (const_int 0)))
3918 (clobber (match_scratch:SI 3 ""))]
3919 "!BYTES_BIG_ENDIAN && reload_completed"
3920 [(set (match_dup 3)
3921 (zero_extend:SI (subreg:HI
3922 (rotate:SI (match_dup 1)
3923 (match_dup 2)) 0)))
3924 (set (match_dup 0)
3925 (compare:CC (match_dup 3)
3926 (const_int 0)))]
3927 "")
3929 (define_split
3930 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3931 (compare:CC (zero_extend:SI
3932 (subreg:HI
3933 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3934 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
3935 (const_int 0)))
3936 (clobber (match_scratch:SI 3 ""))]
3937 "BYTES_BIG_ENDIAN && reload_completed"
3938 [(set (match_dup 3)
3939 (zero_extend:SI (subreg:HI
3940 (rotate:SI (match_dup 1)
3941 (match_dup 2)) 2)))
3942 (set (match_dup 0)
3943 (compare:CC (match_dup 3)
3944 (const_int 0)))]
3945 "")
3947 (define_insn "*rotlsi3_internal12le"
3948 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3949 (compare:CC (zero_extend:SI
3950 (subreg:HI
3951 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3952 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3953 (const_int 0)))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3955 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3956 "!BYTES_BIG_ENDIAN"
3957 "@
3958 rlw%I2nm. %0,%1,%h2,0xffff
3959 #"
3960 [(set_attr "type" "shift")
3961 (set_attr "maybe_var_shift" "yes")
3962 (set_attr "dot" "yes")
3963 (set_attr "length" "4,8")])
3965 (define_insn "*rotlsi3_internal12be"
3966 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3967 (compare:CC (zero_extend:SI
3968 (subreg:HI
3969 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3970 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3971 (const_int 0)))
3972 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3973 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
3974 "BYTES_BIG_ENDIAN"
3975 "@
3976 rlw%I2nm. %0,%1,%h2,0xffff
3977 #"
3978 [(set_attr "type" "shift")
3979 (set_attr "maybe_var_shift" "yes")
3980 (set_attr "dot" "yes")
3981 (set_attr "length" "4,8")])
3983 (define_split
3984 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3985 (compare:CC (zero_extend:SI
3986 (subreg:HI
3987 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3988 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3989 (const_int 0)))
3990 (set (match_operand:SI 0 "gpc_reg_operand" "")
3991 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3992 "!BYTES_BIG_ENDIAN && reload_completed"
3993 [(set (match_dup 0)
3994 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3995 (set (match_dup 3)
3996 (compare:CC (match_dup 0)
3997 (const_int 0)))]
3998 "")
4000 (define_split
4001 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4002 (compare:CC (zero_extend:SI
4003 (subreg:HI
4004 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4005 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4006 (const_int 0)))
4007 (set (match_operand:SI 0 "gpc_reg_operand" "")
4008 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4009 "BYTES_BIG_ENDIAN && reload_completed"
4010 [(set (match_dup 0)
4011 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4012 (set (match_dup 3)
4013 (compare:CC (match_dup 0)
4014 (const_int 0)))]
4015 "")
4018 (define_insn "ashl<mode>3"
4019 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4020 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4021 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4022 ""
4023 "sl<wd>%I2 %0,%1,%<hH>2"
4024 [(set_attr "type" "shift")
4025 (set_attr "maybe_var_shift" "yes")])
4027 (define_insn "*ashlsi3_64"
4028 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4029 (zero_extend:DI
4030 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4031 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4032 "TARGET_POWERPC64"
4033 "slw%I2 %0,%1,%h2"
4034 [(set_attr "type" "shift")
4035 (set_attr "maybe_var_shift" "yes")])
4037 (define_insn_and_split "*ashl<mode>3_dot"
4038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4039 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4040 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4041 (const_int 0)))
4042 (clobber (match_scratch:GPR 0 "=r,r"))]
4043 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4044 "@
4045 sl<wd>%I2. %0,%1,%<hH>2
4046 #"
4047 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4048 [(set (match_dup 0)
4049 (ashift:GPR (match_dup 1)
4050 (match_dup 2)))
4051 (set (match_dup 3)
4052 (compare:CC (match_dup 0)
4053 (const_int 0)))]
4054 ""
4055 [(set_attr "type" "shift")
4056 (set_attr "maybe_var_shift" "yes")
4057 (set_attr "dot" "yes")
4058 (set_attr "length" "4,8")])
4060 (define_insn_and_split "*ashl<mode>3_dot2"
4061 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4062 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4063 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4064 (const_int 0)))
4065 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4066 (ashift:GPR (match_dup 1)
4067 (match_dup 2)))]
4068 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4069 "@
4070 sl<wd>%I2. %0,%1,%<hH>2
4071 #"
4072 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4073 [(set (match_dup 0)
4074 (ashift:GPR (match_dup 1)
4075 (match_dup 2)))
4076 (set (match_dup 3)
4077 (compare:CC (match_dup 0)
4078 (const_int 0)))]
4079 ""
4080 [(set_attr "type" "shift")
4081 (set_attr "maybe_var_shift" "yes")
4082 (set_attr "dot" "yes")
4083 (set_attr "length" "4,8")])
4086 (define_insn "rlwinm"
4087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4088 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4089 (match_operand:SI 2 "const_int_operand" "i"))
4090 (match_operand:SI 3 "mask_operand" "n")))]
4091 "includes_lshift_p (operands[2], operands[3])"
4092 "rlwinm %0,%1,%h2,%m3,%M3"
4093 [(set_attr "type" "shift")])
4095 (define_insn ""
4096 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4097 (compare:CC
4098 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4099 (match_operand:SI 2 "const_int_operand" "i,i"))
4100 (match_operand:SI 3 "mask_operand" "n,n"))
4101 (const_int 0)))
4102 (clobber (match_scratch:SI 4 "=r,r"))]
4103 "includes_lshift_p (operands[2], operands[3])"
4104 "@
4105 rlwinm. %4,%1,%h2,%m3,%M3
4106 #"
4107 [(set_attr "type" "shift")
4108 (set_attr "dot" "yes")
4109 (set_attr "length" "4,8")])
4111 (define_split
4112 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4113 (compare:CC
4114 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4115 (match_operand:SI 2 "const_int_operand" ""))
4116 (match_operand:SI 3 "mask_operand" ""))
4117 (const_int 0)))
4118 (clobber (match_scratch:SI 4 ""))]
4119 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4120 [(set (match_dup 4)
4121 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4122 (match_dup 3)))
4123 (set (match_dup 0)
4124 (compare:CC (match_dup 4)
4125 (const_int 0)))]
4126 "")
4128 (define_insn ""
4129 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4130 (compare:CC
4131 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4132 (match_operand:SI 2 "const_int_operand" "i,i"))
4133 (match_operand:SI 3 "mask_operand" "n,n"))
4134 (const_int 0)))
4135 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4136 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4137 "includes_lshift_p (operands[2], operands[3])"
4138 "@
4139 rlwinm. %0,%1,%h2,%m3,%M3
4140 #"
4141 [(set_attr "type" "shift")
4142 (set_attr "dot" "yes")
4143 (set_attr "length" "4,8")])
4145 (define_split
4146 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4147 (compare:CC
4148 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4149 (match_operand:SI 2 "const_int_operand" ""))
4150 (match_operand:SI 3 "mask_operand" ""))
4151 (const_int 0)))
4152 (set (match_operand:SI 0 "gpc_reg_operand" "")
4153 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4154 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4155 [(set (match_dup 0)
4156 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4157 (set (match_dup 4)
4158 (compare:CC (match_dup 0)
4159 (const_int 0)))]
4160 "")
4163 (define_insn "lshr<mode>3"
4164 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4165 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4166 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4167 ""
4168 "sr<wd>%I2 %0,%1,%<hH>2"
4169 [(set_attr "type" "shift")
4170 (set_attr "maybe_var_shift" "yes")])
4172 (define_insn "*lshrsi3_64"
4173 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4174 (zero_extend:DI
4175 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4176 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4177 "TARGET_POWERPC64"
4178 "srw%I2 %0,%1,%h2"
4179 [(set_attr "type" "shift")
4180 (set_attr "maybe_var_shift" "yes")])
4182 (define_insn_and_split "*lshr<mode>3_dot"
4183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4184 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4185 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4186 (const_int 0)))
4187 (clobber (match_scratch:GPR 0 "=r,r"))]
4188 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4189 "@
4190 sr<wd>%I2. %0,%1,%<hH>2
4191 #"
4192 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4193 [(set (match_dup 0)
4194 (lshiftrt:GPR (match_dup 1)
4195 (match_dup 2)))
4196 (set (match_dup 3)
4197 (compare:CC (match_dup 0)
4198 (const_int 0)))]
4199 ""
4200 [(set_attr "type" "shift")
4201 (set_attr "maybe_var_shift" "yes")
4202 (set_attr "dot" "yes")
4203 (set_attr "length" "4,8")])
4205 (define_insn_and_split "*lshr<mode>3_dot2"
4206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4207 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4208 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4209 (const_int 0)))
4210 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4211 (lshiftrt:GPR (match_dup 1)
4212 (match_dup 2)))]
4213 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4214 "@
4215 sr<wd>%I2. %0,%1,%<hH>2
4216 #"
4217 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4218 [(set (match_dup 0)
4219 (lshiftrt:GPR (match_dup 1)
4220 (match_dup 2)))
4221 (set (match_dup 3)
4222 (compare:CC (match_dup 0)
4223 (const_int 0)))]
4224 ""
4225 [(set_attr "type" "shift")
4226 (set_attr "maybe_var_shift" "yes")
4227 (set_attr "dot" "yes")
4228 (set_attr "length" "4,8")])
4231 (define_insn ""
4232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4233 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4234 (match_operand:SI 2 "const_int_operand" "i"))
4235 (match_operand:SI 3 "mask_operand" "n")))]
4236 "includes_rshift_p (operands[2], operands[3])"
4237 "rlwinm %0,%1,%s2,%m3,%M3"
4238 [(set_attr "type" "shift")])
4240 (define_insn ""
4241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4242 (compare:CC
4243 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4244 (match_operand:SI 2 "const_int_operand" "i,i"))
4245 (match_operand:SI 3 "mask_operand" "n,n"))
4246 (const_int 0)))
4247 (clobber (match_scratch:SI 4 "=r,r"))]
4248 "includes_rshift_p (operands[2], operands[3])"
4249 "@
4250 rlwinm. %4,%1,%s2,%m3,%M3
4251 #"
4252 [(set_attr "type" "shift")
4253 (set_attr "dot" "yes")
4254 (set_attr "length" "4,8")])
4256 (define_split
4257 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4258 (compare:CC
4259 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4260 (match_operand:SI 2 "const_int_operand" ""))
4261 (match_operand:SI 3 "mask_operand" ""))
4262 (const_int 0)))
4263 (clobber (match_scratch:SI 4 ""))]
4264 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4265 [(set (match_dup 4)
4266 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4267 (match_dup 3)))
4268 (set (match_dup 0)
4269 (compare:CC (match_dup 4)
4270 (const_int 0)))]
4271 "")
4273 (define_insn ""
4274 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4275 (compare:CC
4276 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4277 (match_operand:SI 2 "const_int_operand" "i,i"))
4278 (match_operand:SI 3 "mask_operand" "n,n"))
4279 (const_int 0)))
4280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4281 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4282 "includes_rshift_p (operands[2], operands[3])"
4283 "@
4284 rlwinm. %0,%1,%s2,%m3,%M3
4285 #"
4286 [(set_attr "type" "shift")
4287 (set_attr "dot" "yes")
4288 (set_attr "length" "4,8")])
4290 (define_split
4291 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4292 (compare:CC
4293 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4294 (match_operand:SI 2 "const_int_operand" ""))
4295 (match_operand:SI 3 "mask_operand" ""))
4296 (const_int 0)))
4297 (set (match_operand:SI 0 "gpc_reg_operand" "")
4298 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4299 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4300 [(set (match_dup 0)
4301 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4302 (set (match_dup 4)
4303 (compare:CC (match_dup 0)
4304 (const_int 0)))]
4305 "")
4307 (define_insn "*lshiftrt_internal1le"
4308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4309 (zero_extend:SI
4310 (subreg:QI
4311 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4312 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4313 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4314 "rlwinm %0,%1,%s2,0xff"
4315 [(set_attr "type" "shift")])
4317 (define_insn "*lshiftrt_internal1be"
4318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4319 (zero_extend:SI
4320 (subreg:QI
4321 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4322 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4323 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4324 "rlwinm %0,%1,%s2,0xff"
4325 [(set_attr "type" "shift")])
4327 (define_insn "*lshiftrt_internal2le"
4328 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4329 (compare:CC
4330 (zero_extend:SI
4331 (subreg:QI
4332 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4333 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4334 (const_int 0)))
4335 (clobber (match_scratch:SI 3 "=r,r"))]
4336 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4337 "@
4338 rlwinm. %3,%1,%s2,0xff
4339 #"
4340 [(set_attr "type" "shift")
4341 (set_attr "dot" "yes")
4342 (set_attr "length" "4,8")])
4344 (define_insn "*lshiftrt_internal2be"
4345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4346 (compare:CC
4347 (zero_extend:SI
4348 (subreg:QI
4349 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4350 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4351 (const_int 0)))
4352 (clobber (match_scratch:SI 3 "=r,r"))]
4353 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4354 "@
4355 rlwinm. %3,%1,%s2,0xff
4356 #"
4357 [(set_attr "type" "shift")
4358 (set_attr "dot" "yes")
4359 (set_attr "length" "4,8")])
4361 (define_split
4362 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4363 (compare:CC
4364 (zero_extend:SI
4365 (subreg:QI
4366 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4367 (match_operand:SI 2 "const_int_operand" "")) 0))
4368 (const_int 0)))
4369 (clobber (match_scratch:SI 3 ""))]
4370 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4371 [(set (match_dup 3)
4372 (zero_extend:SI (subreg:QI
4373 (lshiftrt:SI (match_dup 1)
4374 (match_dup 2)) 0)))
4375 (set (match_dup 0)
4376 (compare:CC (match_dup 3)
4377 (const_int 0)))]
4378 "")
4380 (define_split
4381 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4382 (compare:CC
4383 (zero_extend:SI
4384 (subreg:QI
4385 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4386 (match_operand:SI 2 "const_int_operand" "")) 3))
4387 (const_int 0)))
4388 (clobber (match_scratch:SI 3 ""))]
4389 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4390 [(set (match_dup 3)
4391 (zero_extend:SI (subreg:QI
4392 (lshiftrt:SI (match_dup 1)
4393 (match_dup 2)) 3)))
4394 (set (match_dup 0)
4395 (compare:CC (match_dup 3)
4396 (const_int 0)))]
4397 "")
4399 (define_insn "*lshiftrt_internal3le"
4400 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4401 (compare:CC
4402 (zero_extend:SI
4403 (subreg:QI
4404 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4405 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4406 (const_int 0)))
4407 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4408 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4409 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4410 "@
4411 rlwinm. %0,%1,%s2,0xff
4412 #"
4413 [(set_attr "type" "shift")
4414 (set_attr "dot" "yes")
4415 (set_attr "length" "4,8")])
4417 (define_insn "*lshiftrt_internal3be"
4418 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4419 (compare:CC
4420 (zero_extend:SI
4421 (subreg:QI
4422 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4423 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4424 (const_int 0)))
4425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4426 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4427 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4428 "@
4429 rlwinm. %0,%1,%s2,0xff
4430 #"
4431 [(set_attr "type" "shift")
4432 (set_attr "dot" "yes")
4433 (set_attr "length" "4,8")])
4435 (define_split
4436 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4437 (compare:CC
4438 (zero_extend:SI
4439 (subreg:QI
4440 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4441 (match_operand:SI 2 "const_int_operand" "")) 0))
4442 (const_int 0)))
4443 (set (match_operand:SI 0 "gpc_reg_operand" "")
4444 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4445 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4446 [(set (match_dup 0)
4447 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4448 (set (match_dup 3)
4449 (compare:CC (match_dup 0)
4450 (const_int 0)))]
4451 "")
4453 (define_split
4454 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4455 (compare:CC
4456 (zero_extend:SI
4457 (subreg:QI
4458 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4459 (match_operand:SI 2 "const_int_operand" "")) 3))
4460 (const_int 0)))
4461 (set (match_operand:SI 0 "gpc_reg_operand" "")
4462 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4463 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4464 [(set (match_dup 0)
4465 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4466 (set (match_dup 3)
4467 (compare:CC (match_dup 0)
4468 (const_int 0)))]
4469 "")
4471 (define_insn "*lshiftrt_internal4le"
4472 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4473 (zero_extend:SI
4474 (subreg:HI
4475 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4476 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4477 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4478 "rlwinm %0,%1,%s2,0xffff"
4479 [(set_attr "type" "shift")])
4481 (define_insn "*lshiftrt_internal4be"
4482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4483 (zero_extend:SI
4484 (subreg:HI
4485 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4486 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4487 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4488 "rlwinm %0,%1,%s2,0xffff"
4489 [(set_attr "type" "shift")])
4491 (define_insn "*lshiftrt_internal5le"
4492 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4493 (compare:CC
4494 (zero_extend:SI
4495 (subreg:HI
4496 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4497 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4498 (const_int 0)))
4499 (clobber (match_scratch:SI 3 "=r,r"))]
4500 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4501 "@
4502 rlwinm. %3,%1,%s2,0xffff
4503 #"
4504 [(set_attr "type" "shift")
4505 (set_attr "dot" "yes")
4506 (set_attr "length" "4,8")])
4508 (define_insn "*lshiftrt_internal5be"
4509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4510 (compare:CC
4511 (zero_extend:SI
4512 (subreg:HI
4513 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4514 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4515 (const_int 0)))
4516 (clobber (match_scratch:SI 3 "=r,r"))]
4517 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4518 "@
4519 rlwinm. %3,%1,%s2,0xffff
4520 #"
4521 [(set_attr "type" "shift")
4522 (set_attr "dot" "yes")
4523 (set_attr "length" "4,8")])
4525 (define_split
4526 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4527 (compare:CC
4528 (zero_extend:SI
4529 (subreg:HI
4530 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4531 (match_operand:SI 2 "const_int_operand" "")) 0))
4532 (const_int 0)))
4533 (clobber (match_scratch:SI 3 ""))]
4534 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4535 [(set (match_dup 3)
4536 (zero_extend:SI (subreg:HI
4537 (lshiftrt:SI (match_dup 1)
4538 (match_dup 2)) 0)))
4539 (set (match_dup 0)
4540 (compare:CC (match_dup 3)
4541 (const_int 0)))]
4542 "")
4544 (define_split
4545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4546 (compare:CC
4547 (zero_extend:SI
4548 (subreg:HI
4549 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4550 (match_operand:SI 2 "const_int_operand" "")) 2))
4551 (const_int 0)))
4552 (clobber (match_scratch:SI 3 ""))]
4553 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4554 [(set (match_dup 3)
4555 (zero_extend:SI (subreg:HI
4556 (lshiftrt:SI (match_dup 1)
4557 (match_dup 2)) 2)))
4558 (set (match_dup 0)
4559 (compare:CC (match_dup 3)
4560 (const_int 0)))]
4561 "")
4563 (define_insn "*lshiftrt_internal5le"
4564 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4565 (compare:CC
4566 (zero_extend:SI
4567 (subreg:HI
4568 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4569 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4570 (const_int 0)))
4571 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4572 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4573 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4574 "@
4575 rlwinm. %0,%1,%s2,0xffff
4576 #"
4577 [(set_attr "type" "shift")
4578 (set_attr "dot" "yes")
4579 (set_attr "length" "4,8")])
4581 (define_insn "*lshiftrt_internal5be"
4582 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4583 (compare:CC
4584 (zero_extend:SI
4585 (subreg:HI
4586 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4587 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4588 (const_int 0)))
4589 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4590 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4591 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4592 "@
4593 rlwinm. %0,%1,%s2,0xffff
4594 #"
4595 [(set_attr "type" "shift")
4596 (set_attr "dot" "yes")
4597 (set_attr "length" "4,8")])
4599 (define_split
4600 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4601 (compare:CC
4602 (zero_extend:SI
4603 (subreg:HI
4604 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4605 (match_operand:SI 2 "const_int_operand" "")) 0))
4606 (const_int 0)))
4607 (set (match_operand:SI 0 "gpc_reg_operand" "")
4608 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4609 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4610 [(set (match_dup 0)
4611 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4612 (set (match_dup 3)
4613 (compare:CC (match_dup 0)
4614 (const_int 0)))]
4615 "")
4617 (define_split
4618 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4619 (compare:CC
4620 (zero_extend:SI
4621 (subreg:HI
4622 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4623 (match_operand:SI 2 "const_int_operand" "")) 2))
4624 (const_int 0)))
4625 (set (match_operand:SI 0 "gpc_reg_operand" "")
4626 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4627 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4628 [(set (match_dup 0)
4629 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4630 (set (match_dup 3)
4631 (compare:CC (match_dup 0)
4632 (const_int 0)))]
4633 "")
4636 (define_expand "ashr<mode>3"
4637 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4638 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4639 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4640 ""
4641 {
4642 /* The generic code does not generate optimal code for the low word
4643 (it should be a rlwimi and a rot). Until we have target code to
4644 solve this generically, keep this expander. */
4646 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4647 {
4648 if (CONST_INT_P (operands[2]))
4649 {
4650 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4651 DONE;
4652 }
4653 else
4654 FAIL;
4655 }
4656 })
4658 (define_insn "*ashr<mode>3"
4659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4660 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4661 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4662 ""
4663 "sra<wd>%I2 %0,%1,%<hH>2"
4664 [(set_attr "type" "shift")
4665 (set_attr "maybe_var_shift" "yes")])
4667 (define_insn "*ashrsi3_64"
4668 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4669 (sign_extend:DI
4670 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4671 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4672 "TARGET_POWERPC64"
4673 "sraw%I2 %0,%1,%h2"
4674 [(set_attr "type" "shift")
4675 (set_attr "maybe_var_shift" "yes")])
4677 (define_insn_and_split "*ashr<mode>3_dot"
4678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4679 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4680 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4681 (const_int 0)))
4682 (clobber (match_scratch:GPR 0 "=r,r"))]
4683 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4684 "@
4685 sra<wd>%I2. %0,%1,%<hH>2
4686 #"
4687 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4688 [(set (match_dup 0)
4689 (ashiftrt:GPR (match_dup 1)
4690 (match_dup 2)))
4691 (set (match_dup 3)
4692 (compare:CC (match_dup 0)
4693 (const_int 0)))]
4694 ""
4695 [(set_attr "type" "shift")
4696 (set_attr "maybe_var_shift" "yes")
4697 (set_attr "dot" "yes")
4698 (set_attr "length" "4,8")])
4700 (define_insn_and_split "*ashr<mode>3_dot2"
4701 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4702 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4703 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4704 (const_int 0)))
4705 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4706 (ashiftrt:GPR (match_dup 1)
4707 (match_dup 2)))]
4708 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4709 "@
4710 sra<wd>%I2. %0,%1,%<hH>2
4711 #"
4712 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4713 [(set (match_dup 0)
4714 (ashiftrt:GPR (match_dup 1)
4715 (match_dup 2)))
4716 (set (match_dup 3)
4717 (compare:CC (match_dup 0)
4718 (const_int 0)))]
4719 ""
4720 [(set_attr "type" "shift")
4721 (set_attr "maybe_var_shift" "yes")
4722 (set_attr "dot" "yes")
4723 (set_attr "length" "4,8")])
4724 \f
4725 ;; Builtins to replace a division to generate FRE reciprocal estimate
4726 ;; instructions and the necessary fixup instructions
4727 (define_expand "recip<mode>3"
4728 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4729 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4730 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4731 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4732 {
4733 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4734 DONE;
4735 })
4737 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4738 ;; hardware division. This is only done before register allocation and with
4739 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4740 (define_split
4741 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4742 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4743 (match_operand 2 "gpc_reg_operand" "")))]
4744 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4745 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4746 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4747 [(const_int 0)]
4748 {
4749 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4750 DONE;
4751 })
4753 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4754 ;; appropriate fixup.
4755 (define_expand "rsqrt<mode>2"
4756 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4757 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4758 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4759 {
4760 rs6000_emit_swrsqrt (operands[0], operands[1]);
4761 DONE;
4762 })
4763 \f
4764 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4765 ;; modes here, and also add in conditional vsx/power8-vector support to access
4766 ;; values in the traditional Altivec registers if the appropriate
4767 ;; -mupper-regs-{df,sf} option is enabled.
4769 (define_expand "abs<mode>2"
4770 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4771 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4772 "TARGET_<MODE>_INSN"
4773 "")
4775 (define_insn "*abs<mode>2_fpr"
4776 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4777 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4778 "TARGET_<MODE>_FPR"
4779 "@
4780 fabs %0,%1
4781 xsabsdp %x0,%x1"
4782 [(set_attr "type" "fp")
4783 (set_attr "fp_type" "fp_addsub_<Fs>")])
4785 (define_insn "*nabs<mode>2_fpr"
4786 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4787 (neg:SFDF
4788 (abs:SFDF
4789 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4790 "TARGET_<MODE>_FPR"
4791 "@
4792 fnabs %0,%1
4793 xsnabsdp %x0,%x1"
4794 [(set_attr "type" "fp")
4795 (set_attr "fp_type" "fp_addsub_<Fs>")])
4797 (define_expand "neg<mode>2"
4798 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4799 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4800 "TARGET_<MODE>_INSN"
4801 "")
4803 (define_insn "*neg<mode>2_fpr"
4804 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4805 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4806 "TARGET_<MODE>_FPR"
4807 "@
4808 fneg %0,%1
4809 xsnegdp %x0,%x1"
4810 [(set_attr "type" "fp")
4811 (set_attr "fp_type" "fp_addsub_<Fs>")])
4813 (define_expand "add<mode>3"
4814 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4815 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4816 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4817 "TARGET_<MODE>_INSN"
4818 "")
4820 (define_insn "*add<mode>3_fpr"
4821 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4822 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4823 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4824 "TARGET_<MODE>_FPR"
4825 "@
4826 fadd<Ftrad> %0,%1,%2
4827 xsadd<Fvsx> %x0,%x1,%x2"
4828 [(set_attr "type" "fp")
4829 (set_attr "fp_type" "fp_addsub_<Fs>")])
4831 (define_expand "sub<mode>3"
4832 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4833 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4834 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4835 "TARGET_<MODE>_INSN"
4836 "")
4838 (define_insn "*sub<mode>3_fpr"
4839 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4840 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4841 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4842 "TARGET_<MODE>_FPR"
4843 "@
4844 fsub<Ftrad> %0,%1,%2
4845 xssub<Fvsx> %x0,%x1,%x2"
4846 [(set_attr "type" "fp")
4847 (set_attr "fp_type" "fp_addsub_<Fs>")])
4849 (define_expand "mul<mode>3"
4850 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4851 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4852 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4853 "TARGET_<MODE>_INSN"
4854 "")
4856 (define_insn "*mul<mode>3_fpr"
4857 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4858 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4859 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4860 "TARGET_<MODE>_FPR"
4861 "@
4862 fmul<Ftrad> %0,%1,%2
4863 xsmul<Fvsx> %x0,%x1,%x2"
4864 [(set_attr "type" "dmul")
4865 (set_attr "fp_type" "fp_mul_<Fs>")])
4867 (define_expand "div<mode>3"
4868 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4869 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4870 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4871 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4872 "")
4874 (define_insn "*div<mode>3_fpr"
4875 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4876 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4877 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4878 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4879 "@
4880 fdiv<Ftrad> %0,%1,%2
4881 xsdiv<Fvsx> %x0,%x1,%x2"
4882 [(set_attr "type" "<Fs>div")
4883 (set_attr "fp_type" "fp_div_<Fs>")])
4885 (define_insn "sqrt<mode>2"
4886 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4887 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4888 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4889 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4890 "@
4891 fsqrt<Ftrad> %0,%1
4892 xssqrt<Fvsx> %x0,%x1"
4893 [(set_attr "type" "<Fs>sqrt")
4894 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4896 ;; Floating point reciprocal approximation
4897 (define_insn "fre<Fs>"
4898 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4899 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4900 UNSPEC_FRES))]
4901 "TARGET_<FFRE>"
4902 "@
4903 fre<Ftrad> %0,%1
4904 xsre<Fvsx> %x0,%x1"
4905 [(set_attr "type" "fp")])
4907 (define_insn "*rsqrt<mode>2"
4908 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4909 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4910 UNSPEC_RSQRT))]
4911 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4912 "@
4913 frsqrte<Ftrad> %0,%1
4914 xsrsqrte<Fvsx> %x0,%x1"
4915 [(set_attr "type" "fp")])
4917 ;; Floating point comparisons
4918 (define_insn "*cmp<mode>_fpr"
4919 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
4920 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4921 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4922 "TARGET_<MODE>_FPR"
4923 "@
4924 fcmpu %0,%1,%2
4925 xscmpudp %0,%x1,%x2"
4926 [(set_attr "type" "fpcompare")])
4928 ;; Floating point conversions
4929 (define_expand "extendsfdf2"
4930 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4931 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4932 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4933 "")
4935 (define_insn_and_split "*extendsfdf2_fpr"
4936 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
4937 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
4938 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4939 "@
4940 #
4941 fmr %0,%1
4942 lfs%U1%X1 %0,%1
4943 #
4944 xxlor %x0,%x1,%x1
4945 lxsspx %x0,%y1"
4946 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4947 [(const_int 0)]
4948 {
4949 emit_note (NOTE_INSN_DELETED);
4950 DONE;
4951 }
4952 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
4954 (define_expand "truncdfsf2"
4955 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4956 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4957 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4958 "")
4960 (define_insn "*truncdfsf2_fpr"
4961 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4962 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4963 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4964 "frsp %0,%1"
4965 [(set_attr "type" "fp")])
4967 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
4968 ;; builtins.c and optabs.c that are not correct for IBM long double
4969 ;; when little-endian.
4970 (define_expand "signbittf2"
4971 [(set (match_dup 2)
4972 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
4973 (set (match_dup 3)
4974 (subreg:DI (match_dup 2) 0))
4975 (set (match_dup 4)
4976 (match_dup 5))
4977 (set (match_operand:SI 0 "gpc_reg_operand" "")
4978 (match_dup 6))]
4979 "!TARGET_IEEEQUAD
4980 && TARGET_HARD_FLOAT
4981 && (TARGET_FPRS || TARGET_E500_DOUBLE)
4982 && TARGET_LONG_DOUBLE_128"
4983 {
4984 operands[2] = gen_reg_rtx (DFmode);
4985 operands[3] = gen_reg_rtx (DImode);
4986 if (TARGET_POWERPC64)
4987 {
4988 operands[4] = gen_reg_rtx (DImode);
4989 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
4990 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
4991 WORDS_BIG_ENDIAN ? 4 : 0);
4992 }
4993 else
4994 {
4995 operands[4] = gen_reg_rtx (SImode);
4996 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
4997 WORDS_BIG_ENDIAN ? 0 : 4);
4998 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
4999 }
5000 })
5002 (define_expand "copysign<mode>3"
5003 [(set (match_dup 3)
5004 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5005 (set (match_dup 4)
5006 (neg:SFDF (abs:SFDF (match_dup 1))))
5007 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5008 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5009 (match_dup 5))
5010 (match_dup 3)
5011 (match_dup 4)))]
5012 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5013 && ((TARGET_PPC_GFXOPT
5014 && !HONOR_NANS (<MODE>mode)
5015 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5016 || TARGET_CMPB
5017 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5018 {
5019 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5020 {
5021 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5022 operands[2]));
5023 DONE;
5024 }
5026 operands[3] = gen_reg_rtx (<MODE>mode);
5027 operands[4] = gen_reg_rtx (<MODE>mode);
5028 operands[5] = CONST0_RTX (<MODE>mode);
5029 })
5031 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5032 ;; compiler from optimizing -0.0
5033 (define_insn "copysign<mode>3_fcpsgn"
5034 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5035 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5036 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5037 UNSPEC_COPYSIGN))]
5038 "TARGET_<MODE>_FPR && TARGET_CMPB"
5039 "@
5040 fcpsgn %0,%2,%1
5041 xscpsgn<Fvsx> %x0,%x2,%x1"
5042 [(set_attr "type" "fp")])
5044 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5045 ;; fsel instruction and some auxiliary computations. Then we just have a
5046 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5047 ;; combine.
5048 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5049 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5050 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5051 ;; define_splits to make them if made by combine. On VSX machines we have the
5052 ;; min/max instructions.
5053 ;;
5054 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5055 ;; to allow either DF/SF to use only traditional registers.
5057 (define_expand "smax<mode>3"
5058 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5059 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5060 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5061 (match_dup 1)
5062 (match_dup 2)))]
5063 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5064 {
5065 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5066 DONE;
5067 })
5069 (define_insn "*smax<mode>3_vsx"
5070 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5071 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5072 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5073 "TARGET_<MODE>_FPR && TARGET_VSX"
5074 "xsmaxdp %x0,%x1,%x2"
5075 [(set_attr "type" "fp")])
5077 (define_expand "smin<mode>3"
5078 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5079 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5080 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5081 (match_dup 2)
5082 (match_dup 1)))]
5083 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5084 {
5085 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5086 DONE;
5087 })
5089 (define_insn "*smin<mode>3_vsx"
5090 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5091 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5092 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5093 "TARGET_<MODE>_FPR && TARGET_VSX"
5094 "xsmindp %x0,%x1,%x2"
5095 [(set_attr "type" "fp")])
5097 (define_split
5098 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5099 (match_operator:SFDF 3 "min_max_operator"
5100 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5101 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5102 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5103 && !TARGET_VSX"
5104 [(const_int 0)]
5105 {
5106 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5107 operands[2]);
5108 DONE;
5109 })
5111 (define_split
5112 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5113 (match_operator:SF 3 "min_max_operator"
5114 [(match_operand:SF 1 "gpc_reg_operand" "")
5115 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5116 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5117 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5118 [(const_int 0)]
5119 "
5120 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5121 operands[1], operands[2]);
5122 DONE;
5123 }")
5125 (define_expand "mov<mode>cc"
5126 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5127 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5128 (match_operand:GPR 2 "gpc_reg_operand" "")
5129 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5130 "TARGET_ISEL<sel>"
5131 "
5132 {
5133 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5134 DONE;
5135 else
5136 FAIL;
5137 }")
5139 ;; We use the BASE_REGS for the isel input operands because, if rA is
5140 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5141 ;; because we may switch the operands and rB may end up being rA.
5142 ;;
5143 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5144 ;; leave out the mode in operand 4 and use one pattern, but reload can
5145 ;; change the mode underneath our feet and then gets confused trying
5146 ;; to reload the value.
5147 (define_insn "isel_signed_<mode>"
5148 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5149 (if_then_else:GPR
5150 (match_operator 1 "scc_comparison_operator"
5151 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5152 (const_int 0)])
5153 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5154 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5155 "TARGET_ISEL<sel>"
5156 "*
5157 { return output_isel (operands); }"
5158 [(set_attr "type" "isel")
5159 (set_attr "length" "4")])
5161 (define_insn "isel_unsigned_<mode>"
5162 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5163 (if_then_else:GPR
5164 (match_operator 1 "scc_comparison_operator"
5165 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5166 (const_int 0)])
5167 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5168 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5169 "TARGET_ISEL<sel>"
5170 "*
5171 { return output_isel (operands); }"
5172 [(set_attr "type" "isel")
5173 (set_attr "length" "4")])
5175 ;; These patterns can be useful for combine; they let combine know that
5176 ;; isel can handle reversed comparisons so long as the operands are
5177 ;; registers.
5179 (define_insn "*isel_reversed_signed_<mode>"
5180 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5181 (if_then_else:GPR
5182 (match_operator 1 "scc_rev_comparison_operator"
5183 [(match_operand:CC 4 "cc_reg_operand" "y")
5184 (const_int 0)])
5185 (match_operand:GPR 2 "gpc_reg_operand" "b")
5186 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5187 "TARGET_ISEL<sel>"
5188 "*
5189 { return output_isel (operands); }"
5190 [(set_attr "type" "isel")
5191 (set_attr "length" "4")])
5193 (define_insn "*isel_reversed_unsigned_<mode>"
5194 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5195 (if_then_else:GPR
5196 (match_operator 1 "scc_rev_comparison_operator"
5197 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5198 (const_int 0)])
5199 (match_operand:GPR 2 "gpc_reg_operand" "b")
5200 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5201 "TARGET_ISEL<sel>"
5202 "*
5203 { return output_isel (operands); }"
5204 [(set_attr "type" "isel")
5205 (set_attr "length" "4")])
5207 (define_expand "movsfcc"
5208 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5209 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5210 (match_operand:SF 2 "gpc_reg_operand" "")
5211 (match_operand:SF 3 "gpc_reg_operand" "")))]
5212 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5213 "
5214 {
5215 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5216 DONE;
5217 else
5218 FAIL;
5219 }")
5221 (define_insn "*fselsfsf4"
5222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5223 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5224 (match_operand:SF 4 "zero_fp_constant" "F"))
5225 (match_operand:SF 2 "gpc_reg_operand" "f")
5226 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5227 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5228 "fsel %0,%1,%2,%3"
5229 [(set_attr "type" "fp")])
5231 (define_insn "*fseldfsf4"
5232 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5233 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5234 (match_operand:DF 4 "zero_fp_constant" "F"))
5235 (match_operand:SF 2 "gpc_reg_operand" "f")
5236 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5237 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5238 "fsel %0,%1,%2,%3"
5239 [(set_attr "type" "fp")])
5241 ;; The conditional move instructions allow us to perform max and min
5242 ;; operations even when
5244 (define_split
5245 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5246 (match_operator:DF 3 "min_max_operator"
5247 [(match_operand:DF 1 "gpc_reg_operand" "")
5248 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5249 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5250 && !flag_trapping_math"
5251 [(const_int 0)]
5252 "
5253 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5254 operands[1], operands[2]);
5255 DONE;
5256 }")
5258 (define_expand "movdfcc"
5259 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5260 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5261 (match_operand:DF 2 "gpc_reg_operand" "")
5262 (match_operand:DF 3 "gpc_reg_operand" "")))]
5263 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5264 "
5265 {
5266 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5267 DONE;
5268 else
5269 FAIL;
5270 }")
5272 (define_insn "*fseldfdf4"
5273 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5274 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5275 (match_operand:DF 4 "zero_fp_constant" "F"))
5276 (match_operand:DF 2 "gpc_reg_operand" "d")
5277 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5278 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5279 "fsel %0,%1,%2,%3"
5280 [(set_attr "type" "fp")])
5282 (define_insn "*fselsfdf4"
5283 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5284 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5285 (match_operand:SF 4 "zero_fp_constant" "F"))
5286 (match_operand:DF 2 "gpc_reg_operand" "d")
5287 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5288 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5289 "fsel %0,%1,%2,%3"
5290 [(set_attr "type" "fp")])
5291 \f
5292 ;; Conversions to and from floating-point.
5294 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5295 ; don't want to support putting SImode in FPR registers.
5296 (define_insn "lfiwax"
5297 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5298 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5299 UNSPEC_LFIWAX))]
5300 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5301 "@
5302 lfiwax %0,%y1
5303 lxsiwax %x0,%y1
5304 mtvsrwa %x0,%1"
5305 [(set_attr "type" "fpload,fpload,mffgpr")])
5307 ; This split must be run before register allocation because it allocates the
5308 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5309 ; it earlier to allow for the combiner to merge insns together where it might
5310 ; not be needed and also in case the insns are deleted as dead code.
5312 (define_insn_and_split "floatsi<mode>2_lfiwax"
5313 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5314 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5315 (clobber (match_scratch:DI 2 "=d"))]
5316 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5317 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5318 "#"
5319 ""
5320 [(pc)]
5321 "
5322 {
5323 rtx dest = operands[0];
5324 rtx src = operands[1];
5325 rtx tmp;
5327 if (!MEM_P (src) && TARGET_POWERPC64
5328 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5329 tmp = convert_to_mode (DImode, src, false);
5330 else
5331 {
5332 tmp = operands[2];
5333 if (GET_CODE (tmp) == SCRATCH)
5334 tmp = gen_reg_rtx (DImode);
5335 if (MEM_P (src))
5336 {
5337 src = rs6000_address_for_fpconvert (src);
5338 emit_insn (gen_lfiwax (tmp, src));
5339 }
5340 else
5341 {
5342 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5343 emit_move_insn (stack, src);
5344 emit_insn (gen_lfiwax (tmp, stack));
5345 }
5346 }
5347 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5348 DONE;
5349 }"
5350 [(set_attr "length" "12")
5351 (set_attr "type" "fpload")])
5353 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5354 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5355 (float:SFDF
5356 (sign_extend:DI
5357 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5358 (clobber (match_scratch:DI 2 "=0,d"))]
5359 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5360 && <SI_CONVERT_FP>"
5361 "#"
5362 ""
5363 [(pc)]
5364 "
5365 {
5366 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5367 if (GET_CODE (operands[2]) == SCRATCH)
5368 operands[2] = gen_reg_rtx (DImode);
5369 emit_insn (gen_lfiwax (operands[2], operands[1]));
5370 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5371 DONE;
5372 }"
5373 [(set_attr "length" "8")
5374 (set_attr "type" "fpload")])
5376 (define_insn "lfiwzx"
5377 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5378 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5379 UNSPEC_LFIWZX))]
5380 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5381 "@
5382 lfiwzx %0,%y1
5383 lxsiwzx %x0,%y1
5384 mtvsrwz %x0,%1"
5385 [(set_attr "type" "fpload,fpload,mftgpr")])
5387 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5388 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5389 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5390 (clobber (match_scratch:DI 2 "=d"))]
5391 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5392 && <SI_CONVERT_FP>"
5393 "#"
5394 ""
5395 [(pc)]
5396 "
5397 {
5398 rtx dest = operands[0];
5399 rtx src = operands[1];
5400 rtx tmp;
5402 if (!MEM_P (src) && TARGET_POWERPC64
5403 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5404 tmp = convert_to_mode (DImode, src, true);
5405 else
5406 {
5407 tmp = operands[2];
5408 if (GET_CODE (tmp) == SCRATCH)
5409 tmp = gen_reg_rtx (DImode);
5410 if (MEM_P (src))
5411 {
5412 src = rs6000_address_for_fpconvert (src);
5413 emit_insn (gen_lfiwzx (tmp, src));
5414 }
5415 else
5416 {
5417 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5418 emit_move_insn (stack, src);
5419 emit_insn (gen_lfiwzx (tmp, stack));
5420 }
5421 }
5422 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5423 DONE;
5424 }"
5425 [(set_attr "length" "12")
5426 (set_attr "type" "fpload")])
5428 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5429 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5430 (unsigned_float:SFDF
5431 (zero_extend:DI
5432 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5433 (clobber (match_scratch:DI 2 "=0,d"))]
5434 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5435 && <SI_CONVERT_FP>"
5436 "#"
5437 ""
5438 [(pc)]
5439 "
5440 {
5441 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5442 if (GET_CODE (operands[2]) == SCRATCH)
5443 operands[2] = gen_reg_rtx (DImode);
5444 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5445 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5446 DONE;
5447 }"
5448 [(set_attr "length" "8")
5449 (set_attr "type" "fpload")])
5451 ; For each of these conversions, there is a define_expand, a define_insn
5452 ; with a '#' template, and a define_split (with C code). The idea is
5453 ; to allow constant folding with the template of the define_insn,
5454 ; then to have the insns split later (between sched1 and final).
5456 (define_expand "floatsidf2"
5457 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5458 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5459 (use (match_dup 2))
5460 (use (match_dup 3))
5461 (clobber (match_dup 4))
5462 (clobber (match_dup 5))
5463 (clobber (match_dup 6))])]
5464 "TARGET_HARD_FLOAT
5465 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5466 "
5467 {
5468 if (TARGET_E500_DOUBLE)
5469 {
5470 if (!REG_P (operands[1]))
5471 operands[1] = force_reg (SImode, operands[1]);
5472 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5473 DONE;
5474 }
5475 else if (TARGET_LFIWAX && TARGET_FCFID)
5476 {
5477 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5478 DONE;
5479 }
5480 else if (TARGET_FCFID)
5481 {
5482 rtx dreg = operands[1];
5483 if (!REG_P (dreg))
5484 dreg = force_reg (SImode, dreg);
5485 dreg = convert_to_mode (DImode, dreg, false);
5486 emit_insn (gen_floatdidf2 (operands[0], dreg));
5487 DONE;
5488 }
5490 if (!REG_P (operands[1]))
5491 operands[1] = force_reg (SImode, operands[1]);
5492 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5493 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5494 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5495 operands[5] = gen_reg_rtx (DFmode);
5496 operands[6] = gen_reg_rtx (SImode);
5497 }")
5499 (define_insn_and_split "*floatsidf2_internal"
5500 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5501 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5502 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5503 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5504 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5505 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5506 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5507 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5508 "#"
5509 ""
5510 [(pc)]
5511 "
5512 {
5513 rtx lowword, highword;
5514 gcc_assert (MEM_P (operands[4]));
5515 highword = adjust_address (operands[4], SImode, 0);
5516 lowword = adjust_address (operands[4], SImode, 4);
5517 if (! WORDS_BIG_ENDIAN)
5518 {
5519 rtx tmp;
5520 tmp = highword; highword = lowword; lowword = tmp;
5521 }
5523 emit_insn (gen_xorsi3 (operands[6], operands[1],
5524 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5525 emit_move_insn (lowword, operands[6]);
5526 emit_move_insn (highword, operands[2]);
5527 emit_move_insn (operands[5], operands[4]);
5528 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5529 DONE;
5530 }"
5531 [(set_attr "length" "24")
5532 (set_attr "type" "fp")])
5534 ;; If we don't have a direct conversion to single precision, don't enable this
5535 ;; conversion for 32-bit without fast math, because we don't have the insn to
5536 ;; generate the fixup swizzle to avoid double rounding problems.
5537 (define_expand "floatunssisf2"
5538 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5539 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5540 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5541 && (!TARGET_FPRS
5542 || (TARGET_FPRS
5543 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5544 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5545 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5546 "
5547 {
5548 if (!TARGET_FPRS)
5549 {
5550 if (!REG_P (operands[1]))
5551 operands[1] = force_reg (SImode, operands[1]);
5552 }
5553 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5554 {
5555 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5556 DONE;
5557 }
5558 else
5559 {
5560 rtx dreg = operands[1];
5561 if (!REG_P (dreg))
5562 dreg = force_reg (SImode, dreg);
5563 dreg = convert_to_mode (DImode, dreg, true);
5564 emit_insn (gen_floatdisf2 (operands[0], dreg));
5565 DONE;
5566 }
5567 }")
5569 (define_expand "floatunssidf2"
5570 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5572 (use (match_dup 2))
5573 (use (match_dup 3))
5574 (clobber (match_dup 4))
5575 (clobber (match_dup 5))])]
5576 "TARGET_HARD_FLOAT
5577 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5578 "
5579 {
5580 if (TARGET_E500_DOUBLE)
5581 {
5582 if (!REG_P (operands[1]))
5583 operands[1] = force_reg (SImode, operands[1]);
5584 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5585 DONE;
5586 }
5587 else if (TARGET_LFIWZX && TARGET_FCFID)
5588 {
5589 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5590 DONE;
5591 }
5592 else if (TARGET_FCFID)
5593 {
5594 rtx dreg = operands[1];
5595 if (!REG_P (dreg))
5596 dreg = force_reg (SImode, dreg);
5597 dreg = convert_to_mode (DImode, dreg, true);
5598 emit_insn (gen_floatdidf2 (operands[0], dreg));
5599 DONE;
5600 }
5602 if (!REG_P (operands[1]))
5603 operands[1] = force_reg (SImode, operands[1]);
5604 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5605 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5606 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5607 operands[5] = gen_reg_rtx (DFmode);
5608 }")
5610 (define_insn_and_split "*floatunssidf2_internal"
5611 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5612 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5613 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5614 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5615 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5616 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5617 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5618 && !(TARGET_FCFID && TARGET_POWERPC64)"
5619 "#"
5620 ""
5621 [(pc)]
5622 "
5623 {
5624 rtx lowword, highword;
5625 gcc_assert (MEM_P (operands[4]));
5626 highword = adjust_address (operands[4], SImode, 0);
5627 lowword = adjust_address (operands[4], SImode, 4);
5628 if (! WORDS_BIG_ENDIAN)
5629 {
5630 rtx tmp;
5631 tmp = highword; highword = lowword; lowword = tmp;
5632 }
5634 emit_move_insn (lowword, operands[1]);
5635 emit_move_insn (highword, operands[2]);
5636 emit_move_insn (operands[5], operands[4]);
5637 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5638 DONE;
5639 }"
5640 [(set_attr "length" "20")
5641 (set_attr "type" "fp")])
5643 (define_expand "fix_trunc<mode>si2"
5644 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5645 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5646 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5647 "
5648 {
5649 if (!<E500_CONVERT>)
5650 {
5651 rtx tmp, stack;
5653 if (TARGET_STFIWX)
5654 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5655 else
5656 {
5657 tmp = gen_reg_rtx (DImode);
5658 stack = rs6000_allocate_stack_temp (DImode, true, false);
5659 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5660 tmp, stack));
5661 }
5662 DONE;
5663 }
5664 }")
5666 ; Like the convert to float patterns, this insn must be split before
5667 ; register allocation so that it can allocate the memory slot if it
5668 ; needed
5669 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5670 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5671 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5672 (clobber (match_scratch:DI 2 "=d"))]
5673 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5674 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5675 && TARGET_STFIWX && can_create_pseudo_p ()"
5676 "#"
5677 ""
5678 [(pc)]
5679 {
5680 rtx dest = operands[0];
5681 rtx src = operands[1];
5682 rtx tmp = operands[2];
5684 if (GET_CODE (tmp) == SCRATCH)
5685 tmp = gen_reg_rtx (DImode);
5687 emit_insn (gen_fctiwz_<mode> (tmp, src));
5688 if (MEM_P (dest))
5689 {
5690 dest = rs6000_address_for_fpconvert (dest);
5691 emit_insn (gen_stfiwx (dest, tmp));
5692 DONE;
5693 }
5694 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5695 {
5696 dest = gen_lowpart (DImode, dest);
5697 emit_move_insn (dest, tmp);
5698 DONE;
5699 }
5700 else
5701 {
5702 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5703 emit_insn (gen_stfiwx (stack, tmp));
5704 emit_move_insn (dest, stack);
5705 DONE;
5706 }
5707 }
5708 [(set_attr "length" "12")
5709 (set_attr "type" "fp")])
5711 (define_insn_and_split "fix_trunc<mode>si2_internal"
5712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5713 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5714 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5715 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5716 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5717 "#"
5718 ""
5719 [(pc)]
5720 "
5721 {
5722 rtx lowword;
5723 gcc_assert (MEM_P (operands[3]));
5724 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5726 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5727 emit_move_insn (operands[3], operands[2]);
5728 emit_move_insn (operands[0], lowword);
5729 DONE;
5730 }"
5731 [(set_attr "length" "16")
5732 (set_attr "type" "fp")])
5734 (define_expand "fix_trunc<mode>di2"
5735 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5736 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5737 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5738 && TARGET_FCFID"
5739 "")
5741 (define_insn "*fix_trunc<mode>di2_fctidz"
5742 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5743 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5744 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5745 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5746 "fctidz %0,%1"
5747 [(set_attr "type" "fp")])
5749 (define_expand "fixuns_trunc<mode>si2"
5750 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5751 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5752 "TARGET_HARD_FLOAT
5753 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5754 || <E500_CONVERT>)"
5755 "
5756 {
5757 if (!<E500_CONVERT>)
5758 {
5759 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5760 DONE;
5761 }
5762 }")
5764 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5765 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5766 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5767 (clobber (match_scratch:DI 2 "=d"))]
5768 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5769 && TARGET_STFIWX && can_create_pseudo_p ()"
5770 "#"
5771 ""
5772 [(pc)]
5773 {
5774 rtx dest = operands[0];
5775 rtx src = operands[1];
5776 rtx tmp = operands[2];
5778 if (GET_CODE (tmp) == SCRATCH)
5779 tmp = gen_reg_rtx (DImode);
5781 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5782 if (MEM_P (dest))
5783 {
5784 dest = rs6000_address_for_fpconvert (dest);
5785 emit_insn (gen_stfiwx (dest, tmp));
5786 DONE;
5787 }
5788 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5789 {
5790 dest = gen_lowpart (DImode, dest);
5791 emit_move_insn (dest, tmp);
5792 DONE;
5793 }
5794 else
5795 {
5796 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5797 emit_insn (gen_stfiwx (stack, tmp));
5798 emit_move_insn (dest, stack);
5799 DONE;
5800 }
5801 }
5802 [(set_attr "length" "12")
5803 (set_attr "type" "fp")])
5805 (define_expand "fixuns_trunc<mode>di2"
5806 [(set (match_operand:DI 0 "register_operand" "")
5807 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5808 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5809 "")
5811 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5812 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5813 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5814 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5815 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5816 "fctiduz %0,%1"
5817 [(set_attr "type" "fp")])
5819 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5820 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5821 ; because the first makes it clear that operand 0 is not live
5822 ; before the instruction.
5823 (define_insn "fctiwz_<mode>"
5824 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5825 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5826 UNSPEC_FCTIWZ))]
5827 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5828 "fctiwz %0,%1"
5829 [(set_attr "type" "fp")])
5831 (define_insn "fctiwuz_<mode>"
5832 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5833 (unspec:DI [(unsigned_fix:SI
5834 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5835 UNSPEC_FCTIWUZ))]
5836 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5837 "fctiwuz %0,%1"
5838 [(set_attr "type" "fp")])
5840 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5841 ;; since the friz instruction does not truncate the value if the floating
5842 ;; point value is < LONG_MIN or > LONG_MAX.
5843 (define_insn "*friz"
5844 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5845 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5846 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5847 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5848 && !flag_trapping_math && TARGET_FRIZ"
5849 "friz %0,%1"
5850 [(set_attr "type" "fp")])
5852 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5853 ;; load to properly sign extend the value, but at least doing a store, load
5854 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5855 ;; if we have 32-bit memory ops
5856 (define_insn_and_split "*round32<mode>2_fprs"
5857 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5858 (float:SFDF
5859 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5860 (clobber (match_scratch:DI 2 "=d"))
5861 (clobber (match_scratch:DI 3 "=d"))]
5862 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5863 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5864 && can_create_pseudo_p ()"
5865 "#"
5866 ""
5867 [(pc)]
5868 {
5869 rtx dest = operands[0];
5870 rtx src = operands[1];
5871 rtx tmp1 = operands[2];
5872 rtx tmp2 = operands[3];
5873 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5875 if (GET_CODE (tmp1) == SCRATCH)
5876 tmp1 = gen_reg_rtx (DImode);
5877 if (GET_CODE (tmp2) == SCRATCH)
5878 tmp2 = gen_reg_rtx (DImode);
5880 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5881 emit_insn (gen_stfiwx (stack, tmp1));
5882 emit_insn (gen_lfiwax (tmp2, stack));
5883 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5884 DONE;
5885 }
5886 [(set_attr "type" "fpload")
5887 (set_attr "length" "16")])
5889 (define_insn_and_split "*roundu32<mode>2_fprs"
5890 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5891 (unsigned_float:SFDF
5892 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5893 (clobber (match_scratch:DI 2 "=d"))
5894 (clobber (match_scratch:DI 3 "=d"))]
5895 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5896 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5897 && can_create_pseudo_p ()"
5898 "#"
5899 ""
5900 [(pc)]
5901 {
5902 rtx dest = operands[0];
5903 rtx src = operands[1];
5904 rtx tmp1 = operands[2];
5905 rtx tmp2 = operands[3];
5906 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5908 if (GET_CODE (tmp1) == SCRATCH)
5909 tmp1 = gen_reg_rtx (DImode);
5910 if (GET_CODE (tmp2) == SCRATCH)
5911 tmp2 = gen_reg_rtx (DImode);
5913 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5914 emit_insn (gen_stfiwx (stack, tmp1));
5915 emit_insn (gen_lfiwzx (tmp2, stack));
5916 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5917 DONE;
5918 }
5919 [(set_attr "type" "fpload")
5920 (set_attr "length" "16")])
5922 ;; No VSX equivalent to fctid
5923 (define_insn "lrint<mode>di2"
5924 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5925 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5926 UNSPEC_FCTID))]
5927 "TARGET_<MODE>_FPR && TARGET_FPRND"
5928 "fctid %0,%1"
5929 [(set_attr "type" "fp")])
5931 (define_insn "btrunc<mode>2"
5932 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5933 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5934 UNSPEC_FRIZ))]
5935 "TARGET_<MODE>_FPR && TARGET_FPRND"
5936 "@
5937 friz %0,%1
5938 xsrdpiz %x0,%x1"
5939 [(set_attr "type" "fp")
5940 (set_attr "fp_type" "fp_addsub_<Fs>")])
5942 (define_insn "ceil<mode>2"
5943 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5944 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5945 UNSPEC_FRIP))]
5946 "TARGET_<MODE>_FPR && TARGET_FPRND"
5947 "@
5948 frip %0,%1
5949 xsrdpip %x0,%x1"
5950 [(set_attr "type" "fp")
5951 (set_attr "fp_type" "fp_addsub_<Fs>")])
5953 (define_insn "floor<mode>2"
5954 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5955 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5956 UNSPEC_FRIM))]
5957 "TARGET_<MODE>_FPR && TARGET_FPRND"
5958 "@
5959 frim %0,%1
5960 xsrdpim %x0,%x1"
5961 [(set_attr "type" "fp")
5962 (set_attr "fp_type" "fp_addsub_<Fs>")])
5964 ;; No VSX equivalent to frin
5965 (define_insn "round<mode>2"
5966 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5967 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5968 UNSPEC_FRIN))]
5969 "TARGET_<MODE>_FPR && TARGET_FPRND"
5970 "frin %0,%1"
5971 [(set_attr "type" "fp")
5972 (set_attr "fp_type" "fp_addsub_<Fs>")])
5974 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5975 (define_insn "stfiwx"
5976 [(set (match_operand:SI 0 "memory_operand" "=Z")
5977 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
5978 UNSPEC_STFIWX))]
5979 "TARGET_PPC_GFXOPT"
5980 "stfiwx %1,%y0"
5981 [(set_attr "type" "fpstore")])
5983 ;; If we don't have a direct conversion to single precision, don't enable this
5984 ;; conversion for 32-bit without fast math, because we don't have the insn to
5985 ;; generate the fixup swizzle to avoid double rounding problems.
5986 (define_expand "floatsisf2"
5987 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5988 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5989 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5990 && (!TARGET_FPRS
5991 || (TARGET_FPRS
5992 && ((TARGET_FCFIDS && TARGET_LFIWAX)
5993 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5994 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5995 "
5996 {
5997 if (!TARGET_FPRS)
5998 {
5999 if (!REG_P (operands[1]))
6000 operands[1] = force_reg (SImode, operands[1]);
6001 }
6002 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6003 {
6004 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6005 DONE;
6006 }
6007 else if (TARGET_FCFID && TARGET_LFIWAX)
6008 {
6009 rtx dfreg = gen_reg_rtx (DFmode);
6010 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6011 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6012 DONE;
6013 }
6014 else
6015 {
6016 rtx dreg = operands[1];
6017 if (!REG_P (dreg))
6018 dreg = force_reg (SImode, dreg);
6019 dreg = convert_to_mode (DImode, dreg, false);
6020 emit_insn (gen_floatdisf2 (operands[0], dreg));
6021 DONE;
6022 }
6023 }")
6025 (define_expand "floatdidf2"
6026 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6027 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6028 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6029 "")
6031 (define_insn "*floatdidf2_fpr"
6032 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6033 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6034 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6035 && !VECTOR_UNIT_VSX_P (DFmode)"
6036 "fcfid %0,%1"
6037 [(set_attr "type" "fp")])
6039 ; Allow the combiner to merge source memory operands to the conversion so that
6040 ; the optimizer/register allocator doesn't try to load the value too early in a
6041 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6042 ; hit. We will split after reload to avoid the trip through the GPRs
6044 (define_insn_and_split "*floatdidf2_mem"
6045 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6046 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6047 (clobber (match_scratch:DI 2 "=d"))]
6048 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6049 "#"
6050 "&& reload_completed"
6051 [(set (match_dup 2) (match_dup 1))
6052 (set (match_dup 0) (float:DF (match_dup 2)))]
6053 ""
6054 [(set_attr "length" "8")
6055 (set_attr "type" "fpload")])
6057 (define_expand "floatunsdidf2"
6058 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6059 (unsigned_float:DF
6060 (match_operand:DI 1 "gpc_reg_operand" "")))]
6061 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6062 "")
6064 (define_insn "*floatunsdidf2_fcfidu"
6065 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6066 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6067 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6068 "fcfidu %0,%1"
6069 [(set_attr "type" "fp")
6070 (set_attr "length" "4")])
6072 (define_insn_and_split "*floatunsdidf2_mem"
6073 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6074 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6075 (clobber (match_scratch:DI 2 "=d"))]
6076 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6077 "#"
6078 "&& reload_completed"
6079 [(set (match_dup 2) (match_dup 1))
6080 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6081 ""
6082 [(set_attr "length" "8")
6083 (set_attr "type" "fpload")])
6085 (define_expand "floatdisf2"
6086 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6087 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6088 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6089 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6090 "
6091 {
6092 if (!TARGET_FCFIDS)
6093 {
6094 rtx val = operands[1];
6095 if (!flag_unsafe_math_optimizations)
6096 {
6097 rtx label = gen_label_rtx ();
6098 val = gen_reg_rtx (DImode);
6099 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6100 emit_label (label);
6101 }
6102 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6103 DONE;
6104 }
6105 }")
6107 (define_insn "floatdisf2_fcfids"
6108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6109 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6110 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6111 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6112 "fcfids %0,%1"
6113 [(set_attr "type" "fp")])
6115 (define_insn_and_split "*floatdisf2_mem"
6116 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6117 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6118 (clobber (match_scratch:DI 2 "=f"))]
6119 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6120 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6121 "#"
6122 "&& reload_completed"
6123 [(pc)]
6124 "
6125 {
6126 emit_move_insn (operands[2], operands[1]);
6127 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6128 DONE;
6129 }"
6130 [(set_attr "length" "8")])
6132 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6133 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6134 ;; from double rounding.
6135 ;; Instead of creating a new cpu type for two FP operations, just use fp
6136 (define_insn_and_split "floatdisf2_internal1"
6137 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6138 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6139 (clobber (match_scratch:DF 2 "=d"))]
6140 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6141 "#"
6142 "&& reload_completed"
6143 [(set (match_dup 2)
6144 (float:DF (match_dup 1)))
6145 (set (match_dup 0)
6146 (float_truncate:SF (match_dup 2)))]
6147 ""
6148 [(set_attr "length" "8")
6149 (set_attr "type" "fp")])
6151 ;; Twiddles bits to avoid double rounding.
6152 ;; Bits that might be truncated when converting to DFmode are replaced
6153 ;; by a bit that won't be lost at that stage, but is below the SFmode
6154 ;; rounding position.
6155 (define_expand "floatdisf2_internal2"
6156 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6157 (const_int 53)))
6158 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6159 (const_int 2047)))
6160 (set (match_dup 3) (plus:DI (match_dup 3)
6161 (const_int 1)))
6162 (set (match_dup 0) (plus:DI (match_dup 0)
6163 (const_int 2047)))
6164 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6165 (const_int 2)))
6166 (set (match_dup 0) (ior:DI (match_dup 0)
6167 (match_dup 1)))
6168 (set (match_dup 0) (and:DI (match_dup 0)
6169 (const_int -2048)))
6170 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6171 (label_ref (match_operand:DI 2 "" ""))
6172 (pc)))
6173 (set (match_dup 0) (match_dup 1))]
6174 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6175 "
6176 {
6177 operands[3] = gen_reg_rtx (DImode);
6178 operands[4] = gen_reg_rtx (CCUNSmode);
6179 }")
6181 (define_expand "floatunsdisf2"
6182 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6183 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6184 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6185 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6186 "")
6188 (define_insn "floatunsdisf2_fcfidus"
6189 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6190 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6191 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6192 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6193 "fcfidus %0,%1"
6194 [(set_attr "type" "fp")])
6196 (define_insn_and_split "*floatunsdisf2_mem"
6197 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6198 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6199 (clobber (match_scratch:DI 2 "=f"))]
6200 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6201 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6202 "#"
6203 "&& reload_completed"
6204 [(pc)]
6205 "
6206 {
6207 emit_move_insn (operands[2], operands[1]);
6208 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6209 DONE;
6210 }"
6211 [(set_attr "length" "8")
6212 (set_attr "type" "fpload")])
6213 \f
6214 ;; Define the TImode operations that can be done in a small number
6215 ;; of instructions. The & constraints are to prevent the register
6216 ;; allocator from allocating registers that overlap with the inputs
6217 ;; (for example, having an input in 7,8 and an output in 6,7). We
6218 ;; also allow for the output being the same as one of the inputs.
6220 (define_insn "addti3"
6221 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6222 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6223 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6224 "TARGET_64BIT"
6225 {
6226 if (WORDS_BIG_ENDIAN)
6227 return (GET_CODE (operands[2])) != CONST_INT
6228 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6229 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6230 else
6231 return (GET_CODE (operands[2])) != CONST_INT
6232 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6233 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6234 }
6235 [(set_attr "type" "two")
6236 (set_attr "length" "8")])
6238 (define_insn "subti3"
6239 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6240 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6241 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6242 "TARGET_64BIT"
6243 {
6244 if (WORDS_BIG_ENDIAN)
6245 return (GET_CODE (operands[1]) != CONST_INT)
6246 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6247 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6248 else
6249 return (GET_CODE (operands[1]) != CONST_INT)
6250 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6251 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6252 }
6253 [(set_attr "type" "two")
6254 (set_attr "length" "8")])
6257 ;; Define the DImode operations that can be done in a small number
6258 ;; of instructions. The & constraints are to prevent the register
6259 ;; allocator from allocating registers that overlap with the inputs
6260 ;; (for example, having an input in 7,8 and an output in 6,7). We
6261 ;; also allow for the output being the same as one of the inputs.
6263 (define_insn "*adddi3_noppc64"
6264 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6265 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6266 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6267 "! TARGET_POWERPC64"
6268 "*
6269 {
6270 if (WORDS_BIG_ENDIAN)
6271 return (GET_CODE (operands[2])) != CONST_INT
6272 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6273 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6274 else
6275 return (GET_CODE (operands[2])) != CONST_INT
6276 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6277 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6278 }"
6279 [(set_attr "type" "two")
6280 (set_attr "length" "8")])
6282 (define_insn "*subdi3_noppc64"
6283 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6284 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6285 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6286 "! TARGET_POWERPC64"
6287 "*
6288 {
6289 if (WORDS_BIG_ENDIAN)
6290 return (GET_CODE (operands[1]) != CONST_INT)
6291 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6292 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6293 else
6294 return (GET_CODE (operands[1]) != CONST_INT)
6295 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6296 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6297 }"
6298 [(set_attr "type" "two")
6299 (set_attr "length" "8")])
6301 (define_insn "*negdi2_noppc64"
6302 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6303 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6304 "! TARGET_POWERPC64"
6305 "*
6306 {
6307 return (WORDS_BIG_ENDIAN)
6308 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6309 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6310 }"
6311 [(set_attr "type" "two")
6312 (set_attr "length" "8")])
6315 ;; Shift by a variable amount is too complex to be worth open-coding. We
6316 ;; just handle shifts by constants.
6317 (define_insn "ashrdi3_no_power"
6318 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6319 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6320 (match_operand:SI 2 "const_int_operand" "M,i")))]
6321 "!TARGET_POWERPC64"
6322 "*
6323 {
6324 switch (which_alternative)
6325 {
6326 default:
6327 gcc_unreachable ();
6328 case 0:
6329 if (WORDS_BIG_ENDIAN)
6330 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6331 else
6332 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6333 case 1:
6334 if (WORDS_BIG_ENDIAN)
6335 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6336 else
6337 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6338 }
6339 }"
6340 [(set_attr "type" "two,three")
6341 (set_attr "length" "8,12")])
6343 (define_insn "*ashrdisi3_noppc64be"
6344 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6345 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6346 (const_int 32)) 4))]
6347 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6348 "*
6349 {
6350 if (REGNO (operands[0]) == REGNO (operands[1]))
6351 return \"\";
6352 else
6353 return \"mr %0,%1\";
6354 }"
6355 [(set_attr "length" "4")])
6357 \f
6358 ;; PowerPC64 DImode operations.
6360 (define_insn "*rotldi3_internal4"
6361 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6362 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6363 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6364 (match_operand:DI 3 "mask64_operand" "n")))]
6365 "TARGET_POWERPC64"
6366 "rld%I2c%B3 %0,%1,%H2,%S3"
6367 [(set_attr "type" "shift")
6368 (set_attr "maybe_var_shift" "yes")])
6370 (define_insn "*rotldi3_internal5"
6371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6372 (compare:CC (and:DI
6373 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6374 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6375 (match_operand:DI 3 "mask64_operand" "n,n"))
6376 (const_int 0)))
6377 (clobber (match_scratch:DI 4 "=r,r"))]
6378 "TARGET_64BIT"
6379 "@
6380 rld%I2c%B3. %4,%1,%H2,%S3
6381 #"
6382 [(set_attr "type" "shift")
6383 (set_attr "maybe_var_shift" "yes")
6384 (set_attr "dot" "yes")
6385 (set_attr "length" "4,8")])
6387 (define_split
6388 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6389 (compare:CC (and:DI
6390 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6391 (match_operand:DI 2 "reg_or_cint_operand" ""))
6392 (match_operand:DI 3 "mask64_operand" ""))
6393 (const_int 0)))
6394 (clobber (match_scratch:DI 4 ""))]
6395 "TARGET_POWERPC64 && reload_completed"
6396 [(set (match_dup 4)
6397 (and:DI (rotate:DI (match_dup 1)
6398 (match_dup 2))
6399 (match_dup 3)))
6400 (set (match_dup 0)
6401 (compare:CC (match_dup 4)
6402 (const_int 0)))]
6403 "")
6405 (define_insn "*rotldi3_internal6"
6406 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6407 (compare:CC (and:DI
6408 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6409 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6410 (match_operand:DI 3 "mask64_operand" "n,n"))
6411 (const_int 0)))
6412 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6413 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6414 "TARGET_64BIT"
6415 "@
6416 rld%I2c%B3. %0,%1,%H2,%S3
6417 #"
6418 [(set_attr "type" "shift")
6419 (set_attr "maybe_var_shift" "yes")
6420 (set_attr "dot" "yes")
6421 (set_attr "length" "4,8")])
6423 (define_split
6424 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6425 (compare:CC (and:DI
6426 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6427 (match_operand:DI 2 "reg_or_cint_operand" ""))
6428 (match_operand:DI 3 "mask64_operand" ""))
6429 (const_int 0)))
6430 (set (match_operand:DI 0 "gpc_reg_operand" "")
6431 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6432 "TARGET_POWERPC64 && reload_completed"
6433 [(set (match_dup 0)
6434 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6435 (set (match_dup 4)
6436 (compare:CC (match_dup 0)
6437 (const_int 0)))]
6438 "")
6440 (define_insn "*rotldi3_internal7le"
6441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6442 (zero_extend:DI
6443 (subreg:QI
6444 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6445 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6446 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6447 "rld%I2cl %0,%1,%H2,56"
6448 [(set_attr "type" "shift")
6449 (set_attr "maybe_var_shift" "yes")])
6451 (define_insn "*rotldi3_internal7be"
6452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6453 (zero_extend:DI
6454 (subreg:QI
6455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6456 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6457 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6458 "rld%I2cl %0,%1,%H2,56"
6459 [(set_attr "type" "shift")
6460 (set_attr "maybe_var_shift" "yes")])
6462 (define_insn "*rotldi3_internal8le"
6463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6464 (compare:CC (zero_extend:DI
6465 (subreg:QI
6466 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6467 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6468 (const_int 0)))
6469 (clobber (match_scratch:DI 3 "=r,r"))]
6470 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6471 "@
6472 rld%I2cl. %3,%1,%H2,56
6473 #"
6474 [(set_attr "type" "shift")
6475 (set_attr "maybe_var_shift" "yes")
6476 (set_attr "dot" "yes")
6477 (set_attr "length" "4,8")])
6479 (define_insn "*rotldi3_internal8be"
6480 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6481 (compare:CC (zero_extend:DI
6482 (subreg:QI
6483 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6484 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6485 (const_int 0)))
6486 (clobber (match_scratch:DI 3 "=r,r"))]
6487 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6488 "@
6489 rld%I2cl. %3,%1,%H2,56
6490 #"
6491 [(set_attr "type" "shift")
6492 (set_attr "maybe_var_shift" "yes")
6493 (set_attr "dot" "yes")
6494 (set_attr "length" "4,8")])
6496 (define_split
6497 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6498 (compare:CC (zero_extend:DI
6499 (subreg:QI
6500 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6501 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6502 (const_int 0)))
6503 (clobber (match_scratch:DI 3 ""))]
6504 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6505 [(set (match_dup 3)
6506 (zero_extend:DI (subreg:QI
6507 (rotate:DI (match_dup 1)
6508 (match_dup 2)) 0)))
6509 (set (match_dup 0)
6510 (compare:CC (match_dup 3)
6511 (const_int 0)))]
6512 "")
6514 (define_split
6515 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6516 (compare:CC (zero_extend:DI
6517 (subreg:QI
6518 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6519 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6520 (const_int 0)))
6521 (clobber (match_scratch:DI 3 ""))]
6522 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6523 [(set (match_dup 3)
6524 (zero_extend:DI (subreg:QI
6525 (rotate:DI (match_dup 1)
6526 (match_dup 2)) 7)))
6527 (set (match_dup 0)
6528 (compare:CC (match_dup 3)
6529 (const_int 0)))]
6530 "")
6532 (define_insn "*rotldi3_internal9le"
6533 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6534 (compare:CC (zero_extend:DI
6535 (subreg:QI
6536 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6537 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6538 (const_int 0)))
6539 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6540 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6541 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6542 "@
6543 rld%I2cl. %0,%1,%H2,56
6544 #"
6545 [(set_attr "type" "shift")
6546 (set_attr "maybe_var_shift" "yes")
6547 (set_attr "dot" "yes")
6548 (set_attr "length" "4,8")])
6550 (define_insn "*rotldi3_internal9be"
6551 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6552 (compare:CC (zero_extend:DI
6553 (subreg:QI
6554 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6555 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6556 (const_int 0)))
6557 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6558 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6559 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6560 "@
6561 rld%I2cl. %0,%1,%H2,56
6562 #"
6563 [(set_attr "type" "shift")
6564 (set_attr "maybe_var_shift" "yes")
6565 (set_attr "dot" "yes")
6566 (set_attr "length" "4,8")])
6568 (define_split
6569 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6570 (compare:CC (zero_extend:DI
6571 (subreg:QI
6572 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6573 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6574 (const_int 0)))
6575 (set (match_operand:DI 0 "gpc_reg_operand" "")
6576 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6577 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6578 [(set (match_dup 0)
6579 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6580 (set (match_dup 3)
6581 (compare:CC (match_dup 0)
6582 (const_int 0)))]
6583 "")
6585 (define_split
6586 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6587 (compare:CC (zero_extend:DI
6588 (subreg:QI
6589 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6590 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6591 (const_int 0)))
6592 (set (match_operand:DI 0 "gpc_reg_operand" "")
6593 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6594 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6595 [(set (match_dup 0)
6596 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6597 (set (match_dup 3)
6598 (compare:CC (match_dup 0)
6599 (const_int 0)))]
6600 "")
6602 (define_insn "*rotldi3_internal10le"
6603 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6604 (zero_extend:DI
6605 (subreg:HI
6606 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6607 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6608 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6609 "rld%I2cl %0,%1,%H2,48"
6610 [(set_attr "type" "shift")
6611 (set_attr "maybe_var_shift" "yes")])
6613 (define_insn "*rotldi3_internal10be"
6614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6615 (zero_extend:DI
6616 (subreg:HI
6617 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6618 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6619 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6620 "rld%I2cl %0,%1,%H2,48"
6621 [(set_attr "type" "shift")
6622 (set_attr "maybe_var_shift" "yes")])
6624 (define_insn "*rotldi3_internal11le"
6625 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6626 (compare:CC (zero_extend:DI
6627 (subreg:HI
6628 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6629 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6630 (const_int 0)))
6631 (clobber (match_scratch:DI 3 "=r,r"))]
6632 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6633 "@
6634 rld%I2cl. %3,%1,%H2,48
6635 #"
6636 [(set_attr "type" "shift")
6637 (set_attr "maybe_var_shift" "yes")
6638 (set_attr "dot" "yes")
6639 (set_attr "length" "4,8")])
6641 (define_insn "*rotldi3_internal11be"
6642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6643 (compare:CC (zero_extend:DI
6644 (subreg:HI
6645 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6646 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6647 (const_int 0)))
6648 (clobber (match_scratch:DI 3 "=r,r"))]
6649 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6650 "@
6651 rld%I2cl. %3,%1,%H2,48
6652 #"
6653 [(set_attr "type" "shift")
6654 (set_attr "maybe_var_shift" "yes")
6655 (set_attr "dot" "yes")
6656 (set_attr "length" "4,8")])
6658 (define_split
6659 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6660 (compare:CC (zero_extend:DI
6661 (subreg:HI
6662 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6663 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6664 (const_int 0)))
6665 (clobber (match_scratch:DI 3 ""))]
6666 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6667 [(set (match_dup 3)
6668 (zero_extend:DI (subreg:HI
6669 (rotate:DI (match_dup 1)
6670 (match_dup 2)) 0)))
6671 (set (match_dup 0)
6672 (compare:CC (match_dup 3)
6673 (const_int 0)))]
6674 "")
6676 (define_split
6677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6678 (compare:CC (zero_extend:DI
6679 (subreg:HI
6680 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6681 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6682 (const_int 0)))
6683 (clobber (match_scratch:DI 3 ""))]
6684 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6685 [(set (match_dup 3)
6686 (zero_extend:DI (subreg:HI
6687 (rotate:DI (match_dup 1)
6688 (match_dup 2)) 6)))
6689 (set (match_dup 0)
6690 (compare:CC (match_dup 3)
6691 (const_int 0)))]
6692 "")
6694 (define_insn "*rotldi3_internal12le"
6695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6696 (compare:CC (zero_extend:DI
6697 (subreg:HI
6698 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6699 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6700 (const_int 0)))
6701 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6702 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6703 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6704 "@
6705 rld%I2cl. %0,%1,%H2,48
6706 #"
6707 [(set_attr "type" "shift")
6708 (set_attr "maybe_var_shift" "yes")
6709 (set_attr "dot" "yes")
6710 (set_attr "length" "4,8")])
6712 (define_insn "*rotldi3_internal12be"
6713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6714 (compare:CC (zero_extend:DI
6715 (subreg:HI
6716 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6717 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6718 (const_int 0)))
6719 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6720 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6721 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6722 "@
6723 rld%I2cl. %0,%1,%H2,48
6724 #"
6725 [(set_attr "type" "shift")
6726 (set_attr "maybe_var_shift" "yes")
6727 (set_attr "dot" "yes")
6728 (set_attr "length" "4,8")])
6730 (define_split
6731 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6732 (compare:CC (zero_extend:DI
6733 (subreg:HI
6734 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6735 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "")
6738 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6739 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6740 [(set (match_dup 0)
6741 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6742 (set (match_dup 3)
6743 (compare:CC (match_dup 0)
6744 (const_int 0)))]
6745 "")
6747 (define_split
6748 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6749 (compare:CC (zero_extend:DI
6750 (subreg:HI
6751 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6752 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6753 (const_int 0)))
6754 (set (match_operand:DI 0 "gpc_reg_operand" "")
6755 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6756 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6757 [(set (match_dup 0)
6758 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6759 (set (match_dup 3)
6760 (compare:CC (match_dup 0)
6761 (const_int 0)))]
6762 "")
6764 (define_insn "*rotldi3_internal13le"
6765 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6766 (zero_extend:DI
6767 (subreg:SI
6768 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6769 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6770 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6771 "rld%I2cl %0,%1,%H2,32"
6772 [(set_attr "type" "shift")
6773 (set_attr "maybe_var_shift" "yes")])
6775 (define_insn "*rotldi3_internal13be"
6776 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6777 (zero_extend:DI
6778 (subreg:SI
6779 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6780 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6781 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6782 "rld%I2cl %0,%1,%H2,32"
6783 [(set_attr "type" "shift")
6784 (set_attr "maybe_var_shift" "yes")])
6786 (define_insn "*rotldi3_internal14le"
6787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6788 (compare:CC (zero_extend:DI
6789 (subreg:SI
6790 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6791 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6792 (const_int 0)))
6793 (clobber (match_scratch:DI 3 "=r,r"))]
6794 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6795 "@
6796 rld%I2cl. %3,%1,%H2,32
6797 #"
6798 [(set_attr "type" "shift")
6799 (set_attr "maybe_var_shift" "yes")
6800 (set_attr "dot" "yes")
6801 (set_attr "length" "4,8")])
6803 (define_insn "*rotldi3_internal14be"
6804 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6805 (compare:CC (zero_extend:DI
6806 (subreg:SI
6807 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6808 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6809 (const_int 0)))
6810 (clobber (match_scratch:DI 3 "=r,r"))]
6811 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6812 "@
6813 rld%I2cl. %3,%1,%H2,32
6814 #"
6815 [(set_attr "type" "shift")
6816 (set_attr "maybe_var_shift" "yes")
6817 (set_attr "dot" "yes")
6818 (set_attr "length" "4,8")])
6820 (define_split
6821 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6822 (compare:CC (zero_extend:DI
6823 (subreg:SI
6824 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6825 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6826 (const_int 0)))
6827 (clobber (match_scratch:DI 3 ""))]
6828 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6829 [(set (match_dup 3)
6830 (zero_extend:DI (subreg:SI
6831 (rotate:DI (match_dup 1)
6832 (match_dup 2)) 0)))
6833 (set (match_dup 0)
6834 (compare:CC (match_dup 3)
6835 (const_int 0)))]
6836 "")
6838 (define_split
6839 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6840 (compare:CC (zero_extend:DI
6841 (subreg:SI
6842 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6843 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6844 (const_int 0)))
6845 (clobber (match_scratch:DI 3 ""))]
6846 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6847 [(set (match_dup 3)
6848 (zero_extend:DI (subreg:SI
6849 (rotate:DI (match_dup 1)
6850 (match_dup 2)) 4)))
6851 (set (match_dup 0)
6852 (compare:CC (match_dup 3)
6853 (const_int 0)))]
6854 "")
6856 (define_insn "*rotldi3_internal15le"
6857 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6858 (compare:CC (zero_extend:DI
6859 (subreg:SI
6860 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6861 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6862 (const_int 0)))
6863 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6864 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6865 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6866 "@
6867 rld%I2cl. %0,%1,%H2,32
6868 #"
6869 [(set_attr "type" "shift")
6870 (set_attr "maybe_var_shift" "yes")
6871 (set_attr "dot" "yes")
6872 (set_attr "length" "4,8")])
6874 (define_insn "*rotldi3_internal15be"
6875 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6876 (compare:CC (zero_extend:DI
6877 (subreg:SI
6878 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6879 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6880 (const_int 0)))
6881 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6882 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6883 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6884 "@
6885 rld%I2cl. %0,%1,%H2,32
6886 #"
6887 [(set_attr "type" "shift")
6888 (set_attr "maybe_var_shift" "yes")
6889 (set_attr "dot" "yes")
6890 (set_attr "length" "4,8")])
6892 (define_split
6893 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6894 (compare:CC (zero_extend:DI
6895 (subreg:SI
6896 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6897 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6898 (const_int 0)))
6899 (set (match_operand:DI 0 "gpc_reg_operand" "")
6900 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6901 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6902 [(set (match_dup 0)
6903 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6904 (set (match_dup 3)
6905 (compare:CC (match_dup 0)
6906 (const_int 0)))]
6907 "")
6909 (define_split
6910 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6911 (compare:CC (zero_extend:DI
6912 (subreg:SI
6913 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6914 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6915 (const_int 0)))
6916 (set (match_operand:DI 0 "gpc_reg_operand" "")
6917 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6918 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6919 [(set (match_dup 0)
6920 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
6921 (set (match_dup 3)
6922 (compare:CC (match_dup 0)
6923 (const_int 0)))]
6924 "")
6926 (define_insn "*ashldi3_internal4"
6927 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6928 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6929 (match_operand:SI 2 "const_int_operand" "i"))
6930 (match_operand:DI 3 "const_int_operand" "n")))]
6931 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6932 "rldic %0,%1,%H2,%W3"
6933 [(set_attr "type" "shift")])
6935 (define_insn "ashldi3_internal5"
6936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6937 (compare:CC
6938 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6939 (match_operand:SI 2 "const_int_operand" "i,i"))
6940 (match_operand:DI 3 "const_int_operand" "n,n"))
6941 (const_int 0)))
6942 (clobber (match_scratch:DI 4 "=r,r"))]
6943 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6944 "@
6945 rldic. %4,%1,%H2,%W3
6946 #"
6947 [(set_attr "type" "shift")
6948 (set_attr "dot" "yes")
6949 (set_attr "length" "4,8")])
6951 (define_split
6952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6953 (compare:CC
6954 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6955 (match_operand:SI 2 "const_int_operand" ""))
6956 (match_operand:DI 3 "const_int_operand" ""))
6957 (const_int 0)))
6958 (clobber (match_scratch:DI 4 ""))]
6959 "TARGET_POWERPC64 && reload_completed
6960 && includes_rldic_lshift_p (operands[2], operands[3])"
6961 [(set (match_dup 4)
6962 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6963 (match_dup 3)))
6964 (set (match_dup 0)
6965 (compare:CC (match_dup 4)
6966 (const_int 0)))]
6967 "")
6969 (define_insn "*ashldi3_internal6"
6970 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6971 (compare:CC
6972 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6973 (match_operand:SI 2 "const_int_operand" "i,i"))
6974 (match_operand:DI 3 "const_int_operand" "n,n"))
6975 (const_int 0)))
6976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6977 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6978 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6979 "@
6980 rldic. %0,%1,%H2,%W3
6981 #"
6982 [(set_attr "type" "shift")
6983 (set_attr "dot" "yes")
6984 (set_attr "length" "4,8")])
6986 (define_split
6987 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6988 (compare:CC
6989 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6990 (match_operand:SI 2 "const_int_operand" ""))
6991 (match_operand:DI 3 "const_int_operand" ""))
6992 (const_int 0)))
6993 (set (match_operand:DI 0 "gpc_reg_operand" "")
6994 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6995 "TARGET_POWERPC64 && reload_completed
6996 && includes_rldic_lshift_p (operands[2], operands[3])"
6997 [(set (match_dup 0)
6998 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6999 (match_dup 3)))
7000 (set (match_dup 4)
7001 (compare:CC (match_dup 0)
7002 (const_int 0)))]
7003 "")
7005 (define_insn "*ashldi3_internal7"
7006 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7007 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7008 (match_operand:SI 2 "const_int_operand" "i"))
7009 (match_operand:DI 3 "mask64_operand" "n")))]
7010 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7011 "rldicr %0,%1,%H2,%S3"
7012 [(set_attr "type" "shift")])
7014 (define_insn "ashldi3_internal8"
7015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7016 (compare:CC
7017 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7018 (match_operand:SI 2 "const_int_operand" "i,i"))
7019 (match_operand:DI 3 "mask64_operand" "n,n"))
7020 (const_int 0)))
7021 (clobber (match_scratch:DI 4 "=r,r"))]
7022 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7023 "@
7024 rldicr. %4,%1,%H2,%S3
7025 #"
7026 [(set_attr "type" "shift")
7027 (set_attr "dot" "yes")
7028 (set_attr "length" "4,8")])
7030 (define_split
7031 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7032 (compare:CC
7033 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7034 (match_operand:SI 2 "const_int_operand" ""))
7035 (match_operand:DI 3 "mask64_operand" ""))
7036 (const_int 0)))
7037 (clobber (match_scratch:DI 4 ""))]
7038 "TARGET_POWERPC64 && reload_completed
7039 && includes_rldicr_lshift_p (operands[2], operands[3])"
7040 [(set (match_dup 4)
7041 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7042 (match_dup 3)))
7043 (set (match_dup 0)
7044 (compare:CC (match_dup 4)
7045 (const_int 0)))]
7046 "")
7048 (define_insn "*ashldi3_internal9"
7049 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7050 (compare:CC
7051 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7052 (match_operand:SI 2 "const_int_operand" "i,i"))
7053 (match_operand:DI 3 "mask64_operand" "n,n"))
7054 (const_int 0)))
7055 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7056 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7057 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7058 "@
7059 rldicr. %0,%1,%H2,%S3
7060 #"
7061 [(set_attr "type" "shift")
7062 (set_attr "dot" "yes")
7063 (set_attr "length" "4,8")])
7065 (define_split
7066 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7067 (compare:CC
7068 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7069 (match_operand:SI 2 "const_int_operand" ""))
7070 (match_operand:DI 3 "mask64_operand" ""))
7071 (const_int 0)))
7072 (set (match_operand:DI 0 "gpc_reg_operand" "")
7073 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7074 "TARGET_POWERPC64 && reload_completed
7075 && includes_rldicr_lshift_p (operands[2], operands[3])"
7076 [(set (match_dup 0)
7077 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7078 (match_dup 3)))
7079 (set (match_dup 4)
7080 (compare:CC (match_dup 0)
7081 (const_int 0)))]
7082 "")
7085 (define_insn_and_split "*anddi3_2rld"
7086 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7087 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7088 (match_operand:DI 2 "and_2rld_operand" "n")))]
7089 "TARGET_POWERPC64"
7090 "#"
7091 ""
7092 [(set (match_dup 0)
7093 (and:DI (rotate:DI (match_dup 1)
7094 (match_dup 4))
7095 (match_dup 5)))
7096 (set (match_dup 0)
7097 (and:DI (rotate:DI (match_dup 0)
7098 (match_dup 6))
7099 (match_dup 7)))]
7100 {
7101 build_mask64_2_operands (operands[2], &operands[4]);
7102 }
7103 [(set_attr "length" "8")])
7105 (define_insn_and_split "*anddi3_2rld_dot"
7106 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7107 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7108 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7109 (const_int 0)))
7110 (clobber (match_scratch:DI 0 "=r,r"))]
7111 "TARGET_64BIT && rs6000_gen_cell_microcode"
7112 "@
7113 #
7114 #"
7115 "&& reload_completed"
7116 [(set (match_dup 0)
7117 (and:DI (rotate:DI (match_dup 1)
7118 (match_dup 4))
7119 (match_dup 5)))
7120 (parallel [(set (match_dup 3)
7121 (compare:CC (and:DI (rotate:DI (match_dup 0)
7122 (match_dup 6))
7123 (match_dup 7))
7124 (const_int 0)))
7125 (clobber (match_dup 0))])]
7126 {
7127 build_mask64_2_operands (operands[2], &operands[4]);
7128 }
7129 [(set_attr "type" "compare")
7130 (set_attr "dot" "yes")
7131 (set_attr "length" "8,12")])
7133 (define_insn_and_split "*anddi3_2rld_dot2"
7134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7135 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7136 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7137 (const_int 0)))
7138 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7139 (and:DI (match_dup 1)
7140 (match_dup 2)))]
7141 "TARGET_64BIT && rs6000_gen_cell_microcode"
7142 "@
7143 #
7144 #"
7145 "&& reload_completed"
7146 [(set (match_dup 0)
7147 (and:DI (rotate:DI (match_dup 1)
7148 (match_dup 4))
7149 (match_dup 5)))
7150 (parallel [(set (match_dup 3)
7151 (compare:CC (and:DI (rotate:DI (match_dup 0)
7152 (match_dup 6))
7153 (match_dup 7))
7154 (const_int 0)))
7155 (set (match_dup 0)
7156 (and:DI (rotate:DI (match_dup 0)
7157 (match_dup 6))
7158 (match_dup 7)))])]
7159 {
7160 build_mask64_2_operands (operands[2], &operands[4]);
7161 }
7162 [(set_attr "type" "compare")
7163 (set_attr "dot" "yes")
7164 (set_attr "length" "8,12")])
7165 \f
7166 ;; 128-bit logical operations expanders
7168 (define_expand "and<mode>3"
7169 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7170 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7171 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7172 ""
7173 "")
7175 (define_expand "ior<mode>3"
7176 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7177 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7178 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7179 ""
7180 "")
7182 (define_expand "xor<mode>3"
7183 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7184 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7185 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7186 ""
7187 "")
7189 (define_expand "one_cmpl<mode>2"
7190 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7191 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7192 ""
7193 "")
7195 (define_expand "nor<mode>3"
7196 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7197 (and:BOOL_128
7198 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7199 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7200 ""
7201 "")
7203 (define_expand "andc<mode>3"
7204 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7205 (and:BOOL_128
7206 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7207 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7208 ""
7209 "")
7211 ;; Power8 vector logical instructions.
7212 (define_expand "eqv<mode>3"
7213 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7214 (not:BOOL_128
7215 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7216 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7217 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7218 "")
7220 ;; Rewrite nand into canonical form
7221 (define_expand "nand<mode>3"
7222 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7223 (ior:BOOL_128
7224 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7225 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7226 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7227 "")
7229 ;; The canonical form is to have the negated element first, so we need to
7230 ;; reverse arguments.
7231 (define_expand "orc<mode>3"
7232 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7233 (ior:BOOL_128
7234 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7235 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7236 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7237 "")
7239 ;; 128-bit logical operations insns and split operations
7240 (define_insn_and_split "*and<mode>3_internal"
7241 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7242 (and:BOOL_128
7243 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7244 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7245 ""
7246 {
7247 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7248 return "xxland %x0,%x1,%x2";
7250 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7251 return "vand %0,%1,%2";
7253 return "#";
7254 }
7255 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7256 [(const_int 0)]
7257 {
7258 rs6000_split_logical (operands, AND, false, false, false);
7259 DONE;
7260 }
7261 [(set (attr "type")
7262 (if_then_else
7263 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7264 (const_string "vecsimple")
7265 (const_string "integer")))
7266 (set (attr "length")
7267 (if_then_else
7268 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7269 (const_string "4")
7270 (if_then_else
7271 (match_test "TARGET_POWERPC64")
7272 (const_string "8")
7273 (const_string "16"))))])
7275 ;; 128-bit IOR/XOR
7276 (define_insn_and_split "*bool<mode>3_internal"
7277 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7278 (match_operator:BOOL_128 3 "boolean_or_operator"
7279 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7280 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7281 ""
7282 {
7283 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7284 return "xxl%q3 %x0,%x1,%x2";
7286 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7287 return "v%q3 %0,%1,%2";
7289 return "#";
7290 }
7291 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7292 [(const_int 0)]
7293 {
7294 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7295 DONE;
7296 }
7297 [(set (attr "type")
7298 (if_then_else
7299 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7300 (const_string "vecsimple")
7301 (const_string "integer")))
7302 (set (attr "length")
7303 (if_then_else
7304 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7305 (const_string "4")
7306 (if_then_else
7307 (match_test "TARGET_POWERPC64")
7308 (const_string "8")
7309 (const_string "16"))))])
7311 ;; 128-bit ANDC/ORC
7312 (define_insn_and_split "*boolc<mode>3_internal1"
7313 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7314 (match_operator:BOOL_128 3 "boolean_operator"
7315 [(not:BOOL_128
7316 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7317 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7318 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7319 {
7320 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7321 return "xxl%q3 %x0,%x1,%x2";
7323 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7324 return "v%q3 %0,%1,%2";
7326 return "#";
7327 }
7328 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7329 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7330 [(const_int 0)]
7331 {
7332 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7333 DONE;
7334 }
7335 [(set (attr "type")
7336 (if_then_else
7337 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7338 (const_string "vecsimple")
7339 (const_string "integer")))
7340 (set (attr "length")
7341 (if_then_else
7342 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7343 (const_string "4")
7344 (if_then_else
7345 (match_test "TARGET_POWERPC64")
7346 (const_string "8")
7347 (const_string "16"))))])
7349 (define_insn_and_split "*boolc<mode>3_internal2"
7350 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7351 (match_operator:TI2 3 "boolean_operator"
7352 [(not:TI2
7353 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7354 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7355 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7356 "#"
7357 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7358 [(const_int 0)]
7359 {
7360 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7361 DONE;
7362 }
7363 [(set_attr "type" "integer")
7364 (set (attr "length")
7365 (if_then_else
7366 (match_test "TARGET_POWERPC64")
7367 (const_string "8")
7368 (const_string "16")))])
7370 ;; 128-bit NAND/NOR
7371 (define_insn_and_split "*boolcc<mode>3_internal1"
7372 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7373 (match_operator:BOOL_128 3 "boolean_operator"
7374 [(not:BOOL_128
7375 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7376 (not:BOOL_128
7377 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7378 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7379 {
7380 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7381 return "xxl%q3 %x0,%x1,%x2";
7383 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7384 return "v%q3 %0,%1,%2";
7386 return "#";
7387 }
7388 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7389 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7390 [(const_int 0)]
7391 {
7392 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7393 DONE;
7394 }
7395 [(set (attr "type")
7396 (if_then_else
7397 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7398 (const_string "vecsimple")
7399 (const_string "integer")))
7400 (set (attr "length")
7401 (if_then_else
7402 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7403 (const_string "4")
7404 (if_then_else
7405 (match_test "TARGET_POWERPC64")
7406 (const_string "8")
7407 (const_string "16"))))])
7409 (define_insn_and_split "*boolcc<mode>3_internal2"
7410 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7411 (match_operator:TI2 3 "boolean_operator"
7412 [(not:TI2
7413 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7414 (not:TI2
7415 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7416 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7417 "#"
7418 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7419 [(const_int 0)]
7420 {
7421 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7422 DONE;
7423 }
7424 [(set_attr "type" "integer")
7425 (set (attr "length")
7426 (if_then_else
7427 (match_test "TARGET_POWERPC64")
7428 (const_string "8")
7429 (const_string "16")))])
7432 ;; 128-bit EQV
7433 (define_insn_and_split "*eqv<mode>3_internal1"
7434 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7435 (not:BOOL_128
7436 (xor:BOOL_128
7437 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7438 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7439 "TARGET_P8_VECTOR"
7440 {
7441 if (vsx_register_operand (operands[0], <MODE>mode))
7442 return "xxleqv %x0,%x1,%x2";
7444 return "#";
7445 }
7446 "TARGET_P8_VECTOR && reload_completed
7447 && int_reg_operand (operands[0], <MODE>mode)"
7448 [(const_int 0)]
7449 {
7450 rs6000_split_logical (operands, XOR, true, false, false);
7451 DONE;
7452 }
7453 [(set (attr "type")
7454 (if_then_else
7455 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7456 (const_string "vecsimple")
7457 (const_string "integer")))
7458 (set (attr "length")
7459 (if_then_else
7460 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7461 (const_string "4")
7462 (if_then_else
7463 (match_test "TARGET_POWERPC64")
7464 (const_string "8")
7465 (const_string "16"))))])
7467 (define_insn_and_split "*eqv<mode>3_internal2"
7468 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7469 (not:TI2
7470 (xor:TI2
7471 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7472 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7473 "!TARGET_P8_VECTOR"
7474 "#"
7475 "reload_completed && !TARGET_P8_VECTOR"
7476 [(const_int 0)]
7477 {
7478 rs6000_split_logical (operands, XOR, true, false, false);
7479 DONE;
7480 }
7481 [(set_attr "type" "integer")
7482 (set (attr "length")
7483 (if_then_else
7484 (match_test "TARGET_POWERPC64")
7485 (const_string "8")
7486 (const_string "16")))])
7488 ;; 128-bit one's complement
7489 (define_insn_and_split "*one_cmpl<mode>3_internal"
7490 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7491 (not:BOOL_128
7492 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7493 ""
7494 {
7495 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7496 return "xxlnor %x0,%x1,%x1";
7498 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7499 return "vnor %0,%1,%1";
7501 return "#";
7502 }
7503 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7504 [(const_int 0)]
7505 {
7506 rs6000_split_logical (operands, NOT, false, false, false);
7507 DONE;
7508 }
7509 [(set (attr "type")
7510 (if_then_else
7511 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7512 (const_string "vecsimple")
7513 (const_string "integer")))
7514 (set (attr "length")
7515 (if_then_else
7516 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7517 (const_string "4")
7518 (if_then_else
7519 (match_test "TARGET_POWERPC64")
7520 (const_string "8")
7521 (const_string "16"))))])
7523 \f
7524 ;; Now define ways of moving data around.
7526 ;; Set up a register with a value from the GOT table
7528 (define_expand "movsi_got"
7529 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7530 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7531 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7532 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7533 "
7534 {
7535 if (GET_CODE (operands[1]) == CONST)
7536 {
7537 rtx offset = const0_rtx;
7538 HOST_WIDE_INT value;
7540 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7541 value = INTVAL (offset);
7542 if (value != 0)
7543 {
7544 rtx tmp = (!can_create_pseudo_p ()
7545 ? operands[0]
7546 : gen_reg_rtx (Pmode));
7547 emit_insn (gen_movsi_got (tmp, operands[1]));
7548 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7549 DONE;
7550 }
7551 }
7553 operands[2] = rs6000_got_register (operands[1]);
7554 }")
7556 (define_insn "*movsi_got_internal"
7557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7558 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7559 (match_operand:SI 2 "gpc_reg_operand" "b")]
7560 UNSPEC_MOVSI_GOT))]
7561 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7562 "lwz %0,%a1@got(%2)"
7563 [(set_attr "type" "load")])
7565 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7566 ;; didn't get allocated to a hard register.
7567 (define_split
7568 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7569 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7570 (match_operand:SI 2 "memory_operand" "")]
7571 UNSPEC_MOVSI_GOT))]
7572 "DEFAULT_ABI == ABI_V4
7573 && flag_pic == 1
7574 && (reload_in_progress || reload_completed)"
7575 [(set (match_dup 0) (match_dup 2))
7576 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7577 UNSPEC_MOVSI_GOT))]
7578 "")
7580 ;; For SI, we special-case integers that can't be loaded in one insn. We
7581 ;; do the load 16-bits at a time. We could do this by loading from memory,
7582 ;; and this is even supposed to be faster, but it is simpler not to get
7583 ;; integers in the TOC.
7584 (define_insn "movsi_low"
7585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7586 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7587 (match_operand 2 "" ""))))]
7588 "TARGET_MACHO && ! TARGET_64BIT"
7589 "lwz %0,lo16(%2)(%1)"
7590 [(set_attr "type" "load")
7591 (set_attr "length" "4")])
7593 (define_insn "*movsi_internal1"
7594 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7595 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7596 "!TARGET_SINGLE_FPU &&
7597 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7598 "@
7599 mr %0,%1
7600 la %0,%a1
7601 lwz%U1%X1 %0,%1
7602 stw%U0%X0 %1,%0
7603 li %0,%1
7604 lis %0,%v1
7605 #
7606 mf%1 %0
7607 mt%0 %1
7608 mt%0 %1
7609 nop"
7610 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7611 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7613 (define_insn "*movsi_internal1_single"
7614 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7615 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7616 "TARGET_SINGLE_FPU &&
7617 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7618 "@
7619 mr %0,%1
7620 la %0,%a1
7621 lwz%U1%X1 %0,%1
7622 stw%U0%X0 %1,%0
7623 li %0,%1
7624 lis %0,%v1
7625 #
7626 mf%1 %0
7627 mt%0 %1
7628 mt%0 %1
7629 nop
7630 stfs%U0%X0 %1,%0
7631 lfs%U1%X1 %0,%1"
7632 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7633 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7635 ;; Split a load of a large constant into the appropriate two-insn
7636 ;; sequence.
7638 (define_split
7639 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7640 (match_operand:SI 1 "const_int_operand" ""))]
7641 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7642 && (INTVAL (operands[1]) & 0xffff) != 0"
7643 [(set (match_dup 0)
7644 (match_dup 2))
7645 (set (match_dup 0)
7646 (ior:SI (match_dup 0)
7647 (match_dup 3)))]
7648 "
7649 {
7650 if (rs6000_emit_set_const (operands[0], operands[1]))
7651 DONE;
7652 else
7653 FAIL;
7654 }")
7656 (define_insn "*mov<mode>_internal2"
7657 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7658 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7659 (const_int 0)))
7660 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7661 ""
7662 "@
7663 cmp<wd>i %2,%0,0
7664 mr. %0,%1
7665 #"
7666 [(set_attr "type" "cmp,logical,cmp")
7667 (set_attr "dot" "yes")
7668 (set_attr "length" "4,4,8")])
7670 (define_split
7671 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7672 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7673 (const_int 0)))
7674 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7675 "reload_completed"
7676 [(set (match_dup 0) (match_dup 1))
7677 (set (match_dup 2)
7678 (compare:CC (match_dup 0)
7679 (const_int 0)))]
7680 "")
7681 \f
7682 (define_insn "*movhi_internal"
7683 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7684 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7685 "gpc_reg_operand (operands[0], HImode)
7686 || gpc_reg_operand (operands[1], HImode)"
7687 "@
7688 mr %0,%1
7689 lhz%U1%X1 %0,%1
7690 sth%U0%X0 %1,%0
7691 li %0,%w1
7692 mf%1 %0
7693 mt%0 %1
7694 nop"
7695 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7697 (define_expand "mov<mode>"
7698 [(set (match_operand:INT 0 "general_operand" "")
7699 (match_operand:INT 1 "any_operand" ""))]
7700 ""
7701 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7703 (define_insn "*movqi_internal"
7704 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7705 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7706 "gpc_reg_operand (operands[0], QImode)
7707 || gpc_reg_operand (operands[1], QImode)"
7708 "@
7709 mr %0,%1
7710 lbz%U1%X1 %0,%1
7711 stb%U0%X0 %1,%0
7712 li %0,%1
7713 mf%1 %0
7714 mt%0 %1
7715 nop"
7716 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7717 \f
7718 ;; Here is how to move condition codes around. When we store CC data in
7719 ;; an integer register or memory, we store just the high-order 4 bits.
7720 ;; This lets us not shift in the most common case of CR0.
7721 (define_expand "movcc"
7722 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7723 (match_operand:CC 1 "nonimmediate_operand" ""))]
7724 ""
7725 "")
7727 (define_insn "*movcc_internal1"
7728 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7729 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7730 "register_operand (operands[0], CCmode)
7731 || register_operand (operands[1], CCmode)"
7732 "@
7733 mcrf %0,%1
7734 mtcrf 128,%1
7735 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7736 crxor %0,%0,%0
7737 mfcr %0%Q1
7738 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7739 mr %0,%1
7740 li %0,%1
7741 mf%1 %0
7742 mt%0 %1
7743 lwz%U1%X1 %0,%1
7744 stw%U0%X0 %1,%0"
7745 [(set (attr "type")
7746 (cond [(eq_attr "alternative" "0,3")
7747 (const_string "cr_logical")
7748 (eq_attr "alternative" "1,2")
7749 (const_string "mtcr")
7750 (eq_attr "alternative" "6,7")
7751 (const_string "integer")
7752 (eq_attr "alternative" "8")
7753 (const_string "mfjmpr")
7754 (eq_attr "alternative" "9")
7755 (const_string "mtjmpr")
7756 (eq_attr "alternative" "10")
7757 (const_string "load")
7758 (eq_attr "alternative" "11")
7759 (const_string "store")
7760 (match_test "TARGET_MFCRF")
7761 (const_string "mfcrf")
7762 ]
7763 (const_string "mfcr")))
7764 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7765 \f
7766 ;; For floating-point, we normally deal with the floating-point registers
7767 ;; unless -msoft-float is used. The sole exception is that parameter passing
7768 ;; can produce floating-point values in fixed-point registers. Unless the
7769 ;; value is a simple constant or already in memory, we deal with this by
7770 ;; allocating memory and copying the value explicitly via that memory location.
7772 ;; Move 32-bit binary/decimal floating point
7773 (define_expand "mov<mode>"
7774 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7775 (match_operand:FMOVE32 1 "any_operand" ""))]
7776 "<fmove_ok>"
7777 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7779 (define_split
7780 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7781 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7782 "reload_completed
7783 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7784 || (GET_CODE (operands[0]) == SUBREG
7785 && GET_CODE (SUBREG_REG (operands[0])) == REG
7786 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7787 [(set (match_dup 2) (match_dup 3))]
7788 "
7789 {
7790 long l;
7791 REAL_VALUE_TYPE rv;
7793 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7794 <real_value_to_target> (rv, l);
7796 if (! TARGET_POWERPC64)
7797 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7798 else
7799 operands[2] = gen_lowpart (SImode, operands[0]);
7801 operands[3] = gen_int_mode (l, SImode);
7802 }")
7804 (define_insn "mov<mode>_hardfloat"
7805 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7806 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
7807 "(gpc_reg_operand (operands[0], <MODE>mode)
7808 || gpc_reg_operand (operands[1], <MODE>mode))
7809 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7810 "@
7811 mr %0,%1
7812 lwz%U1%X1 %0,%1
7813 stw%U0%X0 %1,%0
7814 fmr %0,%1
7815 xxlor %x0,%x1,%x1
7816 xxlxor %x0,%x0,%x0
7817 <f32_li>
7818 <f32_si>
7819 <f32_lv>
7820 <f32_sv>
7821 mtvsrwz %x0,%1
7822 mfvsrwz %0,%x1
7823 mt%0 %1
7824 mf%1 %0
7825 nop
7826 #
7827 #"
7828 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7829 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7831 (define_insn "*mov<mode>_softfloat"
7832 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7833 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7834 "(gpc_reg_operand (operands[0], <MODE>mode)
7835 || gpc_reg_operand (operands[1], <MODE>mode))
7836 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7837 "@
7838 mr %0,%1
7839 mt%0 %1
7840 mf%1 %0
7841 lwz%U1%X1 %0,%1
7842 stw%U0%X0 %1,%0
7843 li %0,%1
7844 lis %0,%v1
7845 #
7846 #
7847 nop"
7848 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7849 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7851 \f
7852 ;; Move 64-bit binary/decimal floating point
7853 (define_expand "mov<mode>"
7854 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7855 (match_operand:FMOVE64 1 "any_operand" ""))]
7856 ""
7857 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7859 (define_split
7860 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7861 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7862 "! TARGET_POWERPC64 && reload_completed
7863 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7864 || (GET_CODE (operands[0]) == SUBREG
7865 && GET_CODE (SUBREG_REG (operands[0])) == REG
7866 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7867 [(set (match_dup 2) (match_dup 4))
7868 (set (match_dup 3) (match_dup 1))]
7869 "
7870 {
7871 int endian = (WORDS_BIG_ENDIAN == 0);
7872 HOST_WIDE_INT value = INTVAL (operands[1]);
7874 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7875 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7876 operands[4] = GEN_INT (value >> 32);
7877 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7878 }")
7880 (define_split
7881 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7882 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7883 "! TARGET_POWERPC64 && reload_completed
7884 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7885 || (GET_CODE (operands[0]) == SUBREG
7886 && GET_CODE (SUBREG_REG (operands[0])) == REG
7887 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7888 [(set (match_dup 2) (match_dup 4))
7889 (set (match_dup 3) (match_dup 5))]
7890 "
7891 {
7892 int endian = (WORDS_BIG_ENDIAN == 0);
7893 long l[2];
7894 REAL_VALUE_TYPE rv;
7896 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7897 <real_value_to_target> (rv, l);
7899 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7900 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7901 operands[4] = gen_int_mode (l[endian], SImode);
7902 operands[5] = gen_int_mode (l[1 - endian], SImode);
7903 }")
7905 (define_split
7906 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7907 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7908 "TARGET_POWERPC64 && reload_completed
7909 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7910 || (GET_CODE (operands[0]) == SUBREG
7911 && GET_CODE (SUBREG_REG (operands[0])) == REG
7912 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7913 [(set (match_dup 2) (match_dup 3))]
7914 "
7915 {
7916 int endian = (WORDS_BIG_ENDIAN == 0);
7917 long l[2];
7918 REAL_VALUE_TYPE rv;
7919 HOST_WIDE_INT val;
7921 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7922 <real_value_to_target> (rv, l);
7924 operands[2] = gen_lowpart (DImode, operands[0]);
7925 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7926 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7927 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7929 operands[3] = gen_int_mode (val, DImode);
7930 }")
7932 ;; Don't have reload use general registers to load a constant. It is
7933 ;; less efficient than loading the constant into an FP register, since
7934 ;; it will probably be used there.
7936 ;; The move constraints are ordered to prefer floating point registers before
7937 ;; general purpose registers to avoid doing a store and a load to get the value
7938 ;; into a floating point register when it is needed for a floating point
7939 ;; operation. Prefer traditional floating point registers over VSX registers,
7940 ;; since the D-form version of the memory instructions does not need a GPR for
7941 ;; reloading.
7943 (define_insn "*mov<mode>_hardfloat32"
7944 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
7945 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
7946 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7947 && (gpc_reg_operand (operands[0], <MODE>mode)
7948 || gpc_reg_operand (operands[1], <MODE>mode))"
7949 "@
7950 stfd%U0%X0 %1,%0
7951 lfd%U1%X1 %0,%1
7952 fmr %0,%1
7953 lxsd%U1x %x0,%y1
7954 stxsd%U0x %x1,%y0
7955 xxlor %x0,%x1,%x1
7956 xxlxor %x0,%x0,%x0
7957 #
7958 #
7959 #
7960 #
7961 #
7962 #"
7963 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
7964 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
7966 (define_insn "*mov<mode>_softfloat32"
7967 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
7968 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
7969 "! TARGET_POWERPC64
7970 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
7971 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
7972 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
7973 && (gpc_reg_operand (operands[0], <MODE>mode)
7974 || gpc_reg_operand (operands[1], <MODE>mode))"
7975 "#"
7976 [(set_attr "type" "store,load,two,*,*,*")
7977 (set_attr "length" "8,8,8,8,12,16")])
7979 ; ld/std require word-aligned displacements -> 'Y' constraint.
7980 ; List Y->r and r->Y before r->r for reload.
7981 (define_insn "*mov<mode>_hardfloat64"
7982 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
7983 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
7984 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7985 && (gpc_reg_operand (operands[0], <MODE>mode)
7986 || gpc_reg_operand (operands[1], <MODE>mode))"
7987 "@
7988 stfd%U0%X0 %1,%0
7989 lfd%U1%X1 %0,%1
7990 fmr %0,%1
7991 lxsd%U1x %x0,%y1
7992 stxsd%U0x %x1,%y0
7993 xxlor %x0,%x1,%x1
7994 xxlxor %x0,%x0,%x0
7995 std%U0%X0 %1,%0
7996 ld%U1%X1 %0,%1
7997 mr %0,%1
7998 mt%0 %1
7999 mf%1 %0
8000 nop
8001 #
8002 #
8003 #
8004 mftgpr %0,%1
8005 mffgpr %0,%1
8006 mfvsrd %0,%x1
8007 mtvsrd %x0,%1"
8008 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8009 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8011 (define_insn "*mov<mode>_softfloat64"
8012 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8013 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8014 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8015 && (gpc_reg_operand (operands[0], <MODE>mode)
8016 || gpc_reg_operand (operands[1], <MODE>mode))"
8017 "@
8018 std%U0%X0 %1,%0
8019 ld%U1%X1 %0,%1
8020 mr %0,%1
8021 mt%0 %1
8022 mf%1 %0
8023 #
8024 #
8025 #
8026 nop"
8027 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8028 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8029 \f
8030 (define_expand "mov<mode>"
8031 [(set (match_operand:FMOVE128 0 "general_operand" "")
8032 (match_operand:FMOVE128 1 "any_operand" ""))]
8033 ""
8034 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8036 ;; It's important to list Y->r and r->Y before r->r because otherwise
8037 ;; reload, given m->r, will try to pick r->r and reload it, which
8038 ;; doesn't make progress.
8040 ;; We can't split little endian direct moves of TDmode, because the words are
8041 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8042 ;; problematical. Don't allow direct move for this case.
8044 (define_insn_and_split "*mov<mode>_64bit_dm"
8045 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8046 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8047 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8048 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8049 && (gpc_reg_operand (operands[0], <MODE>mode)
8050 || gpc_reg_operand (operands[1], <MODE>mode))"
8051 "#"
8052 "&& reload_completed"
8053 [(pc)]
8054 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8055 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8057 (define_insn_and_split "*movtd_64bit_nodm"
8058 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8059 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8060 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8061 && (gpc_reg_operand (operands[0], TDmode)
8062 || gpc_reg_operand (operands[1], TDmode))"
8063 "#"
8064 "&& reload_completed"
8065 [(pc)]
8066 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8067 [(set_attr "length" "8,8,8,12,12,8")])
8069 (define_insn_and_split "*mov<mode>_32bit"
8070 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8071 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8072 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8073 && (gpc_reg_operand (operands[0], <MODE>mode)
8074 || gpc_reg_operand (operands[1], <MODE>mode))"
8075 "#"
8076 "&& reload_completed"
8077 [(pc)]
8078 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8079 [(set_attr "length" "8,8,8,20,20,16")])
8081 (define_insn_and_split "*mov<mode>_softfloat"
8082 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8083 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8084 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8085 && (gpc_reg_operand (operands[0], <MODE>mode)
8086 || gpc_reg_operand (operands[1], <MODE>mode))"
8087 "#"
8088 "&& reload_completed"
8089 [(pc)]
8090 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8091 [(set_attr "length" "20,20,16")])
8093 (define_expand "extenddftf2"
8094 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8095 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8096 "!TARGET_IEEEQUAD
8097 && TARGET_HARD_FLOAT
8098 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8099 && TARGET_LONG_DOUBLE_128"
8100 {
8101 if (TARGET_E500_DOUBLE)
8102 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8103 else
8104 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8105 DONE;
8106 })
8108 (define_expand "extenddftf2_fprs"
8109 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8110 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8111 (use (match_dup 2))])]
8112 "!TARGET_IEEEQUAD
8113 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8114 && TARGET_LONG_DOUBLE_128"
8115 {
8116 operands[2] = CONST0_RTX (DFmode);
8117 /* Generate GOT reference early for SVR4 PIC. */
8118 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8119 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8120 })
8122 (define_insn_and_split "*extenddftf2_internal"
8123 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8124 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8125 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8126 "!TARGET_IEEEQUAD
8127 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8128 && TARGET_LONG_DOUBLE_128"
8129 "#"
8130 "&& reload_completed"
8131 [(pc)]
8132 {
8133 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8134 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8135 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8136 operands[1]);
8137 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8138 operands[2]);
8139 DONE;
8140 })
8142 (define_expand "extendsftf2"
8143 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8144 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8145 "!TARGET_IEEEQUAD
8146 && TARGET_HARD_FLOAT
8147 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8148 && TARGET_LONG_DOUBLE_128"
8149 {
8150 rtx tmp = gen_reg_rtx (DFmode);
8151 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8152 emit_insn (gen_extenddftf2 (operands[0], tmp));
8153 DONE;
8154 })
8156 (define_expand "trunctfdf2"
8157 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8158 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8159 "!TARGET_IEEEQUAD
8160 && TARGET_HARD_FLOAT
8161 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8162 && TARGET_LONG_DOUBLE_128"
8163 "")
8165 (define_insn_and_split "trunctfdf2_internal1"
8166 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8167 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8168 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8169 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8170 "@
8171 #
8172 fmr %0,%1"
8173 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8174 [(const_int 0)]
8175 {
8176 emit_note (NOTE_INSN_DELETED);
8177 DONE;
8178 }
8179 [(set_attr "type" "fp")])
8181 (define_insn "trunctfdf2_internal2"
8182 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8183 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8184 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8185 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8186 && TARGET_LONG_DOUBLE_128"
8187 "fadd %0,%1,%L1"
8188 [(set_attr "type" "fp")
8189 (set_attr "fp_type" "fp_addsub_d")])
8191 (define_expand "trunctfsf2"
8192 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8193 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8194 "!TARGET_IEEEQUAD
8195 && TARGET_HARD_FLOAT
8196 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8197 && TARGET_LONG_DOUBLE_128"
8198 {
8199 if (TARGET_E500_DOUBLE)
8200 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8201 else
8202 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8203 DONE;
8204 })
8206 (define_insn_and_split "trunctfsf2_fprs"
8207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8208 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8209 (clobber (match_scratch:DF 2 "=d"))]
8210 "!TARGET_IEEEQUAD
8211 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8212 && TARGET_LONG_DOUBLE_128"
8213 "#"
8214 "&& reload_completed"
8215 [(set (match_dup 2)
8216 (float_truncate:DF (match_dup 1)))
8217 (set (match_dup 0)
8218 (float_truncate:SF (match_dup 2)))]
8219 "")
8221 (define_expand "floatsitf2"
8222 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8223 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8224 "!TARGET_IEEEQUAD
8225 && TARGET_HARD_FLOAT
8226 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8227 && TARGET_LONG_DOUBLE_128"
8228 {
8229 rtx tmp = gen_reg_rtx (DFmode);
8230 expand_float (tmp, operands[1], false);
8231 emit_insn (gen_extenddftf2 (operands[0], tmp));
8232 DONE;
8233 })
8235 ; fadd, but rounding towards zero.
8236 ; This is probably not the optimal code sequence.
8237 (define_insn "fix_trunc_helper"
8238 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8239 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8240 UNSPEC_FIX_TRUNC_TF))
8241 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8242 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8243 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8244 [(set_attr "type" "fp")
8245 (set_attr "length" "20")])
8247 (define_expand "fix_trunctfsi2"
8248 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8249 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8250 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8251 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8252 {
8253 if (TARGET_E500_DOUBLE)
8254 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8255 else
8256 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8257 DONE;
8258 })
8260 (define_expand "fix_trunctfsi2_fprs"
8261 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8262 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8263 (clobber (match_dup 2))
8264 (clobber (match_dup 3))
8265 (clobber (match_dup 4))
8266 (clobber (match_dup 5))])]
8267 "!TARGET_IEEEQUAD
8268 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8269 {
8270 operands[2] = gen_reg_rtx (DFmode);
8271 operands[3] = gen_reg_rtx (DFmode);
8272 operands[4] = gen_reg_rtx (DImode);
8273 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8274 })
8276 (define_insn_and_split "*fix_trunctfsi2_internal"
8277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8278 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8279 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8280 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8281 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8282 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8283 "!TARGET_IEEEQUAD
8284 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8285 "#"
8286 ""
8287 [(pc)]
8288 {
8289 rtx lowword;
8290 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8292 gcc_assert (MEM_P (operands[5]));
8293 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8295 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8296 emit_move_insn (operands[5], operands[4]);
8297 emit_move_insn (operands[0], lowword);
8298 DONE;
8299 })
8301 (define_expand "negtf2"
8302 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8303 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8304 "!TARGET_IEEEQUAD
8305 && TARGET_HARD_FLOAT
8306 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8307 && TARGET_LONG_DOUBLE_128"
8308 "")
8310 (define_insn "negtf2_internal"
8311 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8312 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8313 "!TARGET_IEEEQUAD
8314 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8315 "*
8316 {
8317 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8318 return \"fneg %L0,%L1\;fneg %0,%1\";
8319 else
8320 return \"fneg %0,%1\;fneg %L0,%L1\";
8321 }"
8322 [(set_attr "type" "fp")
8323 (set_attr "length" "8")])
8325 (define_expand "abstf2"
8326 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8327 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8328 "!TARGET_IEEEQUAD
8329 && TARGET_HARD_FLOAT
8330 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8331 && TARGET_LONG_DOUBLE_128"
8332 "
8333 {
8334 rtx label = gen_label_rtx ();
8335 if (TARGET_E500_DOUBLE)
8336 {
8337 if (flag_finite_math_only && !flag_trapping_math)
8338 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8339 else
8340 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8341 }
8342 else
8343 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8344 emit_label (label);
8345 DONE;
8346 }")
8348 (define_expand "abstf2_internal"
8349 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8350 (match_operand:TF 1 "gpc_reg_operand" ""))
8351 (set (match_dup 3) (match_dup 5))
8352 (set (match_dup 5) (abs:DF (match_dup 5)))
8353 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8354 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8355 (label_ref (match_operand 2 "" ""))
8356 (pc)))
8357 (set (match_dup 6) (neg:DF (match_dup 6)))]
8358 "!TARGET_IEEEQUAD
8359 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8360 && TARGET_LONG_DOUBLE_128"
8361 "
8362 {
8363 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8364 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8365 operands[3] = gen_reg_rtx (DFmode);
8366 operands[4] = gen_reg_rtx (CCFPmode);
8367 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8368 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8369 }")
8370 \f
8371 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8372 ;; must have 3 arguments, and scratch register constraint must be a single
8373 ;; constraint.
8375 ;; Reload patterns to support gpr load/store with misaligned mem.
8376 ;; and multiple gpr load/store at offset >= 0xfffc
8377 (define_expand "reload_<mode>_store"
8378 [(parallel [(match_operand 0 "memory_operand" "=m")
8379 (match_operand 1 "gpc_reg_operand" "r")
8380 (match_operand:GPR 2 "register_operand" "=&b")])]
8381 ""
8382 {
8383 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8384 DONE;
8385 })
8387 (define_expand "reload_<mode>_load"
8388 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8389 (match_operand 1 "memory_operand" "m")
8390 (match_operand:GPR 2 "register_operand" "=b")])]
8391 ""
8392 {
8393 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8394 DONE;
8395 })
8397 \f
8398 ;; Power8 merge instructions to allow direct move to/from floating point
8399 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8400 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8401 ;; value, since it is allocated in reload and not all of the flow information
8402 ;; is setup for it. We have two patterns to do the two moves between gprs and
8403 ;; fprs. There isn't a dependancy between the two, but we could potentially
8404 ;; schedule other instructions between the two instructions. TFmode is
8405 ;; currently limited to traditional FPR registers. If/when this is changed, we
8406 ;; will need to revist %L to make sure it works with VSX registers, or add an
8407 ;; %x version of %L.
8409 (define_insn "p8_fmrgow_<mode>"
8410 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8411 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8412 UNSPEC_P8V_FMRGOW))]
8413 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8414 "fmrgow %0,%1,%L1"
8415 [(set_attr "type" "vecperm")])
8417 (define_insn "p8_mtvsrwz_1"
8418 [(set (match_operand:TF 0 "register_operand" "=d")
8419 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8420 UNSPEC_P8V_MTVSRWZ))]
8421 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8422 "mtvsrwz %x0,%1"
8423 [(set_attr "type" "mftgpr")])
8425 (define_insn "p8_mtvsrwz_2"
8426 [(set (match_operand:TF 0 "register_operand" "+d")
8427 (unspec:TF [(match_dup 0)
8428 (match_operand:SI 1 "register_operand" "r")]
8429 UNSPEC_P8V_MTVSRWZ))]
8430 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8431 "mtvsrwz %L0,%1"
8432 [(set_attr "type" "mftgpr")])
8434 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8435 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8436 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8437 UNSPEC_P8V_RELOAD_FROM_GPR))
8438 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8439 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8440 "#"
8441 "&& reload_completed"
8442 [(const_int 0)]
8443 {
8444 rtx dest = operands[0];
8445 rtx src = operands[1];
8446 rtx tmp = operands[2];
8447 rtx gpr_hi_reg = gen_highpart (SImode, src);
8448 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8450 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8451 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8452 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8453 DONE;
8454 }
8455 [(set_attr "length" "12")
8456 (set_attr "type" "three")])
8458 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8459 (define_insn "p8_mtvsrd_1"
8460 [(set (match_operand:TF 0 "register_operand" "=ws")
8461 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8462 UNSPEC_P8V_MTVSRD))]
8463 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8464 "mtvsrd %0,%1"
8465 [(set_attr "type" "mftgpr")])
8467 (define_insn "p8_mtvsrd_2"
8468 [(set (match_operand:TF 0 "register_operand" "+ws")
8469 (unspec:TF [(match_dup 0)
8470 (match_operand:DI 1 "register_operand" "r")]
8471 UNSPEC_P8V_MTVSRD))]
8472 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8473 "mtvsrd %L0,%1"
8474 [(set_attr "type" "mftgpr")])
8476 (define_insn "p8_xxpermdi_<mode>"
8477 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8478 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8479 UNSPEC_P8V_XXPERMDI))]
8480 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8481 "xxpermdi %x0,%1,%L1,0"
8482 [(set_attr "type" "vecperm")])
8484 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8485 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8486 (unspec:FMOVE128_GPR
8487 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8488 UNSPEC_P8V_RELOAD_FROM_GPR))
8489 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8490 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8491 "#"
8492 "&& reload_completed"
8493 [(const_int 0)]
8494 {
8495 rtx dest = operands[0];
8496 rtx src = operands[1];
8497 rtx tmp = operands[2];
8498 rtx gpr_hi_reg = gen_highpart (DImode, src);
8499 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8501 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8502 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8503 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8504 }
8505 [(set_attr "length" "12")
8506 (set_attr "type" "three")])
8508 (define_split
8509 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8510 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8511 "reload_completed
8512 && (int_reg_operand (operands[0], <MODE>mode)
8513 || int_reg_operand (operands[1], <MODE>mode))"
8514 [(pc)]
8515 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8517 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8518 ;; type is stored internally as double precision in the VSX registers, we have
8519 ;; to convert it from the vector format.
8521 (define_insn_and_split "reload_vsx_from_gprsf"
8522 [(set (match_operand:SF 0 "register_operand" "=wa")
8523 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8524 UNSPEC_P8V_RELOAD_FROM_GPR))
8525 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8526 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8527 "#"
8528 "&& reload_completed"
8529 [(const_int 0)]
8530 {
8531 rtx op0 = operands[0];
8532 rtx op1 = operands[1];
8533 rtx op2 = operands[2];
8534 /* Also use the destination register to hold the unconverted DImode value.
8535 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8536 rather than simplify_gen_subreg. */
8537 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8538 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8540 /* Move SF value to upper 32-bits for xscvspdpn. */
8541 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8542 emit_move_insn (op0_di, op2);
8543 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8544 DONE;
8545 }
8546 [(set_attr "length" "8")
8547 (set_attr "type" "two")])
8549 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8550 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8551 ;; and then doing a move of that.
8552 (define_insn "p8_mfvsrd_3_<mode>"
8553 [(set (match_operand:DF 0 "register_operand" "=r")
8554 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8555 UNSPEC_P8V_RELOAD_FROM_VSX))]
8556 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8557 "mfvsrd %0,%x1"
8558 [(set_attr "type" "mftgpr")])
8560 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8561 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8562 (unspec:FMOVE128_GPR
8563 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8564 UNSPEC_P8V_RELOAD_FROM_VSX))
8565 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8566 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8567 "#"
8568 "&& reload_completed"
8569 [(const_int 0)]
8570 {
8571 rtx dest = operands[0];
8572 rtx src = operands[1];
8573 rtx tmp = operands[2];
8574 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8575 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8577 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8578 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8579 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8580 }
8581 [(set_attr "length" "12")
8582 (set_attr "type" "three")])
8584 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8585 ;; type is stored internally as double precision, we have to convert it to the
8586 ;; vector format.
8588 (define_insn_and_split "reload_gpr_from_vsxsf"
8589 [(set (match_operand:SF 0 "register_operand" "=r")
8590 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8591 UNSPEC_P8V_RELOAD_FROM_VSX))
8592 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8593 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8594 "#"
8595 "&& reload_completed"
8596 [(const_int 0)]
8597 {
8598 rtx op0 = operands[0];
8599 rtx op1 = operands[1];
8600 rtx op2 = operands[2];
8601 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8603 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8604 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8605 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8606 DONE;
8607 }
8608 [(set_attr "length" "12")
8609 (set_attr "type" "three")])
8611 (define_insn "p8_mfvsrd_4_disf"
8612 [(set (match_operand:DI 0 "register_operand" "=r")
8613 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8614 UNSPEC_P8V_RELOAD_FROM_VSX))]
8615 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8616 "mfvsrd %0,%x1"
8617 [(set_attr "type" "mftgpr")])
8619 \f
8620 ;; Next come the multi-word integer load and store and the load and store
8621 ;; multiple insns.
8623 ;; List r->r after r->Y, otherwise reload will try to reload a
8624 ;; non-offsettable address by using r->r which won't make progress.
8625 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8626 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8627 (define_insn "*movdi_internal32"
8628 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8629 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8630 "! TARGET_POWERPC64
8631 && (gpc_reg_operand (operands[0], DImode)
8632 || gpc_reg_operand (operands[1], DImode))"
8633 "@
8634 #
8635 #
8636 #
8637 stfd%U0%X0 %1,%0
8638 lfd%U1%X1 %0,%1
8639 fmr %0,%1
8640 #"
8641 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8643 (define_split
8644 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8645 (match_operand:DI 1 "const_int_operand" ""))]
8646 "! TARGET_POWERPC64 && reload_completed
8647 && gpr_or_gpr_p (operands[0], operands[1])
8648 && !direct_move_p (operands[0], operands[1])"
8649 [(set (match_dup 2) (match_dup 4))
8650 (set (match_dup 3) (match_dup 1))]
8651 "
8652 {
8653 HOST_WIDE_INT value = INTVAL (operands[1]);
8654 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8655 DImode);
8656 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8657 DImode);
8658 operands[4] = GEN_INT (value >> 32);
8659 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8660 }")
8662 (define_split
8663 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8664 (match_operand:DIFD 1 "input_operand" ""))]
8665 "reload_completed && !TARGET_POWERPC64
8666 && gpr_or_gpr_p (operands[0], operands[1])
8667 && !direct_move_p (operands[0], operands[1])"
8668 [(pc)]
8669 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8671 (define_insn "*movdi_internal64"
8672 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8673 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8674 "TARGET_POWERPC64
8675 && (gpc_reg_operand (operands[0], DImode)
8676 || gpc_reg_operand (operands[1], DImode))"
8677 "@
8678 std%U0%X0 %1,%0
8679 ld%U1%X1 %0,%1
8680 mr %0,%1
8681 li %0,%1
8682 lis %0,%v1
8683 #
8684 stfd%U0%X0 %1,%0
8685 lfd%U1%X1 %0,%1
8686 fmr %0,%1
8687 mf%1 %0
8688 mt%0 %1
8689 nop
8690 mftgpr %0,%1
8691 mffgpr %0,%1
8692 mfvsrd %0,%x1
8693 mtvsrd %x0,%1
8694 xxlxor %x0,%x0,%x0"
8695 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8696 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8698 ;; Generate all one-bits and clear left or right.
8699 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8700 (define_split
8701 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8702 (match_operand:DI 1 "mask64_operand" ""))]
8703 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8704 [(set (match_dup 0) (const_int -1))
8705 (set (match_dup 0)
8706 (and:DI (rotate:DI (match_dup 0)
8707 (const_int 0))
8708 (match_dup 1)))]
8709 "")
8711 ;; Split a load of a large constant into the appropriate five-instruction
8712 ;; sequence. Handle anything in a constant number of insns.
8713 ;; When non-easy constants can go in the TOC, this should use
8714 ;; easy_fp_constant predicate.
8715 (define_split
8716 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8717 (match_operand:DI 1 "const_int_operand" ""))]
8718 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8719 [(set (match_dup 0) (match_dup 2))
8720 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8721 "
8722 {
8723 if (rs6000_emit_set_const (operands[0], operands[1]))
8724 DONE;
8725 else
8726 FAIL;
8727 }")
8729 (define_split
8730 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8731 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8732 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8733 [(set (match_dup 0) (match_dup 2))
8734 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8735 "
8736 {
8737 if (rs6000_emit_set_const (operands[0], operands[1]))
8738 DONE;
8739 else
8740 FAIL;
8741 }")
8742 \f
8743 ;; TImode/PTImode is similar, except that we usually want to compute the
8744 ;; address into a register and use lsi/stsi (the exception is during reload).
8746 (define_insn "*mov<mode>_string"
8747 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8748 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8749 "! TARGET_POWERPC64
8750 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8751 && (gpc_reg_operand (operands[0], <MODE>mode)
8752 || gpc_reg_operand (operands[1], <MODE>mode))"
8753 "*
8754 {
8755 switch (which_alternative)
8756 {
8757 default:
8758 gcc_unreachable ();
8759 case 0:
8760 if (TARGET_STRING)
8761 return \"stswi %1,%P0,16\";
8762 case 1:
8763 return \"#\";
8764 case 2:
8765 /* If the address is not used in the output, we can use lsi. Otherwise,
8766 fall through to generating four loads. */
8767 if (TARGET_STRING
8768 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8769 return \"lswi %0,%P1,16\";
8770 /* ... fall through ... */
8771 case 3:
8772 case 4:
8773 case 5:
8774 return \"#\";
8775 }
8776 }"
8777 [(set_attr "type" "store,store,load,load,*,*")
8778 (set_attr "update" "yes")
8779 (set_attr "indexed" "yes")
8780 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8781 (const_string "always")
8782 (const_string "conditional")))])
8784 (define_insn "*mov<mode>_ppc64"
8785 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8786 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8787 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8788 && (gpc_reg_operand (operands[0], <MODE>mode)
8789 || gpc_reg_operand (operands[1], <MODE>mode)))"
8790 {
8791 return rs6000_output_move_128bit (operands);
8792 }
8793 [(set_attr "type" "store,store,load,load,*,*")
8794 (set_attr "length" "8")])
8796 (define_split
8797 [(set (match_operand:TI2 0 "int_reg_operand" "")
8798 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8799 "TARGET_POWERPC64
8800 && (VECTOR_MEM_NONE_P (<MODE>mode)
8801 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8802 [(set (match_dup 2) (match_dup 4))
8803 (set (match_dup 3) (match_dup 5))]
8804 "
8805 {
8806 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8807 <MODE>mode);
8808 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8809 <MODE>mode);
8810 if (CONST_WIDE_INT_P (operands[1]))
8811 {
8812 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8813 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8814 }
8815 else if (CONST_INT_P (operands[1]))
8816 {
8817 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8818 operands[5] = operands[1];
8819 }
8820 else
8821 FAIL;
8822 }")
8824 (define_split
8825 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8826 (match_operand:TI2 1 "input_operand" ""))]
8827 "reload_completed
8828 && gpr_or_gpr_p (operands[0], operands[1])
8829 && !direct_move_p (operands[0], operands[1])
8830 && !quad_load_store_p (operands[0], operands[1])"
8831 [(pc)]
8832 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8833 \f
8834 (define_expand "load_multiple"
8835 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8836 (match_operand:SI 1 "" ""))
8837 (use (match_operand:SI 2 "" ""))])]
8838 "TARGET_STRING && !TARGET_POWERPC64"
8839 "
8840 {
8841 int regno;
8842 int count;
8843 rtx op1;
8844 int i;
8846 /* Support only loading a constant number of fixed-point registers from
8847 memory and only bother with this if more than two; the machine
8848 doesn't support more than eight. */
8849 if (GET_CODE (operands[2]) != CONST_INT
8850 || INTVAL (operands[2]) <= 2
8851 || INTVAL (operands[2]) > 8
8852 || GET_CODE (operands[1]) != MEM
8853 || GET_CODE (operands[0]) != REG
8854 || REGNO (operands[0]) >= 32)
8855 FAIL;
8857 count = INTVAL (operands[2]);
8858 regno = REGNO (operands[0]);
8860 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8861 op1 = replace_equiv_address (operands[1],
8862 force_reg (SImode, XEXP (operands[1], 0)));
8864 for (i = 0; i < count; i++)
8865 XVECEXP (operands[3], 0, i)
8866 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8867 adjust_address_nv (op1, SImode, i * 4));
8868 }")
8870 (define_insn "*ldmsi8"
8871 [(match_parallel 0 "load_multiple_operation"
8872 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8873 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8874 (set (match_operand:SI 3 "gpc_reg_operand" "")
8875 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8876 (set (match_operand:SI 4 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8878 (set (match_operand:SI 5 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8880 (set (match_operand:SI 6 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8882 (set (match_operand:SI 7 "gpc_reg_operand" "")
8883 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8884 (set (match_operand:SI 8 "gpc_reg_operand" "")
8885 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8886 (set (match_operand:SI 9 "gpc_reg_operand" "")
8887 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8888 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8889 "*
8890 { return rs6000_output_load_multiple (operands); }"
8891 [(set_attr "type" "load")
8892 (set_attr "update" "yes")
8893 (set_attr "indexed" "yes")
8894 (set_attr "length" "32")])
8896 (define_insn "*ldmsi7"
8897 [(match_parallel 0 "load_multiple_operation"
8898 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8899 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8900 (set (match_operand:SI 3 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8902 (set (match_operand:SI 4 "gpc_reg_operand" "")
8903 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8904 (set (match_operand:SI 5 "gpc_reg_operand" "")
8905 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8906 (set (match_operand:SI 6 "gpc_reg_operand" "")
8907 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8908 (set (match_operand:SI 7 "gpc_reg_operand" "")
8909 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8910 (set (match_operand:SI 8 "gpc_reg_operand" "")
8911 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8912 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8913 "*
8914 { return rs6000_output_load_multiple (operands); }"
8915 [(set_attr "type" "load")
8916 (set_attr "update" "yes")
8917 (set_attr "indexed" "yes")
8918 (set_attr "length" "32")])
8920 (define_insn "*ldmsi6"
8921 [(match_parallel 0 "load_multiple_operation"
8922 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8923 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8924 (set (match_operand:SI 3 "gpc_reg_operand" "")
8925 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8926 (set (match_operand:SI 4 "gpc_reg_operand" "")
8927 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8928 (set (match_operand:SI 5 "gpc_reg_operand" "")
8929 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8930 (set (match_operand:SI 6 "gpc_reg_operand" "")
8931 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8932 (set (match_operand:SI 7 "gpc_reg_operand" "")
8933 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8934 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8935 "*
8936 { return rs6000_output_load_multiple (operands); }"
8937 [(set_attr "type" "load")
8938 (set_attr "update" "yes")
8939 (set_attr "indexed" "yes")
8940 (set_attr "length" "32")])
8942 (define_insn "*ldmsi5"
8943 [(match_parallel 0 "load_multiple_operation"
8944 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8945 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8946 (set (match_operand:SI 3 "gpc_reg_operand" "")
8947 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8948 (set (match_operand:SI 4 "gpc_reg_operand" "")
8949 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8950 (set (match_operand:SI 5 "gpc_reg_operand" "")
8951 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8952 (set (match_operand:SI 6 "gpc_reg_operand" "")
8953 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8954 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8955 "*
8956 { return rs6000_output_load_multiple (operands); }"
8957 [(set_attr "type" "load")
8958 (set_attr "update" "yes")
8959 (set_attr "indexed" "yes")
8960 (set_attr "length" "32")])
8962 (define_insn "*ldmsi4"
8963 [(match_parallel 0 "load_multiple_operation"
8964 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8965 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8966 (set (match_operand:SI 3 "gpc_reg_operand" "")
8967 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8968 (set (match_operand:SI 4 "gpc_reg_operand" "")
8969 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8970 (set (match_operand:SI 5 "gpc_reg_operand" "")
8971 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8972 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8973 "*
8974 { return rs6000_output_load_multiple (operands); }"
8975 [(set_attr "type" "load")
8976 (set_attr "update" "yes")
8977 (set_attr "indexed" "yes")
8978 (set_attr "length" "32")])
8980 (define_insn "*ldmsi3"
8981 [(match_parallel 0 "load_multiple_operation"
8982 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8983 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8984 (set (match_operand:SI 3 "gpc_reg_operand" "")
8985 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8986 (set (match_operand:SI 4 "gpc_reg_operand" "")
8987 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8988 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8989 "*
8990 { return rs6000_output_load_multiple (operands); }"
8991 [(set_attr "type" "load")
8992 (set_attr "update" "yes")
8993 (set_attr "indexed" "yes")
8994 (set_attr "length" "32")])
8996 (define_expand "store_multiple"
8997 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8998 (match_operand:SI 1 "" ""))
8999 (clobber (scratch:SI))
9000 (use (match_operand:SI 2 "" ""))])]
9001 "TARGET_STRING && !TARGET_POWERPC64"
9002 "
9003 {
9004 int regno;
9005 int count;
9006 rtx to;
9007 rtx op0;
9008 int i;
9010 /* Support only storing a constant number of fixed-point registers to
9011 memory and only bother with this if more than two; the machine
9012 doesn't support more than eight. */
9013 if (GET_CODE (operands[2]) != CONST_INT
9014 || INTVAL (operands[2]) <= 2
9015 || INTVAL (operands[2]) > 8
9016 || GET_CODE (operands[0]) != MEM
9017 || GET_CODE (operands[1]) != REG
9018 || REGNO (operands[1]) >= 32)
9019 FAIL;
9021 count = INTVAL (operands[2]);
9022 regno = REGNO (operands[1]);
9024 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9025 to = force_reg (SImode, XEXP (operands[0], 0));
9026 op0 = replace_equiv_address (operands[0], to);
9028 XVECEXP (operands[3], 0, 0)
9029 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9030 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9031 gen_rtx_SCRATCH (SImode));
9033 for (i = 1; i < count; i++)
9034 XVECEXP (operands[3], 0, i + 1)
9035 = gen_rtx_SET (VOIDmode,
9036 adjust_address_nv (op0, SImode, i * 4),
9037 gen_rtx_REG (SImode, regno + i));
9038 }")
9040 (define_insn "*stmsi8"
9041 [(match_parallel 0 "store_multiple_operation"
9042 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9043 (match_operand:SI 2 "gpc_reg_operand" "r"))
9044 (clobber (match_scratch:SI 3 "=X"))
9045 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9046 (match_operand:SI 4 "gpc_reg_operand" "r"))
9047 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9048 (match_operand:SI 5 "gpc_reg_operand" "r"))
9049 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9050 (match_operand:SI 6 "gpc_reg_operand" "r"))
9051 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9052 (match_operand:SI 7 "gpc_reg_operand" "r"))
9053 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9054 (match_operand:SI 8 "gpc_reg_operand" "r"))
9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9056 (match_operand:SI 9 "gpc_reg_operand" "r"))
9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9058 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9059 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9060 "stswi %2,%1,%O0"
9061 [(set_attr "type" "store")
9062 (set_attr "update" "yes")
9063 (set_attr "indexed" "yes")
9064 (set_attr "cell_micro" "always")])
9066 (define_insn "*stmsi7"
9067 [(match_parallel 0 "store_multiple_operation"
9068 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9069 (match_operand:SI 2 "gpc_reg_operand" "r"))
9070 (clobber (match_scratch:SI 3 "=X"))
9071 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9072 (match_operand:SI 4 "gpc_reg_operand" "r"))
9073 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9074 (match_operand:SI 5 "gpc_reg_operand" "r"))
9075 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9076 (match_operand:SI 6 "gpc_reg_operand" "r"))
9077 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9078 (match_operand:SI 7 "gpc_reg_operand" "r"))
9079 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9080 (match_operand:SI 8 "gpc_reg_operand" "r"))
9081 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9082 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9083 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9084 "stswi %2,%1,%O0"
9085 [(set_attr "type" "store")
9086 (set_attr "update" "yes")
9087 (set_attr "indexed" "yes")
9088 (set_attr "cell_micro" "always")])
9090 (define_insn "*stmsi6"
9091 [(match_parallel 0 "store_multiple_operation"
9092 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9093 (match_operand:SI 2 "gpc_reg_operand" "r"))
9094 (clobber (match_scratch:SI 3 "=X"))
9095 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9096 (match_operand:SI 4 "gpc_reg_operand" "r"))
9097 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9098 (match_operand:SI 5 "gpc_reg_operand" "r"))
9099 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9100 (match_operand:SI 6 "gpc_reg_operand" "r"))
9101 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9102 (match_operand:SI 7 "gpc_reg_operand" "r"))
9103 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9104 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9105 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9106 "stswi %2,%1,%O0"
9107 [(set_attr "type" "store")
9108 (set_attr "update" "yes")
9109 (set_attr "indexed" "yes")
9110 (set_attr "cell_micro" "always")])
9112 (define_insn "*stmsi5"
9113 [(match_parallel 0 "store_multiple_operation"
9114 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9115 (match_operand:SI 2 "gpc_reg_operand" "r"))
9116 (clobber (match_scratch:SI 3 "=X"))
9117 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9118 (match_operand:SI 4 "gpc_reg_operand" "r"))
9119 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9120 (match_operand:SI 5 "gpc_reg_operand" "r"))
9121 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9122 (match_operand:SI 6 "gpc_reg_operand" "r"))
9123 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9124 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9125 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9126 "stswi %2,%1,%O0"
9127 [(set_attr "type" "store")
9128 (set_attr "update" "yes")
9129 (set_attr "indexed" "yes")
9130 (set_attr "cell_micro" "always")])
9132 (define_insn "*stmsi4"
9133 [(match_parallel 0 "store_multiple_operation"
9134 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9135 (match_operand:SI 2 "gpc_reg_operand" "r"))
9136 (clobber (match_scratch:SI 3 "=X"))
9137 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9138 (match_operand:SI 4 "gpc_reg_operand" "r"))
9139 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9140 (match_operand:SI 5 "gpc_reg_operand" "r"))
9141 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9142 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9143 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9144 "stswi %2,%1,%O0"
9145 [(set_attr "type" "store")
9146 (set_attr "update" "yes")
9147 (set_attr "indexed" "yes")
9148 (set_attr "cell_micro" "always")])
9150 (define_insn "*stmsi3"
9151 [(match_parallel 0 "store_multiple_operation"
9152 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9153 (match_operand:SI 2 "gpc_reg_operand" "r"))
9154 (clobber (match_scratch:SI 3 "=X"))
9155 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9156 (match_operand:SI 4 "gpc_reg_operand" "r"))
9157 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9158 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9159 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9160 "stswi %2,%1,%O0"
9161 [(set_attr "type" "store")
9162 (set_attr "update" "yes")
9163 (set_attr "indexed" "yes")
9164 (set_attr "cell_micro" "always")])
9165 \f
9166 (define_expand "setmemsi"
9167 [(parallel [(set (match_operand:BLK 0 "" "")
9168 (match_operand 2 "const_int_operand" ""))
9169 (use (match_operand:SI 1 "" ""))
9170 (use (match_operand:SI 3 "" ""))])]
9171 ""
9172 "
9173 {
9174 /* If value to set is not zero, use the library routine. */
9175 if (operands[2] != const0_rtx)
9176 FAIL;
9178 if (expand_block_clear (operands))
9179 DONE;
9180 else
9181 FAIL;
9182 }")
9184 ;; String/block move insn.
9185 ;; Argument 0 is the destination
9186 ;; Argument 1 is the source
9187 ;; Argument 2 is the length
9188 ;; Argument 3 is the alignment
9190 (define_expand "movmemsi"
9191 [(parallel [(set (match_operand:BLK 0 "" "")
9192 (match_operand:BLK 1 "" ""))
9193 (use (match_operand:SI 2 "" ""))
9194 (use (match_operand:SI 3 "" ""))])]
9195 ""
9196 "
9197 {
9198 if (expand_block_move (operands))
9199 DONE;
9200 else
9201 FAIL;
9202 }")
9204 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9205 ;; register allocator doesn't have a clue about allocating 8 word registers.
9206 ;; rD/rS = r5 is preferred, efficient form.
9207 (define_expand "movmemsi_8reg"
9208 [(parallel [(set (match_operand 0 "" "")
9209 (match_operand 1 "" ""))
9210 (use (match_operand 2 "" ""))
9211 (use (match_operand 3 "" ""))
9212 (clobber (reg:SI 5))
9213 (clobber (reg:SI 6))
9214 (clobber (reg:SI 7))
9215 (clobber (reg:SI 8))
9216 (clobber (reg:SI 9))
9217 (clobber (reg:SI 10))
9218 (clobber (reg:SI 11))
9219 (clobber (reg:SI 12))
9220 (clobber (match_scratch:SI 4 ""))])]
9221 "TARGET_STRING"
9222 "")
9224 (define_insn ""
9225 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9226 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9227 (use (match_operand:SI 2 "immediate_operand" "i"))
9228 (use (match_operand:SI 3 "immediate_operand" "i"))
9229 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9230 (clobber (reg:SI 6))
9231 (clobber (reg:SI 7))
9232 (clobber (reg:SI 8))
9233 (clobber (reg:SI 9))
9234 (clobber (reg:SI 10))
9235 (clobber (reg:SI 11))
9236 (clobber (reg:SI 12))
9237 (clobber (match_scratch:SI 5 "=X"))]
9238 "TARGET_STRING
9239 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9240 || INTVAL (operands[2]) == 0)
9241 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9242 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9243 && REGNO (operands[4]) == 5"
9244 "lswi %4,%1,%2\;stswi %4,%0,%2"
9245 [(set_attr "type" "store")
9246 (set_attr "update" "yes")
9247 (set_attr "indexed" "yes")
9248 (set_attr "cell_micro" "always")
9249 (set_attr "length" "8")])
9251 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9252 ;; register allocator doesn't have a clue about allocating 6 word registers.
9253 ;; rD/rS = r5 is preferred, efficient form.
9254 (define_expand "movmemsi_6reg"
9255 [(parallel [(set (match_operand 0 "" "")
9256 (match_operand 1 "" ""))
9257 (use (match_operand 2 "" ""))
9258 (use (match_operand 3 "" ""))
9259 (clobber (reg:SI 5))
9260 (clobber (reg:SI 6))
9261 (clobber (reg:SI 7))
9262 (clobber (reg:SI 8))
9263 (clobber (reg:SI 9))
9264 (clobber (reg:SI 10))
9265 (clobber (match_scratch:SI 4 ""))])]
9266 "TARGET_STRING"
9267 "")
9269 (define_insn ""
9270 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9271 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9272 (use (match_operand:SI 2 "immediate_operand" "i"))
9273 (use (match_operand:SI 3 "immediate_operand" "i"))
9274 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9275 (clobber (reg:SI 6))
9276 (clobber (reg:SI 7))
9277 (clobber (reg:SI 8))
9278 (clobber (reg:SI 9))
9279 (clobber (reg:SI 10))
9280 (clobber (match_scratch:SI 5 "=X"))]
9281 "TARGET_STRING
9282 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9283 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9284 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9285 && REGNO (operands[4]) == 5"
9286 "lswi %4,%1,%2\;stswi %4,%0,%2"
9287 [(set_attr "type" "store")
9288 (set_attr "update" "yes")
9289 (set_attr "indexed" "yes")
9290 (set_attr "cell_micro" "always")
9291 (set_attr "length" "8")])
9293 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9294 ;; problems with TImode.
9295 ;; rD/rS = r5 is preferred, efficient form.
9296 (define_expand "movmemsi_4reg"
9297 [(parallel [(set (match_operand 0 "" "")
9298 (match_operand 1 "" ""))
9299 (use (match_operand 2 "" ""))
9300 (use (match_operand 3 "" ""))
9301 (clobber (reg:SI 5))
9302 (clobber (reg:SI 6))
9303 (clobber (reg:SI 7))
9304 (clobber (reg:SI 8))
9305 (clobber (match_scratch:SI 4 ""))])]
9306 "TARGET_STRING"
9307 "")
9309 (define_insn ""
9310 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9311 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9312 (use (match_operand:SI 2 "immediate_operand" "i"))
9313 (use (match_operand:SI 3 "immediate_operand" "i"))
9314 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9315 (clobber (reg:SI 6))
9316 (clobber (reg:SI 7))
9317 (clobber (reg:SI 8))
9318 (clobber (match_scratch:SI 5 "=X"))]
9319 "TARGET_STRING
9320 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9321 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9322 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9323 && REGNO (operands[4]) == 5"
9324 "lswi %4,%1,%2\;stswi %4,%0,%2"
9325 [(set_attr "type" "store")
9326 (set_attr "update" "yes")
9327 (set_attr "indexed" "yes")
9328 (set_attr "cell_micro" "always")
9329 (set_attr "length" "8")])
9331 ;; Move up to 8 bytes at a time.
9332 (define_expand "movmemsi_2reg"
9333 [(parallel [(set (match_operand 0 "" "")
9334 (match_operand 1 "" ""))
9335 (use (match_operand 2 "" ""))
9336 (use (match_operand 3 "" ""))
9337 (clobber (match_scratch:DI 4 ""))
9338 (clobber (match_scratch:SI 5 ""))])]
9339 "TARGET_STRING && ! TARGET_POWERPC64"
9340 "")
9342 (define_insn ""
9343 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9344 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9345 (use (match_operand:SI 2 "immediate_operand" "i"))
9346 (use (match_operand:SI 3 "immediate_operand" "i"))
9347 (clobber (match_scratch:DI 4 "=&r"))
9348 (clobber (match_scratch:SI 5 "=X"))]
9349 "TARGET_STRING && ! TARGET_POWERPC64
9350 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9351 "lswi %4,%1,%2\;stswi %4,%0,%2"
9352 [(set_attr "type" "store")
9353 (set_attr "update" "yes")
9354 (set_attr "indexed" "yes")
9355 (set_attr "cell_micro" "always")
9356 (set_attr "length" "8")])
9358 ;; Move up to 4 bytes at a time.
9359 (define_expand "movmemsi_1reg"
9360 [(parallel [(set (match_operand 0 "" "")
9361 (match_operand 1 "" ""))
9362 (use (match_operand 2 "" ""))
9363 (use (match_operand 3 "" ""))
9364 (clobber (match_scratch:SI 4 ""))
9365 (clobber (match_scratch:SI 5 ""))])]
9366 "TARGET_STRING"
9367 "")
9369 (define_insn ""
9370 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9371 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9372 (use (match_operand:SI 2 "immediate_operand" "i"))
9373 (use (match_operand:SI 3 "immediate_operand" "i"))
9374 (clobber (match_scratch:SI 4 "=&r"))
9375 (clobber (match_scratch:SI 5 "=X"))]
9376 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9377 "lswi %4,%1,%2\;stswi %4,%0,%2"
9378 [(set_attr "type" "store")
9379 (set_attr "update" "yes")
9380 (set_attr "indexed" "yes")
9381 (set_attr "cell_micro" "always")
9382 (set_attr "length" "8")])
9383 \f
9384 ;; Define insns that do load or store with update. Some of these we can
9385 ;; get by using pre-decrement or pre-increment, but the hardware can also
9386 ;; do cases where the increment is not the size of the object.
9387 ;;
9388 ;; In all these cases, we use operands 0 and 1 for the register being
9389 ;; incremented because those are the operands that local-alloc will
9390 ;; tie and these are the pair most likely to be tieable (and the ones
9391 ;; that will benefit the most).
9393 (define_insn "*movdi_update1"
9394 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9395 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9396 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9397 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9398 (plus:DI (match_dup 1) (match_dup 2)))]
9399 "TARGET_POWERPC64 && TARGET_UPDATE
9400 && (!avoiding_indexed_address_p (DImode)
9401 || !gpc_reg_operand (operands[2], DImode))"
9402 "@
9403 ldux %3,%0,%2
9404 ldu %3,%2(%0)"
9405 [(set_attr "type" "load")
9406 (set_attr "update" "yes")
9407 (set_attr "indexed" "yes,no")])
9409 (define_insn "movdi_<mode>_update"
9410 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9411 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9412 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9413 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9414 (plus:P (match_dup 1) (match_dup 2)))]
9415 "TARGET_POWERPC64 && TARGET_UPDATE
9416 && (!avoiding_indexed_address_p (Pmode)
9417 || !gpc_reg_operand (operands[2], Pmode)
9418 || (REG_P (operands[0])
9419 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9420 "@
9421 stdux %3,%0,%2
9422 stdu %3,%2(%0)"
9423 [(set_attr "type" "store")
9424 (set_attr "update" "yes")
9425 (set_attr "indexed" "yes,no")])
9427 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9428 ;; needed for stack allocation, even if the user passes -mno-update.
9429 (define_insn "movdi_<mode>_update_stack"
9430 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9431 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9432 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9433 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9434 (plus:P (match_dup 1) (match_dup 2)))]
9435 "TARGET_POWERPC64"
9436 "@
9437 stdux %3,%0,%2
9438 stdu %3,%2(%0)"
9439 [(set_attr "type" "store")
9440 (set_attr "update" "yes")
9441 (set_attr "indexed" "yes,no")])
9443 (define_insn "*movsi_update1"
9444 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9445 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9446 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9447 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9448 (plus:SI (match_dup 1) (match_dup 2)))]
9449 "TARGET_UPDATE
9450 && (!avoiding_indexed_address_p (SImode)
9451 || !gpc_reg_operand (operands[2], SImode))"
9452 "@
9453 lwzux %3,%0,%2
9454 lwzu %3,%2(%0)"
9455 [(set_attr "type" "load")
9456 (set_attr "update" "yes")
9457 (set_attr "indexed" "yes,no")])
9459 (define_insn "*movsi_update2"
9460 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9461 (sign_extend:DI
9462 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9463 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9464 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9465 (plus:DI (match_dup 1) (match_dup 2)))]
9466 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9467 && !avoiding_indexed_address_p (DImode)"
9468 "lwaux %3,%0,%2"
9469 [(set_attr "type" "load")
9470 (set_attr "sign_extend" "yes")
9471 (set_attr "update" "yes")
9472 (set_attr "indexed" "yes")])
9474 (define_insn "movsi_update"
9475 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9476 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9477 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9478 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9479 (plus:SI (match_dup 1) (match_dup 2)))]
9480 "TARGET_UPDATE
9481 && (!avoiding_indexed_address_p (SImode)
9482 || !gpc_reg_operand (operands[2], SImode)
9483 || (REG_P (operands[0])
9484 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9485 "@
9486 stwux %3,%0,%2
9487 stwu %3,%2(%0)"
9488 [(set_attr "type" "store")
9489 (set_attr "update" "yes")
9490 (set_attr "indexed" "yes,no")])
9492 ;; This is an unconditional pattern; needed for stack allocation, even
9493 ;; if the user passes -mno-update.
9494 (define_insn "movsi_update_stack"
9495 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9496 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9497 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9498 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9499 (plus:SI (match_dup 1) (match_dup 2)))]
9500 ""
9501 "@
9502 stwux %3,%0,%2
9503 stwu %3,%2(%0)"
9504 [(set_attr "type" "store")
9505 (set_attr "update" "yes")
9506 (set_attr "indexed" "yes,no")])
9508 (define_insn "*movhi_update1"
9509 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9510 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9511 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9512 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9513 (plus:SI (match_dup 1) (match_dup 2)))]
9514 "TARGET_UPDATE
9515 && (!avoiding_indexed_address_p (SImode)
9516 || !gpc_reg_operand (operands[2], SImode))"
9517 "@
9518 lhzux %3,%0,%2
9519 lhzu %3,%2(%0)"
9520 [(set_attr "type" "load")
9521 (set_attr "update" "yes")
9522 (set_attr "indexed" "yes,no")])
9524 (define_insn "*movhi_update2"
9525 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9526 (zero_extend:SI
9527 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9528 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9529 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9530 (plus:SI (match_dup 1) (match_dup 2)))]
9531 "TARGET_UPDATE
9532 && (!avoiding_indexed_address_p (SImode)
9533 || !gpc_reg_operand (operands[2], SImode))"
9534 "@
9535 lhzux %3,%0,%2
9536 lhzu %3,%2(%0)"
9537 [(set_attr "type" "load")
9538 (set_attr "update" "yes")
9539 (set_attr "indexed" "yes,no")])
9541 (define_insn "*movhi_update3"
9542 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9543 (sign_extend:SI
9544 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9545 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9546 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9547 (plus:SI (match_dup 1) (match_dup 2)))]
9548 "TARGET_UPDATE && rs6000_gen_cell_microcode
9549 && (!avoiding_indexed_address_p (SImode)
9550 || !gpc_reg_operand (operands[2], SImode))"
9551 "@
9552 lhaux %3,%0,%2
9553 lhau %3,%2(%0)"
9554 [(set_attr "type" "load")
9555 (set_attr "sign_extend" "yes")
9556 (set_attr "update" "yes")
9557 (set_attr "indexed" "yes,no")])
9559 (define_insn "*movhi_update4"
9560 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9561 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9562 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9563 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9564 (plus:SI (match_dup 1) (match_dup 2)))]
9565 "TARGET_UPDATE
9566 && (!avoiding_indexed_address_p (SImode)
9567 || !gpc_reg_operand (operands[2], SImode))"
9568 "@
9569 sthux %3,%0,%2
9570 sthu %3,%2(%0)"
9571 [(set_attr "type" "store")
9572 (set_attr "update" "yes")
9573 (set_attr "indexed" "yes,no")])
9575 (define_insn "*movqi_update1"
9576 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9577 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9578 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9579 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9580 (plus:SI (match_dup 1) (match_dup 2)))]
9581 "TARGET_UPDATE
9582 && (!avoiding_indexed_address_p (SImode)
9583 || !gpc_reg_operand (operands[2], SImode))"
9584 "@
9585 lbzux %3,%0,%2
9586 lbzu %3,%2(%0)"
9587 [(set_attr "type" "load")
9588 (set_attr "update" "yes")
9589 (set_attr "indexed" "yes,no")])
9591 (define_insn "*movqi_update2"
9592 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9593 (zero_extend:SI
9594 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9595 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9596 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9597 (plus:SI (match_dup 1) (match_dup 2)))]
9598 "TARGET_UPDATE
9599 && (!avoiding_indexed_address_p (SImode)
9600 || !gpc_reg_operand (operands[2], SImode))"
9601 "@
9602 lbzux %3,%0,%2
9603 lbzu %3,%2(%0)"
9604 [(set_attr "type" "load")
9605 (set_attr "update" "yes")
9606 (set_attr "indexed" "yes,no")])
9608 (define_insn "*movqi_update3"
9609 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9610 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9611 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9612 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9613 (plus:SI (match_dup 1) (match_dup 2)))]
9614 "TARGET_UPDATE
9615 && (!avoiding_indexed_address_p (SImode)
9616 || !gpc_reg_operand (operands[2], SImode))"
9617 "@
9618 stbux %3,%0,%2
9619 stbu %3,%2(%0)"
9620 [(set_attr "type" "store")
9621 (set_attr "update" "yes")
9622 (set_attr "indexed" "yes,no")])
9624 (define_insn "*movsf_update1"
9625 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9626 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9627 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9628 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9629 (plus:SI (match_dup 1) (match_dup 2)))]
9630 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9631 && (!avoiding_indexed_address_p (SImode)
9632 || !gpc_reg_operand (operands[2], SImode))"
9633 "@
9634 lfsux %3,%0,%2
9635 lfsu %3,%2(%0)"
9636 [(set_attr "type" "fpload")
9637 (set_attr "update" "yes")
9638 (set_attr "indexed" "yes,no")])
9640 (define_insn "*movsf_update2"
9641 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9642 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9643 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9644 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9645 (plus:SI (match_dup 1) (match_dup 2)))]
9646 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9647 && (!avoiding_indexed_address_p (SImode)
9648 || !gpc_reg_operand (operands[2], SImode))"
9649 "@
9650 stfsux %3,%0,%2
9651 stfsu %3,%2(%0)"
9652 [(set_attr "type" "fpstore")
9653 (set_attr "update" "yes")
9654 (set_attr "indexed" "yes,no")])
9656 (define_insn "*movsf_update3"
9657 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9658 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9659 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9660 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9661 (plus:SI (match_dup 1) (match_dup 2)))]
9662 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9663 && (!avoiding_indexed_address_p (SImode)
9664 || !gpc_reg_operand (operands[2], SImode))"
9665 "@
9666 lwzux %3,%0,%2
9667 lwzu %3,%2(%0)"
9668 [(set_attr "type" "load")
9669 (set_attr "update" "yes")
9670 (set_attr "indexed" "yes,no")])
9672 (define_insn "*movsf_update4"
9673 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9674 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9675 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9676 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9677 (plus:SI (match_dup 1) (match_dup 2)))]
9678 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9679 && (!avoiding_indexed_address_p (SImode)
9680 || !gpc_reg_operand (operands[2], SImode))"
9681 "@
9682 stwux %3,%0,%2
9683 stwu %3,%2(%0)"
9684 [(set_attr "type" "store")
9685 (set_attr "update" "yes")
9686 (set_attr "indexed" "yes,no")])
9688 (define_insn "*movdf_update1"
9689 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9690 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9691 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9692 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9693 (plus:SI (match_dup 1) (match_dup 2)))]
9694 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9695 && (!avoiding_indexed_address_p (SImode)
9696 || !gpc_reg_operand (operands[2], SImode))"
9697 "@
9698 lfdux %3,%0,%2
9699 lfdu %3,%2(%0)"
9700 [(set_attr "type" "fpload")
9701 (set_attr "update" "yes")
9702 (set_attr "indexed" "yes,no")])
9704 (define_insn "*movdf_update2"
9705 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9706 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9707 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9708 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9709 (plus:SI (match_dup 1) (match_dup 2)))]
9710 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9711 && (!avoiding_indexed_address_p (SImode)
9712 || !gpc_reg_operand (operands[2], SImode))"
9713 "@
9714 stfdux %3,%0,%2
9715 stfdu %3,%2(%0)"
9716 [(set_attr "type" "fpstore")
9717 (set_attr "update" "yes")
9718 (set_attr "indexed" "yes,no")])
9721 ;; After inserting conditional returns we can sometimes have
9722 ;; unnecessary register moves. Unfortunately we cannot have a
9723 ;; modeless peephole here, because some single SImode sets have early
9724 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9725 ;; sequences, using get_attr_length here will smash the operands
9726 ;; array. Neither is there an early_cobbler_p predicate.
9727 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9728 (define_peephole2
9729 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9730 (match_operand:DF 1 "any_operand" ""))
9731 (set (match_operand:DF 2 "gpc_reg_operand" "")
9732 (match_dup 0))]
9733 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9734 && peep2_reg_dead_p (2, operands[0])"
9735 [(set (match_dup 2) (match_dup 1))])
9737 (define_peephole2
9738 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9739 (match_operand:SF 1 "any_operand" ""))
9740 (set (match_operand:SF 2 "gpc_reg_operand" "")
9741 (match_dup 0))]
9742 "peep2_reg_dead_p (2, operands[0])"
9743 [(set (match_dup 2) (match_dup 1))])
9745 \f
9746 ;; TLS support.
9748 ;; Mode attributes for different ABIs.
9749 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9750 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9751 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9752 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9754 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9755 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9756 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9757 (match_operand 4 "" "g")))
9758 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9759 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9760 UNSPEC_TLSGD)
9761 (clobber (reg:SI LR_REGNO))]
9762 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9763 {
9764 if (TARGET_CMODEL != CMODEL_SMALL)
9765 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9766 "bl %z3\;nop";
9767 else
9768 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9769 }
9770 "&& TARGET_TLS_MARKERS"
9771 [(set (match_dup 0)
9772 (unspec:TLSmode [(match_dup 1)
9773 (match_dup 2)]
9774 UNSPEC_TLSGD))
9775 (parallel [(set (match_dup 0)
9776 (call (mem:TLSmode (match_dup 3))
9777 (match_dup 4)))
9778 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9779 (clobber (reg:SI LR_REGNO))])]
9780 ""
9781 [(set_attr "type" "two")
9782 (set (attr "length")
9783 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9784 (const_int 16)
9785 (const_int 12)))])
9787 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9788 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9789 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9790 (match_operand 4 "" "g")))
9791 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9792 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9793 UNSPEC_TLSGD)
9794 (clobber (reg:SI LR_REGNO))]
9795 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9796 {
9797 if (flag_pic)
9798 {
9799 if (TARGET_SECURE_PLT && flag_pic == 2)
9800 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9801 else
9802 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9803 }
9804 else
9805 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9806 }
9807 "&& TARGET_TLS_MARKERS"
9808 [(set (match_dup 0)
9809 (unspec:TLSmode [(match_dup 1)
9810 (match_dup 2)]
9811 UNSPEC_TLSGD))
9812 (parallel [(set (match_dup 0)
9813 (call (mem:TLSmode (match_dup 3))
9814 (match_dup 4)))
9815 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9816 (clobber (reg:SI LR_REGNO))])]
9817 ""
9818 [(set_attr "type" "two")
9819 (set_attr "length" "8")])
9821 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9822 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9823 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9824 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9825 UNSPEC_TLSGD))]
9826 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9827 "addi %0,%1,%2@got@tlsgd"
9828 "&& TARGET_CMODEL != CMODEL_SMALL"
9829 [(set (match_dup 3)
9830 (high:TLSmode
9831 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9832 (set (match_dup 0)
9833 (lo_sum:TLSmode (match_dup 3)
9834 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9835 "
9836 {
9837 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9838 }"
9839 [(set (attr "length")
9840 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9841 (const_int 8)
9842 (const_int 4)))])
9844 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9845 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9846 (high:TLSmode
9847 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9848 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9849 UNSPEC_TLSGD)))]
9850 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9851 "addis %0,%1,%2@got@tlsgd@ha"
9852 [(set_attr "length" "4")])
9854 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9855 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9856 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9857 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9858 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9859 UNSPEC_TLSGD)))]
9860 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9861 "addi %0,%1,%2@got@tlsgd@l"
9862 [(set_attr "length" "4")])
9864 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9865 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9866 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9867 (match_operand 2 "" "g")))
9868 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9869 UNSPEC_TLSGD)
9870 (clobber (reg:SI LR_REGNO))]
9871 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9872 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9873 "bl %z1(%3@tlsgd)\;nop"
9874 [(set_attr "type" "branch")
9875 (set_attr "length" "8")])
9877 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9878 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9879 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9880 (match_operand 2 "" "g")))
9881 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9882 UNSPEC_TLSGD)
9883 (clobber (reg:SI LR_REGNO))]
9884 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9885 {
9886 if (flag_pic)
9887 {
9888 if (TARGET_SECURE_PLT && flag_pic == 2)
9889 return "bl %z1+32768(%3@tlsgd)@plt";
9890 return "bl %z1(%3@tlsgd)@plt";
9891 }
9892 return "bl %z1(%3@tlsgd)";
9893 }
9894 [(set_attr "type" "branch")
9895 (set_attr "length" "4")])
9897 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9898 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9899 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9900 (match_operand 3 "" "g")))
9901 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9902 UNSPEC_TLSLD)
9903 (clobber (reg:SI LR_REGNO))]
9904 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9905 {
9906 if (TARGET_CMODEL != CMODEL_SMALL)
9907 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9908 "bl %z2\;nop";
9909 else
9910 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9911 }
9912 "&& TARGET_TLS_MARKERS"
9913 [(set (match_dup 0)
9914 (unspec:TLSmode [(match_dup 1)]
9915 UNSPEC_TLSLD))
9916 (parallel [(set (match_dup 0)
9917 (call (mem:TLSmode (match_dup 2))
9918 (match_dup 3)))
9919 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9920 (clobber (reg:SI LR_REGNO))])]
9921 ""
9922 [(set_attr "type" "two")
9923 (set (attr "length")
9924 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9925 (const_int 16)
9926 (const_int 12)))])
9928 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9929 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9930 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9931 (match_operand 3 "" "g")))
9932 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9933 UNSPEC_TLSLD)
9934 (clobber (reg:SI LR_REGNO))]
9935 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9936 {
9937 if (flag_pic)
9938 {
9939 if (TARGET_SECURE_PLT && flag_pic == 2)
9940 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9941 else
9942 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9943 }
9944 else
9945 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9946 }
9947 "&& TARGET_TLS_MARKERS"
9948 [(set (match_dup 0)
9949 (unspec:TLSmode [(match_dup 1)]
9950 UNSPEC_TLSLD))
9951 (parallel [(set (match_dup 0)
9952 (call (mem:TLSmode (match_dup 2))
9953 (match_dup 3)))
9954 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9955 (clobber (reg:SI LR_REGNO))])]
9956 ""
9957 [(set_attr "length" "8")])
9959 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
9960 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9961 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9962 UNSPEC_TLSLD))]
9963 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9964 "addi %0,%1,%&@got@tlsld"
9965 "&& TARGET_CMODEL != CMODEL_SMALL"
9966 [(set (match_dup 2)
9967 (high:TLSmode
9968 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
9969 (set (match_dup 0)
9970 (lo_sum:TLSmode (match_dup 2)
9971 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
9972 "
9973 {
9974 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9975 }"
9976 [(set (attr "length")
9977 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9978 (const_int 8)
9979 (const_int 4)))])
9981 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
9982 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9983 (high:TLSmode
9984 (unspec:TLSmode [(const_int 0)
9985 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9986 UNSPEC_TLSLD)))]
9987 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9988 "addis %0,%1,%&@got@tlsld@ha"
9989 [(set_attr "length" "4")])
9991 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
9992 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9993 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9994 (unspec:TLSmode [(const_int 0)
9995 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
9996 UNSPEC_TLSLD)))]
9997 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9998 "addi %0,%1,%&@got@tlsld@l"
9999 [(set_attr "length" "4")])
10001 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10002 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10003 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10004 (match_operand 2 "" "g")))
10005 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10006 (clobber (reg:SI LR_REGNO))]
10007 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10008 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10009 "bl %z1(%&@tlsld)\;nop"
10010 [(set_attr "type" "branch")
10011 (set_attr "length" "8")])
10013 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10014 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10015 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10016 (match_operand 2 "" "g")))
10017 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10018 (clobber (reg:SI LR_REGNO))]
10019 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10020 {
10021 if (flag_pic)
10022 {
10023 if (TARGET_SECURE_PLT && flag_pic == 2)
10024 return "bl %z1+32768(%&@tlsld)@plt";
10025 return "bl %z1(%&@tlsld)@plt";
10026 }
10027 return "bl %z1(%&@tlsld)";
10028 }
10029 [(set_attr "type" "branch")
10030 (set_attr "length" "4")])
10032 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10033 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10034 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10035 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10036 UNSPEC_TLSDTPREL))]
10037 "HAVE_AS_TLS"
10038 "addi %0,%1,%2@dtprel")
10040 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10041 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10042 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10043 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10044 UNSPEC_TLSDTPRELHA))]
10045 "HAVE_AS_TLS"
10046 "addis %0,%1,%2@dtprel@ha")
10048 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10049 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10050 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10051 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10052 UNSPEC_TLSDTPRELLO))]
10053 "HAVE_AS_TLS"
10054 "addi %0,%1,%2@dtprel@l")
10056 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10057 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10058 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10059 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10060 UNSPEC_TLSGOTDTPREL))]
10061 "HAVE_AS_TLS"
10062 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10063 "&& TARGET_CMODEL != CMODEL_SMALL"
10064 [(set (match_dup 3)
10065 (high:TLSmode
10066 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10067 (set (match_dup 0)
10068 (lo_sum:TLSmode (match_dup 3)
10069 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10070 "
10071 {
10072 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10073 }"
10074 [(set (attr "length")
10075 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10076 (const_int 8)
10077 (const_int 4)))])
10079 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10080 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10081 (high:TLSmode
10082 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10083 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10084 UNSPEC_TLSGOTDTPREL)))]
10085 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10086 "addis %0,%1,%2@got@dtprel@ha"
10087 [(set_attr "length" "4")])
10089 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10090 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10091 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10092 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10093 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10094 UNSPEC_TLSGOTDTPREL)))]
10095 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10096 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10097 [(set_attr "length" "4")])
10099 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10100 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10101 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10102 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10103 UNSPEC_TLSTPREL))]
10104 "HAVE_AS_TLS"
10105 "addi %0,%1,%2@tprel")
10107 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10108 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10109 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10110 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10111 UNSPEC_TLSTPRELHA))]
10112 "HAVE_AS_TLS"
10113 "addis %0,%1,%2@tprel@ha")
10115 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10116 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10117 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10118 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10119 UNSPEC_TLSTPRELLO))]
10120 "HAVE_AS_TLS"
10121 "addi %0,%1,%2@tprel@l")
10123 ;; "b" output constraint here and on tls_tls input to support linker tls
10124 ;; optimization. The linker may edit the instructions emitted by a
10125 ;; tls_got_tprel/tls_tls pair to addis,addi.
10126 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10127 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10128 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10129 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10130 UNSPEC_TLSGOTTPREL))]
10131 "HAVE_AS_TLS"
10132 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10133 "&& TARGET_CMODEL != CMODEL_SMALL"
10134 [(set (match_dup 3)
10135 (high:TLSmode
10136 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10137 (set (match_dup 0)
10138 (lo_sum:TLSmode (match_dup 3)
10139 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10140 "
10141 {
10142 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10143 }"
10144 [(set (attr "length")
10145 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10146 (const_int 8)
10147 (const_int 4)))])
10149 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10150 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10151 (high:TLSmode
10152 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10153 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10154 UNSPEC_TLSGOTTPREL)))]
10155 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10156 "addis %0,%1,%2@got@tprel@ha"
10157 [(set_attr "length" "4")])
10159 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10160 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10161 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10162 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10163 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10164 UNSPEC_TLSGOTTPREL)))]
10165 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10166 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10167 [(set_attr "length" "4")])
10169 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10170 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10171 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10172 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10173 UNSPEC_TLSTLS))]
10174 "TARGET_ELF && HAVE_AS_TLS"
10175 "add %0,%1,%2@tls")
10177 (define_expand "tls_get_tpointer"
10178 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10179 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10180 "TARGET_XCOFF && HAVE_AS_TLS"
10181 "
10182 {
10183 emit_insn (gen_tls_get_tpointer_internal ());
10184 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10185 DONE;
10186 }")
10188 (define_insn "tls_get_tpointer_internal"
10189 [(set (reg:SI 3)
10190 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10191 (clobber (reg:SI LR_REGNO))]
10192 "TARGET_XCOFF && HAVE_AS_TLS"
10193 "bla __get_tpointer")
10195 (define_expand "tls_get_addr<mode>"
10196 [(set (match_operand:P 0 "gpc_reg_operand" "")
10197 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10198 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10199 "TARGET_XCOFF && HAVE_AS_TLS"
10200 "
10201 {
10202 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10203 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10204 emit_insn (gen_tls_get_addr_internal<mode> ());
10205 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10206 DONE;
10207 }")
10209 (define_insn "tls_get_addr_internal<mode>"
10210 [(set (reg:P 3)
10211 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10212 (clobber (reg:P 0))
10213 (clobber (reg:P 4))
10214 (clobber (reg:P 5))
10215 (clobber (reg:P 11))
10216 (clobber (reg:CC CR0_REGNO))
10217 (clobber (reg:P LR_REGNO))]
10218 "TARGET_XCOFF && HAVE_AS_TLS"
10219 "bla __tls_get_addr")
10220 \f
10221 ;; Next come insns related to the calling sequence.
10222 ;;
10223 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10224 ;; We move the back-chain and decrement the stack pointer.
10226 (define_expand "allocate_stack"
10227 [(set (match_operand 0 "gpc_reg_operand" "")
10228 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10229 (set (reg 1)
10230 (minus (reg 1) (match_dup 1)))]
10231 ""
10232 "
10233 { rtx chain = gen_reg_rtx (Pmode);
10234 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10235 rtx neg_op0;
10236 rtx insn, par, set, mem;
10238 emit_move_insn (chain, stack_bot);
10240 /* Check stack bounds if necessary. */
10241 if (crtl->limit_stack)
10242 {
10243 rtx available;
10244 available = expand_binop (Pmode, sub_optab,
10245 stack_pointer_rtx, stack_limit_rtx,
10246 NULL_RTX, 1, OPTAB_WIDEN);
10247 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10248 }
10250 if (GET_CODE (operands[1]) != CONST_INT
10251 || INTVAL (operands[1]) < -32767
10252 || INTVAL (operands[1]) > 32768)
10253 {
10254 neg_op0 = gen_reg_rtx (Pmode);
10255 if (TARGET_32BIT)
10256 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10257 else
10258 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10259 }
10260 else
10261 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10263 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10264 : gen_movdi_di_update_stack))
10265 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10266 chain));
10267 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10268 it now and set the alias set/attributes. The above gen_*_update
10269 calls will generate a PARALLEL with the MEM set being the first
10270 operation. */
10271 par = PATTERN (insn);
10272 gcc_assert (GET_CODE (par) == PARALLEL);
10273 set = XVECEXP (par, 0, 0);
10274 gcc_assert (GET_CODE (set) == SET);
10275 mem = SET_DEST (set);
10276 gcc_assert (MEM_P (mem));
10277 MEM_NOTRAP_P (mem) = 1;
10278 set_mem_alias_set (mem, get_frame_alias_set ());
10280 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10281 DONE;
10282 }")
10284 ;; These patterns say how to save and restore the stack pointer. We need not
10285 ;; save the stack pointer at function level since we are careful to
10286 ;; preserve the backchain. At block level, we have to restore the backchain
10287 ;; when we restore the stack pointer.
10288 ;;
10289 ;; For nonlocal gotos, we must save both the stack pointer and its
10290 ;; backchain and restore both. Note that in the nonlocal case, the
10291 ;; save area is a memory location.
10293 (define_expand "save_stack_function"
10294 [(match_operand 0 "any_operand" "")
10295 (match_operand 1 "any_operand" "")]
10296 ""
10297 "DONE;")
10299 (define_expand "restore_stack_function"
10300 [(match_operand 0 "any_operand" "")
10301 (match_operand 1 "any_operand" "")]
10302 ""
10303 "DONE;")
10305 ;; Adjust stack pointer (op0) to a new value (op1).
10306 ;; First copy old stack backchain to new location, and ensure that the
10307 ;; scheduler won't reorder the sp assignment before the backchain write.
10308 (define_expand "restore_stack_block"
10309 [(set (match_dup 2) (match_dup 3))
10310 (set (match_dup 4) (match_dup 2))
10311 (match_dup 5)
10312 (set (match_operand 0 "register_operand" "")
10313 (match_operand 1 "register_operand" ""))]
10314 ""
10315 "
10316 {
10317 rtvec p;
10319 operands[1] = force_reg (Pmode, operands[1]);
10320 operands[2] = gen_reg_rtx (Pmode);
10321 operands[3] = gen_frame_mem (Pmode, operands[0]);
10322 operands[4] = gen_frame_mem (Pmode, operands[1]);
10323 p = rtvec_alloc (1);
10324 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10325 gen_frame_mem (BLKmode, operands[0]),
10326 const0_rtx);
10327 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10328 }")
10330 (define_expand "save_stack_nonlocal"
10331 [(set (match_dup 3) (match_dup 4))
10332 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10333 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10334 ""
10335 "
10336 {
10337 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10339 /* Copy the backchain to the first word, sp to the second. */
10340 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10341 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10342 operands[3] = gen_reg_rtx (Pmode);
10343 operands[4] = gen_frame_mem (Pmode, operands[1]);
10344 }")
10346 (define_expand "restore_stack_nonlocal"
10347 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10348 (set (match_dup 3) (match_dup 4))
10349 (set (match_dup 5) (match_dup 2))
10350 (match_dup 6)
10351 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10352 ""
10353 "
10354 {
10355 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10356 rtvec p;
10358 /* Restore the backchain from the first word, sp from the second. */
10359 operands[2] = gen_reg_rtx (Pmode);
10360 operands[3] = gen_reg_rtx (Pmode);
10361 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10362 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10363 operands[5] = gen_frame_mem (Pmode, operands[3]);
10364 p = rtvec_alloc (1);
10365 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10366 gen_frame_mem (BLKmode, operands[0]),
10367 const0_rtx);
10368 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10369 }")
10370 \f
10371 ;; TOC register handling.
10373 ;; Code to initialize the TOC register...
10375 (define_insn "load_toc_aix_si"
10376 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10377 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10378 (use (reg:SI 2))])]
10379 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10380 "*
10381 {
10382 char buf[30];
10383 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10384 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10385 operands[2] = gen_rtx_REG (Pmode, 2);
10386 return \"lwz %0,%1(%2)\";
10387 }"
10388 [(set_attr "type" "load")
10389 (set_attr "update" "no")
10390 (set_attr "indexed" "no")])
10392 (define_insn "load_toc_aix_di"
10393 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10394 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10395 (use (reg:DI 2))])]
10396 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10397 "*
10398 {
10399 char buf[30];
10400 #ifdef TARGET_RELOCATABLE
10401 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10402 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10403 #else
10404 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10405 #endif
10406 if (TARGET_ELF)
10407 strcat (buf, \"@toc\");
10408 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10409 operands[2] = gen_rtx_REG (Pmode, 2);
10410 return \"ld %0,%1(%2)\";
10411 }"
10412 [(set_attr "type" "load")
10413 (set_attr "update" "no")
10414 (set_attr "indexed" "no")])
10416 (define_insn "load_toc_v4_pic_si"
10417 [(set (reg:SI LR_REGNO)
10418 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10419 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10420 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10421 [(set_attr "type" "branch")
10422 (set_attr "length" "4")])
10424 (define_expand "load_toc_v4_PIC_1"
10425 [(parallel [(set (reg:SI LR_REGNO)
10426 (match_operand:SI 0 "immediate_operand" "s"))
10427 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10428 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10429 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10430 "")
10432 (define_insn "load_toc_v4_PIC_1_normal"
10433 [(set (reg:SI LR_REGNO)
10434 (match_operand:SI 0 "immediate_operand" "s"))
10435 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10436 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10437 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10438 "bcl 20,31,%0\\n%0:"
10439 [(set_attr "type" "branch")
10440 (set_attr "length" "4")])
10442 (define_insn "load_toc_v4_PIC_1_476"
10443 [(set (reg:SI LR_REGNO)
10444 (match_operand:SI 0 "immediate_operand" "s"))
10445 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10446 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10447 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10448 "*
10449 {
10450 char name[32];
10451 static char templ[32];
10453 get_ppc476_thunk_name (name);
10454 sprintf (templ, \"bl %s\\n%%0:\", name);
10455 return templ;
10456 }"
10457 [(set_attr "type" "branch")
10458 (set_attr "length" "4")])
10460 (define_expand "load_toc_v4_PIC_1b"
10461 [(parallel [(set (reg:SI LR_REGNO)
10462 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10463 (label_ref (match_operand 1 "" ""))]
10464 UNSPEC_TOCPTR))
10465 (match_dup 1)])]
10466 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10467 "")
10469 (define_insn "load_toc_v4_PIC_1b_normal"
10470 [(set (reg:SI LR_REGNO)
10471 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10472 (label_ref (match_operand 1 "" ""))]
10473 UNSPEC_TOCPTR))
10474 (match_dup 1)]
10475 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10476 "bcl 20,31,$+8\;.long %0-$"
10477 [(set_attr "type" "branch")
10478 (set_attr "length" "8")])
10480 (define_insn "load_toc_v4_PIC_1b_476"
10481 [(set (reg:SI LR_REGNO)
10482 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10483 (label_ref (match_operand 1 "" ""))]
10484 UNSPEC_TOCPTR))
10485 (match_dup 1)]
10486 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10487 "*
10488 {
10489 char name[32];
10490 static char templ[32];
10492 get_ppc476_thunk_name (name);
10493 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10494 return templ;
10495 }"
10496 [(set_attr "type" "branch")
10497 (set_attr "length" "16")])
10499 (define_insn "load_toc_v4_PIC_2"
10500 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10501 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10502 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10503 (match_operand:SI 3 "immediate_operand" "s")))))]
10504 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10505 "lwz %0,%2-%3(%1)"
10506 [(set_attr "type" "load")])
10508 (define_insn "load_toc_v4_PIC_3b"
10509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10510 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10511 (high:SI
10512 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10513 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10514 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10515 "addis %0,%1,%2-%3@ha")
10517 (define_insn "load_toc_v4_PIC_3c"
10518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10519 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10520 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10521 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10522 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10523 "addi %0,%1,%2-%3@l")
10525 ;; If the TOC is shared over a translation unit, as happens with all
10526 ;; the kinds of PIC that we support, we need to restore the TOC
10527 ;; pointer only when jumping over units of translation.
10528 ;; On Darwin, we need to reload the picbase.
10530 (define_expand "builtin_setjmp_receiver"
10531 [(use (label_ref (match_operand 0 "" "")))]
10532 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10533 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10534 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10535 "
10536 {
10537 #if TARGET_MACHO
10538 if (DEFAULT_ABI == ABI_DARWIN)
10539 {
10540 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10541 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10542 rtx tmplabrtx;
10543 char tmplab[20];
10545 crtl->uses_pic_offset_table = 1;
10546 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10547 CODE_LABEL_NUMBER (operands[0]));
10548 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10550 emit_insn (gen_load_macho_picbase (tmplabrtx));
10551 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10552 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10553 }
10554 else
10555 #endif
10556 rs6000_emit_load_toc_table (FALSE);
10557 DONE;
10558 }")
10560 ;; Largetoc support
10561 (define_insn "*largetoc_high"
10562 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10563 (high:DI
10564 (unspec [(match_operand:DI 1 "" "")
10565 (match_operand:DI 2 "gpc_reg_operand" "b")]
10566 UNSPEC_TOCREL)))]
10567 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10568 "addis %0,%2,%1@toc@ha")
10570 (define_insn "*largetoc_high_aix<mode>"
10571 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10572 (high:P
10573 (unspec [(match_operand:P 1 "" "")
10574 (match_operand:P 2 "gpc_reg_operand" "b")]
10575 UNSPEC_TOCREL)))]
10576 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10577 "addis %0,%1@u(%2)")
10579 (define_insn "*largetoc_high_plus"
10580 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10581 (high:DI
10582 (plus:DI
10583 (unspec [(match_operand:DI 1 "" "")
10584 (match_operand:DI 2 "gpc_reg_operand" "b")]
10585 UNSPEC_TOCREL)
10586 (match_operand:DI 3 "add_cint_operand" "n"))))]
10587 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10588 "addis %0,%2,%1+%3@toc@ha")
10590 (define_insn "*largetoc_high_plus_aix<mode>"
10591 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10592 (high:P
10593 (plus:P
10594 (unspec [(match_operand:P 1 "" "")
10595 (match_operand:P 2 "gpc_reg_operand" "b")]
10596 UNSPEC_TOCREL)
10597 (match_operand:P 3 "add_cint_operand" "n"))))]
10598 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10599 "addis %0,%1+%3@u(%2)")
10601 (define_insn "*largetoc_low"
10602 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10603 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10604 (match_operand:DI 2 "" "")))]
10605 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10606 "@
10607 addi %0,%1,%2@l
10608 addic %0,%1,%2@l")
10610 (define_insn "*largetoc_low_aix<mode>"
10611 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10612 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10613 (match_operand:P 2 "" "")))]
10614 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10615 "la %0,%2@l(%1)")
10617 (define_insn_and_split "*tocref<mode>"
10618 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10619 (match_operand:P 1 "small_toc_ref" "R"))]
10620 "TARGET_TOC"
10621 "la %0,%a1"
10622 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10623 [(set (match_dup 0) (high:P (match_dup 1)))
10624 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10626 ;; Elf specific ways of loading addresses for non-PIC code.
10627 ;; The output of this could be r0, but we make a very strong
10628 ;; preference for a base register because it will usually
10629 ;; be needed there.
10630 (define_insn "elf_high"
10631 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10632 (high:SI (match_operand 1 "" "")))]
10633 "TARGET_ELF && ! TARGET_64BIT"
10634 "lis %0,%1@ha")
10636 (define_insn "elf_low"
10637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10638 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10639 (match_operand 2 "" "")))]
10640 "TARGET_ELF && ! TARGET_64BIT"
10641 "@
10642 la %0,%2@l(%1)
10643 addic %0,%1,%K2")
10644 \f
10645 ;; Call and call_value insns
10646 (define_expand "call"
10647 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10648 (match_operand 1 "" ""))
10649 (use (match_operand 2 "" ""))
10650 (clobber (reg:SI LR_REGNO))])]
10651 ""
10652 "
10653 {
10654 #if TARGET_MACHO
10655 if (MACHOPIC_INDIRECT)
10656 operands[0] = machopic_indirect_call_target (operands[0]);
10657 #endif
10659 gcc_assert (GET_CODE (operands[0]) == MEM);
10660 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10662 operands[0] = XEXP (operands[0], 0);
10664 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10665 {
10666 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10667 DONE;
10668 }
10670 if (GET_CODE (operands[0]) != SYMBOL_REF
10671 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10672 {
10673 if (INTVAL (operands[2]) & CALL_LONG)
10674 operands[0] = rs6000_longcall_ref (operands[0]);
10676 switch (DEFAULT_ABI)
10677 {
10678 case ABI_V4:
10679 case ABI_DARWIN:
10680 operands[0] = force_reg (Pmode, operands[0]);
10681 break;
10683 default:
10684 gcc_unreachable ();
10685 }
10686 }
10687 }")
10689 (define_expand "call_value"
10690 [(parallel [(set (match_operand 0 "" "")
10691 (call (mem:SI (match_operand 1 "address_operand" ""))
10692 (match_operand 2 "" "")))
10693 (use (match_operand 3 "" ""))
10694 (clobber (reg:SI LR_REGNO))])]
10695 ""
10696 "
10697 {
10698 #if TARGET_MACHO
10699 if (MACHOPIC_INDIRECT)
10700 operands[1] = machopic_indirect_call_target (operands[1]);
10701 #endif
10703 gcc_assert (GET_CODE (operands[1]) == MEM);
10704 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10706 operands[1] = XEXP (operands[1], 0);
10708 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10709 {
10710 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10711 DONE;
10712 }
10714 if (GET_CODE (operands[1]) != SYMBOL_REF
10715 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10716 {
10717 if (INTVAL (operands[3]) & CALL_LONG)
10718 operands[1] = rs6000_longcall_ref (operands[1]);
10720 switch (DEFAULT_ABI)
10721 {
10722 case ABI_V4:
10723 case ABI_DARWIN:
10724 operands[1] = force_reg (Pmode, operands[1]);
10725 break;
10727 default:
10728 gcc_unreachable ();
10729 }
10730 }
10731 }")
10733 ;; Call to function in current module. No TOC pointer reload needed.
10734 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10735 ;; either the function was not prototyped, or it was prototyped as a
10736 ;; variable argument function. It is > 0 if FP registers were passed
10737 ;; and < 0 if they were not.
10739 (define_insn "*call_local32"
10740 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10741 (match_operand 1 "" "g,g"))
10742 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10743 (clobber (reg:SI LR_REGNO))]
10744 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10745 "*
10746 {
10747 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10748 output_asm_insn (\"crxor 6,6,6\", operands);
10750 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10751 output_asm_insn (\"creqv 6,6,6\", operands);
10753 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10754 }"
10755 [(set_attr "type" "branch")
10756 (set_attr "length" "4,8")])
10758 (define_insn "*call_local64"
10759 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10760 (match_operand 1 "" "g,g"))
10761 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10762 (clobber (reg:SI LR_REGNO))]
10763 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10764 "*
10765 {
10766 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10767 output_asm_insn (\"crxor 6,6,6\", operands);
10769 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10770 output_asm_insn (\"creqv 6,6,6\", operands);
10772 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10773 }"
10774 [(set_attr "type" "branch")
10775 (set_attr "length" "4,8")])
10777 (define_insn "*call_value_local32"
10778 [(set (match_operand 0 "" "")
10779 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10780 (match_operand 2 "" "g,g")))
10781 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10782 (clobber (reg:SI LR_REGNO))]
10783 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10784 "*
10785 {
10786 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10787 output_asm_insn (\"crxor 6,6,6\", operands);
10789 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10790 output_asm_insn (\"creqv 6,6,6\", operands);
10792 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10793 }"
10794 [(set_attr "type" "branch")
10795 (set_attr "length" "4,8")])
10798 (define_insn "*call_value_local64"
10799 [(set (match_operand 0 "" "")
10800 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10801 (match_operand 2 "" "g,g")))
10802 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10803 (clobber (reg:SI LR_REGNO))]
10804 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10805 "*
10806 {
10807 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10808 output_asm_insn (\"crxor 6,6,6\", operands);
10810 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10811 output_asm_insn (\"creqv 6,6,6\", operands);
10813 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10814 }"
10815 [(set_attr "type" "branch")
10816 (set_attr "length" "4,8")])
10819 ;; A function pointer under System V is just a normal pointer
10820 ;; operands[0] is the function pointer
10821 ;; operands[1] is the stack size to clean up
10822 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10823 ;; which indicates how to set cr1
10825 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10826 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10827 (match_operand 1 "" "g,g,g,g"))
10828 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10829 (clobber (reg:SI LR_REGNO))]
10830 "DEFAULT_ABI == ABI_V4
10831 || DEFAULT_ABI == ABI_DARWIN"
10832 {
10833 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10834 output_asm_insn ("crxor 6,6,6", operands);
10836 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10837 output_asm_insn ("creqv 6,6,6", operands);
10839 return "b%T0l";
10840 }
10841 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10842 (set_attr "length" "4,4,8,8")])
10844 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10845 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10846 (match_operand 1 "" "g,g"))
10847 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10848 (clobber (reg:SI LR_REGNO))]
10849 "(DEFAULT_ABI == ABI_DARWIN
10850 || (DEFAULT_ABI == ABI_V4
10851 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10852 {
10853 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10854 output_asm_insn ("crxor 6,6,6", operands);
10856 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10857 output_asm_insn ("creqv 6,6,6", operands);
10859 #if TARGET_MACHO
10860 return output_call(insn, operands, 0, 2);
10861 #else
10862 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10863 {
10864 gcc_assert (!TARGET_SECURE_PLT);
10865 return "bl %z0@plt";
10866 }
10867 else
10868 return "bl %z0";
10869 #endif
10870 }
10871 "DEFAULT_ABI == ABI_V4
10872 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10873 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10874 [(parallel [(call (mem:SI (match_dup 0))
10875 (match_dup 1))
10876 (use (match_dup 2))
10877 (use (match_dup 3))
10878 (clobber (reg:SI LR_REGNO))])]
10879 {
10880 operands[3] = pic_offset_table_rtx;
10881 }
10882 [(set_attr "type" "branch,branch")
10883 (set_attr "length" "4,8")])
10885 (define_insn "*call_nonlocal_sysv_secure<mode>"
10886 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10887 (match_operand 1 "" "g,g"))
10888 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10889 (use (match_operand:SI 3 "register_operand" "r,r"))
10890 (clobber (reg:SI LR_REGNO))]
10891 "(DEFAULT_ABI == ABI_V4
10892 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10893 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10894 {
10895 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10896 output_asm_insn ("crxor 6,6,6", operands);
10898 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10899 output_asm_insn ("creqv 6,6,6", operands);
10901 if (flag_pic == 2)
10902 /* The magic 32768 offset here and in the other sysv call insns
10903 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10904 See sysv4.h:toc_section. */
10905 return "bl %z0+32768@plt";
10906 else
10907 return "bl %z0@plt";
10908 }
10909 [(set_attr "type" "branch,branch")
10910 (set_attr "length" "4,8")])
10912 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10913 [(set (match_operand 0 "" "")
10914 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10915 (match_operand 2 "" "g,g,g,g")))
10916 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10917 (clobber (reg:SI LR_REGNO))]
10918 "DEFAULT_ABI == ABI_V4
10919 || DEFAULT_ABI == ABI_DARWIN"
10920 {
10921 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10922 output_asm_insn ("crxor 6,6,6", operands);
10924 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10925 output_asm_insn ("creqv 6,6,6", operands);
10927 return "b%T1l";
10928 }
10929 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10930 (set_attr "length" "4,4,8,8")])
10932 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10933 [(set (match_operand 0 "" "")
10934 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10935 (match_operand 2 "" "g,g")))
10936 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10937 (clobber (reg:SI LR_REGNO))]
10938 "(DEFAULT_ABI == ABI_DARWIN
10939 || (DEFAULT_ABI == ABI_V4
10940 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10941 {
10942 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10943 output_asm_insn ("crxor 6,6,6", operands);
10945 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10946 output_asm_insn ("creqv 6,6,6", operands);
10948 #if TARGET_MACHO
10949 return output_call(insn, operands, 1, 3);
10950 #else
10951 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10952 {
10953 gcc_assert (!TARGET_SECURE_PLT);
10954 return "bl %z1@plt";
10955 }
10956 else
10957 return "bl %z1";
10958 #endif
10959 }
10960 "DEFAULT_ABI == ABI_V4
10961 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10962 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10963 [(parallel [(set (match_dup 0)
10964 (call (mem:SI (match_dup 1))
10965 (match_dup 2)))
10966 (use (match_dup 3))
10967 (use (match_dup 4))
10968 (clobber (reg:SI LR_REGNO))])]
10969 {
10970 operands[4] = pic_offset_table_rtx;
10971 }
10972 [(set_attr "type" "branch,branch")
10973 (set_attr "length" "4,8")])
10975 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
10976 [(set (match_operand 0 "" "")
10977 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10978 (match_operand 2 "" "g,g")))
10979 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10980 (use (match_operand:SI 4 "register_operand" "r,r"))
10981 (clobber (reg:SI LR_REGNO))]
10982 "(DEFAULT_ABI == ABI_V4
10983 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10984 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
10985 {
10986 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10987 output_asm_insn ("crxor 6,6,6", operands);
10989 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10990 output_asm_insn ("creqv 6,6,6", operands);
10992 if (flag_pic == 2)
10993 return "bl %z1+32768@plt";
10994 else
10995 return "bl %z1@plt";
10996 }
10997 [(set_attr "type" "branch,branch")
10998 (set_attr "length" "4,8")])
11001 ;; Call to AIX abi function in the same module.
11003 (define_insn "*call_local_aix<mode>"
11004 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11005 (match_operand 1 "" "g"))
11006 (clobber (reg:P LR_REGNO))]
11007 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11008 "bl %z0"
11009 [(set_attr "type" "branch")
11010 (set_attr "length" "4")])
11012 (define_insn "*call_value_local_aix<mode>"
11013 [(set (match_operand 0 "" "")
11014 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11015 (match_operand 2 "" "g")))
11016 (clobber (reg:P LR_REGNO))]
11017 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11018 "bl %z1"
11019 [(set_attr "type" "branch")
11020 (set_attr "length" "4")])
11022 ;; Call to AIX abi function which may be in another module.
11023 ;; Restore the TOC pointer (r2) after the call.
11025 (define_insn "*call_nonlocal_aix<mode>"
11026 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11027 (match_operand 1 "" "g"))
11028 (clobber (reg:P LR_REGNO))]
11029 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11030 "bl %z0\;nop"
11031 [(set_attr "type" "branch")
11032 (set_attr "length" "8")])
11034 (define_insn "*call_value_nonlocal_aix<mode>"
11035 [(set (match_operand 0 "" "")
11036 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11037 (match_operand 2 "" "g")))
11038 (clobber (reg:P LR_REGNO))]
11039 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11040 "bl %z1\;nop"
11041 [(set_attr "type" "branch")
11042 (set_attr "length" "8")])
11044 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11045 ;; Operand0 is the addresss of the function to call
11046 ;; Operand2 is the location in the function descriptor to load r2 from
11047 ;; Operand3 is the stack location to hold the current TOC pointer
11049 (define_insn "*call_indirect_aix<mode>"
11050 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11051 (match_operand 1 "" "g,g"))
11052 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11053 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11054 (clobber (reg:P LR_REGNO))]
11055 "DEFAULT_ABI == ABI_AIX"
11056 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11057 [(set_attr "type" "jmpreg")
11058 (set_attr "length" "12")])
11060 (define_insn "*call_value_indirect_aix<mode>"
11061 [(set (match_operand 0 "" "")
11062 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11063 (match_operand 2 "" "g,g")))
11064 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11065 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11066 (clobber (reg:P LR_REGNO))]
11067 "DEFAULT_ABI == ABI_AIX"
11068 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11069 [(set_attr "type" "jmpreg")
11070 (set_attr "length" "12")])
11072 ;; Call to indirect functions with the ELFv2 ABI.
11073 ;; Operand0 is the addresss of the function to call
11074 ;; Operand2 is the stack location to hold the current TOC pointer
11076 (define_insn "*call_indirect_elfv2<mode>"
11077 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11078 (match_operand 1 "" "g,g"))
11079 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11080 (clobber (reg:P LR_REGNO))]
11081 "DEFAULT_ABI == ABI_ELFv2"
11082 "b%T0l\;<ptrload> 2,%2"
11083 [(set_attr "type" "jmpreg")
11084 (set_attr "length" "8")])
11086 (define_insn "*call_value_indirect_elfv2<mode>"
11087 [(set (match_operand 0 "" "")
11088 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11089 (match_operand 2 "" "g,g")))
11090 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11091 (clobber (reg:P LR_REGNO))]
11092 "DEFAULT_ABI == ABI_ELFv2"
11093 "b%T1l\;<ptrload> 2,%3"
11094 [(set_attr "type" "jmpreg")
11095 (set_attr "length" "8")])
11098 ;; Call subroutine returning any type.
11099 (define_expand "untyped_call"
11100 [(parallel [(call (match_operand 0 "" "")
11101 (const_int 0))
11102 (match_operand 1 "" "")
11103 (match_operand 2 "" "")])]
11104 ""
11105 "
11106 {
11107 int i;
11109 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11111 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11112 {
11113 rtx set = XVECEXP (operands[2], 0, i);
11114 emit_move_insn (SET_DEST (set), SET_SRC (set));
11115 }
11117 /* The optimizer does not know that the call sets the function value
11118 registers we stored in the result block. We avoid problems by
11119 claiming that all hard registers are used and clobbered at this
11120 point. */
11121 emit_insn (gen_blockage ());
11123 DONE;
11124 }")
11126 ;; sibling call patterns
11127 (define_expand "sibcall"
11128 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11129 (match_operand 1 "" ""))
11130 (use (match_operand 2 "" ""))
11131 (use (reg:SI LR_REGNO))
11132 (simple_return)])]
11133 ""
11134 "
11135 {
11136 #if TARGET_MACHO
11137 if (MACHOPIC_INDIRECT)
11138 operands[0] = machopic_indirect_call_target (operands[0]);
11139 #endif
11141 gcc_assert (GET_CODE (operands[0]) == MEM);
11142 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11144 operands[0] = XEXP (operands[0], 0);
11146 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11147 {
11148 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11149 DONE;
11150 }
11151 }")
11153 (define_expand "sibcall_value"
11154 [(parallel [(set (match_operand 0 "register_operand" "")
11155 (call (mem:SI (match_operand 1 "address_operand" ""))
11156 (match_operand 2 "" "")))
11157 (use (match_operand 3 "" ""))
11158 (use (reg:SI LR_REGNO))
11159 (simple_return)])]
11160 ""
11161 "
11162 {
11163 #if TARGET_MACHO
11164 if (MACHOPIC_INDIRECT)
11165 operands[1] = machopic_indirect_call_target (operands[1]);
11166 #endif
11168 gcc_assert (GET_CODE (operands[1]) == MEM);
11169 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11171 operands[1] = XEXP (operands[1], 0);
11173 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11174 {
11175 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11176 DONE;
11177 }
11178 }")
11180 ;; this and similar patterns must be marked as using LR, otherwise
11181 ;; dataflow will try to delete the store into it. This is true
11182 ;; even when the actual reg to jump to is in CTR, when LR was
11183 ;; saved and restored around the PIC-setting BCL.
11184 (define_insn "*sibcall_local32"
11185 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11186 (match_operand 1 "" "g,g"))
11187 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11188 (use (reg:SI LR_REGNO))
11189 (simple_return)]
11190 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11191 "*
11192 {
11193 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11194 output_asm_insn (\"crxor 6,6,6\", operands);
11196 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11197 output_asm_insn (\"creqv 6,6,6\", operands);
11199 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11200 }"
11201 [(set_attr "type" "branch")
11202 (set_attr "length" "4,8")])
11204 (define_insn "*sibcall_local64"
11205 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11206 (match_operand 1 "" "g,g"))
11207 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11208 (use (reg:SI LR_REGNO))
11209 (simple_return)]
11210 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11211 "*
11212 {
11213 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11214 output_asm_insn (\"crxor 6,6,6\", operands);
11216 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11217 output_asm_insn (\"creqv 6,6,6\", operands);
11219 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11220 }"
11221 [(set_attr "type" "branch")
11222 (set_attr "length" "4,8")])
11224 (define_insn "*sibcall_value_local32"
11225 [(set (match_operand 0 "" "")
11226 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11227 (match_operand 2 "" "g,g")))
11228 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11229 (use (reg:SI LR_REGNO))
11230 (simple_return)]
11231 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11232 "*
11233 {
11234 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11235 output_asm_insn (\"crxor 6,6,6\", operands);
11237 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11238 output_asm_insn (\"creqv 6,6,6\", operands);
11240 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11241 }"
11242 [(set_attr "type" "branch")
11243 (set_attr "length" "4,8")])
11245 (define_insn "*sibcall_value_local64"
11246 [(set (match_operand 0 "" "")
11247 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11248 (match_operand 2 "" "g,g")))
11249 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11250 (use (reg:SI LR_REGNO))
11251 (simple_return)]
11252 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11253 "*
11254 {
11255 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11256 output_asm_insn (\"crxor 6,6,6\", operands);
11258 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11259 output_asm_insn (\"creqv 6,6,6\", operands);
11261 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11262 }"
11263 [(set_attr "type" "branch")
11264 (set_attr "length" "4,8")])
11266 (define_insn "*sibcall_nonlocal_sysv<mode>"
11267 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11268 (match_operand 1 "" ""))
11269 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11270 (use (reg:SI LR_REGNO))
11271 (simple_return)]
11272 "(DEFAULT_ABI == ABI_DARWIN
11273 || DEFAULT_ABI == ABI_V4)
11274 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11275 "*
11276 {
11277 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11278 output_asm_insn (\"crxor 6,6,6\", operands);
11280 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11281 output_asm_insn (\"creqv 6,6,6\", operands);
11283 if (which_alternative >= 2)
11284 return \"b%T0\";
11285 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11286 {
11287 gcc_assert (!TARGET_SECURE_PLT);
11288 return \"b %z0@plt\";
11289 }
11290 else
11291 return \"b %z0\";
11292 }"
11293 [(set_attr "type" "branch")
11294 (set_attr "length" "4,8,4,8")])
11296 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11297 [(set (match_operand 0 "" "")
11298 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11299 (match_operand 2 "" "")))
11300 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11301 (use (reg:SI LR_REGNO))
11302 (simple_return)]
11303 "(DEFAULT_ABI == ABI_DARWIN
11304 || DEFAULT_ABI == ABI_V4)
11305 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11306 "*
11307 {
11308 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11309 output_asm_insn (\"crxor 6,6,6\", operands);
11311 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11312 output_asm_insn (\"creqv 6,6,6\", operands);
11314 if (which_alternative >= 2)
11315 return \"b%T1\";
11316 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11317 {
11318 gcc_assert (!TARGET_SECURE_PLT);
11319 return \"b %z1@plt\";
11320 }
11321 else
11322 return \"b %z1\";
11323 }"
11324 [(set_attr "type" "branch")
11325 (set_attr "length" "4,8,4,8")])
11327 ;; AIX ABI sibling call patterns.
11329 (define_insn "*sibcall_aix<mode>"
11330 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11331 (match_operand 1 "" "g,g"))
11332 (simple_return)]
11333 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11334 "@
11335 b %z0
11336 b%T0"
11337 [(set_attr "type" "branch")
11338 (set_attr "length" "4")])
11340 (define_insn "*sibcall_value_aix<mode>"
11341 [(set (match_operand 0 "" "")
11342 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11343 (match_operand 2 "" "g,g")))
11344 (simple_return)]
11345 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11346 "@
11347 b %z1
11348 b%T1"
11349 [(set_attr "type" "branch")
11350 (set_attr "length" "4")])
11352 (define_expand "sibcall_epilogue"
11353 [(use (const_int 0))]
11354 ""
11355 {
11356 if (!TARGET_SCHED_PROLOG)
11357 emit_insn (gen_blockage ());
11358 rs6000_emit_epilogue (TRUE);
11359 DONE;
11360 })
11362 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11363 ;; all of memory. This blocks insns from being moved across this point.
11365 (define_insn "blockage"
11366 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11367 ""
11368 "")
11370 (define_expand "probe_stack"
11371 [(set (match_operand 0 "memory_operand" "=m")
11372 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11373 ""
11374 {
11375 if (TARGET_64BIT)
11376 emit_insn (gen_probe_stack_di (operands[0]));
11377 else
11378 emit_insn (gen_probe_stack_si (operands[0]));
11379 DONE;
11380 })
11382 (define_insn "probe_stack_<mode>"
11383 [(set (match_operand:P 0 "memory_operand" "=m")
11384 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11385 ""
11386 {
11387 operands[1] = gen_rtx_REG (Pmode, 0);
11388 return "st<wd>%U0%X0 %1,%0";
11389 }
11390 [(set_attr "type" "store")
11391 (set (attr "update")
11392 (if_then_else (match_operand 0 "update_address_mem")
11393 (const_string "yes")
11394 (const_string "no")))
11395 (set (attr "indexed")
11396 (if_then_else (match_operand 0 "indexed_address_mem")
11397 (const_string "yes")
11398 (const_string "no")))
11399 (set_attr "length" "4")])
11401 (define_insn "probe_stack_range<P:mode>"
11402 [(set (match_operand:P 0 "register_operand" "=r")
11403 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11404 (match_operand:P 2 "register_operand" "r")]
11405 UNSPECV_PROBE_STACK_RANGE))]
11406 ""
11407 "* return output_probe_stack_range (operands[0], operands[2]);"
11408 [(set_attr "type" "three")])
11409 \f
11410 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11411 ;; signed & unsigned, and one type of branch.
11412 ;;
11413 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11414 ;; insns, and branches.
11416 (define_expand "cbranch<mode>4"
11417 [(use (match_operator 0 "rs6000_cbranch_operator"
11418 [(match_operand:GPR 1 "gpc_reg_operand" "")
11419 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11420 (use (match_operand 3 ""))]
11421 ""
11422 "
11423 {
11424 /* Take care of the possibility that operands[2] might be negative but
11425 this might be a logical operation. That insn doesn't exist. */
11426 if (GET_CODE (operands[2]) == CONST_INT
11427 && INTVAL (operands[2]) < 0)
11428 {
11429 operands[2] = force_reg (<MODE>mode, operands[2]);
11430 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11431 GET_MODE (operands[0]),
11432 operands[1], operands[2]);
11433 }
11435 rs6000_emit_cbranch (<MODE>mode, operands);
11436 DONE;
11437 }")
11439 (define_expand "cbranch<mode>4"
11440 [(use (match_operator 0 "rs6000_cbranch_operator"
11441 [(match_operand:FP 1 "gpc_reg_operand" "")
11442 (match_operand:FP 2 "gpc_reg_operand" "")]))
11443 (use (match_operand 3 ""))]
11444 ""
11445 "
11446 {
11447 rs6000_emit_cbranch (<MODE>mode, operands);
11448 DONE;
11449 }")
11451 (define_expand "cstore<mode>4"
11452 [(use (match_operator 1 "rs6000_cbranch_operator"
11453 [(match_operand:GPR 2 "gpc_reg_operand" "")
11454 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11455 (clobber (match_operand:SI 0 "register_operand"))]
11456 ""
11457 "
11458 {
11459 /* Take care of the possibility that operands[3] might be negative but
11460 this might be a logical operation. That insn doesn't exist. */
11461 if (GET_CODE (operands[3]) == CONST_INT
11462 && INTVAL (operands[3]) < 0)
11463 {
11464 operands[3] = force_reg (<MODE>mode, operands[3]);
11465 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11466 GET_MODE (operands[1]),
11467 operands[2], operands[3]);
11468 }
11470 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11471 For SEQ, likewise, except that comparisons with zero should be done
11472 with an scc insns. However, due to the order that combine see the
11473 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11474 the cases we don't want to handle or are best handled by portable
11475 code. */
11476 if (GET_CODE (operands[1]) == NE)
11477 FAIL;
11478 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11479 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11480 && operands[3] == const0_rtx)
11481 FAIL;
11482 rs6000_emit_sCOND (<MODE>mode, operands);
11483 DONE;
11484 }")
11486 (define_expand "cstore<mode>4"
11487 [(use (match_operator 1 "rs6000_cbranch_operator"
11488 [(match_operand:FP 2 "gpc_reg_operand" "")
11489 (match_operand:FP 3 "gpc_reg_operand" "")]))
11490 (clobber (match_operand:SI 0 "register_operand"))]
11491 ""
11492 "
11493 {
11494 rs6000_emit_sCOND (<MODE>mode, operands);
11495 DONE;
11496 }")
11499 (define_expand "stack_protect_set"
11500 [(match_operand 0 "memory_operand" "")
11501 (match_operand 1 "memory_operand" "")]
11502 ""
11503 {
11504 #ifdef TARGET_THREAD_SSP_OFFSET
11505 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11506 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11507 operands[1] = gen_rtx_MEM (Pmode, addr);
11508 #endif
11509 if (TARGET_64BIT)
11510 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11511 else
11512 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11513 DONE;
11514 })
11516 (define_insn "stack_protect_setsi"
11517 [(set (match_operand:SI 0 "memory_operand" "=m")
11518 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11519 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11520 "TARGET_32BIT"
11521 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11522 [(set_attr "type" "three")
11523 (set_attr "length" "12")])
11525 (define_insn "stack_protect_setdi"
11526 [(set (match_operand:DI 0 "memory_operand" "=Y")
11527 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11528 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11529 "TARGET_64BIT"
11530 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11531 [(set_attr "type" "three")
11532 (set_attr "length" "12")])
11534 (define_expand "stack_protect_test"
11535 [(match_operand 0 "memory_operand" "")
11536 (match_operand 1 "memory_operand" "")
11537 (match_operand 2 "" "")]
11538 ""
11539 {
11540 rtx test, op0, op1;
11541 #ifdef TARGET_THREAD_SSP_OFFSET
11542 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11543 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11544 operands[1] = gen_rtx_MEM (Pmode, addr);
11545 #endif
11546 op0 = operands[0];
11547 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11548 test = gen_rtx_EQ (VOIDmode, op0, op1);
11549 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11550 DONE;
11551 })
11553 (define_insn "stack_protect_testsi"
11554 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11555 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11556 (match_operand:SI 2 "memory_operand" "m,m")]
11557 UNSPEC_SP_TEST))
11558 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11559 (clobber (match_scratch:SI 3 "=&r,&r"))]
11560 "TARGET_32BIT"
11561 "@
11562 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11563 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11564 [(set_attr "length" "16,20")])
11566 (define_insn "stack_protect_testdi"
11567 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11568 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11569 (match_operand:DI 2 "memory_operand" "Y,Y")]
11570 UNSPEC_SP_TEST))
11571 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11572 (clobber (match_scratch:DI 3 "=&r,&r"))]
11573 "TARGET_64BIT"
11574 "@
11575 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11576 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11577 [(set_attr "length" "16,20")])
11579 \f
11580 ;; Here are the actual compare insns.
11581 (define_insn "*cmp<mode>_internal1"
11582 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11583 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11584 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11585 ""
11586 "cmp<wd>%I2 %0,%1,%2"
11587 [(set_attr "type" "cmp")])
11589 ;; If we are comparing a register for equality with a large constant,
11590 ;; we can do this with an XOR followed by a compare. But this is profitable
11591 ;; only if the large constant is only used for the comparison (and in this
11592 ;; case we already have a register to reuse as scratch).
11593 ;;
11594 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11595 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11597 (define_peephole2
11598 [(set (match_operand:SI 0 "register_operand")
11599 (match_operand:SI 1 "logical_const_operand" ""))
11600 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11601 [(match_dup 0)
11602 (match_operand:SI 2 "logical_const_operand" "")]))
11603 (set (match_operand:CC 4 "cc_reg_operand" "")
11604 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11605 (match_dup 0)))
11606 (set (pc)
11607 (if_then_else (match_operator 6 "equality_operator"
11608 [(match_dup 4) (const_int 0)])
11609 (match_operand 7 "" "")
11610 (match_operand 8 "" "")))]
11611 "peep2_reg_dead_p (3, operands[0])
11612 && peep2_reg_dead_p (4, operands[4])"
11613 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11614 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11615 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11617 {
11618 /* Get the constant we are comparing against, and see what it looks like
11619 when sign-extended from 16 to 32 bits. Then see what constant we could
11620 XOR with SEXTC to get the sign-extended value. */
11621 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11622 SImode,
11623 operands[1], operands[2]);
11624 HOST_WIDE_INT c = INTVAL (cnst);
11625 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11626 HOST_WIDE_INT xorv = c ^ sextc;
11628 operands[9] = GEN_INT (xorv);
11629 operands[10] = GEN_INT (sextc);
11630 })
11632 (define_insn "*cmpsi_internal2"
11633 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11634 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11635 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11636 ""
11637 "cmplw%I2 %0,%1,%b2"
11638 [(set_attr "type" "cmp")])
11640 (define_insn "*cmpdi_internal2"
11641 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11642 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11643 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11644 ""
11645 "cmpld%I2 %0,%1,%b2"
11646 [(set_attr "type" "cmp")])
11648 ;; The following two insns don't exist as single insns, but if we provide
11649 ;; them, we can swap an add and compare, which will enable us to overlap more
11650 ;; of the required delay between a compare and branch. We generate code for
11651 ;; them by splitting.
11653 (define_insn ""
11654 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11655 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11656 (match_operand:SI 2 "short_cint_operand" "i")))
11657 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11658 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11659 ""
11660 "#"
11661 [(set_attr "length" "8")])
11663 (define_insn ""
11664 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11665 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11666 (match_operand:SI 2 "u_short_cint_operand" "i")))
11667 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11668 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11669 ""
11670 "#"
11671 [(set_attr "length" "8")])
11673 (define_split
11674 [(set (match_operand:CC 3 "cc_reg_operand" "")
11675 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11676 (match_operand:SI 2 "short_cint_operand" "")))
11677 (set (match_operand:SI 0 "gpc_reg_operand" "")
11678 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11679 ""
11680 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11681 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11683 (define_split
11684 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11685 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11686 (match_operand:SI 2 "u_short_cint_operand" "")))
11687 (set (match_operand:SI 0 "gpc_reg_operand" "")
11688 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11689 ""
11690 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11691 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11693 ;; Only need to compare second words if first words equal
11694 (define_insn "*cmptf_internal1"
11695 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11696 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11697 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11698 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11699 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11700 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11701 [(set_attr "type" "fpcompare")
11702 (set_attr "length" "12")])
11704 (define_insn_and_split "*cmptf_internal2"
11705 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11706 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11707 (match_operand:TF 2 "gpc_reg_operand" "d")))
11708 (clobber (match_scratch:DF 3 "=d"))
11709 (clobber (match_scratch:DF 4 "=d"))
11710 (clobber (match_scratch:DF 5 "=d"))
11711 (clobber (match_scratch:DF 6 "=d"))
11712 (clobber (match_scratch:DF 7 "=d"))
11713 (clobber (match_scratch:DF 8 "=d"))
11714 (clobber (match_scratch:DF 9 "=d"))
11715 (clobber (match_scratch:DF 10 "=d"))
11716 (clobber (match_scratch:GPR 11 "=b"))]
11717 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11718 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11719 "#"
11720 "&& reload_completed"
11721 [(set (match_dup 3) (match_dup 14))
11722 (set (match_dup 4) (match_dup 15))
11723 (set (match_dup 9) (abs:DF (match_dup 5)))
11724 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11725 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11726 (label_ref (match_dup 12))
11727 (pc)))
11728 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11729 (set (pc) (label_ref (match_dup 13)))
11730 (match_dup 12)
11731 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11732 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11733 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11734 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11735 (match_dup 13)]
11736 {
11737 REAL_VALUE_TYPE rv;
11738 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11739 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11741 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11742 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11743 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11744 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11745 operands[12] = gen_label_rtx ();
11746 operands[13] = gen_label_rtx ();
11747 real_inf (&rv);
11748 operands[14] = force_const_mem (DFmode,
11749 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11750 operands[15] = force_const_mem (DFmode,
11751 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11752 DFmode));
11753 if (TARGET_TOC)
11754 {
11755 rtx tocref;
11756 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11757 operands[14] = gen_const_mem (DFmode, tocref);
11758 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11759 operands[15] = gen_const_mem (DFmode, tocref);
11760 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11761 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11762 }
11763 })
11764 \f
11765 ;; Now we have the scc insns. We can do some combinations because of the
11766 ;; way the machine works.
11767 ;;
11768 ;; Note that this is probably faster if we can put an insn between the
11769 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11770 ;; cases the insns below which don't use an intermediate CR field will
11771 ;; be used instead.
11772 (define_insn ""
11773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11774 (match_operator:SI 1 "scc_comparison_operator"
11775 [(match_operand 2 "cc_reg_operand" "y")
11776 (const_int 0)]))]
11777 ""
11778 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11779 [(set (attr "type")
11780 (cond [(match_test "TARGET_MFCRF")
11781 (const_string "mfcrf")
11782 ]
11783 (const_string "mfcr")))
11784 (set_attr "length" "8")])
11786 ;; Same as above, but get the GT bit.
11787 (define_insn "move_from_CR_gt_bit"
11788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11789 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11790 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11791 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11792 [(set_attr "type" "mfcr")
11793 (set_attr "length" "8")])
11795 ;; Same as above, but get the OV/ORDERED bit.
11796 (define_insn "move_from_CR_ov_bit"
11797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11798 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11799 UNSPEC_MV_CR_OV))]
11800 "TARGET_ISEL"
11801 "mfcr %0\;rlwinm %0,%0,%t1,1"
11802 [(set_attr "type" "mfcr")
11803 (set_attr "length" "8")])
11805 (define_insn ""
11806 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11807 (match_operator:DI 1 "scc_comparison_operator"
11808 [(match_operand 2 "cc_reg_operand" "y")
11809 (const_int 0)]))]
11810 "TARGET_POWERPC64"
11811 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11812 [(set (attr "type")
11813 (cond [(match_test "TARGET_MFCRF")
11814 (const_string "mfcrf")
11815 ]
11816 (const_string "mfcr")))
11817 (set_attr "length" "8")])
11819 (define_insn ""
11820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11821 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11822 [(match_operand 2 "cc_reg_operand" "y,y")
11823 (const_int 0)])
11824 (const_int 0)))
11825 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11826 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11827 "TARGET_32BIT"
11828 "@
11829 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11830 #"
11831 [(set_attr "type" "shift")
11832 (set_attr "dot" "yes")
11833 (set_attr "length" "8,16")])
11835 (define_split
11836 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11837 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11838 [(match_operand 2 "cc_reg_operand" "")
11839 (const_int 0)])
11840 (const_int 0)))
11841 (set (match_operand:SI 3 "gpc_reg_operand" "")
11842 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11843 "TARGET_32BIT && reload_completed"
11844 [(set (match_dup 3)
11845 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11846 (set (match_dup 0)
11847 (compare:CC (match_dup 3)
11848 (const_int 0)))]
11849 "")
11851 (define_insn ""
11852 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11853 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11854 [(match_operand 2 "cc_reg_operand" "y")
11855 (const_int 0)])
11856 (match_operand:SI 3 "const_int_operand" "n")))]
11857 ""
11858 "*
11859 {
11860 int is_bit = ccr_bit (operands[1], 1);
11861 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11862 int count;
11864 if (is_bit >= put_bit)
11865 count = is_bit - put_bit;
11866 else
11867 count = 32 - (put_bit - is_bit);
11869 operands[4] = GEN_INT (count);
11870 operands[5] = GEN_INT (put_bit);
11872 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11873 }"
11874 [(set (attr "type")
11875 (cond [(match_test "TARGET_MFCRF")
11876 (const_string "mfcrf")
11877 ]
11878 (const_string "mfcr")))
11879 (set_attr "length" "8")])
11881 (define_insn ""
11882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11883 (compare:CC
11884 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11885 [(match_operand 2 "cc_reg_operand" "y,y")
11886 (const_int 0)])
11887 (match_operand:SI 3 "const_int_operand" "n,n"))
11888 (const_int 0)))
11889 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11890 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11891 (match_dup 3)))]
11892 ""
11893 "*
11894 {
11895 int is_bit = ccr_bit (operands[1], 1);
11896 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11897 int count;
11899 /* Force split for non-cc0 compare. */
11900 if (which_alternative == 1)
11901 return \"#\";
11903 if (is_bit >= put_bit)
11904 count = is_bit - put_bit;
11905 else
11906 count = 32 - (put_bit - is_bit);
11908 operands[5] = GEN_INT (count);
11909 operands[6] = GEN_INT (put_bit);
11911 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11912 }"
11913 [(set_attr "type" "shift")
11914 (set_attr "dot" "yes")
11915 (set_attr "length" "8,16")])
11917 (define_split
11918 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11919 (compare:CC
11920 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11921 [(match_operand 2 "cc_reg_operand" "")
11922 (const_int 0)])
11923 (match_operand:SI 3 "const_int_operand" ""))
11924 (const_int 0)))
11925 (set (match_operand:SI 4 "gpc_reg_operand" "")
11926 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11927 (match_dup 3)))]
11928 "reload_completed"
11929 [(set (match_dup 4)
11930 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11931 (match_dup 3)))
11932 (set (match_dup 0)
11933 (compare:CC (match_dup 4)
11934 (const_int 0)))]
11935 "")
11937 ;; There is a 3 cycle delay between consecutive mfcr instructions
11938 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11940 (define_peephole
11941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11942 (match_operator:SI 1 "scc_comparison_operator"
11943 [(match_operand 2 "cc_reg_operand" "y")
11944 (const_int 0)]))
11945 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11946 (match_operator:SI 4 "scc_comparison_operator"
11947 [(match_operand 5 "cc_reg_operand" "y")
11948 (const_int 0)]))]
11949 "REGNO (operands[2]) != REGNO (operands[5])"
11950 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11951 [(set_attr "type" "mfcr")
11952 (set_attr "length" "12")])
11954 (define_peephole
11955 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11956 (match_operator:DI 1 "scc_comparison_operator"
11957 [(match_operand 2 "cc_reg_operand" "y")
11958 (const_int 0)]))
11959 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11960 (match_operator:DI 4 "scc_comparison_operator"
11961 [(match_operand 5 "cc_reg_operand" "y")
11962 (const_int 0)]))]
11963 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11964 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11965 [(set_attr "type" "mfcr")
11966 (set_attr "length" "12")])
11968 ;; There are some scc insns that can be done directly, without a compare.
11969 ;; These are faster because they don't involve the communications between
11970 ;; the FXU and branch units. In fact, we will be replacing all of the
11971 ;; integer scc insns here or in the portable methods in emit_store_flag.
11972 ;;
11973 ;; Also support (neg (scc ..)) since that construct is used to replace
11974 ;; branches, (plus (scc ..) ..) since that construct is common and
11975 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11976 ;; cases where it is no more expensive than (neg (scc ..)).
11978 ;; Have reload force a constant into a register for the simple insns that
11979 ;; otherwise won't accept constants. We do this because it is faster than
11980 ;; the cmp/mfcr sequence we would otherwise generate.
11982 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11983 (DI "rKJI")])
11985 (define_insn_and_split "*eq<mode>"
11986 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11987 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11988 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11989 ""
11990 "#"
11991 ""
11992 [(set (match_dup 0)
11993 (clz:GPR (match_dup 3)))
11994 (set (match_dup 0)
11995 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11996 {
11997 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11998 {
11999 /* Use output operand as intermediate. */
12000 operands[3] = operands[0];
12002 if (logical_operand (operands[2], <MODE>mode))
12003 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12004 gen_rtx_XOR (<MODE>mode,
12005 operands[1], operands[2])));
12006 else
12007 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12008 gen_rtx_PLUS (<MODE>mode, operands[1],
12009 negate_rtx (<MODE>mode,
12010 operands[2]))));
12011 }
12012 else
12013 operands[3] = operands[1];
12015 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12016 })
12018 (define_insn_and_split "*eq<mode>_compare"
12019 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12020 (compare:CC
12021 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12022 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12023 (const_int 0)))
12024 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12025 (eq:P (match_dup 1) (match_dup 2)))]
12026 "optimize_size"
12027 "#"
12028 "optimize_size"
12029 [(set (match_dup 0)
12030 (clz:P (match_dup 4)))
12031 (parallel [(set (match_dup 3)
12032 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12033 (const_int 0)))
12034 (set (match_dup 0)
12035 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12036 {
12037 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12038 {
12039 /* Use output operand as intermediate. */
12040 operands[4] = operands[0];
12042 if (logical_operand (operands[2], <MODE>mode))
12043 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12044 gen_rtx_XOR (<MODE>mode,
12045 operands[1], operands[2])));
12046 else
12047 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12048 gen_rtx_PLUS (<MODE>mode, operands[1],
12049 negate_rtx (<MODE>mode,
12050 operands[2]))));
12051 }
12052 else
12053 operands[4] = operands[1];
12055 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12056 })
12058 ;; We have insns of the form shown by the first define_insn below. If
12059 ;; there is something inside the comparison operation, we must split it.
12060 (define_split
12061 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12062 (plus:SI (match_operator 1 "comparison_operator"
12063 [(match_operand:SI 2 "" "")
12064 (match_operand:SI 3
12065 "reg_or_cint_operand" "")])
12066 (match_operand:SI 4 "gpc_reg_operand" "")))
12067 (clobber (match_operand:SI 5 "register_operand" ""))]
12068 "! gpc_reg_operand (operands[2], SImode)"
12069 [(set (match_dup 5) (match_dup 2))
12070 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12071 (match_dup 4)))])
12073 (define_insn "*plus_eqsi"
12074 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12075 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12076 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12077 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12078 "TARGET_32BIT"
12079 "@
12080 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12081 subfic %0,%1,0\;addze %0,%3
12082 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12083 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12084 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12085 [(set_attr "type" "three,two,three,three,three")
12086 (set_attr "length" "12,8,12,12,12")])
12088 (define_insn "*compare_plus_eqsi"
12089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12090 (compare:CC
12091 (plus:SI
12092 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12093 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12094 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12095 (const_int 0)))
12096 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12097 "TARGET_32BIT && optimize_size"
12098 "@
12099 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12100 subfic %4,%1,0\;addze. %4,%3
12101 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12102 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12103 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12104 #
12105 #
12106 #
12107 #
12108 #"
12109 [(set_attr "type" "compare")
12110 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12112 (define_split
12113 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12114 (compare:CC
12115 (plus:SI
12116 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12117 (match_operand:SI 2 "scc_eq_operand" ""))
12118 (match_operand:SI 3 "gpc_reg_operand" ""))
12119 (const_int 0)))
12120 (clobber (match_scratch:SI 4 ""))]
12121 "TARGET_32BIT && optimize_size && reload_completed"
12122 [(set (match_dup 4)
12123 (plus:SI (eq:SI (match_dup 1)
12124 (match_dup 2))
12125 (match_dup 3)))
12126 (set (match_dup 0)
12127 (compare:CC (match_dup 4)
12128 (const_int 0)))]
12129 "")
12131 (define_insn "*plus_eqsi_compare"
12132 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12133 (compare:CC
12134 (plus:SI
12135 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12136 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12137 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12138 (const_int 0)))
12139 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12140 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12141 "TARGET_32BIT && optimize_size"
12142 "@
12143 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12144 subfic %0,%1,0\;addze. %0,%3
12145 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12146 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12147 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12148 #
12149 #
12150 #
12151 #
12152 #"
12153 [(set_attr "type" "compare")
12154 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12156 (define_split
12157 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12158 (compare:CC
12159 (plus:SI
12160 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12161 (match_operand:SI 2 "scc_eq_operand" ""))
12162 (match_operand:SI 3 "gpc_reg_operand" ""))
12163 (const_int 0)))
12164 (set (match_operand:SI 0 "gpc_reg_operand" "")
12165 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12166 "TARGET_32BIT && optimize_size && reload_completed"
12167 [(set (match_dup 0)
12168 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12169 (set (match_dup 4)
12170 (compare:CC (match_dup 0)
12171 (const_int 0)))]
12172 "")
12174 (define_insn "*neg_eq0<mode>"
12175 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12176 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12177 (const_int 0))))]
12178 ""
12179 "addic %0,%1,-1\;subfe %0,%0,%0"
12180 [(set_attr "type" "two")
12181 (set_attr "length" "8")])
12183 (define_insn_and_split "*neg_eq<mode>"
12184 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12185 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12186 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12187 ""
12188 "#"
12189 ""
12190 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12191 {
12192 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12193 {
12194 /* Use output operand as intermediate. */
12195 operands[3] = operands[0];
12197 if (logical_operand (operands[2], <MODE>mode))
12198 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12199 gen_rtx_XOR (<MODE>mode,
12200 operands[1], operands[2])));
12201 else
12202 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12203 gen_rtx_PLUS (<MODE>mode, operands[1],
12204 negate_rtx (<MODE>mode,
12205 operands[2]))));
12206 }
12207 else
12208 operands[3] = operands[1];
12209 })
12211 (define_insn "*ne0_<mode>"
12212 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12213 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12214 (const_int 0)))
12215 (clobber (match_scratch:P 2 "=&r"))]
12216 "!(TARGET_32BIT && TARGET_ISEL)"
12217 "addic %2,%1,-1\;subfe %0,%2,%1"
12218 [(set_attr "type" "two")
12219 (set_attr "length" "8")])
12221 (define_insn "*plus_ne0_<mode>"
12222 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12223 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12224 (const_int 0))
12225 (match_operand:P 2 "gpc_reg_operand" "r")))
12226 (clobber (match_scratch:P 3 "=&r"))]
12227 ""
12228 "addic %3,%1,-1\;addze %0,%2"
12229 [(set_attr "type" "two")
12230 (set_attr "length" "8")])
12232 (define_insn "*compare_plus_ne0_<mode>"
12233 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12234 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12235 (const_int 0))
12236 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12237 (const_int 0)))
12238 (clobber (match_scratch:P 3 "=&r,&r"))
12239 (clobber (match_scratch:P 4 "=X,&r"))]
12240 ""
12241 "@
12242 addic %3,%1,-1\;addze. %3,%2
12243 #"
12244 [(set_attr "type" "compare")
12245 (set_attr "length" "8,12")])
12247 (define_split
12248 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12249 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12250 (const_int 0))
12251 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12252 (clobber (match_scratch:P 3 ""))
12253 (clobber (match_scratch:P 4 ""))]
12254 "reload_completed"
12255 [(parallel [(set (match_dup 3)
12256 (plus:P (ne:P (match_dup 1)
12257 (const_int 0))
12258 (match_dup 2)))
12259 (clobber (match_dup 4))])
12260 (set (match_dup 0)
12261 (compare:CC (match_dup 3)
12262 (const_int 0)))]
12263 "")
12265 ; For combine.
12266 (define_insn "*compare_plus_ne0_<mode>_1"
12267 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12268 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12269 (const_int 0))
12270 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12271 (clobber (match_scratch:P 3 "=&r,&r"))
12272 (clobber (match_scratch:P 4 "=X,&r"))]
12273 ""
12274 "@
12275 addic %3,%1,-1\;addze. %3,%2
12276 #"
12277 [(set_attr "type" "compare")
12278 (set_attr "length" "8,12")])
12280 (define_split
12281 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12282 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12283 (const_int 0))
12284 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12285 (clobber (match_scratch:P 3 ""))
12286 (clobber (match_scratch:P 4 ""))]
12287 "reload_completed"
12288 [(parallel [(set (match_dup 3)
12289 (plus:P (ne:P (match_dup 1)
12290 (const_int 0))
12291 (match_dup 2)))
12292 (clobber (match_dup 4))])
12293 (set (match_dup 0)
12294 (compare:CC (match_dup 3)
12295 (const_int 0)))]
12296 "")
12298 (define_insn "*plus_ne0_<mode>_compare"
12299 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12300 (compare:CC
12301 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12302 (const_int 0))
12303 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12304 (const_int 0)))
12305 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12306 (plus:P (ne:P (match_dup 1)
12307 (const_int 0))
12308 (match_dup 2)))
12309 (clobber (match_scratch:P 3 "=&r,&r"))]
12310 ""
12311 "@
12312 addic %3,%1,-1\;addze. %0,%2
12313 #"
12314 [(set_attr "type" "compare")
12315 (set_attr "length" "8,12")])
12317 (define_split
12318 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12319 (compare:CC
12320 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12321 (const_int 0))
12322 (match_operand:P 2 "gpc_reg_operand" ""))
12323 (const_int 0)))
12324 (set (match_operand:P 0 "gpc_reg_operand" "")
12325 (plus:P (ne:P (match_dup 1)
12326 (const_int 0))
12327 (match_dup 2)))
12328 (clobber (match_scratch:P 3 ""))]
12329 "reload_completed"
12330 [(parallel [(set (match_dup 0)
12331 (plus:P (ne:P (match_dup 1)
12332 (const_int 0))
12333 (match_dup 2)))
12334 (clobber (match_dup 3))])
12335 (set (match_dup 4)
12336 (compare:CC (match_dup 0)
12337 (const_int 0)))]
12338 "")
12340 (define_insn "*leu<mode>"
12341 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12342 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12343 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12344 ""
12345 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12346 [(set_attr "type" "three")
12347 (set_attr "length" "12")])
12349 (define_insn "*leu<mode>_compare"
12350 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12351 (compare:CC
12352 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12353 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12354 (const_int 0)))
12355 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12356 (leu:P (match_dup 1) (match_dup 2)))]
12357 ""
12358 "@
12359 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12360 #"
12361 [(set_attr "type" "compare")
12362 (set_attr "length" "12,16")])
12364 (define_split
12365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12366 (compare:CC
12367 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12368 (match_operand:P 2 "reg_or_short_operand" ""))
12369 (const_int 0)))
12370 (set (match_operand:P 0 "gpc_reg_operand" "")
12371 (leu:P (match_dup 1) (match_dup 2)))]
12372 "reload_completed"
12373 [(set (match_dup 0)
12374 (leu:P (match_dup 1) (match_dup 2)))
12375 (set (match_dup 3)
12376 (compare:CC (match_dup 0)
12377 (const_int 0)))]
12378 "")
12380 (define_insn "*plus_leu<mode>"
12381 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12382 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12383 (match_operand:P 2 "reg_or_short_operand" "rI"))
12384 (match_operand:P 3 "gpc_reg_operand" "r")))]
12385 ""
12386 "subf%I2c %0,%1,%2\;addze %0,%3"
12387 [(set_attr "type" "two")
12388 (set_attr "length" "8")])
12390 (define_insn ""
12391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12392 (compare:CC
12393 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12394 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12395 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12396 (const_int 0)))
12397 (clobber (match_scratch:SI 4 "=&r,&r"))]
12398 "TARGET_32BIT"
12399 "@
12400 subf%I2c %4,%1,%2\;addze. %4,%3
12401 #"
12402 [(set_attr "type" "compare")
12403 (set_attr "length" "8,12")])
12405 (define_split
12406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12407 (compare:CC
12408 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12409 (match_operand:SI 2 "reg_or_short_operand" ""))
12410 (match_operand:SI 3 "gpc_reg_operand" ""))
12411 (const_int 0)))
12412 (clobber (match_scratch:SI 4 ""))]
12413 "TARGET_32BIT && reload_completed"
12414 [(set (match_dup 4)
12415 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12416 (match_dup 3)))
12417 (set (match_dup 0)
12418 (compare:CC (match_dup 4)
12419 (const_int 0)))]
12420 "")
12422 (define_insn ""
12423 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12424 (compare:CC
12425 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12426 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12427 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12428 (const_int 0)))
12429 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12430 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12431 "TARGET_32BIT"
12432 "@
12433 subf%I2c %0,%1,%2\;addze. %0,%3
12434 #"
12435 [(set_attr "type" "compare")
12436 (set_attr "length" "8,12")])
12438 (define_split
12439 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12440 (compare:CC
12441 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12442 (match_operand:SI 2 "reg_or_short_operand" ""))
12443 (match_operand:SI 3 "gpc_reg_operand" ""))
12444 (const_int 0)))
12445 (set (match_operand:SI 0 "gpc_reg_operand" "")
12446 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12447 "TARGET_32BIT && reload_completed"
12448 [(set (match_dup 0)
12449 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12450 (set (match_dup 4)
12451 (compare:CC (match_dup 0)
12452 (const_int 0)))]
12453 "")
12455 (define_insn "*neg_leu<mode>"
12456 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12457 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12458 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12459 ""
12460 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12461 [(set_attr "type" "three")
12462 (set_attr "length" "12")])
12464 (define_insn "*and_neg_leu<mode>"
12465 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12466 (and:P (neg:P
12467 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12468 (match_operand:P 2 "reg_or_short_operand" "rI")))
12469 (match_operand:P 3 "gpc_reg_operand" "r")))]
12470 ""
12471 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12472 [(set_attr "type" "three")
12473 (set_attr "length" "12")])
12475 (define_insn ""
12476 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12477 (compare:CC
12478 (and:SI (neg:SI
12479 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12480 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12481 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12482 (const_int 0)))
12483 (clobber (match_scratch:SI 4 "=&r,&r"))]
12484 "TARGET_32BIT"
12485 "@
12486 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12487 #"
12488 [(set_attr "type" "compare")
12489 (set_attr "length" "12,16")])
12491 (define_split
12492 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12493 (compare:CC
12494 (and:SI (neg:SI
12495 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12496 (match_operand:SI 2 "reg_or_short_operand" "")))
12497 (match_operand:SI 3 "gpc_reg_operand" ""))
12498 (const_int 0)))
12499 (clobber (match_scratch:SI 4 ""))]
12500 "TARGET_32BIT && reload_completed"
12501 [(set (match_dup 4)
12502 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12503 (match_dup 3)))
12504 (set (match_dup 0)
12505 (compare:CC (match_dup 4)
12506 (const_int 0)))]
12507 "")
12509 (define_insn ""
12510 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12511 (compare:CC
12512 (and:SI (neg:SI
12513 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12514 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12515 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12516 (const_int 0)))
12517 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12518 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12519 "TARGET_32BIT"
12520 "@
12521 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12522 #"
12523 [(set_attr "type" "compare")
12524 (set_attr "length" "12,16")])
12526 (define_split
12527 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12528 (compare:CC
12529 (and:SI (neg:SI
12530 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12531 (match_operand:SI 2 "reg_or_short_operand" "")))
12532 (match_operand:SI 3 "gpc_reg_operand" ""))
12533 (const_int 0)))
12534 (set (match_operand:SI 0 "gpc_reg_operand" "")
12535 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12536 "TARGET_32BIT && reload_completed"
12537 [(set (match_dup 0)
12538 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12539 (match_dup 3)))
12540 (set (match_dup 4)
12541 (compare:CC (match_dup 0)
12542 (const_int 0)))]
12543 "")
12545 (define_insn_and_split "*ltu<mode>"
12546 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12547 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12548 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12549 ""
12550 "#"
12551 ""
12552 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12553 (set (match_dup 0) (neg:P (match_dup 0)))]
12554 "")
12556 (define_insn_and_split "*ltu<mode>_compare"
12557 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12558 (compare:CC
12559 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12560 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12561 (const_int 0)))
12562 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12563 (ltu:P (match_dup 1) (match_dup 2)))]
12564 ""
12565 "#"
12566 ""
12567 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12568 (parallel [(set (match_dup 3)
12569 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12570 (set (match_dup 0) (neg:P (match_dup 0)))])]
12571 "")
12573 (define_insn_and_split "*plus_ltu<mode>"
12574 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12575 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12576 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12577 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12578 ""
12579 "#"
12580 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12581 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12582 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12583 "")
12585 (define_insn_and_split "*plus_ltu<mode>_1"
12586 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12587 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12588 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12589 (match_operand:P 3 "short_cint_operand" "I,I")))]
12590 ""
12591 "#"
12592 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12593 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12594 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
12595 (clobber (reg:P CA_REGNO))])]
12596 "")
12598 (define_insn_and_split "*plus_ltu<mode>_compare"
12599 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12600 (compare:CC
12601 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12602 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12603 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12604 (const_int 0)))
12605 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12606 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12607 ""
12608 "#"
12609 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12610 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12611 (parallel [(set (match_dup 4)
12612 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12613 (const_int 0)))
12614 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12615 "")
12617 (define_insn "*neg_ltu<mode>"
12618 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12619 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12620 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12621 ""
12622 "@
12623 subfc %0,%2,%1\;subfe %0,%0,%0
12624 addic %0,%1,%n2\;subfe %0,%0,%0"
12625 [(set_attr "type" "two")
12626 (set_attr "length" "8")])
12628 (define_insn "*geu<mode>"
12629 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12630 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12631 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12632 ""
12633 "@
12634 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12635 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12636 [(set_attr "type" "three")
12637 (set_attr "length" "12")])
12639 (define_insn "*geu<mode>_compare"
12640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12641 (compare:CC
12642 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12643 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12644 (const_int 0)))
12645 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12646 (geu:P (match_dup 1) (match_dup 2)))]
12647 ""
12648 "@
12649 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12650 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12651 #
12652 #"
12653 [(set_attr "type" "compare")
12654 (set_attr "length" "12,12,16,16")])
12656 (define_split
12657 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12658 (compare:CC
12659 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12660 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12661 (const_int 0)))
12662 (set (match_operand:P 0 "gpc_reg_operand" "")
12663 (geu:P (match_dup 1) (match_dup 2)))]
12664 "reload_completed"
12665 [(set (match_dup 0)
12666 (geu:P (match_dup 1) (match_dup 2)))
12667 (set (match_dup 3)
12668 (compare:CC (match_dup 0)
12669 (const_int 0)))]
12670 "")
12672 (define_insn "*plus_geu<mode>"
12673 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12674 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12675 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12676 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12677 ""
12678 "@
12679 subfc %0,%2,%1\;addze %0,%3
12680 addic %0,%1,%n2\;addze %0,%3"
12681 [(set_attr "type" "two")
12682 (set_attr "length" "8")])
12684 (define_insn ""
12685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12686 (compare:CC
12687 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12688 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12689 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12690 (const_int 0)))
12691 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12692 "TARGET_32BIT"
12693 "@
12694 subfc %4,%2,%1\;addze. %4,%3
12695 addic %4,%1,%n2\;addze. %4,%3
12696 #
12697 #"
12698 [(set_attr "type" "compare")
12699 (set_attr "length" "8,8,12,12")])
12701 (define_split
12702 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12703 (compare:CC
12704 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12705 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12706 (match_operand:SI 3 "gpc_reg_operand" ""))
12707 (const_int 0)))
12708 (clobber (match_scratch:SI 4 ""))]
12709 "TARGET_32BIT && reload_completed"
12710 [(set (match_dup 4)
12711 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12712 (match_dup 3)))
12713 (set (match_dup 0)
12714 (compare:CC (match_dup 4)
12715 (const_int 0)))]
12716 "")
12718 (define_insn ""
12719 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12720 (compare:CC
12721 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12722 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12723 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12724 (const_int 0)))
12725 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12726 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12727 "TARGET_32BIT"
12728 "@
12729 subfc %0,%2,%1\;addze. %0,%3
12730 addic %0,%1,%n2\;addze. %0,%3
12731 #
12732 #"
12733 [(set_attr "type" "compare")
12734 (set_attr "length" "8,8,12,12")])
12736 (define_split
12737 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12738 (compare:CC
12739 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12740 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12741 (match_operand:SI 3 "gpc_reg_operand" ""))
12742 (const_int 0)))
12743 (set (match_operand:SI 0 "gpc_reg_operand" "")
12744 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12745 "TARGET_32BIT && reload_completed"
12746 [(set (match_dup 0)
12747 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12748 (set (match_dup 4)
12749 (compare:CC (match_dup 0)
12750 (const_int 0)))]
12751 "")
12753 (define_insn "*neg_geu<mode>"
12754 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12755 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12756 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12757 ""
12758 "@
12759 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12760 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12761 [(set_attr "type" "three")
12762 (set_attr "length" "12")])
12764 (define_insn "*and_neg_geu<mode>"
12765 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12766 (and:P (neg:P
12767 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12768 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12769 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12770 ""
12771 "@
12772 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12773 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12774 [(set_attr "type" "three")
12775 (set_attr "length" "12")])
12777 (define_insn ""
12778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12779 (compare:CC
12780 (and:SI (neg:SI
12781 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12782 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12783 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12784 (const_int 0)))
12785 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12786 "TARGET_32BIT"
12787 "@
12788 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12789 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12790 #
12791 #"
12792 [(set_attr "type" "compare")
12793 (set_attr "length" "12,12,16,16")])
12795 (define_split
12796 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12797 (compare:CC
12798 (and:SI (neg:SI
12799 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12800 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12801 (match_operand:SI 3 "gpc_reg_operand" ""))
12802 (const_int 0)))
12803 (clobber (match_scratch:SI 4 ""))]
12804 "TARGET_32BIT && reload_completed"
12805 [(set (match_dup 4)
12806 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12807 (match_dup 3)))
12808 (set (match_dup 0)
12809 (compare:CC (match_dup 4)
12810 (const_int 0)))]
12811 "")
12813 (define_insn ""
12814 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12815 (compare:CC
12816 (and:SI (neg:SI
12817 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12818 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12819 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12820 (const_int 0)))
12821 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12822 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12823 "TARGET_32BIT"
12824 "@
12825 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12826 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12827 #
12828 #"
12829 [(set_attr "type" "compare")
12830 (set_attr "length" "12,12,16,16")])
12832 (define_split
12833 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12834 (compare:CC
12835 (and:SI (neg:SI
12836 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12837 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12838 (match_operand:SI 3 "gpc_reg_operand" ""))
12839 (const_int 0)))
12840 (set (match_operand:SI 0 "gpc_reg_operand" "")
12841 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12842 "TARGET_32BIT && reload_completed"
12843 [(set (match_dup 0)
12844 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12845 (set (match_dup 4)
12846 (compare:CC (match_dup 0)
12847 (const_int 0)))]
12848 "")
12850 (define_insn "*plus_gt0<mode>"
12851 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12852 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12853 (const_int 0))
12854 (match_operand:P 2 "gpc_reg_operand" "r")))]
12855 ""
12856 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12857 [(set_attr "type" "three")
12858 (set_attr "length" "12")])
12860 (define_insn ""
12861 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12862 (compare:CC
12863 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12864 (const_int 0))
12865 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12866 (const_int 0)))
12867 (clobber (match_scratch:SI 3 "=&r,&r"))]
12868 "TARGET_32BIT"
12869 "@
12870 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12871 #"
12872 [(set_attr "type" "compare")
12873 (set_attr "length" "12,16")])
12875 (define_split
12876 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12877 (compare:CC
12878 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12879 (const_int 0))
12880 (match_operand:SI 2 "gpc_reg_operand" ""))
12881 (const_int 0)))
12882 (clobber (match_scratch:SI 3 ""))]
12883 "TARGET_32BIT && reload_completed"
12884 [(set (match_dup 3)
12885 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12886 (match_dup 2)))
12887 (set (match_dup 0)
12888 (compare:CC (match_dup 3)
12889 (const_int 0)))]
12890 "")
12892 (define_insn ""
12893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12894 (compare:CC
12895 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12896 (const_int 0))
12897 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12898 (const_int 0)))
12899 (clobber (match_scratch:DI 3 "=&r,&r"))]
12900 "TARGET_64BIT"
12901 "@
12902 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12903 #"
12904 [(set_attr "type" "compare")
12905 (set_attr "length" "12,16")])
12907 (define_split
12908 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12909 (compare:CC
12910 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12911 (const_int 0))
12912 (match_operand:DI 2 "gpc_reg_operand" ""))
12913 (const_int 0)))
12914 (clobber (match_scratch:DI 3 ""))]
12915 "TARGET_64BIT && reload_completed"
12916 [(set (match_dup 3)
12917 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12918 (match_dup 2)))
12919 (set (match_dup 0)
12920 (compare:CC (match_dup 3)
12921 (const_int 0)))]
12922 "")
12924 (define_insn ""
12925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12926 (compare:CC
12927 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12928 (const_int 0))
12929 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12930 (const_int 0)))
12931 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12932 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12933 "TARGET_32BIT"
12934 "@
12935 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12936 #"
12937 [(set_attr "type" "compare")
12938 (set_attr "length" "12,16")])
12940 (define_split
12941 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12942 (compare:CC
12943 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12944 (const_int 0))
12945 (match_operand:SI 2 "gpc_reg_operand" ""))
12946 (const_int 0)))
12947 (set (match_operand:SI 0 "gpc_reg_operand" "")
12948 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12949 "TARGET_32BIT && reload_completed"
12950 [(set (match_dup 0)
12951 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12952 (set (match_dup 3)
12953 (compare:CC (match_dup 0)
12954 (const_int 0)))]
12955 "")
12957 (define_insn ""
12958 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12959 (compare:CC
12960 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12961 (const_int 0))
12962 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12963 (const_int 0)))
12964 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12965 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12966 "TARGET_64BIT"
12967 "@
12968 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12969 #"
12970 [(set_attr "type" "compare")
12971 (set_attr "length" "12,16")])
12973 (define_split
12974 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12975 (compare:CC
12976 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12977 (const_int 0))
12978 (match_operand:DI 2 "gpc_reg_operand" ""))
12979 (const_int 0)))
12980 (set (match_operand:DI 0 "gpc_reg_operand" "")
12981 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12982 "TARGET_64BIT && reload_completed"
12983 [(set (match_dup 0)
12984 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12985 (set (match_dup 3)
12986 (compare:CC (match_dup 0)
12987 (const_int 0)))]
12988 "")
12990 (define_insn_and_split "*gtu<mode>"
12991 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12992 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12993 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12994 ""
12995 "#"
12996 ""
12997 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12998 (set (match_dup 0) (neg:P (match_dup 0)))]
12999 "")
13001 (define_insn_and_split "*gtu<mode>_compare"
13002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13003 (compare:CC
13004 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13005 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13006 (const_int 0)))
13007 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13008 (gtu:P (match_dup 1) (match_dup 2)))]
13009 ""
13010 "#"
13011 ""
13012 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13013 (parallel [(set (match_dup 3)
13014 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13015 (set (match_dup 0) (neg:P (match_dup 0)))])]
13016 "")
13018 (define_insn_and_split "*plus_gtu<mode>"
13019 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13020 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13021 (match_operand:P 2 "reg_or_short_operand" "rI"))
13022 (match_operand:P 3 "gpc_reg_operand" "r")))]
13023 ""
13024 "#"
13025 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13026 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13027 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13028 "")
13030 (define_insn_and_split "*plus_gtu<mode>_1"
13031 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13032 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13033 (match_operand:P 2 "reg_or_short_operand" "rI"))
13034 (match_operand:P 3 "short_cint_operand" "I")))]
13035 ""
13036 "#"
13037 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13038 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13039 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
13040 (clobber (reg:P CA_REGNO))])]
13041 "")
13043 (define_insn_and_split "*plus_gtu<mode>_compare"
13044 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13045 (compare:CC
13046 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13047 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13048 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13049 (const_int 0)))
13050 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13051 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13052 ""
13053 "#"
13054 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13055 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13056 (parallel [(set (match_dup 4)
13057 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13058 (const_int 0)))
13059 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13060 "")
13062 (define_insn "*neg_gtu<mode>"
13063 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13064 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13065 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13066 ""
13067 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13068 [(set_attr "type" "two")
13069 (set_attr "length" "8")])
13071 \f
13072 ;; Define both directions of branch and return. If we need a reload
13073 ;; register, we'd rather use CR0 since it is much easier to copy a
13074 ;; register CC value to there.
13076 (define_insn ""
13077 [(set (pc)
13078 (if_then_else (match_operator 1 "branch_comparison_operator"
13079 [(match_operand 2
13080 "cc_reg_operand" "y")
13081 (const_int 0)])
13082 (label_ref (match_operand 0 "" ""))
13083 (pc)))]
13084 ""
13085 "*
13086 {
13087 return output_cbranch (operands[1], \"%l0\", 0, insn);
13088 }"
13089 [(set_attr "type" "branch")])
13091 (define_insn ""
13092 [(set (pc)
13093 (if_then_else (match_operator 0 "branch_comparison_operator"
13094 [(match_operand 1
13095 "cc_reg_operand" "y")
13096 (const_int 0)])
13097 (any_return)
13098 (pc)))]
13099 "<return_pred>"
13100 "*
13101 {
13102 return output_cbranch (operands[0], NULL, 0, insn);
13103 }"
13104 [(set_attr "type" "jmpreg")
13105 (set_attr "length" "4")])
13107 (define_insn ""
13108 [(set (pc)
13109 (if_then_else (match_operator 1 "branch_comparison_operator"
13110 [(match_operand 2
13111 "cc_reg_operand" "y")
13112 (const_int 0)])
13113 (pc)
13114 (label_ref (match_operand 0 "" ""))))]
13115 ""
13116 "*
13117 {
13118 return output_cbranch (operands[1], \"%l0\", 1, insn);
13119 }"
13120 [(set_attr "type" "branch")])
13122 (define_insn ""
13123 [(set (pc)
13124 (if_then_else (match_operator 0 "branch_comparison_operator"
13125 [(match_operand 1
13126 "cc_reg_operand" "y")
13127 (const_int 0)])
13128 (pc)
13129 (any_return)))]
13130 "<return_pred>"
13131 "*
13132 {
13133 return output_cbranch (operands[0], NULL, 1, insn);
13134 }"
13135 [(set_attr "type" "jmpreg")
13136 (set_attr "length" "4")])
13138 ;; Logic on condition register values.
13140 ; This pattern matches things like
13141 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13142 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13143 ; (const_int 1)))
13144 ; which are generated by the branch logic.
13145 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13147 (define_insn "*cceq_ior_compare"
13148 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13149 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13150 [(match_operator:SI 2
13151 "branch_positive_comparison_operator"
13152 [(match_operand 3
13153 "cc_reg_operand" "y,y")
13154 (const_int 0)])
13155 (match_operator:SI 4
13156 "branch_positive_comparison_operator"
13157 [(match_operand 5
13158 "cc_reg_operand" "0,y")
13159 (const_int 0)])])
13160 (const_int 1)))]
13161 ""
13162 "cr%q1 %E0,%j2,%j4"
13163 [(set_attr "type" "cr_logical,delayed_cr")])
13165 ; Why is the constant -1 here, but 1 in the previous pattern?
13166 ; Because ~1 has all but the low bit set.
13167 (define_insn ""
13168 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13169 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13170 [(not:SI (match_operator:SI 2
13171 "branch_positive_comparison_operator"
13172 [(match_operand 3
13173 "cc_reg_operand" "y,y")
13174 (const_int 0)]))
13175 (match_operator:SI 4
13176 "branch_positive_comparison_operator"
13177 [(match_operand 5
13178 "cc_reg_operand" "0,y")
13179 (const_int 0)])])
13180 (const_int -1)))]
13181 ""
13182 "cr%q1 %E0,%j2,%j4"
13183 [(set_attr "type" "cr_logical,delayed_cr")])
13185 (define_insn "*cceq_rev_compare"
13186 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13187 (compare:CCEQ (match_operator:SI 1
13188 "branch_positive_comparison_operator"
13189 [(match_operand 2
13190 "cc_reg_operand" "0,y")
13191 (const_int 0)])
13192 (const_int 0)))]
13193 ""
13194 "crnot %E0,%j1"
13195 [(set_attr "type" "cr_logical,delayed_cr")])
13197 ;; If we are comparing the result of two comparisons, this can be done
13198 ;; using creqv or crxor.
13200 (define_insn_and_split ""
13201 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13202 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13203 [(match_operand 2 "cc_reg_operand" "y")
13204 (const_int 0)])
13205 (match_operator 3 "branch_comparison_operator"
13206 [(match_operand 4 "cc_reg_operand" "y")
13207 (const_int 0)])))]
13208 ""
13209 "#"
13210 ""
13211 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13212 (match_dup 5)))]
13213 "
13214 {
13215 int positive_1, positive_2;
13217 positive_1 = branch_positive_comparison_operator (operands[1],
13218 GET_MODE (operands[1]));
13219 positive_2 = branch_positive_comparison_operator (operands[3],
13220 GET_MODE (operands[3]));
13222 if (! positive_1)
13223 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13224 GET_CODE (operands[1])),
13225 SImode,
13226 operands[2], const0_rtx);
13227 else if (GET_MODE (operands[1]) != SImode)
13228 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13229 operands[2], const0_rtx);
13231 if (! positive_2)
13232 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13233 GET_CODE (operands[3])),
13234 SImode,
13235 operands[4], const0_rtx);
13236 else if (GET_MODE (operands[3]) != SImode)
13237 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13238 operands[4], const0_rtx);
13240 if (positive_1 == positive_2)
13241 {
13242 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13243 operands[5] = constm1_rtx;
13244 }
13245 else
13246 {
13247 operands[5] = const1_rtx;
13248 }
13249 }")
13251 ;; Unconditional branch and return.
13253 (define_insn "jump"
13254 [(set (pc)
13255 (label_ref (match_operand 0 "" "")))]
13256 ""
13257 "b %l0"
13258 [(set_attr "type" "branch")])
13260 (define_insn "<return_str>return"
13261 [(any_return)]
13262 "<return_pred>"
13263 "blr"
13264 [(set_attr "type" "jmpreg")])
13266 (define_expand "indirect_jump"
13267 [(set (pc) (match_operand 0 "register_operand" ""))])
13269 (define_insn "*indirect_jump<mode>"
13270 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13271 ""
13272 "@
13273 bctr
13274 blr"
13275 [(set_attr "type" "jmpreg")])
13277 ;; Table jump for switch statements:
13278 (define_expand "tablejump"
13279 [(use (match_operand 0 "" ""))
13280 (use (label_ref (match_operand 1 "" "")))]
13281 ""
13282 "
13283 {
13284 if (TARGET_32BIT)
13285 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13286 else
13287 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13288 DONE;
13289 }")
13291 (define_expand "tablejumpsi"
13292 [(set (match_dup 3)
13293 (plus:SI (match_operand:SI 0 "" "")
13294 (match_dup 2)))
13295 (parallel [(set (pc) (match_dup 3))
13296 (use (label_ref (match_operand 1 "" "")))])]
13297 "TARGET_32BIT"
13298 "
13299 { operands[0] = force_reg (SImode, operands[0]);
13300 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13301 operands[3] = gen_reg_rtx (SImode);
13302 }")
13304 (define_expand "tablejumpdi"
13305 [(set (match_dup 4)
13306 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13307 (set (match_dup 3)
13308 (plus:DI (match_dup 4)
13309 (match_dup 2)))
13310 (parallel [(set (pc) (match_dup 3))
13311 (use (label_ref (match_operand 1 "" "")))])]
13312 "TARGET_64BIT"
13313 "
13314 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13315 operands[3] = gen_reg_rtx (DImode);
13316 operands[4] = gen_reg_rtx (DImode);
13317 }")
13319 (define_insn "*tablejump<mode>_internal1"
13320 [(set (pc)
13321 (match_operand:P 0 "register_operand" "c,*l"))
13322 (use (label_ref (match_operand 1 "" "")))]
13323 ""
13324 "@
13325 bctr
13326 blr"
13327 [(set_attr "type" "jmpreg")])
13329 (define_insn "nop"
13330 [(const_int 0)]
13331 ""
13332 "nop")
13334 (define_insn "group_ending_nop"
13335 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13336 ""
13337 "*
13338 {
13339 if (rs6000_cpu_attr == CPU_POWER6)
13340 return \"ori 1,1,0\";
13341 return \"ori 2,2,0\";
13342 }")
13343 \f
13344 ;; Define the subtract-one-and-jump insns, starting with the template
13345 ;; so loop.c knows what to generate.
13347 (define_expand "doloop_end"
13348 [(use (match_operand 0 "" "")) ; loop pseudo
13349 (use (match_operand 1 "" ""))] ; label
13350 ""
13351 "
13352 {
13353 if (TARGET_64BIT)
13354 {
13355 if (GET_MODE (operands[0]) != DImode)
13356 FAIL;
13357 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13358 }
13359 else
13360 {
13361 if (GET_MODE (operands[0]) != SImode)
13362 FAIL;
13363 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13364 }
13365 DONE;
13366 }")
13368 (define_expand "ctr<mode>"
13369 [(parallel [(set (pc)
13370 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13371 (const_int 1))
13372 (label_ref (match_operand 1 "" ""))
13373 (pc)))
13374 (set (match_dup 0)
13375 (plus:P (match_dup 0)
13376 (const_int -1)))
13377 (clobber (match_scratch:CC 2 ""))
13378 (clobber (match_scratch:P 3 ""))])]
13379 ""
13380 "")
13382 ;; We need to be able to do this for any operand, including MEM, or we
13383 ;; will cause reload to blow up since we don't allow output reloads on
13384 ;; JUMP_INSNs.
13385 ;; For the length attribute to be calculated correctly, the
13386 ;; label MUST be operand 0.
13388 (define_insn "*ctr<mode>_internal1"
13389 [(set (pc)
13390 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13391 (const_int 1))
13392 (label_ref (match_operand 0 "" ""))
13393 (pc)))
13394 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13395 (plus:P (match_dup 1)
13396 (const_int -1)))
13397 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13398 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13399 ""
13400 "*
13401 {
13402 if (which_alternative != 0)
13403 return \"#\";
13404 else if (get_attr_length (insn) == 4)
13405 return \"bdnz %l0\";
13406 else
13407 return \"bdz $+8\;b %l0\";
13408 }"
13409 [(set_attr "type" "branch")
13410 (set_attr "length" "*,12,16,16")])
13412 (define_insn "*ctr<mode>_internal2"
13413 [(set (pc)
13414 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13415 (const_int 1))
13416 (pc)
13417 (label_ref (match_operand 0 "" ""))))
13418 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13419 (plus:P (match_dup 1)
13420 (const_int -1)))
13421 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13422 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13423 ""
13424 "*
13425 {
13426 if (which_alternative != 0)
13427 return \"#\";
13428 else if (get_attr_length (insn) == 4)
13429 return \"bdz %l0\";
13430 else
13431 return \"bdnz $+8\;b %l0\";
13432 }"
13433 [(set_attr "type" "branch")
13434 (set_attr "length" "*,12,16,16")])
13436 ;; Similar but use EQ
13438 (define_insn "*ctr<mode>_internal5"
13439 [(set (pc)
13440 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13441 (const_int 1))
13442 (label_ref (match_operand 0 "" ""))
13443 (pc)))
13444 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13445 (plus:P (match_dup 1)
13446 (const_int -1)))
13447 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13448 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13449 ""
13450 "*
13451 {
13452 if (which_alternative != 0)
13453 return \"#\";
13454 else if (get_attr_length (insn) == 4)
13455 return \"bdz %l0\";
13456 else
13457 return \"bdnz $+8\;b %l0\";
13458 }"
13459 [(set_attr "type" "branch")
13460 (set_attr "length" "*,12,16,16")])
13462 (define_insn "*ctr<mode>_internal6"
13463 [(set (pc)
13464 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13465 (const_int 1))
13466 (pc)
13467 (label_ref (match_operand 0 "" ""))))
13468 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13469 (plus:P (match_dup 1)
13470 (const_int -1)))
13471 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13472 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13473 ""
13474 "*
13475 {
13476 if (which_alternative != 0)
13477 return \"#\";
13478 else if (get_attr_length (insn) == 4)
13479 return \"bdnz %l0\";
13480 else
13481 return \"bdz $+8\;b %l0\";
13482 }"
13483 [(set_attr "type" "branch")
13484 (set_attr "length" "*,12,16,16")])
13486 ;; Now the splitters if we could not allocate the CTR register
13488 (define_split
13489 [(set (pc)
13490 (if_then_else (match_operator 2 "comparison_operator"
13491 [(match_operand:P 1 "gpc_reg_operand" "")
13492 (const_int 1)])
13493 (match_operand 5 "" "")
13494 (match_operand 6 "" "")))
13495 (set (match_operand:P 0 "gpc_reg_operand" "")
13496 (plus:P (match_dup 1) (const_int -1)))
13497 (clobber (match_scratch:CC 3 ""))
13498 (clobber (match_scratch:P 4 ""))]
13499 "reload_completed"
13500 [(parallel [(set (match_dup 3)
13501 (compare:CC (plus:P (match_dup 1)
13502 (const_int -1))
13503 (const_int 0)))
13504 (set (match_dup 0)
13505 (plus:P (match_dup 1)
13506 (const_int -1)))])
13507 (set (pc) (if_then_else (match_dup 7)
13508 (match_dup 5)
13509 (match_dup 6)))]
13510 "
13511 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13512 operands[3], const0_rtx); }")
13514 (define_split
13515 [(set (pc)
13516 (if_then_else (match_operator 2 "comparison_operator"
13517 [(match_operand:P 1 "gpc_reg_operand" "")
13518 (const_int 1)])
13519 (match_operand 5 "" "")
13520 (match_operand 6 "" "")))
13521 (set (match_operand:P 0 "nonimmediate_operand" "")
13522 (plus:P (match_dup 1) (const_int -1)))
13523 (clobber (match_scratch:CC 3 ""))
13524 (clobber (match_scratch:P 4 ""))]
13525 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13526 [(parallel [(set (match_dup 3)
13527 (compare:CC (plus:P (match_dup 1)
13528 (const_int -1))
13529 (const_int 0)))
13530 (set (match_dup 4)
13531 (plus:P (match_dup 1)
13532 (const_int -1)))])
13533 (set (match_dup 0)
13534 (match_dup 4))
13535 (set (pc) (if_then_else (match_dup 7)
13536 (match_dup 5)
13537 (match_dup 6)))]
13538 "
13539 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13540 operands[3], const0_rtx); }")
13541 \f
13542 (define_insn "trap"
13543 [(trap_if (const_int 1) (const_int 0))]
13544 ""
13545 "trap"
13546 [(set_attr "type" "trap")])
13548 (define_expand "ctrap<mode>4"
13549 [(trap_if (match_operator 0 "ordered_comparison_operator"
13550 [(match_operand:GPR 1 "register_operand")
13551 (match_operand:GPR 2 "reg_or_short_operand")])
13552 (match_operand 3 "zero_constant" ""))]
13553 ""
13554 "")
13556 (define_insn ""
13557 [(trap_if (match_operator 0 "ordered_comparison_operator"
13558 [(match_operand:GPR 1 "register_operand" "r")
13559 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13560 (const_int 0))]
13561 ""
13562 "t<wd>%V0%I2 %1,%2"
13563 [(set_attr "type" "trap")])
13564 \f
13565 ;; Insns related to generating the function prologue and epilogue.
13567 (define_expand "prologue"
13568 [(use (const_int 0))]
13569 ""
13570 {
13571 rs6000_emit_prologue ();
13572 if (!TARGET_SCHED_PROLOG)
13573 emit_insn (gen_blockage ());
13574 DONE;
13575 })
13577 (define_insn "*movesi_from_cr_one"
13578 [(match_parallel 0 "mfcr_operation"
13579 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13580 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13581 (match_operand 3 "immediate_operand" "n")]
13582 UNSPEC_MOVESI_FROM_CR))])]
13583 "TARGET_MFCRF"
13584 "*
13585 {
13586 int mask = 0;
13587 int i;
13588 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13589 {
13590 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13591 operands[4] = GEN_INT (mask);
13592 output_asm_insn (\"mfcr %1,%4\", operands);
13593 }
13594 return \"\";
13595 }"
13596 [(set_attr "type" "mfcrf")])
13598 (define_insn "movesi_from_cr"
13599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13600 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13601 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13602 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13603 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13604 UNSPEC_MOVESI_FROM_CR))]
13605 ""
13606 "mfcr %0"
13607 [(set_attr "type" "mfcr")])
13609 (define_insn "*crsave"
13610 [(match_parallel 0 "crsave_operation"
13611 [(set (match_operand:SI 1 "memory_operand" "=m")
13612 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13613 ""
13614 "stw %2,%1"
13615 [(set_attr "type" "store")])
13617 (define_insn "*stmw"
13618 [(match_parallel 0 "stmw_operation"
13619 [(set (match_operand:SI 1 "memory_operand" "=m")
13620 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13621 "TARGET_MULTIPLE"
13622 "stmw %2,%1"
13623 [(set_attr "type" "store")
13624 (set_attr "update" "yes")
13625 (set_attr "indexed" "yes")])
13627 ; The following comment applies to:
13628 ; save_gpregs_*
13629 ; save_fpregs_*
13630 ; restore_gpregs*
13631 ; return_and_restore_gpregs*
13632 ; return_and_restore_fpregs*
13633 ; return_and_restore_fpregs_aix*
13634 ;
13635 ; The out-of-line save / restore functions expects one input argument.
13636 ; Since those are not standard call_insn's, we must avoid using
13637 ; MATCH_OPERAND for that argument. That way the register rename
13638 ; optimization will not try to rename this register.
13639 ; Each pattern is repeated for each possible register number used in
13640 ; various ABIs (r11, r1, and for some functions r12)
13642 (define_insn "*save_gpregs_<mode>_r11"
13643 [(match_parallel 0 "any_parallel_operand"
13644 [(clobber (reg:P 65))
13645 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13646 (use (reg:P 11))
13647 (set (match_operand:P 2 "memory_operand" "=m")
13648 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13649 ""
13650 "bl %1"
13651 [(set_attr "type" "branch")
13652 (set_attr "length" "4")])
13654 (define_insn "*save_gpregs_<mode>_r12"
13655 [(match_parallel 0 "any_parallel_operand"
13656 [(clobber (reg:P 65))
13657 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13658 (use (reg:P 12))
13659 (set (match_operand:P 2 "memory_operand" "=m")
13660 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13661 ""
13662 "bl %1"
13663 [(set_attr "type" "branch")
13664 (set_attr "length" "4")])
13666 (define_insn "*save_gpregs_<mode>_r1"
13667 [(match_parallel 0 "any_parallel_operand"
13668 [(clobber (reg:P 65))
13669 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13670 (use (reg:P 1))
13671 (set (match_operand:P 2 "memory_operand" "=m")
13672 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13673 ""
13674 "bl %1"
13675 [(set_attr "type" "branch")
13676 (set_attr "length" "4")])
13678 (define_insn "*save_fpregs_<mode>_r11"
13679 [(match_parallel 0 "any_parallel_operand"
13680 [(clobber (reg:P 65))
13681 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13682 (use (reg:P 11))
13683 (set (match_operand:DF 2 "memory_operand" "=m")
13684 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13685 ""
13686 "bl %1"
13687 [(set_attr "type" "branch")
13688 (set_attr "length" "4")])
13690 (define_insn "*save_fpregs_<mode>_r12"
13691 [(match_parallel 0 "any_parallel_operand"
13692 [(clobber (reg:P 65))
13693 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13694 (use (reg:P 12))
13695 (set (match_operand:DF 2 "memory_operand" "=m")
13696 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13697 ""
13698 "bl %1"
13699 [(set_attr "type" "branch")
13700 (set_attr "length" "4")])
13702 (define_insn "*save_fpregs_<mode>_r1"
13703 [(match_parallel 0 "any_parallel_operand"
13704 [(clobber (reg:P 65))
13705 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13706 (use (reg:P 1))
13707 (set (match_operand:DF 2 "memory_operand" "=m")
13708 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13709 ""
13710 "bl %1"
13711 [(set_attr "type" "branch")
13712 (set_attr "length" "4")])
13714 ; This is to explain that changes to the stack pointer should
13715 ; not be moved over loads from or stores to stack memory.
13716 (define_insn "stack_tie"
13717 [(match_parallel 0 "tie_operand"
13718 [(set (mem:BLK (reg 1)) (const_int 0))])]
13719 ""
13720 ""
13721 [(set_attr "length" "0")])
13723 (define_expand "epilogue"
13724 [(use (const_int 0))]
13725 ""
13726 {
13727 if (!TARGET_SCHED_PROLOG)
13728 emit_insn (gen_blockage ());
13729 rs6000_emit_epilogue (FALSE);
13730 DONE;
13731 })
13733 ; On some processors, doing the mtcrf one CC register at a time is
13734 ; faster (like on the 604e). On others, doing them all at once is
13735 ; faster; for instance, on the 601 and 750.
13737 (define_expand "movsi_to_cr_one"
13738 [(set (match_operand:CC 0 "cc_reg_operand" "")
13739 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13740 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13741 ""
13742 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13744 (define_insn "*movsi_to_cr"
13745 [(match_parallel 0 "mtcrf_operation"
13746 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13747 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13748 (match_operand 3 "immediate_operand" "n")]
13749 UNSPEC_MOVESI_TO_CR))])]
13750 ""
13751 "*
13752 {
13753 int mask = 0;
13754 int i;
13755 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13756 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13757 operands[4] = GEN_INT (mask);
13758 return \"mtcrf %4,%2\";
13759 }"
13760 [(set_attr "type" "mtcr")])
13762 (define_insn "*mtcrfsi"
13763 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13764 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13765 (match_operand 2 "immediate_operand" "n")]
13766 UNSPEC_MOVESI_TO_CR))]
13767 "GET_CODE (operands[0]) == REG
13768 && CR_REGNO_P (REGNO (operands[0]))
13769 && GET_CODE (operands[2]) == CONST_INT
13770 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13771 "mtcrf %R0,%1"
13772 [(set_attr "type" "mtcr")])
13774 ; The load-multiple instructions have similar properties.
13775 ; Note that "load_multiple" is a name known to the machine-independent
13776 ; code that actually corresponds to the PowerPC load-string.
13778 (define_insn "*lmw"
13779 [(match_parallel 0 "lmw_operation"
13780 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13781 (match_operand:SI 2 "memory_operand" "m"))])]
13782 "TARGET_MULTIPLE"
13783 "lmw %1,%2"
13784 [(set_attr "type" "load")
13785 (set_attr "update" "yes")
13786 (set_attr "indexed" "yes")
13787 (set_attr "cell_micro" "always")])
13789 (define_insn "*return_internal_<mode>"
13790 [(simple_return)
13791 (use (match_operand:P 0 "register_operand" "lc"))]
13792 ""
13793 "b%T0"
13794 [(set_attr "type" "jmpreg")])
13796 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13797 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13799 ; The following comment applies to:
13800 ; save_gpregs_*
13801 ; save_fpregs_*
13802 ; restore_gpregs*
13803 ; return_and_restore_gpregs*
13804 ; return_and_restore_fpregs*
13805 ; return_and_restore_fpregs_aix*
13806 ;
13807 ; The out-of-line save / restore functions expects one input argument.
13808 ; Since those are not standard call_insn's, we must avoid using
13809 ; MATCH_OPERAND for that argument. That way the register rename
13810 ; optimization will not try to rename this register.
13811 ; Each pattern is repeated for each possible register number used in
13812 ; various ABIs (r11, r1, and for some functions r12)
13814 (define_insn "*restore_gpregs_<mode>_r11"
13815 [(match_parallel 0 "any_parallel_operand"
13816 [(clobber (match_operand:P 1 "register_operand" "=l"))
13817 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13818 (use (reg:P 11))
13819 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13820 (match_operand:P 4 "memory_operand" "m"))])]
13821 ""
13822 "bl %2"
13823 [(set_attr "type" "branch")
13824 (set_attr "length" "4")])
13826 (define_insn "*restore_gpregs_<mode>_r12"
13827 [(match_parallel 0 "any_parallel_operand"
13828 [(clobber (match_operand:P 1 "register_operand" "=l"))
13829 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13830 (use (reg:P 12))
13831 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13832 (match_operand:P 4 "memory_operand" "m"))])]
13833 ""
13834 "bl %2"
13835 [(set_attr "type" "branch")
13836 (set_attr "length" "4")])
13838 (define_insn "*restore_gpregs_<mode>_r1"
13839 [(match_parallel 0 "any_parallel_operand"
13840 [(clobber (match_operand:P 1 "register_operand" "=l"))
13841 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13842 (use (reg:P 1))
13843 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13844 (match_operand:P 4 "memory_operand" "m"))])]
13845 ""
13846 "bl %2"
13847 [(set_attr "type" "branch")
13848 (set_attr "length" "4")])
13850 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13851 [(match_parallel 0 "any_parallel_operand"
13852 [(return)
13853 (clobber (match_operand:P 1 "register_operand" "=l"))
13854 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13855 (use (reg:P 11))
13856 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13857 (match_operand:P 4 "memory_operand" "m"))])]
13858 ""
13859 "b %2"
13860 [(set_attr "type" "branch")
13861 (set_attr "length" "4")])
13863 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13864 [(match_parallel 0 "any_parallel_operand"
13865 [(return)
13866 (clobber (match_operand:P 1 "register_operand" "=l"))
13867 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13868 (use (reg:P 12))
13869 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13870 (match_operand:P 4 "memory_operand" "m"))])]
13871 ""
13872 "b %2"
13873 [(set_attr "type" "branch")
13874 (set_attr "length" "4")])
13876 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13877 [(match_parallel 0 "any_parallel_operand"
13878 [(return)
13879 (clobber (match_operand:P 1 "register_operand" "=l"))
13880 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13881 (use (reg:P 1))
13882 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13883 (match_operand:P 4 "memory_operand" "m"))])]
13884 ""
13885 "b %2"
13886 [(set_attr "type" "branch")
13887 (set_attr "length" "4")])
13889 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13890 [(match_parallel 0 "any_parallel_operand"
13891 [(return)
13892 (clobber (match_operand:P 1 "register_operand" "=l"))
13893 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13894 (use (reg:P 11))
13895 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13896 (match_operand:DF 4 "memory_operand" "m"))])]
13897 ""
13898 "b %2"
13899 [(set_attr "type" "branch")
13900 (set_attr "length" "4")])
13902 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13903 [(match_parallel 0 "any_parallel_operand"
13904 [(return)
13905 (clobber (match_operand:P 1 "register_operand" "=l"))
13906 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13907 (use (reg:P 12))
13908 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13909 (match_operand:DF 4 "memory_operand" "m"))])]
13910 ""
13911 "b %2"
13912 [(set_attr "type" "branch")
13913 (set_attr "length" "4")])
13915 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13916 [(match_parallel 0 "any_parallel_operand"
13917 [(return)
13918 (clobber (match_operand:P 1 "register_operand" "=l"))
13919 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13920 (use (reg:P 1))
13921 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13922 (match_operand:DF 4 "memory_operand" "m"))])]
13923 ""
13924 "b %2"
13925 [(set_attr "type" "branch")
13926 (set_attr "length" "4")])
13928 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13929 [(match_parallel 0 "any_parallel_operand"
13930 [(return)
13931 (use (match_operand:P 1 "register_operand" "l"))
13932 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13933 (use (reg:P 11))
13934 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13935 (match_operand:DF 4 "memory_operand" "m"))])]
13936 ""
13937 "b %2"
13938 [(set_attr "type" "branch")
13939 (set_attr "length" "4")])
13941 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13942 [(match_parallel 0 "any_parallel_operand"
13943 [(return)
13944 (use (match_operand:P 1 "register_operand" "l"))
13945 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13946 (use (reg:P 1))
13947 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13948 (match_operand:DF 4 "memory_operand" "m"))])]
13949 ""
13950 "b %2"
13951 [(set_attr "type" "branch")
13952 (set_attr "length" "4")])
13954 ; This is used in compiling the unwind routines.
13955 (define_expand "eh_return"
13956 [(use (match_operand 0 "general_operand" ""))]
13957 ""
13958 "
13959 {
13960 if (TARGET_32BIT)
13961 emit_insn (gen_eh_set_lr_si (operands[0]));
13962 else
13963 emit_insn (gen_eh_set_lr_di (operands[0]));
13964 DONE;
13965 }")
13967 ; We can't expand this before we know where the link register is stored.
13968 (define_insn "eh_set_lr_<mode>"
13969 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13970 UNSPECV_EH_RR)
13971 (clobber (match_scratch:P 1 "=&b"))]
13972 ""
13973 "#")
13975 (define_split
13976 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13977 (clobber (match_scratch 1 ""))]
13978 "reload_completed"
13979 [(const_int 0)]
13980 "
13981 {
13982 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13983 DONE;
13984 }")
13986 (define_insn "prefetch"
13987 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13988 (match_operand:SI 1 "const_int_operand" "n")
13989 (match_operand:SI 2 "const_int_operand" "n"))]
13990 ""
13991 "*
13992 {
13993 if (GET_CODE (operands[0]) == REG)
13994 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13995 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13996 }"
13997 [(set_attr "type" "load")])
13998 \f
13999 (define_insn "bpermd_<mode>"
14000 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14001 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14002 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14003 "TARGET_POPCNTD"
14004 "bpermd %0,%1,%2"
14005 [(set_attr "type" "popcnt")])
14007 \f
14008 ;; Builtin fma support. Handle
14009 ;; Note that the conditions for expansion are in the FMA_F iterator.
14011 (define_expand "fma<mode>4"
14012 [(set (match_operand:FMA_F 0 "register_operand" "")
14013 (fma:FMA_F
14014 (match_operand:FMA_F 1 "register_operand" "")
14015 (match_operand:FMA_F 2 "register_operand" "")
14016 (match_operand:FMA_F 3 "register_operand" "")))]
14017 ""
14018 "")
14020 (define_insn "*fma<mode>4_fpr"
14021 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14022 (fma:SFDF
14023 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14024 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14025 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14026 "TARGET_<MODE>_FPR"
14027 "@
14028 fmadd<Ftrad> %0,%1,%2,%3
14029 xsmadda<Fvsx> %x0,%x1,%x2
14030 xsmaddm<Fvsx> %x0,%x1,%x3"
14031 [(set_attr "type" "fp")
14032 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14034 ; Altivec only has fma and nfms.
14035 (define_expand "fms<mode>4"
14036 [(set (match_operand:FMA_F 0 "register_operand" "")
14037 (fma:FMA_F
14038 (match_operand:FMA_F 1 "register_operand" "")
14039 (match_operand:FMA_F 2 "register_operand" "")
14040 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14041 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14042 "")
14044 (define_insn "*fms<mode>4_fpr"
14045 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14046 (fma:SFDF
14047 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14048 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14049 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14050 "TARGET_<MODE>_FPR"
14051 "@
14052 fmsub<Ftrad> %0,%1,%2,%3
14053 xsmsuba<Fvsx> %x0,%x1,%x2
14054 xsmsubm<Fvsx> %x0,%x1,%x3"
14055 [(set_attr "type" "fp")
14056 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14058 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14059 (define_expand "fnma<mode>4"
14060 [(set (match_operand:FMA_F 0 "register_operand" "")
14061 (neg:FMA_F
14062 (fma:FMA_F
14063 (match_operand:FMA_F 1 "register_operand" "")
14064 (match_operand:FMA_F 2 "register_operand" "")
14065 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14066 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14067 "")
14069 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14070 (define_expand "fnms<mode>4"
14071 [(set (match_operand:FMA_F 0 "register_operand" "")
14072 (neg:FMA_F
14073 (fma:FMA_F
14074 (match_operand:FMA_F 1 "register_operand" "")
14075 (match_operand:FMA_F 2 "register_operand" "")
14076 (match_operand:FMA_F 3 "register_operand" ""))))]
14077 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14078 "")
14080 ; Not an official optab name, but used from builtins.
14081 (define_expand "nfma<mode>4"
14082 [(set (match_operand:FMA_F 0 "register_operand" "")
14083 (neg:FMA_F
14084 (fma:FMA_F
14085 (match_operand:FMA_F 1 "register_operand" "")
14086 (match_operand:FMA_F 2 "register_operand" "")
14087 (match_operand:FMA_F 3 "register_operand" ""))))]
14088 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14089 "")
14091 (define_insn "*nfma<mode>4_fpr"
14092 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14093 (neg:SFDF
14094 (fma:SFDF
14095 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14096 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14097 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14098 "TARGET_<MODE>_FPR"
14099 "@
14100 fnmadd<Ftrad> %0,%1,%2,%3
14101 xsnmadda<Fvsx> %x0,%x1,%x2
14102 xsnmaddm<Fvsx> %x0,%x1,%x3"
14103 [(set_attr "type" "fp")
14104 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14106 ; Not an official optab name, but used from builtins.
14107 (define_expand "nfms<mode>4"
14108 [(set (match_operand:FMA_F 0 "register_operand" "")
14109 (neg:FMA_F
14110 (fma:FMA_F
14111 (match_operand:FMA_F 1 "register_operand" "")
14112 (match_operand:FMA_F 2 "register_operand" "")
14113 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14114 ""
14115 "")
14117 (define_insn "*nfmssf4_fpr"
14118 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14119 (neg:SFDF
14120 (fma:SFDF
14121 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14122 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14123 (neg:SFDF
14124 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14125 "TARGET_<MODE>_FPR"
14126 "@
14127 fnmsub<Ftrad> %0,%1,%2,%3
14128 xsnmsuba<Fvsx> %x0,%x1,%x2
14129 xsnmsubm<Fvsx> %x0,%x1,%x3"
14130 [(set_attr "type" "fp")
14131 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14133 \f
14134 (define_expand "rs6000_get_timebase"
14135 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14136 ""
14137 {
14138 if (TARGET_POWERPC64)
14139 emit_insn (gen_rs6000_mftb_di (operands[0]));
14140 else
14141 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14142 DONE;
14143 })
14145 (define_insn "rs6000_get_timebase_ppc32"
14146 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14147 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14148 (clobber (match_scratch:SI 1 "=r"))
14149 (clobber (match_scratch:CC 2 "=y"))]
14150 "!TARGET_POWERPC64"
14151 {
14152 if (WORDS_BIG_ENDIAN)
14153 if (TARGET_MFCRF)
14154 {
14155 return "mfspr %0,269\;"
14156 "mfspr %L0,268\;"
14157 "mfspr %1,269\;"
14158 "cmpw %2,%0,%1\;"
14159 "bne- %2,$-16";
14160 }
14161 else
14162 {
14163 return "mftbu %0\;"
14164 "mftb %L0\;"
14165 "mftbu %1\;"
14166 "cmpw %2,%0,%1\;"
14167 "bne- %2,$-16";
14168 }
14169 else
14170 if (TARGET_MFCRF)
14171 {
14172 return "mfspr %L0,269\;"
14173 "mfspr %0,268\;"
14174 "mfspr %1,269\;"
14175 "cmpw %2,%L0,%1\;"
14176 "bne- %2,$-16";
14177 }
14178 else
14179 {
14180 return "mftbu %L0\;"
14181 "mftb %0\;"
14182 "mftbu %1\;"
14183 "cmpw %2,%L0,%1\;"
14184 "bne- %2,$-16";
14185 }
14186 }
14187 [(set_attr "length" "20")])
14189 (define_insn "rs6000_mftb_<mode>"
14190 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
14191 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
14192 ""
14193 {
14194 if (TARGET_MFCRF)
14195 return "mfspr %0,268";
14196 else
14197 return "mftb %0";
14198 })
14200 \f
14201 (define_insn "rs6000_mffs"
14202 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14203 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14204 "TARGET_HARD_FLOAT && TARGET_FPRS"
14205 "mffs %0")
14207 (define_insn "rs6000_mtfsf"
14208 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14209 (match_operand:DF 1 "gpc_reg_operand" "d")]
14210 UNSPECV_MTFSF)]
14211 "TARGET_HARD_FLOAT && TARGET_FPRS"
14212 "mtfsf %0,%1")
14214 \f
14215 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14216 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14217 ;; register that is being loaded. The fused ops must be physically adjacent.
14219 ;; Find cases where the addis that feeds into a load instruction is either used
14220 ;; once or is the same as the target register, and replace it with the fusion
14221 ;; insn
14223 (define_peephole2
14224 [(set (match_operand:P 0 "base_reg_operand" "")
14225 (match_operand:P 1 "fusion_gpr_addis" ""))
14226 (set (match_operand:INT1 2 "base_reg_operand" "")
14227 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14228 "TARGET_P8_FUSION
14229 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
14230 operands[3])"
14231 [(const_int 0)]
14232 {
14233 expand_fusion_gpr_load (operands);
14234 DONE;
14235 })
14237 ;; Fusion insn, created by the define_peephole2 above (and eventually by
14238 ;; reload)
14240 (define_insn "fusion_gpr_load_<mode>"
14241 [(set (match_operand:INT1 0 "base_reg_operand" "=&b")
14242 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
14243 UNSPEC_FUSION_GPR))]
14244 "TARGET_P8_FUSION"
14245 {
14246 return emit_fusion_gpr_load (operands[0], operands[1]);
14247 }
14248 [(set_attr "type" "load")
14249 (set_attr "length" "8")])
14251 \f
14252 ;; Miscellaneous ISA 2.06 (power7) instructions
14253 (define_insn "addg6s"
14254 [(set (match_operand:SI 0 "register_operand" "=r")
14255 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14256 (match_operand:SI 2 "register_operand" "r")]
14257 UNSPEC_ADDG6S))]
14258 "TARGET_POPCNTD"
14259 "addg6s %0,%1,%2"
14260 [(set_attr "type" "integer")
14261 (set_attr "length" "4")])
14263 (define_insn "cdtbcd"
14264 [(set (match_operand:SI 0 "register_operand" "=r")
14265 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14266 UNSPEC_CDTBCD))]
14267 "TARGET_POPCNTD"
14268 "cdtbcd %0,%1"
14269 [(set_attr "type" "integer")
14270 (set_attr "length" "4")])
14272 (define_insn "cbcdtd"
14273 [(set (match_operand:SI 0 "register_operand" "=r")
14274 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14275 UNSPEC_CBCDTD))]
14276 "TARGET_POPCNTD"
14277 "cbcdtd %0,%1"
14278 [(set_attr "type" "integer")
14279 (set_attr "length" "4")])
14281 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14282 UNSPEC_DIVEO
14283 UNSPEC_DIVEU
14284 UNSPEC_DIVEUO])
14286 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14287 (UNSPEC_DIVEO "eo")
14288 (UNSPEC_DIVEU "eu")
14289 (UNSPEC_DIVEUO "euo")])
14291 (define_insn "div<div_extend>_<mode>"
14292 [(set (match_operand:GPR 0 "register_operand" "=r")
14293 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14294 (match_operand:GPR 2 "register_operand" "r")]
14295 UNSPEC_DIV_EXTEND))]
14296 "TARGET_POPCNTD"
14297 "div<wd><div_extend> %0,%1,%2"
14298 [(set_attr "type" "div")
14299 (set_attr "size" "<bits>")])
14301 \f
14302 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14304 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14305 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14307 (define_expand "unpack<mode>"
14308 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14309 (unspec:<FP128_64>
14310 [(match_operand:FMOVE128 1 "register_operand" "")
14311 (match_operand:QI 2 "const_0_to_1_operand" "")]
14312 UNSPEC_UNPACK_128BIT))]
14313 ""
14314 "")
14316 (define_insn_and_split "unpack<mode>_dm"
14317 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14318 (unspec:<FP128_64>
14319 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14320 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14321 UNSPEC_UNPACK_128BIT))]
14322 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14323 "#"
14324 "&& reload_completed"
14325 [(set (match_dup 0) (match_dup 3))]
14326 {
14327 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14329 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14330 {
14331 emit_note (NOTE_INSN_DELETED);
14332 DONE;
14333 }
14335 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14336 }
14337 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14338 (set_attr "length" "4")])
14340 (define_insn_and_split "unpack<mode>_nodm"
14341 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14342 (unspec:<FP128_64>
14343 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14344 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14345 UNSPEC_UNPACK_128BIT))]
14346 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14347 "#"
14348 "&& reload_completed"
14349 [(set (match_dup 0) (match_dup 3))]
14350 {
14351 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14353 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14354 {
14355 emit_note (NOTE_INSN_DELETED);
14356 DONE;
14357 }
14359 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14360 }
14361 [(set_attr "type" "fp,fpstore")
14362 (set_attr "length" "4")])
14364 (define_insn_and_split "pack<mode>"
14365 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14366 (unspec:FMOVE128
14367 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14368 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14369 UNSPEC_PACK_128BIT))]
14370 ""
14371 "@
14372 fmr %L0,%2
14373 #"
14374 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14375 [(set (match_dup 3) (match_dup 1))
14376 (set (match_dup 4) (match_dup 2))]
14377 {
14378 unsigned dest_hi = REGNO (operands[0]);
14379 unsigned dest_lo = dest_hi + 1;
14381 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14382 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14384 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14385 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14386 }
14387 [(set_attr "type" "fp,fp")
14388 (set_attr "length" "4,8")])
14390 (define_insn "unpackv1ti"
14391 [(set (match_operand:DI 0 "register_operand" "=d,d")
14392 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14393 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14394 UNSPEC_UNPACK_128BIT))]
14395 "TARGET_VSX"
14396 {
14397 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14398 return ASM_COMMENT_START " xxpermdi to same register";
14400 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14401 return "xxpermdi %x0,%x1,%x1,%3";
14402 }
14403 [(set_attr "type" "vecperm")
14404 (set_attr "length" "4")])
14406 (define_insn "packv1ti"
14407 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14408 (unspec:V1TI
14409 [(match_operand:DI 1 "register_operand" "d")
14410 (match_operand:DI 2 "register_operand" "d")]
14411 UNSPEC_PACK_128BIT))]
14412 "TARGET_VSX"
14413 "xxpermdi %x0,%x1,%x2,0"
14414 [(set_attr "type" "vecperm")
14415 (set_attr "length" "4")])
14417 \f
14419 (include "sync.md")
14420 (include "vector.md")
14421 (include "vsx.md")
14422 (include "altivec.md")
14423 (include "spe.md")
14424 (include "dfp.md")
14425 (include "paired.md")
14426 (include "crypto.md")
14427 (include "htm.md")