| blob | 9f96270727b92c1ee2a57c89cdebc9e423a7fff7 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2012 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(STACK_POINTER_REGNUM 1)
29 (TOC_REGNUM 2)
30 (STATIC_CHAIN_REGNUM 11)
31 (HARD_FRAME_POINTER_REGNUM 31)
32 (LR_REGNO 65)
33 (CTR_REGNO 66)
34 (ARG_POINTER_REGNUM 67)
35 (CR0_REGNO 68)
36 (CR1_REGNO 69)
37 (CR2_REGNO 70)
38 (CR3_REGNO 71)
39 (CR4_REGNO 72)
40 (CR5_REGNO 73)
41 (CR6_REGNO 74)
42 (CR7_REGNO 75)
43 (MAX_CR_REGNO 75)
44 (CA_REGNO 76)
45 (FIRST_ALTIVEC_REGNO 77)
46 (LAST_ALTIVEC_REGNO 108)
47 (VRSAVE_REGNO 109)
48 (VSCR_REGNO 110)
49 (SPE_ACC_REGNO 111)
50 (SPEFSCR_REGNO 112)
51 (FRAME_POINTER_REGNUM 113)
53 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
54 (TOC_SAVE_OFFSET_32BIT 20)
55 (TOC_SAVE_OFFSET_64BIT 40)
57 ; Function TOC offset in the AIX function descriptor.
58 (AIX_FUNC_DESC_TOC_32BIT 4)
59 (AIX_FUNC_DESC_TOC_64BIT 8)
61 ; Static chain offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_SC_32BIT 8)
63 (AIX_FUNC_DESC_SC_64BIT 16)
64 ])
66 ;;
67 ;; UNSPEC usage
68 ;;
70 (define_c_enum "unspec"
71 [UNSPEC_FRSP ; frsp for POWER machines
72 UNSPEC_PROBE_STACK ; probe stack memory reference
73 UNSPEC_TOCPTR ; address of a word pointing to the TOC
74 UNSPEC_TOC ; address of the TOC (more-or-less)
75 UNSPEC_MOVSI_GOT
76 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
77 UNSPEC_FCTIWZ
78 UNSPEC_FRIM
79 UNSPEC_FRIN
80 UNSPEC_FRIP
81 UNSPEC_FRIZ
82 UNSPEC_LD_MPIC ; load_macho_picbase
83 UNSPEC_MPIC_CORRECT ; macho_correct_pic
84 UNSPEC_TLSGD
85 UNSPEC_TLSLD
86 UNSPEC_MOVESI_FROM_CR
87 UNSPEC_MOVESI_TO_CR
88 UNSPEC_TLSDTPREL
89 UNSPEC_TLSDTPRELHA
90 UNSPEC_TLSDTPRELLO
91 UNSPEC_TLSGOTDTPREL
92 UNSPEC_TLSTPREL
93 UNSPEC_TLSTPRELHA
94 UNSPEC_TLSTPRELLO
95 UNSPEC_TLSGOTTPREL
96 UNSPEC_TLSTLS
97 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
98 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
99 UNSPEC_STFIWX
100 UNSPEC_POPCNTB
101 UNSPEC_FRES
102 UNSPEC_SP_SET
103 UNSPEC_SP_TEST
104 UNSPEC_SYNC
105 UNSPEC_LWSYNC
106 UNSPEC_SYNC_OP
107 UNSPEC_ATOMIC
108 UNSPEC_CMPXCHG
109 UNSPEC_XCHG
110 UNSPEC_AND
111 UNSPEC_DLMZB
112 UNSPEC_DLMZB_CR
113 UNSPEC_DLMZB_STRLEN
114 UNSPEC_RSQRT
115 UNSPEC_TOCREL
116 UNSPEC_MACHOPIC_OFFSET
117 UNSPEC_BPERM
118 UNSPEC_COPYSIGN
119 UNSPEC_PARITY
120 UNSPEC_FCTIW
121 UNSPEC_FCTID
122 UNSPEC_LFIWAX
123 UNSPEC_LFIWZX
124 UNSPEC_FCTIWUZ
125 UNSPEC_GRP_END_NOP
126 ])
128 ;;
129 ;; UNSPEC_VOLATILE usage
130 ;;
132 (define_c_enum "unspecv"
133 [UNSPECV_BLOCK
134 UNSPECV_LL ; load-locked
135 UNSPECV_SC ; store-conditional
136 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
137 UNSPECV_EH_RR ; eh_reg_restore
138 UNSPECV_ISYNC ; isync instruction
139 UNSPECV_MFTB ; move from time base
140 ])
142 \f
143 ;; Define an insn type attribute. This is used in function unit delay
144 ;; computations.
145 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
146 (const_string "integer"))
148 ;; Define floating point instruction sub-types for use with Xfpu.md
149 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
151 ;; Length (in bytes).
152 ; '(pc)' in the following doesn't include the instruction itself; it is
153 ; calculated as if the instruction had zero size.
154 (define_attr "length" ""
155 (if_then_else (eq_attr "type" "branch")
156 (if_then_else (and (ge (minus (match_dup 0) (pc))
157 (const_int -32768))
158 (lt (minus (match_dup 0) (pc))
159 (const_int 32764)))
160 (const_int 4)
161 (const_int 8))
162 (const_int 4)))
164 ;; Processor type -- this attribute must exactly match the processor_type
165 ;; enumeration in rs6000.h.
167 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
168 (const (symbol_ref "rs6000_cpu_attr")))
171 ;; If this instruction is microcoded on the CELL processor
172 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
173 (define_attr "cell_micro" "not,conditional,always"
174 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
175 (const_string "always")
176 (const_string "not")))
178 (automata_option "ndfa")
180 (include "rs64.md")
181 (include "mpc.md")
182 (include "40x.md")
183 (include "440.md")
184 (include "476.md")
185 (include "601.md")
186 (include "603.md")
187 (include "6xx.md")
188 (include "7xx.md")
189 (include "7450.md")
190 (include "8540.md")
191 (include "e300c2c3.md")
192 (include "e500mc.md")
193 (include "e500mc64.md")
194 (include "e5500.md")
195 (include "e6500.md")
196 (include "power4.md")
197 (include "power5.md")
198 (include "power6.md")
199 (include "power7.md")
200 (include "cell.md")
201 (include "xfpu.md")
202 (include "a2.md")
203 (include "titan.md")
205 (include "predicates.md")
206 (include "constraints.md")
208 (include "darwin.md")
210 \f
211 ;; Mode iterators
213 ; This mode iterator allows :GPR to be used to indicate the allowable size
214 ; of whole values in GPRs.
215 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
217 ; Any supported integer mode.
218 (define_mode_iterator INT [QI HI SI DI TI])
220 ; Any supported integer mode that fits in one register.
221 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
223 ; extend modes for DImode
224 (define_mode_iterator QHSI [QI HI SI])
226 ; SImode or DImode, even if DImode doesn't fit in GPRs.
227 (define_mode_iterator SDI [SI DI])
229 ; The size of a pointer. Also, the size of the value that a record-condition
230 ; (one with a '.') will compare; and the size used for arithmetic carries.
231 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
233 ; Any hardware-supported floating-point mode
234 (define_mode_iterator FP [
235 (SF "TARGET_HARD_FLOAT
236 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
237 (DF "TARGET_HARD_FLOAT
238 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
239 (TF "!TARGET_IEEEQUAD
240 && TARGET_HARD_FLOAT
241 && (TARGET_FPRS || TARGET_E500_DOUBLE)
242 && TARGET_LONG_DOUBLE_128")
243 (DD "TARGET_DFP")
244 (TD "TARGET_DFP")])
246 ; Any fma capable floating-point mode.
247 (define_mode_iterator FMA_F [
248 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
249 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
250 || VECTOR_UNIT_VSX_P (DFmode)")
251 (V2SF "TARGET_PAIRED_FLOAT")
252 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
253 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
254 ])
256 ; These modes do not fit in integer registers in 32-bit mode.
257 ; but on e500v2, the gpr are 64 bit registers
258 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
260 ; Iterator for reciprocal estimate instructions
261 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
263 ; Iterator for just SF/DF
264 (define_mode_iterator SFDF [SF DF])
266 ; Conditional returns.
267 (define_code_iterator any_return [return simple_return])
268 (define_code_attr return_pred [(return "direct_return ()")
269 (simple_return "")])
270 (define_code_attr return_str [(return "") (simple_return "simple_")])
272 ; Various instructions that come in SI and DI forms.
273 ; A generic w/d attribute, for things like cmpw/cmpd.
274 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
276 ; DImode bits
277 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
279 ;; ISEL/ISEL64 target selection
280 (define_mode_attr sel [(SI "") (DI "64")])
282 ;; Suffix for reload patterns
283 (define_mode_attr ptrsize [(SI "32bit")
284 (DI "64bit")])
286 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
287 (DI "TARGET_64BIT")])
289 (define_mode_attr mptrsize [(SI "si")
290 (DI "di")])
292 (define_mode_attr ptrload [(SI "lwz")
293 (DI "ld")])
295 (define_mode_attr rreg [(SF "f")
296 (DF "ws")
297 (V4SF "wf")
298 (V2DF "wd")])
300 (define_mode_attr rreg2 [(SF "f")
301 (DF "d")])
303 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
304 (DF "TARGET_FCFID")])
306 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
307 (DF "TARGET_E500_DOUBLE")])
309 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
310 (DF "TARGET_DOUBLE_FLOAT")])
311 \f
312 ;; Start with fixed-point load and store insns. Here we put only the more
313 ;; complex forms. Basic data transfer is done later.
315 (define_expand "zero_extend<mode>di2"
316 [(set (match_operand:DI 0 "gpc_reg_operand" "")
317 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
318 "TARGET_POWERPC64"
319 "")
321 (define_insn "*zero_extend<mode>di2_internal1"
322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
324 "TARGET_POWERPC64"
325 "@
326 l<wd>z%U1%X1 %0,%1
327 rldicl %0,%1,0,<dbits>"
328 [(set_attr "type" "load,*")])
330 (define_insn "*zero_extend<mode>di2_internal2"
331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 "=r,r"))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %2,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
342 (define_split
343 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (clobber (match_scratch:DI 2 ""))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 2)
349 (zero_extend:DI (match_dup 1)))
350 (set (match_dup 0)
351 (compare:CC (match_dup 2)
352 (const_int 0)))]
353 "")
355 (define_insn "*zero_extend<mode>di2_internal3"
356 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
360 (zero_extend:DI (match_dup 1)))]
361 "TARGET_64BIT"
362 "@
363 rldicl. %0,%1,0,<dbits>
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
368 (define_split
369 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (set (match_operand:DI 0 "gpc_reg_operand" "")
373 (zero_extend:DI (match_dup 1)))]
374 "TARGET_POWERPC64 && reload_completed"
375 [(set (match_dup 0)
376 (zero_extend:DI (match_dup 1)))
377 (set (match_dup 2)
378 (compare:CC (match_dup 0)
379 (const_int 0)))]
380 "")
382 (define_insn "extendqidi2"
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
384 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
385 "TARGET_POWERPC64"
386 "extsb %0,%1"
387 [(set_attr "type" "exts")])
389 (define_insn ""
390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (clobber (match_scratch:DI 2 "=r,r"))]
394 "TARGET_64BIT"
395 "@
396 extsb. %2,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
401 (define_split
402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (clobber (match_scratch:DI 2 ""))]
406 "TARGET_POWERPC64 && reload_completed"
407 [(set (match_dup 2)
408 (sign_extend:DI (match_dup 1)))
409 (set (match_dup 0)
410 (compare:CC (match_dup 2)
411 (const_int 0)))]
412 "")
414 (define_insn ""
415 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
416 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_64BIT"
421 "@
422 extsb. %0,%1
423 #"
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
427 (define_split
428 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
429 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_POWERPC64 && reload_completed"
434 [(set (match_dup 0)
435 (sign_extend:DI (match_dup 1)))
436 (set (match_dup 2)
437 (compare:CC (match_dup 0)
438 (const_int 0)))]
439 "")
441 (define_expand "extendhidi2"
442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
444 "TARGET_POWERPC64"
445 "")
447 (define_insn ""
448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
449 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
450 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 "@
452 lha%U1%X1 %0,%1
453 extsh %0,%1"
454 [(set_attr "type" "load_ext,exts")])
456 (define_insn ""
457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
458 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
459 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 "extsh %0,%1"
461 [(set_attr "type" "exts")])
463 (define_insn ""
464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (clobber (match_scratch:DI 2 "=r,r"))]
468 "TARGET_64BIT"
469 "@
470 extsh. %2,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
475 (define_split
476 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (clobber (match_scratch:DI 2 ""))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 2)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 0)
484 (compare:CC (match_dup 2)
485 (const_int 0)))]
486 "")
488 (define_insn ""
489 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_64BIT"
495 "@
496 extsh. %0,%1
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
501 (define_split
502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
503 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (set (match_operand:DI 0 "gpc_reg_operand" "")
506 (sign_extend:DI (match_dup 1)))]
507 "TARGET_POWERPC64 && reload_completed"
508 [(set (match_dup 0)
509 (sign_extend:DI (match_dup 1)))
510 (set (match_dup 2)
511 (compare:CC (match_dup 0)
512 (const_int 0)))]
513 "")
515 (define_expand "extendsidi2"
516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
517 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
518 "TARGET_POWERPC64"
519 "")
521 (define_insn ""
522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
524 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
525 "@
526 lwa%U1%X1 %0,%1
527 extsw %0,%1"
528 [(set_attr "type" "load_ext,exts")])
530 (define_insn ""
531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
532 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
533 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
534 "extsw %0,%1"
535 [(set_attr "type" "exts")])
537 (define_insn ""
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (clobber (match_scratch:DI 2 "=r,r"))]
542 "TARGET_64BIT"
543 "@
544 extsw. %2,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
549 (define_split
550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 ""))]
554 "TARGET_POWERPC64 && reload_completed"
555 [(set (match_dup 2)
556 (sign_extend:DI (match_dup 1)))
557 (set (match_dup 0)
558 (compare:CC (match_dup 2)
559 (const_int 0)))]
560 "")
562 (define_insn ""
563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
567 (sign_extend:DI (match_dup 1)))]
568 "TARGET_64BIT"
569 "@
570 extsw. %0,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
575 (define_split
576 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_dup 1)))]
581 "TARGET_POWERPC64 && reload_completed"
582 [(set (match_dup 0)
583 (sign_extend:DI (match_dup 1)))
584 (set (match_dup 2)
585 (compare:CC (match_dup 0)
586 (const_int 0)))]
587 "")
589 (define_expand "zero_extendqisi2"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "")
591 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
595 (define_insn ""
596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 rlwinm %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:SI 2 "=r,r"))]
609 ""
610 "@
611 andi. %2,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:SI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:SI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:SI (match_dup 1)))]
635 ""
636 "@
637 andi. %0,%1,0xff
638 #"
639 [(set_attr "type" "fast_compare,compare")
640 (set_attr "length" "4,8")])
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
644 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:SI 0 "gpc_reg_operand" "")
647 (zero_extend:SI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:SI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
656 (define_insn "extendqisi2"
657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
658 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
659 ""
660 "extsb %0,%1"
661 [(set_attr "type" "exts")])
663 (define_insn ""
664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
665 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
666 (const_int 0)))
667 (clobber (match_scratch:SI 2 "=r,r"))]
668 ""
669 "@
670 extsb. %2,%1
671 #"
672 [(set_attr "type" "compare")
673 (set_attr "length" "4,8")])
675 (define_split
676 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
677 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
678 (const_int 0)))
679 (clobber (match_scratch:SI 2 ""))]
680 "reload_completed"
681 [(set (match_dup 2)
682 (sign_extend:SI (match_dup 1)))
683 (set (match_dup 0)
684 (compare:CC (match_dup 2)
685 (const_int 0)))]
686 "")
688 (define_insn ""
689 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
690 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
693 (sign_extend:SI (match_dup 1)))]
694 ""
695 "@
696 extsb. %0,%1
697 #"
698 [(set_attr "type" "compare")
699 (set_attr "length" "4,8")])
701 (define_split
702 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
703 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
704 (const_int 0)))
705 (set (match_operand:SI 0 "gpc_reg_operand" "")
706 (sign_extend:SI (match_dup 1)))]
707 "reload_completed"
708 [(set (match_dup 0)
709 (sign_extend:SI (match_dup 1)))
710 (set (match_dup 2)
711 (compare:CC (match_dup 0)
712 (const_int 0)))]
713 "")
715 (define_insn ""
716 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
717 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
718 ""
719 "@
720 lbz%U1%X1 %0,%1
721 rlwinm %0,%1,0,0xff"
722 [(set_attr "type" "load,*")])
724 (define_insn ""
725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
726 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
727 (const_int 0)))
728 (clobber (match_scratch:HI 2 "=r,r"))]
729 ""
730 "@
731 andi. %2,%1,0xff
732 #"
733 [(set_attr "type" "fast_compare,compare")
734 (set_attr "length" "4,8")])
736 (define_split
737 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
738 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
739 (const_int 0)))
740 (clobber (match_scratch:HI 2 ""))]
741 "reload_completed"
742 [(set (match_dup 2)
743 (zero_extend:HI (match_dup 1)))
744 (set (match_dup 0)
745 (compare:CC (match_dup 2)
746 (const_int 0)))]
747 "")
749 (define_insn ""
750 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
751 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
752 (const_int 0)))
753 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
754 (zero_extend:HI (match_dup 1)))]
755 ""
756 "@
757 andi. %0,%1,0xff
758 #"
759 [(set_attr "type" "fast_compare,compare")
760 (set_attr "length" "4,8")])
762 (define_split
763 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
764 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
765 (const_int 0)))
766 (set (match_operand:HI 0 "gpc_reg_operand" "")
767 (zero_extend:HI (match_dup 1)))]
768 "reload_completed"
769 [(set (match_dup 0)
770 (zero_extend:HI (match_dup 1)))
771 (set (match_dup 2)
772 (compare:CC (match_dup 0)
773 (const_int 0)))]
774 "")
776 (define_insn "extendqihi2"
777 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
778 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
779 ""
780 "extsb %0,%1"
781 [(set_attr "type" "exts")])
783 (define_insn ""
784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
785 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
786 (const_int 0)))
787 (clobber (match_scratch:HI 2 "=r,r"))]
788 ""
789 "@
790 extsb. %2,%1
791 #"
792 [(set_attr "type" "compare")
793 (set_attr "length" "4,8")])
795 (define_split
796 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
797 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
798 (const_int 0)))
799 (clobber (match_scratch:HI 2 ""))]
800 "reload_completed"
801 [(set (match_dup 2)
802 (sign_extend:HI (match_dup 1)))
803 (set (match_dup 0)
804 (compare:CC (match_dup 2)
805 (const_int 0)))]
806 "")
808 (define_insn ""
809 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
810 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
811 (const_int 0)))
812 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
813 (sign_extend:HI (match_dup 1)))]
814 ""
815 "@
816 extsb. %0,%1
817 #"
818 [(set_attr "type" "compare")
819 (set_attr "length" "4,8")])
821 (define_split
822 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
823 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
824 (const_int 0)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (sign_extend:HI (match_dup 1)))]
827 "reload_completed"
828 [(set (match_dup 0)
829 (sign_extend:HI (match_dup 1)))
830 (set (match_dup 2)
831 (compare:CC (match_dup 0)
832 (const_int 0)))]
833 "")
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
838 ""
839 "")
841 (define_insn ""
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
847 rlwinm %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
850 (define_insn ""
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (clobber (match_scratch:SI 2 "=r,r"))]
855 ""
856 "@
857 andi. %2,%1,0xffff
858 #"
859 [(set_attr "type" "fast_compare,compare")
860 (set_attr "length" "4,8")])
862 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
875 (define_insn ""
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
881 ""
882 "@
883 andi. %0,%1,0xffff
884 #"
885 [(set_attr "type" "fast_compare,compare")
886 (set_attr "length" "4,8")])
888 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
905 ""
906 "")
908 (define_insn ""
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 "rs6000_gen_cell_microcode"
912 "@
913 lha%U1%X1 %0,%1
914 extsh %0,%1"
915 [(set_attr "type" "load_ext,exts")])
917 (define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
921 "extsh %0,%1"
922 [(set_attr "type" "exts")])
924 (define_insn ""
925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
927 (const_int 0)))
928 (clobber (match_scratch:SI 2 "=r,r"))]
929 ""
930 "@
931 extsh. %2,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
936 (define_split
937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (const_int 0)))
940 (clobber (match_scratch:SI 2 ""))]
941 "reload_completed"
942 [(set (match_dup 2)
943 (sign_extend:SI (match_dup 1)))
944 (set (match_dup 0)
945 (compare:CC (match_dup 2)
946 (const_int 0)))]
947 "")
949 (define_insn ""
950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (sign_extend:SI (match_dup 1)))]
955 ""
956 "@
957 extsh. %0,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
962 (define_split
963 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "")
967 (sign_extend:SI (match_dup 1)))]
968 "reload_completed"
969 [(set (match_dup 0)
970 (sign_extend:SI (match_dup 1)))
971 (set (match_dup 2)
972 (compare:CC (match_dup 0)
973 (const_int 0)))]
974 "")
975 \f
976 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
978 (define_insn "*macchwc"
979 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
980 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
981 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (const_int 16))
983 (sign_extend:SI
984 (match_operand:HI 1 "gpc_reg_operand" "r")))
985 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (ashiftrt:SI
989 (match_dup 2)
990 (const_int 16))
991 (sign_extend:SI
992 (match_dup 1)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "macchw. %0,%1,%2"
996 [(set_attr "type" "imul3")])
998 (define_insn "*macchw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (const_int 16))
1003 (sign_extend:SI
1004 (match_operand:HI 1 "gpc_reg_operand" "r")))
1005 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1006 "TARGET_MULHW"
1007 "macchw %0,%1,%2"
1008 [(set_attr "type" "imul3")])
1010 (define_insn "*macchwuc"
1011 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1012 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1013 (match_operand:SI 2 "gpc_reg_operand" "r")
1014 (const_int 16))
1015 (zero_extend:SI
1016 (match_operand:HI 1 "gpc_reg_operand" "r")))
1017 (match_operand:SI 4 "gpc_reg_operand" "0"))
1018 (const_int 0)))
1019 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1020 (plus:SI (mult:SI (lshiftrt:SI
1021 (match_dup 2)
1022 (const_int 16))
1023 (zero_extend:SI
1024 (match_dup 1)))
1025 (match_dup 4)))]
1026 "TARGET_MULHW"
1027 "macchwu. %0,%1,%2"
1028 [(set_attr "type" "imul3")])
1030 (define_insn "*macchwu"
1031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1032 (plus:SI (mult:SI (lshiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16))
1035 (zero_extend:SI
1036 (match_operand:HI 1 "gpc_reg_operand" "r")))
1037 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1038 "TARGET_MULHW"
1039 "macchwu %0,%1,%2"
1040 [(set_attr "type" "imul3")])
1042 (define_insn "*machhwc"
1043 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1044 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1045 (match_operand:SI 1 "gpc_reg_operand" "%r")
1046 (const_int 16))
1047 (ashiftrt:SI
1048 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (const_int 16)))
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (const_int 0)))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (ashiftrt:SI
1054 (match_dup 1)
1055 (const_int 16))
1056 (ashiftrt:SI
1057 (match_dup 2)
1058 (const_int 16)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "machhw. %0,%1,%2"
1062 [(set_attr "type" "imul3")])
1064 (define_insn "*machhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (ashiftrt:SI
1067 (match_operand:SI 1 "gpc_reg_operand" "%r")
1068 (const_int 16))
1069 (ashiftrt:SI
1070 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (const_int 16)))
1072 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1073 "TARGET_MULHW"
1074 "machhw %0,%1,%2"
1075 [(set_attr "type" "imul3")])
1077 (define_insn "*machhwuc"
1078 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1079 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1080 (match_operand:SI 1 "gpc_reg_operand" "%r")
1081 (const_int 16))
1082 (lshiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16)))
1085 (match_operand:SI 4 "gpc_reg_operand" "0"))
1086 (const_int 0)))
1087 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1088 (plus:SI (mult:SI (lshiftrt:SI
1089 (match_dup 1)
1090 (const_int 16))
1091 (lshiftrt:SI
1092 (match_dup 2)
1093 (const_int 16)))
1094 (match_dup 4)))]
1095 "TARGET_MULHW"
1096 "machhwu. %0,%1,%2"
1097 [(set_attr "type" "imul3")])
1099 (define_insn "*machhwu"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (lshiftrt:SI
1102 (match_operand:SI 1 "gpc_reg_operand" "%r")
1103 (const_int 16))
1104 (lshiftrt:SI
1105 (match_operand:SI 2 "gpc_reg_operand" "r")
1106 (const_int 16)))
1107 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1108 "TARGET_MULHW"
1109 "machhwu %0,%1,%2"
1110 [(set_attr "type" "imul3")])
1112 (define_insn "*maclhwc"
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1115 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1116 (sign_extend:SI
1117 (match_operand:HI 2 "gpc_reg_operand" "r")))
1118 (match_operand:SI 4 "gpc_reg_operand" "0"))
1119 (const_int 0)))
1120 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (plus:SI (mult:SI (sign_extend:SI
1122 (match_dup 1))
1123 (sign_extend:SI
1124 (match_dup 2)))
1125 (match_dup 4)))]
1126 "TARGET_MULHW"
1127 "maclhw. %0,%1,%2"
1128 [(set_attr "type" "imul3")])
1130 (define_insn "*maclhw"
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1132 (plus:SI (mult:SI (sign_extend:SI
1133 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1134 (sign_extend:SI
1135 (match_operand:HI 2 "gpc_reg_operand" "r")))
1136 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1137 "TARGET_MULHW"
1138 "maclhw %0,%1,%2"
1139 [(set_attr "type" "imul3")])
1141 (define_insn "*maclhwuc"
1142 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1143 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1144 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1145 (zero_extend:SI
1146 (match_operand:HI 2 "gpc_reg_operand" "r")))
1147 (match_operand:SI 4 "gpc_reg_operand" "0"))
1148 (const_int 0)))
1149 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1150 (plus:SI (mult:SI (zero_extend:SI
1151 (match_dup 1))
1152 (zero_extend:SI
1153 (match_dup 2)))
1154 (match_dup 4)))]
1155 "TARGET_MULHW"
1156 "maclhwu. %0,%1,%2"
1157 [(set_attr "type" "imul3")])
1159 (define_insn "*maclhwu"
1160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (plus:SI (mult:SI (zero_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (zero_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r")))
1165 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1166 "TARGET_MULHW"
1167 "maclhwu %0,%1,%2"
1168 [(set_attr "type" "imul3")])
1170 (define_insn "*nmacchwc"
1171 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1172 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1173 (mult:SI (ashiftrt:SI
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1175 (const_int 16))
1176 (sign_extend:SI
1177 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (ashiftrt:SI
1182 (match_dup 2)
1183 (const_int 16))
1184 (sign_extend:SI
1185 (match_dup 1)))))]
1186 "TARGET_MULHW"
1187 "nmacchw. %0,%1,%2"
1188 [(set_attr "type" "imul3")])
1190 (define_insn "*nmacchw"
1191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1192 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1193 (mult:SI (ashiftrt:SI
1194 (match_operand:SI 2 "gpc_reg_operand" "r")
1195 (const_int 16))
1196 (sign_extend:SI
1197 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1198 "TARGET_MULHW"
1199 "nmacchw %0,%1,%2"
1200 [(set_attr "type" "imul3")])
1202 (define_insn "*nmachhwc"
1203 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1204 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1205 (mult:SI (ashiftrt:SI
1206 (match_operand:SI 1 "gpc_reg_operand" "%r")
1207 (const_int 16))
1208 (ashiftrt:SI
1209 (match_operand:SI 2 "gpc_reg_operand" "r")
1210 (const_int 16))))
1211 (const_int 0)))
1212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (minus:SI (match_dup 4)
1214 (mult:SI (ashiftrt:SI
1215 (match_dup 1)
1216 (const_int 16))
1217 (ashiftrt:SI
1218 (match_dup 2)
1219 (const_int 16)))))]
1220 "TARGET_MULHW"
1221 "nmachhw. %0,%1,%2"
1222 [(set_attr "type" "imul3")])
1224 (define_insn "*nmachhw"
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1227 (mult:SI (ashiftrt:SI
1228 (match_operand:SI 1 "gpc_reg_operand" "%r")
1229 (const_int 16))
1230 (ashiftrt:SI
1231 (match_operand:SI 2 "gpc_reg_operand" "r")
1232 (const_int 16)))))]
1233 "TARGET_MULHW"
1234 "nmachhw %0,%1,%2"
1235 [(set_attr "type" "imul3")])
1237 (define_insn "*nmaclhwc"
1238 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1239 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1240 (mult:SI (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1242 (sign_extend:SI
1243 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1244 (const_int 0)))
1245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (minus:SI (match_dup 4)
1247 (mult:SI (sign_extend:SI
1248 (match_dup 1))
1249 (sign_extend:SI
1250 (match_dup 2)))))]
1251 "TARGET_MULHW"
1252 "nmaclhw. %0,%1,%2"
1253 [(set_attr "type" "imul3")])
1255 (define_insn "*nmaclhw"
1256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1257 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1258 (mult:SI (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1260 (sign_extend:SI
1261 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1262 "TARGET_MULHW"
1263 "nmaclhw %0,%1,%2"
1264 [(set_attr "type" "imul3")])
1266 (define_insn "*mulchwc"
1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1268 (compare:CC (mult:SI (ashiftrt:SI
1269 (match_operand:SI 2 "gpc_reg_operand" "r")
1270 (const_int 16))
1271 (sign_extend:SI
1272 (match_operand:HI 1 "gpc_reg_operand" "r")))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (ashiftrt:SI
1276 (match_dup 2)
1277 (const_int 16))
1278 (sign_extend:SI
1279 (match_dup 1))))]
1280 "TARGET_MULHW"
1281 "mulchw. %0,%1,%2"
1282 [(set_attr "type" "imul3")])
1284 (define_insn "*mulchw"
1285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1286 (mult:SI (ashiftrt:SI
1287 (match_operand:SI 2 "gpc_reg_operand" "r")
1288 (const_int 16))
1289 (sign_extend:SI
1290 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1291 "TARGET_MULHW"
1292 "mulchw %0,%1,%2"
1293 [(set_attr "type" "imul3")])
1295 (define_insn "*mulchwuc"
1296 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1297 (compare:CC (mult:SI (lshiftrt:SI
1298 (match_operand:SI 2 "gpc_reg_operand" "r")
1299 (const_int 16))
1300 (zero_extend:SI
1301 (match_operand:HI 1 "gpc_reg_operand" "r")))
1302 (const_int 0)))
1303 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1304 (mult:SI (lshiftrt:SI
1305 (match_dup 2)
1306 (const_int 16))
1307 (zero_extend:SI
1308 (match_dup 1))))]
1309 "TARGET_MULHW"
1310 "mulchwu. %0,%1,%2"
1311 [(set_attr "type" "imul3")])
1313 (define_insn "*mulchwu"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))
1318 (zero_extend:SI
1319 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1320 "TARGET_MULHW"
1321 "mulchwu %0,%1,%2"
1322 [(set_attr "type" "imul3")])
1324 (define_insn "*mulhhwc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (ashiftrt:SI
1327 (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (const_int 16))
1329 (ashiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16)))
1332 (const_int 0)))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (mult:SI (ashiftrt:SI
1335 (match_dup 1)
1336 (const_int 16))
1337 (ashiftrt:SI
1338 (match_dup 2)
1339 (const_int 16))))]
1340 "TARGET_MULHW"
1341 "mulhhw. %0,%1,%2"
1342 [(set_attr "type" "imul3")])
1344 (define_insn "*mulhhw"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (ashiftrt:SI
1347 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (const_int 16))
1349 (ashiftrt:SI
1350 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (const_int 16))))]
1352 "TARGET_MULHW"
1353 "mulhhw %0,%1,%2"
1354 [(set_attr "type" "imul3")])
1356 (define_insn "*mulhhwuc"
1357 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1358 (compare:CC (mult:SI (lshiftrt:SI
1359 (match_operand:SI 1 "gpc_reg_operand" "%r")
1360 (const_int 16))
1361 (lshiftrt:SI
1362 (match_operand:SI 2 "gpc_reg_operand" "r")
1363 (const_int 16)))
1364 (const_int 0)))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (lshiftrt:SI
1367 (match_dup 1)
1368 (const_int 16))
1369 (lshiftrt:SI
1370 (match_dup 2)
1371 (const_int 16))))]
1372 "TARGET_MULHW"
1373 "mulhhwu. %0,%1,%2"
1374 [(set_attr "type" "imul3")])
1376 (define_insn "*mulhhwu"
1377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1378 (mult:SI (lshiftrt:SI
1379 (match_operand:SI 1 "gpc_reg_operand" "%r")
1380 (const_int 16))
1381 (lshiftrt:SI
1382 (match_operand:SI 2 "gpc_reg_operand" "r")
1383 (const_int 16))))]
1384 "TARGET_MULHW"
1385 "mulhhwu %0,%1,%2"
1386 [(set_attr "type" "imul3")])
1388 (define_insn "*mullhwc"
1389 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1390 (compare:CC (mult:SI (sign_extend:SI
1391 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1392 (sign_extend:SI
1393 (match_operand:HI 2 "gpc_reg_operand" "r")))
1394 (const_int 0)))
1395 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (sign_extend:SI
1397 (match_dup 1))
1398 (sign_extend:SI
1399 (match_dup 2))))]
1400 "TARGET_MULHW"
1401 "mullhw. %0,%1,%2"
1402 [(set_attr "type" "imul3")])
1404 (define_insn "*mullhw"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1406 (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (sign_extend:SI
1409 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1410 "TARGET_MULHW"
1411 "mullhw %0,%1,%2"
1412 [(set_attr "type" "imul3")])
1414 (define_insn "*mullhwuc"
1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1416 (compare:CC (mult:SI (zero_extend:SI
1417 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1418 (zero_extend:SI
1419 (match_operand:HI 2 "gpc_reg_operand" "r")))
1420 (const_int 0)))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (mult:SI (zero_extend:SI
1423 (match_dup 1))
1424 (zero_extend:SI
1425 (match_dup 2))))]
1426 "TARGET_MULHW"
1427 "mullhwu. %0,%1,%2"
1428 [(set_attr "type" "imul3")])
1430 (define_insn "*mullhwu"
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (mult:SI (zero_extend:SI
1433 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1434 (zero_extend:SI
1435 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1436 "TARGET_MULHW"
1437 "mullhwu %0,%1,%2"
1438 [(set_attr "type" "imul3")])
1439 \f
1440 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1441 (define_insn "dlmzb"
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1443 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1444 (match_operand:SI 2 "gpc_reg_operand" "r")]
1445 UNSPEC_DLMZB_CR))
1446 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1447 (unspec:SI [(match_dup 1)
1448 (match_dup 2)]
1449 UNSPEC_DLMZB))]
1450 "TARGET_DLMZB"
1451 "dlmzb. %0,%1,%2")
1453 (define_expand "strlensi"
1454 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1455 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1456 (match_operand:QI 2 "const_int_operand" "")
1457 (match_operand 3 "const_int_operand" "")]
1458 UNSPEC_DLMZB_STRLEN))
1459 (clobber (match_scratch:CC 4 "=x"))]
1460 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1461 {
1462 rtx result = operands[0];
1463 rtx src = operands[1];
1464 rtx search_char = operands[2];
1465 rtx align = operands[3];
1466 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1467 rtx loop_label, end_label, mem, cr0, cond;
1468 if (search_char != const0_rtx
1469 || GET_CODE (align) != CONST_INT
1470 || INTVAL (align) < 8)
1471 FAIL;
1472 word1 = gen_reg_rtx (SImode);
1473 word2 = gen_reg_rtx (SImode);
1474 scratch_dlmzb = gen_reg_rtx (SImode);
1475 scratch_string = gen_reg_rtx (Pmode);
1476 loop_label = gen_label_rtx ();
1477 end_label = gen_label_rtx ();
1478 addr = force_reg (Pmode, XEXP (src, 0));
1479 emit_move_insn (scratch_string, addr);
1480 emit_label (loop_label);
1481 mem = change_address (src, SImode, scratch_string);
1482 emit_move_insn (word1, mem);
1483 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1484 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1485 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1486 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1487 emit_jump_insn (gen_rtx_SET (VOIDmode,
1488 pc_rtx,
1489 gen_rtx_IF_THEN_ELSE (VOIDmode,
1490 cond,
1491 gen_rtx_LABEL_REF
1492 (VOIDmode,
1493 end_label),
1494 pc_rtx)));
1495 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1496 emit_jump_insn (gen_rtx_SET (VOIDmode,
1497 pc_rtx,
1498 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1499 emit_barrier ();
1500 emit_label (end_label);
1501 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1502 emit_insn (gen_subsi3 (result, scratch_string, addr));
1503 emit_insn (gen_subsi3 (result, result, const1_rtx));
1504 DONE;
1505 })
1506 \f
1507 ;; Fixed-point arithmetic insns.
1509 (define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1513 ""
1514 {
1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1516 {
1517 if (non_short_cint_operand (operands[2], DImode))
1518 FAIL;
1519 }
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
1522 {
1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
1527 HOST_WIDE_INT val = INTVAL (operands[2]);
1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1532 FAIL;
1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1539 DONE;
1540 }
1541 })
1543 ;; Discourage ai/addic because of carry but provide it in an alternative
1544 ;; allowing register zero as source.
1545 (define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1550 "@
1551 add %0,%1,%2
1552 addi %0,%1,%2
1553 addic %0,%1,%2
1554 addis %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1557 (define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "addis %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1565 (define_insn "*add<mode>3_internal2"
1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1569 (const_int 0)))
1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1571 ""
1572 "@
1573 add. %3,%1,%2
1574 addic. %3,%1,%2
1575 #
1576 #"
1577 [(set_attr "type" "fast_compare,compare,compare,compare")
1578 (set_attr "length" "4,4,8,8")])
1580 (define_split
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:GPR 3 ""))]
1586 "reload_completed"
1587 [(set (match_dup 3)
1588 (plus:GPR (match_dup 1)
1589 (match_dup 2)))
1590 (set (match_dup 0)
1591 (compare:CC (match_dup 3)
1592 (const_int 0)))]
1593 "")
1595 (define_insn "*add<mode>3_internal3"
1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1599 (const_int 0)))
1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1602 (match_dup 2)))]
1603 ""
1604 "@
1605 add. %0,%1,%2
1606 addic. %0,%1,%2
1607 #
1608 #"
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1612 (define_split
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
1616 (const_int 0)))
1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1619 "reload_completed"
1620 [(set (match_dup 0)
1621 (plus:P (match_dup 1)
1622 (match_dup 2)))
1623 (set (match_dup 3)
1624 (compare:CC (match_dup 0)
1625 (const_int 0)))]
1626 "")
1628 ;; Split an add that we can't do in one insn into two insns, each of which
1629 ;; does one 16-bit part. This is used by combine. Note that the low-order
1630 ;; add should be last in case the result gets used in an address.
1632 (define_split
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1636 ""
1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1639 {
1640 HOST_WIDE_INT val = INTVAL (operands[2]);
1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1644 operands[4] = GEN_INT (low);
1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1646 operands[3] = GEN_INT (rest);
1647 else if (can_create_pseudo_p ())
1648 {
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1652 DONE;
1653 }
1654 else
1655 FAIL;
1656 })
1658 (define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1661 ""
1662 "nor %0,%1,%1")
1664 (define_insn ""
1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 2 "=r,r"))]
1669 ""
1670 "@
1671 nor. %2,%1,%1
1672 #"
1673 [(set_attr "type" "fast_compare,compare")
1674 (set_attr "length" "4,8")])
1676 (define_split
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1679 (const_int 0)))
1680 (clobber (match_scratch:P 2 ""))]
1681 "reload_completed"
1682 [(set (match_dup 2)
1683 (not:P (match_dup 1)))
1684 (set (match_dup 0)
1685 (compare:CC (match_dup 2)
1686 (const_int 0)))]
1687 "")
1689 (define_insn ""
1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1692 (const_int 0)))
1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1695 ""
1696 "@
1697 nor. %0,%1,%1
1698 #"
1699 [(set_attr "type" "fast_compare,compare")
1700 (set_attr "length" "4,8")])
1702 (define_split
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1705 (const_int 0)))
1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1708 "reload_completed"
1709 [(set (match_dup 0)
1710 (not:P (match_dup 1)))
1711 (set (match_dup 2)
1712 (compare:CC (match_dup 0)
1713 (const_int 0)))]
1714 "")
1716 (define_insn ""
1717 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1718 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1719 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1720 ""
1721 "@
1722 subf %0,%2,%1
1723 subfic %0,%2,%1")
1725 (define_insn ""
1726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1728 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1729 (const_int 0)))
1730 (clobber (match_scratch:P 3 "=r,r"))]
1731 ""
1732 "@
1733 subf. %3,%2,%1
1734 #"
1735 [(set_attr "type" "fast_compare")
1736 (set_attr "length" "4,8")])
1738 (define_split
1739 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1740 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1741 (match_operand:P 2 "gpc_reg_operand" ""))
1742 (const_int 0)))
1743 (clobber (match_scratch:P 3 ""))]
1744 "reload_completed"
1745 [(set (match_dup 3)
1746 (minus:P (match_dup 1)
1747 (match_dup 2)))
1748 (set (match_dup 0)
1749 (compare:CC (match_dup 3)
1750 (const_int 0)))]
1751 "")
1753 (define_insn ""
1754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1755 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1756 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1757 (const_int 0)))
1758 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1759 (minus:P (match_dup 1)
1760 (match_dup 2)))]
1761 ""
1762 "@
1763 subf. %0,%2,%1
1764 #"
1765 [(set_attr "type" "fast_compare")
1766 (set_attr "length" "4,8")])
1768 (define_split
1769 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1770 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1771 (match_operand:P 2 "gpc_reg_operand" ""))
1772 (const_int 0)))
1773 (set (match_operand:P 0 "gpc_reg_operand" "")
1774 (minus:P (match_dup 1)
1775 (match_dup 2)))]
1776 "reload_completed"
1777 [(set (match_dup 0)
1778 (minus:P (match_dup 1)
1779 (match_dup 2)))
1780 (set (match_dup 3)
1781 (compare:CC (match_dup 0)
1782 (const_int 0)))]
1783 "")
1785 (define_expand "sub<mode>3"
1786 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1787 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1788 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1789 ""
1790 "
1791 {
1792 if (GET_CODE (operands[2]) == CONST_INT)
1793 {
1794 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1795 negate_rtx (<MODE>mode, operands[2])));
1796 DONE;
1797 }
1798 }")
1800 (define_expand "neg<mode>2"
1801 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1802 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1803 ""
1804 "")
1806 (define_insn "*neg<mode>2_internal"
1807 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1808 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1809 ""
1810 "neg %0,%1")
1812 (define_insn ""
1813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1814 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1815 (const_int 0)))
1816 (clobber (match_scratch:P 2 "=r,r"))]
1817 ""
1818 "@
1819 neg. %2,%1
1820 #"
1821 [(set_attr "type" "fast_compare")
1822 (set_attr "length" "4,8")])
1824 (define_split
1825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1826 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1827 (const_int 0)))
1828 (clobber (match_scratch:P 2 ""))]
1829 "reload_completed"
1830 [(set (match_dup 2)
1831 (neg:P (match_dup 1)))
1832 (set (match_dup 0)
1833 (compare:CC (match_dup 2)
1834 (const_int 0)))]
1835 "")
1837 (define_insn ""
1838 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1839 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1840 (const_int 0)))
1841 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1842 (neg:P (match_dup 1)))]
1843 ""
1844 "@
1845 neg. %0,%1
1846 #"
1847 [(set_attr "type" "fast_compare")
1848 (set_attr "length" "4,8")])
1850 (define_split
1851 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1852 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1853 (const_int 0)))
1854 (set (match_operand:P 0 "gpc_reg_operand" "")
1855 (neg:P (match_dup 1)))]
1856 "reload_completed"
1857 [(set (match_dup 0)
1858 (neg:P (match_dup 1)))
1859 (set (match_dup 2)
1860 (compare:CC (match_dup 0)
1861 (const_int 0)))]
1862 "")
1864 (define_insn "clz<mode>2"
1865 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1866 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1867 ""
1868 "cntlz<wd> %0,%1"
1869 [(set_attr "type" "cntlz")])
1871 (define_expand "ctz<mode>2"
1872 [(set (match_dup 2)
1873 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1874 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1875 (match_dup 2)))
1876 (clobber (scratch:CC))])
1877 (set (match_dup 4) (clz:GPR (match_dup 3)))
1878 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (minus:GPR (match_dup 5) (match_dup 4)))]
1880 ""
1881 {
1882 operands[2] = gen_reg_rtx (<MODE>mode);
1883 operands[3] = gen_reg_rtx (<MODE>mode);
1884 operands[4] = gen_reg_rtx (<MODE>mode);
1885 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1886 })
1888 (define_expand "ffs<mode>2"
1889 [(set (match_dup 2)
1890 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1891 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1892 (match_dup 2)))
1893 (clobber (scratch:CC))])
1894 (set (match_dup 4) (clz:GPR (match_dup 3)))
1895 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1896 (minus:GPR (match_dup 5) (match_dup 4)))]
1897 ""
1898 {
1899 operands[2] = gen_reg_rtx (<MODE>mode);
1900 operands[3] = gen_reg_rtx (<MODE>mode);
1901 operands[4] = gen_reg_rtx (<MODE>mode);
1902 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1903 })
1905 (define_insn "popcntb<mode>2"
1906 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1907 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1908 UNSPEC_POPCNTB))]
1909 "TARGET_POPCNTB"
1910 "popcntb %0,%1"
1911 [(set_attr "length" "4")
1912 (set_attr "type" "popcnt")])
1914 (define_insn "popcntd<mode>2"
1915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1916 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1917 "TARGET_POPCNTD"
1918 "popcnt<wd> %0,%1"
1919 [(set_attr "length" "4")
1920 (set_attr "type" "popcnt")])
1922 (define_expand "popcount<mode>2"
1923 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1924 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1925 "TARGET_POPCNTB || TARGET_POPCNTD"
1926 {
1927 rs6000_emit_popcount (operands[0], operands[1]);
1928 DONE;
1929 })
1931 (define_insn "parity<mode>2_cmpb"
1932 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1933 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1934 "TARGET_CMPB && TARGET_POPCNTB"
1935 "prty<wd> %0,%1")
1937 (define_expand "parity<mode>2"
1938 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1939 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1940 "TARGET_POPCNTB"
1941 {
1942 rs6000_emit_parity (operands[0], operands[1]);
1943 DONE;
1944 })
1946 ;; Since the hardware zeros the upper part of the register, save generating the
1947 ;; AND immediate if we are converting to unsigned
1948 (define_insn "*bswaphi2_extenddi"
1949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1950 (zero_extend:DI
1951 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1952 "TARGET_POWERPC64"
1953 "lhbrx %0,%y1"
1954 [(set_attr "length" "4")
1955 (set_attr "type" "load")])
1957 (define_insn "*bswaphi2_extendsi"
1958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1959 (zero_extend:SI
1960 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1961 ""
1962 "lhbrx %0,%y1"
1963 [(set_attr "length" "4")
1964 (set_attr "type" "load")])
1966 (define_expand "bswaphi2"
1967 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1968 (bswap:HI
1969 (match_operand:HI 1 "reg_or_mem_operand" "")))
1970 (clobber (match_scratch:SI 2 ""))])]
1971 ""
1972 {
1973 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1974 operands[1] = force_reg (HImode, operands[1]);
1975 })
1977 (define_insn "bswaphi2_internal"
1978 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1979 (bswap:HI
1980 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1981 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1982 ""
1983 "@
1984 lhbrx %0,%y1
1985 sthbrx %1,%y0
1986 #"
1987 [(set_attr "length" "4,4,12")
1988 (set_attr "type" "load,store,*")])
1990 (define_split
1991 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1992 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1993 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1994 "reload_completed"
1995 [(set (match_dup 3)
1996 (zero_extract:SI (match_dup 4)
1997 (const_int 8)
1998 (const_int 16)))
1999 (set (match_dup 2)
2000 (and:SI (ashift:SI (match_dup 4)
2001 (const_int 8))
2002 (const_int 65280))) ;; 0xff00
2003 (set (match_dup 3)
2004 (ior:SI (match_dup 3)
2005 (match_dup 2)))]
2006 "
2007 {
2008 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2009 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2010 }")
2012 (define_insn "*bswapsi2_extenddi"
2013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2014 (zero_extend:DI
2015 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2016 "TARGET_POWERPC64"
2017 "lwbrx %0,%y1"
2018 [(set_attr "length" "4")
2019 (set_attr "type" "load")])
2021 (define_expand "bswapsi2"
2022 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2023 (bswap:SI
2024 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2025 ""
2026 {
2027 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2028 operands[1] = force_reg (SImode, operands[1]);
2029 })
2031 (define_insn "*bswapsi2_internal"
2032 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2033 (bswap:SI
2034 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2035 ""
2036 "@
2037 lwbrx %0,%y1
2038 stwbrx %1,%y0
2039 #"
2040 [(set_attr "length" "4,4,12")
2041 (set_attr "type" "load,store,*")])
2043 (define_split
2044 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2045 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2046 "reload_completed"
2047 [(set (match_dup 0)
2048 (rotate:SI (match_dup 1) (const_int 8)))
2049 (set (zero_extract:SI (match_dup 0)
2050 (const_int 8)
2051 (const_int 0))
2052 (match_dup 1))
2053 (set (zero_extract:SI (match_dup 0)
2054 (const_int 8)
2055 (const_int 16))
2056 (rotate:SI (match_dup 1)
2057 (const_int 16)))]
2058 "")
2060 (define_expand "bswapdi2"
2061 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2062 (bswap:DI
2063 (match_operand:DI 1 "reg_or_mem_operand" "")))
2064 (clobber (match_scratch:DI 2 ""))
2065 (clobber (match_scratch:DI 3 ""))
2066 (clobber (match_scratch:DI 4 ""))])]
2067 ""
2068 {
2069 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2070 operands[1] = force_reg (DImode, operands[1]);
2072 if (!TARGET_POWERPC64)
2073 {
2074 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2075 that uses 64-bit registers needs the same scratch registers as 64-bit
2076 mode. */
2077 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2078 DONE;
2079 }
2080 })
2082 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2083 (define_insn "*bswapdi2_ldbrx"
2084 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2085 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2086 (clobber (match_scratch:DI 2 "=X,X,&r"))
2087 (clobber (match_scratch:DI 3 "=X,X,&r"))
2088 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2089 "TARGET_POWERPC64 && TARGET_LDBRX
2090 && (REG_P (operands[0]) || REG_P (operands[1]))"
2091 "@
2092 ldbrx %0,%y1
2093 stdbrx %1,%y0
2094 #"
2095 [(set_attr "length" "4,4,36")
2096 (set_attr "type" "load,store,*")])
2098 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2099 (define_insn "*bswapdi2_64bit"
2100 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2101 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2102 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2103 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2104 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2105 "TARGET_POWERPC64 && !TARGET_LDBRX
2106 && (REG_P (operands[0]) || REG_P (operands[1]))"
2107 "#"
2108 [(set_attr "length" "16,12,36")])
2110 (define_split
2111 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2112 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2113 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2114 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2115 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2116 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2117 [(const_int 0)]
2118 "
2119 {
2120 rtx dest = operands[0];
2121 rtx src = operands[1];
2122 rtx op2 = operands[2];
2123 rtx op3 = operands[3];
2124 rtx op4 = operands[4];
2125 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2126 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2127 rtx addr1;
2128 rtx addr2;
2129 rtx word_high;
2130 rtx word_low;
2132 addr1 = XEXP (src, 0);
2133 if (GET_CODE (addr1) == PLUS)
2134 {
2135 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2136 if (TARGET_AVOID_XFORM)
2137 {
2138 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2139 addr2 = op2;
2140 }
2141 else
2142 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2143 }
2144 else if (TARGET_AVOID_XFORM)
2145 {
2146 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2147 addr2 = op2;
2148 }
2149 else
2150 {
2151 emit_move_insn (op2, GEN_INT (4));
2152 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2153 }
2155 if (BYTES_BIG_ENDIAN)
2156 {
2157 word_high = change_address (src, SImode, addr1);
2158 word_low = change_address (src, SImode, addr2);
2159 }
2160 else
2161 {
2162 word_high = change_address (src, SImode, addr2);
2163 word_low = change_address (src, SImode, addr1);
2164 }
2166 emit_insn (gen_bswapsi2 (op3_32, word_low));
2167 emit_insn (gen_bswapsi2 (op4_32, word_high));
2168 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2169 emit_insn (gen_iordi3 (dest, dest, op4));
2170 }")
2172 (define_split
2173 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2174 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2175 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2176 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2177 (clobber (match_operand:DI 4 "" ""))]
2178 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2179 [(const_int 0)]
2180 "
2181 {
2182 rtx dest = operands[0];
2183 rtx src = operands[1];
2184 rtx op2 = operands[2];
2185 rtx op3 = operands[3];
2186 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2187 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2188 rtx addr1;
2189 rtx addr2;
2190 rtx word_high;
2191 rtx word_low;
2193 addr1 = XEXP (dest, 0);
2194 if (GET_CODE (addr1) == PLUS)
2195 {
2196 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2197 if (TARGET_AVOID_XFORM)
2198 {
2199 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2200 addr2 = op2;
2201 }
2202 else
2203 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2204 }
2205 else if (TARGET_AVOID_XFORM)
2206 {
2207 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2208 addr2 = op2;
2209 }
2210 else
2211 {
2212 emit_move_insn (op2, GEN_INT (4));
2213 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2214 }
2216 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2217 if (BYTES_BIG_ENDIAN)
2218 {
2219 word_high = change_address (dest, SImode, addr1);
2220 word_low = change_address (dest, SImode, addr2);
2221 emit_insn (gen_bswapsi2 (word_high, src_si));
2222 emit_insn (gen_bswapsi2 (word_low, op3_si));
2223 }
2224 else
2225 {
2226 word_high = change_address (dest, SImode, addr2);
2227 word_low = change_address (dest, SImode, addr1);
2228 emit_insn (gen_bswapsi2 (word_low, src_si));
2229 emit_insn (gen_bswapsi2 (word_high, op3_si));
2230 }
2231 }")
2233 (define_split
2234 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2235 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2236 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2237 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2238 (clobber (match_operand:DI 4 "" ""))]
2239 "TARGET_POWERPC64 && reload_completed"
2240 [(const_int 0)]
2241 "
2242 {
2243 rtx dest = operands[0];
2244 rtx src = operands[1];
2245 rtx op2 = operands[2];
2246 rtx op3 = operands[3];
2247 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2248 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2249 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2250 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2252 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2253 emit_insn (gen_bswapsi2 (dest_si, src_si));
2254 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2255 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2256 emit_insn (gen_iordi3 (dest, dest, op3));
2257 }")
2259 (define_insn "bswapdi2_32bit"
2260 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2261 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2262 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2263 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2264 "#"
2265 [(set_attr "length" "16,12,36")])
2267 (define_split
2268 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2269 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2270 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2271 "!TARGET_POWERPC64 && reload_completed"
2272 [(const_int 0)]
2273 "
2274 {
2275 rtx dest = operands[0];
2276 rtx src = operands[1];
2277 rtx op2 = operands[2];
2278 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2279 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2280 rtx addr1;
2281 rtx addr2;
2282 rtx word_high;
2283 rtx word_low;
2285 addr1 = XEXP (src, 0);
2286 if (GET_CODE (addr1) == PLUS)
2287 {
2288 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2289 if (TARGET_AVOID_XFORM)
2290 {
2291 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2292 addr2 = op2;
2293 }
2294 else
2295 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2296 }
2297 else if (TARGET_AVOID_XFORM)
2298 {
2299 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2300 addr2 = op2;
2301 }
2302 else
2303 {
2304 emit_move_insn (op2, GEN_INT (4));
2305 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2306 }
2308 if (BYTES_BIG_ENDIAN)
2309 {
2310 word_high = change_address (src, SImode, addr1);
2311 word_low = change_address (src, SImode, addr2);
2312 }
2313 else
2314 {
2315 word_high = change_address (src, SImode, addr2);
2316 word_low = change_address (src, SImode, addr1);
2317 }
2319 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2320 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2321 }")
2323 (define_split
2324 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2325 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2326 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2327 "!TARGET_POWERPC64 && reload_completed"
2328 [(const_int 0)]
2329 "
2330 {
2331 rtx dest = operands[0];
2332 rtx src = operands[1];
2333 rtx op2 = operands[2];
2334 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2335 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2336 rtx addr1;
2337 rtx addr2;
2338 rtx word_high;
2339 rtx word_low;
2341 addr1 = XEXP (dest, 0);
2342 if (GET_CODE (addr1) == PLUS)
2343 {
2344 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2345 if (TARGET_AVOID_XFORM)
2346 {
2347 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2348 addr2 = op2;
2349 }
2350 else
2351 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2352 }
2353 else if (TARGET_AVOID_XFORM)
2354 {
2355 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2356 addr2 = op2;
2357 }
2358 else
2359 {
2360 emit_move_insn (op2, GEN_INT (4));
2361 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2362 }
2364 if (BYTES_BIG_ENDIAN)
2365 {
2366 word_high = change_address (dest, SImode, addr1);
2367 word_low = change_address (dest, SImode, addr2);
2368 }
2369 else
2370 {
2371 word_high = change_address (dest, SImode, addr2);
2372 word_low = change_address (dest, SImode, addr1);
2373 }
2375 emit_insn (gen_bswapsi2 (word_high, src_low));
2376 emit_insn (gen_bswapsi2 (word_low, src_high));
2377 }")
2379 (define_split
2380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2381 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2382 (clobber (match_operand:SI 2 "" ""))]
2383 "!TARGET_POWERPC64 && reload_completed"
2384 [(const_int 0)]
2385 "
2386 {
2387 rtx dest = operands[0];
2388 rtx src = operands[1];
2389 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2390 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2391 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2392 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2394 emit_insn (gen_bswapsi2 (dest_high, src_low));
2395 emit_insn (gen_bswapsi2 (dest_low, src_high));
2396 }")
2398 (define_insn "mulsi3"
2399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2400 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2401 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2402 ""
2403 "@
2404 mullw %0,%1,%2
2405 mulli %0,%1,%2"
2406 [(set (attr "type")
2407 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2408 (const_string "imul3")
2409 (match_operand:SI 2 "short_cint_operand" "")
2410 (const_string "imul2")]
2411 (const_string "imul")))])
2413 (define_insn "*mulsi3_internal1"
2414 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2415 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2416 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2417 (const_int 0)))
2418 (clobber (match_scratch:SI 3 "=r,r"))]
2419 ""
2420 "@
2421 mullw. %3,%1,%2
2422 #"
2423 [(set_attr "type" "imul_compare")
2424 (set_attr "length" "4,8")])
2426 (define_split
2427 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2428 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2429 (match_operand:SI 2 "gpc_reg_operand" ""))
2430 (const_int 0)))
2431 (clobber (match_scratch:SI 3 ""))]
2432 "reload_completed"
2433 [(set (match_dup 3)
2434 (mult:SI (match_dup 1) (match_dup 2)))
2435 (set (match_dup 0)
2436 (compare:CC (match_dup 3)
2437 (const_int 0)))]
2438 "")
2440 (define_insn "*mulsi3_internal2"
2441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2442 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2443 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2444 (const_int 0)))
2445 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2446 (mult:SI (match_dup 1) (match_dup 2)))]
2447 ""
2448 "@
2449 mullw. %0,%1,%2
2450 #"
2451 [(set_attr "type" "imul_compare")
2452 (set_attr "length" "4,8")])
2454 (define_split
2455 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2456 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2457 (match_operand:SI 2 "gpc_reg_operand" ""))
2458 (const_int 0)))
2459 (set (match_operand:SI 0 "gpc_reg_operand" "")
2460 (mult:SI (match_dup 1) (match_dup 2)))]
2461 "reload_completed"
2462 [(set (match_dup 0)
2463 (mult:SI (match_dup 1) (match_dup 2)))
2464 (set (match_dup 3)
2465 (compare:CC (match_dup 0)
2466 (const_int 0)))]
2467 "")
2470 (define_insn "udiv<mode>3"
2471 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2472 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2473 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2474 ""
2475 "div<wd>u %0,%1,%2"
2476 [(set (attr "type")
2477 (cond [(match_operand:SI 0 "" "")
2478 (const_string "idiv")]
2479 (const_string "ldiv")))])
2482 ;; For powers of two we can do srai/aze for divide and then adjust for
2483 ;; modulus. If it isn't a power of two, force operands into register and do
2484 ;; a normal divide.
2485 (define_expand "div<mode>3"
2486 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2487 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2488 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2489 ""
2490 {
2491 if (GET_CODE (operands[2]) != CONST_INT
2492 || INTVAL (operands[2]) <= 0
2493 || exact_log2 (INTVAL (operands[2])) < 0)
2494 operands[2] = force_reg (<MODE>mode, operands[2]);
2495 })
2497 (define_insn "*div<mode>3"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2501 ""
2502 "div<wd> %0,%1,%2"
2503 [(set (attr "type")
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2508 (define_expand "mod<mode>3"
2509 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2510 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2511 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2512 ""
2513 "
2514 {
2515 int i;
2516 rtx temp1;
2517 rtx temp2;
2519 if (GET_CODE (operands[2]) != CONST_INT
2520 || INTVAL (operands[2]) <= 0
2521 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2522 FAIL;
2524 temp1 = gen_reg_rtx (<MODE>mode);
2525 temp2 = gen_reg_rtx (<MODE>mode);
2527 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2528 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2529 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2530 DONE;
2531 }")
2533 (define_insn ""
2534 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2535 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2536 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2537 ""
2538 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2539 [(set_attr "type" "two")
2540 (set_attr "length" "8")])
2542 (define_insn ""
2543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2544 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2545 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2546 (const_int 0)))
2547 (clobber (match_scratch:P 3 "=r,r"))]
2548 ""
2549 "@
2550 sra<wd>i %3,%1,%p2\;addze. %3,%3
2551 #"
2552 [(set_attr "type" "compare")
2553 (set_attr "length" "8,12")
2554 (set_attr "cell_micro" "not")])
2556 (define_split
2557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2558 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2559 (match_operand:GPR 2 "exact_log2_cint_operand"
2560 ""))
2561 (const_int 0)))
2562 (clobber (match_scratch:GPR 3 ""))]
2563 "reload_completed"
2564 [(set (match_dup 3)
2565 (div:<MODE> (match_dup 1) (match_dup 2)))
2566 (set (match_dup 0)
2567 (compare:CC (match_dup 3)
2568 (const_int 0)))]
2569 "")
2571 (define_insn ""
2572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2573 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2574 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2575 (const_int 0)))
2576 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2577 (div:P (match_dup 1) (match_dup 2)))]
2578 ""
2579 "@
2580 sra<wd>i %0,%1,%p2\;addze. %0,%0
2581 #"
2582 [(set_attr "type" "compare")
2583 (set_attr "length" "8,12")
2584 (set_attr "cell_micro" "not")])
2586 (define_split
2587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2588 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2589 (match_operand:GPR 2 "exact_log2_cint_operand"
2590 ""))
2591 (const_int 0)))
2592 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2593 (div:GPR (match_dup 1) (match_dup 2)))]
2594 "reload_completed"
2595 [(set (match_dup 0)
2596 (div:<MODE> (match_dup 1) (match_dup 2)))
2597 (set (match_dup 3)
2598 (compare:CC (match_dup 0)
2599 (const_int 0)))]
2600 "")
2601 \f
2602 ;; Logical instructions
2603 ;; The logical instructions are mostly combined by using match_operator,
2604 ;; but the plain AND insns are somewhat different because there is no
2605 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2606 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2608 (define_expand "andsi3"
2609 [(parallel
2610 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2611 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2612 (match_operand:SI 2 "and_operand" "")))
2613 (clobber (match_scratch:CC 3 ""))])]
2614 ""
2615 "")
2617 (define_insn "andsi3_mc"
2618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2619 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2620 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2621 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2622 "rs6000_gen_cell_microcode"
2623 "@
2624 and %0,%1,%2
2625 rlwinm %0,%1,0,%m2,%M2
2626 andi. %0,%1,%b2
2627 andis. %0,%1,%u2"
2628 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2630 (define_insn "andsi3_nomc"
2631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2633 (match_operand:SI 2 "and_operand" "?r,T")))
2634 (clobber (match_scratch:CC 3 "=X,X"))]
2635 "!rs6000_gen_cell_microcode"
2636 "@
2637 and %0,%1,%2
2638 rlwinm %0,%1,0,%m2,%M2")
2640 (define_insn "andsi3_internal0_nomc"
2641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2642 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2643 (match_operand:SI 2 "and_operand" "?r,T")))]
2644 "!rs6000_gen_cell_microcode"
2645 "@
2646 and %0,%1,%2
2647 rlwinm %0,%1,0,%m2,%M2")
2650 ;; Note to set cr's other than cr0 we do the and immediate and then
2651 ;; the test again -- this avoids a mfcr which on the higher end
2652 ;; machines causes an execution serialization
2654 (define_insn "*andsi3_internal2_mc"
2655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2656 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2657 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2658 (const_int 0)))
2659 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2660 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2661 "TARGET_32BIT && rs6000_gen_cell_microcode"
2662 "@
2663 and. %3,%1,%2
2664 andi. %3,%1,%b2
2665 andis. %3,%1,%u2
2666 rlwinm. %3,%1,0,%m2,%M2
2667 #
2668 #
2669 #
2670 #"
2671 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2672 compare,compare,compare,compare")
2673 (set_attr "length" "4,4,4,4,8,8,8,8")])
2675 (define_insn "*andsi3_internal3_mc"
2676 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2677 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2678 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2679 (const_int 0)))
2680 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2681 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2682 "TARGET_64BIT && rs6000_gen_cell_microcode"
2683 "@
2684 #
2685 andi. %3,%1,%b2
2686 andis. %3,%1,%u2
2687 rlwinm. %3,%1,0,%m2,%M2
2688 #
2689 #
2690 #
2691 #"
2692 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2693 compare,compare,compare")
2694 (set_attr "length" "8,4,4,4,8,8,8,8")])
2696 (define_split
2697 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2698 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2699 (match_operand:GPR 2 "and_operand" ""))
2700 (const_int 0)))
2701 (clobber (match_scratch:GPR 3 ""))
2702 (clobber (match_scratch:CC 4 ""))]
2703 "reload_completed"
2704 [(parallel [(set (match_dup 3)
2705 (and:<MODE> (match_dup 1)
2706 (match_dup 2)))
2707 (clobber (match_dup 4))])
2708 (set (match_dup 0)
2709 (compare:CC (match_dup 3)
2710 (const_int 0)))]
2711 "")
2713 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2714 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2716 (define_split
2717 [(set (match_operand:CC 0 "cc_reg_operand" "")
2718 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "gpc_reg_operand" ""))
2720 (const_int 0)))
2721 (clobber (match_scratch:SI 3 ""))
2722 (clobber (match_scratch:CC 4 ""))]
2723 "TARGET_POWERPC64 && reload_completed"
2724 [(parallel [(set (match_dup 3)
2725 (and:SI (match_dup 1)
2726 (match_dup 2)))
2727 (clobber (match_dup 4))])
2728 (set (match_dup 0)
2729 (compare:CC (match_dup 3)
2730 (const_int 0)))]
2731 "")
2733 (define_insn "*andsi3_internal4"
2734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2735 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2736 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2737 (const_int 0)))
2738 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2739 (and:SI (match_dup 1)
2740 (match_dup 2)))
2741 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2742 "TARGET_32BIT && rs6000_gen_cell_microcode"
2743 "@
2744 and. %0,%1,%2
2745 andi. %0,%1,%b2
2746 andis. %0,%1,%u2
2747 rlwinm. %0,%1,0,%m2,%M2
2748 #
2749 #
2750 #
2751 #"
2752 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2753 compare,compare,compare,compare")
2754 (set_attr "length" "4,4,4,4,8,8,8,8")])
2756 (define_insn "*andsi3_internal5_mc"
2757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2758 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2759 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2760 (const_int 0)))
2761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2762 (and:SI (match_dup 1)
2763 (match_dup 2)))
2764 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2765 "TARGET_64BIT && rs6000_gen_cell_microcode"
2766 "@
2767 #
2768 andi. %0,%1,%b2
2769 andis. %0,%1,%u2
2770 rlwinm. %0,%1,0,%m2,%M2
2771 #
2772 #
2773 #
2774 #"
2775 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2776 compare,compare,compare")
2777 (set_attr "length" "8,4,4,4,8,8,8,8")])
2779 (define_split
2780 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2781 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2782 (match_operand:SI 2 "and_operand" ""))
2783 (const_int 0)))
2784 (set (match_operand:SI 0 "gpc_reg_operand" "")
2785 (and:SI (match_dup 1)
2786 (match_dup 2)))
2787 (clobber (match_scratch:CC 4 ""))]
2788 "reload_completed"
2789 [(parallel [(set (match_dup 0)
2790 (and:SI (match_dup 1)
2791 (match_dup 2)))
2792 (clobber (match_dup 4))])
2793 (set (match_dup 3)
2794 (compare:CC (match_dup 0)
2795 (const_int 0)))]
2796 "")
2798 (define_split
2799 [(set (match_operand:CC 3 "cc_reg_operand" "")
2800 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2801 (match_operand:SI 2 "gpc_reg_operand" ""))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "")
2804 (and:SI (match_dup 1)
2805 (match_dup 2)))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 0)
2809 (and:SI (match_dup 1)
2810 (match_dup 2)))
2811 (clobber (match_dup 4))])
2812 (set (match_dup 3)
2813 (compare:CC (match_dup 0)
2814 (const_int 0)))]
2815 "")
2817 ;; Handle the PowerPC64 rlwinm corner case
2819 (define_insn_and_split "*andsi3_internal6"
2820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2821 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2822 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2823 "TARGET_POWERPC64"
2824 "#"
2825 "TARGET_POWERPC64"
2826 [(set (match_dup 0)
2827 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2828 (match_dup 4)))
2829 (set (match_dup 0)
2830 (rotate:SI (match_dup 0) (match_dup 5)))]
2831 "
2832 {
2833 int mb = extract_MB (operands[2]);
2834 int me = extract_ME (operands[2]);
2835 operands[3] = GEN_INT (me + 1);
2836 operands[5] = GEN_INT (32 - (me + 1));
2837 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2838 }"
2839 [(set_attr "length" "8")])
2841 (define_expand "iorsi3"
2842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2843 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2844 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2845 ""
2846 "
2847 {
2848 if (GET_CODE (operands[2]) == CONST_INT
2849 && ! logical_operand (operands[2], SImode))
2850 {
2851 HOST_WIDE_INT value = INTVAL (operands[2]);
2852 rtx tmp = ((!can_create_pseudo_p ()
2853 || rtx_equal_p (operands[0], operands[1]))
2854 ? operands[0] : gen_reg_rtx (SImode));
2856 emit_insn (gen_iorsi3 (tmp, operands[1],
2857 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2858 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2859 DONE;
2860 }
2861 }")
2863 (define_expand "xorsi3"
2864 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2865 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2866 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2867 ""
2868 "
2869 {
2870 if (GET_CODE (operands[2]) == CONST_INT
2871 && ! logical_operand (operands[2], SImode))
2872 {
2873 HOST_WIDE_INT value = INTVAL (operands[2]);
2874 rtx tmp = ((!can_create_pseudo_p ()
2875 || rtx_equal_p (operands[0], operands[1]))
2876 ? operands[0] : gen_reg_rtx (SImode));
2878 emit_insn (gen_xorsi3 (tmp, operands[1],
2879 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2880 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2881 DONE;
2882 }
2883 }")
2885 (define_insn "*boolsi3_internal1"
2886 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2887 (match_operator:SI 3 "boolean_or_operator"
2888 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2889 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2890 ""
2891 "@
2892 %q3 %0,%1,%2
2893 %q3i %0,%1,%b2
2894 %q3is %0,%1,%u2")
2896 (define_insn "*boolsi3_internal2"
2897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2898 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2899 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2900 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2901 (const_int 0)))
2902 (clobber (match_scratch:SI 3 "=r,r"))]
2903 "TARGET_32BIT"
2904 "@
2905 %q4. %3,%1,%2
2906 #"
2907 [(set_attr "type" "fast_compare,compare")
2908 (set_attr "length" "4,8")])
2910 (define_split
2911 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2912 (compare:CC (match_operator:SI 4 "boolean_operator"
2913 [(match_operand:SI 1 "gpc_reg_operand" "")
2914 (match_operand:SI 2 "gpc_reg_operand" "")])
2915 (const_int 0)))
2916 (clobber (match_scratch:SI 3 ""))]
2917 "TARGET_32BIT && reload_completed"
2918 [(set (match_dup 3) (match_dup 4))
2919 (set (match_dup 0)
2920 (compare:CC (match_dup 3)
2921 (const_int 0)))]
2922 "")
2924 (define_insn "*boolsi3_internal3"
2925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2926 (compare:CC (match_operator:SI 4 "boolean_operator"
2927 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2928 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2929 (const_int 0)))
2930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2931 (match_dup 4))]
2932 "TARGET_32BIT"
2933 "@
2934 %q4. %0,%1,%2
2935 #"
2936 [(set_attr "type" "fast_compare,compare")
2937 (set_attr "length" "4,8")])
2939 (define_split
2940 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2941 (compare:CC (match_operator:SI 4 "boolean_operator"
2942 [(match_operand:SI 1 "gpc_reg_operand" "")
2943 (match_operand:SI 2 "gpc_reg_operand" "")])
2944 (const_int 0)))
2945 (set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (match_dup 4))]
2947 "TARGET_32BIT && reload_completed"
2948 [(set (match_dup 0) (match_dup 4))
2949 (set (match_dup 3)
2950 (compare:CC (match_dup 0)
2951 (const_int 0)))]
2952 "")
2954 ;; Split a logical operation that we can't do in one insn into two insns,
2955 ;; each of which does one 16-bit part. This is used by combine.
2957 (define_split
2958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (match_operator:SI 3 "boolean_or_operator"
2960 [(match_operand:SI 1 "gpc_reg_operand" "")
2961 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2962 ""
2963 [(set (match_dup 0) (match_dup 4))
2964 (set (match_dup 0) (match_dup 5))]
2965 "
2966 {
2967 rtx i;
2968 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2969 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2970 operands[1], i);
2971 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2972 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2973 operands[0], i);
2974 }")
2976 (define_insn "*boolcsi3_internal1"
2977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2978 (match_operator:SI 3 "boolean_operator"
2979 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2980 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2981 ""
2982 "%q3 %0,%2,%1")
2984 (define_insn "*boolcsi3_internal2"
2985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2986 (compare:CC (match_operator:SI 4 "boolean_operator"
2987 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2988 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2989 (const_int 0)))
2990 (clobber (match_scratch:SI 3 "=r,r"))]
2991 "TARGET_32BIT"
2992 "@
2993 %q4. %3,%2,%1
2994 #"
2995 [(set_attr "type" "compare")
2996 (set_attr "length" "4,8")])
2998 (define_split
2999 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3000 (compare:CC (match_operator:SI 4 "boolean_operator"
3001 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3002 (match_operand:SI 2 "gpc_reg_operand" "")])
3003 (const_int 0)))
3004 (clobber (match_scratch:SI 3 ""))]
3005 "TARGET_32BIT && reload_completed"
3006 [(set (match_dup 3) (match_dup 4))
3007 (set (match_dup 0)
3008 (compare:CC (match_dup 3)
3009 (const_int 0)))]
3010 "")
3012 (define_insn "*boolcsi3_internal3"
3013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3014 (compare:CC (match_operator:SI 4 "boolean_operator"
3015 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3016 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3017 (const_int 0)))
3018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3019 (match_dup 4))]
3020 "TARGET_32BIT"
3021 "@
3022 %q4. %0,%2,%1
3023 #"
3024 [(set_attr "type" "compare")
3025 (set_attr "length" "4,8")])
3027 (define_split
3028 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3029 (compare:CC (match_operator:SI 4 "boolean_operator"
3030 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3031 (match_operand:SI 2 "gpc_reg_operand" "")])
3032 (const_int 0)))
3033 (set (match_operand:SI 0 "gpc_reg_operand" "")
3034 (match_dup 4))]
3035 "TARGET_32BIT && reload_completed"
3036 [(set (match_dup 0) (match_dup 4))
3037 (set (match_dup 3)
3038 (compare:CC (match_dup 0)
3039 (const_int 0)))]
3040 "")
3042 (define_insn "*boolccsi3_internal1"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (match_operator:SI 3 "boolean_operator"
3045 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3046 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3047 ""
3048 "%q3 %0,%1,%2")
3050 (define_insn "*boolccsi3_internal2"
3051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3052 (compare:CC (match_operator:SI 4 "boolean_operator"
3053 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3054 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3055 (const_int 0)))
3056 (clobber (match_scratch:SI 3 "=r,r"))]
3057 "TARGET_32BIT"
3058 "@
3059 %q4. %3,%1,%2
3060 #"
3061 [(set_attr "type" "fast_compare,compare")
3062 (set_attr "length" "4,8")])
3064 (define_split
3065 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3068 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3069 (const_int 0)))
3070 (clobber (match_scratch:SI 3 ""))]
3071 "TARGET_32BIT && reload_completed"
3072 [(set (match_dup 3) (match_dup 4))
3073 (set (match_dup 0)
3074 (compare:CC (match_dup 3)
3075 (const_int 0)))]
3076 "")
3078 (define_insn "*boolccsi3_internal3"
3079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3082 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3083 (const_int 0)))
3084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3085 (match_dup 4))]
3086 "TARGET_32BIT"
3087 "@
3088 %q4. %0,%1,%2
3089 #"
3090 [(set_attr "type" "fast_compare,compare")
3091 (set_attr "length" "4,8")])
3093 (define_split
3094 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3097 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3098 (const_int 0)))
3099 (set (match_operand:SI 0 "gpc_reg_operand" "")
3100 (match_dup 4))]
3101 "TARGET_32BIT && reload_completed"
3102 [(set (match_dup 0) (match_dup 4))
3103 (set (match_dup 3)
3104 (compare:CC (match_dup 0)
3105 (const_int 0)))]
3106 "")
3107 \f
3108 ;; Rotate and shift insns, in all their variants. These support shifts,
3109 ;; field inserts and extracts, and various combinations thereof.
3110 (define_expand "insv"
3111 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3112 (match_operand:SI 1 "const_int_operand" "")
3113 (match_operand:SI 2 "const_int_operand" ""))
3114 (match_operand 3 "gpc_reg_operand" ""))]
3115 ""
3116 "
3117 {
3118 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3119 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3120 compiler if the address of the structure is taken later. Likewise, do
3121 not handle invalid E500 subregs. */
3122 if (GET_CODE (operands[0]) == SUBREG
3123 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3124 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3125 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3126 FAIL;
3128 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3129 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3130 else
3131 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3132 DONE;
3133 }")
3135 (define_insn "insvsi"
3136 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3137 (match_operand:SI 1 "const_int_operand" "i")
3138 (match_operand:SI 2 "const_int_operand" "i"))
3139 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3140 ""
3141 "*
3142 {
3143 int start = INTVAL (operands[2]) & 31;
3144 int size = INTVAL (operands[1]) & 31;
3146 operands[4] = GEN_INT (32 - start - size);
3147 operands[1] = GEN_INT (start + size - 1);
3148 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3149 }"
3150 [(set_attr "type" "insert_word")])
3152 (define_insn "*insvsi_internal1"
3153 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3154 (match_operand:SI 1 "const_int_operand" "i")
3155 (match_operand:SI 2 "const_int_operand" "i"))
3156 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3157 (match_operand:SI 4 "const_int_operand" "i")))]
3158 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3159 "*
3160 {
3161 int shift = INTVAL (operands[4]) & 31;
3162 int start = INTVAL (operands[2]) & 31;
3163 int size = INTVAL (operands[1]) & 31;
3165 operands[4] = GEN_INT (shift - start - size);
3166 operands[1] = GEN_INT (start + size - 1);
3167 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3168 }"
3169 [(set_attr "type" "insert_word")])
3171 (define_insn "*insvsi_internal2"
3172 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3173 (match_operand:SI 1 "const_int_operand" "i")
3174 (match_operand:SI 2 "const_int_operand" "i"))
3175 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3176 (match_operand:SI 4 "const_int_operand" "i")))]
3177 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3178 "*
3179 {
3180 int shift = INTVAL (operands[4]) & 31;
3181 int start = INTVAL (operands[2]) & 31;
3182 int size = INTVAL (operands[1]) & 31;
3184 operands[4] = GEN_INT (32 - shift - start - size);
3185 operands[1] = GEN_INT (start + size - 1);
3186 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3187 }"
3188 [(set_attr "type" "insert_word")])
3190 (define_insn "*insvsi_internal3"
3191 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3192 (match_operand:SI 1 "const_int_operand" "i")
3193 (match_operand:SI 2 "const_int_operand" "i"))
3194 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3195 (match_operand:SI 4 "const_int_operand" "i")))]
3196 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3197 "*
3198 {
3199 int shift = INTVAL (operands[4]) & 31;
3200 int start = INTVAL (operands[2]) & 31;
3201 int size = INTVAL (operands[1]) & 31;
3203 operands[4] = GEN_INT (32 - shift - start - size);
3204 operands[1] = GEN_INT (start + size - 1);
3205 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3206 }"
3207 [(set_attr "type" "insert_word")])
3209 (define_insn "*insvsi_internal4"
3210 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3211 (match_operand:SI 1 "const_int_operand" "i")
3212 (match_operand:SI 2 "const_int_operand" "i"))
3213 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3214 (match_operand:SI 4 "const_int_operand" "i")
3215 (match_operand:SI 5 "const_int_operand" "i")))]
3216 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3217 "*
3218 {
3219 int extract_start = INTVAL (operands[5]) & 31;
3220 int extract_size = INTVAL (operands[4]) & 31;
3221 int insert_start = INTVAL (operands[2]) & 31;
3222 int insert_size = INTVAL (operands[1]) & 31;
3224 /* Align extract field with insert field */
3225 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3226 operands[1] = GEN_INT (insert_start + insert_size - 1);
3227 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3228 }"
3229 [(set_attr "type" "insert_word")])
3231 ;; combine patterns for rlwimi
3232 (define_insn "*insvsi_internal5"
3233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3234 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3235 (match_operand:SI 1 "mask_operand" "i"))
3236 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3237 (match_operand:SI 2 "const_int_operand" "i"))
3238 (match_operand:SI 5 "mask_operand" "i"))))]
3239 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3240 "*
3241 {
3242 int me = extract_ME(operands[5]);
3243 int mb = extract_MB(operands[5]);
3244 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3245 operands[2] = GEN_INT(mb);
3246 operands[1] = GEN_INT(me);
3247 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3248 }"
3249 [(set_attr "type" "insert_word")])
3251 (define_insn "*insvsi_internal6"
3252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3253 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3254 (match_operand:SI 2 "const_int_operand" "i"))
3255 (match_operand:SI 5 "mask_operand" "i"))
3256 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3257 (match_operand:SI 1 "mask_operand" "i"))))]
3258 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3259 "*
3260 {
3261 int me = extract_ME(operands[5]);
3262 int mb = extract_MB(operands[5]);
3263 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3264 operands[2] = GEN_INT(mb);
3265 operands[1] = GEN_INT(me);
3266 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3267 }"
3268 [(set_attr "type" "insert_word")])
3270 (define_insn "insvdi"
3271 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3272 (match_operand:SI 1 "const_int_operand" "i")
3273 (match_operand:SI 2 "const_int_operand" "i"))
3274 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3275 "TARGET_POWERPC64"
3276 "*
3277 {
3278 int start = INTVAL (operands[2]) & 63;
3279 int size = INTVAL (operands[1]) & 63;
3281 operands[1] = GEN_INT (64 - start - size);
3282 return \"rldimi %0,%3,%H1,%H2\";
3283 }"
3284 [(set_attr "type" "insert_dword")])
3286 (define_insn "*insvdi_internal2"
3287 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3288 (match_operand:SI 1 "const_int_operand" "i")
3289 (match_operand:SI 2 "const_int_operand" "i"))
3290 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3291 (match_operand:SI 4 "const_int_operand" "i")))]
3292 "TARGET_POWERPC64
3293 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3294 "*
3295 {
3296 int shift = INTVAL (operands[4]) & 63;
3297 int start = (INTVAL (operands[2]) & 63) - 32;
3298 int size = INTVAL (operands[1]) & 63;
3300 operands[4] = GEN_INT (64 - shift - start - size);
3301 operands[2] = GEN_INT (start);
3302 operands[1] = GEN_INT (start + size - 1);
3303 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3304 }")
3306 (define_insn "*insvdi_internal3"
3307 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3308 (match_operand:SI 1 "const_int_operand" "i")
3309 (match_operand:SI 2 "const_int_operand" "i"))
3310 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3311 (match_operand:SI 4 "const_int_operand" "i")))]
3312 "TARGET_POWERPC64
3313 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3314 "*
3315 {
3316 int shift = INTVAL (operands[4]) & 63;
3317 int start = (INTVAL (operands[2]) & 63) - 32;
3318 int size = INTVAL (operands[1]) & 63;
3320 operands[4] = GEN_INT (64 - shift - start - size);
3321 operands[2] = GEN_INT (start);
3322 operands[1] = GEN_INT (start + size - 1);
3323 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3324 }")
3326 (define_expand "extzv"
3327 [(set (match_operand 0 "gpc_reg_operand" "")
3328 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3329 (match_operand:SI 2 "const_int_operand" "")
3330 (match_operand:SI 3 "const_int_operand" "")))]
3331 ""
3332 "
3333 {
3334 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3335 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3336 compiler if the address of the structure is taken later. */
3337 if (GET_CODE (operands[0]) == SUBREG
3338 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3339 FAIL;
3341 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3342 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3343 else
3344 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3345 DONE;
3346 }")
3348 (define_insn "extzvsi"
3349 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3350 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3351 (match_operand:SI 2 "const_int_operand" "i")
3352 (match_operand:SI 3 "const_int_operand" "i")))]
3353 ""
3354 "*
3355 {
3356 int start = INTVAL (operands[3]) & 31;
3357 int size = INTVAL (operands[2]) & 31;
3359 if (start + size >= 32)
3360 operands[3] = const0_rtx;
3361 else
3362 operands[3] = GEN_INT (start + size);
3363 return \"rlwinm %0,%1,%3,%s2,31\";
3364 }")
3366 (define_insn "*extzvsi_internal1"
3367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3368 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3369 (match_operand:SI 2 "const_int_operand" "i,i")
3370 (match_operand:SI 3 "const_int_operand" "i,i"))
3371 (const_int 0)))
3372 (clobber (match_scratch:SI 4 "=r,r"))]
3373 ""
3374 "*
3375 {
3376 int start = INTVAL (operands[3]) & 31;
3377 int size = INTVAL (operands[2]) & 31;
3379 /* Force split for non-cc0 compare. */
3380 if (which_alternative == 1)
3381 return \"#\";
3383 /* If the bit-field being tested fits in the upper or lower half of a
3384 word, it is possible to use andiu. or andil. to test it. This is
3385 useful because the condition register set-use delay is smaller for
3386 andi[ul]. than for rlinm. This doesn't work when the starting bit
3387 position is 0 because the LT and GT bits may be set wrong. */
3389 if ((start > 0 && start + size <= 16) || start >= 16)
3390 {
3391 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3392 - (1 << (16 - (start & 15) - size))));
3393 if (start < 16)
3394 return \"andis. %4,%1,%3\";
3395 else
3396 return \"andi. %4,%1,%3\";
3397 }
3399 if (start + size >= 32)
3400 operands[3] = const0_rtx;
3401 else
3402 operands[3] = GEN_INT (start + size);
3403 return \"rlwinm. %4,%1,%3,%s2,31\";
3404 }"
3405 [(set_attr "type" "delayed_compare")
3406 (set_attr "length" "4,8")])
3408 (define_split
3409 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3410 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3411 (match_operand:SI 2 "const_int_operand" "")
3412 (match_operand:SI 3 "const_int_operand" ""))
3413 (const_int 0)))
3414 (clobber (match_scratch:SI 4 ""))]
3415 "reload_completed"
3416 [(set (match_dup 4)
3417 (zero_extract:SI (match_dup 1) (match_dup 2)
3418 (match_dup 3)))
3419 (set (match_dup 0)
3420 (compare:CC (match_dup 4)
3421 (const_int 0)))]
3422 "")
3424 (define_insn "*extzvsi_internal2"
3425 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3426 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3427 (match_operand:SI 2 "const_int_operand" "i,i")
3428 (match_operand:SI 3 "const_int_operand" "i,i"))
3429 (const_int 0)))
3430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3431 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3432 ""
3433 "*
3434 {
3435 int start = INTVAL (operands[3]) & 31;
3436 int size = INTVAL (operands[2]) & 31;
3438 /* Force split for non-cc0 compare. */
3439 if (which_alternative == 1)
3440 return \"#\";
3442 /* Since we are using the output value, we can't ignore any need for
3443 a shift. The bit-field must end at the LSB. */
3444 if (start >= 16 && start + size == 32)
3445 {
3446 operands[3] = GEN_INT ((1 << size) - 1);
3447 return \"andi. %0,%1,%3\";
3448 }
3450 if (start + size >= 32)
3451 operands[3] = const0_rtx;
3452 else
3453 operands[3] = GEN_INT (start + size);
3454 return \"rlwinm. %0,%1,%3,%s2,31\";
3455 }"
3456 [(set_attr "type" "delayed_compare")
3457 (set_attr "length" "4,8")])
3459 (define_split
3460 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3461 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3462 (match_operand:SI 2 "const_int_operand" "")
3463 (match_operand:SI 3 "const_int_operand" ""))
3464 (const_int 0)))
3465 (set (match_operand:SI 0 "gpc_reg_operand" "")
3466 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3467 "reload_completed"
3468 [(set (match_dup 0)
3469 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3470 (set (match_dup 4)
3471 (compare:CC (match_dup 0)
3472 (const_int 0)))]
3473 "")
3475 (define_insn "extzvdi"
3476 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3477 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3478 (match_operand:SI 2 "const_int_operand" "i")
3479 (match_operand:SI 3 "const_int_operand" "i")))]
3480 "TARGET_POWERPC64"
3481 "*
3482 {
3483 int start = INTVAL (operands[3]) & 63;
3484 int size = INTVAL (operands[2]) & 63;
3486 if (start + size >= 64)
3487 operands[3] = const0_rtx;
3488 else
3489 operands[3] = GEN_INT (start + size);
3490 operands[2] = GEN_INT (64 - size);
3491 return \"rldicl %0,%1,%3,%2\";
3492 }")
3494 (define_insn "*extzvdi_internal1"
3495 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3496 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3497 (match_operand:SI 2 "const_int_operand" "i")
3498 (match_operand:SI 3 "const_int_operand" "i"))
3499 (const_int 0)))
3500 (clobber (match_scratch:DI 4 "=r"))]
3501 "TARGET_64BIT && rs6000_gen_cell_microcode"
3502 "*
3503 {
3504 int start = INTVAL (operands[3]) & 63;
3505 int size = INTVAL (operands[2]) & 63;
3507 if (start + size >= 64)
3508 operands[3] = const0_rtx;
3509 else
3510 operands[3] = GEN_INT (start + size);
3511 operands[2] = GEN_INT (64 - size);
3512 return \"rldicl. %4,%1,%3,%2\";
3513 }"
3514 [(set_attr "type" "compare")])
3516 (define_insn "*extzvdi_internal2"
3517 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3518 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3519 (match_operand:SI 2 "const_int_operand" "i")
3520 (match_operand:SI 3 "const_int_operand" "i"))
3521 (const_int 0)))
3522 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3523 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3524 "TARGET_64BIT && rs6000_gen_cell_microcode"
3525 "*
3526 {
3527 int start = INTVAL (operands[3]) & 63;
3528 int size = INTVAL (operands[2]) & 63;
3530 if (start + size >= 64)
3531 operands[3] = const0_rtx;
3532 else
3533 operands[3] = GEN_INT (start + size);
3534 operands[2] = GEN_INT (64 - size);
3535 return \"rldicl. %0,%1,%3,%2\";
3536 }"
3537 [(set_attr "type" "compare")])
3539 (define_insn "rotlsi3"
3540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3541 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3542 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3543 ""
3544 "@
3545 rlwnm %0,%1,%2,0xffffffff
3546 rlwinm %0,%1,%h2,0xffffffff"
3547 [(set_attr "type" "var_shift_rotate,integer")])
3549 (define_insn "*rotlsi3_64"
3550 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3551 (zero_extend:DI
3552 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3553 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3554 "TARGET_64BIT"
3555 "@
3556 rlwnm %0,%1,%2,0xffffffff
3557 rlwinm %0,%1,%h2,0xffffffff"
3558 [(set_attr "type" "var_shift_rotate,integer")])
3560 (define_insn "*rotlsi3_internal2"
3561 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3562 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3563 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3564 (const_int 0)))
3565 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3566 ""
3567 "@
3568 rlwnm. %3,%1,%2,0xffffffff
3569 rlwinm. %3,%1,%h2,0xffffffff
3570 #
3571 #"
3572 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3573 (set_attr "length" "4,4,8,8")])
3575 (define_split
3576 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3577 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3578 (match_operand:SI 2 "reg_or_cint_operand" ""))
3579 (const_int 0)))
3580 (clobber (match_scratch:SI 3 ""))]
3581 "reload_completed"
3582 [(set (match_dup 3)
3583 (rotate:SI (match_dup 1) (match_dup 2)))
3584 (set (match_dup 0)
3585 (compare:CC (match_dup 3)
3586 (const_int 0)))]
3587 "")
3589 (define_insn "*rotlsi3_internal3"
3590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3591 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3592 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3593 (const_int 0)))
3594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3595 (rotate:SI (match_dup 1) (match_dup 2)))]
3596 ""
3597 "@
3598 rlwnm. %0,%1,%2,0xffffffff
3599 rlwinm. %0,%1,%h2,0xffffffff
3600 #
3601 #"
3602 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3603 (set_attr "length" "4,4,8,8")])
3605 (define_split
3606 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3607 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3608 (match_operand:SI 2 "reg_or_cint_operand" ""))
3609 (const_int 0)))
3610 (set (match_operand:SI 0 "gpc_reg_operand" "")
3611 (rotate:SI (match_dup 1) (match_dup 2)))]
3612 "reload_completed"
3613 [(set (match_dup 0)
3614 (rotate:SI (match_dup 1) (match_dup 2)))
3615 (set (match_dup 3)
3616 (compare:CC (match_dup 0)
3617 (const_int 0)))]
3618 "")
3620 (define_insn "*rotlsi3_internal4"
3621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3622 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3623 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3624 (match_operand:SI 3 "mask_operand" "n,n")))]
3625 ""
3626 "@
3627 rlwnm %0,%1,%2,%m3,%M3
3628 rlwinm %0,%1,%h2,%m3,%M3"
3629 [(set_attr "type" "var_shift_rotate,integer")])
3631 (define_insn "*rotlsi3_internal5"
3632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3633 (compare:CC (and:SI
3634 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3635 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3636 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3637 (const_int 0)))
3638 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3639 ""
3640 "@
3641 rlwnm. %4,%1,%2,%m3,%M3
3642 rlwinm. %4,%1,%h2,%m3,%M3
3643 #
3644 #"
3645 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3646 (set_attr "length" "4,4,8,8")])
3648 (define_split
3649 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3650 (compare:CC (and:SI
3651 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3652 (match_operand:SI 2 "reg_or_cint_operand" ""))
3653 (match_operand:SI 3 "mask_operand" ""))
3654 (const_int 0)))
3655 (clobber (match_scratch:SI 4 ""))]
3656 "reload_completed"
3657 [(set (match_dup 4)
3658 (and:SI (rotate:SI (match_dup 1)
3659 (match_dup 2))
3660 (match_dup 3)))
3661 (set (match_dup 0)
3662 (compare:CC (match_dup 4)
3663 (const_int 0)))]
3664 "")
3666 (define_insn "*rotlsi3_internal6"
3667 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3668 (compare:CC (and:SI
3669 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3670 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3671 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3672 (const_int 0)))
3673 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3674 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3675 ""
3676 "@
3677 rlwnm. %0,%1,%2,%m3,%M3
3678 rlwinm. %0,%1,%h2,%m3,%M3
3679 #
3680 #"
3681 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3682 (set_attr "length" "4,4,8,8")])
3684 (define_split
3685 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3686 (compare:CC (and:SI
3687 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3688 (match_operand:SI 2 "reg_or_cint_operand" ""))
3689 (match_operand:SI 3 "mask_operand" ""))
3690 (const_int 0)))
3691 (set (match_operand:SI 0 "gpc_reg_operand" "")
3692 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3693 "reload_completed"
3694 [(set (match_dup 0)
3695 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3696 (set (match_dup 4)
3697 (compare:CC (match_dup 0)
3698 (const_int 0)))]
3699 "")
3701 (define_insn "*rotlsi3_internal7"
3702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3703 (zero_extend:SI
3704 (subreg:QI
3705 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3706 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3707 ""
3708 "rlw%I2nm %0,%1,%h2,0xff"
3709 [(set (attr "cell_micro")
3710 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3711 (const_string "not")
3712 (const_string "always")))])
3714 (define_insn "*rotlsi3_internal8"
3715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3716 (compare:CC (zero_extend:SI
3717 (subreg:QI
3718 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3719 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3720 (const_int 0)))
3721 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3722 ""
3723 "@
3724 rlwnm. %3,%1,%2,0xff
3725 rlwinm. %3,%1,%h2,0xff
3726 #
3727 #"
3728 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3729 (set_attr "length" "4,4,8,8")])
3731 (define_split
3732 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3733 (compare:CC (zero_extend:SI
3734 (subreg:QI
3735 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3736 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3737 (const_int 0)))
3738 (clobber (match_scratch:SI 3 ""))]
3739 "reload_completed"
3740 [(set (match_dup 3)
3741 (zero_extend:SI (subreg:QI
3742 (rotate:SI (match_dup 1)
3743 (match_dup 2)) 0)))
3744 (set (match_dup 0)
3745 (compare:CC (match_dup 3)
3746 (const_int 0)))]
3747 "")
3749 (define_insn "*rotlsi3_internal9"
3750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3751 (compare:CC (zero_extend:SI
3752 (subreg:QI
3753 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3754 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3755 (const_int 0)))
3756 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3757 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3758 ""
3759 "@
3760 rlwnm. %0,%1,%2,0xff
3761 rlwinm. %0,%1,%h2,0xff
3762 #
3763 #"
3764 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3765 (set_attr "length" "4,4,8,8")])
3767 (define_split
3768 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3769 (compare:CC (zero_extend:SI
3770 (subreg:QI
3771 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3773 (const_int 0)))
3774 (set (match_operand:SI 0 "gpc_reg_operand" "")
3775 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3776 "reload_completed"
3777 [(set (match_dup 0)
3778 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3779 (set (match_dup 3)
3780 (compare:CC (match_dup 0)
3781 (const_int 0)))]
3782 "")
3784 (define_insn "*rotlsi3_internal10"
3785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3786 (zero_extend:SI
3787 (subreg:HI
3788 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3789 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
3790 ""
3791 "@
3792 rlwnm %0,%1,%2,0xffff
3793 rlwinm %0,%1,%h2,0xffff"
3794 [(set_attr "type" "var_shift_rotate,integer")])
3797 (define_insn "*rotlsi3_internal11"
3798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3799 (compare:CC (zero_extend:SI
3800 (subreg:HI
3801 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3802 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3803 (const_int 0)))
3804 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3805 ""
3806 "@
3807 rlwnm. %3,%1,%2,0xffff
3808 rlwinm. %3,%1,%h2,0xffff
3809 #
3810 #"
3811 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3812 (set_attr "length" "4,4,8,8")])
3814 (define_split
3815 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3816 (compare:CC (zero_extend:SI
3817 (subreg:HI
3818 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3819 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3820 (const_int 0)))
3821 (clobber (match_scratch:SI 3 ""))]
3822 "reload_completed"
3823 [(set (match_dup 3)
3824 (zero_extend:SI (subreg:HI
3825 (rotate:SI (match_dup 1)
3826 (match_dup 2)) 0)))
3827 (set (match_dup 0)
3828 (compare:CC (match_dup 3)
3829 (const_int 0)))]
3830 "")
3832 (define_insn "*rotlsi3_internal12"
3833 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3834 (compare:CC (zero_extend:SI
3835 (subreg:HI
3836 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3837 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3838 (const_int 0)))
3839 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3840 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3841 ""
3842 "@
3843 rlwnm. %0,%1,%2,0xffff
3844 rlwinm. %0,%1,%h2,0xffff
3845 #
3846 #"
3847 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3848 (set_attr "length" "4,4,8,8")])
3850 (define_split
3851 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3852 (compare:CC (zero_extend:SI
3853 (subreg:HI
3854 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3855 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3856 (const_int 0)))
3857 (set (match_operand:SI 0 "gpc_reg_operand" "")
3858 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3859 "reload_completed"
3860 [(set (match_dup 0)
3861 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3862 (set (match_dup 3)
3863 (compare:CC (match_dup 0)
3864 (const_int 0)))]
3865 "")
3867 (define_insn "ashlsi3"
3868 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3869 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3870 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3871 ""
3872 "@
3873 slw %0,%1,%2
3874 slwi %0,%1,%h2"
3875 [(set_attr "type" "var_shift_rotate,shift")])
3877 (define_insn "*ashlsi3_64"
3878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3879 (zero_extend:DI
3880 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3882 "TARGET_POWERPC64"
3883 "@
3884 slw %0,%1,%2
3885 slwi %0,%1,%h2"
3886 [(set_attr "type" "var_shift_rotate,shift")])
3888 (define_insn ""
3889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3890 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3891 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3892 (const_int 0)))
3893 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3894 "TARGET_32BIT"
3895 "@
3896 slw. %3,%1,%2
3897 slwi. %3,%1,%h2
3898 #
3899 #"
3900 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3901 (set_attr "length" "4,4,8,8")])
3903 (define_split
3904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3905 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "reg_or_cint_operand" ""))
3907 (const_int 0)))
3908 (clobber (match_scratch:SI 3 ""))]
3909 "TARGET_32BIT && reload_completed"
3910 [(set (match_dup 3)
3911 (ashift:SI (match_dup 1) (match_dup 2)))
3912 (set (match_dup 0)
3913 (compare:CC (match_dup 3)
3914 (const_int 0)))]
3915 "")
3917 (define_insn ""
3918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3919 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3920 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3921 (const_int 0)))
3922 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3923 (ashift:SI (match_dup 1) (match_dup 2)))]
3924 "TARGET_32BIT"
3925 "@
3926 slw. %0,%1,%2
3927 slwi. %0,%1,%h2
3928 #
3929 #"
3930 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3931 (set_attr "length" "4,4,8,8")])
3933 (define_split
3934 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3935 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3936 (match_operand:SI 2 "reg_or_cint_operand" ""))
3937 (const_int 0)))
3938 (set (match_operand:SI 0 "gpc_reg_operand" "")
3939 (ashift:SI (match_dup 1) (match_dup 2)))]
3940 "TARGET_32BIT && reload_completed"
3941 [(set (match_dup 0)
3942 (ashift:SI (match_dup 1) (match_dup 2)))
3943 (set (match_dup 3)
3944 (compare:CC (match_dup 0)
3945 (const_int 0)))]
3946 "")
3948 (define_insn "rlwinm"
3949 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3950 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3951 (match_operand:SI 2 "const_int_operand" "i"))
3952 (match_operand:SI 3 "mask_operand" "n")))]
3953 "includes_lshift_p (operands[2], operands[3])"
3954 "rlwinm %0,%1,%h2,%m3,%M3")
3956 (define_insn ""
3957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3958 (compare:CC
3959 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3960 (match_operand:SI 2 "const_int_operand" "i,i"))
3961 (match_operand:SI 3 "mask_operand" "n,n"))
3962 (const_int 0)))
3963 (clobber (match_scratch:SI 4 "=r,r"))]
3964 "includes_lshift_p (operands[2], operands[3])"
3965 "@
3966 rlwinm. %4,%1,%h2,%m3,%M3
3967 #"
3968 [(set_attr "type" "delayed_compare")
3969 (set_attr "length" "4,8")])
3971 (define_split
3972 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3973 (compare:CC
3974 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3975 (match_operand:SI 2 "const_int_operand" ""))
3976 (match_operand:SI 3 "mask_operand" ""))
3977 (const_int 0)))
3978 (clobber (match_scratch:SI 4 ""))]
3979 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3980 [(set (match_dup 4)
3981 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3982 (match_dup 3)))
3983 (set (match_dup 0)
3984 (compare:CC (match_dup 4)
3985 (const_int 0)))]
3986 "")
3988 (define_insn ""
3989 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3990 (compare:CC
3991 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3992 (match_operand:SI 2 "const_int_operand" "i,i"))
3993 (match_operand:SI 3 "mask_operand" "n,n"))
3994 (const_int 0)))
3995 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3996 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3997 "includes_lshift_p (operands[2], operands[3])"
3998 "@
3999 rlwinm. %0,%1,%h2,%m3,%M3
4000 #"
4001 [(set_attr "type" "delayed_compare")
4002 (set_attr "length" "4,8")])
4004 (define_split
4005 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4006 (compare:CC
4007 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4008 (match_operand:SI 2 "const_int_operand" ""))
4009 (match_operand:SI 3 "mask_operand" ""))
4010 (const_int 0)))
4011 (set (match_operand:SI 0 "gpc_reg_operand" "")
4012 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4013 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4014 [(set (match_dup 0)
4015 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4016 (set (match_dup 4)
4017 (compare:CC (match_dup 0)
4018 (const_int 0)))]
4019 "")
4021 (define_insn "lshrsi3"
4022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4023 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4024 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4025 ""
4026 "@
4027 mr %0,%1
4028 srw %0,%1,%2
4029 srwi %0,%1,%h2"
4030 [(set_attr "type" "integer,var_shift_rotate,shift")])
4032 (define_insn "*lshrsi3_64"
4033 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4034 (zero_extend:DI
4035 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4036 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4037 "TARGET_POWERPC64"
4038 "@
4039 srw %0,%1,%2
4040 srwi %0,%1,%h2"
4041 [(set_attr "type" "var_shift_rotate,shift")])
4043 (define_insn ""
4044 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4045 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4046 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4047 (const_int 0)))
4048 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4049 "TARGET_32BIT"
4050 "@
4051 mr. %1,%1
4052 srw. %3,%1,%2
4053 srwi. %3,%1,%h2
4054 #
4055 #
4056 #"
4057 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4058 (set_attr "length" "4,4,4,8,8,8")])
4060 (define_split
4061 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4062 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4063 (match_operand:SI 2 "reg_or_cint_operand" ""))
4064 (const_int 0)))
4065 (clobber (match_scratch:SI 3 ""))]
4066 "TARGET_32BIT && reload_completed"
4067 [(set (match_dup 3)
4068 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4069 (set (match_dup 0)
4070 (compare:CC (match_dup 3)
4071 (const_int 0)))]
4072 "")
4074 (define_insn ""
4075 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4076 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4077 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4078 (const_int 0)))
4079 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4080 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4081 "TARGET_32BIT"
4082 "@
4083 mr. %0,%1
4084 srw. %0,%1,%2
4085 srwi. %0,%1,%h2
4086 #
4087 #
4088 #"
4089 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4090 (set_attr "length" "4,4,4,8,8,8")])
4092 (define_split
4093 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4094 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4095 (match_operand:SI 2 "reg_or_cint_operand" ""))
4096 (const_int 0)))
4097 (set (match_operand:SI 0 "gpc_reg_operand" "")
4098 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4099 "TARGET_32BIT && reload_completed"
4100 [(set (match_dup 0)
4101 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4102 (set (match_dup 3)
4103 (compare:CC (match_dup 0)
4104 (const_int 0)))]
4105 "")
4107 (define_insn ""
4108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4109 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4110 (match_operand:SI 2 "const_int_operand" "i"))
4111 (match_operand:SI 3 "mask_operand" "n")))]
4112 "includes_rshift_p (operands[2], operands[3])"
4113 "rlwinm %0,%1,%s2,%m3,%M3")
4115 (define_insn ""
4116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4117 (compare:CC
4118 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4119 (match_operand:SI 2 "const_int_operand" "i,i"))
4120 (match_operand:SI 3 "mask_operand" "n,n"))
4121 (const_int 0)))
4122 (clobber (match_scratch:SI 4 "=r,r"))]
4123 "includes_rshift_p (operands[2], operands[3])"
4124 "@
4125 rlwinm. %4,%1,%s2,%m3,%M3
4126 #"
4127 [(set_attr "type" "delayed_compare")
4128 (set_attr "length" "4,8")])
4130 (define_split
4131 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4132 (compare:CC
4133 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" ""))
4135 (match_operand:SI 3 "mask_operand" ""))
4136 (const_int 0)))
4137 (clobber (match_scratch:SI 4 ""))]
4138 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4139 [(set (match_dup 4)
4140 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4141 (match_dup 3)))
4142 (set (match_dup 0)
4143 (compare:CC (match_dup 4)
4144 (const_int 0)))]
4145 "")
4147 (define_insn ""
4148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4149 (compare:CC
4150 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4151 (match_operand:SI 2 "const_int_operand" "i,i"))
4152 (match_operand:SI 3 "mask_operand" "n,n"))
4153 (const_int 0)))
4154 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4155 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4156 "includes_rshift_p (operands[2], operands[3])"
4157 "@
4158 rlwinm. %0,%1,%s2,%m3,%M3
4159 #"
4160 [(set_attr "type" "delayed_compare")
4161 (set_attr "length" "4,8")])
4163 (define_split
4164 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4165 (compare:CC
4166 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4167 (match_operand:SI 2 "const_int_operand" ""))
4168 (match_operand:SI 3 "mask_operand" ""))
4169 (const_int 0)))
4170 (set (match_operand:SI 0 "gpc_reg_operand" "")
4171 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4172 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4173 [(set (match_dup 0)
4174 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4175 (set (match_dup 4)
4176 (compare:CC (match_dup 0)
4177 (const_int 0)))]
4178 "")
4180 (define_insn ""
4181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4182 (zero_extend:SI
4183 (subreg:QI
4184 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4185 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4186 "includes_rshift_p (operands[2], GEN_INT (255))"
4187 "rlwinm %0,%1,%s2,0xff")
4189 (define_insn ""
4190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4191 (compare:CC
4192 (zero_extend:SI
4193 (subreg:QI
4194 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4195 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4196 (const_int 0)))
4197 (clobber (match_scratch:SI 3 "=r,r"))]
4198 "includes_rshift_p (operands[2], GEN_INT (255))"
4199 "@
4200 rlwinm. %3,%1,%s2,0xff
4201 #"
4202 [(set_attr "type" "delayed_compare")
4203 (set_attr "length" "4,8")])
4205 (define_split
4206 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4207 (compare:CC
4208 (zero_extend:SI
4209 (subreg:QI
4210 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4211 (match_operand:SI 2 "const_int_operand" "")) 0))
4212 (const_int 0)))
4213 (clobber (match_scratch:SI 3 ""))]
4214 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4215 [(set (match_dup 3)
4216 (zero_extend:SI (subreg:QI
4217 (lshiftrt:SI (match_dup 1)
4218 (match_dup 2)) 0)))
4219 (set (match_dup 0)
4220 (compare:CC (match_dup 3)
4221 (const_int 0)))]
4222 "")
4224 (define_insn ""
4225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4226 (compare:CC
4227 (zero_extend:SI
4228 (subreg:QI
4229 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4230 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4231 (const_int 0)))
4232 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4233 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4234 "includes_rshift_p (operands[2], GEN_INT (255))"
4235 "@
4236 rlwinm. %0,%1,%s2,0xff
4237 #"
4238 [(set_attr "type" "delayed_compare")
4239 (set_attr "length" "4,8")])
4241 (define_split
4242 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4243 (compare:CC
4244 (zero_extend:SI
4245 (subreg:QI
4246 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4247 (match_operand:SI 2 "const_int_operand" "")) 0))
4248 (const_int 0)))
4249 (set (match_operand:SI 0 "gpc_reg_operand" "")
4250 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4251 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4252 [(set (match_dup 0)
4253 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4254 (set (match_dup 3)
4255 (compare:CC (match_dup 0)
4256 (const_int 0)))]
4257 "")
4259 (define_insn ""
4260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4261 (zero_extend:SI
4262 (subreg:HI
4263 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4264 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4265 "includes_rshift_p (operands[2], GEN_INT (65535))"
4266 "rlwinm %0,%1,%s2,0xffff")
4268 (define_insn ""
4269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4270 (compare:CC
4271 (zero_extend:SI
4272 (subreg:HI
4273 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4274 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4275 (const_int 0)))
4276 (clobber (match_scratch:SI 3 "=r,r"))]
4277 "includes_rshift_p (operands[2], GEN_INT (65535))"
4278 "@
4279 rlwinm. %3,%1,%s2,0xffff
4280 #"
4281 [(set_attr "type" "delayed_compare")
4282 (set_attr "length" "4,8")])
4284 (define_split
4285 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4286 (compare:CC
4287 (zero_extend:SI
4288 (subreg:HI
4289 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4290 (match_operand:SI 2 "const_int_operand" "")) 0))
4291 (const_int 0)))
4292 (clobber (match_scratch:SI 3 ""))]
4293 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4294 [(set (match_dup 3)
4295 (zero_extend:SI (subreg:HI
4296 (lshiftrt:SI (match_dup 1)
4297 (match_dup 2)) 0)))
4298 (set (match_dup 0)
4299 (compare:CC (match_dup 3)
4300 (const_int 0)))]
4301 "")
4303 (define_insn ""
4304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4305 (compare:CC
4306 (zero_extend:SI
4307 (subreg:HI
4308 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4309 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4310 (const_int 0)))
4311 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4312 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4313 "includes_rshift_p (operands[2], GEN_INT (65535))"
4314 "@
4315 rlwinm. %0,%1,%s2,0xffff
4316 #"
4317 [(set_attr "type" "delayed_compare")
4318 (set_attr "length" "4,8")])
4320 (define_split
4321 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4322 (compare:CC
4323 (zero_extend:SI
4324 (subreg:HI
4325 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4326 (match_operand:SI 2 "const_int_operand" "")) 0))
4327 (const_int 0)))
4328 (set (match_operand:SI 0 "gpc_reg_operand" "")
4329 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4330 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4331 [(set (match_dup 0)
4332 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4333 (set (match_dup 3)
4334 (compare:CC (match_dup 0)
4335 (const_int 0)))]
4336 "")
4338 (define_insn "ashrsi3"
4339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4340 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4341 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4342 ""
4343 "@
4344 sraw %0,%1,%2
4345 srawi %0,%1,%h2"
4346 [(set_attr "type" "var_shift_rotate,shift")])
4348 (define_insn "*ashrsi3_64"
4349 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4350 (sign_extend:DI
4351 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4352 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4353 "TARGET_POWERPC64"
4354 "@
4355 sraw %0,%1,%2
4356 srawi %0,%1,%h2"
4357 [(set_attr "type" "var_shift_rotate,shift")])
4359 (define_insn ""
4360 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4361 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4362 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4363 (const_int 0)))
4364 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4365 ""
4366 "@
4367 sraw. %3,%1,%2
4368 srawi. %3,%1,%h2
4369 #
4370 #"
4371 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4372 (set_attr "length" "4,4,8,8")])
4374 (define_split
4375 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4376 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4377 (match_operand:SI 2 "reg_or_cint_operand" ""))
4378 (const_int 0)))
4379 (clobber (match_scratch:SI 3 ""))]
4380 "reload_completed"
4381 [(set (match_dup 3)
4382 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4383 (set (match_dup 0)
4384 (compare:CC (match_dup 3)
4385 (const_int 0)))]
4386 "")
4388 (define_insn ""
4389 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4390 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4391 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4392 (const_int 0)))
4393 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4394 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4395 ""
4396 "@
4397 sraw. %0,%1,%2
4398 srawi. %0,%1,%h2
4399 #
4400 #"
4401 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4402 (set_attr "length" "4,4,8,8")])
4403 \f
4404 ;; Builtins to replace a division to generate FRE reciprocal estimate
4405 ;; instructions and the necessary fixup instructions
4406 (define_expand "recip<mode>3"
4407 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4408 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4409 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4410 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4411 {
4412 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4413 DONE;
4414 })
4416 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4417 ;; hardware division. This is only done before register allocation and with
4418 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4419 (define_split
4420 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4421 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4422 (match_operand 2 "gpc_reg_operand" "")))]
4423 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4424 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4425 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4426 [(const_int 0)]
4427 {
4428 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4429 DONE;
4430 })
4432 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4433 ;; appropriate fixup.
4434 (define_expand "rsqrt<mode>2"
4435 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4436 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4437 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4438 {
4439 rs6000_emit_swrsqrt (operands[0], operands[1]);
4440 DONE;
4441 })
4442 \f
4443 (define_split
4444 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4445 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4446 (match_operand:SI 2 "reg_or_cint_operand" ""))
4447 (const_int 0)))
4448 (set (match_operand:SI 0 "gpc_reg_operand" "")
4449 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4450 "reload_completed"
4451 [(set (match_dup 0)
4452 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4453 (set (match_dup 3)
4454 (compare:CC (match_dup 0)
4455 (const_int 0)))]
4456 "")
4458 ;; Floating-point insns, excluding normal data motion.
4459 ;;
4460 ;; PowerPC has a full set of single-precision floating point instructions.
4461 ;;
4462 ;; For the POWER architecture, we pretend that we have both SFmode and
4463 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4464 ;; The only conversions we will do will be when storing to memory. In that
4465 ;; case, we will use the "frsp" instruction before storing.
4466 ;;
4467 ;; Note that when we store into a single-precision memory location, we need to
4468 ;; use the frsp insn first. If the register being stored isn't dead, we
4469 ;; need a scratch register for the frsp. But this is difficult when the store
4470 ;; is done by reload. It is not incorrect to do the frsp on the register in
4471 ;; this case, we just lose precision that we would have otherwise gotten but
4472 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4474 (define_expand "extendsfdf2"
4475 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4476 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4477 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4478 "")
4480 (define_insn_and_split "*extendsfdf2_fpr"
4481 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4482 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4483 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4484 "@
4485 #
4486 fmr %0,%1
4487 lfs%U1%X1 %0,%1"
4488 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4489 [(const_int 0)]
4490 {
4491 emit_note (NOTE_INSN_DELETED);
4492 DONE;
4493 }
4494 [(set_attr "type" "fp,fp,fpload")])
4496 (define_expand "truncdfsf2"
4497 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4498 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4499 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4500 "")
4502 (define_insn "*truncdfsf2_fpr"
4503 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4504 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4505 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4506 "frsp %0,%1"
4507 [(set_attr "type" "fp")])
4509 (define_expand "negsf2"
4510 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4511 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4512 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4513 "")
4515 (define_insn "*negsf2"
4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4518 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4519 "fneg %0,%1"
4520 [(set_attr "type" "fp")])
4522 (define_expand "abssf2"
4523 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4524 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4525 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4526 "")
4528 (define_insn "*abssf2"
4529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4530 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4531 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4532 "fabs %0,%1"
4533 [(set_attr "type" "fp")])
4535 (define_insn ""
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4538 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4539 "fnabs %0,%1"
4540 [(set_attr "type" "fp")])
4542 (define_expand "addsf3"
4543 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4544 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4545 (match_operand:SF 2 "gpc_reg_operand" "")))]
4546 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4547 "")
4549 (define_insn ""
4550 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4551 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4552 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4553 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4554 "fadds %0,%1,%2"
4555 [(set_attr "type" "fp")
4556 (set_attr "fp_type" "fp_addsub_s")])
4558 (define_expand "subsf3"
4559 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4560 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4561 (match_operand:SF 2 "gpc_reg_operand" "")))]
4562 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4563 "")
4565 (define_insn ""
4566 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4567 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4568 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4569 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4570 "fsubs %0,%1,%2"
4571 [(set_attr "type" "fp")
4572 (set_attr "fp_type" "fp_addsub_s")])
4574 (define_expand "mulsf3"
4575 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4576 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4577 (match_operand:SF 2 "gpc_reg_operand" "")))]
4578 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4579 "")
4581 (define_insn ""
4582 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4583 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4584 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4585 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4586 "fmuls %0,%1,%2"
4587 [(set_attr "type" "fp")
4588 (set_attr "fp_type" "fp_mul_s")])
4590 (define_expand "divsf3"
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4592 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4593 (match_operand:SF 2 "gpc_reg_operand" "")))]
4594 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4595 "")
4597 (define_insn ""
4598 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4599 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4600 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4601 "TARGET_HARD_FLOAT && TARGET_FPRS
4602 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4603 "fdivs %0,%1,%2"
4604 [(set_attr "type" "sdiv")])
4606 (define_insn "fres"
4607 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4608 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4609 "TARGET_FRES"
4610 "fres %0,%1"
4611 [(set_attr "type" "fp")])
4613 ; builtin fmaf support
4614 (define_insn "*fmasf4_fpr"
4615 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4616 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4617 (match_operand:SF 2 "gpc_reg_operand" "f")
4618 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4619 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4620 "fmadds %0,%1,%2,%3"
4621 [(set_attr "type" "fp")
4622 (set_attr "fp_type" "fp_maddsub_s")])
4624 (define_insn "*fmssf4_fpr"
4625 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4626 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4627 (match_operand:SF 2 "gpc_reg_operand" "f")
4628 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4629 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4630 "fmsubs %0,%1,%2,%3"
4631 [(set_attr "type" "fp")
4632 (set_attr "fp_type" "fp_maddsub_s")])
4634 (define_insn "*nfmasf4_fpr"
4635 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4636 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4637 (match_operand:SF 2 "gpc_reg_operand" "f")
4638 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4639 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4640 "fnmadds %0,%1,%2,%3"
4641 [(set_attr "type" "fp")
4642 (set_attr "fp_type" "fp_maddsub_s")])
4644 (define_insn "*nfmssf4_fpr"
4645 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4646 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4647 (match_operand:SF 2 "gpc_reg_operand" "f")
4648 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
4649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4650 "fnmsubs %0,%1,%2,%3"
4651 [(set_attr "type" "fp")
4652 (set_attr "fp_type" "fp_maddsub_s")])
4654 (define_expand "sqrtsf2"
4655 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4656 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4657 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
4658 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
4659 && !TARGET_SIMPLE_FPU"
4660 "")
4662 (define_insn ""
4663 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4664 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4665 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
4666 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4667 "fsqrts %0,%1"
4668 [(set_attr "type" "ssqrt")])
4670 (define_insn "*rsqrtsf_internal1"
4671 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4672 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
4673 UNSPEC_RSQRT))]
4674 "TARGET_FRSQRTES"
4675 "frsqrtes %0,%1"
4676 [(set_attr "type" "fp")])
4678 (define_expand "copysign<mode>3"
4679 [(set (match_dup 3)
4680 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
4681 (set (match_dup 4)
4682 (neg:SFDF (abs:SFDF (match_dup 1))))
4683 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
4684 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
4685 (match_dup 5))
4686 (match_dup 3)
4687 (match_dup 4)))]
4688 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
4689 && ((TARGET_PPC_GFXOPT
4690 && !HONOR_NANS (<MODE>mode)
4691 && !HONOR_SIGNED_ZEROS (<MODE>mode))
4692 || TARGET_CMPB
4693 || VECTOR_UNIT_VSX_P (<MODE>mode))"
4694 {
4695 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
4696 {
4697 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
4698 operands[2]));
4699 DONE;
4700 }
4702 operands[3] = gen_reg_rtx (<MODE>mode);
4703 operands[4] = gen_reg_rtx (<MODE>mode);
4704 operands[5] = CONST0_RTX (<MODE>mode);
4705 })
4707 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
4708 ;; compiler from optimizing -0.0
4709 (define_insn "copysign<mode>3_fcpsgn"
4710 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
4711 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
4712 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
4713 UNSPEC_COPYSIGN))]
4714 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
4715 "fcpsgn %0,%2,%1"
4716 [(set_attr "type" "fp")])
4718 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4719 ;; fsel instruction and some auxiliary computations. Then we just have a
4720 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4721 ;; combine.
4722 (define_expand "smaxsf3"
4723 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4724 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4725 (match_operand:SF 2 "gpc_reg_operand" ""))
4726 (match_dup 1)
4727 (match_dup 2)))]
4728 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4729 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4730 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4732 (define_expand "sminsf3"
4733 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4734 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4735 (match_operand:SF 2 "gpc_reg_operand" ""))
4736 (match_dup 2)
4737 (match_dup 1)))]
4738 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4739 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4740 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4742 (define_split
4743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4744 (match_operator:SF 3 "min_max_operator"
4745 [(match_operand:SF 1 "gpc_reg_operand" "")
4746 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4747 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4748 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4749 [(const_int 0)]
4750 "
4751 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4752 operands[1], operands[2]);
4753 DONE;
4754 }")
4756 (define_expand "mov<mode>cc"
4757 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4758 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
4759 (match_operand:GPR 2 "gpc_reg_operand" "")
4760 (match_operand:GPR 3 "gpc_reg_operand" "")))]
4761 "TARGET_ISEL<sel>"
4762 "
4763 {
4764 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4765 DONE;
4766 else
4767 FAIL;
4768 }")
4770 ;; We use the BASE_REGS for the isel input operands because, if rA is
4771 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4772 ;; because we may switch the operands and rB may end up being rA.
4773 ;;
4774 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4775 ;; leave out the mode in operand 4 and use one pattern, but reload can
4776 ;; change the mode underneath our feet and then gets confused trying
4777 ;; to reload the value.
4778 (define_insn "isel_signed_<mode>"
4779 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4780 (if_then_else:GPR
4781 (match_operator 1 "scc_comparison_operator"
4782 [(match_operand:CC 4 "cc_reg_operand" "y,y")
4783 (const_int 0)])
4784 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4785 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4786 "TARGET_ISEL<sel>"
4787 "*
4788 { return output_isel (operands); }"
4789 [(set_attr "type" "isel")
4790 (set_attr "length" "4")])
4792 (define_insn "isel_unsigned_<mode>"
4793 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4794 (if_then_else:GPR
4795 (match_operator 1 "scc_comparison_operator"
4796 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
4797 (const_int 0)])
4798 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4799 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4800 "TARGET_ISEL<sel>"
4801 "*
4802 { return output_isel (operands); }"
4803 [(set_attr "type" "isel")
4804 (set_attr "length" "4")])
4806 ;; These patterns can be useful for combine; they let combine know that
4807 ;; isel can handle reversed comparisons so long as the operands are
4808 ;; registers.
4810 (define_insn "*isel_reversed_signed_<mode>"
4811 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4812 (if_then_else:GPR
4813 (match_operator 1 "scc_rev_comparison_operator"
4814 [(match_operand:CC 4 "cc_reg_operand" "y")
4815 (const_int 0)])
4816 (match_operand:GPR 2 "gpc_reg_operand" "b")
4817 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4818 "TARGET_ISEL<sel>"
4819 "*
4820 { return output_isel (operands); }"
4821 [(set_attr "type" "isel")
4822 (set_attr "length" "4")])
4824 (define_insn "*isel_reversed_unsigned_<mode>"
4825 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4826 (if_then_else:GPR
4827 (match_operator 1 "scc_rev_comparison_operator"
4828 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4829 (const_int 0)])
4830 (match_operand:GPR 2 "gpc_reg_operand" "b")
4831 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4832 "TARGET_ISEL<sel>"
4833 "*
4834 { return output_isel (operands); }"
4835 [(set_attr "type" "isel")
4836 (set_attr "length" "4")])
4838 (define_expand "movsfcc"
4839 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4840 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4841 (match_operand:SF 2 "gpc_reg_operand" "")
4842 (match_operand:SF 3 "gpc_reg_operand" "")))]
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4844 "
4845 {
4846 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4847 DONE;
4848 else
4849 FAIL;
4850 }")
4852 (define_insn "*fselsfsf4"
4853 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4854 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4855 (match_operand:SF 4 "zero_fp_constant" "F"))
4856 (match_operand:SF 2 "gpc_reg_operand" "f")
4857 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4858 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4859 "fsel %0,%1,%2,%3"
4860 [(set_attr "type" "fp")])
4862 (define_insn "*fseldfsf4"
4863 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4864 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
4865 (match_operand:DF 4 "zero_fp_constant" "F"))
4866 (match_operand:SF 2 "gpc_reg_operand" "f")
4867 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4868 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
4869 "fsel %0,%1,%2,%3"
4870 [(set_attr "type" "fp")])
4872 (define_expand "negdf2"
4873 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4874 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4875 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4876 "")
4878 (define_insn "*negdf2_fpr"
4879 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4880 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4881 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4882 && !VECTOR_UNIT_VSX_P (DFmode)"
4883 "fneg %0,%1"
4884 [(set_attr "type" "fp")])
4886 (define_expand "absdf2"
4887 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4888 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4889 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4890 "")
4892 (define_insn "*absdf2_fpr"
4893 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4894 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4895 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4896 && !VECTOR_UNIT_VSX_P (DFmode)"
4897 "fabs %0,%1"
4898 [(set_attr "type" "fp")])
4900 (define_insn "*nabsdf2_fpr"
4901 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4902 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
4903 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4904 && !VECTOR_UNIT_VSX_P (DFmode)"
4905 "fnabs %0,%1"
4906 [(set_attr "type" "fp")])
4908 (define_expand "adddf3"
4909 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4910 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4911 (match_operand:DF 2 "gpc_reg_operand" "")))]
4912 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4913 "")
4915 (define_insn "*adddf3_fpr"
4916 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4917 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4918 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4919 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4920 && !VECTOR_UNIT_VSX_P (DFmode)"
4921 "fadd %0,%1,%2"
4922 [(set_attr "type" "fp")
4923 (set_attr "fp_type" "fp_addsub_d")])
4925 (define_expand "subdf3"
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4927 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4928 (match_operand:DF 2 "gpc_reg_operand" "")))]
4929 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4930 "")
4932 (define_insn "*subdf3_fpr"
4933 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4934 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4935 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4936 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4937 && !VECTOR_UNIT_VSX_P (DFmode)"
4938 "fsub %0,%1,%2"
4939 [(set_attr "type" "fp")
4940 (set_attr "fp_type" "fp_addsub_d")])
4942 (define_expand "muldf3"
4943 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4944 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4945 (match_operand:DF 2 "gpc_reg_operand" "")))]
4946 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4947 "")
4949 (define_insn "*muldf3_fpr"
4950 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4951 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4952 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4953 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4954 && !VECTOR_UNIT_VSX_P (DFmode)"
4955 "fmul %0,%1,%2"
4956 [(set_attr "type" "dmul")
4957 (set_attr "fp_type" "fp_mul_d")])
4959 (define_expand "divdf3"
4960 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4961 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4962 (match_operand:DF 2 "gpc_reg_operand" "")))]
4963 "TARGET_HARD_FLOAT
4964 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
4965 && !TARGET_SIMPLE_FPU"
4966 "")
4968 (define_insn "*divdf3_fpr"
4969 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4970 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4971 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4972 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
4973 && !VECTOR_UNIT_VSX_P (DFmode)"
4974 "fdiv %0,%1,%2"
4975 [(set_attr "type" "ddiv")])
4977 (define_insn "*fred_fpr"
4978 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4979 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4980 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
4981 "fre %0,%1"
4982 [(set_attr "type" "fp")])
4984 (define_insn "*rsqrtdf_internal1"
4985 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4986 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
4987 UNSPEC_RSQRT))]
4988 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
4989 "frsqrte %0,%1"
4990 [(set_attr "type" "fp")])
4992 ; builtin fma support
4993 (define_insn "*fmadf4_fpr"
4994 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4995 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4996 (match_operand:DF 2 "gpc_reg_operand" "f")
4997 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4998 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4999 && VECTOR_UNIT_NONE_P (DFmode)"
5000 "fmadd %0,%1,%2,%3"
5001 [(set_attr "type" "fp")
5002 (set_attr "fp_type" "fp_maddsub_d")])
5004 (define_insn "*fmsdf4_fpr"
5005 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5006 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5007 (match_operand:DF 2 "gpc_reg_operand" "f")
5008 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5009 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5010 && VECTOR_UNIT_NONE_P (DFmode)"
5011 "fmsub %0,%1,%2,%3"
5012 [(set_attr "type" "fp")
5013 (set_attr "fp_type" "fp_maddsub_d")])
5015 (define_insn "*nfmadf4_fpr"
5016 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5017 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5018 (match_operand:DF 2 "gpc_reg_operand" "f")
5019 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5020 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5021 && VECTOR_UNIT_NONE_P (DFmode)"
5022 "fnmadd %0,%1,%2,%3"
5023 [(set_attr "type" "fp")
5024 (set_attr "fp_type" "fp_maddsub_d")])
5026 (define_insn "*nfmsdf4_fpr"
5027 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5028 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5029 (match_operand:DF 2 "gpc_reg_operand" "f")
5030 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5031 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5032 && VECTOR_UNIT_NONE_P (DFmode)"
5033 "fnmsub %0,%1,%2,%3"
5034 [(set_attr "type" "fp")
5035 (set_attr "fp_type" "fp_maddsub_d")])
5037 (define_expand "sqrtdf2"
5038 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5039 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5040 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5041 "")
5043 (define_insn "*sqrtdf2_fpr"
5044 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5045 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5046 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5047 && !VECTOR_UNIT_VSX_P (DFmode)"
5048 "fsqrt %0,%1"
5049 [(set_attr "type" "dsqrt")])
5051 ;; The conditional move instructions allow us to perform max and min
5052 ;; operations even when
5054 (define_expand "smaxdf3"
5055 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5056 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5057 (match_operand:DF 2 "gpc_reg_operand" ""))
5058 (match_dup 1)
5059 (match_dup 2)))]
5060 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5061 && !flag_trapping_math"
5062 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5064 (define_expand "smindf3"
5065 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5066 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5067 (match_operand:DF 2 "gpc_reg_operand" ""))
5068 (match_dup 2)
5069 (match_dup 1)))]
5070 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5071 && !flag_trapping_math"
5072 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5074 (define_split
5075 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5076 (match_operator:DF 3 "min_max_operator"
5077 [(match_operand:DF 1 "gpc_reg_operand" "")
5078 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5079 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5080 && !flag_trapping_math"
5081 [(const_int 0)]
5082 "
5083 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5084 operands[1], operands[2]);
5085 DONE;
5086 }")
5088 (define_expand "movdfcc"
5089 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5090 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5091 (match_operand:DF 2 "gpc_reg_operand" "")
5092 (match_operand:DF 3 "gpc_reg_operand" "")))]
5093 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5094 "
5095 {
5096 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5097 DONE;
5098 else
5099 FAIL;
5100 }")
5102 (define_insn "*fseldfdf4"
5103 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5104 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5105 (match_operand:DF 4 "zero_fp_constant" "F"))
5106 (match_operand:DF 2 "gpc_reg_operand" "d")
5107 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5108 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5109 "fsel %0,%1,%2,%3"
5110 [(set_attr "type" "fp")])
5112 (define_insn "*fselsfdf4"
5113 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5114 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5115 (match_operand:SF 4 "zero_fp_constant" "F"))
5116 (match_operand:DF 2 "gpc_reg_operand" "d")
5117 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5118 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5119 "fsel %0,%1,%2,%3"
5120 [(set_attr "type" "fp")])
5121 \f
5122 ;; Conversions to and from floating-point.
5124 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5125 ; don't want to support putting SImode in FPR registers.
5126 (define_insn "lfiwax"
5127 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5128 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5129 UNSPEC_LFIWAX))]
5130 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5131 "lfiwax %0,%y1"
5132 [(set_attr "type" "fpload")])
5134 ; This split must be run before register allocation because it allocates the
5135 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5136 ; it earlier to allow for the combiner to merge insns together where it might
5137 ; not be needed and also in case the insns are deleted as dead code.
5139 (define_insn_and_split "floatsi<mode>2_lfiwax"
5140 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5141 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5142 (clobber (match_scratch:DI 2 "=d"))]
5143 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5144 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5145 "#"
5146 ""
5147 [(pc)]
5148 "
5149 {
5150 rtx dest = operands[0];
5151 rtx src = operands[1];
5152 rtx tmp;
5154 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5155 tmp = convert_to_mode (DImode, src, false);
5156 else
5157 {
5158 tmp = operands[2];
5159 if (GET_CODE (tmp) == SCRATCH)
5160 tmp = gen_reg_rtx (DImode);
5161 if (MEM_P (src))
5162 {
5163 src = rs6000_address_for_fpconvert (src);
5164 emit_insn (gen_lfiwax (tmp, src));
5165 }
5166 else
5167 {
5168 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5169 emit_move_insn (stack, src);
5170 emit_insn (gen_lfiwax (tmp, stack));
5171 }
5172 }
5173 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5174 DONE;
5175 }"
5176 [(set_attr "length" "12")
5177 (set_attr "type" "fpload")])
5179 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5180 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5181 (float:SFDF
5182 (sign_extend:DI
5183 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5184 (clobber (match_scratch:DI 2 "=0,d"))]
5185 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5186 && <SI_CONVERT_FP>"
5187 "#"
5188 ""
5189 [(pc)]
5190 "
5191 {
5192 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5193 if (GET_CODE (operands[2]) == SCRATCH)
5194 operands[2] = gen_reg_rtx (DImode);
5195 emit_insn (gen_lfiwax (operands[2], operands[1]));
5196 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5197 DONE;
5198 }"
5199 [(set_attr "length" "8")
5200 (set_attr "type" "fpload")])
5202 (define_insn "lfiwzx"
5203 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5204 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5205 UNSPEC_LFIWZX))]
5206 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5207 "lfiwzx %0,%y1"
5208 [(set_attr "type" "fpload")])
5210 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5211 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5212 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5213 (clobber (match_scratch:DI 2 "=d"))]
5214 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5215 && <SI_CONVERT_FP>"
5216 "#"
5217 ""
5218 [(pc)]
5219 "
5220 {
5221 rtx dest = operands[0];
5222 rtx src = operands[1];
5223 rtx tmp;
5225 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5226 tmp = convert_to_mode (DImode, src, true);
5227 else
5228 {
5229 tmp = operands[2];
5230 if (GET_CODE (tmp) == SCRATCH)
5231 tmp = gen_reg_rtx (DImode);
5232 if (MEM_P (src))
5233 {
5234 src = rs6000_address_for_fpconvert (src);
5235 emit_insn (gen_lfiwzx (tmp, src));
5236 }
5237 else
5238 {
5239 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5240 emit_move_insn (stack, src);
5241 emit_insn (gen_lfiwzx (tmp, stack));
5242 }
5243 }
5244 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5245 DONE;
5246 }"
5247 [(set_attr "length" "12")
5248 (set_attr "type" "fpload")])
5250 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5251 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5252 (unsigned_float:SFDF
5253 (zero_extend:DI
5254 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5255 (clobber (match_scratch:DI 2 "=0,d"))]
5256 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5257 && <SI_CONVERT_FP>"
5258 "#"
5259 ""
5260 [(pc)]
5261 "
5262 {
5263 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5264 if (GET_CODE (operands[2]) == SCRATCH)
5265 operands[2] = gen_reg_rtx (DImode);
5266 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5267 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5268 DONE;
5269 }"
5270 [(set_attr "length" "8")
5271 (set_attr "type" "fpload")])
5273 ; For each of these conversions, there is a define_expand, a define_insn
5274 ; with a '#' template, and a define_split (with C code). The idea is
5275 ; to allow constant folding with the template of the define_insn,
5276 ; then to have the insns split later (between sched1 and final).
5278 (define_expand "floatsidf2"
5279 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5280 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5281 (use (match_dup 2))
5282 (use (match_dup 3))
5283 (clobber (match_dup 4))
5284 (clobber (match_dup 5))
5285 (clobber (match_dup 6))])]
5286 "TARGET_HARD_FLOAT
5287 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5288 "
5289 {
5290 if (TARGET_E500_DOUBLE)
5291 {
5292 if (!REG_P (operands[1]))
5293 operands[1] = force_reg (SImode, operands[1]);
5294 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5295 DONE;
5296 }
5297 else if (TARGET_LFIWAX && TARGET_FCFID)
5298 {
5299 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5300 DONE;
5301 }
5302 else if (TARGET_FCFID)
5303 {
5304 rtx dreg = operands[1];
5305 if (!REG_P (dreg))
5306 dreg = force_reg (SImode, dreg);
5307 dreg = convert_to_mode (DImode, dreg, false);
5308 emit_insn (gen_floatdidf2 (operands[0], dreg));
5309 DONE;
5310 }
5312 if (!REG_P (operands[1]))
5313 operands[1] = force_reg (SImode, operands[1]);
5314 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5315 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5316 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5317 operands[5] = gen_reg_rtx (DFmode);
5318 operands[6] = gen_reg_rtx (SImode);
5319 }")
5321 (define_insn_and_split "*floatsidf2_internal"
5322 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5323 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5324 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5325 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5326 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5327 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5328 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5329 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5330 "#"
5331 ""
5332 [(pc)]
5333 "
5334 {
5335 rtx lowword, highword;
5336 gcc_assert (MEM_P (operands[4]));
5337 highword = adjust_address (operands[4], SImode, 0);
5338 lowword = adjust_address (operands[4], SImode, 4);
5339 if (! WORDS_BIG_ENDIAN)
5340 {
5341 rtx tmp;
5342 tmp = highword; highword = lowword; lowword = tmp;
5343 }
5345 emit_insn (gen_xorsi3 (operands[6], operands[1],
5346 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5347 emit_move_insn (lowword, operands[6]);
5348 emit_move_insn (highword, operands[2]);
5349 emit_move_insn (operands[5], operands[4]);
5350 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5351 DONE;
5352 }"
5353 [(set_attr "length" "24")
5354 (set_attr "type" "fp")])
5356 ;; If we don't have a direct conversion to single precision, don't enable this
5357 ;; conversion for 32-bit without fast math, because we don't have the insn to
5358 ;; generate the fixup swizzle to avoid double rounding problems.
5359 (define_expand "floatunssisf2"
5360 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5361 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5362 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5363 && (!TARGET_FPRS
5364 || (TARGET_FPRS
5365 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5366 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5367 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5368 "
5369 {
5370 if (!TARGET_FPRS)
5371 {
5372 if (!REG_P (operands[1]))
5373 operands[1] = force_reg (SImode, operands[1]);
5374 }
5375 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5376 {
5377 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5378 DONE;
5379 }
5380 else
5381 {
5382 rtx dreg = operands[1];
5383 if (!REG_P (dreg))
5384 dreg = force_reg (SImode, dreg);
5385 dreg = convert_to_mode (DImode, dreg, true);
5386 emit_insn (gen_floatdisf2 (operands[0], dreg));
5387 DONE;
5388 }
5389 }")
5391 (define_expand "floatunssidf2"
5392 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5393 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5394 (use (match_dup 2))
5395 (use (match_dup 3))
5396 (clobber (match_dup 4))
5397 (clobber (match_dup 5))])]
5398 "TARGET_HARD_FLOAT
5399 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5400 "
5401 {
5402 if (TARGET_E500_DOUBLE)
5403 {
5404 if (!REG_P (operands[1]))
5405 operands[1] = force_reg (SImode, operands[1]);
5406 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5407 DONE;
5408 }
5409 else if (TARGET_LFIWZX && TARGET_FCFID)
5410 {
5411 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5412 DONE;
5413 }
5414 else if (TARGET_FCFID)
5415 {
5416 rtx dreg = operands[1];
5417 if (!REG_P (dreg))
5418 dreg = force_reg (SImode, dreg);
5419 dreg = convert_to_mode (DImode, dreg, true);
5420 emit_insn (gen_floatdidf2 (operands[0], dreg));
5421 DONE;
5422 }
5424 if (!REG_P (operands[1]))
5425 operands[1] = force_reg (SImode, operands[1]);
5426 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5427 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5428 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5429 operands[5] = gen_reg_rtx (DFmode);
5430 }")
5432 (define_insn_and_split "*floatunssidf2_internal"
5433 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5434 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5435 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5436 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5437 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5438 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5439 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5440 && !(TARGET_FCFID && TARGET_POWERPC64)"
5441 "#"
5442 ""
5443 [(pc)]
5444 "
5445 {
5446 rtx lowword, highword;
5447 gcc_assert (MEM_P (operands[4]));
5448 highword = adjust_address (operands[4], SImode, 0);
5449 lowword = adjust_address (operands[4], SImode, 4);
5450 if (! WORDS_BIG_ENDIAN)
5451 {
5452 rtx tmp;
5453 tmp = highword; highword = lowword; lowword = tmp;
5454 }
5456 emit_move_insn (lowword, operands[1]);
5457 emit_move_insn (highword, operands[2]);
5458 emit_move_insn (operands[5], operands[4]);
5459 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5460 DONE;
5461 }"
5462 [(set_attr "length" "20")
5463 (set_attr "type" "fp")])
5465 (define_expand "fix_trunc<mode>si2"
5466 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5467 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5468 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5469 "
5470 {
5471 if (!<E500_CONVERT>)
5472 {
5473 rtx tmp, stack;
5475 if (TARGET_STFIWX)
5476 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5477 else
5478 {
5479 tmp = gen_reg_rtx (DImode);
5480 stack = rs6000_allocate_stack_temp (DImode, true, false);
5481 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5482 tmp, stack));
5483 }
5484 DONE;
5485 }
5486 }")
5488 ; Like the convert to float patterns, this insn must be split before
5489 ; register allocation so that it can allocate the memory slot if it
5490 ; needed
5491 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5492 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5493 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5494 (clobber (match_scratch:DI 2 "=d"))]
5495 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5496 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5497 && TARGET_STFIWX && can_create_pseudo_p ()"
5498 "#"
5499 ""
5500 [(pc)]
5501 {
5502 rtx dest = operands[0];
5503 rtx src = operands[1];
5504 rtx tmp = operands[2];
5506 if (GET_CODE (tmp) == SCRATCH)
5507 tmp = gen_reg_rtx (DImode);
5509 emit_insn (gen_fctiwz_<mode> (tmp, src));
5510 if (MEM_P (dest))
5511 {
5512 dest = rs6000_address_for_fpconvert (dest);
5513 emit_insn (gen_stfiwx (dest, tmp));
5514 DONE;
5515 }
5516 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5517 {
5518 dest = gen_lowpart (DImode, dest);
5519 emit_move_insn (dest, tmp);
5520 DONE;
5521 }
5522 else
5523 {
5524 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5525 emit_insn (gen_stfiwx (stack, tmp));
5526 emit_move_insn (dest, stack);
5527 DONE;
5528 }
5529 }
5530 [(set_attr "length" "12")
5531 (set_attr "type" "fp")])
5533 (define_insn_and_split "fix_trunc<mode>si2_internal"
5534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5535 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5536 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5537 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5538 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5539 "#"
5540 ""
5541 [(pc)]
5542 "
5543 {
5544 rtx lowword;
5545 gcc_assert (MEM_P (operands[3]));
5546 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5548 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5549 emit_move_insn (operands[3], operands[2]);
5550 emit_move_insn (operands[0], lowword);
5551 DONE;
5552 }"
5553 [(set_attr "length" "16")
5554 (set_attr "type" "fp")])
5556 (define_expand "fix_trunc<mode>di2"
5557 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5558 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5559 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5560 && TARGET_FCFID"
5561 "")
5563 (define_insn "*fix_trunc<mode>di2_fctidz"
5564 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5565 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5566 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5567 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5568 "fctidz %0,%1"
5569 [(set_attr "type" "fp")])
5571 (define_expand "fixuns_trunc<mode>si2"
5572 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5573 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5574 "TARGET_HARD_FLOAT
5575 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5576 || <E500_CONVERT>)"
5577 "
5578 {
5579 if (!<E500_CONVERT>)
5580 {
5581 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5582 DONE;
5583 }
5584 }")
5586 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5587 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5588 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5589 (clobber (match_scratch:DI 2 "=d"))]
5590 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5591 && TARGET_STFIWX && can_create_pseudo_p ()"
5592 "#"
5593 ""
5594 [(pc)]
5595 {
5596 rtx dest = operands[0];
5597 rtx src = operands[1];
5598 rtx tmp = operands[2];
5600 if (GET_CODE (tmp) == SCRATCH)
5601 tmp = gen_reg_rtx (DImode);
5603 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5604 if (MEM_P (dest))
5605 {
5606 dest = rs6000_address_for_fpconvert (dest);
5607 emit_insn (gen_stfiwx (dest, tmp));
5608 DONE;
5609 }
5610 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5611 {
5612 dest = gen_lowpart (DImode, dest);
5613 emit_move_insn (dest, tmp);
5614 DONE;
5615 }
5616 else
5617 {
5618 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5619 emit_insn (gen_stfiwx (stack, tmp));
5620 emit_move_insn (dest, stack);
5621 DONE;
5622 }
5623 }
5624 [(set_attr "length" "12")
5625 (set_attr "type" "fp")])
5627 (define_expand "fixuns_trunc<mode>di2"
5628 [(set (match_operand:DI 0 "register_operand" "")
5629 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5630 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5631 "")
5633 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5635 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5636 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5637 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5638 "fctiduz %0,%1"
5639 [(set_attr "type" "fp")])
5641 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5642 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5643 ; because the first makes it clear that operand 0 is not live
5644 ; before the instruction.
5645 (define_insn "fctiwz_<mode>"
5646 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5647 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5648 UNSPEC_FCTIWZ))]
5649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5650 "fctiwz %0,%1"
5651 [(set_attr "type" "fp")])
5653 (define_insn "fctiwuz_<mode>"
5654 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5655 (unspec:DI [(unsigned_fix:SI
5656 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5657 UNSPEC_FCTIWUZ))]
5658 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5659 "fctiwuz %0,%1"
5660 [(set_attr "type" "fp")])
5662 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5663 ;; since the friz instruction does not truncate the value if the floating
5664 ;; point value is < LONG_MIN or > LONG_MAX.
5665 (define_insn "*friz"
5666 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5667 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5668 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5669 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5670 && !flag_trapping_math && TARGET_FRIZ"
5671 "friz %0,%1"
5672 [(set_attr "type" "fp")])
5674 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5675 ;; load to properly sign extend the value, but at least doing a store, load
5676 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5677 ;; if we have 32-bit memory ops
5678 (define_insn_and_split "*round32<mode>2_fprs"
5679 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5680 (float:SFDF
5681 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5682 (clobber (match_scratch:DI 2 "=d"))
5683 (clobber (match_scratch:DI 3 "=d"))]
5684 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5685 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5686 && can_create_pseudo_p ()"
5687 "#"
5688 ""
5689 [(pc)]
5690 {
5691 rtx dest = operands[0];
5692 rtx src = operands[1];
5693 rtx tmp1 = operands[2];
5694 rtx tmp2 = operands[3];
5695 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5697 if (GET_CODE (tmp1) == SCRATCH)
5698 tmp1 = gen_reg_rtx (DImode);
5699 if (GET_CODE (tmp2) == SCRATCH)
5700 tmp2 = gen_reg_rtx (DImode);
5702 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5703 emit_insn (gen_stfiwx (stack, tmp1));
5704 emit_insn (gen_lfiwax (tmp2, stack));
5705 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5706 DONE;
5707 }
5708 [(set_attr "type" "fpload")
5709 (set_attr "length" "16")])
5711 (define_insn_and_split "*roundu32<mode>2_fprs"
5712 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5713 (unsigned_float:SFDF
5714 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5715 (clobber (match_scratch:DI 2 "=d"))
5716 (clobber (match_scratch:DI 3 "=d"))]
5717 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5718 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5719 && can_create_pseudo_p ()"
5720 "#"
5721 ""
5722 [(pc)]
5723 {
5724 rtx dest = operands[0];
5725 rtx src = operands[1];
5726 rtx tmp1 = operands[2];
5727 rtx tmp2 = operands[3];
5728 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5730 if (GET_CODE (tmp1) == SCRATCH)
5731 tmp1 = gen_reg_rtx (DImode);
5732 if (GET_CODE (tmp2) == SCRATCH)
5733 tmp2 = gen_reg_rtx (DImode);
5735 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5736 emit_insn (gen_stfiwx (stack, tmp1));
5737 emit_insn (gen_lfiwzx (tmp2, stack));
5738 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5739 DONE;
5740 }
5741 [(set_attr "type" "fpload")
5742 (set_attr "length" "16")])
5744 ;; No VSX equivalent to fctid
5745 (define_insn "lrint<mode>di2"
5746 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5747 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5748 UNSPEC_FCTID))]
5749 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5750 "fctid %0,%1"
5751 [(set_attr "type" "fp")])
5753 (define_expand "btrunc<mode>2"
5754 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5755 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5756 UNSPEC_FRIZ))]
5757 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5758 "")
5760 (define_insn "*btrunc<mode>2_fpr"
5761 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5762 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5763 UNSPEC_FRIZ))]
5764 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5765 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5766 "friz %0,%1"
5767 [(set_attr "type" "fp")])
5769 (define_expand "ceil<mode>2"
5770 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5771 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5772 UNSPEC_FRIP))]
5773 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5774 "")
5776 (define_insn "*ceil<mode>2_fpr"
5777 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5778 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5779 UNSPEC_FRIP))]
5780 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5781 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5782 "frip %0,%1"
5783 [(set_attr "type" "fp")])
5785 (define_expand "floor<mode>2"
5786 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5787 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5788 UNSPEC_FRIM))]
5789 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5790 "")
5792 (define_insn "*floor<mode>2_fpr"
5793 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5794 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5795 UNSPEC_FRIM))]
5796 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5797 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5798 "frim %0,%1"
5799 [(set_attr "type" "fp")])
5801 ;; No VSX equivalent to frin
5802 (define_insn "round<mode>2"
5803 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5804 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5805 UNSPEC_FRIN))]
5806 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5807 "frin %0,%1"
5808 [(set_attr "type" "fp")])
5810 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5811 (define_insn "stfiwx"
5812 [(set (match_operand:SI 0 "memory_operand" "=Z")
5813 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
5814 UNSPEC_STFIWX))]
5815 "TARGET_PPC_GFXOPT"
5816 "stfiwx %1,%y0"
5817 [(set_attr "type" "fpstore")])
5819 ;; If we don't have a direct conversion to single precision, don't enable this
5820 ;; conversion for 32-bit without fast math, because we don't have the insn to
5821 ;; generate the fixup swizzle to avoid double rounding problems.
5822 (define_expand "floatsisf2"
5823 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5824 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5825 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5826 && (!TARGET_FPRS
5827 || (TARGET_FPRS
5828 && ((TARGET_FCFIDS && TARGET_LFIWAX)
5829 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5830 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5831 "
5832 {
5833 if (!TARGET_FPRS)
5834 {
5835 if (!REG_P (operands[1]))
5836 operands[1] = force_reg (SImode, operands[1]);
5837 }
5838 else if (TARGET_FCFIDS && TARGET_LFIWAX)
5839 {
5840 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
5841 DONE;
5842 }
5843 else if (TARGET_FCFID && TARGET_LFIWAX)
5844 {
5845 rtx dfreg = gen_reg_rtx (DFmode);
5846 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
5847 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
5848 DONE;
5849 }
5850 else
5851 {
5852 rtx dreg = operands[1];
5853 if (!REG_P (dreg))
5854 dreg = force_reg (SImode, dreg);
5855 dreg = convert_to_mode (DImode, dreg, false);
5856 emit_insn (gen_floatdisf2 (operands[0], dreg));
5857 DONE;
5858 }
5859 }")
5861 (define_expand "floatdidf2"
5862 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5863 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
5864 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
5865 "")
5867 (define_insn "*floatdidf2_fpr"
5868 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5869 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5870 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5871 && !VECTOR_UNIT_VSX_P (DFmode)"
5872 "fcfid %0,%1"
5873 [(set_attr "type" "fp")])
5875 ; Allow the combiner to merge source memory operands to the conversion so that
5876 ; the optimizer/register allocator doesn't try to load the value too early in a
5877 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
5878 ; hit. We will split after reload to avoid the trip through the GPRs
5880 (define_insn_and_split "*floatdidf2_mem"
5881 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5882 (float:DF (match_operand:DI 1 "memory_operand" "m")))
5883 (clobber (match_scratch:DI 2 "=d"))]
5884 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
5885 "#"
5886 "&& reload_completed"
5887 [(set (match_dup 2) (match_dup 1))
5888 (set (match_dup 0) (float:DF (match_dup 2)))]
5889 ""
5890 [(set_attr "length" "8")
5891 (set_attr "type" "fpload")])
5893 (define_expand "floatunsdidf2"
5894 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5895 (unsigned_float:DF
5896 (match_operand:DI 1 "gpc_reg_operand" "")))]
5897 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5898 "")
5900 (define_insn "*floatunsdidf2_fcfidu"
5901 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5902 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5903 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
5904 "fcfidu %0,%1"
5905 [(set_attr "type" "fp")
5906 (set_attr "length" "4")])
5908 (define_insn_and_split "*floatunsdidf2_mem"
5909 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5910 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
5911 (clobber (match_scratch:DI 2 "=d"))]
5912 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5913 "#"
5914 "&& reload_completed"
5915 [(set (match_dup 2) (match_dup 1))
5916 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
5917 ""
5918 [(set_attr "length" "8")
5919 (set_attr "type" "fpload")])
5921 (define_expand "floatdisf2"
5922 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5923 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5924 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5925 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
5926 "
5927 {
5928 if (!TARGET_FCFIDS)
5929 {
5930 rtx val = operands[1];
5931 if (!flag_unsafe_math_optimizations)
5932 {
5933 rtx label = gen_label_rtx ();
5934 val = gen_reg_rtx (DImode);
5935 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5936 emit_label (label);
5937 }
5938 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5939 DONE;
5940 }
5941 }")
5943 (define_insn "floatdisf2_fcfids"
5944 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5945 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5946 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5947 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5948 "fcfids %0,%1"
5949 [(set_attr "type" "fp")])
5951 (define_insn_and_split "*floatdisf2_mem"
5952 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5953 (float:SF (match_operand:DI 1 "memory_operand" "m")))
5954 (clobber (match_scratch:DI 2 "=f"))]
5955 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5956 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5957 "#"
5958 "&& reload_completed"
5959 [(pc)]
5960 "
5961 {
5962 emit_move_insn (operands[2], operands[1]);
5963 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
5964 DONE;
5965 }"
5966 [(set_attr "length" "8")])
5968 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5969 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5970 ;; from double rounding.
5971 ;; Instead of creating a new cpu type for two FP operations, just use fp
5972 (define_insn_and_split "floatdisf2_internal1"
5973 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5974 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
5975 (clobber (match_scratch:DF 2 "=d"))]
5976 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5977 "#"
5978 "&& reload_completed"
5979 [(set (match_dup 2)
5980 (float:DF (match_dup 1)))
5981 (set (match_dup 0)
5982 (float_truncate:SF (match_dup 2)))]
5983 ""
5984 [(set_attr "length" "8")
5985 (set_attr "type" "fp")])
5987 ;; Twiddles bits to avoid double rounding.
5988 ;; Bits that might be truncated when converting to DFmode are replaced
5989 ;; by a bit that won't be lost at that stage, but is below the SFmode
5990 ;; rounding position.
5991 (define_expand "floatdisf2_internal2"
5992 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5993 (const_int 53)))
5994 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5995 (const_int 2047)))
5996 (clobber (scratch:CC))])
5997 (set (match_dup 3) (plus:DI (match_dup 3)
5998 (const_int 1)))
5999 (set (match_dup 0) (plus:DI (match_dup 0)
6000 (const_int 2047)))
6001 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6002 (const_int 2)))
6003 (set (match_dup 0) (ior:DI (match_dup 0)
6004 (match_dup 1)))
6005 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6006 (const_int -2048)))
6007 (clobber (scratch:CC))])
6008 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6009 (label_ref (match_operand:DI 2 "" ""))
6010 (pc)))
6011 (set (match_dup 0) (match_dup 1))]
6012 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6013 "
6014 {
6015 operands[3] = gen_reg_rtx (DImode);
6016 operands[4] = gen_reg_rtx (CCUNSmode);
6017 }")
6019 (define_expand "floatunsdisf2"
6020 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6021 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6022 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6023 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6024 "")
6026 (define_insn "floatunsdisf2_fcfidus"
6027 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6028 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6029 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6030 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6031 "fcfidus %0,%1"
6032 [(set_attr "type" "fp")])
6034 (define_insn_and_split "*floatunsdisf2_mem"
6035 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6036 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6037 (clobber (match_scratch:DI 2 "=f"))]
6038 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6039 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6040 "#"
6041 "&& reload_completed"
6042 [(pc)]
6043 "
6044 {
6045 emit_move_insn (operands[2], operands[1]);
6046 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6047 DONE;
6048 }"
6049 [(set_attr "length" "8")
6050 (set_attr "type" "fpload")])
6051 \f
6052 ;; Define the DImode operations that can be done in a small number
6053 ;; of instructions. The & constraints are to prevent the register
6054 ;; allocator from allocating registers that overlap with the inputs
6055 ;; (for example, having an input in 7,8 and an output in 6,7). We
6056 ;; also allow for the output being the same as one of the inputs.
6058 (define_insn "*adddi3_noppc64"
6059 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6060 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6061 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6062 "! TARGET_POWERPC64"
6063 "*
6064 {
6065 if (WORDS_BIG_ENDIAN)
6066 return (GET_CODE (operands[2])) != CONST_INT
6067 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6068 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6069 else
6070 return (GET_CODE (operands[2])) != CONST_INT
6071 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6072 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6073 }"
6074 [(set_attr "type" "two")
6075 (set_attr "length" "8")])
6077 (define_insn "*subdi3_noppc64"
6078 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6079 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6080 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6081 "! TARGET_POWERPC64"
6082 "*
6083 {
6084 if (WORDS_BIG_ENDIAN)
6085 return (GET_CODE (operands[1]) != CONST_INT)
6086 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6087 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6088 else
6089 return (GET_CODE (operands[1]) != CONST_INT)
6090 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6091 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6092 }"
6093 [(set_attr "type" "two")
6094 (set_attr "length" "8")])
6096 (define_insn "*negdi2_noppc64"
6097 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6098 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6099 "! TARGET_POWERPC64"
6100 "*
6101 {
6102 return (WORDS_BIG_ENDIAN)
6103 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6104 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6105 }"
6106 [(set_attr "type" "two")
6107 (set_attr "length" "8")])
6109 (define_insn "mulsidi3"
6110 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6111 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6112 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6113 "! TARGET_POWERPC64"
6114 {
6115 return (WORDS_BIG_ENDIAN)
6116 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6117 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6118 }
6119 [(set_attr "type" "imul")
6120 (set_attr "length" "8")])
6122 (define_split
6123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6124 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6125 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6126 "! TARGET_POWERPC64 && reload_completed"
6127 [(set (match_dup 3)
6128 (truncate:SI
6129 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6130 (sign_extend:DI (match_dup 2)))
6131 (const_int 32))))
6132 (set (match_dup 4)
6133 (mult:SI (match_dup 1)
6134 (match_dup 2)))]
6135 "
6136 {
6137 int endian = (WORDS_BIG_ENDIAN == 0);
6138 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6139 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6140 }")
6142 (define_insn "umulsidi3"
6143 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6144 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6145 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6146 "! TARGET_POWERPC64"
6147 "*
6148 {
6149 return (WORDS_BIG_ENDIAN)
6150 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6151 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6152 }"
6153 [(set_attr "type" "imul")
6154 (set_attr "length" "8")])
6156 (define_split
6157 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6158 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6159 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6160 "! TARGET_POWERPC64 && reload_completed"
6161 [(set (match_dup 3)
6162 (truncate:SI
6163 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6164 (zero_extend:DI (match_dup 2)))
6165 (const_int 32))))
6166 (set (match_dup 4)
6167 (mult:SI (match_dup 1)
6168 (match_dup 2)))]
6169 "
6170 {
6171 int endian = (WORDS_BIG_ENDIAN == 0);
6172 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6173 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6174 }")
6176 (define_insn "smulsi3_highpart"
6177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6178 (truncate:SI
6179 (lshiftrt:DI (mult:DI (sign_extend:DI
6180 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6181 (sign_extend:DI
6182 (match_operand:SI 2 "gpc_reg_operand" "r")))
6183 (const_int 32))))]
6184 ""
6185 "mulhw %0,%1,%2"
6186 [(set_attr "type" "imul")])
6188 (define_insn "umulsi3_highpart"
6189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6190 (truncate:SI
6191 (lshiftrt:DI (mult:DI (zero_extend:DI
6192 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6193 (zero_extend:DI
6194 (match_operand:SI 2 "gpc_reg_operand" "r")))
6195 (const_int 32))))]
6196 ""
6197 "mulhwu %0,%1,%2"
6198 [(set_attr "type" "imul")])
6200 ;; Shift by a variable amount is too complex to be worth open-coding. We
6201 ;; just handle shifts by constants.
6202 (define_insn "ashrdi3_no_power"
6203 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6204 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6205 (match_operand:SI 2 "const_int_operand" "M,i")))]
6206 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6207 "@
6208 srawi %0,%1,31\;srawi %L0,%1,%h2
6209 srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2"
6210 [(set_attr "type" "two,three")
6211 (set_attr "length" "8,12")])
6213 (define_insn "*ashrdisi3_noppc64"
6214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6215 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6216 (const_int 32)) 4))]
6217 "TARGET_32BIT && !TARGET_POWERPC64"
6218 "*
6219 {
6220 if (REGNO (operands[0]) == REGNO (operands[1]))
6221 return \"\";
6222 else
6223 return \"mr %0,%1\";
6224 }"
6225 [(set_attr "length" "4")])
6227 \f
6228 ;; PowerPC64 DImode operations.
6230 (define_insn "muldi3"
6231 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6232 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6233 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6234 "TARGET_POWERPC64"
6235 "@
6236 mulld %0,%1,%2
6237 mulli %0,%1,%2"
6238 [(set (attr "type")
6239 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6240 (const_string "imul3")
6241 (match_operand:SI 2 "short_cint_operand" "")
6242 (const_string "imul2")]
6243 (const_string "lmul")))])
6245 (define_insn "*muldi3_internal1"
6246 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6247 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6248 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6249 (const_int 0)))
6250 (clobber (match_scratch:DI 3 "=r,r"))]
6251 "TARGET_POWERPC64"
6252 "@
6253 mulld. %3,%1,%2
6254 #"
6255 [(set_attr "type" "lmul_compare")
6256 (set_attr "length" "4,8")])
6258 (define_split
6259 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6260 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6261 (match_operand:DI 2 "gpc_reg_operand" ""))
6262 (const_int 0)))
6263 (clobber (match_scratch:DI 3 ""))]
6264 "TARGET_POWERPC64 && reload_completed"
6265 [(set (match_dup 3)
6266 (mult:DI (match_dup 1) (match_dup 2)))
6267 (set (match_dup 0)
6268 (compare:CC (match_dup 3)
6269 (const_int 0)))]
6270 "")
6272 (define_insn "*muldi3_internal2"
6273 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6274 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6275 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6276 (const_int 0)))
6277 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6278 (mult:DI (match_dup 1) (match_dup 2)))]
6279 "TARGET_POWERPC64"
6280 "@
6281 mulld. %0,%1,%2
6282 #"
6283 [(set_attr "type" "lmul_compare")
6284 (set_attr "length" "4,8")])
6286 (define_split
6287 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6288 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6289 (match_operand:DI 2 "gpc_reg_operand" ""))
6290 (const_int 0)))
6291 (set (match_operand:DI 0 "gpc_reg_operand" "")
6292 (mult:DI (match_dup 1) (match_dup 2)))]
6293 "TARGET_POWERPC64 && reload_completed"
6294 [(set (match_dup 0)
6295 (mult:DI (match_dup 1) (match_dup 2)))
6296 (set (match_dup 3)
6297 (compare:CC (match_dup 0)
6298 (const_int 0)))]
6299 "")
6301 (define_insn "smuldi3_highpart"
6302 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6303 (truncate:DI
6304 (lshiftrt:TI (mult:TI (sign_extend:TI
6305 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6306 (sign_extend:TI
6307 (match_operand:DI 2 "gpc_reg_operand" "r")))
6308 (const_int 64))))]
6309 "TARGET_POWERPC64"
6310 "mulhd %0,%1,%2"
6311 [(set_attr "type" "lmul")])
6313 (define_insn "umuldi3_highpart"
6314 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6315 (truncate:DI
6316 (lshiftrt:TI (mult:TI (zero_extend:TI
6317 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6318 (zero_extend:TI
6319 (match_operand:DI 2 "gpc_reg_operand" "r")))
6320 (const_int 64))))]
6321 "TARGET_POWERPC64"
6322 "mulhdu %0,%1,%2"
6323 [(set_attr "type" "lmul")])
6325 (define_insn "rotldi3"
6326 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6327 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6328 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6329 "TARGET_POWERPC64"
6330 "@
6331 rldcl %0,%1,%2,0
6332 rldicl %0,%1,%H2,0"
6333 [(set_attr "type" "var_shift_rotate,integer")])
6335 (define_insn "*rotldi3_internal2"
6336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6337 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6338 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6339 (const_int 0)))
6340 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6341 "TARGET_64BIT"
6342 "@
6343 rldcl. %3,%1,%2,0
6344 rldicl. %3,%1,%H2,0
6345 #
6346 #"
6347 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6348 (set_attr "length" "4,4,8,8")])
6350 (define_split
6351 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6352 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6353 (match_operand:DI 2 "reg_or_cint_operand" ""))
6354 (const_int 0)))
6355 (clobber (match_scratch:DI 3 ""))]
6356 "TARGET_POWERPC64 && reload_completed"
6357 [(set (match_dup 3)
6358 (rotate:DI (match_dup 1) (match_dup 2)))
6359 (set (match_dup 0)
6360 (compare:CC (match_dup 3)
6361 (const_int 0)))]
6362 "")
6364 (define_insn "*rotldi3_internal3"
6365 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6366 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6367 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6368 (const_int 0)))
6369 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6370 (rotate:DI (match_dup 1) (match_dup 2)))]
6371 "TARGET_64BIT"
6372 "@
6373 rldcl. %0,%1,%2,0
6374 rldicl. %0,%1,%H2,0
6375 #
6376 #"
6377 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6378 (set_attr "length" "4,4,8,8")])
6380 (define_split
6381 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6382 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6383 (match_operand:DI 2 "reg_or_cint_operand" ""))
6384 (const_int 0)))
6385 (set (match_operand:DI 0 "gpc_reg_operand" "")
6386 (rotate:DI (match_dup 1) (match_dup 2)))]
6387 "TARGET_POWERPC64 && reload_completed"
6388 [(set (match_dup 0)
6389 (rotate:DI (match_dup 1) (match_dup 2)))
6390 (set (match_dup 3)
6391 (compare:CC (match_dup 0)
6392 (const_int 0)))]
6393 "")
6395 (define_insn "*rotldi3_internal4"
6396 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6397 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6398 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6399 (match_operand:DI 3 "mask64_operand" "n,n")))]
6400 "TARGET_POWERPC64"
6401 "@
6402 rldc%B3 %0,%1,%2,%S3
6403 rldic%B3 %0,%1,%H2,%S3"
6404 [(set_attr "type" "var_shift_rotate,integer")])
6406 (define_insn "*rotldi3_internal5"
6407 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6408 (compare:CC (and:DI
6409 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6410 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6411 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6412 (const_int 0)))
6413 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6414 "TARGET_64BIT"
6415 "@
6416 rldc%B3. %4,%1,%2,%S3
6417 rldic%B3. %4,%1,%H2,%S3
6418 #
6419 #"
6420 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6421 (set_attr "length" "4,4,8,8")])
6423 (define_split
6424 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6425 (compare:CC (and:DI
6426 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6427 (match_operand:DI 2 "reg_or_cint_operand" ""))
6428 (match_operand:DI 3 "mask64_operand" ""))
6429 (const_int 0)))
6430 (clobber (match_scratch:DI 4 ""))]
6431 "TARGET_POWERPC64 && reload_completed"
6432 [(set (match_dup 4)
6433 (and:DI (rotate:DI (match_dup 1)
6434 (match_dup 2))
6435 (match_dup 3)))
6436 (set (match_dup 0)
6437 (compare:CC (match_dup 4)
6438 (const_int 0)))]
6439 "")
6441 (define_insn "*rotldi3_internal6"
6442 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6443 (compare:CC (and:DI
6444 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6445 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6446 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6447 (const_int 0)))
6448 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6449 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6450 "TARGET_64BIT"
6451 "@
6452 rldc%B3. %0,%1,%2,%S3
6453 rldic%B3. %0,%1,%H2,%S3
6454 #
6455 #"
6456 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6457 (set_attr "length" "4,4,8,8")])
6459 (define_split
6460 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6461 (compare:CC (and:DI
6462 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6463 (match_operand:DI 2 "reg_or_cint_operand" ""))
6464 (match_operand:DI 3 "mask64_operand" ""))
6465 (const_int 0)))
6466 (set (match_operand:DI 0 "gpc_reg_operand" "")
6467 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6468 "TARGET_POWERPC64 && reload_completed"
6469 [(set (match_dup 0)
6470 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6471 (set (match_dup 4)
6472 (compare:CC (match_dup 0)
6473 (const_int 0)))]
6474 "")
6476 (define_insn "*rotldi3_internal7"
6477 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6478 (zero_extend:DI
6479 (subreg:QI
6480 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6481 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6482 "TARGET_POWERPC64"
6483 "@
6484 rldcl %0,%1,%2,56
6485 rldicl %0,%1,%H2,56"
6486 [(set_attr "type" "var_shift_rotate,integer")])
6488 (define_insn "*rotldi3_internal8"
6489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6490 (compare:CC (zero_extend:DI
6491 (subreg:QI
6492 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6493 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6494 (const_int 0)))
6495 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6496 "TARGET_64BIT"
6497 "@
6498 rldcl. %3,%1,%2,56
6499 rldicl. %3,%1,%H2,56
6500 #
6501 #"
6502 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6503 (set_attr "length" "4,4,8,8")])
6505 (define_split
6506 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6507 (compare:CC (zero_extend:DI
6508 (subreg:QI
6509 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6510 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6511 (const_int 0)))
6512 (clobber (match_scratch:DI 3 ""))]
6513 "TARGET_POWERPC64 && reload_completed"
6514 [(set (match_dup 3)
6515 (zero_extend:DI (subreg:QI
6516 (rotate:DI (match_dup 1)
6517 (match_dup 2)) 0)))
6518 (set (match_dup 0)
6519 (compare:CC (match_dup 3)
6520 (const_int 0)))]
6521 "")
6523 (define_insn "*rotldi3_internal9"
6524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6525 (compare:CC (zero_extend:DI
6526 (subreg:QI
6527 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6528 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6529 (const_int 0)))
6530 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6531 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6532 "TARGET_64BIT"
6533 "@
6534 rldcl. %0,%1,%2,56
6535 rldicl. %0,%1,%H2,56
6536 #
6537 #"
6538 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6539 (set_attr "length" "4,4,8,8")])
6541 (define_split
6542 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6543 (compare:CC (zero_extend:DI
6544 (subreg:QI
6545 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6546 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6547 (const_int 0)))
6548 (set (match_operand:DI 0 "gpc_reg_operand" "")
6549 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6550 "TARGET_POWERPC64 && reload_completed"
6551 [(set (match_dup 0)
6552 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6553 (set (match_dup 3)
6554 (compare:CC (match_dup 0)
6555 (const_int 0)))]
6556 "")
6558 (define_insn "*rotldi3_internal10"
6559 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6560 (zero_extend:DI
6561 (subreg:HI
6562 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6563 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6564 "TARGET_POWERPC64"
6565 "@
6566 rldcl %0,%1,%2,48
6567 rldicl %0,%1,%H2,48"
6568 [(set_attr "type" "var_shift_rotate,integer")])
6570 (define_insn "*rotldi3_internal11"
6571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6572 (compare:CC (zero_extend:DI
6573 (subreg:HI
6574 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6575 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6576 (const_int 0)))
6577 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6578 "TARGET_64BIT"
6579 "@
6580 rldcl. %3,%1,%2,48
6581 rldicl. %3,%1,%H2,48
6582 #
6583 #"
6584 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6585 (set_attr "length" "4,4,8,8")])
6587 (define_split
6588 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6589 (compare:CC (zero_extend:DI
6590 (subreg:HI
6591 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6592 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6593 (const_int 0)))
6594 (clobber (match_scratch:DI 3 ""))]
6595 "TARGET_POWERPC64 && reload_completed"
6596 [(set (match_dup 3)
6597 (zero_extend:DI (subreg:HI
6598 (rotate:DI (match_dup 1)
6599 (match_dup 2)) 0)))
6600 (set (match_dup 0)
6601 (compare:CC (match_dup 3)
6602 (const_int 0)))]
6603 "")
6605 (define_insn "*rotldi3_internal12"
6606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6607 (compare:CC (zero_extend:DI
6608 (subreg:HI
6609 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6610 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6611 (const_int 0)))
6612 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6613 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6614 "TARGET_64BIT"
6615 "@
6616 rldcl. %0,%1,%2,48
6617 rldicl. %0,%1,%H2,48
6618 #
6619 #"
6620 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6621 (set_attr "length" "4,4,8,8")])
6623 (define_split
6624 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6625 (compare:CC (zero_extend:DI
6626 (subreg:HI
6627 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6628 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6629 (const_int 0)))
6630 (set (match_operand:DI 0 "gpc_reg_operand" "")
6631 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6632 "TARGET_POWERPC64 && reload_completed"
6633 [(set (match_dup 0)
6634 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6635 (set (match_dup 3)
6636 (compare:CC (match_dup 0)
6637 (const_int 0)))]
6638 "")
6640 (define_insn "*rotldi3_internal13"
6641 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6642 (zero_extend:DI
6643 (subreg:SI
6644 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6645 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6646 "TARGET_POWERPC64"
6647 "@
6648 rldcl %0,%1,%2,32
6649 rldicl %0,%1,%H2,32"
6650 [(set_attr "type" "var_shift_rotate,integer")])
6652 (define_insn "*rotldi3_internal14"
6653 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6654 (compare:CC (zero_extend:DI
6655 (subreg:SI
6656 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6657 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6658 (const_int 0)))
6659 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6660 "TARGET_64BIT"
6661 "@
6662 rldcl. %3,%1,%2,32
6663 rldicl. %3,%1,%H2,32
6664 #
6665 #"
6666 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6667 (set_attr "length" "4,4,8,8")])
6669 (define_split
6670 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6671 (compare:CC (zero_extend:DI
6672 (subreg:SI
6673 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6675 (const_int 0)))
6676 (clobber (match_scratch:DI 3 ""))]
6677 "TARGET_POWERPC64 && reload_completed"
6678 [(set (match_dup 3)
6679 (zero_extend:DI (subreg:SI
6680 (rotate:DI (match_dup 1)
6681 (match_dup 2)) 0)))
6682 (set (match_dup 0)
6683 (compare:CC (match_dup 3)
6684 (const_int 0)))]
6685 "")
6687 (define_insn "*rotldi3_internal15"
6688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6689 (compare:CC (zero_extend:DI
6690 (subreg:SI
6691 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6692 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6693 (const_int 0)))
6694 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6695 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6696 "TARGET_64BIT"
6697 "@
6698 rldcl. %0,%1,%2,32
6699 rldicl. %0,%1,%H2,32
6700 #
6701 #"
6702 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6703 (set_attr "length" "4,4,8,8")])
6705 (define_split
6706 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6707 (compare:CC (zero_extend:DI
6708 (subreg:SI
6709 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6710 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6711 (const_int 0)))
6712 (set (match_operand:DI 0 "gpc_reg_operand" "")
6713 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6714 "TARGET_POWERPC64 && reload_completed"
6715 [(set (match_dup 0)
6716 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6717 (set (match_dup 3)
6718 (compare:CC (match_dup 0)
6719 (const_int 0)))]
6720 "")
6722 (define_expand "ashldi3"
6723 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6724 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6725 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6726 "TARGET_POWERPC64"
6727 "")
6729 (define_insn "*ashldi3_internal1"
6730 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6731 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6732 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6733 "TARGET_POWERPC64"
6734 "@
6735 sld %0,%1,%2
6736 sldi %0,%1,%H2"
6737 [(set_attr "type" "var_shift_rotate,shift")])
6739 (define_insn "*ashldi3_internal2"
6740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6741 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6742 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6743 (const_int 0)))
6744 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6745 "TARGET_64BIT"
6746 "@
6747 sld. %3,%1,%2
6748 sldi. %3,%1,%H2
6749 #
6750 #"
6751 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6752 (set_attr "length" "4,4,8,8")])
6754 (define_split
6755 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6756 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6757 (match_operand:SI 2 "reg_or_cint_operand" ""))
6758 (const_int 0)))
6759 (clobber (match_scratch:DI 3 ""))]
6760 "TARGET_POWERPC64 && reload_completed"
6761 [(set (match_dup 3)
6762 (ashift:DI (match_dup 1) (match_dup 2)))
6763 (set (match_dup 0)
6764 (compare:CC (match_dup 3)
6765 (const_int 0)))]
6766 "")
6768 (define_insn "*ashldi3_internal3"
6769 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6770 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6772 (const_int 0)))
6773 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6774 (ashift:DI (match_dup 1) (match_dup 2)))]
6775 "TARGET_64BIT"
6776 "@
6777 sld. %0,%1,%2
6778 sldi. %0,%1,%H2
6779 #
6780 #"
6781 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6782 (set_attr "length" "4,4,8,8")])
6784 (define_split
6785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6786 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:SI 2 "reg_or_cint_operand" ""))
6788 (const_int 0)))
6789 (set (match_operand:DI 0 "gpc_reg_operand" "")
6790 (ashift:DI (match_dup 1) (match_dup 2)))]
6791 "TARGET_POWERPC64 && reload_completed"
6792 [(set (match_dup 0)
6793 (ashift:DI (match_dup 1) (match_dup 2)))
6794 (set (match_dup 3)
6795 (compare:CC (match_dup 0)
6796 (const_int 0)))]
6797 "")
6799 (define_insn "*ashldi3_internal4"
6800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6801 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6802 (match_operand:SI 2 "const_int_operand" "i"))
6803 (match_operand:DI 3 "const_int_operand" "n")))]
6804 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6805 "rldic %0,%1,%H2,%W3")
6807 (define_insn "ashldi3_internal5"
6808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6809 (compare:CC
6810 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6811 (match_operand:SI 2 "const_int_operand" "i,i"))
6812 (match_operand:DI 3 "const_int_operand" "n,n"))
6813 (const_int 0)))
6814 (clobber (match_scratch:DI 4 "=r,r"))]
6815 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6816 "@
6817 rldic. %4,%1,%H2,%W3
6818 #"
6819 [(set_attr "type" "compare")
6820 (set_attr "length" "4,8")])
6822 (define_split
6823 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6824 (compare:CC
6825 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6826 (match_operand:SI 2 "const_int_operand" ""))
6827 (match_operand:DI 3 "const_int_operand" ""))
6828 (const_int 0)))
6829 (clobber (match_scratch:DI 4 ""))]
6830 "TARGET_POWERPC64 && reload_completed
6831 && includes_rldic_lshift_p (operands[2], operands[3])"
6832 [(set (match_dup 4)
6833 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6834 (match_dup 3)))
6835 (set (match_dup 0)
6836 (compare:CC (match_dup 4)
6837 (const_int 0)))]
6838 "")
6840 (define_insn "*ashldi3_internal6"
6841 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6842 (compare:CC
6843 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6844 (match_operand:SI 2 "const_int_operand" "i,i"))
6845 (match_operand:DI 3 "const_int_operand" "n,n"))
6846 (const_int 0)))
6847 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6848 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6849 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6850 "@
6851 rldic. %0,%1,%H2,%W3
6852 #"
6853 [(set_attr "type" "compare")
6854 (set_attr "length" "4,8")])
6856 (define_split
6857 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6858 (compare:CC
6859 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6860 (match_operand:SI 2 "const_int_operand" ""))
6861 (match_operand:DI 3 "const_int_operand" ""))
6862 (const_int 0)))
6863 (set (match_operand:DI 0 "gpc_reg_operand" "")
6864 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6865 "TARGET_POWERPC64 && reload_completed
6866 && includes_rldic_lshift_p (operands[2], operands[3])"
6867 [(set (match_dup 0)
6868 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6869 (match_dup 3)))
6870 (set (match_dup 4)
6871 (compare:CC (match_dup 0)
6872 (const_int 0)))]
6873 "")
6875 (define_insn "*ashldi3_internal7"
6876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6877 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6878 (match_operand:SI 2 "const_int_operand" "i"))
6879 (match_operand:DI 3 "mask64_operand" "n")))]
6880 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6881 "rldicr %0,%1,%H2,%S3")
6883 (define_insn "ashldi3_internal8"
6884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6885 (compare:CC
6886 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6887 (match_operand:SI 2 "const_int_operand" "i,i"))
6888 (match_operand:DI 3 "mask64_operand" "n,n"))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 4 "=r,r"))]
6891 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6892 "@
6893 rldicr. %4,%1,%H2,%S3
6894 #"
6895 [(set_attr "type" "compare")
6896 (set_attr "length" "4,8")])
6898 (define_split
6899 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6900 (compare:CC
6901 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6902 (match_operand:SI 2 "const_int_operand" ""))
6903 (match_operand:DI 3 "mask64_operand" ""))
6904 (const_int 0)))
6905 (clobber (match_scratch:DI 4 ""))]
6906 "TARGET_POWERPC64 && reload_completed
6907 && includes_rldicr_lshift_p (operands[2], operands[3])"
6908 [(set (match_dup 4)
6909 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6910 (match_dup 3)))
6911 (set (match_dup 0)
6912 (compare:CC (match_dup 4)
6913 (const_int 0)))]
6914 "")
6916 (define_insn "*ashldi3_internal9"
6917 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6918 (compare:CC
6919 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6920 (match_operand:SI 2 "const_int_operand" "i,i"))
6921 (match_operand:DI 3 "mask64_operand" "n,n"))
6922 (const_int 0)))
6923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6924 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6925 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6926 "@
6927 rldicr. %0,%1,%H2,%S3
6928 #"
6929 [(set_attr "type" "compare")
6930 (set_attr "length" "4,8")])
6932 (define_split
6933 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6934 (compare:CC
6935 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6936 (match_operand:SI 2 "const_int_operand" ""))
6937 (match_operand:DI 3 "mask64_operand" ""))
6938 (const_int 0)))
6939 (set (match_operand:DI 0 "gpc_reg_operand" "")
6940 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6941 "TARGET_POWERPC64 && reload_completed
6942 && includes_rldicr_lshift_p (operands[2], operands[3])"
6943 [(set (match_dup 0)
6944 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6945 (match_dup 3)))
6946 (set (match_dup 4)
6947 (compare:CC (match_dup 0)
6948 (const_int 0)))]
6949 "")
6951 (define_expand "lshrdi3"
6952 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6953 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6954 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6955 "TARGET_POWERPC64"
6956 "")
6958 (define_insn "*lshrdi3_internal1"
6959 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6960 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6961 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6962 "TARGET_POWERPC64"
6963 "@
6964 srd %0,%1,%2
6965 srdi %0,%1,%H2"
6966 [(set_attr "type" "var_shift_rotate,shift")])
6968 (define_insn "*lshrdi3_internal2"
6969 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6970 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6971 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6972 (const_int 0)))
6973 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6974 "TARGET_64BIT "
6975 "@
6976 srd. %3,%1,%2
6977 srdi. %3,%1,%H2
6978 #
6979 #"
6980 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6981 (set_attr "length" "4,4,8,8")])
6983 (define_split
6984 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6985 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:SI 2 "reg_or_cint_operand" ""))
6987 (const_int 0)))
6988 (clobber (match_scratch:DI 3 ""))]
6989 "TARGET_POWERPC64 && reload_completed"
6990 [(set (match_dup 3)
6991 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6992 (set (match_dup 0)
6993 (compare:CC (match_dup 3)
6994 (const_int 0)))]
6995 "")
6997 (define_insn "*lshrdi3_internal3"
6998 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6999 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7000 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7001 (const_int 0)))
7002 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7003 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7004 "TARGET_64BIT"
7005 "@
7006 srd. %0,%1,%2
7007 srdi. %0,%1,%H2
7008 #
7009 #"
7010 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7011 (set_attr "length" "4,4,8,8")])
7013 (define_split
7014 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7015 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7016 (match_operand:SI 2 "reg_or_cint_operand" ""))
7017 (const_int 0)))
7018 (set (match_operand:DI 0 "gpc_reg_operand" "")
7019 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7020 "TARGET_POWERPC64 && reload_completed"
7021 [(set (match_dup 0)
7022 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7023 (set (match_dup 3)
7024 (compare:CC (match_dup 0)
7025 (const_int 0)))]
7026 "")
7028 (define_expand "ashrdi3"
7029 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7030 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7031 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7032 "WORDS_BIG_ENDIAN"
7033 "
7034 {
7035 if (TARGET_POWERPC64)
7036 ;
7037 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7038 && WORDS_BIG_ENDIAN)
7039 {
7040 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7041 DONE;
7042 }
7043 else
7044 FAIL;
7045 }")
7047 (define_insn "*ashrdi3_internal1"
7048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7049 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7050 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7051 "TARGET_POWERPC64"
7052 "@
7053 srad %0,%1,%2
7054 sradi %0,%1,%H2"
7055 [(set_attr "type" "var_shift_rotate,shift")])
7057 (define_insn "*ashrdi3_internal2"
7058 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7059 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7060 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7061 (const_int 0)))
7062 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7063 "TARGET_64BIT"
7064 "@
7065 srad. %3,%1,%2
7066 sradi. %3,%1,%H2
7067 #
7068 #"
7069 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7070 (set_attr "length" "4,4,8,8")])
7072 (define_split
7073 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7074 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7075 (match_operand:SI 2 "reg_or_cint_operand" ""))
7076 (const_int 0)))
7077 (clobber (match_scratch:DI 3 ""))]
7078 "TARGET_POWERPC64 && reload_completed"
7079 [(set (match_dup 3)
7080 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7081 (set (match_dup 0)
7082 (compare:CC (match_dup 3)
7083 (const_int 0)))]
7084 "")
7086 (define_insn "*ashrdi3_internal3"
7087 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7088 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7089 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7090 (const_int 0)))
7091 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7092 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7093 "TARGET_64BIT"
7094 "@
7095 srad. %0,%1,%2
7096 sradi. %0,%1,%H2
7097 #
7098 #"
7099 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7100 (set_attr "length" "4,4,8,8")])
7102 (define_split
7103 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7104 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7105 (match_operand:SI 2 "reg_or_cint_operand" ""))
7106 (const_int 0)))
7107 (set (match_operand:DI 0 "gpc_reg_operand" "")
7108 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7109 "TARGET_POWERPC64 && reload_completed"
7110 [(set (match_dup 0)
7111 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7112 (set (match_dup 3)
7113 (compare:CC (match_dup 0)
7114 (const_int 0)))]
7115 "")
7117 (define_expand "anddi3"
7118 [(parallel
7119 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7120 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7121 (match_operand:DI 2 "and64_2_operand" "")))
7122 (clobber (match_scratch:CC 3 ""))])]
7123 "TARGET_POWERPC64"
7124 "")
7126 (define_insn "anddi3_mc"
7127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7128 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7129 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7130 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7131 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7132 "@
7133 and %0,%1,%2
7134 rldic%B2 %0,%1,0,%S2
7135 rlwinm %0,%1,0,%m2,%M2
7136 andi. %0,%1,%b2
7137 andis. %0,%1,%u2
7138 #"
7139 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7140 (set_attr "length" "4,4,4,4,4,8")])
7142 (define_insn "anddi3_nomc"
7143 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7144 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7145 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7146 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7147 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7148 "@
7149 and %0,%1,%2
7150 rldic%B2 %0,%1,0,%S2
7151 rlwinm %0,%1,0,%m2,%M2
7152 #"
7153 [(set_attr "length" "4,4,4,8")])
7155 (define_split
7156 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7157 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7158 (match_operand:DI 2 "mask64_2_operand" "")))
7159 (clobber (match_scratch:CC 3 ""))]
7160 "TARGET_POWERPC64
7161 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7162 && !mask_operand (operands[2], DImode)
7163 && !mask64_operand (operands[2], DImode)"
7164 [(set (match_dup 0)
7165 (and:DI (rotate:DI (match_dup 1)
7166 (match_dup 4))
7167 (match_dup 5)))
7168 (set (match_dup 0)
7169 (and:DI (rotate:DI (match_dup 0)
7170 (match_dup 6))
7171 (match_dup 7)))]
7172 {
7173 build_mask64_2_operands (operands[2], &operands[4]);
7174 })
7176 (define_insn "*anddi3_internal2_mc"
7177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7178 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7179 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7180 (const_int 0)))
7181 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7182 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7183 "TARGET_64BIT && rs6000_gen_cell_microcode"
7184 "@
7185 and. %3,%1,%2
7186 rldic%B2. %3,%1,0,%S2
7187 rlwinm. %3,%1,0,%m2,%M2
7188 andi. %3,%1,%b2
7189 andis. %3,%1,%u2
7190 #
7191 #
7192 #
7193 #
7194 #
7195 #
7196 #"
7197 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7198 fast_compare,compare,compare,compare,compare,compare,\
7199 compare,compare")
7200 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7202 (define_split
7203 [(set (match_operand:CC 0 "cc_reg_operand" "")
7204 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7205 (match_operand:DI 2 "mask64_2_operand" ""))
7206 (const_int 0)))
7207 (clobber (match_scratch:DI 3 ""))
7208 (clobber (match_scratch:CC 4 ""))]
7209 "TARGET_64BIT && reload_completed
7210 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7211 && !mask_operand (operands[2], DImode)
7212 && !mask64_operand (operands[2], DImode)"
7213 [(set (match_dup 3)
7214 (and:DI (rotate:DI (match_dup 1)
7215 (match_dup 5))
7216 (match_dup 6)))
7217 (parallel [(set (match_dup 0)
7218 (compare:CC (and:DI (rotate:DI (match_dup 3)
7219 (match_dup 7))
7220 (match_dup 8))
7221 (const_int 0)))
7222 (clobber (match_dup 3))])]
7223 "
7224 {
7225 build_mask64_2_operands (operands[2], &operands[5]);
7226 }")
7228 (define_insn "*anddi3_internal3_mc"
7229 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7230 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7231 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7232 (const_int 0)))
7233 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7234 (and:DI (match_dup 1) (match_dup 2)))
7235 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7236 "TARGET_64BIT && rs6000_gen_cell_microcode"
7237 "@
7238 and. %0,%1,%2
7239 rldic%B2. %0,%1,0,%S2
7240 rlwinm. %0,%1,0,%m2,%M2
7241 andi. %0,%1,%b2
7242 andis. %0,%1,%u2
7243 #
7244 #
7245 #
7246 #
7247 #
7248 #
7249 #"
7250 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7251 fast_compare,compare,compare,compare,compare,compare,\
7252 compare,compare")
7253 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7255 (define_split
7256 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7257 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7258 (match_operand:DI 2 "and64_2_operand" ""))
7259 (const_int 0)))
7260 (set (match_operand:DI 0 "gpc_reg_operand" "")
7261 (and:DI (match_dup 1) (match_dup 2)))
7262 (clobber (match_scratch:CC 4 ""))]
7263 "TARGET_64BIT && reload_completed"
7264 [(parallel [(set (match_dup 0)
7265 (and:DI (match_dup 1) (match_dup 2)))
7266 (clobber (match_dup 4))])
7267 (set (match_dup 3)
7268 (compare:CC (match_dup 0)
7269 (const_int 0)))]
7270 "")
7272 (define_split
7273 [(set (match_operand:CC 3 "cc_reg_operand" "")
7274 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7275 (match_operand:DI 2 "mask64_2_operand" ""))
7276 (const_int 0)))
7277 (set (match_operand:DI 0 "gpc_reg_operand" "")
7278 (and:DI (match_dup 1) (match_dup 2)))
7279 (clobber (match_scratch:CC 4 ""))]
7280 "TARGET_64BIT && reload_completed
7281 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7282 && !mask_operand (operands[2], DImode)
7283 && !mask64_operand (operands[2], DImode)"
7284 [(set (match_dup 0)
7285 (and:DI (rotate:DI (match_dup 1)
7286 (match_dup 5))
7287 (match_dup 6)))
7288 (parallel [(set (match_dup 3)
7289 (compare:CC (and:DI (rotate:DI (match_dup 0)
7290 (match_dup 7))
7291 (match_dup 8))
7292 (const_int 0)))
7293 (set (match_dup 0)
7294 (and:DI (rotate:DI (match_dup 0)
7295 (match_dup 7))
7296 (match_dup 8)))])]
7297 "
7298 {
7299 build_mask64_2_operands (operands[2], &operands[5]);
7300 }")
7302 (define_expand "iordi3"
7303 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7304 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7305 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7306 "TARGET_POWERPC64"
7307 "
7308 {
7309 if (non_logical_cint_operand (operands[2], DImode))
7310 {
7311 HOST_WIDE_INT value;
7312 rtx tmp = ((!can_create_pseudo_p ()
7313 || rtx_equal_p (operands[0], operands[1]))
7314 ? operands[0] : gen_reg_rtx (DImode));
7316 if (GET_CODE (operands[2]) == CONST_INT)
7317 {
7318 value = INTVAL (operands[2]);
7319 emit_insn (gen_iordi3 (tmp, operands[1],
7320 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7321 }
7322 else
7323 {
7324 value = CONST_DOUBLE_LOW (operands[2]);
7325 emit_insn (gen_iordi3 (tmp, operands[1],
7326 immed_double_const (value
7327 & (~ (HOST_WIDE_INT) 0xffff),
7328 0, DImode)));
7329 }
7331 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7332 DONE;
7333 }
7334 }")
7336 (define_expand "xordi3"
7337 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7338 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7339 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7340 "TARGET_POWERPC64"
7341 "
7342 {
7343 if (non_logical_cint_operand (operands[2], DImode))
7344 {
7345 HOST_WIDE_INT value;
7346 rtx tmp = ((!can_create_pseudo_p ()
7347 || rtx_equal_p (operands[0], operands[1]))
7348 ? operands[0] : gen_reg_rtx (DImode));
7350 if (GET_CODE (operands[2]) == CONST_INT)
7351 {
7352 value = INTVAL (operands[2]);
7353 emit_insn (gen_xordi3 (tmp, operands[1],
7354 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7355 }
7356 else
7357 {
7358 value = CONST_DOUBLE_LOW (operands[2]);
7359 emit_insn (gen_xordi3 (tmp, operands[1],
7360 immed_double_const (value
7361 & (~ (HOST_WIDE_INT) 0xffff),
7362 0, DImode)));
7363 }
7365 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7366 DONE;
7367 }
7368 }")
7370 (define_insn "*booldi3_internal1"
7371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7372 (match_operator:DI 3 "boolean_or_operator"
7373 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7374 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7375 "TARGET_POWERPC64"
7376 "@
7377 %q3 %0,%1,%2
7378 %q3i %0,%1,%b2
7379 %q3is %0,%1,%u2")
7381 (define_insn "*booldi3_internal2"
7382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7383 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7384 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7385 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7386 (const_int 0)))
7387 (clobber (match_scratch:DI 3 "=r,r"))]
7388 "TARGET_64BIT"
7389 "@
7390 %q4. %3,%1,%2
7391 #"
7392 [(set_attr "type" "fast_compare,compare")
7393 (set_attr "length" "4,8")])
7395 (define_split
7396 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7397 (compare:CC (match_operator:DI 4 "boolean_operator"
7398 [(match_operand:DI 1 "gpc_reg_operand" "")
7399 (match_operand:DI 2 "gpc_reg_operand" "")])
7400 (const_int 0)))
7401 (clobber (match_scratch:DI 3 ""))]
7402 "TARGET_POWERPC64 && reload_completed"
7403 [(set (match_dup 3) (match_dup 4))
7404 (set (match_dup 0)
7405 (compare:CC (match_dup 3)
7406 (const_int 0)))]
7407 "")
7409 (define_insn "*booldi3_internal3"
7410 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7411 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7412 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7413 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7414 (const_int 0)))
7415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7416 (match_dup 4))]
7417 "TARGET_64BIT"
7418 "@
7419 %q4. %0,%1,%2
7420 #"
7421 [(set_attr "type" "fast_compare,compare")
7422 (set_attr "length" "4,8")])
7424 (define_split
7425 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7426 (compare:CC (match_operator:DI 4 "boolean_operator"
7427 [(match_operand:DI 1 "gpc_reg_operand" "")
7428 (match_operand:DI 2 "gpc_reg_operand" "")])
7429 (const_int 0)))
7430 (set (match_operand:DI 0 "gpc_reg_operand" "")
7431 (match_dup 4))]
7432 "TARGET_POWERPC64 && reload_completed"
7433 [(set (match_dup 0) (match_dup 4))
7434 (set (match_dup 3)
7435 (compare:CC (match_dup 0)
7436 (const_int 0)))]
7437 "")
7439 ;; Split a logical operation that we can't do in one insn into two insns,
7440 ;; each of which does one 16-bit part. This is used by combine.
7442 (define_split
7443 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7444 (match_operator:DI 3 "boolean_or_operator"
7445 [(match_operand:DI 1 "gpc_reg_operand" "")
7446 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7447 "TARGET_POWERPC64"
7448 [(set (match_dup 0) (match_dup 4))
7449 (set (match_dup 0) (match_dup 5))]
7450 "
7451 {
7452 rtx i3,i4;
7454 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7455 {
7456 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7457 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7458 0, DImode);
7459 i4 = GEN_INT (value & 0xffff);
7460 }
7461 else
7462 {
7463 i3 = GEN_INT (INTVAL (operands[2])
7464 & (~ (HOST_WIDE_INT) 0xffff));
7465 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7466 }
7467 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7468 operands[1], i3);
7469 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7470 operands[0], i4);
7471 }")
7473 (define_insn "*boolcdi3_internal1"
7474 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7475 (match_operator:DI 3 "boolean_operator"
7476 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7477 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7478 "TARGET_POWERPC64"
7479 "%q3 %0,%2,%1")
7481 (define_insn "*boolcdi3_internal2"
7482 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7483 (compare:CC (match_operator:DI 4 "boolean_operator"
7484 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7485 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7486 (const_int 0)))
7487 (clobber (match_scratch:DI 3 "=r,r"))]
7488 "TARGET_64BIT"
7489 "@
7490 %q4. %3,%2,%1
7491 #"
7492 [(set_attr "type" "fast_compare,compare")
7493 (set_attr "length" "4,8")])
7495 (define_split
7496 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7497 (compare:CC (match_operator:DI 4 "boolean_operator"
7498 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7499 (match_operand:DI 2 "gpc_reg_operand" "")])
7500 (const_int 0)))
7501 (clobber (match_scratch:DI 3 ""))]
7502 "TARGET_POWERPC64 && reload_completed"
7503 [(set (match_dup 3) (match_dup 4))
7504 (set (match_dup 0)
7505 (compare:CC (match_dup 3)
7506 (const_int 0)))]
7507 "")
7509 (define_insn "*boolcdi3_internal3"
7510 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7511 (compare:CC (match_operator:DI 4 "boolean_operator"
7512 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7513 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7514 (const_int 0)))
7515 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7516 (match_dup 4))]
7517 "TARGET_64BIT"
7518 "@
7519 %q4. %0,%2,%1
7520 #"
7521 [(set_attr "type" "fast_compare,compare")
7522 (set_attr "length" "4,8")])
7524 (define_split
7525 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7526 (compare:CC (match_operator:DI 4 "boolean_operator"
7527 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7528 (match_operand:DI 2 "gpc_reg_operand" "")])
7529 (const_int 0)))
7530 (set (match_operand:DI 0 "gpc_reg_operand" "")
7531 (match_dup 4))]
7532 "TARGET_POWERPC64 && reload_completed"
7533 [(set (match_dup 0) (match_dup 4))
7534 (set (match_dup 3)
7535 (compare:CC (match_dup 0)
7536 (const_int 0)))]
7537 "")
7539 (define_insn "*boolccdi3_internal1"
7540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7541 (match_operator:DI 3 "boolean_operator"
7542 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7543 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7544 "TARGET_POWERPC64"
7545 "%q3 %0,%1,%2")
7547 (define_insn "*boolccdi3_internal2"
7548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7549 (compare:CC (match_operator:DI 4 "boolean_operator"
7550 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7551 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7552 (const_int 0)))
7553 (clobber (match_scratch:DI 3 "=r,r"))]
7554 "TARGET_64BIT"
7555 "@
7556 %q4. %3,%1,%2
7557 #"
7558 [(set_attr "type" "fast_compare,compare")
7559 (set_attr "length" "4,8")])
7561 (define_split
7562 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7563 (compare:CC (match_operator:DI 4 "boolean_operator"
7564 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7565 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7566 (const_int 0)))
7567 (clobber (match_scratch:DI 3 ""))]
7568 "TARGET_POWERPC64 && reload_completed"
7569 [(set (match_dup 3) (match_dup 4))
7570 (set (match_dup 0)
7571 (compare:CC (match_dup 3)
7572 (const_int 0)))]
7573 "")
7575 (define_insn "*boolccdi3_internal3"
7576 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7577 (compare:CC (match_operator:DI 4 "boolean_operator"
7578 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7579 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7580 (const_int 0)))
7581 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7582 (match_dup 4))]
7583 "TARGET_64BIT"
7584 "@
7585 %q4. %0,%1,%2
7586 #"
7587 [(set_attr "type" "fast_compare,compare")
7588 (set_attr "length" "4,8")])
7590 (define_split
7591 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7592 (compare:CC (match_operator:DI 4 "boolean_operator"
7593 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7594 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7595 (const_int 0)))
7596 (set (match_operand:DI 0 "gpc_reg_operand" "")
7597 (match_dup 4))]
7598 "TARGET_POWERPC64 && reload_completed"
7599 [(set (match_dup 0) (match_dup 4))
7600 (set (match_dup 3)
7601 (compare:CC (match_dup 0)
7602 (const_int 0)))]
7603 "")
7604 \f
7605 ;; Now define ways of moving data around.
7607 ;; Set up a register with a value from the GOT table
7609 (define_expand "movsi_got"
7610 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7611 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7612 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7613 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7614 "
7615 {
7616 if (GET_CODE (operands[1]) == CONST)
7617 {
7618 rtx offset = const0_rtx;
7619 HOST_WIDE_INT value;
7621 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7622 value = INTVAL (offset);
7623 if (value != 0)
7624 {
7625 rtx tmp = (!can_create_pseudo_p ()
7626 ? operands[0]
7627 : gen_reg_rtx (Pmode));
7628 emit_insn (gen_movsi_got (tmp, operands[1]));
7629 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7630 DONE;
7631 }
7632 }
7634 operands[2] = rs6000_got_register (operands[1]);
7635 }")
7637 (define_insn "*movsi_got_internal"
7638 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7639 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7640 (match_operand:SI 2 "gpc_reg_operand" "b")]
7641 UNSPEC_MOVSI_GOT))]
7642 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7643 "lwz %0,%a1@got(%2)"
7644 [(set_attr "type" "load")])
7646 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7647 ;; didn't get allocated to a hard register.
7648 (define_split
7649 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7650 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7651 (match_operand:SI 2 "memory_operand" "")]
7652 UNSPEC_MOVSI_GOT))]
7653 "DEFAULT_ABI == ABI_V4
7654 && flag_pic == 1
7655 && (reload_in_progress || reload_completed)"
7656 [(set (match_dup 0) (match_dup 2))
7657 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7658 UNSPEC_MOVSI_GOT))]
7659 "")
7661 ;; For SI, we special-case integers that can't be loaded in one insn. We
7662 ;; do the load 16-bits at a time. We could do this by loading from memory,
7663 ;; and this is even supposed to be faster, but it is simpler not to get
7664 ;; integers in the TOC.
7665 (define_insn "movsi_low"
7666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7667 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7668 (match_operand 2 "" ""))))]
7669 "TARGET_MACHO && ! TARGET_64BIT"
7670 "lwz %0,lo16(%2)(%1)"
7671 [(set_attr "type" "load")
7672 (set_attr "length" "4")])
7674 (define_insn "*movsi_internal1"
7675 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7676 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7677 "!TARGET_SINGLE_FPU &&
7678 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7679 "@
7680 mr %0,%1
7681 la %0,%a1
7682 lwz%U1%X1 %0,%1
7683 stw%U0%X0 %1,%0
7684 li %0,%1
7685 lis %0,%v1
7686 #
7687 mf%1 %0
7688 mt%0 %1
7689 mt%0 %1
7690 nop"
7691 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7692 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7694 (define_insn "*movsi_internal1_single"
7695 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7696 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7697 "TARGET_SINGLE_FPU &&
7698 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7699 "@
7700 mr %0,%1
7701 la %0,%a1
7702 lwz%U1%X1 %0,%1
7703 stw%U0%X0 %1,%0
7704 li %0,%1
7705 lis %0,%v1
7706 #
7707 mf%1 %0
7708 mt%0 %1
7709 mt%0 %1
7710 nop
7711 stfs%U0%X0 %1,%0
7712 lfs%U1%X1 %0,%1"
7713 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
7714 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7716 ;; Split a load of a large constant into the appropriate two-insn
7717 ;; sequence.
7719 (define_split
7720 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7721 (match_operand:SI 1 "const_int_operand" ""))]
7722 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7723 && (INTVAL (operands[1]) & 0xffff) != 0"
7724 [(set (match_dup 0)
7725 (match_dup 2))
7726 (set (match_dup 0)
7727 (ior:SI (match_dup 0)
7728 (match_dup 3)))]
7729 "
7730 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7732 if (tem == operands[0])
7733 DONE;
7734 else
7735 FAIL;
7736 }")
7738 (define_insn "*mov<mode>_internal2"
7739 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7740 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7741 (const_int 0)))
7742 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7743 ""
7744 "@
7745 cmp<wd>i %2,%0,0
7746 mr. %0,%1
7747 #"
7748 [(set_attr "type" "cmp,compare,cmp")
7749 (set_attr "length" "4,4,8")])
7751 (define_split
7752 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7753 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7754 (const_int 0)))
7755 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7756 "reload_completed"
7757 [(set (match_dup 0) (match_dup 1))
7758 (set (match_dup 2)
7759 (compare:CC (match_dup 0)
7760 (const_int 0)))]
7761 "")
7762 \f
7763 (define_insn "*movhi_internal"
7764 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7765 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7766 "gpc_reg_operand (operands[0], HImode)
7767 || gpc_reg_operand (operands[1], HImode)"
7768 "@
7769 mr %0,%1
7770 lhz%U1%X1 %0,%1
7771 sth%U0%X0 %1,%0
7772 li %0,%w1
7773 mf%1 %0
7774 mt%0 %1
7775 nop"
7776 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7778 (define_expand "mov<mode>"
7779 [(set (match_operand:INT 0 "general_operand" "")
7780 (match_operand:INT 1 "any_operand" ""))]
7781 ""
7782 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7784 (define_insn "*movqi_internal"
7785 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7786 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7787 "gpc_reg_operand (operands[0], QImode)
7788 || gpc_reg_operand (operands[1], QImode)"
7789 "@
7790 mr %0,%1
7791 lbz%U1%X1 %0,%1
7792 stb%U0%X0 %1,%0
7793 li %0,%1
7794 mf%1 %0
7795 mt%0 %1
7796 nop"
7797 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7798 \f
7799 ;; Here is how to move condition codes around. When we store CC data in
7800 ;; an integer register or memory, we store just the high-order 4 bits.
7801 ;; This lets us not shift in the most common case of CR0.
7802 (define_expand "movcc"
7803 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7804 (match_operand:CC 1 "nonimmediate_operand" ""))]
7805 ""
7806 "")
7808 (define_insn "*movcc_internal1"
7809 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7810 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7811 "register_operand (operands[0], CCmode)
7812 || register_operand (operands[1], CCmode)"
7813 "@
7814 mcrf %0,%1
7815 mtcrf 128,%1
7816 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7817 crxor %0,%0,%0
7818 mfcr %0%Q1
7819 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7820 mr %0,%1
7821 li %0,%1
7822 mf%1 %0
7823 mt%0 %1
7824 lwz%U1%X1 %0,%1
7825 stw%U0%U1 %1,%0"
7826 [(set (attr "type")
7827 (cond [(eq_attr "alternative" "0,3")
7828 (const_string "cr_logical")
7829 (eq_attr "alternative" "1,2")
7830 (const_string "mtcr")
7831 (eq_attr "alternative" "6,7")
7832 (const_string "integer")
7833 (eq_attr "alternative" "8")
7834 (const_string "mfjmpr")
7835 (eq_attr "alternative" "9")
7836 (const_string "mtjmpr")
7837 (eq_attr "alternative" "10")
7838 (const_string "load")
7839 (eq_attr "alternative" "11")
7840 (const_string "store")
7841 (match_test "TARGET_MFCRF")
7842 (const_string "mfcrf")
7843 ]
7844 (const_string "mfcr")))
7845 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7846 \f
7847 ;; For floating-point, we normally deal with the floating-point registers
7848 ;; unless -msoft-float is used. The sole exception is that parameter passing
7849 ;; can produce floating-point values in fixed-point registers. Unless the
7850 ;; value is a simple constant or already in memory, we deal with this by
7851 ;; allocating memory and copying the value explicitly via that memory location.
7852 (define_expand "movsf"
7853 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7854 (match_operand:SF 1 "any_operand" ""))]
7855 ""
7856 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7858 (define_split
7859 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7860 (match_operand:SF 1 "const_double_operand" ""))]
7861 "reload_completed
7862 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7863 || (GET_CODE (operands[0]) == SUBREG
7864 && GET_CODE (SUBREG_REG (operands[0])) == REG
7865 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7866 [(set (match_dup 2) (match_dup 3))]
7867 "
7868 {
7869 long l;
7870 REAL_VALUE_TYPE rv;
7872 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7873 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7875 if (! TARGET_POWERPC64)
7876 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7877 else
7878 operands[2] = gen_lowpart (SImode, operands[0]);
7880 operands[3] = gen_int_mode (l, SImode);
7881 }")
7883 (define_insn "*movsf_hardfloat"
7884 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
7885 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
7886 "(gpc_reg_operand (operands[0], SFmode)
7887 || gpc_reg_operand (operands[1], SFmode))
7888 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7889 "@
7890 mr %0,%1
7891 lwz%U1%X1 %0,%1
7892 stw%U0%X0 %1,%0
7893 fmr %0,%1
7894 lfs%U1%X1 %0,%1
7895 stfs%U0%X0 %1,%0
7896 mt%0 %1
7897 mf%1 %0
7898 nop
7899 #
7900 #"
7901 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
7902 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7904 (define_insn "*movsf_softfloat"
7905 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7906 (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7907 "(gpc_reg_operand (operands[0], SFmode)
7908 || gpc_reg_operand (operands[1], SFmode))
7909 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7910 "@
7911 mr %0,%1
7912 mt%0 %1
7913 mf%1 %0
7914 lwz%U1%X1 %0,%1
7915 stw%U0%X0 %1,%0
7916 li %0,%1
7917 lis %0,%v1
7918 #
7919 #
7920 nop"
7921 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7922 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7924 \f
7925 (define_expand "movdf"
7926 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7927 (match_operand:DF 1 "any_operand" ""))]
7928 ""
7929 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7931 (define_split
7932 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7933 (match_operand:DF 1 "const_int_operand" ""))]
7934 "! TARGET_POWERPC64 && reload_completed
7935 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7936 || (GET_CODE (operands[0]) == SUBREG
7937 && GET_CODE (SUBREG_REG (operands[0])) == REG
7938 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7939 [(set (match_dup 2) (match_dup 4))
7940 (set (match_dup 3) (match_dup 1))]
7941 "
7942 {
7943 int endian = (WORDS_BIG_ENDIAN == 0);
7944 HOST_WIDE_INT value = INTVAL (operands[1]);
7946 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7947 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7948 #if HOST_BITS_PER_WIDE_INT == 32
7949 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7950 #else
7951 operands[4] = GEN_INT (value >> 32);
7952 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7953 #endif
7954 }")
7956 (define_split
7957 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7958 (match_operand:DF 1 "const_double_operand" ""))]
7959 "! TARGET_POWERPC64 && reload_completed
7960 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7961 || (GET_CODE (operands[0]) == SUBREG
7962 && GET_CODE (SUBREG_REG (operands[0])) == REG
7963 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7964 [(set (match_dup 2) (match_dup 4))
7965 (set (match_dup 3) (match_dup 5))]
7966 "
7967 {
7968 int endian = (WORDS_BIG_ENDIAN == 0);
7969 long l[2];
7970 REAL_VALUE_TYPE rv;
7972 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7973 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7975 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7976 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7977 operands[4] = gen_int_mode (l[endian], SImode);
7978 operands[5] = gen_int_mode (l[1 - endian], SImode);
7979 }")
7981 (define_split
7982 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7983 (match_operand:DF 1 "const_double_operand" ""))]
7984 "TARGET_POWERPC64 && reload_completed
7985 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7986 || (GET_CODE (operands[0]) == SUBREG
7987 && GET_CODE (SUBREG_REG (operands[0])) == REG
7988 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7989 [(set (match_dup 2) (match_dup 3))]
7990 "
7991 {
7992 int endian = (WORDS_BIG_ENDIAN == 0);
7993 long l[2];
7994 REAL_VALUE_TYPE rv;
7995 #if HOST_BITS_PER_WIDE_INT >= 64
7996 HOST_WIDE_INT val;
7997 #endif
7999 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8000 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8002 operands[2] = gen_lowpart (DImode, operands[0]);
8003 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8004 #if HOST_BITS_PER_WIDE_INT >= 64
8005 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8006 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8008 operands[3] = gen_int_mode (val, DImode);
8009 #else
8010 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8011 #endif
8012 }")
8014 ;; Don't have reload use general registers to load a constant. It is
8015 ;; less efficient than loading the constant into an FP register, since
8016 ;; it will probably be used there.
8017 (define_insn "*movdf_hardfloat32"
8018 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,!r,!r,!r")
8019 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
8020 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8021 && (gpc_reg_operand (operands[0], DFmode)
8022 || gpc_reg_operand (operands[1], DFmode))"
8023 "*
8024 {
8025 switch (which_alternative)
8026 {
8027 default:
8028 gcc_unreachable ();
8029 case 0:
8030 case 1:
8031 case 2:
8032 return \"#\";
8033 case 3:
8034 case 4:
8035 return \"xxlor %x0,%x1,%x1\";
8036 case 5:
8037 case 6:
8038 return \"lxsd%U1x %x0,%y1\";
8039 case 7:
8040 case 8:
8041 return \"stxsd%U0x %x1,%y0\";
8042 case 9:
8043 return \"stfd%U0%X0 %1,%0\";
8044 case 10:
8045 return \"lfd%U1%X1 %0,%1\";
8046 case 11:
8047 return \"fmr %0,%1\";
8048 case 12:
8049 return \"xxlxor %x0,%x0,%x0\";
8050 case 13:
8051 case 14:
8052 case 15:
8053 return \"#\";
8054 }
8055 }"
8056 [(set_attr "type" "store,load,two,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,*,*,*")
8057 (set_attr "length" "8,8,8,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8059 (define_insn "*movdf_softfloat32"
8060 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8061 (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
8062 "! TARGET_POWERPC64
8063 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8064 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8065 && (gpc_reg_operand (operands[0], DFmode)
8066 || gpc_reg_operand (operands[1], DFmode))"
8067 "#"
8068 [(set_attr "type" "store,load,two,*,*,*")
8069 (set_attr "length" "8,8,8,8,12,16")])
8071 ;; Reload patterns to support gpr load/store with misaligned mem.
8072 ;; and multiple gpr load/store at offset >= 0xfffc
8073 (define_expand "reload_<mode>_store"
8074 [(parallel [(match_operand 0 "memory_operand" "=m")
8075 (match_operand 1 "gpc_reg_operand" "r")
8076 (match_operand:GPR 2 "register_operand" "=&b")])]
8077 ""
8078 {
8079 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8080 DONE;
8081 })
8083 (define_expand "reload_<mode>_load"
8084 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8085 (match_operand 1 "memory_operand" "m")
8086 (match_operand:GPR 2 "register_operand" "=b")])]
8087 ""
8088 {
8089 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8090 DONE;
8091 })
8093 ; ld/std require word-aligned displacements -> 'Y' constraint.
8094 ; List Y->r and r->Y before r->r for reload.
8095 (define_insn "*movdf_hardfloat64_mfpgpr"
8096 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
8097 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
8098 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8099 && TARGET_DOUBLE_FLOAT
8100 && (gpc_reg_operand (operands[0], DFmode)
8101 || gpc_reg_operand (operands[1], DFmode))"
8102 "@
8103 std%U0%X0 %1,%0
8104 ld%U1%X1 %0,%1
8105 mr %0,%1
8106 xxlor %x0,%x1,%x1
8107 xxlor %x0,%x1,%x1
8108 lxsd%U1x %x0,%y1
8109 lxsd%U1x %x0,%y1
8110 stxsd%U0x %x1,%y0
8111 stxsd%U0x %x1,%y0
8112 stfd%U0%X0 %1,%0
8113 lfd%U1%X1 %0,%1
8114 fmr %0,%1
8115 xxlxor %x0,%x0,%x0
8116 mt%0 %1
8117 mf%1 %0
8118 nop
8119 #
8120 #
8121 #
8122 mftgpr %0,%1
8123 mffgpr %0,%1"
8124 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8125 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8127 ; ld/std require word-aligned displacements -> 'Y' constraint.
8128 ; List Y->r and r->Y before r->r for reload.
8129 (define_insn "*movdf_hardfloat64"
8130 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r")
8131 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
8132 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8133 && TARGET_DOUBLE_FLOAT
8134 && (gpc_reg_operand (operands[0], DFmode)
8135 || gpc_reg_operand (operands[1], DFmode))"
8136 "@
8137 std%U0%X0 %1,%0
8138 ld%U1%X1 %0,%1
8139 mr %0,%1
8140 xxlor %x0,%x1,%x1
8141 xxlor %x0,%x1,%x1
8142 lxsd%U1x %x0,%y1
8143 lxsd%U1x %x0,%y1
8144 stxsd%U0x %x1,%y0
8145 stxsd%U0x %x1,%y0
8146 stfd%U0%X0 %1,%0
8147 lfd%U1%X1 %0,%1
8148 fmr %0,%1
8149 xxlxor %x0,%x0,%x0
8150 mt%0 %1
8151 mf%1 %0
8152 nop
8153 #
8154 #
8155 #"
8156 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
8157 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8159 (define_insn "*movdf_softfloat64"
8160 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8161 (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8162 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8163 && (gpc_reg_operand (operands[0], DFmode)
8164 || gpc_reg_operand (operands[1], DFmode))"
8165 "@
8166 std%U0%X0 %1,%0
8167 ld%U1%X1 %0,%1
8168 mr %0,%1
8169 mt%0 %1
8170 mf%1 %0
8171 #
8172 #
8173 #
8174 nop"
8175 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8176 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8177 \f
8178 (define_expand "movtf"
8179 [(set (match_operand:TF 0 "general_operand" "")
8180 (match_operand:TF 1 "any_operand" ""))]
8181 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8182 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8184 ;; It's important to list Y->r and r->Y before r->r because otherwise
8185 ;; reload, given m->r, will try to pick r->r and reload it, which
8186 ;; doesn't make progress.
8187 (define_insn_and_split "*movtf_internal"
8188 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8189 (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
8190 "!TARGET_IEEEQUAD
8191 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8192 && (gpc_reg_operand (operands[0], TFmode)
8193 || gpc_reg_operand (operands[1], TFmode))"
8194 "#"
8195 "&& reload_completed"
8196 [(pc)]
8197 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8198 [(set_attr "length" "8,8,8,20,20,16")])
8200 (define_insn_and_split "*movtf_softfloat"
8201 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8202 (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
8203 "!TARGET_IEEEQUAD
8204 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8205 && (gpc_reg_operand (operands[0], TFmode)
8206 || gpc_reg_operand (operands[1], TFmode))"
8207 "#"
8208 "&& reload_completed"
8209 [(pc)]
8210 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8211 [(set_attr "length" "20,20,16")])
8213 (define_expand "extenddftf2"
8214 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8215 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8216 "!TARGET_IEEEQUAD
8217 && TARGET_HARD_FLOAT
8218 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8219 && TARGET_LONG_DOUBLE_128"
8220 {
8221 if (TARGET_E500_DOUBLE)
8222 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8223 else
8224 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8225 DONE;
8226 })
8228 (define_expand "extenddftf2_fprs"
8229 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8230 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8231 (use (match_dup 2))])]
8232 "!TARGET_IEEEQUAD
8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8234 && TARGET_LONG_DOUBLE_128"
8235 {
8236 operands[2] = CONST0_RTX (DFmode);
8237 /* Generate GOT reference early for SVR4 PIC. */
8238 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8239 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8240 })
8242 (define_insn_and_split "*extenddftf2_internal"
8243 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8244 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8245 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8246 "!TARGET_IEEEQUAD
8247 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8248 && TARGET_LONG_DOUBLE_128"
8249 "#"
8250 "&& reload_completed"
8251 [(pc)]
8252 {
8253 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8254 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8255 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8256 operands[1]);
8257 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8258 operands[2]);
8259 DONE;
8260 })
8262 (define_expand "extendsftf2"
8263 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8264 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8265 "!TARGET_IEEEQUAD
8266 && TARGET_HARD_FLOAT
8267 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8268 && TARGET_LONG_DOUBLE_128"
8269 {
8270 rtx tmp = gen_reg_rtx (DFmode);
8271 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8272 emit_insn (gen_extenddftf2 (operands[0], tmp));
8273 DONE;
8274 })
8276 (define_expand "trunctfdf2"
8277 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8278 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8279 "!TARGET_IEEEQUAD
8280 && TARGET_HARD_FLOAT
8281 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8282 && TARGET_LONG_DOUBLE_128"
8283 "")
8285 (define_insn_and_split "trunctfdf2_internal1"
8286 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8287 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8288 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8289 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8290 "@
8291 #
8292 fmr %0,%1"
8293 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8294 [(const_int 0)]
8295 {
8296 emit_note (NOTE_INSN_DELETED);
8297 DONE;
8298 }
8299 [(set_attr "type" "fp")])
8301 (define_insn "trunctfdf2_internal2"
8302 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8303 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8304 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8305 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8306 && TARGET_LONG_DOUBLE_128"
8307 "fadd %0,%1,%L1"
8308 [(set_attr "type" "fp")
8309 (set_attr "fp_type" "fp_addsub_d")])
8311 (define_expand "trunctfsf2"
8312 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8313 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8314 "!TARGET_IEEEQUAD
8315 && TARGET_HARD_FLOAT
8316 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8317 && TARGET_LONG_DOUBLE_128"
8318 {
8319 if (TARGET_E500_DOUBLE)
8320 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8321 else
8322 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8323 DONE;
8324 })
8326 (define_insn_and_split "trunctfsf2_fprs"
8327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8328 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8329 (clobber (match_scratch:DF 2 "=d"))]
8330 "!TARGET_IEEEQUAD
8331 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8332 && TARGET_LONG_DOUBLE_128"
8333 "#"
8334 "&& reload_completed"
8335 [(set (match_dup 2)
8336 (float_truncate:DF (match_dup 1)))
8337 (set (match_dup 0)
8338 (float_truncate:SF (match_dup 2)))]
8339 "")
8341 (define_expand "floatsitf2"
8342 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8343 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8344 "!TARGET_IEEEQUAD
8345 && TARGET_HARD_FLOAT
8346 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8347 && TARGET_LONG_DOUBLE_128"
8348 {
8349 rtx tmp = gen_reg_rtx (DFmode);
8350 expand_float (tmp, operands[1], false);
8351 emit_insn (gen_extenddftf2 (operands[0], tmp));
8352 DONE;
8353 })
8355 ; fadd, but rounding towards zero.
8356 ; This is probably not the optimal code sequence.
8357 (define_insn "fix_trunc_helper"
8358 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8359 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8360 UNSPEC_FIX_TRUNC_TF))
8361 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8362 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8363 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8364 [(set_attr "type" "fp")
8365 (set_attr "length" "20")])
8367 (define_expand "fix_trunctfsi2"
8368 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8369 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8370 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8371 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8372 {
8373 if (TARGET_E500_DOUBLE)
8374 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8375 else
8376 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8377 DONE;
8378 })
8380 (define_expand "fix_trunctfsi2_fprs"
8381 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8382 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8383 (clobber (match_dup 2))
8384 (clobber (match_dup 3))
8385 (clobber (match_dup 4))
8386 (clobber (match_dup 5))])]
8387 "!TARGET_IEEEQUAD
8388 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8389 {
8390 operands[2] = gen_reg_rtx (DFmode);
8391 operands[3] = gen_reg_rtx (DFmode);
8392 operands[4] = gen_reg_rtx (DImode);
8393 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8394 })
8396 (define_insn_and_split "*fix_trunctfsi2_internal"
8397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8398 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8399 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8400 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8401 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8402 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8403 "!TARGET_IEEEQUAD
8404 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8405 "#"
8406 ""
8407 [(pc)]
8408 {
8409 rtx lowword;
8410 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8412 gcc_assert (MEM_P (operands[5]));
8413 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8415 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8416 emit_move_insn (operands[5], operands[4]);
8417 emit_move_insn (operands[0], lowword);
8418 DONE;
8419 })
8421 (define_expand "negtf2"
8422 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8423 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8424 "!TARGET_IEEEQUAD
8425 && TARGET_HARD_FLOAT
8426 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8427 && TARGET_LONG_DOUBLE_128"
8428 "")
8430 (define_insn "negtf2_internal"
8431 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8432 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8433 "!TARGET_IEEEQUAD
8434 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8435 "*
8436 {
8437 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8438 return \"fneg %L0,%L1\;fneg %0,%1\";
8439 else
8440 return \"fneg %0,%1\;fneg %L0,%L1\";
8441 }"
8442 [(set_attr "type" "fp")
8443 (set_attr "length" "8")])
8445 (define_expand "abstf2"
8446 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8447 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8448 "!TARGET_IEEEQUAD
8449 && TARGET_HARD_FLOAT
8450 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8451 && TARGET_LONG_DOUBLE_128"
8452 "
8453 {
8454 rtx label = gen_label_rtx ();
8455 if (TARGET_E500_DOUBLE)
8456 {
8457 if (flag_finite_math_only && !flag_trapping_math)
8458 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8459 else
8460 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8461 }
8462 else
8463 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8464 emit_label (label);
8465 DONE;
8466 }")
8468 (define_expand "abstf2_internal"
8469 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8470 (match_operand:TF 1 "gpc_reg_operand" ""))
8471 (set (match_dup 3) (match_dup 5))
8472 (set (match_dup 5) (abs:DF (match_dup 5)))
8473 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8474 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8475 (label_ref (match_operand 2 "" ""))
8476 (pc)))
8477 (set (match_dup 6) (neg:DF (match_dup 6)))]
8478 "!TARGET_IEEEQUAD
8479 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8480 && TARGET_LONG_DOUBLE_128"
8481 "
8482 {
8483 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8484 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8485 operands[3] = gen_reg_rtx (DFmode);
8486 operands[4] = gen_reg_rtx (CCFPmode);
8487 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8488 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8489 }")
8490 \f
8491 ;; Next come the multi-word integer load and store and the load and store
8492 ;; multiple insns.
8494 ;; List r->r after r->Y, otherwise reload will try to reload a
8495 ;; non-offsettable address by using r->r which won't make progress.
8496 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8497 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8498 (define_insn "*movdi_internal32"
8499 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
8500 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
8501 "! TARGET_POWERPC64
8502 && (gpc_reg_operand (operands[0], DImode)
8503 || gpc_reg_operand (operands[1], DImode))"
8504 "@
8505 #
8506 #
8507 #
8508 stfd%U0%X0 %1,%0
8509 lfd%U1%X1 %0,%1
8510 fmr %0,%1
8511 #
8512 xxlxor %x0,%x0,%x0"
8513 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
8515 (define_split
8516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8517 (match_operand:DI 1 "const_int_operand" ""))]
8518 "! TARGET_POWERPC64 && reload_completed
8519 && gpr_or_gpr_p (operands[0], operands[1])"
8520 [(set (match_dup 2) (match_dup 4))
8521 (set (match_dup 3) (match_dup 1))]
8522 "
8523 {
8524 HOST_WIDE_INT value = INTVAL (operands[1]);
8525 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8526 DImode);
8527 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8528 DImode);
8529 #if HOST_BITS_PER_WIDE_INT == 32
8530 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8531 #else
8532 operands[4] = GEN_INT (value >> 32);
8533 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8534 #endif
8535 }")
8537 (define_split
8538 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8539 (match_operand:DIFD 1 "input_operand" ""))]
8540 "reload_completed && !TARGET_POWERPC64
8541 && gpr_or_gpr_p (operands[0], operands[1])"
8542 [(pc)]
8543 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8545 (define_insn "*movdi_mfpgpr"
8546 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
8547 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
8548 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8549 && (gpc_reg_operand (operands[0], DImode)
8550 || gpc_reg_operand (operands[1], DImode))"
8551 "@
8552 std%U0%X0 %1,%0
8553 ld%U1%X1 %0,%1
8554 mr %0,%1
8555 li %0,%1
8556 lis %0,%v1
8557 #
8558 stfd%U0%X0 %1,%0
8559 lfd%U1%X1 %0,%1
8560 fmr %0,%1
8561 mf%1 %0
8562 mt%0 %1
8563 nop
8564 mftgpr %0,%1
8565 mffgpr %0,%1"
8566 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8567 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
8569 (define_insn "*movdi_internal64"
8570 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
8571 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
8572 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8573 && (gpc_reg_operand (operands[0], DImode)
8574 || gpc_reg_operand (operands[1], DImode))"
8575 "@
8576 std%U0%X0 %1,%0
8577 ld%U1%X1 %0,%1
8578 mr %0,%1
8579 li %0,%1
8580 lis %0,%v1
8581 #
8582 stfd%U0%X0 %1,%0
8583 lfd%U1%X1 %0,%1
8584 fmr %0,%1
8585 mf%1 %0
8586 mt%0 %1
8587 nop
8588 xxlxor %x0,%x0,%x0"
8589 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
8590 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8592 ;; immediate value valid for a single instruction hiding in a const_double
8593 (define_insn ""
8594 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8595 (match_operand:DI 1 "const_double_operand" "F"))]
8596 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8597 && GET_CODE (operands[1]) == CONST_DOUBLE
8598 && num_insns_constant (operands[1], DImode) == 1"
8599 "*
8600 {
8601 return ((unsigned HOST_WIDE_INT)
8602 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8603 ? \"li %0,%1\" : \"lis %0,%v1\";
8604 }")
8606 ;; Generate all one-bits and clear left or right.
8607 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8608 (define_split
8609 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8610 (match_operand:DI 1 "mask64_operand" ""))]
8611 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8612 [(set (match_dup 0) (const_int -1))
8613 (set (match_dup 0)
8614 (and:DI (rotate:DI (match_dup 0)
8615 (const_int 0))
8616 (match_dup 1)))]
8617 "")
8619 ;; Split a load of a large constant into the appropriate five-instruction
8620 ;; sequence. Handle anything in a constant number of insns.
8621 ;; When non-easy constants can go in the TOC, this should use
8622 ;; easy_fp_constant predicate.
8623 (define_split
8624 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8625 (match_operand:DI 1 "const_int_operand" ""))]
8626 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8627 [(set (match_dup 0) (match_dup 2))
8628 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8629 "
8630 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8632 if (tem == operands[0])
8633 DONE;
8634 else
8635 FAIL;
8636 }")
8638 (define_split
8639 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8640 (match_operand:DI 1 "const_double_operand" ""))]
8641 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8642 [(set (match_dup 0) (match_dup 2))
8643 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8644 "
8645 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8647 if (tem == operands[0])
8648 DONE;
8649 else
8650 FAIL;
8651 }")
8652 \f
8653 ;; TImode is similar, except that we usually want to compute the address into
8654 ;; a register and use lsi/stsi (the exception is during reload).
8656 (define_insn "*movti_string"
8657 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8658 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
8659 "! TARGET_POWERPC64
8660 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8661 "*
8662 {
8663 switch (which_alternative)
8664 {
8665 default:
8666 gcc_unreachable ();
8667 case 0:
8668 if (TARGET_STRING)
8669 return \"stswi %1,%P0,16\";
8670 case 1:
8671 return \"#\";
8672 case 2:
8673 /* If the address is not used in the output, we can use lsi. Otherwise,
8674 fall through to generating four loads. */
8675 if (TARGET_STRING
8676 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8677 return \"lswi %0,%P1,16\";
8678 /* ... fall through ... */
8679 case 3:
8680 case 4:
8681 case 5:
8682 return \"#\";
8683 }
8684 }"
8685 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
8686 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8687 (const_string "always")
8688 (const_string "conditional")))])
8690 (define_insn "*movti_ppc64"
8691 [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
8692 (match_operand:TI 1 "input_operand" "r,Y,r"))]
8693 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8694 || gpc_reg_operand (operands[1], TImode)))
8695 && VECTOR_MEM_NONE_P (TImode)"
8696 "#"
8697 [(set_attr "type" "store,load,*")])
8699 (define_split
8700 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8701 (match_operand:TI 1 "const_double_operand" ""))]
8702 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
8703 [(set (match_dup 2) (match_dup 4))
8704 (set (match_dup 3) (match_dup 5))]
8705 "
8706 {
8707 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8708 TImode);
8709 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8710 TImode);
8711 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8712 {
8713 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8714 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8715 }
8716 else if (GET_CODE (operands[1]) == CONST_INT)
8717 {
8718 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8719 operands[5] = operands[1];
8720 }
8721 else
8722 FAIL;
8723 }")
8725 (define_split
8726 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8727 (match_operand:TI 1 "input_operand" ""))]
8728 "reload_completed && VECTOR_MEM_NONE_P (TImode)
8729 && gpr_or_gpr_p (operands[0], operands[1])"
8730 [(pc)]
8731 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8732 \f
8733 (define_expand "load_multiple"
8734 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8735 (match_operand:SI 1 "" ""))
8736 (use (match_operand:SI 2 "" ""))])]
8737 "TARGET_STRING && !TARGET_POWERPC64"
8738 "
8739 {
8740 int regno;
8741 int count;
8742 rtx op1;
8743 int i;
8745 /* Support only loading a constant number of fixed-point registers from
8746 memory and only bother with this if more than two; the machine
8747 doesn't support more than eight. */
8748 if (GET_CODE (operands[2]) != CONST_INT
8749 || INTVAL (operands[2]) <= 2
8750 || INTVAL (operands[2]) > 8
8751 || GET_CODE (operands[1]) != MEM
8752 || GET_CODE (operands[0]) != REG
8753 || REGNO (operands[0]) >= 32)
8754 FAIL;
8756 count = INTVAL (operands[2]);
8757 regno = REGNO (operands[0]);
8759 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8760 op1 = replace_equiv_address (operands[1],
8761 force_reg (SImode, XEXP (operands[1], 0)));
8763 for (i = 0; i < count; i++)
8764 XVECEXP (operands[3], 0, i)
8765 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8766 adjust_address_nv (op1, SImode, i * 4));
8767 }")
8769 (define_insn "*ldmsi8"
8770 [(match_parallel 0 "load_multiple_operation"
8771 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8772 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8773 (set (match_operand:SI 3 "gpc_reg_operand" "")
8774 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8775 (set (match_operand:SI 4 "gpc_reg_operand" "")
8776 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8777 (set (match_operand:SI 5 "gpc_reg_operand" "")
8778 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8779 (set (match_operand:SI 6 "gpc_reg_operand" "")
8780 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8781 (set (match_operand:SI 7 "gpc_reg_operand" "")
8782 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8783 (set (match_operand:SI 8 "gpc_reg_operand" "")
8784 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8785 (set (match_operand:SI 9 "gpc_reg_operand" "")
8786 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8787 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8788 "*
8789 { return rs6000_output_load_multiple (operands); }"
8790 [(set_attr "type" "load_ux")
8791 (set_attr "length" "32")])
8793 (define_insn "*ldmsi7"
8794 [(match_parallel 0 "load_multiple_operation"
8795 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8796 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8797 (set (match_operand:SI 3 "gpc_reg_operand" "")
8798 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8799 (set (match_operand:SI 4 "gpc_reg_operand" "")
8800 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8801 (set (match_operand:SI 5 "gpc_reg_operand" "")
8802 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8803 (set (match_operand:SI 6 "gpc_reg_operand" "")
8804 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8805 (set (match_operand:SI 7 "gpc_reg_operand" "")
8806 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8807 (set (match_operand:SI 8 "gpc_reg_operand" "")
8808 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8809 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8810 "*
8811 { return rs6000_output_load_multiple (operands); }"
8812 [(set_attr "type" "load_ux")
8813 (set_attr "length" "32")])
8815 (define_insn "*ldmsi6"
8816 [(match_parallel 0 "load_multiple_operation"
8817 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8818 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8819 (set (match_operand:SI 3 "gpc_reg_operand" "")
8820 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8821 (set (match_operand:SI 4 "gpc_reg_operand" "")
8822 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8823 (set (match_operand:SI 5 "gpc_reg_operand" "")
8824 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8825 (set (match_operand:SI 6 "gpc_reg_operand" "")
8826 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8827 (set (match_operand:SI 7 "gpc_reg_operand" "")
8828 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8829 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8830 "*
8831 { return rs6000_output_load_multiple (operands); }"
8832 [(set_attr "type" "load_ux")
8833 (set_attr "length" "32")])
8835 (define_insn "*ldmsi5"
8836 [(match_parallel 0 "load_multiple_operation"
8837 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8838 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8839 (set (match_operand:SI 3 "gpc_reg_operand" "")
8840 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8841 (set (match_operand:SI 4 "gpc_reg_operand" "")
8842 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8843 (set (match_operand:SI 5 "gpc_reg_operand" "")
8844 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8845 (set (match_operand:SI 6 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8847 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8848 "*
8849 { return rs6000_output_load_multiple (operands); }"
8850 [(set_attr "type" "load_ux")
8851 (set_attr "length" "32")])
8853 (define_insn "*ldmsi4"
8854 [(match_parallel 0 "load_multiple_operation"
8855 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8856 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8857 (set (match_operand:SI 3 "gpc_reg_operand" "")
8858 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8859 (set (match_operand:SI 4 "gpc_reg_operand" "")
8860 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8861 (set (match_operand:SI 5 "gpc_reg_operand" "")
8862 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8863 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8864 "*
8865 { return rs6000_output_load_multiple (operands); }"
8866 [(set_attr "type" "load_ux")
8867 (set_attr "length" "32")])
8869 (define_insn "*ldmsi3"
8870 [(match_parallel 0 "load_multiple_operation"
8871 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8872 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8873 (set (match_operand:SI 3 "gpc_reg_operand" "")
8874 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8875 (set (match_operand:SI 4 "gpc_reg_operand" "")
8876 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8877 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8878 "*
8879 { return rs6000_output_load_multiple (operands); }"
8880 [(set_attr "type" "load_ux")
8881 (set_attr "length" "32")])
8883 (define_expand "store_multiple"
8884 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8885 (match_operand:SI 1 "" ""))
8886 (clobber (scratch:SI))
8887 (use (match_operand:SI 2 "" ""))])]
8888 "TARGET_STRING && !TARGET_POWERPC64"
8889 "
8890 {
8891 int regno;
8892 int count;
8893 rtx to;
8894 rtx op0;
8895 int i;
8897 /* Support only storing a constant number of fixed-point registers to
8898 memory and only bother with this if more than two; the machine
8899 doesn't support more than eight. */
8900 if (GET_CODE (operands[2]) != CONST_INT
8901 || INTVAL (operands[2]) <= 2
8902 || INTVAL (operands[2]) > 8
8903 || GET_CODE (operands[0]) != MEM
8904 || GET_CODE (operands[1]) != REG
8905 || REGNO (operands[1]) >= 32)
8906 FAIL;
8908 count = INTVAL (operands[2]);
8909 regno = REGNO (operands[1]);
8911 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8912 to = force_reg (SImode, XEXP (operands[0], 0));
8913 op0 = replace_equiv_address (operands[0], to);
8915 XVECEXP (operands[3], 0, 0)
8916 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8917 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8918 gen_rtx_SCRATCH (SImode));
8920 for (i = 1; i < count; i++)
8921 XVECEXP (operands[3], 0, i + 1)
8922 = gen_rtx_SET (VOIDmode,
8923 adjust_address_nv (op0, SImode, i * 4),
8924 gen_rtx_REG (SImode, regno + i));
8925 }")
8927 (define_insn "*stmsi8"
8928 [(match_parallel 0 "store_multiple_operation"
8929 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8930 (match_operand:SI 2 "gpc_reg_operand" "r"))
8931 (clobber (match_scratch:SI 3 "=X"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8933 (match_operand:SI 4 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8935 (match_operand:SI 5 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8937 (match_operand:SI 6 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8939 (match_operand:SI 7 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8941 (match_operand:SI 8 "gpc_reg_operand" "r"))
8942 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8943 (match_operand:SI 9 "gpc_reg_operand" "r"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8945 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8946 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
8947 "stswi %2,%1,%O0"
8948 [(set_attr "type" "store_ux")
8949 (set_attr "cell_micro" "always")])
8951 (define_insn "*stmsi7"
8952 [(match_parallel 0 "store_multiple_operation"
8953 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8954 (match_operand:SI 2 "gpc_reg_operand" "r"))
8955 (clobber (match_scratch:SI 3 "=X"))
8956 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8957 (match_operand:SI 4 "gpc_reg_operand" "r"))
8958 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8959 (match_operand:SI 5 "gpc_reg_operand" "r"))
8960 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8961 (match_operand:SI 6 "gpc_reg_operand" "r"))
8962 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8963 (match_operand:SI 7 "gpc_reg_operand" "r"))
8964 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8965 (match_operand:SI 8 "gpc_reg_operand" "r"))
8966 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8967 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8968 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8969 "stswi %2,%1,%O0"
8970 [(set_attr "type" "store_ux")
8971 (set_attr "cell_micro" "always")])
8973 (define_insn "*stmsi6"
8974 [(match_parallel 0 "store_multiple_operation"
8975 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8976 (match_operand:SI 2 "gpc_reg_operand" "r"))
8977 (clobber (match_scratch:SI 3 "=X"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8979 (match_operand:SI 4 "gpc_reg_operand" "r"))
8980 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8981 (match_operand:SI 5 "gpc_reg_operand" "r"))
8982 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8983 (match_operand:SI 6 "gpc_reg_operand" "r"))
8984 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8985 (match_operand:SI 7 "gpc_reg_operand" "r"))
8986 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8987 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8988 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8989 "stswi %2,%1,%O0"
8990 [(set_attr "type" "store_ux")
8991 (set_attr "cell_micro" "always")])
8993 (define_insn "*stmsi5"
8994 [(match_parallel 0 "store_multiple_operation"
8995 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8996 (match_operand:SI 2 "gpc_reg_operand" "r"))
8997 (clobber (match_scratch:SI 3 "=X"))
8998 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8999 (match_operand:SI 4 "gpc_reg_operand" "r"))
9000 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9001 (match_operand:SI 5 "gpc_reg_operand" "r"))
9002 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9003 (match_operand:SI 6 "gpc_reg_operand" "r"))
9004 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9005 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9006 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9007 "stswi %2,%1,%O0"
9008 [(set_attr "type" "store_ux")
9009 (set_attr "cell_micro" "always")])
9011 (define_insn "*stmsi4"
9012 [(match_parallel 0 "store_multiple_operation"
9013 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9014 (match_operand:SI 2 "gpc_reg_operand" "r"))
9015 (clobber (match_scratch:SI 3 "=X"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9017 (match_operand:SI 4 "gpc_reg_operand" "r"))
9018 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9019 (match_operand:SI 5 "gpc_reg_operand" "r"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9021 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9022 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9023 "stswi %2,%1,%O0"
9024 [(set_attr "type" "store_ux")
9025 (set_attr "cell_micro" "always")])
9027 (define_insn "*stmsi3"
9028 [(match_parallel 0 "store_multiple_operation"
9029 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9030 (match_operand:SI 2 "gpc_reg_operand" "r"))
9031 (clobber (match_scratch:SI 3 "=X"))
9032 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9033 (match_operand:SI 4 "gpc_reg_operand" "r"))
9034 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9035 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9036 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9037 "stswi %2,%1,%O0"
9038 [(set_attr "type" "store_ux")
9039 (set_attr "cell_micro" "always")])
9040 \f
9041 (define_expand "setmemsi"
9042 [(parallel [(set (match_operand:BLK 0 "" "")
9043 (match_operand 2 "const_int_operand" ""))
9044 (use (match_operand:SI 1 "" ""))
9045 (use (match_operand:SI 3 "" ""))])]
9046 ""
9047 "
9048 {
9049 /* If value to set is not zero, use the library routine. */
9050 if (operands[2] != const0_rtx)
9051 FAIL;
9053 if (expand_block_clear (operands))
9054 DONE;
9055 else
9056 FAIL;
9057 }")
9059 ;; String/block move insn.
9060 ;; Argument 0 is the destination
9061 ;; Argument 1 is the source
9062 ;; Argument 2 is the length
9063 ;; Argument 3 is the alignment
9065 (define_expand "movmemsi"
9066 [(parallel [(set (match_operand:BLK 0 "" "")
9067 (match_operand:BLK 1 "" ""))
9068 (use (match_operand:SI 2 "" ""))
9069 (use (match_operand:SI 3 "" ""))])]
9070 ""
9071 "
9072 {
9073 if (expand_block_move (operands))
9074 DONE;
9075 else
9076 FAIL;
9077 }")
9079 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9080 ;; register allocator doesn't have a clue about allocating 8 word registers.
9081 ;; rD/rS = r5 is preferred, efficient form.
9082 (define_expand "movmemsi_8reg"
9083 [(parallel [(set (match_operand 0 "" "")
9084 (match_operand 1 "" ""))
9085 (use (match_operand 2 "" ""))
9086 (use (match_operand 3 "" ""))
9087 (clobber (reg:SI 5))
9088 (clobber (reg:SI 6))
9089 (clobber (reg:SI 7))
9090 (clobber (reg:SI 8))
9091 (clobber (reg:SI 9))
9092 (clobber (reg:SI 10))
9093 (clobber (reg:SI 11))
9094 (clobber (reg:SI 12))
9095 (clobber (match_scratch:SI 4 ""))])]
9096 "TARGET_STRING"
9097 "")
9099 (define_insn ""
9100 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9101 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9102 (use (match_operand:SI 2 "immediate_operand" "i"))
9103 (use (match_operand:SI 3 "immediate_operand" "i"))
9104 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9105 (clobber (reg:SI 6))
9106 (clobber (reg:SI 7))
9107 (clobber (reg:SI 8))
9108 (clobber (reg:SI 9))
9109 (clobber (reg:SI 10))
9110 (clobber (reg:SI 11))
9111 (clobber (reg:SI 12))
9112 (clobber (match_scratch:SI 5 "=X"))]
9113 "TARGET_STRING
9114 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9115 || INTVAL (operands[2]) == 0)
9116 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9117 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9118 && REGNO (operands[4]) == 5"
9119 "lswi %4,%1,%2\;stswi %4,%0,%2"
9120 [(set_attr "type" "store_ux")
9121 (set_attr "cell_micro" "always")
9122 (set_attr "length" "8")])
9124 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9125 ;; register allocator doesn't have a clue about allocating 6 word registers.
9126 ;; rD/rS = r5 is preferred, efficient form.
9127 (define_expand "movmemsi_6reg"
9128 [(parallel [(set (match_operand 0 "" "")
9129 (match_operand 1 "" ""))
9130 (use (match_operand 2 "" ""))
9131 (use (match_operand 3 "" ""))
9132 (clobber (reg:SI 5))
9133 (clobber (reg:SI 6))
9134 (clobber (reg:SI 7))
9135 (clobber (reg:SI 8))
9136 (clobber (reg:SI 9))
9137 (clobber (reg:SI 10))
9138 (clobber (match_scratch:SI 4 ""))])]
9139 "TARGET_STRING"
9140 "")
9142 (define_insn ""
9143 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9144 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9145 (use (match_operand:SI 2 "immediate_operand" "i"))
9146 (use (match_operand:SI 3 "immediate_operand" "i"))
9147 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9148 (clobber (reg:SI 6))
9149 (clobber (reg:SI 7))
9150 (clobber (reg:SI 8))
9151 (clobber (reg:SI 9))
9152 (clobber (reg:SI 10))
9153 (clobber (match_scratch:SI 5 "=X"))]
9154 "TARGET_STRING
9155 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9156 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9157 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9158 && REGNO (operands[4]) == 5"
9159 "lswi %4,%1,%2\;stswi %4,%0,%2"
9160 [(set_attr "type" "store_ux")
9161 (set_attr "cell_micro" "always")
9162 (set_attr "length" "8")])
9164 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9165 ;; problems with TImode.
9166 ;; rD/rS = r5 is preferred, efficient form.
9167 (define_expand "movmemsi_4reg"
9168 [(parallel [(set (match_operand 0 "" "")
9169 (match_operand 1 "" ""))
9170 (use (match_operand 2 "" ""))
9171 (use (match_operand 3 "" ""))
9172 (clobber (reg:SI 5))
9173 (clobber (reg:SI 6))
9174 (clobber (reg:SI 7))
9175 (clobber (reg:SI 8))
9176 (clobber (match_scratch:SI 4 ""))])]
9177 "TARGET_STRING"
9178 "")
9180 (define_insn ""
9181 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9182 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9183 (use (match_operand:SI 2 "immediate_operand" "i"))
9184 (use (match_operand:SI 3 "immediate_operand" "i"))
9185 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9186 (clobber (reg:SI 6))
9187 (clobber (reg:SI 7))
9188 (clobber (reg:SI 8))
9189 (clobber (match_scratch:SI 5 "=X"))]
9190 "TARGET_STRING
9191 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9192 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9193 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9194 && REGNO (operands[4]) == 5"
9195 "lswi %4,%1,%2\;stswi %4,%0,%2"
9196 [(set_attr "type" "store_ux")
9197 (set_attr "cell_micro" "always")
9198 (set_attr "length" "8")])
9200 ;; Move up to 8 bytes at a time.
9201 (define_expand "movmemsi_2reg"
9202 [(parallel [(set (match_operand 0 "" "")
9203 (match_operand 1 "" ""))
9204 (use (match_operand 2 "" ""))
9205 (use (match_operand 3 "" ""))
9206 (clobber (match_scratch:DI 4 ""))
9207 (clobber (match_scratch:SI 5 ""))])]
9208 "TARGET_STRING && ! TARGET_POWERPC64"
9209 "")
9211 (define_insn ""
9212 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9213 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9214 (use (match_operand:SI 2 "immediate_operand" "i"))
9215 (use (match_operand:SI 3 "immediate_operand" "i"))
9216 (clobber (match_scratch:DI 4 "=&r"))
9217 (clobber (match_scratch:SI 5 "=X"))]
9218 "TARGET_STRING && ! TARGET_POWERPC64
9219 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9220 "lswi %4,%1,%2\;stswi %4,%0,%2"
9221 [(set_attr "type" "store_ux")
9222 (set_attr "cell_micro" "always")
9223 (set_attr "length" "8")])
9225 ;; Move up to 4 bytes at a time.
9226 (define_expand "movmemsi_1reg"
9227 [(parallel [(set (match_operand 0 "" "")
9228 (match_operand 1 "" ""))
9229 (use (match_operand 2 "" ""))
9230 (use (match_operand 3 "" ""))
9231 (clobber (match_scratch:SI 4 ""))
9232 (clobber (match_scratch:SI 5 ""))])]
9233 "TARGET_STRING"
9234 "")
9236 (define_insn ""
9237 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9238 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9239 (use (match_operand:SI 2 "immediate_operand" "i"))
9240 (use (match_operand:SI 3 "immediate_operand" "i"))
9241 (clobber (match_scratch:SI 4 "=&r"))
9242 (clobber (match_scratch:SI 5 "=X"))]
9243 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9244 "lswi %4,%1,%2\;stswi %4,%0,%2"
9245 [(set_attr "type" "store_ux")
9246 (set_attr "cell_micro" "always")
9247 (set_attr "length" "8")])
9248 \f
9249 ;; Define insns that do load or store with update. Some of these we can
9250 ;; get by using pre-decrement or pre-increment, but the hardware can also
9251 ;; do cases where the increment is not the size of the object.
9252 ;;
9253 ;; In all these cases, we use operands 0 and 1 for the register being
9254 ;; incremented because those are the operands that local-alloc will
9255 ;; tie and these are the pair most likely to be tieable (and the ones
9256 ;; that will benefit the most).
9258 (define_insn "*movdi_update1"
9259 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9260 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9261 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9262 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9263 (plus:DI (match_dup 1) (match_dup 2)))]
9264 "TARGET_POWERPC64 && TARGET_UPDATE
9265 && (!avoiding_indexed_address_p (DImode)
9266 || !gpc_reg_operand (operands[2], DImode))"
9267 "@
9268 ldux %3,%0,%2
9269 ldu %3,%2(%0)"
9270 [(set_attr "type" "load_ux,load_u")])
9272 (define_insn "movdi_<mode>_update"
9273 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9274 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9275 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9276 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9277 (plus:P (match_dup 1) (match_dup 2)))]
9278 "TARGET_POWERPC64 && TARGET_UPDATE
9279 && (!avoiding_indexed_address_p (Pmode)
9280 || !gpc_reg_operand (operands[2], Pmode)
9281 || (REG_P (operands[0])
9282 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9283 "@
9284 stdux %3,%0,%2
9285 stdu %3,%2(%0)"
9286 [(set_attr "type" "store_ux,store_u")])
9288 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9289 ;; needed for stack allocation, even if the user passes -mno-update.
9290 (define_insn "movdi_<mode>_update_stack"
9291 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9292 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9293 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9294 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9295 (plus:P (match_dup 1) (match_dup 2)))]
9296 "TARGET_POWERPC64"
9297 "@
9298 stdux %3,%0,%2
9299 stdu %3,%2(%0)"
9300 [(set_attr "type" "store_ux,store_u")])
9302 (define_insn "*movsi_update1"
9303 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9304 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9305 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9306 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9307 (plus:SI (match_dup 1) (match_dup 2)))]
9308 "TARGET_UPDATE
9309 && (!avoiding_indexed_address_p (SImode)
9310 || !gpc_reg_operand (operands[2], SImode))"
9311 "@
9312 lwzux %3,%0,%2
9313 lwzu %3,%2(%0)"
9314 [(set_attr "type" "load_ux,load_u")])
9316 (define_insn "*movsi_update2"
9317 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9318 (sign_extend:DI
9319 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9320 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9321 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9322 (plus:DI (match_dup 1) (match_dup 2)))]
9323 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9324 && !avoiding_indexed_address_p (DImode)"
9325 "lwaux %3,%0,%2"
9326 [(set_attr "type" "load_ext_ux")])
9328 (define_insn "movsi_update"
9329 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9330 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9331 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9332 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9333 (plus:SI (match_dup 1) (match_dup 2)))]
9334 "TARGET_UPDATE
9335 && (!avoiding_indexed_address_p (SImode)
9336 || !gpc_reg_operand (operands[2], SImode)
9337 || (REG_P (operands[0])
9338 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9339 "@
9340 stwux %3,%0,%2
9341 stwu %3,%2(%0)"
9342 [(set_attr "type" "store_ux,store_u")])
9344 ;; This is an unconditional pattern; needed for stack allocation, even
9345 ;; if the user passes -mno-update.
9346 (define_insn "movsi_update_stack"
9347 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9348 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9349 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9350 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9351 (plus:SI (match_dup 1) (match_dup 2)))]
9352 ""
9353 "@
9354 stwux %3,%0,%2
9355 stwu %3,%2(%0)"
9356 [(set_attr "type" "store_ux,store_u")])
9358 (define_insn "*movhi_update1"
9359 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9360 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9361 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9362 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9363 (plus:SI (match_dup 1) (match_dup 2)))]
9364 "TARGET_UPDATE
9365 && (!avoiding_indexed_address_p (SImode)
9366 || !gpc_reg_operand (operands[2], SImode))"
9367 "@
9368 lhzux %3,%0,%2
9369 lhzu %3,%2(%0)"
9370 [(set_attr "type" "load_ux,load_u")])
9372 (define_insn "*movhi_update2"
9373 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9374 (zero_extend:SI
9375 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9376 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9377 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9378 (plus:SI (match_dup 1) (match_dup 2)))]
9379 "TARGET_UPDATE
9380 && (!avoiding_indexed_address_p (SImode)
9381 || !gpc_reg_operand (operands[2], SImode))"
9382 "@
9383 lhzux %3,%0,%2
9384 lhzu %3,%2(%0)"
9385 [(set_attr "type" "load_ux,load_u")])
9387 (define_insn "*movhi_update3"
9388 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9389 (sign_extend:SI
9390 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9391 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9392 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9393 (plus:SI (match_dup 1) (match_dup 2)))]
9394 "TARGET_UPDATE && rs6000_gen_cell_microcode
9395 && (!avoiding_indexed_address_p (SImode)
9396 || !gpc_reg_operand (operands[2], SImode))"
9397 "@
9398 lhaux %3,%0,%2
9399 lhau %3,%2(%0)"
9400 [(set_attr "type" "load_ext_ux,load_ext_u")])
9402 (define_insn "*movhi_update4"
9403 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9404 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9405 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9406 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9407 (plus:SI (match_dup 1) (match_dup 2)))]
9408 "TARGET_UPDATE
9409 && (!avoiding_indexed_address_p (SImode)
9410 || !gpc_reg_operand (operands[2], SImode))"
9411 "@
9412 sthux %3,%0,%2
9413 sthu %3,%2(%0)"
9414 [(set_attr "type" "store_ux,store_u")])
9416 (define_insn "*movqi_update1"
9417 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9418 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9419 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9420 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9421 (plus:SI (match_dup 1) (match_dup 2)))]
9422 "TARGET_UPDATE
9423 && (!avoiding_indexed_address_p (SImode)
9424 || !gpc_reg_operand (operands[2], SImode))"
9425 "@
9426 lbzux %3,%0,%2
9427 lbzu %3,%2(%0)"
9428 [(set_attr "type" "load_ux,load_u")])
9430 (define_insn "*movqi_update2"
9431 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9432 (zero_extend:SI
9433 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9434 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9435 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9436 (plus:SI (match_dup 1) (match_dup 2)))]
9437 "TARGET_UPDATE
9438 && (!avoiding_indexed_address_p (SImode)
9439 || !gpc_reg_operand (operands[2], SImode))"
9440 "@
9441 lbzux %3,%0,%2
9442 lbzu %3,%2(%0)"
9443 [(set_attr "type" "load_ux,load_u")])
9445 (define_insn "*movqi_update3"
9446 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9447 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9448 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9449 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9450 (plus:SI (match_dup 1) (match_dup 2)))]
9451 "TARGET_UPDATE
9452 && (!avoiding_indexed_address_p (SImode)
9453 || !gpc_reg_operand (operands[2], SImode))"
9454 "@
9455 stbux %3,%0,%2
9456 stbu %3,%2(%0)"
9457 [(set_attr "type" "store_ux,store_u")])
9459 (define_insn "*movsf_update1"
9460 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9461 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9462 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9463 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9464 (plus:SI (match_dup 1) (match_dup 2)))]
9465 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9466 && (!avoiding_indexed_address_p (SImode)
9467 || !gpc_reg_operand (operands[2], SImode))"
9468 "@
9469 lfsux %3,%0,%2
9470 lfsu %3,%2(%0)"
9471 [(set_attr "type" "fpload_ux,fpload_u")])
9473 (define_insn "*movsf_update2"
9474 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9475 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9476 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9477 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9478 (plus:SI (match_dup 1) (match_dup 2)))]
9479 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9480 && (!avoiding_indexed_address_p (SImode)
9481 || !gpc_reg_operand (operands[2], SImode))"
9482 "@
9483 stfsux %3,%0,%2
9484 stfsu %3,%2(%0)"
9485 [(set_attr "type" "fpstore_ux,fpstore_u")])
9487 (define_insn "*movsf_update3"
9488 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9489 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9490 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9491 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9492 (plus:SI (match_dup 1) (match_dup 2)))]
9493 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9494 && (!avoiding_indexed_address_p (SImode)
9495 || !gpc_reg_operand (operands[2], SImode))"
9496 "@
9497 lwzux %3,%0,%2
9498 lwzu %3,%2(%0)"
9499 [(set_attr "type" "load_ux,load_u")])
9501 (define_insn "*movsf_update4"
9502 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9503 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9504 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9505 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9506 (plus:SI (match_dup 1) (match_dup 2)))]
9507 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9508 && (!avoiding_indexed_address_p (SImode)
9509 || !gpc_reg_operand (operands[2], SImode))"
9510 "@
9511 stwux %3,%0,%2
9512 stwu %3,%2(%0)"
9513 [(set_attr "type" "store_ux,store_u")])
9515 (define_insn "*movdf_update1"
9516 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9517 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9518 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9519 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9520 (plus:SI (match_dup 1) (match_dup 2)))]
9521 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9522 && (!avoiding_indexed_address_p (SImode)
9523 || !gpc_reg_operand (operands[2], SImode))"
9524 "@
9525 lfdux %3,%0,%2
9526 lfdu %3,%2(%0)"
9527 [(set_attr "type" "fpload_ux,fpload_u")])
9529 (define_insn "*movdf_update2"
9530 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9531 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9532 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9533 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9534 (plus:SI (match_dup 1) (match_dup 2)))]
9535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9536 && (!avoiding_indexed_address_p (SImode)
9537 || !gpc_reg_operand (operands[2], SImode))"
9538 "@
9539 stfdux %3,%0,%2
9540 stfdu %3,%2(%0)"
9541 [(set_attr "type" "fpstore_ux,fpstore_u")])
9544 ;; After inserting conditional returns we can sometimes have
9545 ;; unnecessary register moves. Unfortunately we cannot have a
9546 ;; modeless peephole here, because some single SImode sets have early
9547 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9548 ;; sequences, using get_attr_length here will smash the operands
9549 ;; array. Neither is there an early_cobbler_p predicate.
9550 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9551 (define_peephole2
9552 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9553 (match_operand:DF 1 "any_operand" ""))
9554 (set (match_operand:DF 2 "gpc_reg_operand" "")
9555 (match_dup 0))]
9556 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9557 && peep2_reg_dead_p (2, operands[0])"
9558 [(set (match_dup 2) (match_dup 1))])
9560 (define_peephole2
9561 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9562 (match_operand:SF 1 "any_operand" ""))
9563 (set (match_operand:SF 2 "gpc_reg_operand" "")
9564 (match_dup 0))]
9565 "peep2_reg_dead_p (2, operands[0])"
9566 [(set (match_dup 2) (match_dup 1))])
9568 \f
9569 ;; TLS support.
9571 ;; Mode attributes for different ABIs.
9572 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9573 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9574 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9575 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9577 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9578 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9579 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9580 (match_operand 4 "" "g")))
9581 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9582 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9583 UNSPEC_TLSGD)
9584 (clobber (reg:SI LR_REGNO))]
9585 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9586 {
9587 if (TARGET_CMODEL != CMODEL_SMALL)
9588 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9589 "bl %z3\;nop";
9590 else
9591 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9592 }
9593 "&& TARGET_TLS_MARKERS"
9594 [(set (match_dup 0)
9595 (unspec:TLSmode [(match_dup 1)
9596 (match_dup 2)]
9597 UNSPEC_TLSGD))
9598 (parallel [(set (match_dup 0)
9599 (call (mem:TLSmode (match_dup 3))
9600 (match_dup 4)))
9601 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9602 (clobber (reg:SI LR_REGNO))])]
9603 ""
9604 [(set_attr "type" "two")
9605 (set (attr "length")
9606 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9607 (const_int 16)
9608 (const_int 12)))])
9610 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9611 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9612 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9613 (match_operand 4 "" "g")))
9614 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9615 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9616 UNSPEC_TLSGD)
9617 (clobber (reg:SI LR_REGNO))]
9618 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9619 {
9620 if (flag_pic)
9621 {
9622 if (TARGET_SECURE_PLT && flag_pic == 2)
9623 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9624 else
9625 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9626 }
9627 else
9628 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9629 }
9630 "&& TARGET_TLS_MARKERS"
9631 [(set (match_dup 0)
9632 (unspec:TLSmode [(match_dup 1)
9633 (match_dup 2)]
9634 UNSPEC_TLSGD))
9635 (parallel [(set (match_dup 0)
9636 (call (mem:TLSmode (match_dup 3))
9637 (match_dup 4)))
9638 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9639 (clobber (reg:SI LR_REGNO))])]
9640 ""
9641 [(set_attr "type" "two")
9642 (set_attr "length" "8")])
9644 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9645 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9646 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9647 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9648 UNSPEC_TLSGD))]
9649 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9650 "addi %0,%1,%2@got@tlsgd"
9651 "&& TARGET_CMODEL != CMODEL_SMALL"
9652 [(set (match_dup 3)
9653 (high:TLSmode
9654 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9655 (set (match_dup 0)
9656 (lo_sum:TLSmode (match_dup 3)
9657 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
9658 "
9659 {
9660 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9661 }"
9662 [(set (attr "length")
9663 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9664 (const_int 8)
9665 (const_int 4)))])
9667 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9668 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9669 (high:TLSmode
9670 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9671 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9672 UNSPEC_TLSGD)))]
9673 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9674 "addis %0,%1,%2@got@tlsgd@ha"
9675 [(set_attr "length" "4")])
9677 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9678 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9679 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9680 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9681 UNSPEC_TLSGD)))]
9682 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9683 "addi %0,%1,%2@got@tlsgd@l"
9684 [(set_attr "length" "4")])
9686 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9687 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9688 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9689 (match_operand 2 "" "g")))
9690 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9691 UNSPEC_TLSGD)
9692 (clobber (reg:SI LR_REGNO))]
9693 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9694 "bl %z1(%3@tlsgd)\;nop"
9695 [(set_attr "type" "branch")
9696 (set_attr "length" "8")])
9698 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9699 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9700 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9701 (match_operand 2 "" "g")))
9702 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9703 UNSPEC_TLSGD)
9704 (clobber (reg:SI LR_REGNO))]
9705 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9706 {
9707 if (flag_pic)
9708 {
9709 if (TARGET_SECURE_PLT && flag_pic == 2)
9710 return "bl %z1+32768(%3@tlsgd)@plt";
9711 return "bl %z1(%3@tlsgd)@plt";
9712 }
9713 return "bl %z1(%3@tlsgd)";
9714 }
9715 [(set_attr "type" "branch")
9716 (set_attr "length" "4")])
9718 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9719 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9720 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9721 (match_operand 3 "" "g")))
9722 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9723 UNSPEC_TLSLD)
9724 (clobber (reg:SI LR_REGNO))]
9725 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9726 {
9727 if (TARGET_CMODEL != CMODEL_SMALL)
9728 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9729 "bl %z2\;nop";
9730 else
9731 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9732 }
9733 "&& TARGET_TLS_MARKERS"
9734 [(set (match_dup 0)
9735 (unspec:TLSmode [(match_dup 1)]
9736 UNSPEC_TLSLD))
9737 (parallel [(set (match_dup 0)
9738 (call (mem:TLSmode (match_dup 2))
9739 (match_dup 3)))
9740 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9741 (clobber (reg:SI LR_REGNO))])]
9742 ""
9743 [(set_attr "type" "two")
9744 (set (attr "length")
9745 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9746 (const_int 16)
9747 (const_int 12)))])
9749 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9750 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9751 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9752 (match_operand 3 "" "g")))
9753 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9754 UNSPEC_TLSLD)
9755 (clobber (reg:SI LR_REGNO))]
9756 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9757 {
9758 if (flag_pic)
9759 {
9760 if (TARGET_SECURE_PLT && flag_pic == 2)
9761 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9762 else
9763 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9764 }
9765 else
9766 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9767 }
9768 "&& TARGET_TLS_MARKERS"
9769 [(set (match_dup 0)
9770 (unspec:TLSmode [(match_dup 1)]
9771 UNSPEC_TLSLD))
9772 (parallel [(set (match_dup 0)
9773 (call (mem:TLSmode (match_dup 2))
9774 (match_dup 3)))
9775 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9776 (clobber (reg:SI LR_REGNO))])]
9777 ""
9778 [(set_attr "length" "8")])
9780 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
9781 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9782 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9783 UNSPEC_TLSLD))]
9784 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9785 "addi %0,%1,%&@got@tlsld"
9786 "&& TARGET_CMODEL != CMODEL_SMALL"
9787 [(set (match_dup 2)
9788 (high:TLSmode
9789 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
9790 (set (match_dup 0)
9791 (lo_sum:TLSmode (match_dup 2)
9792 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9793 "
9794 {
9795 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9796 }"
9797 [(set (attr "length")
9798 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9799 (const_int 8)
9800 (const_int 4)))])
9802 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
9803 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9804 (high:TLSmode
9805 (unspec:TLSmode [(const_int 0)
9806 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9807 UNSPEC_TLSLD)))]
9808 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9809 "addis %0,%1,%&@got@tlsld@ha"
9810 [(set_attr "length" "4")])
9812 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
9813 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9814 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9815 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9816 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9817 "addi %0,%1,%&@got@tlsld@l"
9818 [(set_attr "length" "4")])
9820 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
9821 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9822 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9823 (match_operand 2 "" "g")))
9824 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9825 (clobber (reg:SI LR_REGNO))]
9826 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9827 "bl %z1(%&@tlsld)\;nop"
9828 [(set_attr "type" "branch")
9829 (set_attr "length" "8")])
9831 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
9832 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9833 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9834 (match_operand 2 "" "g")))
9835 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9836 (clobber (reg:SI LR_REGNO))]
9837 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9838 {
9839 if (flag_pic)
9840 {
9841 if (TARGET_SECURE_PLT && flag_pic == 2)
9842 return "bl %z1+32768(%&@tlsld)@plt";
9843 return "bl %z1(%&@tlsld)@plt";
9844 }
9845 return "bl %z1(%&@tlsld)";
9846 }
9847 [(set_attr "type" "branch")
9848 (set_attr "length" "4")])
9850 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
9851 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9852 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9853 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9854 UNSPEC_TLSDTPREL))]
9855 "HAVE_AS_TLS"
9856 "addi %0,%1,%2@dtprel")
9858 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
9859 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9860 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9861 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9862 UNSPEC_TLSDTPRELHA))]
9863 "HAVE_AS_TLS"
9864 "addis %0,%1,%2@dtprel@ha")
9866 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
9867 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9868 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9869 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9870 UNSPEC_TLSDTPRELLO))]
9871 "HAVE_AS_TLS"
9872 "addi %0,%1,%2@dtprel@l")
9874 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
9875 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9876 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9877 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9878 UNSPEC_TLSGOTDTPREL))]
9879 "HAVE_AS_TLS"
9880 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
9881 "&& TARGET_CMODEL != CMODEL_SMALL"
9882 [(set (match_dup 3)
9883 (high:TLSmode
9884 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
9885 (set (match_dup 0)
9886 (lo_sum:TLSmode (match_dup 3)
9887 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
9888 "
9889 {
9890 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9891 }"
9892 [(set (attr "length")
9893 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9894 (const_int 8)
9895 (const_int 4)))])
9897 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
9898 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9899 (high:TLSmode
9900 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9901 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9902 UNSPEC_TLSGOTDTPREL)))]
9903 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9904 "addis %0,%1,%2@got@dtprel@ha"
9905 [(set_attr "length" "4")])
9907 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
9908 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9909 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9910 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9911 UNSPEC_TLSGOTDTPREL)))]
9912 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9913 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
9914 [(set_attr "length" "4")])
9916 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
9917 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9918 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9919 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9920 UNSPEC_TLSTPREL))]
9921 "HAVE_AS_TLS"
9922 "addi %0,%1,%2@tprel")
9924 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
9925 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9926 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9927 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9928 UNSPEC_TLSTPRELHA))]
9929 "HAVE_AS_TLS"
9930 "addis %0,%1,%2@tprel@ha")
9932 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
9933 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9934 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9935 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9936 UNSPEC_TLSTPRELLO))]
9937 "HAVE_AS_TLS"
9938 "addi %0,%1,%2@tprel@l")
9940 ;; "b" output constraint here and on tls_tls input to support linker tls
9941 ;; optimization. The linker may edit the instructions emitted by a
9942 ;; tls_got_tprel/tls_tls pair to addis,addi.
9943 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
9944 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9945 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9946 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9947 UNSPEC_TLSGOTTPREL))]
9948 "HAVE_AS_TLS"
9949 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
9950 "&& TARGET_CMODEL != CMODEL_SMALL"
9951 [(set (match_dup 3)
9952 (high:TLSmode
9953 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
9954 (set (match_dup 0)
9955 (lo_sum:TLSmode (match_dup 3)
9956 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
9957 "
9958 {
9959 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9960 }"
9961 [(set (attr "length")
9962 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9963 (const_int 8)
9964 (const_int 4)))])
9966 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
9967 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9968 (high:TLSmode
9969 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9970 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9971 UNSPEC_TLSGOTTPREL)))]
9972 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9973 "addis %0,%1,%2@got@tprel@ha"
9974 [(set_attr "length" "4")])
9976 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
9977 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9978 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9979 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9980 UNSPEC_TLSGOTTPREL)))]
9981 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9982 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
9983 [(set_attr "length" "4")])
9985 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
9986 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9987 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9988 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9989 UNSPEC_TLSTLS))]
9990 "HAVE_AS_TLS"
9991 "add %0,%1,%2@tls")
9992 \f
9993 ;; Next come insns related to the calling sequence.
9994 ;;
9995 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9996 ;; We move the back-chain and decrement the stack pointer.
9998 (define_expand "allocate_stack"
9999 [(set (match_operand 0 "gpc_reg_operand" "")
10000 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10001 (set (reg 1)
10002 (minus (reg 1) (match_dup 1)))]
10003 ""
10004 "
10005 { rtx chain = gen_reg_rtx (Pmode);
10006 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10007 rtx neg_op0;
10008 rtx insn, par, set, mem;
10010 emit_move_insn (chain, stack_bot);
10012 /* Check stack bounds if necessary. */
10013 if (crtl->limit_stack)
10014 {
10015 rtx available;
10016 available = expand_binop (Pmode, sub_optab,
10017 stack_pointer_rtx, stack_limit_rtx,
10018 NULL_RTX, 1, OPTAB_WIDEN);
10019 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10020 }
10022 if (GET_CODE (operands[1]) != CONST_INT
10023 || INTVAL (operands[1]) < -32767
10024 || INTVAL (operands[1]) > 32768)
10025 {
10026 neg_op0 = gen_reg_rtx (Pmode);
10027 if (TARGET_32BIT)
10028 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10029 else
10030 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10031 }
10032 else
10033 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10035 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10036 : gen_movdi_di_update_stack))
10037 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10038 chain));
10039 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10040 it now and set the alias set/attributes. The above gen_*_update
10041 calls will generate a PARALLEL with the MEM set being the first
10042 operation. */
10043 par = PATTERN (insn);
10044 gcc_assert (GET_CODE (par) == PARALLEL);
10045 set = XVECEXP (par, 0, 0);
10046 gcc_assert (GET_CODE (set) == SET);
10047 mem = SET_DEST (set);
10048 gcc_assert (MEM_P (mem));
10049 MEM_NOTRAP_P (mem) = 1;
10050 set_mem_alias_set (mem, get_frame_alias_set ());
10052 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10053 DONE;
10054 }")
10056 ;; These patterns say how to save and restore the stack pointer. We need not
10057 ;; save the stack pointer at function level since we are careful to
10058 ;; preserve the backchain. At block level, we have to restore the backchain
10059 ;; when we restore the stack pointer.
10060 ;;
10061 ;; For nonlocal gotos, we must save both the stack pointer and its
10062 ;; backchain and restore both. Note that in the nonlocal case, the
10063 ;; save area is a memory location.
10065 (define_expand "save_stack_function"
10066 [(match_operand 0 "any_operand" "")
10067 (match_operand 1 "any_operand" "")]
10068 ""
10069 "DONE;")
10071 (define_expand "restore_stack_function"
10072 [(match_operand 0 "any_operand" "")
10073 (match_operand 1 "any_operand" "")]
10074 ""
10075 "DONE;")
10077 ;; Adjust stack pointer (op0) to a new value (op1).
10078 ;; First copy old stack backchain to new location, and ensure that the
10079 ;; scheduler won't reorder the sp assignment before the backchain write.
10080 (define_expand "restore_stack_block"
10081 [(set (match_dup 2) (match_dup 3))
10082 (set (match_dup 4) (match_dup 2))
10083 (match_dup 5)
10084 (set (match_operand 0 "register_operand" "")
10085 (match_operand 1 "register_operand" ""))]
10086 ""
10087 "
10088 {
10089 rtvec p;
10091 operands[1] = force_reg (Pmode, operands[1]);
10092 operands[2] = gen_reg_rtx (Pmode);
10093 operands[3] = gen_frame_mem (Pmode, operands[0]);
10094 operands[4] = gen_frame_mem (Pmode, operands[1]);
10095 p = rtvec_alloc (1);
10096 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10097 gen_frame_mem (BLKmode, operands[0]),
10098 const0_rtx);
10099 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10100 }")
10102 (define_expand "save_stack_nonlocal"
10103 [(set (match_dup 3) (match_dup 4))
10104 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10105 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10106 ""
10107 "
10108 {
10109 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10111 /* Copy the backchain to the first word, sp to the second. */
10112 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10113 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10114 operands[3] = gen_reg_rtx (Pmode);
10115 operands[4] = gen_frame_mem (Pmode, operands[1]);
10116 }")
10118 (define_expand "restore_stack_nonlocal"
10119 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10120 (set (match_dup 3) (match_dup 4))
10121 (set (match_dup 5) (match_dup 2))
10122 (match_dup 6)
10123 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10124 ""
10125 "
10126 {
10127 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10128 rtvec p;
10130 /* Restore the backchain from the first word, sp from the second. */
10131 operands[2] = gen_reg_rtx (Pmode);
10132 operands[3] = gen_reg_rtx (Pmode);
10133 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10134 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10135 operands[5] = gen_frame_mem (Pmode, operands[3]);
10136 p = rtvec_alloc (1);
10137 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10138 gen_frame_mem (BLKmode, operands[0]),
10139 const0_rtx);
10140 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10141 }")
10142 \f
10143 ;; TOC register handling.
10145 ;; Code to initialize the TOC register...
10147 (define_insn "load_toc_aix_si"
10148 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10149 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10150 (use (reg:SI 2))])]
10151 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10152 "*
10153 {
10154 char buf[30];
10155 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10156 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10157 operands[2] = gen_rtx_REG (Pmode, 2);
10158 return \"lwz %0,%1(%2)\";
10159 }"
10160 [(set_attr "type" "load")])
10162 (define_insn "load_toc_aix_di"
10163 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10164 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10165 (use (reg:DI 2))])]
10166 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10167 "*
10168 {
10169 char buf[30];
10170 #ifdef TARGET_RELOCATABLE
10171 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10172 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10173 #else
10174 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10175 #endif
10176 if (TARGET_ELF)
10177 strcat (buf, \"@toc\");
10178 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10179 operands[2] = gen_rtx_REG (Pmode, 2);
10180 return \"ld %0,%1(%2)\";
10181 }"
10182 [(set_attr "type" "load")])
10184 (define_insn "load_toc_v4_pic_si"
10185 [(set (reg:SI LR_REGNO)
10186 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10187 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10188 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10189 [(set_attr "type" "branch")
10190 (set_attr "length" "4")])
10192 (define_expand "load_toc_v4_PIC_1"
10193 [(parallel [(set (reg:SI LR_REGNO)
10194 (match_operand:SI 0 "immediate_operand" "s"))
10195 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10196 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10197 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10198 "")
10200 (define_insn "load_toc_v4_PIC_1_normal"
10201 [(set (reg:SI LR_REGNO)
10202 (match_operand:SI 0 "immediate_operand" "s"))
10203 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10204 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10205 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10206 "bcl 20,31,%0\\n%0:"
10207 [(set_attr "type" "branch")
10208 (set_attr "length" "4")])
10210 (define_insn "load_toc_v4_PIC_1_476"
10211 [(set (reg:SI LR_REGNO)
10212 (match_operand:SI 0 "immediate_operand" "s"))
10213 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10214 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10215 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10216 "*
10217 {
10218 char name[32];
10219 static char templ[32];
10221 get_ppc476_thunk_name (name);
10222 sprintf (templ, \"bl %s\\n%%0:\", name);
10223 return templ;
10224 }"
10225 [(set_attr "type" "branch")
10226 (set_attr "length" "4")])
10228 (define_expand "load_toc_v4_PIC_1b"
10229 [(parallel [(set (reg:SI LR_REGNO)
10230 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10231 (label_ref (match_operand 1 "" ""))]
10232 UNSPEC_TOCPTR))
10233 (match_dup 1)])]
10234 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10235 "")
10237 (define_insn "load_toc_v4_PIC_1b_normal"
10238 [(set (reg:SI LR_REGNO)
10239 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10240 (label_ref (match_operand 1 "" ""))]
10241 UNSPEC_TOCPTR))
10242 (match_dup 1)]
10243 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10244 "bcl 20,31,$+8\;.long %0-$"
10245 [(set_attr "type" "branch")
10246 (set_attr "length" "8")])
10248 (define_insn "load_toc_v4_PIC_1b_476"
10249 [(set (reg:SI LR_REGNO)
10250 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10251 (label_ref (match_operand 1 "" ""))]
10252 UNSPEC_TOCPTR))
10253 (match_dup 1)]
10254 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10255 "*
10256 {
10257 char name[32];
10258 static char templ[32];
10260 get_ppc476_thunk_name (name);
10261 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10262 return templ;
10263 }"
10264 [(set_attr "type" "branch")
10265 (set_attr "length" "16")])
10267 (define_insn "load_toc_v4_PIC_2"
10268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10269 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10270 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10271 (match_operand:SI 3 "immediate_operand" "s")))))]
10272 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10273 "lwz %0,%2-%3(%1)"
10274 [(set_attr "type" "load")])
10276 (define_insn "load_toc_v4_PIC_3b"
10277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10278 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10279 (high:SI
10280 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10281 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10282 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10283 "addis %0,%1,%2-%3@ha")
10285 (define_insn "load_toc_v4_PIC_3c"
10286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10287 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10288 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10289 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10290 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10291 "addi %0,%1,%2-%3@l")
10293 ;; If the TOC is shared over a translation unit, as happens with all
10294 ;; the kinds of PIC that we support, we need to restore the TOC
10295 ;; pointer only when jumping over units of translation.
10296 ;; On Darwin, we need to reload the picbase.
10298 (define_expand "builtin_setjmp_receiver"
10299 [(use (label_ref (match_operand 0 "" "")))]
10300 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10301 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10302 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10303 "
10304 {
10305 #if TARGET_MACHO
10306 if (DEFAULT_ABI == ABI_DARWIN)
10307 {
10308 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10309 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10310 rtx tmplabrtx;
10311 char tmplab[20];
10313 crtl->uses_pic_offset_table = 1;
10314 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10315 CODE_LABEL_NUMBER (operands[0]));
10316 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10318 emit_insn (gen_load_macho_picbase (tmplabrtx));
10319 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10320 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10321 }
10322 else
10323 #endif
10324 rs6000_emit_load_toc_table (FALSE);
10325 DONE;
10326 }")
10328 ;; Largetoc support
10329 (define_insn "*largetoc_high"
10330 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10331 (high:DI
10332 (unspec [(match_operand:DI 1 "" "")
10333 (match_operand:DI 2 "gpc_reg_operand" "b")]
10334 UNSPEC_TOCREL)))]
10335 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10336 "addis %0,%2,%1@toc@ha")
10338 (define_insn "*largetoc_high_plus"
10339 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10340 (high:DI
10341 (plus:DI
10342 (unspec [(match_operand:DI 1 "" "")
10343 (match_operand:DI 2 "gpc_reg_operand" "b")]
10344 UNSPEC_TOCREL)
10345 (match_operand 3 "const_int_operand" "n"))))]
10346 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10347 "addis %0,%2,%1+%3@toc@ha")
10349 (define_insn "*largetoc_low"
10350 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10351 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10352 (match_operand:DI 2 "" "")))]
10353 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10354 "@
10355 addi %0,%1,%2@l
10356 addic %0,%1,%2@l")
10358 (define_insn_and_split "*tocref<mode>"
10359 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10360 (match_operand:P 1 "small_toc_ref" "R"))]
10361 "TARGET_TOC"
10362 "la %0,%a1"
10363 "&& TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10364 [(set (match_dup 0) (high:P (match_dup 1)))
10365 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10367 ;; Elf specific ways of loading addresses for non-PIC code.
10368 ;; The output of this could be r0, but we make a very strong
10369 ;; preference for a base register because it will usually
10370 ;; be needed there.
10371 (define_insn "elf_high"
10372 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10373 (high:SI (match_operand 1 "" "")))]
10374 "TARGET_ELF && ! TARGET_64BIT"
10375 "lis %0,%1@ha")
10377 (define_insn "elf_low"
10378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10379 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10380 (match_operand 2 "" "")))]
10381 "TARGET_ELF && ! TARGET_64BIT"
10382 "@
10383 la %0,%2@l(%1)
10384 addic %0,%1,%K2")
10385 \f
10386 ;; Call and call_value insns
10387 (define_expand "call"
10388 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10389 (match_operand 1 "" ""))
10390 (use (match_operand 2 "" ""))
10391 (clobber (reg:SI LR_REGNO))])]
10392 ""
10393 "
10394 {
10395 #if TARGET_MACHO
10396 if (MACHOPIC_INDIRECT)
10397 operands[0] = machopic_indirect_call_target (operands[0]);
10398 #endif
10400 gcc_assert (GET_CODE (operands[0]) == MEM);
10401 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10403 operands[0] = XEXP (operands[0], 0);
10405 if (GET_CODE (operands[0]) != SYMBOL_REF
10406 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10407 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10408 {
10409 if (INTVAL (operands[2]) & CALL_LONG)
10410 operands[0] = rs6000_longcall_ref (operands[0]);
10412 switch (DEFAULT_ABI)
10413 {
10414 case ABI_V4:
10415 case ABI_DARWIN:
10416 operands[0] = force_reg (Pmode, operands[0]);
10417 break;
10419 case ABI_AIX:
10420 /* AIX function pointers are really pointers to a three word
10421 area. */
10422 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
10423 DONE;
10425 default:
10426 gcc_unreachable ();
10427 }
10428 }
10429 }")
10431 (define_expand "call_value"
10432 [(parallel [(set (match_operand 0 "" "")
10433 (call (mem:SI (match_operand 1 "address_operand" ""))
10434 (match_operand 2 "" "")))
10435 (use (match_operand 3 "" ""))
10436 (clobber (reg:SI LR_REGNO))])]
10437 ""
10438 "
10439 {
10440 #if TARGET_MACHO
10441 if (MACHOPIC_INDIRECT)
10442 operands[1] = machopic_indirect_call_target (operands[1]);
10443 #endif
10445 gcc_assert (GET_CODE (operands[1]) == MEM);
10446 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10448 operands[1] = XEXP (operands[1], 0);
10450 if (GET_CODE (operands[1]) != SYMBOL_REF
10451 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10452 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10453 {
10454 if (INTVAL (operands[3]) & CALL_LONG)
10455 operands[1] = rs6000_longcall_ref (operands[1]);
10457 switch (DEFAULT_ABI)
10458 {
10459 case ABI_V4:
10460 case ABI_DARWIN:
10461 operands[1] = force_reg (Pmode, operands[1]);
10462 break;
10464 case ABI_AIX:
10465 /* AIX function pointers are really pointers to a three word
10466 area. */
10467 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
10468 DONE;
10470 default:
10471 gcc_unreachable ();
10472 }
10473 }
10474 }")
10476 ;; Call to function in current module. No TOC pointer reload needed.
10477 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10478 ;; either the function was not prototyped, or it was prototyped as a
10479 ;; variable argument function. It is > 0 if FP registers were passed
10480 ;; and < 0 if they were not.
10482 (define_insn "*call_local32"
10483 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10484 (match_operand 1 "" "g,g"))
10485 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10486 (clobber (reg:SI LR_REGNO))]
10487 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10488 "*
10489 {
10490 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10491 output_asm_insn (\"crxor 6,6,6\", operands);
10493 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10494 output_asm_insn (\"creqv 6,6,6\", operands);
10496 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10497 }"
10498 [(set_attr "type" "branch")
10499 (set_attr "length" "4,8")])
10501 (define_insn "*call_local64"
10502 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10503 (match_operand 1 "" "g,g"))
10504 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10505 (clobber (reg:SI LR_REGNO))]
10506 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10507 "*
10508 {
10509 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10510 output_asm_insn (\"crxor 6,6,6\", operands);
10512 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10513 output_asm_insn (\"creqv 6,6,6\", operands);
10515 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10516 }"
10517 [(set_attr "type" "branch")
10518 (set_attr "length" "4,8")])
10520 (define_insn "*call_value_local32"
10521 [(set (match_operand 0 "" "")
10522 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10523 (match_operand 2 "" "g,g")))
10524 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10525 (clobber (reg:SI LR_REGNO))]
10526 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10527 "*
10528 {
10529 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10530 output_asm_insn (\"crxor 6,6,6\", operands);
10532 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10533 output_asm_insn (\"creqv 6,6,6\", operands);
10535 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10536 }"
10537 [(set_attr "type" "branch")
10538 (set_attr "length" "4,8")])
10541 (define_insn "*call_value_local64"
10542 [(set (match_operand 0 "" "")
10543 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10544 (match_operand 2 "" "g,g")))
10545 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10546 (clobber (reg:SI LR_REGNO))]
10547 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10548 "*
10549 {
10550 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10551 output_asm_insn (\"crxor 6,6,6\", operands);
10553 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10554 output_asm_insn (\"creqv 6,6,6\", operands);
10556 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10557 }"
10558 [(set_attr "type" "branch")
10559 (set_attr "length" "4,8")])
10561 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
10562 ;; Operand0 is the addresss of the function to call
10563 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10564 ;; Operand2 is the location in the function descriptor to load r2 from
10565 ;; Operand3 is the stack location to hold the current TOC pointer
10567 (define_insn "call_indirect_aix<ptrsize>"
10568 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10569 (match_operand 1 "" "g,g"))
10570 (use (match_operand:P 2 "memory_operand" "m,m"))
10571 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10572 (use (reg:P STATIC_CHAIN_REGNUM))
10573 (clobber (reg:P LR_REGNO))]
10574 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10575 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10576 [(set_attr "type" "jmpreg")
10577 (set_attr "length" "12")])
10579 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
10580 ;; Operand0 is the addresss of the function to call
10581 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10582 ;; Operand2 is the location in the function descriptor to load r2 from
10583 ;; Operand3 is the stack location to hold the current TOC pointer
10585 (define_insn "call_indirect_aix<ptrsize>_nor11"
10586 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10587 (match_operand 1 "" "g,g"))
10588 (use (match_operand:P 2 "memory_operand" "m,m"))
10589 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10590 (clobber (reg:P LR_REGNO))]
10591 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10592 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10593 [(set_attr "type" "jmpreg")
10594 (set_attr "length" "12")])
10596 ;; Operand0 is the return result of the function
10597 ;; Operand1 is the addresss of the function to call
10598 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10599 ;; Operand3 is the location in the function descriptor to load r2 from
10600 ;; Operand4 is the stack location to hold the current TOC pointer
10602 (define_insn "call_value_indirect_aix<ptrsize>"
10603 [(set (match_operand 0 "" "")
10604 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10605 (match_operand 2 "" "g,g")))
10606 (use (match_operand:P 3 "memory_operand" "m,m"))
10607 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10608 (use (reg:P STATIC_CHAIN_REGNUM))
10609 (clobber (reg:P LR_REGNO))]
10610 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10611 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10612 [(set_attr "type" "jmpreg")
10613 (set_attr "length" "12")])
10615 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
10616 ;; Operand0 is the return result of the function
10617 ;; Operand1 is the addresss of the function to call
10618 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10619 ;; Operand3 is the location in the function descriptor to load r2 from
10620 ;; Operand4 is the stack location to hold the current TOC pointer
10622 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
10623 [(set (match_operand 0 "" "")
10624 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10625 (match_operand 2 "" "g,g")))
10626 (use (match_operand:P 3 "memory_operand" "m,m"))
10627 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10628 (clobber (reg:P LR_REGNO))]
10629 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10630 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10631 [(set_attr "type" "jmpreg")
10632 (set_attr "length" "12")])
10634 ;; Call to function which may be in another module. Restore the TOC
10635 ;; pointer (r2) after the call unless this is System V.
10636 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10637 ;; either the function was not prototyped, or it was prototyped as a
10638 ;; variable argument function. It is > 0 if FP registers were passed
10639 ;; and < 0 if they were not.
10641 (define_insn "*call_nonlocal_aix32"
10642 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10643 (match_operand 1 "" "g"))
10644 (use (match_operand:SI 2 "immediate_operand" "O"))
10645 (clobber (reg:SI LR_REGNO))]
10646 "TARGET_32BIT
10647 && DEFAULT_ABI == ABI_AIX
10648 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10649 "bl %z0\;nop"
10650 [(set_attr "type" "branch")
10651 (set_attr "length" "8")])
10653 (define_insn "*call_nonlocal_aix64"
10654 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10655 (match_operand 1 "" "g"))
10656 (use (match_operand:SI 2 "immediate_operand" "O"))
10657 (clobber (reg:SI LR_REGNO))]
10658 "TARGET_64BIT
10659 && DEFAULT_ABI == ABI_AIX
10660 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10661 "bl %z0\;nop"
10662 [(set_attr "type" "branch")
10663 (set_attr "length" "8")])
10665 (define_insn "*call_value_nonlocal_aix32"
10666 [(set (match_operand 0 "" "")
10667 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10668 (match_operand 2 "" "g")))
10669 (use (match_operand:SI 3 "immediate_operand" "O"))
10670 (clobber (reg:SI LR_REGNO))]
10671 "TARGET_32BIT
10672 && DEFAULT_ABI == ABI_AIX
10673 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10674 "bl %z1\;nop"
10675 [(set_attr "type" "branch")
10676 (set_attr "length" "8")])
10678 (define_insn "*call_value_nonlocal_aix64"
10679 [(set (match_operand 0 "" "")
10680 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10681 (match_operand 2 "" "g")))
10682 (use (match_operand:SI 3 "immediate_operand" "O"))
10683 (clobber (reg:SI LR_REGNO))]
10684 "TARGET_64BIT
10685 && DEFAULT_ABI == ABI_AIX
10686 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10687 "bl %z1\;nop"
10688 [(set_attr "type" "branch")
10689 (set_attr "length" "8")])
10691 ;; A function pointer under System V is just a normal pointer
10692 ;; operands[0] is the function pointer
10693 ;; operands[1] is the stack size to clean up
10694 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10695 ;; which indicates how to set cr1
10697 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10698 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10699 (match_operand 1 "" "g,g,g,g"))
10700 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10701 (clobber (reg:SI LR_REGNO))]
10702 "DEFAULT_ABI == ABI_V4
10703 || DEFAULT_ABI == ABI_DARWIN"
10704 {
10705 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10706 output_asm_insn ("crxor 6,6,6", operands);
10708 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10709 output_asm_insn ("creqv 6,6,6", operands);
10711 return "b%T0l";
10712 }
10713 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10714 (set_attr "length" "4,4,8,8")])
10716 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10717 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10718 (match_operand 1 "" "g,g"))
10719 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10720 (clobber (reg:SI LR_REGNO))]
10721 "(DEFAULT_ABI == ABI_DARWIN
10722 || (DEFAULT_ABI == ABI_V4
10723 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10724 {
10725 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10726 output_asm_insn ("crxor 6,6,6", operands);
10728 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10729 output_asm_insn ("creqv 6,6,6", operands);
10731 #if TARGET_MACHO
10732 return output_call(insn, operands, 0, 2);
10733 #else
10734 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10735 {
10736 gcc_assert (!TARGET_SECURE_PLT);
10737 return "bl %z0@plt";
10738 }
10739 else
10740 return "bl %z0";
10741 #endif
10742 }
10743 "DEFAULT_ABI == ABI_V4
10744 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10745 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10746 [(parallel [(call (mem:SI (match_dup 0))
10747 (match_dup 1))
10748 (use (match_dup 2))
10749 (use (match_dup 3))
10750 (clobber (reg:SI LR_REGNO))])]
10751 {
10752 operands[3] = pic_offset_table_rtx;
10753 }
10754 [(set_attr "type" "branch,branch")
10755 (set_attr "length" "4,8")])
10757 (define_insn "*call_nonlocal_sysv_secure<mode>"
10758 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10759 (match_operand 1 "" "g,g"))
10760 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10761 (use (match_operand:SI 3 "register_operand" "r,r"))
10762 (clobber (reg:SI LR_REGNO))]
10763 "(DEFAULT_ABI == ABI_V4
10764 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10765 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10766 {
10767 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10768 output_asm_insn ("crxor 6,6,6", operands);
10770 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10771 output_asm_insn ("creqv 6,6,6", operands);
10773 if (flag_pic == 2)
10774 /* The magic 32768 offset here and in the other sysv call insns
10775 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10776 See sysv4.h:toc_section. */
10777 return "bl %z0+32768@plt";
10778 else
10779 return "bl %z0@plt";
10780 }
10781 [(set_attr "type" "branch,branch")
10782 (set_attr "length" "4,8")])
10784 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10785 [(set (match_operand 0 "" "")
10786 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10787 (match_operand 2 "" "g,g,g,g")))
10788 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10789 (clobber (reg:SI LR_REGNO))]
10790 "DEFAULT_ABI == ABI_V4
10791 || DEFAULT_ABI == ABI_DARWIN"
10792 {
10793 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10794 output_asm_insn ("crxor 6,6,6", operands);
10796 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10797 output_asm_insn ("creqv 6,6,6", operands);
10799 return "b%T1l";
10800 }
10801 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10802 (set_attr "length" "4,4,8,8")])
10804 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10805 [(set (match_operand 0 "" "")
10806 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10807 (match_operand 2 "" "g,g")))
10808 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10809 (clobber (reg:SI LR_REGNO))]
10810 "(DEFAULT_ABI == ABI_DARWIN
10811 || (DEFAULT_ABI == ABI_V4
10812 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10813 {
10814 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10815 output_asm_insn ("crxor 6,6,6", operands);
10817 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10818 output_asm_insn ("creqv 6,6,6", operands);
10820 #if TARGET_MACHO
10821 return output_call(insn, operands, 1, 3);
10822 #else
10823 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10824 {
10825 gcc_assert (!TARGET_SECURE_PLT);
10826 return "bl %z1@plt";
10827 }
10828 else
10829 return "bl %z1";
10830 #endif
10831 }
10832 "DEFAULT_ABI == ABI_V4
10833 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10834 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10835 [(parallel [(set (match_dup 0)
10836 (call (mem:SI (match_dup 1))
10837 (match_dup 2)))
10838 (use (match_dup 3))
10839 (use (match_dup 4))
10840 (clobber (reg:SI LR_REGNO))])]
10841 {
10842 operands[4] = pic_offset_table_rtx;
10843 }
10844 [(set_attr "type" "branch,branch")
10845 (set_attr "length" "4,8")])
10847 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
10848 [(set (match_operand 0 "" "")
10849 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10850 (match_operand 2 "" "g,g")))
10851 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10852 (use (match_operand:SI 4 "register_operand" "r,r"))
10853 (clobber (reg:SI LR_REGNO))]
10854 "(DEFAULT_ABI == ABI_V4
10855 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10856 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
10857 {
10858 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10859 output_asm_insn ("crxor 6,6,6", operands);
10861 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10862 output_asm_insn ("creqv 6,6,6", operands);
10864 if (flag_pic == 2)
10865 return "bl %z1+32768@plt";
10866 else
10867 return "bl %z1@plt";
10868 }
10869 [(set_attr "type" "branch,branch")
10870 (set_attr "length" "4,8")])
10872 ;; Call subroutine returning any type.
10873 (define_expand "untyped_call"
10874 [(parallel [(call (match_operand 0 "" "")
10875 (const_int 0))
10876 (match_operand 1 "" "")
10877 (match_operand 2 "" "")])]
10878 ""
10879 "
10880 {
10881 int i;
10883 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10885 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10886 {
10887 rtx set = XVECEXP (operands[2], 0, i);
10888 emit_move_insn (SET_DEST (set), SET_SRC (set));
10889 }
10891 /* The optimizer does not know that the call sets the function value
10892 registers we stored in the result block. We avoid problems by
10893 claiming that all hard registers are used and clobbered at this
10894 point. */
10895 emit_insn (gen_blockage ());
10897 DONE;
10898 }")
10900 ;; sibling call patterns
10901 (define_expand "sibcall"
10902 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10903 (match_operand 1 "" ""))
10904 (use (match_operand 2 "" ""))
10905 (use (reg:SI LR_REGNO))
10906 (simple_return)])]
10907 ""
10908 "
10909 {
10910 #if TARGET_MACHO
10911 if (MACHOPIC_INDIRECT)
10912 operands[0] = machopic_indirect_call_target (operands[0]);
10913 #endif
10915 gcc_assert (GET_CODE (operands[0]) == MEM);
10916 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10918 operands[0] = XEXP (operands[0], 0);
10919 }")
10921 ;; this and similar patterns must be marked as using LR, otherwise
10922 ;; dataflow will try to delete the store into it. This is true
10923 ;; even when the actual reg to jump to is in CTR, when LR was
10924 ;; saved and restored around the PIC-setting BCL.
10925 (define_insn "*sibcall_local32"
10926 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10927 (match_operand 1 "" "g,g"))
10928 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10929 (use (reg:SI LR_REGNO))
10930 (simple_return)]
10931 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10932 "*
10933 {
10934 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10935 output_asm_insn (\"crxor 6,6,6\", operands);
10937 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10938 output_asm_insn (\"creqv 6,6,6\", operands);
10940 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10941 }"
10942 [(set_attr "type" "branch")
10943 (set_attr "length" "4,8")])
10945 (define_insn "*sibcall_local64"
10946 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10947 (match_operand 1 "" "g,g"))
10948 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10949 (use (reg:SI LR_REGNO))
10950 (simple_return)]
10951 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10952 "*
10953 {
10954 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10955 output_asm_insn (\"crxor 6,6,6\", operands);
10957 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10958 output_asm_insn (\"creqv 6,6,6\", operands);
10960 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10961 }"
10962 [(set_attr "type" "branch")
10963 (set_attr "length" "4,8")])
10965 (define_insn "*sibcall_value_local32"
10966 [(set (match_operand 0 "" "")
10967 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10968 (match_operand 2 "" "g,g")))
10969 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10970 (use (reg:SI LR_REGNO))
10971 (simple_return)]
10972 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10973 "*
10974 {
10975 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10976 output_asm_insn (\"crxor 6,6,6\", operands);
10978 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10979 output_asm_insn (\"creqv 6,6,6\", operands);
10981 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10982 }"
10983 [(set_attr "type" "branch")
10984 (set_attr "length" "4,8")])
10987 (define_insn "*sibcall_value_local64"
10988 [(set (match_operand 0 "" "")
10989 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10990 (match_operand 2 "" "g,g")))
10991 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10992 (use (reg:SI LR_REGNO))
10993 (simple_return)]
10994 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10995 "*
10996 {
10997 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10998 output_asm_insn (\"crxor 6,6,6\", operands);
11000 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11001 output_asm_insn (\"creqv 6,6,6\", operands);
11003 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11004 }"
11005 [(set_attr "type" "branch")
11006 (set_attr "length" "4,8")])
11008 (define_insn "*sibcall_nonlocal_aix<mode>"
11009 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11010 (match_operand 1 "" "g,g"))
11011 (use (match_operand:SI 2 "immediate_operand" "O,O"))
11012 (use (reg:SI LR_REGNO))
11013 (simple_return)]
11014 "DEFAULT_ABI == ABI_AIX
11015 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11016 "@
11017 b %z0
11018 b%T0"
11019 [(set_attr "type" "branch")
11020 (set_attr "length" "4")])
11022 (define_insn "*sibcall_value_nonlocal_aix<mode>"
11023 [(set (match_operand 0 "" "")
11024 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11025 (match_operand 2 "" "g,g")))
11026 (use (match_operand:SI 3 "immediate_operand" "O,O"))
11027 (use (reg:SI LR_REGNO))
11028 (simple_return)]
11029 "DEFAULT_ABI == ABI_AIX
11030 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11031 "@
11032 b %z1
11033 b%T1"
11034 [(set_attr "type" "branch")
11035 (set_attr "length" "4")])
11037 (define_insn "*sibcall_nonlocal_sysv<mode>"
11038 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11039 (match_operand 1 "" ""))
11040 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11041 (use (reg:SI LR_REGNO))
11042 (simple_return)]
11043 "(DEFAULT_ABI == ABI_DARWIN
11044 || DEFAULT_ABI == ABI_V4)
11045 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11046 "*
11047 {
11048 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11049 output_asm_insn (\"crxor 6,6,6\", operands);
11051 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11052 output_asm_insn (\"creqv 6,6,6\", operands);
11054 if (which_alternative >= 2)
11055 return \"b%T0\";
11056 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11057 {
11058 gcc_assert (!TARGET_SECURE_PLT);
11059 return \"b %z0@plt\";
11060 }
11061 else
11062 return \"b %z0\";
11063 }"
11064 [(set_attr "type" "branch")
11065 (set_attr "length" "4,8,4,8")])
11067 (define_expand "sibcall_value"
11068 [(parallel [(set (match_operand 0 "register_operand" "")
11069 (call (mem:SI (match_operand 1 "address_operand" ""))
11070 (match_operand 2 "" "")))
11071 (use (match_operand 3 "" ""))
11072 (use (reg:SI LR_REGNO))
11073 (simple_return)])]
11074 ""
11075 "
11076 {
11077 #if TARGET_MACHO
11078 if (MACHOPIC_INDIRECT)
11079 operands[1] = machopic_indirect_call_target (operands[1]);
11080 #endif
11082 gcc_assert (GET_CODE (operands[1]) == MEM);
11083 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11085 operands[1] = XEXP (operands[1], 0);
11086 }")
11088 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11089 [(set (match_operand 0 "" "")
11090 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11091 (match_operand 2 "" "")))
11092 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11093 (use (reg:SI LR_REGNO))
11094 (simple_return)]
11095 "(DEFAULT_ABI == ABI_DARWIN
11096 || DEFAULT_ABI == ABI_V4)
11097 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11098 "*
11099 {
11100 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11101 output_asm_insn (\"crxor 6,6,6\", operands);
11103 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11104 output_asm_insn (\"creqv 6,6,6\", operands);
11106 if (which_alternative >= 2)
11107 return \"b%T1\";
11108 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11109 {
11110 gcc_assert (!TARGET_SECURE_PLT);
11111 return \"b %z1@plt\";
11112 }
11113 else
11114 return \"b %z1\";
11115 }"
11116 [(set_attr "type" "branch")
11117 (set_attr "length" "4,8,4,8")])
11119 (define_expand "sibcall_epilogue"
11120 [(use (const_int 0))]
11121 ""
11122 {
11123 if (!TARGET_SCHED_PROLOG)
11124 emit_insn (gen_blockage ());
11125 rs6000_emit_epilogue (TRUE);
11126 DONE;
11127 })
11129 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11130 ;; all of memory. This blocks insns from being moved across this point.
11132 (define_insn "blockage"
11133 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11134 ""
11135 "")
11137 (define_insn "probe_stack"
11138 [(set (match_operand 0 "memory_operand" "=m")
11139 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11140 ""
11141 "*
11142 {
11143 operands[1] = gen_rtx_REG (Pmode, 0);
11144 return \"stw%U0%X0 %1,%0\";
11145 }"
11146 [(set_attr "type" "store")
11147 (set_attr "length" "4")])
11149 (define_insn "probe_stack_range<P:mode>"
11150 [(set (match_operand:P 0 "register_operand" "=r")
11151 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11152 (match_operand:P 2 "register_operand" "r")]
11153 UNSPECV_PROBE_STACK_RANGE))]
11154 ""
11155 "* return output_probe_stack_range (operands[0], operands[2]);"
11156 [(set_attr "type" "three")])
11157 \f
11158 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11159 ;; signed & unsigned, and one type of branch.
11160 ;;
11161 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11162 ;; insns, and branches.
11164 (define_expand "cbranch<mode>4"
11165 [(use (match_operator 0 "rs6000_cbranch_operator"
11166 [(match_operand:GPR 1 "gpc_reg_operand" "")
11167 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11168 (use (match_operand 3 ""))]
11169 ""
11170 "
11171 {
11172 /* Take care of the possibility that operands[2] might be negative but
11173 this might be a logical operation. That insn doesn't exist. */
11174 if (GET_CODE (operands[2]) == CONST_INT
11175 && INTVAL (operands[2]) < 0)
11176 {
11177 operands[2] = force_reg (<MODE>mode, operands[2]);
11178 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11179 GET_MODE (operands[0]),
11180 operands[1], operands[2]);
11181 }
11183 rs6000_emit_cbranch (<MODE>mode, operands);
11184 DONE;
11185 }")
11187 (define_expand "cbranch<mode>4"
11188 [(use (match_operator 0 "rs6000_cbranch_operator"
11189 [(match_operand:FP 1 "gpc_reg_operand" "")
11190 (match_operand:FP 2 "gpc_reg_operand" "")]))
11191 (use (match_operand 3 ""))]
11192 ""
11193 "
11194 {
11195 rs6000_emit_cbranch (<MODE>mode, operands);
11196 DONE;
11197 }")
11199 (define_expand "cstore<mode>4"
11200 [(use (match_operator 1 "rs6000_cbranch_operator"
11201 [(match_operand:GPR 2 "gpc_reg_operand" "")
11202 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11203 (clobber (match_operand:SI 0 "register_operand"))]
11204 ""
11205 "
11206 {
11207 /* Take care of the possibility that operands[3] might be negative but
11208 this might be a logical operation. That insn doesn't exist. */
11209 if (GET_CODE (operands[3]) == CONST_INT
11210 && INTVAL (operands[3]) < 0)
11211 {
11212 operands[3] = force_reg (<MODE>mode, operands[3]);
11213 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11214 GET_MODE (operands[1]),
11215 operands[2], operands[3]);
11216 }
11218 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11219 For SEQ, likewise, except that comparisons with zero should be done
11220 with an scc insns. However, due to the order that combine see the
11221 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11222 the cases we don't want to handle or are best handled by portable
11223 code. */
11224 if (GET_CODE (operands[1]) == NE)
11225 FAIL;
11226 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11227 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11228 && operands[3] == const0_rtx)
11229 FAIL;
11230 rs6000_emit_sCOND (<MODE>mode, operands);
11231 DONE;
11232 }")
11234 (define_expand "cstore<mode>4"
11235 [(use (match_operator 1 "rs6000_cbranch_operator"
11236 [(match_operand:FP 2 "gpc_reg_operand" "")
11237 (match_operand:FP 3 "gpc_reg_operand" "")]))
11238 (clobber (match_operand:SI 0 "register_operand"))]
11239 ""
11240 "
11241 {
11242 rs6000_emit_sCOND (<MODE>mode, operands);
11243 DONE;
11244 }")
11247 (define_expand "stack_protect_set"
11248 [(match_operand 0 "memory_operand" "")
11249 (match_operand 1 "memory_operand" "")]
11250 ""
11251 {
11252 #ifdef TARGET_THREAD_SSP_OFFSET
11253 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11254 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11255 operands[1] = gen_rtx_MEM (Pmode, addr);
11256 #endif
11257 if (TARGET_64BIT)
11258 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11259 else
11260 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11261 DONE;
11262 })
11264 (define_insn "stack_protect_setsi"
11265 [(set (match_operand:SI 0 "memory_operand" "=m")
11266 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11267 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11268 "TARGET_32BIT"
11269 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11270 [(set_attr "type" "three")
11271 (set_attr "length" "12")])
11273 (define_insn "stack_protect_setdi"
11274 [(set (match_operand:DI 0 "memory_operand" "=Y")
11275 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11276 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11277 "TARGET_64BIT"
11278 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11279 [(set_attr "type" "three")
11280 (set_attr "length" "12")])
11282 (define_expand "stack_protect_test"
11283 [(match_operand 0 "memory_operand" "")
11284 (match_operand 1 "memory_operand" "")
11285 (match_operand 2 "" "")]
11286 ""
11287 {
11288 rtx test, op0, op1;
11289 #ifdef TARGET_THREAD_SSP_OFFSET
11290 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11291 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11292 operands[1] = gen_rtx_MEM (Pmode, addr);
11293 #endif
11294 op0 = operands[0];
11295 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11296 test = gen_rtx_EQ (VOIDmode, op0, op1);
11297 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11298 DONE;
11299 })
11301 (define_insn "stack_protect_testsi"
11302 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11303 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11304 (match_operand:SI 2 "memory_operand" "m,m")]
11305 UNSPEC_SP_TEST))
11306 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11307 (clobber (match_scratch:SI 3 "=&r,&r"))]
11308 "TARGET_32BIT"
11309 "@
11310 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11311 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11312 [(set_attr "length" "16,20")])
11314 (define_insn "stack_protect_testdi"
11315 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11316 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11317 (match_operand:DI 2 "memory_operand" "Y,Y")]
11318 UNSPEC_SP_TEST))
11319 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11320 (clobber (match_scratch:DI 3 "=&r,&r"))]
11321 "TARGET_64BIT"
11322 "@
11323 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11324 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11325 [(set_attr "length" "16,20")])
11327 \f
11328 ;; Here are the actual compare insns.
11329 (define_insn "*cmp<mode>_internal1"
11330 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11331 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11332 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11333 ""
11334 "cmp<wd>%I2 %0,%1,%2"
11335 [(set_attr "type" "cmp")])
11337 ;; If we are comparing a register for equality with a large constant,
11338 ;; we can do this with an XOR followed by a compare. But this is profitable
11339 ;; only if the large constant is only used for the comparison (and in this
11340 ;; case we already have a register to reuse as scratch).
11341 ;;
11342 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11343 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11345 (define_peephole2
11346 [(set (match_operand:SI 0 "register_operand")
11347 (match_operand:SI 1 "logical_const_operand" ""))
11348 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11349 [(match_dup 0)
11350 (match_operand:SI 2 "logical_const_operand" "")]))
11351 (set (match_operand:CC 4 "cc_reg_operand" "")
11352 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11353 (match_dup 0)))
11354 (set (pc)
11355 (if_then_else (match_operator 6 "equality_operator"
11356 [(match_dup 4) (const_int 0)])
11357 (match_operand 7 "" "")
11358 (match_operand 8 "" "")))]
11359 "peep2_reg_dead_p (3, operands[0])
11360 && peep2_reg_dead_p (4, operands[4])"
11361 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11362 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11363 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11365 {
11366 /* Get the constant we are comparing against, and see what it looks like
11367 when sign-extended from 16 to 32 bits. Then see what constant we could
11368 XOR with SEXTC to get the sign-extended value. */
11369 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11370 SImode,
11371 operands[1], operands[2]);
11372 HOST_WIDE_INT c = INTVAL (cnst);
11373 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11374 HOST_WIDE_INT xorv = c ^ sextc;
11376 operands[9] = GEN_INT (xorv);
11377 operands[10] = GEN_INT (sextc);
11378 })
11380 (define_insn "*cmpsi_internal2"
11381 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11382 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11383 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11384 ""
11385 "cmplw%I2 %0,%1,%b2"
11386 [(set_attr "type" "cmp")])
11388 (define_insn "*cmpdi_internal2"
11389 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11390 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11391 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11392 ""
11393 "cmpld%I2 %0,%1,%b2"
11394 [(set_attr "type" "cmp")])
11396 ;; The following two insns don't exist as single insns, but if we provide
11397 ;; them, we can swap an add and compare, which will enable us to overlap more
11398 ;; of the required delay between a compare and branch. We generate code for
11399 ;; them by splitting.
11401 (define_insn ""
11402 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11403 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11404 (match_operand:SI 2 "short_cint_operand" "i")))
11405 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11406 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11407 ""
11408 "#"
11409 [(set_attr "length" "8")])
11411 (define_insn ""
11412 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11413 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11414 (match_operand:SI 2 "u_short_cint_operand" "i")))
11415 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11416 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11417 ""
11418 "#"
11419 [(set_attr "length" "8")])
11421 (define_split
11422 [(set (match_operand:CC 3 "cc_reg_operand" "")
11423 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11424 (match_operand:SI 2 "short_cint_operand" "")))
11425 (set (match_operand:SI 0 "gpc_reg_operand" "")
11426 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11427 ""
11428 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11429 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11431 (define_split
11432 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11433 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11434 (match_operand:SI 2 "u_short_cint_operand" "")))
11435 (set (match_operand:SI 0 "gpc_reg_operand" "")
11436 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11437 ""
11438 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11439 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11441 (define_insn "*cmpsf_internal1"
11442 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11443 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11444 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11445 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11446 "fcmpu %0,%1,%2"
11447 [(set_attr "type" "fpcompare")])
11449 (define_insn "*cmpdf_internal1"
11450 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11451 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
11452 (match_operand:DF 2 "gpc_reg_operand" "d")))]
11453 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11454 && !VECTOR_UNIT_VSX_P (DFmode)"
11455 "fcmpu %0,%1,%2"
11456 [(set_attr "type" "fpcompare")])
11458 ;; Only need to compare second words if first words equal
11459 (define_insn "*cmptf_internal1"
11460 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11461 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11462 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11463 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11464 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11465 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11466 [(set_attr "type" "fpcompare")
11467 (set_attr "length" "12")])
11469 (define_insn_and_split "*cmptf_internal2"
11470 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11471 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11472 (match_operand:TF 2 "gpc_reg_operand" "d")))
11473 (clobber (match_scratch:DF 3 "=d"))
11474 (clobber (match_scratch:DF 4 "=d"))
11475 (clobber (match_scratch:DF 5 "=d"))
11476 (clobber (match_scratch:DF 6 "=d"))
11477 (clobber (match_scratch:DF 7 "=d"))
11478 (clobber (match_scratch:DF 8 "=d"))
11479 (clobber (match_scratch:DF 9 "=d"))
11480 (clobber (match_scratch:DF 10 "=d"))
11481 (clobber (match_scratch:GPR 11 "=b"))]
11482 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11483 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11484 "#"
11485 "&& reload_completed"
11486 [(set (match_dup 3) (match_dup 14))
11487 (set (match_dup 4) (match_dup 15))
11488 (set (match_dup 9) (abs:DF (match_dup 5)))
11489 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11490 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11491 (label_ref (match_dup 12))
11492 (pc)))
11493 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11494 (set (pc) (label_ref (match_dup 13)))
11495 (match_dup 12)
11496 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11497 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11498 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11499 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11500 (match_dup 13)]
11501 {
11502 REAL_VALUE_TYPE rv;
11503 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11504 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11506 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11507 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11508 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11509 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11510 operands[12] = gen_label_rtx ();
11511 operands[13] = gen_label_rtx ();
11512 real_inf (&rv);
11513 operands[14] = force_const_mem (DFmode,
11514 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11515 operands[15] = force_const_mem (DFmode,
11516 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11517 DFmode));
11518 if (TARGET_TOC)
11519 {
11520 rtx tocref;
11521 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11522 operands[14] = gen_const_mem (DFmode, tocref);
11523 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11524 operands[15] = gen_const_mem (DFmode, tocref);
11525 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11526 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11527 }
11528 })
11529 \f
11530 ;; Now we have the scc insns. We can do some combinations because of the
11531 ;; way the machine works.
11532 ;;
11533 ;; Note that this is probably faster if we can put an insn between the
11534 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11535 ;; cases the insns below which don't use an intermediate CR field will
11536 ;; be used instead.
11537 (define_insn ""
11538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11539 (match_operator:SI 1 "scc_comparison_operator"
11540 [(match_operand 2 "cc_reg_operand" "y")
11541 (const_int 0)]))]
11542 ""
11543 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11544 [(set (attr "type")
11545 (cond [(match_test "TARGET_MFCRF")
11546 (const_string "mfcrf")
11547 ]
11548 (const_string "mfcr")))
11549 (set_attr "length" "8")])
11551 ;; Same as above, but get the GT bit.
11552 (define_insn "move_from_CR_gt_bit"
11553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11554 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11555 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11556 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11557 [(set_attr "type" "mfcr")
11558 (set_attr "length" "8")])
11560 ;; Same as above, but get the OV/ORDERED bit.
11561 (define_insn "move_from_CR_ov_bit"
11562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11563 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11564 "TARGET_ISEL"
11565 "mfcr %0\;rlwinm %0,%0,%t1,1"
11566 [(set_attr "type" "mfcr")
11567 (set_attr "length" "8")])
11569 (define_insn ""
11570 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11571 (match_operator:DI 1 "scc_comparison_operator"
11572 [(match_operand 2 "cc_reg_operand" "y")
11573 (const_int 0)]))]
11574 "TARGET_POWERPC64"
11575 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11576 [(set (attr "type")
11577 (cond [(match_test "TARGET_MFCRF")
11578 (const_string "mfcrf")
11579 ]
11580 (const_string "mfcr")))
11581 (set_attr "length" "8")])
11583 (define_insn ""
11584 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11585 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11586 [(match_operand 2 "cc_reg_operand" "y,y")
11587 (const_int 0)])
11588 (const_int 0)))
11589 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11590 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11591 "TARGET_32BIT"
11592 "@
11593 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11594 #"
11595 [(set_attr "type" "delayed_compare")
11596 (set_attr "length" "8,16")])
11598 (define_split
11599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11600 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11601 [(match_operand 2 "cc_reg_operand" "")
11602 (const_int 0)])
11603 (const_int 0)))
11604 (set (match_operand:SI 3 "gpc_reg_operand" "")
11605 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11606 "TARGET_32BIT && reload_completed"
11607 [(set (match_dup 3)
11608 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11609 (set (match_dup 0)
11610 (compare:CC (match_dup 3)
11611 (const_int 0)))]
11612 "")
11614 (define_insn ""
11615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11616 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11617 [(match_operand 2 "cc_reg_operand" "y")
11618 (const_int 0)])
11619 (match_operand:SI 3 "const_int_operand" "n")))]
11620 ""
11621 "*
11622 {
11623 int is_bit = ccr_bit (operands[1], 1);
11624 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11625 int count;
11627 if (is_bit >= put_bit)
11628 count = is_bit - put_bit;
11629 else
11630 count = 32 - (put_bit - is_bit);
11632 operands[4] = GEN_INT (count);
11633 operands[5] = GEN_INT (put_bit);
11635 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11636 }"
11637 [(set (attr "type")
11638 (cond [(match_test "TARGET_MFCRF")
11639 (const_string "mfcrf")
11640 ]
11641 (const_string "mfcr")))
11642 (set_attr "length" "8")])
11644 (define_insn ""
11645 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11646 (compare:CC
11647 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11648 [(match_operand 2 "cc_reg_operand" "y,y")
11649 (const_int 0)])
11650 (match_operand:SI 3 "const_int_operand" "n,n"))
11651 (const_int 0)))
11652 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11653 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11654 (match_dup 3)))]
11655 ""
11656 "*
11657 {
11658 int is_bit = ccr_bit (operands[1], 1);
11659 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11660 int count;
11662 /* Force split for non-cc0 compare. */
11663 if (which_alternative == 1)
11664 return \"#\";
11666 if (is_bit >= put_bit)
11667 count = is_bit - put_bit;
11668 else
11669 count = 32 - (put_bit - is_bit);
11671 operands[5] = GEN_INT (count);
11672 operands[6] = GEN_INT (put_bit);
11674 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11675 }"
11676 [(set_attr "type" "delayed_compare")
11677 (set_attr "length" "8,16")])
11679 (define_split
11680 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11681 (compare:CC
11682 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11683 [(match_operand 2 "cc_reg_operand" "")
11684 (const_int 0)])
11685 (match_operand:SI 3 "const_int_operand" ""))
11686 (const_int 0)))
11687 (set (match_operand:SI 4 "gpc_reg_operand" "")
11688 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11689 (match_dup 3)))]
11690 "reload_completed"
11691 [(set (match_dup 4)
11692 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11693 (match_dup 3)))
11694 (set (match_dup 0)
11695 (compare:CC (match_dup 4)
11696 (const_int 0)))]
11697 "")
11699 ;; There is a 3 cycle delay between consecutive mfcr instructions
11700 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11702 (define_peephole
11703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11704 (match_operator:SI 1 "scc_comparison_operator"
11705 [(match_operand 2 "cc_reg_operand" "y")
11706 (const_int 0)]))
11707 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11708 (match_operator:SI 4 "scc_comparison_operator"
11709 [(match_operand 5 "cc_reg_operand" "y")
11710 (const_int 0)]))]
11711 "REGNO (operands[2]) != REGNO (operands[5])"
11712 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11713 [(set_attr "type" "mfcr")
11714 (set_attr "length" "12")])
11716 (define_peephole
11717 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11718 (match_operator:DI 1 "scc_comparison_operator"
11719 [(match_operand 2 "cc_reg_operand" "y")
11720 (const_int 0)]))
11721 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11722 (match_operator:DI 4 "scc_comparison_operator"
11723 [(match_operand 5 "cc_reg_operand" "y")
11724 (const_int 0)]))]
11725 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11726 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11727 [(set_attr "type" "mfcr")
11728 (set_attr "length" "12")])
11730 ;; There are some scc insns that can be done directly, without a compare.
11731 ;; These are faster because they don't involve the communications between
11732 ;; the FXU and branch units. In fact, we will be replacing all of the
11733 ;; integer scc insns here or in the portable methods in emit_store_flag.
11734 ;;
11735 ;; Also support (neg (scc ..)) since that construct is used to replace
11736 ;; branches, (plus (scc ..) ..) since that construct is common and
11737 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11738 ;; cases where it is no more expensive than (neg (scc ..)).
11740 ;; Have reload force a constant into a register for the simple insns that
11741 ;; otherwise won't accept constants. We do this because it is faster than
11742 ;; the cmp/mfcr sequence we would otherwise generate.
11744 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11745 (DI "rKJI")])
11747 (define_insn_and_split "*eq<mode>"
11748 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11749 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11750 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11751 ""
11752 "#"
11753 ""
11754 [(set (match_dup 0)
11755 (clz:GPR (match_dup 3)))
11756 (set (match_dup 0)
11757 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11758 {
11759 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11760 {
11761 /* Use output operand as intermediate. */
11762 operands[3] = operands[0];
11764 if (logical_operand (operands[2], <MODE>mode))
11765 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11766 gen_rtx_XOR (<MODE>mode,
11767 operands[1], operands[2])));
11768 else
11769 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11770 gen_rtx_PLUS (<MODE>mode, operands[1],
11771 negate_rtx (<MODE>mode,
11772 operands[2]))));
11773 }
11774 else
11775 operands[3] = operands[1];
11777 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11778 })
11780 (define_insn_and_split "*eq<mode>_compare"
11781 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11782 (compare:CC
11783 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11784 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11785 (const_int 0)))
11786 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11787 (eq:P (match_dup 1) (match_dup 2)))]
11788 "optimize_size"
11789 "#"
11790 "optimize_size"
11791 [(set (match_dup 0)
11792 (clz:P (match_dup 4)))
11793 (parallel [(set (match_dup 3)
11794 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11795 (const_int 0)))
11796 (set (match_dup 0)
11797 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11798 {
11799 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11800 {
11801 /* Use output operand as intermediate. */
11802 operands[4] = operands[0];
11804 if (logical_operand (operands[2], <MODE>mode))
11805 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11806 gen_rtx_XOR (<MODE>mode,
11807 operands[1], operands[2])));
11808 else
11809 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11810 gen_rtx_PLUS (<MODE>mode, operands[1],
11811 negate_rtx (<MODE>mode,
11812 operands[2]))));
11813 }
11814 else
11815 operands[4] = operands[1];
11817 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11818 })
11820 ;; We have insns of the form shown by the first define_insn below. If
11821 ;; there is something inside the comparison operation, we must split it.
11822 (define_split
11823 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11824 (plus:SI (match_operator 1 "comparison_operator"
11825 [(match_operand:SI 2 "" "")
11826 (match_operand:SI 3
11827 "reg_or_cint_operand" "")])
11828 (match_operand:SI 4 "gpc_reg_operand" "")))
11829 (clobber (match_operand:SI 5 "register_operand" ""))]
11830 "! gpc_reg_operand (operands[2], SImode)"
11831 [(set (match_dup 5) (match_dup 2))
11832 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
11833 (match_dup 4)))])
11835 (define_insn "*plus_eqsi"
11836 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11837 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11838 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11839 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11840 "TARGET_32BIT"
11841 "@
11842 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
11843 subfic %0,%1,0\;addze %0,%3
11844 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
11845 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
11846 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
11847 [(set_attr "type" "three,two,three,three,three")
11848 (set_attr "length" "12,8,12,12,12")])
11850 (define_insn "*compare_plus_eqsi"
11851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11852 (compare:CC
11853 (plus:SI
11854 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11855 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11856 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11857 (const_int 0)))
11858 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11859 "TARGET_32BIT && optimize_size"
11860 "@
11861 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11862 subfic %4,%1,0\;addze. %4,%3
11863 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
11864 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
11865 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11866 #
11867 #
11868 #
11869 #
11870 #"
11871 [(set_attr "type" "compare")
11872 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11874 (define_split
11875 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11876 (compare:CC
11877 (plus:SI
11878 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11879 (match_operand:SI 2 "scc_eq_operand" ""))
11880 (match_operand:SI 3 "gpc_reg_operand" ""))
11881 (const_int 0)))
11882 (clobber (match_scratch:SI 4 ""))]
11883 "TARGET_32BIT && optimize_size && reload_completed"
11884 [(set (match_dup 4)
11885 (plus:SI (eq:SI (match_dup 1)
11886 (match_dup 2))
11887 (match_dup 3)))
11888 (set (match_dup 0)
11889 (compare:CC (match_dup 4)
11890 (const_int 0)))]
11891 "")
11893 (define_insn "*plus_eqsi_compare"
11894 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11895 (compare:CC
11896 (plus:SI
11897 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11898 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11899 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11900 (const_int 0)))
11901 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11902 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11903 "TARGET_32BIT && optimize_size"
11904 "@
11905 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11906 subfic %0,%1,0\;addze. %0,%3
11907 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
11908 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
11909 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11910 #
11911 #
11912 #
11913 #
11914 #"
11915 [(set_attr "type" "compare")
11916 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11918 (define_split
11919 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11920 (compare:CC
11921 (plus:SI
11922 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11923 (match_operand:SI 2 "scc_eq_operand" ""))
11924 (match_operand:SI 3 "gpc_reg_operand" ""))
11925 (const_int 0)))
11926 (set (match_operand:SI 0 "gpc_reg_operand" "")
11927 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11928 "TARGET_32BIT && optimize_size && reload_completed"
11929 [(set (match_dup 0)
11930 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11931 (set (match_dup 4)
11932 (compare:CC (match_dup 0)
11933 (const_int 0)))]
11934 "")
11936 (define_insn "*neg_eq0<mode>"
11937 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11938 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11939 (const_int 0))))]
11940 ""
11941 "addic %0,%1,-1\;subfe %0,%0,%0"
11942 [(set_attr "type" "two")
11943 (set_attr "length" "8")])
11945 (define_insn_and_split "*neg_eq<mode>"
11946 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11947 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11948 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11949 ""
11950 "#"
11951 ""
11952 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11953 {
11954 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11955 {
11956 /* Use output operand as intermediate. */
11957 operands[3] = operands[0];
11959 if (logical_operand (operands[2], <MODE>mode))
11960 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11961 gen_rtx_XOR (<MODE>mode,
11962 operands[1], operands[2])));
11963 else
11964 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11965 gen_rtx_PLUS (<MODE>mode, operands[1],
11966 negate_rtx (<MODE>mode,
11967 operands[2]))));
11968 }
11969 else
11970 operands[3] = operands[1];
11971 })
11973 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11974 ;; since it nabs/sr is just as fast.
11975 (define_insn "*ne0si"
11976 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11977 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11978 (const_int 31)))
11979 (clobber (match_scratch:SI 2 "=&r"))]
11980 "TARGET_32BIT && !TARGET_ISEL"
11981 "addic %2,%1,-1\;subfe %0,%2,%1"
11982 [(set_attr "type" "two")
11983 (set_attr "length" "8")])
11985 (define_insn "*ne0di"
11986 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11987 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11988 (const_int 63)))
11989 (clobber (match_scratch:DI 2 "=&r"))]
11990 "TARGET_64BIT"
11991 "addic %2,%1,-1\;subfe %0,%2,%1"
11992 [(set_attr "type" "two")
11993 (set_attr "length" "8")])
11995 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11996 (define_insn "*plus_ne0si"
11997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11998 (plus:SI (lshiftrt:SI
11999 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12000 (const_int 31))
12001 (match_operand:SI 2 "gpc_reg_operand" "r")))
12002 (clobber (match_scratch:SI 3 "=&r"))]
12003 "TARGET_32BIT"
12004 "addic %3,%1,-1\;addze %0,%2"
12005 [(set_attr "type" "two")
12006 (set_attr "length" "8")])
12008 (define_insn "*plus_ne0di"
12009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12010 (plus:DI (lshiftrt:DI
12011 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12012 (const_int 63))
12013 (match_operand:DI 2 "gpc_reg_operand" "r")))
12014 (clobber (match_scratch:DI 3 "=&r"))]
12015 "TARGET_64BIT"
12016 "addic %3,%1,-1\;addze %0,%2"
12017 [(set_attr "type" "two")
12018 (set_attr "length" "8")])
12020 (define_insn "*compare_plus_ne0si"
12021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12022 (compare:CC
12023 (plus:SI (lshiftrt:SI
12024 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12025 (const_int 31))
12026 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12027 (const_int 0)))
12028 (clobber (match_scratch:SI 3 "=&r,&r"))
12029 (clobber (match_scratch:SI 4 "=X,&r"))]
12030 "TARGET_32BIT"
12031 "@
12032 addic %3,%1,-1\;addze. %3,%2
12033 #"
12034 [(set_attr "type" "compare")
12035 (set_attr "length" "8,12")])
12037 (define_split
12038 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12039 (compare:CC
12040 (plus:SI (lshiftrt:SI
12041 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12042 (const_int 31))
12043 (match_operand:SI 2 "gpc_reg_operand" ""))
12044 (const_int 0)))
12045 (clobber (match_scratch:SI 3 ""))
12046 (clobber (match_scratch:SI 4 ""))]
12047 "TARGET_32BIT && reload_completed"
12048 [(parallel [(set (match_dup 3)
12049 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12050 (const_int 31))
12051 (match_dup 2)))
12052 (clobber (match_dup 4))])
12053 (set (match_dup 0)
12054 (compare:CC (match_dup 3)
12055 (const_int 0)))]
12056 "")
12058 (define_insn "*compare_plus_ne0di"
12059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12060 (compare:CC
12061 (plus:DI (lshiftrt:DI
12062 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12063 (const_int 63))
12064 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12065 (const_int 0)))
12066 (clobber (match_scratch:DI 3 "=&r,&r"))]
12067 "TARGET_64BIT"
12068 "@
12069 addic %3,%1,-1\;addze. %3,%2
12070 #"
12071 [(set_attr "type" "compare")
12072 (set_attr "length" "8,12")])
12074 (define_split
12075 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12076 (compare:CC
12077 (plus:DI (lshiftrt:DI
12078 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12079 (const_int 63))
12080 (match_operand:DI 2 "gpc_reg_operand" ""))
12081 (const_int 0)))
12082 (clobber (match_scratch:DI 3 ""))]
12083 "TARGET_64BIT && reload_completed"
12084 [(set (match_dup 3)
12085 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12086 (const_int 63))
12087 (match_dup 2)))
12088 (set (match_dup 0)
12089 (compare:CC (match_dup 3)
12090 (const_int 0)))]
12091 "")
12093 (define_insn "*plus_ne0si_compare"
12094 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12095 (compare:CC
12096 (plus:SI (lshiftrt:SI
12097 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12098 (const_int 31))
12099 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12100 (const_int 0)))
12101 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12102 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12103 (match_dup 2)))
12104 (clobber (match_scratch:SI 3 "=&r,&r"))]
12105 "TARGET_32BIT"
12106 "@
12107 addic %3,%1,-1\;addze. %0,%2
12108 #"
12109 [(set_attr "type" "compare")
12110 (set_attr "length" "8,12")])
12112 (define_split
12113 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12114 (compare:CC
12115 (plus:SI (lshiftrt:SI
12116 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12117 (const_int 31))
12118 (match_operand:SI 2 "gpc_reg_operand" ""))
12119 (const_int 0)))
12120 (set (match_operand:SI 0 "gpc_reg_operand" "")
12121 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12122 (match_dup 2)))
12123 (clobber (match_scratch:SI 3 ""))]
12124 "TARGET_32BIT && reload_completed"
12125 [(parallel [(set (match_dup 0)
12126 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12127 (match_dup 2)))
12128 (clobber (match_dup 3))])
12129 (set (match_dup 4)
12130 (compare:CC (match_dup 0)
12131 (const_int 0)))]
12132 "")
12134 (define_insn "*plus_ne0di_compare"
12135 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12136 (compare:CC
12137 (plus:DI (lshiftrt:DI
12138 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12139 (const_int 63))
12140 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12141 (const_int 0)))
12142 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12143 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12144 (match_dup 2)))
12145 (clobber (match_scratch:DI 3 "=&r,&r"))]
12146 "TARGET_64BIT"
12147 "@
12148 addic %3,%1,-1\;addze. %0,%2
12149 #"
12150 [(set_attr "type" "compare")
12151 (set_attr "length" "8,12")])
12153 (define_split
12154 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12155 (compare:CC
12156 (plus:DI (lshiftrt:DI
12157 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12158 (const_int 63))
12159 (match_operand:DI 2 "gpc_reg_operand" ""))
12160 (const_int 0)))
12161 (set (match_operand:DI 0 "gpc_reg_operand" "")
12162 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12163 (match_dup 2)))
12164 (clobber (match_scratch:DI 3 ""))]
12165 "TARGET_64BIT && reload_completed"
12166 [(parallel [(set (match_dup 0)
12167 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12168 (match_dup 2)))
12169 (clobber (match_dup 3))])
12170 (set (match_dup 4)
12171 (compare:CC (match_dup 0)
12172 (const_int 0)))]
12173 "")
12175 (define_insn "*leu<mode>"
12176 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12177 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12178 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12179 ""
12180 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12181 [(set_attr "type" "three")
12182 (set_attr "length" "12")])
12184 (define_insn "*leu<mode>_compare"
12185 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12186 (compare:CC
12187 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12188 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12189 (const_int 0)))
12190 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12191 (leu:P (match_dup 1) (match_dup 2)))]
12192 ""
12193 "@
12194 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12195 #"
12196 [(set_attr "type" "compare")
12197 (set_attr "length" "12,16")])
12199 (define_split
12200 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12201 (compare:CC
12202 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12203 (match_operand:P 2 "reg_or_short_operand" ""))
12204 (const_int 0)))
12205 (set (match_operand:P 0 "gpc_reg_operand" "")
12206 (leu:P (match_dup 1) (match_dup 2)))]
12207 "reload_completed"
12208 [(set (match_dup 0)
12209 (leu:P (match_dup 1) (match_dup 2)))
12210 (set (match_dup 3)
12211 (compare:CC (match_dup 0)
12212 (const_int 0)))]
12213 "")
12215 (define_insn "*plus_leu<mode>"
12216 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12217 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12218 (match_operand:P 2 "reg_or_short_operand" "rI"))
12219 (match_operand:P 3 "gpc_reg_operand" "r")))]
12220 ""
12221 "subf%I2c %0,%1,%2\;addze %0,%3"
12222 [(set_attr "type" "two")
12223 (set_attr "length" "8")])
12225 (define_insn ""
12226 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12227 (compare:CC
12228 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12229 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12230 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12231 (const_int 0)))
12232 (clobber (match_scratch:SI 4 "=&r,&r"))]
12233 "TARGET_32BIT"
12234 "@
12235 subf%I2c %4,%1,%2\;addze. %4,%3
12236 #"
12237 [(set_attr "type" "compare")
12238 (set_attr "length" "8,12")])
12240 (define_split
12241 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12242 (compare:CC
12243 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12244 (match_operand:SI 2 "reg_or_short_operand" ""))
12245 (match_operand:SI 3 "gpc_reg_operand" ""))
12246 (const_int 0)))
12247 (clobber (match_scratch:SI 4 ""))]
12248 "TARGET_32BIT && reload_completed"
12249 [(set (match_dup 4)
12250 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12251 (match_dup 3)))
12252 (set (match_dup 0)
12253 (compare:CC (match_dup 4)
12254 (const_int 0)))]
12255 "")
12257 (define_insn ""
12258 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12259 (compare:CC
12260 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12261 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12262 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12263 (const_int 0)))
12264 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12265 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12266 "TARGET_32BIT"
12267 "@
12268 subf%I2c %0,%1,%2\;addze. %0,%3
12269 #"
12270 [(set_attr "type" "compare")
12271 (set_attr "length" "8,12")])
12273 (define_split
12274 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12275 (compare:CC
12276 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12277 (match_operand:SI 2 "reg_or_short_operand" ""))
12278 (match_operand:SI 3 "gpc_reg_operand" ""))
12279 (const_int 0)))
12280 (set (match_operand:SI 0 "gpc_reg_operand" "")
12281 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12282 "TARGET_32BIT && reload_completed"
12283 [(set (match_dup 0)
12284 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12285 (set (match_dup 4)
12286 (compare:CC (match_dup 0)
12287 (const_int 0)))]
12288 "")
12290 (define_insn "*neg_leu<mode>"
12291 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12292 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12293 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12294 ""
12295 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12296 [(set_attr "type" "three")
12297 (set_attr "length" "12")])
12299 (define_insn "*and_neg_leu<mode>"
12300 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12301 (and:P (neg:P
12302 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12303 (match_operand:P 2 "reg_or_short_operand" "rI")))
12304 (match_operand:P 3 "gpc_reg_operand" "r")))]
12305 ""
12306 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12307 [(set_attr "type" "three")
12308 (set_attr "length" "12")])
12310 (define_insn ""
12311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12312 (compare:CC
12313 (and:SI (neg:SI
12314 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12315 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12316 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12317 (const_int 0)))
12318 (clobber (match_scratch:SI 4 "=&r,&r"))]
12319 "TARGET_32BIT"
12320 "@
12321 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12322 #"
12323 [(set_attr "type" "compare")
12324 (set_attr "length" "12,16")])
12326 (define_split
12327 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12328 (compare:CC
12329 (and:SI (neg:SI
12330 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12331 (match_operand:SI 2 "reg_or_short_operand" "")))
12332 (match_operand:SI 3 "gpc_reg_operand" ""))
12333 (const_int 0)))
12334 (clobber (match_scratch:SI 4 ""))]
12335 "TARGET_32BIT && reload_completed"
12336 [(set (match_dup 4)
12337 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12338 (match_dup 3)))
12339 (set (match_dup 0)
12340 (compare:CC (match_dup 4)
12341 (const_int 0)))]
12342 "")
12344 (define_insn ""
12345 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12346 (compare:CC
12347 (and:SI (neg:SI
12348 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12349 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12350 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12351 (const_int 0)))
12352 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12353 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12354 "TARGET_32BIT"
12355 "@
12356 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12357 #"
12358 [(set_attr "type" "compare")
12359 (set_attr "length" "12,16")])
12361 (define_split
12362 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12363 (compare:CC
12364 (and:SI (neg:SI
12365 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12366 (match_operand:SI 2 "reg_or_short_operand" "")))
12367 (match_operand:SI 3 "gpc_reg_operand" ""))
12368 (const_int 0)))
12369 (set (match_operand:SI 0 "gpc_reg_operand" "")
12370 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12371 "TARGET_32BIT && reload_completed"
12372 [(set (match_dup 0)
12373 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12374 (match_dup 3)))
12375 (set (match_dup 4)
12376 (compare:CC (match_dup 0)
12377 (const_int 0)))]
12378 "")
12380 (define_insn_and_split "*ltu<mode>"
12381 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12382 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12383 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12384 ""
12385 "#"
12386 ""
12387 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12388 (set (match_dup 0) (neg:P (match_dup 0)))]
12389 "")
12391 (define_insn_and_split "*ltu<mode>_compare"
12392 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12393 (compare:CC
12394 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12395 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12396 (const_int 0)))
12397 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12398 (ltu:P (match_dup 1) (match_dup 2)))]
12399 ""
12400 "#"
12401 ""
12402 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12403 (parallel [(set (match_dup 3)
12404 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12405 (set (match_dup 0) (neg:P (match_dup 0)))])]
12406 "")
12408 (define_insn_and_split "*plus_ltu<mode>"
12409 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12410 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12411 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12412 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12413 ""
12414 "#"
12415 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12416 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12417 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12418 "")
12420 (define_insn_and_split "*plus_ltu<mode>_compare"
12421 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12422 (compare:CC
12423 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12424 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12425 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12426 (const_int 0)))
12427 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12428 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12429 ""
12430 "#"
12431 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12432 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12433 (parallel [(set (match_dup 4)
12434 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12435 (const_int 0)))
12436 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12437 "")
12439 (define_insn "*neg_ltu<mode>"
12440 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12441 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12442 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12443 ""
12444 "@
12445 subfc %0,%2,%1\;subfe %0,%0,%0
12446 addic %0,%1,%n2\;subfe %0,%0,%0"
12447 [(set_attr "type" "two")
12448 (set_attr "length" "8")])
12450 (define_insn "*geu<mode>"
12451 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12452 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12453 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12454 ""
12455 "@
12456 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12457 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12458 [(set_attr "type" "three")
12459 (set_attr "length" "12")])
12461 (define_insn "*geu<mode>_compare"
12462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12463 (compare:CC
12464 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12465 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12466 (const_int 0)))
12467 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12468 (geu:P (match_dup 1) (match_dup 2)))]
12469 ""
12470 "@
12471 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12472 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12473 #
12474 #"
12475 [(set_attr "type" "compare")
12476 (set_attr "length" "12,12,16,16")])
12478 (define_split
12479 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12480 (compare:CC
12481 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12482 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12483 (const_int 0)))
12484 (set (match_operand:P 0 "gpc_reg_operand" "")
12485 (geu:P (match_dup 1) (match_dup 2)))]
12486 "reload_completed"
12487 [(set (match_dup 0)
12488 (geu:P (match_dup 1) (match_dup 2)))
12489 (set (match_dup 3)
12490 (compare:CC (match_dup 0)
12491 (const_int 0)))]
12492 "")
12494 (define_insn "*plus_geu<mode>"
12495 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12496 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12497 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12498 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12499 ""
12500 "@
12501 subfc %0,%2,%1\;addze %0,%3
12502 addic %0,%1,%n2\;addze %0,%3"
12503 [(set_attr "type" "two")
12504 (set_attr "length" "8")])
12506 (define_insn ""
12507 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12508 (compare:CC
12509 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12510 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12511 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12512 (const_int 0)))
12513 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12514 "TARGET_32BIT"
12515 "@
12516 subfc %4,%2,%1\;addze. %4,%3
12517 addic %4,%1,%n2\;addze. %4,%3
12518 #
12519 #"
12520 [(set_attr "type" "compare")
12521 (set_attr "length" "8,8,12,12")])
12523 (define_split
12524 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12525 (compare:CC
12526 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12527 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12528 (match_operand:SI 3 "gpc_reg_operand" ""))
12529 (const_int 0)))
12530 (clobber (match_scratch:SI 4 ""))]
12531 "TARGET_32BIT && reload_completed"
12532 [(set (match_dup 4)
12533 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12534 (match_dup 3)))
12535 (set (match_dup 0)
12536 (compare:CC (match_dup 4)
12537 (const_int 0)))]
12538 "")
12540 (define_insn ""
12541 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12542 (compare:CC
12543 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12544 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12545 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12546 (const_int 0)))
12547 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12548 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12549 "TARGET_32BIT"
12550 "@
12551 subfc %0,%2,%1\;addze. %0,%3
12552 addic %0,%1,%n2\;addze. %0,%3
12553 #
12554 #"
12555 [(set_attr "type" "compare")
12556 (set_attr "length" "8,8,12,12")])
12558 (define_split
12559 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12560 (compare:CC
12561 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12562 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12563 (match_operand:SI 3 "gpc_reg_operand" ""))
12564 (const_int 0)))
12565 (set (match_operand:SI 0 "gpc_reg_operand" "")
12566 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12567 "TARGET_32BIT && reload_completed"
12568 [(set (match_dup 0)
12569 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12570 (set (match_dup 4)
12571 (compare:CC (match_dup 0)
12572 (const_int 0)))]
12573 "")
12575 (define_insn "*neg_geu<mode>"
12576 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12577 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12578 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12579 ""
12580 "@
12581 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12582 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12583 [(set_attr "type" "three")
12584 (set_attr "length" "12")])
12586 (define_insn "*and_neg_geu<mode>"
12587 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12588 (and:P (neg:P
12589 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12590 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12591 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12592 ""
12593 "@
12594 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12595 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12596 [(set_attr "type" "three")
12597 (set_attr "length" "12")])
12599 (define_insn ""
12600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12601 (compare:CC
12602 (and:SI (neg:SI
12603 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12604 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12605 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12606 (const_int 0)))
12607 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12608 "TARGET_32BIT"
12609 "@
12610 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12611 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12612 #
12613 #"
12614 [(set_attr "type" "compare")
12615 (set_attr "length" "12,12,16,16")])
12617 (define_split
12618 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12619 (compare:CC
12620 (and:SI (neg:SI
12621 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12622 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12623 (match_operand:SI 3 "gpc_reg_operand" ""))
12624 (const_int 0)))
12625 (clobber (match_scratch:SI 4 ""))]
12626 "TARGET_32BIT && reload_completed"
12627 [(set (match_dup 4)
12628 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12629 (match_dup 3)))
12630 (set (match_dup 0)
12631 (compare:CC (match_dup 4)
12632 (const_int 0)))]
12633 "")
12635 (define_insn ""
12636 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12637 (compare:CC
12638 (and:SI (neg:SI
12639 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12640 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12641 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12642 (const_int 0)))
12643 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12644 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12645 "TARGET_32BIT"
12646 "@
12647 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12648 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12649 #
12650 #"
12651 [(set_attr "type" "compare")
12652 (set_attr "length" "12,12,16,16")])
12654 (define_split
12655 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12656 (compare:CC
12657 (and:SI (neg:SI
12658 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12659 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12660 (match_operand:SI 3 "gpc_reg_operand" ""))
12661 (const_int 0)))
12662 (set (match_operand:SI 0 "gpc_reg_operand" "")
12663 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12664 "TARGET_32BIT && reload_completed"
12665 [(set (match_dup 0)
12666 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12667 (set (match_dup 4)
12668 (compare:CC (match_dup 0)
12669 (const_int 0)))]
12670 "")
12672 (define_insn "*plus_gt0<mode>"
12673 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12674 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12675 (const_int 0))
12676 (match_operand:P 2 "gpc_reg_operand" "r")))]
12677 ""
12678 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12679 [(set_attr "type" "three")
12680 (set_attr "length" "12")])
12682 (define_insn ""
12683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12684 (compare:CC
12685 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12686 (const_int 0))
12687 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12688 (const_int 0)))
12689 (clobber (match_scratch:SI 3 "=&r,&r"))]
12690 "TARGET_32BIT"
12691 "@
12692 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12693 #"
12694 [(set_attr "type" "compare")
12695 (set_attr "length" "12,16")])
12697 (define_split
12698 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12699 (compare:CC
12700 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12701 (const_int 0))
12702 (match_operand:SI 2 "gpc_reg_operand" ""))
12703 (const_int 0)))
12704 (clobber (match_scratch:SI 3 ""))]
12705 "TARGET_32BIT && reload_completed"
12706 [(set (match_dup 3)
12707 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12708 (match_dup 2)))
12709 (set (match_dup 0)
12710 (compare:CC (match_dup 3)
12711 (const_int 0)))]
12712 "")
12714 (define_insn ""
12715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12716 (compare:CC
12717 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12718 (const_int 0))
12719 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12720 (const_int 0)))
12721 (clobber (match_scratch:DI 3 "=&r,&r"))]
12722 "TARGET_64BIT"
12723 "@
12724 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12725 #"
12726 [(set_attr "type" "compare")
12727 (set_attr "length" "12,16")])
12729 (define_split
12730 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12731 (compare:CC
12732 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12733 (const_int 0))
12734 (match_operand:DI 2 "gpc_reg_operand" ""))
12735 (const_int 0)))
12736 (clobber (match_scratch:DI 3 ""))]
12737 "TARGET_64BIT && reload_completed"
12738 [(set (match_dup 3)
12739 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12740 (match_dup 2)))
12741 (set (match_dup 0)
12742 (compare:CC (match_dup 3)
12743 (const_int 0)))]
12744 "")
12746 (define_insn ""
12747 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12748 (compare:CC
12749 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12750 (const_int 0))
12751 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12752 (const_int 0)))
12753 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12754 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12755 "TARGET_32BIT"
12756 "@
12757 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12758 #"
12759 [(set_attr "type" "compare")
12760 (set_attr "length" "12,16")])
12762 (define_split
12763 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12764 (compare:CC
12765 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12766 (const_int 0))
12767 (match_operand:SI 2 "gpc_reg_operand" ""))
12768 (const_int 0)))
12769 (set (match_operand:SI 0 "gpc_reg_operand" "")
12770 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12771 "TARGET_32BIT && reload_completed"
12772 [(set (match_dup 0)
12773 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12774 (set (match_dup 3)
12775 (compare:CC (match_dup 0)
12776 (const_int 0)))]
12777 "")
12779 (define_insn ""
12780 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12781 (compare:CC
12782 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12783 (const_int 0))
12784 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12785 (const_int 0)))
12786 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12787 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12788 "TARGET_64BIT"
12789 "@
12790 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12791 #"
12792 [(set_attr "type" "compare")
12793 (set_attr "length" "12,16")])
12795 (define_split
12796 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12797 (compare:CC
12798 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12799 (const_int 0))
12800 (match_operand:DI 2 "gpc_reg_operand" ""))
12801 (const_int 0)))
12802 (set (match_operand:DI 0 "gpc_reg_operand" "")
12803 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12804 "TARGET_64BIT && reload_completed"
12805 [(set (match_dup 0)
12806 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12807 (set (match_dup 3)
12808 (compare:CC (match_dup 0)
12809 (const_int 0)))]
12810 "")
12812 (define_insn_and_split "*gtu<mode>"
12813 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12814 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12815 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12816 ""
12817 "#"
12818 ""
12819 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12820 (set (match_dup 0) (neg:P (match_dup 0)))]
12821 "")
12823 (define_insn_and_split "*gtu<mode>_compare"
12824 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12825 (compare:CC
12826 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12827 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12828 (const_int 0)))
12829 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12830 (gtu:P (match_dup 1) (match_dup 2)))]
12831 ""
12832 "#"
12833 ""
12834 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12835 (parallel [(set (match_dup 3)
12836 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12837 (set (match_dup 0) (neg:P (match_dup 0)))])]
12838 "")
12840 (define_insn_and_split "*plus_gtu<mode>"
12841 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12842 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12843 (match_operand:P 2 "reg_or_short_operand" "rI"))
12844 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12845 ""
12846 "#"
12847 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12848 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12849 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12850 "")
12852 (define_insn_and_split "*plus_gtu<mode>_compare"
12853 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12854 (compare:CC
12855 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12856 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12857 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12858 (const_int 0)))
12859 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12860 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12861 ""
12862 "#"
12863 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12864 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12865 (parallel [(set (match_dup 4)
12866 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12867 (const_int 0)))
12868 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12869 "")
12871 (define_insn "*neg_gtu<mode>"
12872 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12873 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12874 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12875 ""
12876 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12877 [(set_attr "type" "two")
12878 (set_attr "length" "8")])
12880 \f
12881 ;; Define both directions of branch and return. If we need a reload
12882 ;; register, we'd rather use CR0 since it is much easier to copy a
12883 ;; register CC value to there.
12885 (define_insn ""
12886 [(set (pc)
12887 (if_then_else (match_operator 1 "branch_comparison_operator"
12888 [(match_operand 2
12889 "cc_reg_operand" "y")
12890 (const_int 0)])
12891 (label_ref (match_operand 0 "" ""))
12892 (pc)))]
12893 ""
12894 "*
12895 {
12896 return output_cbranch (operands[1], \"%l0\", 0, insn);
12897 }"
12898 [(set_attr "type" "branch")])
12900 (define_insn ""
12901 [(set (pc)
12902 (if_then_else (match_operator 0 "branch_comparison_operator"
12903 [(match_operand 1
12904 "cc_reg_operand" "y")
12905 (const_int 0)])
12906 (any_return)
12907 (pc)))]
12908 "<return_pred>"
12909 "*
12910 {
12911 return output_cbranch (operands[0], NULL, 0, insn);
12912 }"
12913 [(set_attr "type" "jmpreg")
12914 (set_attr "length" "4")])
12916 (define_insn ""
12917 [(set (pc)
12918 (if_then_else (match_operator 1 "branch_comparison_operator"
12919 [(match_operand 2
12920 "cc_reg_operand" "y")
12921 (const_int 0)])
12922 (pc)
12923 (label_ref (match_operand 0 "" ""))))]
12924 ""
12925 "*
12926 {
12927 return output_cbranch (operands[1], \"%l0\", 1, insn);
12928 }"
12929 [(set_attr "type" "branch")])
12931 (define_insn ""
12932 [(set (pc)
12933 (if_then_else (match_operator 0 "branch_comparison_operator"
12934 [(match_operand 1
12935 "cc_reg_operand" "y")
12936 (const_int 0)])
12937 (pc)
12938 (any_return)))]
12939 "<return_pred>"
12940 "*
12941 {
12942 return output_cbranch (operands[0], NULL, 1, insn);
12943 }"
12944 [(set_attr "type" "jmpreg")
12945 (set_attr "length" "4")])
12947 ;; Logic on condition register values.
12949 ; This pattern matches things like
12950 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12951 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12952 ; (const_int 1)))
12953 ; which are generated by the branch logic.
12954 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12956 (define_insn "*cceq_ior_compare"
12957 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12958 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12959 [(match_operator:SI 2
12960 "branch_positive_comparison_operator"
12961 [(match_operand 3
12962 "cc_reg_operand" "y,y")
12963 (const_int 0)])
12964 (match_operator:SI 4
12965 "branch_positive_comparison_operator"
12966 [(match_operand 5
12967 "cc_reg_operand" "0,y")
12968 (const_int 0)])])
12969 (const_int 1)))]
12970 ""
12971 "cr%q1 %E0,%j2,%j4"
12972 [(set_attr "type" "cr_logical,delayed_cr")])
12974 ; Why is the constant -1 here, but 1 in the previous pattern?
12975 ; Because ~1 has all but the low bit set.
12976 (define_insn ""
12977 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12978 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12979 [(not:SI (match_operator:SI 2
12980 "branch_positive_comparison_operator"
12981 [(match_operand 3
12982 "cc_reg_operand" "y,y")
12983 (const_int 0)]))
12984 (match_operator:SI 4
12985 "branch_positive_comparison_operator"
12986 [(match_operand 5
12987 "cc_reg_operand" "0,y")
12988 (const_int 0)])])
12989 (const_int -1)))]
12990 ""
12991 "cr%q1 %E0,%j2,%j4"
12992 [(set_attr "type" "cr_logical,delayed_cr")])
12994 (define_insn "*cceq_rev_compare"
12995 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12996 (compare:CCEQ (match_operator:SI 1
12997 "branch_positive_comparison_operator"
12998 [(match_operand 2
12999 "cc_reg_operand" "0,y")
13000 (const_int 0)])
13001 (const_int 0)))]
13002 ""
13003 "crnot %E0,%j1"
13004 [(set_attr "type" "cr_logical,delayed_cr")])
13006 ;; If we are comparing the result of two comparisons, this can be done
13007 ;; using creqv or crxor.
13009 (define_insn_and_split ""
13010 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13011 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13012 [(match_operand 2 "cc_reg_operand" "y")
13013 (const_int 0)])
13014 (match_operator 3 "branch_comparison_operator"
13015 [(match_operand 4 "cc_reg_operand" "y")
13016 (const_int 0)])))]
13017 ""
13018 "#"
13019 ""
13020 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13021 (match_dup 5)))]
13022 "
13023 {
13024 int positive_1, positive_2;
13026 positive_1 = branch_positive_comparison_operator (operands[1],
13027 GET_MODE (operands[1]));
13028 positive_2 = branch_positive_comparison_operator (operands[3],
13029 GET_MODE (operands[3]));
13031 if (! positive_1)
13032 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13033 GET_CODE (operands[1])),
13034 SImode,
13035 operands[2], const0_rtx);
13036 else if (GET_MODE (operands[1]) != SImode)
13037 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13038 operands[2], const0_rtx);
13040 if (! positive_2)
13041 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13042 GET_CODE (operands[3])),
13043 SImode,
13044 operands[4], const0_rtx);
13045 else if (GET_MODE (operands[3]) != SImode)
13046 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13047 operands[4], const0_rtx);
13049 if (positive_1 == positive_2)
13050 {
13051 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13052 operands[5] = constm1_rtx;
13053 }
13054 else
13055 {
13056 operands[5] = const1_rtx;
13057 }
13058 }")
13060 ;; Unconditional branch and return.
13062 (define_insn "jump"
13063 [(set (pc)
13064 (label_ref (match_operand 0 "" "")))]
13065 ""
13066 "b %l0"
13067 [(set_attr "type" "branch")])
13069 (define_insn "<return_str>return"
13070 [(any_return)]
13071 "<return_pred>"
13072 "blr"
13073 [(set_attr "type" "jmpreg")])
13075 (define_expand "indirect_jump"
13076 [(set (pc) (match_operand 0 "register_operand" ""))])
13078 (define_insn "*indirect_jump<mode>"
13079 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13080 ""
13081 "@
13082 bctr
13083 blr"
13084 [(set_attr "type" "jmpreg")])
13086 ;; Table jump for switch statements:
13087 (define_expand "tablejump"
13088 [(use (match_operand 0 "" ""))
13089 (use (label_ref (match_operand 1 "" "")))]
13090 ""
13091 "
13092 {
13093 if (TARGET_32BIT)
13094 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13095 else
13096 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13097 DONE;
13098 }")
13100 (define_expand "tablejumpsi"
13101 [(set (match_dup 3)
13102 (plus:SI (match_operand:SI 0 "" "")
13103 (match_dup 2)))
13104 (parallel [(set (pc) (match_dup 3))
13105 (use (label_ref (match_operand 1 "" "")))])]
13106 "TARGET_32BIT"
13107 "
13108 { operands[0] = force_reg (SImode, operands[0]);
13109 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13110 operands[3] = gen_reg_rtx (SImode);
13111 }")
13113 (define_expand "tablejumpdi"
13114 [(set (match_dup 4)
13115 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13116 (set (match_dup 3)
13117 (plus:DI (match_dup 4)
13118 (match_dup 2)))
13119 (parallel [(set (pc) (match_dup 3))
13120 (use (label_ref (match_operand 1 "" "")))])]
13121 "TARGET_64BIT"
13122 "
13123 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13124 operands[3] = gen_reg_rtx (DImode);
13125 operands[4] = gen_reg_rtx (DImode);
13126 }")
13128 (define_insn "*tablejump<mode>_internal1"
13129 [(set (pc)
13130 (match_operand:P 0 "register_operand" "c,*l"))
13131 (use (label_ref (match_operand 1 "" "")))]
13132 ""
13133 "@
13134 bctr
13135 blr"
13136 [(set_attr "type" "jmpreg")])
13138 (define_insn "nop"
13139 [(const_int 0)]
13140 ""
13141 "nop")
13143 (define_insn "group_ending_nop"
13144 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13145 ""
13146 "*
13147 {
13148 if (rs6000_cpu_attr == CPU_POWER6)
13149 return \"ori 1,1,0\";
13150 return \"ori 2,2,0\";
13151 }")
13152 \f
13153 ;; Define the subtract-one-and-jump insns, starting with the template
13154 ;; so loop.c knows what to generate.
13156 (define_expand "doloop_end"
13157 [(use (match_operand 0 "" "")) ; loop pseudo
13158 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13159 (use (match_operand 2 "" "")) ; max iterations
13160 (use (match_operand 3 "" "")) ; loop level
13161 (use (match_operand 4 "" ""))] ; label
13162 ""
13163 "
13164 {
13165 /* Only use this on innermost loops. */
13166 if (INTVAL (operands[3]) > 1)
13167 FAIL;
13168 if (TARGET_64BIT)
13169 {
13170 if (GET_MODE (operands[0]) != DImode)
13171 FAIL;
13172 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13173 }
13174 else
13175 {
13176 if (GET_MODE (operands[0]) != SImode)
13177 FAIL;
13178 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13179 }
13180 DONE;
13181 }")
13183 (define_expand "ctr<mode>"
13184 [(parallel [(set (pc)
13185 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13186 (const_int 1))
13187 (label_ref (match_operand 1 "" ""))
13188 (pc)))
13189 (set (match_dup 0)
13190 (plus:P (match_dup 0)
13191 (const_int -1)))
13192 (clobber (match_scratch:CC 2 ""))
13193 (clobber (match_scratch:P 3 ""))])]
13194 ""
13195 "")
13197 ;; We need to be able to do this for any operand, including MEM, or we
13198 ;; will cause reload to blow up since we don't allow output reloads on
13199 ;; JUMP_INSNs.
13200 ;; For the length attribute to be calculated correctly, the
13201 ;; label MUST be operand 0.
13203 (define_insn "*ctr<mode>_internal1"
13204 [(set (pc)
13205 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13206 (const_int 1))
13207 (label_ref (match_operand 0 "" ""))
13208 (pc)))
13209 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13210 (plus:P (match_dup 1)
13211 (const_int -1)))
13212 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13213 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13214 ""
13215 "*
13216 {
13217 if (which_alternative != 0)
13218 return \"#\";
13219 else if (get_attr_length (insn) == 4)
13220 return \"bdnz %l0\";
13221 else
13222 return \"bdz $+8\;b %l0\";
13223 }"
13224 [(set_attr "type" "branch")
13225 (set_attr "length" "*,12,16,16")])
13227 (define_insn "*ctr<mode>_internal2"
13228 [(set (pc)
13229 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13230 (const_int 1))
13231 (pc)
13232 (label_ref (match_operand 0 "" ""))))
13233 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13234 (plus:P (match_dup 1)
13235 (const_int -1)))
13236 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13237 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13238 ""
13239 "*
13240 {
13241 if (which_alternative != 0)
13242 return \"#\";
13243 else if (get_attr_length (insn) == 4)
13244 return \"bdz %l0\";
13245 else
13246 return \"bdnz $+8\;b %l0\";
13247 }"
13248 [(set_attr "type" "branch")
13249 (set_attr "length" "*,12,16,16")])
13251 ;; Similar but use EQ
13253 (define_insn "*ctr<mode>_internal5"
13254 [(set (pc)
13255 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13256 (const_int 1))
13257 (label_ref (match_operand 0 "" ""))
13258 (pc)))
13259 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13260 (plus:P (match_dup 1)
13261 (const_int -1)))
13262 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13263 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13264 ""
13265 "*
13266 {
13267 if (which_alternative != 0)
13268 return \"#\";
13269 else if (get_attr_length (insn) == 4)
13270 return \"bdz %l0\";
13271 else
13272 return \"bdnz $+8\;b %l0\";
13273 }"
13274 [(set_attr "type" "branch")
13275 (set_attr "length" "*,12,16,16")])
13277 (define_insn "*ctr<mode>_internal6"
13278 [(set (pc)
13279 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13280 (const_int 1))
13281 (pc)
13282 (label_ref (match_operand 0 "" ""))))
13283 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13284 (plus:P (match_dup 1)
13285 (const_int -1)))
13286 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13287 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13288 ""
13289 "*
13290 {
13291 if (which_alternative != 0)
13292 return \"#\";
13293 else if (get_attr_length (insn) == 4)
13294 return \"bdnz %l0\";
13295 else
13296 return \"bdz $+8\;b %l0\";
13297 }"
13298 [(set_attr "type" "branch")
13299 (set_attr "length" "*,12,16,16")])
13301 ;; Now the splitters if we could not allocate the CTR register
13303 (define_split
13304 [(set (pc)
13305 (if_then_else (match_operator 2 "comparison_operator"
13306 [(match_operand:P 1 "gpc_reg_operand" "")
13307 (const_int 1)])
13308 (match_operand 5 "" "")
13309 (match_operand 6 "" "")))
13310 (set (match_operand:P 0 "gpc_reg_operand" "")
13311 (plus:P (match_dup 1) (const_int -1)))
13312 (clobber (match_scratch:CC 3 ""))
13313 (clobber (match_scratch:P 4 ""))]
13314 "reload_completed"
13315 [(parallel [(set (match_dup 3)
13316 (compare:CC (plus:P (match_dup 1)
13317 (const_int -1))
13318 (const_int 0)))
13319 (set (match_dup 0)
13320 (plus:P (match_dup 1)
13321 (const_int -1)))])
13322 (set (pc) (if_then_else (match_dup 7)
13323 (match_dup 5)
13324 (match_dup 6)))]
13325 "
13326 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13327 operands[3], const0_rtx); }")
13329 (define_split
13330 [(set (pc)
13331 (if_then_else (match_operator 2 "comparison_operator"
13332 [(match_operand:P 1 "gpc_reg_operand" "")
13333 (const_int 1)])
13334 (match_operand 5 "" "")
13335 (match_operand 6 "" "")))
13336 (set (match_operand:P 0 "nonimmediate_operand" "")
13337 (plus:P (match_dup 1) (const_int -1)))
13338 (clobber (match_scratch:CC 3 ""))
13339 (clobber (match_scratch:P 4 ""))]
13340 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13341 [(parallel [(set (match_dup 3)
13342 (compare:CC (plus:P (match_dup 1)
13343 (const_int -1))
13344 (const_int 0)))
13345 (set (match_dup 4)
13346 (plus:P (match_dup 1)
13347 (const_int -1)))])
13348 (set (match_dup 0)
13349 (match_dup 4))
13350 (set (pc) (if_then_else (match_dup 7)
13351 (match_dup 5)
13352 (match_dup 6)))]
13353 "
13354 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13355 operands[3], const0_rtx); }")
13356 \f
13357 (define_insn "trap"
13358 [(trap_if (const_int 1) (const_int 0))]
13359 ""
13360 "trap"
13361 [(set_attr "type" "trap")])
13363 (define_expand "ctrap<mode>4"
13364 [(trap_if (match_operator 0 "ordered_comparison_operator"
13365 [(match_operand:GPR 1 "register_operand")
13366 (match_operand:GPR 2 "reg_or_short_operand")])
13367 (match_operand 3 "zero_constant" ""))]
13368 ""
13369 "")
13371 (define_insn ""
13372 [(trap_if (match_operator 0 "ordered_comparison_operator"
13373 [(match_operand:GPR 1 "register_operand" "r")
13374 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13375 (const_int 0))]
13376 ""
13377 "t<wd>%V0%I2 %1,%2"
13378 [(set_attr "type" "trap")])
13379 \f
13380 ;; Insns related to generating the function prologue and epilogue.
13382 (define_expand "prologue"
13383 [(use (const_int 0))]
13384 ""
13385 {
13386 rs6000_emit_prologue ();
13387 if (!TARGET_SCHED_PROLOG)
13388 emit_insn (gen_blockage ());
13389 DONE;
13390 })
13392 (define_insn "*movesi_from_cr_one"
13393 [(match_parallel 0 "mfcr_operation"
13394 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13395 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13396 (match_operand 3 "immediate_operand" "n")]
13397 UNSPEC_MOVESI_FROM_CR))])]
13398 "TARGET_MFCRF"
13399 "*
13400 {
13401 int mask = 0;
13402 int i;
13403 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13404 {
13405 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13406 operands[4] = GEN_INT (mask);
13407 output_asm_insn (\"mfcr %1,%4\", operands);
13408 }
13409 return \"\";
13410 }"
13411 [(set_attr "type" "mfcrf")])
13413 (define_insn "movesi_from_cr"
13414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13415 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13416 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13417 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13418 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13419 UNSPEC_MOVESI_FROM_CR))]
13420 ""
13421 "mfcr %0"
13422 [(set_attr "type" "mfcr")])
13424 (define_insn "*stmw"
13425 [(match_parallel 0 "stmw_operation"
13426 [(set (match_operand:SI 1 "memory_operand" "=m")
13427 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13428 "TARGET_MULTIPLE"
13429 "stmw %2,%1"
13430 [(set_attr "type" "store_ux")])
13432 ; The following comment applies to:
13433 ; save_gpregs_*
13434 ; save_fpregs_*
13435 ; restore_gpregs*
13436 ; return_and_restore_gpregs*
13437 ; return_and_restore_fpregs*
13438 ; return_and_restore_fpregs_aix*
13439 ;
13440 ; The out-of-line save / restore functions expects one input argument.
13441 ; Since those are not standard call_insn's, we must avoid using
13442 ; MATCH_OPERAND for that argument. That way the register rename
13443 ; optimization will not try to rename this register.
13444 ; Each pattern is repeated for each possible register number used in
13445 ; various ABIs (r11, r1, and for some functions r12)
13447 (define_insn "*save_gpregs_<mode>_r11"
13448 [(match_parallel 0 "any_parallel_operand"
13449 [(clobber (reg:P 65))
13450 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13451 (use (reg:P 11))
13452 (set (match_operand:P 2 "memory_operand" "=m")
13453 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13454 ""
13455 "bl %1"
13456 [(set_attr "type" "branch")
13457 (set_attr "length" "4")])
13459 (define_insn "*save_gpregs_<mode>_r12"
13460 [(match_parallel 0 "any_parallel_operand"
13461 [(clobber (reg:P 65))
13462 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13463 (use (reg:P 12))
13464 (set (match_operand:P 2 "memory_operand" "=m")
13465 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13466 ""
13467 "bl %1"
13468 [(set_attr "type" "branch")
13469 (set_attr "length" "4")])
13471 (define_insn "*save_gpregs_<mode>_r1"
13472 [(match_parallel 0 "any_parallel_operand"
13473 [(clobber (reg:P 65))
13474 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13475 (use (reg:P 1))
13476 (set (match_operand:P 2 "memory_operand" "=m")
13477 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13478 ""
13479 "bl %1"
13480 [(set_attr "type" "branch")
13481 (set_attr "length" "4")])
13483 (define_insn "*save_fpregs_<mode>_r11"
13484 [(match_parallel 0 "any_parallel_operand"
13485 [(clobber (reg:P 65))
13486 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13487 (use (reg:P 11))
13488 (set (match_operand:DF 2 "memory_operand" "=m")
13489 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13490 ""
13491 "bl %1"
13492 [(set_attr "type" "branch")
13493 (set_attr "length" "4")])
13495 (define_insn "*save_fpregs_<mode>_r12"
13496 [(match_parallel 0 "any_parallel_operand"
13497 [(clobber (reg:P 65))
13498 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13499 (use (reg:P 12))
13500 (set (match_operand:DF 2 "memory_operand" "=m")
13501 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13502 ""
13503 "bl %1"
13504 [(set_attr "type" "branch")
13505 (set_attr "length" "4")])
13507 (define_insn "*save_fpregs_<mode>_r1"
13508 [(match_parallel 0 "any_parallel_operand"
13509 [(clobber (reg:P 65))
13510 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13511 (use (reg:P 1))
13512 (set (match_operand:DF 2 "memory_operand" "=m")
13513 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13514 ""
13515 "bl %1"
13516 [(set_attr "type" "branch")
13517 (set_attr "length" "4")])
13519 ; This is to explain that changes to the stack pointer should
13520 ; not be moved over loads from or stores to stack memory.
13521 (define_insn "stack_tie"
13522 [(match_parallel 0 "tie_operand"
13523 [(set (mem:BLK (reg 1)) (const_int 0))])]
13524 ""
13525 ""
13526 [(set_attr "length" "0")])
13528 (define_expand "epilogue"
13529 [(use (const_int 0))]
13530 ""
13531 {
13532 if (!TARGET_SCHED_PROLOG)
13533 emit_insn (gen_blockage ());
13534 rs6000_emit_epilogue (FALSE);
13535 DONE;
13536 })
13538 ; On some processors, doing the mtcrf one CC register at a time is
13539 ; faster (like on the 604e). On others, doing them all at once is
13540 ; faster; for instance, on the 601 and 750.
13542 (define_expand "movsi_to_cr_one"
13543 [(set (match_operand:CC 0 "cc_reg_operand" "")
13544 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13545 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13546 ""
13547 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13549 (define_insn "*movsi_to_cr"
13550 [(match_parallel 0 "mtcrf_operation"
13551 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13552 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13553 (match_operand 3 "immediate_operand" "n")]
13554 UNSPEC_MOVESI_TO_CR))])]
13555 ""
13556 "*
13557 {
13558 int mask = 0;
13559 int i;
13560 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13561 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13562 operands[4] = GEN_INT (mask);
13563 return \"mtcrf %4,%2\";
13564 }"
13565 [(set_attr "type" "mtcr")])
13567 (define_insn "*mtcrfsi"
13568 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13569 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13570 (match_operand 2 "immediate_operand" "n")]
13571 UNSPEC_MOVESI_TO_CR))]
13572 "GET_CODE (operands[0]) == REG
13573 && CR_REGNO_P (REGNO (operands[0]))
13574 && GET_CODE (operands[2]) == CONST_INT
13575 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13576 "mtcrf %R0,%1"
13577 [(set_attr "type" "mtcr")])
13579 ; The load-multiple instructions have similar properties.
13580 ; Note that "load_multiple" is a name known to the machine-independent
13581 ; code that actually corresponds to the PowerPC load-string.
13583 (define_insn "*lmw"
13584 [(match_parallel 0 "lmw_operation"
13585 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13586 (match_operand:SI 2 "memory_operand" "m"))])]
13587 "TARGET_MULTIPLE"
13588 "lmw %1,%2"
13589 [(set_attr "type" "load_ux")
13590 (set_attr "cell_micro" "always")])
13592 (define_insn "*return_internal_<mode>"
13593 [(simple_return)
13594 (use (match_operand:P 0 "register_operand" "lc"))]
13595 ""
13596 "b%T0"
13597 [(set_attr "type" "jmpreg")])
13599 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13600 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13602 ; The following comment applies to:
13603 ; save_gpregs_*
13604 ; save_fpregs_*
13605 ; restore_gpregs*
13606 ; return_and_restore_gpregs*
13607 ; return_and_restore_fpregs*
13608 ; return_and_restore_fpregs_aix*
13609 ;
13610 ; The out-of-line save / restore functions expects one input argument.
13611 ; Since those are not standard call_insn's, we must avoid using
13612 ; MATCH_OPERAND for that argument. That way the register rename
13613 ; optimization will not try to rename this register.
13614 ; Each pattern is repeated for each possible register number used in
13615 ; various ABIs (r11, r1, and for some functions r12)
13617 (define_insn "*restore_gpregs_<mode>_r11"
13618 [(match_parallel 0 "any_parallel_operand"
13619 [(clobber (match_operand:P 1 "register_operand" "=l"))
13620 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13621 (use (reg:P 11))
13622 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13623 (match_operand:P 4 "memory_operand" "m"))])]
13624 ""
13625 "bl %2"
13626 [(set_attr "type" "branch")
13627 (set_attr "length" "4")])
13629 (define_insn "*restore_gpregs_<mode>_r12"
13630 [(match_parallel 0 "any_parallel_operand"
13631 [(clobber (match_operand:P 1 "register_operand" "=l"))
13632 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13633 (use (reg:P 12))
13634 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13635 (match_operand:P 4 "memory_operand" "m"))])]
13636 ""
13637 "bl %2"
13638 [(set_attr "type" "branch")
13639 (set_attr "length" "4")])
13641 (define_insn "*restore_gpregs_<mode>_r1"
13642 [(match_parallel 0 "any_parallel_operand"
13643 [(clobber (match_operand:P 1 "register_operand" "=l"))
13644 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13645 (use (reg:P 1))
13646 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13647 (match_operand:P 4 "memory_operand" "m"))])]
13648 ""
13649 "bl %2"
13650 [(set_attr "type" "branch")
13651 (set_attr "length" "4")])
13653 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13654 [(match_parallel 0 "any_parallel_operand"
13655 [(return)
13656 (clobber (match_operand:P 1 "register_operand" "=l"))
13657 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13658 (use (reg:P 11))
13659 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13660 (match_operand:P 4 "memory_operand" "m"))])]
13661 ""
13662 "b %2"
13663 [(set_attr "type" "branch")
13664 (set_attr "length" "4")])
13666 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13667 [(match_parallel 0 "any_parallel_operand"
13668 [(return)
13669 (clobber (match_operand:P 1 "register_operand" "=l"))
13670 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13671 (use (reg:P 12))
13672 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13673 (match_operand:P 4 "memory_operand" "m"))])]
13674 ""
13675 "b %2"
13676 [(set_attr "type" "branch")
13677 (set_attr "length" "4")])
13679 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13680 [(match_parallel 0 "any_parallel_operand"
13681 [(return)
13682 (clobber (match_operand:P 1 "register_operand" "=l"))
13683 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13684 (use (reg:P 1))
13685 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13686 (match_operand:P 4 "memory_operand" "m"))])]
13687 ""
13688 "b %2"
13689 [(set_attr "type" "branch")
13690 (set_attr "length" "4")])
13692 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13693 [(match_parallel 0 "any_parallel_operand"
13694 [(return)
13695 (clobber (match_operand:P 1 "register_operand" "=l"))
13696 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13697 (use (reg:P 11))
13698 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13699 (match_operand:DF 4 "memory_operand" "m"))])]
13700 ""
13701 "b %2"
13702 [(set_attr "type" "branch")
13703 (set_attr "length" "4")])
13705 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13706 [(match_parallel 0 "any_parallel_operand"
13707 [(return)
13708 (clobber (match_operand:P 1 "register_operand" "=l"))
13709 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13710 (use (reg:P 12))
13711 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13712 (match_operand:DF 4 "memory_operand" "m"))])]
13713 ""
13714 "b %2"
13715 [(set_attr "type" "branch")
13716 (set_attr "length" "4")])
13718 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13719 [(match_parallel 0 "any_parallel_operand"
13720 [(return)
13721 (clobber (match_operand:P 1 "register_operand" "=l"))
13722 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13723 (use (reg:P 1))
13724 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13725 (match_operand:DF 4 "memory_operand" "m"))])]
13726 ""
13727 "b %2"
13728 [(set_attr "type" "branch")
13729 (set_attr "length" "4")])
13731 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13732 [(match_parallel 0 "any_parallel_operand"
13733 [(return)
13734 (use (match_operand:P 1 "register_operand" "l"))
13735 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13736 (use (reg:P 11))
13737 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13738 (match_operand:DF 4 "memory_operand" "m"))])]
13739 ""
13740 "b %2"
13741 [(set_attr "type" "branch")
13742 (set_attr "length" "4")])
13744 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13745 [(match_parallel 0 "any_parallel_operand"
13746 [(return)
13747 (use (match_operand:P 1 "register_operand" "l"))
13748 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13749 (use (reg:P 1))
13750 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13751 (match_operand:DF 4 "memory_operand" "m"))])]
13752 ""
13753 "b %2"
13754 [(set_attr "type" "branch")
13755 (set_attr "length" "4")])
13757 ; This is used in compiling the unwind routines.
13758 (define_expand "eh_return"
13759 [(use (match_operand 0 "general_operand" ""))]
13760 ""
13761 "
13762 {
13763 if (TARGET_32BIT)
13764 emit_insn (gen_eh_set_lr_si (operands[0]));
13765 else
13766 emit_insn (gen_eh_set_lr_di (operands[0]));
13767 DONE;
13768 }")
13770 ; We can't expand this before we know where the link register is stored.
13771 (define_insn "eh_set_lr_<mode>"
13772 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13773 UNSPECV_EH_RR)
13774 (clobber (match_scratch:P 1 "=&b"))]
13775 ""
13776 "#")
13778 (define_split
13779 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13780 (clobber (match_scratch 1 ""))]
13781 "reload_completed"
13782 [(const_int 0)]
13783 "
13784 {
13785 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13786 DONE;
13787 }")
13789 (define_insn "prefetch"
13790 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13791 (match_operand:SI 1 "const_int_operand" "n")
13792 (match_operand:SI 2 "const_int_operand" "n"))]
13793 ""
13794 "*
13795 {
13796 if (GET_CODE (operands[0]) == REG)
13797 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13798 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13799 }"
13800 [(set_attr "type" "load")])
13801 \f
13802 (define_insn "bpermd_<mode>"
13803 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13804 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
13805 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
13806 "TARGET_POPCNTD"
13807 "bpermd %0,%1,%2"
13808 [(set_attr "type" "integer")])
13810 \f
13811 ;; Builtin fma support. Handle
13812 ;; Note that the conditions for expansion are in the FMA_F iterator.
13814 (define_expand "fma<mode>4"
13815 [(set (match_operand:FMA_F 0 "register_operand" "")
13816 (fma:FMA_F
13817 (match_operand:FMA_F 1 "register_operand" "")
13818 (match_operand:FMA_F 2 "register_operand" "")
13819 (match_operand:FMA_F 3 "register_operand" "")))]
13820 ""
13821 "")
13823 ; Altivec only has fma and nfms.
13824 (define_expand "fms<mode>4"
13825 [(set (match_operand:FMA_F 0 "register_operand" "")
13826 (fma:FMA_F
13827 (match_operand:FMA_F 1 "register_operand" "")
13828 (match_operand:FMA_F 2 "register_operand" "")
13829 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
13830 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13831 "")
13833 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
13834 (define_expand "fnma<mode>4"
13835 [(set (match_operand:FMA_F 0 "register_operand" "")
13836 (neg:FMA_F
13837 (fma:FMA_F
13838 (match_operand:FMA_F 1 "register_operand" "")
13839 (match_operand:FMA_F 2 "register_operand" "")
13840 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13841 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
13842 "")
13844 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
13845 (define_expand "fnms<mode>4"
13846 [(set (match_operand:FMA_F 0 "register_operand" "")
13847 (neg:FMA_F
13848 (fma:FMA_F
13849 (match_operand:FMA_F 1 "register_operand" "")
13850 (match_operand:FMA_F 2 "register_operand" "")
13851 (match_operand:FMA_F 3 "register_operand" ""))))]
13852 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13853 "")
13855 ; Not an official optab name, but used from builtins.
13856 (define_expand "nfma<mode>4"
13857 [(set (match_operand:FMA_F 0 "register_operand" "")
13858 (neg:FMA_F
13859 (fma:FMA_F
13860 (match_operand:FMA_F 1 "register_operand" "")
13861 (match_operand:FMA_F 2 "register_operand" "")
13862 (match_operand:FMA_F 3 "register_operand" ""))))]
13863 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13864 "")
13866 ; Not an official optab name, but used from builtins.
13867 (define_expand "nfms<mode>4"
13868 [(set (match_operand:FMA_F 0 "register_operand" "")
13869 (neg:FMA_F
13870 (fma:FMA_F
13871 (match_operand:FMA_F 1 "register_operand" "")
13872 (match_operand:FMA_F 2 "register_operand" "")
13873 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13874 ""
13875 "")
13877 (define_expand "rs6000_get_timebase"
13878 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
13879 ""
13880 {
13881 if (TARGET_POWERPC64)
13882 emit_insn (gen_rs6000_mftb_di (operands[0]));
13883 else
13884 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
13885 DONE;
13886 })
13888 (define_insn "rs6000_get_timebase_ppc32"
13889 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13890 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
13891 (clobber (match_scratch:SI 1 "=r"))
13892 (clobber (match_scratch:CC 2 "=y"))]
13893 "!TARGET_POWERPC64"
13894 {
13895 if (WORDS_BIG_ENDIAN)
13896 if (TARGET_MFCRF)
13897 {
13898 return "mfspr %0,269\;"
13899 "mfspr %L0,268\;"
13900 "mfspr %1,269\;"
13901 "cmpw %2,%0,%1\;"
13902 "bne- %2,$-16";
13903 }
13904 else
13905 {
13906 return "mftbu %0\;"
13907 "mftb %L0\;"
13908 "mftbu %1\;"
13909 "cmpw %2,%0,%1\;"
13910 "bne- %2,$-16";
13911 }
13912 else
13913 if (TARGET_MFCRF)
13914 {
13915 return "mfspr %L0,269\;"
13916 "mfspr %0,268\;"
13917 "mfspr %1,269\;"
13918 "cmpw %2,%L0,%1\;"
13919 "bne- %2,$-16";
13920 }
13921 else
13922 {
13923 return "mftbu %L0\;"
13924 "mftb %0\;"
13925 "mftbu %1\;"
13926 "cmpw %2,%L0,%1\;"
13927 "bne- %2,$-16";
13928 }
13929 })
13931 (define_insn "rs6000_mftb_<mode>"
13932 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13933 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
13934 ""
13935 {
13936 if (TARGET_MFCRF)
13937 return "mfspr %0,268";
13938 else
13939 return "mftb %0";
13940 })
13942 \f
13944 (include "sync.md")
13945 (include "vector.md")
13946 (include "vsx.md")
13947 (include "altivec.md")
13948 (include "spe.md")
13949 (include "dfp.md")
13950 (include "paired.md")