1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode
;
56 typedef struct minipool_fixup Mfix
;
58 /* In order to improve the layout of the prototypes below
59 some short type abbreviations are defined here. */
60 #define Hint HOST_WIDE_INT
61 #define Mmode enum machine_mode
62 #define Ulong unsigned long
63 #define Ccstar const char *
65 const char extra_reg_names1
[][16] =
66 { "mv0", "mv1", "mv2", "mv3", "mv4", "mv5", "mv6", "mv7",
67 "mv8", "mv9", "mv10", "mv11", "mv12", "mv13", "mv14", "mv15"
69 #define extra_reg_names1 bogus1_regnames
71 const struct attribute_spec arm_attribute_table
[];
73 /* Forward function declarations. */
74 static void arm_add_gc_roots
PARAMS ((void));
75 static int arm_gen_constant
PARAMS ((enum rtx_code
, Mmode
, Hint
, rtx
, rtx
, int, int));
76 static unsigned bit_count
PARAMS ((Ulong
));
77 static int arm_address_register_rtx_p
PARAMS ((rtx
, int));
78 static int arm_legitimate_index_p
PARAMS ((Mmode
, rtx
, int));
79 static int thumb_base_register_rtx_p
PARAMS ((rtx
, Mmode
, int));
80 inline static int thumb_index_register_rtx_p
PARAMS ((rtx
, int));
81 static int const_ok_for_op
PARAMS ((Hint
, enum rtx_code
));
82 static int eliminate_lr2ip
PARAMS ((rtx
*));
83 static rtx emit_multi_reg_push
PARAMS ((int));
84 static rtx emit_sfm
PARAMS ((int, int));
86 static bool arm_assemble_integer
PARAMS ((rtx
, unsigned int, int));
88 static Ccstar fp_const_from_val
PARAMS ((REAL_VALUE_TYPE
*));
89 static arm_cc get_arm_condition_code
PARAMS ((rtx
));
90 static void init_fpa_table
PARAMS ((void));
91 static Hint int_log2
PARAMS ((Hint
));
92 static rtx is_jump_table
PARAMS ((rtx
));
93 static Ccstar output_multi_immediate
PARAMS ((rtx
*, Ccstar
, Ccstar
, int, Hint
));
94 static void print_multi_reg
PARAMS ((FILE *, Ccstar
, int, int));
95 static Ccstar shift_op
PARAMS ((rtx
, Hint
*));
96 static struct machine_function
* arm_init_machine_status
PARAMS ((void));
97 static int number_of_first_bit_set
PARAMS ((int));
98 static void replace_symbols_in_block
PARAMS ((tree
, rtx
, rtx
));
99 static void thumb_exit
PARAMS ((FILE *, int, rtx
));
100 static void thumb_pushpop
PARAMS ((FILE *, int, int));
101 static Ccstar thumb_condition_code
PARAMS ((rtx
, int));
102 static rtx is_jump_table
PARAMS ((rtx
));
103 static Hint get_jump_table_size
PARAMS ((rtx
));
104 static Mnode
* move_minipool_fix_forward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
105 static Mnode
* add_minipool_forward_ref
PARAMS ((Mfix
*));
106 static Mnode
* move_minipool_fix_backward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
107 static Mnode
* add_minipool_backward_ref
PARAMS ((Mfix
*));
108 static void assign_minipool_offsets
PARAMS ((Mfix
*));
109 static void arm_print_value
PARAMS ((FILE *, rtx
));
110 static void dump_minipool
PARAMS ((rtx
));
111 static int arm_barrier_cost
PARAMS ((rtx
));
112 static Mfix
* create_fix_barrier
PARAMS ((Mfix
*, Hint
));
113 static void push_minipool_barrier
PARAMS ((rtx
, Hint
));
114 static void push_minipool_fix
PARAMS ((rtx
, Hint
, rtx
*, Mmode
, rtx
));
115 static bool note_invalid_constants
PARAMS ((rtx
, Hint
, int));
116 static int current_file_function_operand
PARAMS ((rtx
));
117 static Ulong arm_compute_save_reg0_reg12_mask
PARAMS ((void));
118 static Ulong arm_compute_save_reg_mask
PARAMS ((void));
119 static Ulong arm_isr_value
PARAMS ((tree
));
120 static Ulong arm_compute_func_type
PARAMS ((void));
121 static tree arm_handle_fndecl_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
122 static tree arm_handle_isr_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
123 static void arm_output_function_epilogue
PARAMS ((FILE *, Hint
));
124 static void arm_output_function_prologue
PARAMS ((FILE *, Hint
));
125 static void thumb_output_function_prologue
PARAMS ((FILE *, Hint
));
126 static int arm_comp_type_attributes
PARAMS ((tree
, tree
));
127 static void arm_set_default_type_attributes
PARAMS ((tree
));
128 static int arm_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
129 static int count_insns_for_constant
PARAMS ((Hint
, int));
130 static int arm_get_strip_length
PARAMS ((int));
131 static bool arm_function_ok_for_sibcall
PARAMS ((tree
, tree
));
132 static void arm_internal_label
PARAMS ((FILE *, Ccstar
, Ulong
));
133 static void arm_output_mi_thunk
PARAMS ((FILE *, tree
, Hint
, Hint
, tree
));
134 static int arm_rtx_costs_1
PARAMS ((rtx
, enum rtx_code
, enum rtx_code
));
135 static bool arm_rtx_costs
PARAMS ((rtx
, int, int, int *));
136 static int arm_address_cost
PARAMS ((rtx
));
137 static bool arm_memory_load_p
PARAMS ((rtx
));
138 static bool arm_cirrus_insn_p
PARAMS ((rtx
));
139 static void cirrus_reorg
PARAMS ((rtx
));
140 #ifdef OBJECT_FORMAT_ELF
141 static void arm_elf_asm_named_section
PARAMS ((Ccstar
, unsigned int));
144 static void arm_encode_section_info
PARAMS ((tree
, rtx
, int));
147 static void aof_globalize_label
PARAMS ((FILE *, Ccstar
));
155 /* Initialize the GCC target structure. */
156 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
157 #undef TARGET_MERGE_DECL_ATTRIBUTES
158 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
161 #undef TARGET_ATTRIBUTE_TABLE
162 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tDCB\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
171 #undef TARGET_ASM_GLOBALIZE_LABEL
172 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
174 #undef TARGET_ASM_ALIGNED_SI_OP
175 #define TARGET_ASM_ALIGNED_SI_OP NULL
176 #undef TARGET_ASM_INTEGER
177 #define TARGET_ASM_INTEGER arm_assemble_integer
180 #undef TARGET_ASM_FUNCTION_PROLOGUE
181 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
183 #undef TARGET_ASM_FUNCTION_EPILOGUE
184 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
186 #undef TARGET_COMP_TYPE_ATTRIBUTES
187 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
189 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
190 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
192 #undef TARGET_SCHED_ADJUST_COST
193 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
195 #undef TARGET_ENCODE_SECTION_INFO
197 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
199 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
202 #undef TARGET_STRIP_NAME_ENCODING
203 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
205 #undef TARGET_ASM_INTERNAL_LABEL
206 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
208 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
209 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
211 #undef TARGET_ASM_OUTPUT_MI_THUNK
212 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
213 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
214 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
216 #undef TARGET_RTX_COSTS
217 #define TARGET_RTX_COSTS arm_rtx_costs
218 #undef TARGET_ADDRESS_COST
219 #define TARGET_ADDRESS_COST arm_address_cost
221 struct gcc_target targetm
= TARGET_INITIALIZER
;
223 /* Obstack for minipool constant handling. */
224 static struct obstack minipool_obstack
;
225 static char * minipool_startobj
;
227 /* The maximum number of insns skipped which
228 will be conditionalised if possible. */
229 static int max_insns_skipped
= 5;
231 extern FILE * asm_out_file
;
233 /* True if we are currently building a constant table. */
234 int making_const_table
;
236 /* Define the information needed to generate branch insns. This is
237 stored from the compare operation. */
238 rtx arm_compare_op0
, arm_compare_op1
;
240 /* What type of floating point are we tuning for? */
241 enum fputype arm_fpu_tune
;
243 /* What type of floating point instructions are available? */
244 enum fputype arm_fpu_arch
;
246 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
247 enum prog_mode_type arm_prgmode
;
249 /* Set by the -mfp=... option. */
250 const char * target_fp_name
= NULL
;
252 /* Used to parse -mstructure_size_boundary command line option. */
253 const char * structure_size_string
= NULL
;
254 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
256 /* Bit values used to identify processor capabilities. */
257 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
258 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
259 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
260 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
261 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
262 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
263 #define FL_THUMB (1 << 6) /* Thumb aware */
264 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
265 #define FL_STRONG (1 << 8) /* StrongARM */
266 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
267 #define FL_XSCALE (1 << 10) /* XScale */
268 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
270 /* The bits in this mask specify which
271 instructions we are allowed to generate. */
272 static unsigned long insn_flags
= 0;
274 /* The bits in this mask specify which instruction scheduling options should
275 be used. Note - there is an overlap with the FL_FAST_MULT. For some
276 hardware we want to be able to generate the multiply instructions, but to
277 tune as if they were not present in the architecture. */
278 static unsigned long tune_flags
= 0;
280 /* The following are used in the arm.md file as equivalents to bits
281 in the above two flag variables. */
283 /* Nonzero if this is an "M" variant of the processor. */
284 int arm_fast_multiply
= 0;
286 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
289 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
292 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
295 /* Nonzero if this chip can benefit from load scheduling. */
296 int arm_ld_sched
= 0;
298 /* Nonzero if this chip is a StrongARM. */
299 int arm_is_strong
= 0;
301 /* Nonzero if this chip is an XScale. */
302 int arm_is_xscale
= 0;
304 /* Nonzero if this chip is an ARM6 or an ARM7. */
305 int arm_is_6_or_7
= 0;
307 /* Nonzero if this chip is a Cirrus/DSP. */
308 int arm_is_cirrus
= 0;
310 /* Nonzero if generating Thumb instructions. */
313 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
314 must report the mode of the memory reference from PRINT_OPERAND to
315 PRINT_OPERAND_ADDRESS. */
316 enum machine_mode output_memory_reference_mode
;
318 /* The register number to be used for the PIC offset register. */
319 const char * arm_pic_register_string
= NULL
;
320 int arm_pic_register
= INVALID_REGNUM
;
322 /* Set to 1 when a return insn is output, this means that the epilogue
324 int return_used_this_function
;
326 /* Set to 1 after arm_reorg has started. Reset to start at the start of
327 the next function. */
328 static int after_arm_reorg
= 0;
330 /* The maximum number of insns to be used when loading a constant. */
331 static int arm_constant_limit
= 3;
333 /* For an explanation of these variables, see final_prescan_insn below. */
335 enum arm_cond_code arm_current_cc
;
337 int arm_target_label
;
339 /* The condition codes of the ARM, and the inverse function. */
340 static const char * const arm_condition_codes
[] =
342 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
343 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
346 #define streq(string1, string2) (strcmp (string1, string2) == 0)
348 /* Initialization code. */
352 const char *const name
;
353 const unsigned long flags
;
356 /* Not all of these give usefully different compilation alternatives,
357 but there is no simple way of generalizing them. */
358 static const struct processors all_cores
[] =
362 {"arm2", FL_CO_PROC
| FL_MODE26
},
363 {"arm250", FL_CO_PROC
| FL_MODE26
},
364 {"arm3", FL_CO_PROC
| FL_MODE26
},
365 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
366 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
367 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
368 {"arm610", FL_MODE26
| FL_MODE32
},
369 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
370 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
371 /* arm7m doesn't exist on its own, but only with D, (and I), but
372 those don't alter the code, so arm7m is sometimes used. */
373 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
374 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
375 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
376 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
377 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
378 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
379 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
380 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
381 {"arm710", FL_MODE26
| FL_MODE32
},
382 {"arm710t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
383 {"arm720", FL_MODE26
| FL_MODE32
},
384 {"arm720t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
385 {"arm740t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
386 {"arm710c", FL_MODE26
| FL_MODE32
},
387 {"arm7100", FL_MODE26
| FL_MODE32
},
388 {"arm7500", FL_MODE26
| FL_MODE32
},
389 /* Doesn't have an external co-proc, but does have embedded fpa. */
390 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
391 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
392 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
393 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
394 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
395 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
396 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
397 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
398 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
399 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
400 {"ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
401 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
402 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
403 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
404 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
405 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
406 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
407 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
412 static const struct processors all_architectures
[] =
414 /* ARM Architectures */
416 { "armv2", FL_CO_PROC
| FL_MODE26
},
417 { "armv2a", FL_CO_PROC
| FL_MODE26
},
418 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
419 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
420 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
421 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
422 implementations that support it, so we will leave it out for now. */
423 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
424 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
425 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
426 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
427 { "ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
431 /* This is a magic stucture. The 'string' field is magically filled in
432 with a pointer to the value specified by the user on the command line
433 assuming that the user has specified such a value. */
435 struct arm_cpu_select arm_select
[] =
437 /* string name processors */
438 { NULL
, "-mcpu=", all_cores
},
439 { NULL
, "-march=", all_architectures
},
440 { NULL
, "-mtune=", all_cores
}
443 /* Return the number of bits set in VALUE. */
448 unsigned long count
= 0;
453 value
&= value
- 1; /* Clear the least-significant set bit. */
459 /* Fix up any incompatible options that the user has specified.
460 This has now turned into a maze. */
462 arm_override_options ()
466 /* Set up the flags based on the cpu/architecture selected by the user. */
467 for (i
= ARRAY_SIZE (arm_select
); i
--;)
469 struct arm_cpu_select
* ptr
= arm_select
+ i
;
471 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
473 const struct processors
* sel
;
475 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
476 if (streq (ptr
->string
, sel
->name
))
479 tune_flags
= sel
->flags
;
482 /* If we have been given an architecture and a processor
483 make sure that they are compatible. We only generate
484 a warning though, and we prefer the CPU over the
486 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
487 warning ("switch -mcpu=%s conflicts with -march= switch",
490 insn_flags
= sel
->flags
;
496 if (sel
->name
== NULL
)
497 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
501 /* If the user did not specify a processor, choose one for them. */
504 const struct processors
* sel
;
506 static const struct cpu_default
509 const char *const name
;
513 { TARGET_CPU_arm2
, "arm2" },
514 { TARGET_CPU_arm6
, "arm6" },
515 { TARGET_CPU_arm610
, "arm610" },
516 { TARGET_CPU_arm710
, "arm710" },
517 { TARGET_CPU_arm7m
, "arm7m" },
518 { TARGET_CPU_arm7500fe
, "arm7500fe" },
519 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
520 { TARGET_CPU_arm8
, "arm8" },
521 { TARGET_CPU_arm810
, "arm810" },
522 { TARGET_CPU_arm9
, "arm9" },
523 { TARGET_CPU_strongarm
, "strongarm" },
524 { TARGET_CPU_xscale
, "xscale" },
525 { TARGET_CPU_ep9312
, "ep9312" },
526 { TARGET_CPU_generic
, "arm" },
529 const struct cpu_default
* def
;
531 /* Find the default. */
532 for (def
= cpu_defaults
; def
->name
; def
++)
533 if (def
->cpu
== TARGET_CPU_DEFAULT
)
536 /* Make sure we found the default CPU. */
537 if (def
->name
== NULL
)
540 /* Find the default CPU's flags. */
541 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
542 if (streq (def
->name
, sel
->name
))
545 if (sel
->name
== NULL
)
548 insn_flags
= sel
->flags
;
550 /* Now check to see if the user has specified some command line
551 switch that require certain abilities from the cpu. */
554 if (TARGET_INTERWORK
|| TARGET_THUMB
)
556 sought
|= (FL_THUMB
| FL_MODE32
);
558 /* Force apcs-32 to be used for interworking. */
559 target_flags
|= ARM_FLAG_APCS_32
;
561 /* There are no ARM processors that support both APCS-26 and
562 interworking. Therefore we force FL_MODE26 to be removed
563 from insn_flags here (if it was set), so that the search
564 below will always be able to find a compatible processor. */
565 insn_flags
&= ~FL_MODE26
;
567 else if (!TARGET_APCS_32
)
570 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
572 /* Try to locate a CPU type that supports all of the abilities
573 of the default CPU, plus the extra abilities requested by
575 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
576 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
579 if (sel
->name
== NULL
)
581 unsigned current_bit_count
= 0;
582 const struct processors
* best_fit
= NULL
;
584 /* Ideally we would like to issue an error message here
585 saying that it was not possible to find a CPU compatible
586 with the default CPU, but which also supports the command
587 line options specified by the programmer, and so they
588 ought to use the -mcpu=<name> command line option to
589 override the default CPU type.
591 Unfortunately this does not work with multilibing. We
592 need to be able to support multilibs for -mapcs-26 and for
593 -mthumb-interwork and there is no CPU that can support both
594 options. Instead if we cannot find a cpu that has both the
595 characteristics of the default cpu and the given command line
596 options we scan the array again looking for a best match. */
597 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
598 if ((sel
->flags
& sought
) == sought
)
602 count
= bit_count (sel
->flags
& insn_flags
);
604 if (count
>= current_bit_count
)
607 current_bit_count
= count
;
611 if (best_fit
== NULL
)
617 insn_flags
= sel
->flags
;
621 /* If tuning has not been specified, tune for whichever processor or
622 architecture has been selected. */
624 tune_flags
= insn_flags
;
626 /* Make sure that the processor choice does not conflict with any of the
627 other command line choices. */
628 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
630 /* If APCS-32 was not the default then it must have been set by the
631 user, so issue a warning message. If the user has specified
632 "-mapcs-32 -mcpu=arm2" then we loose here. */
633 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
634 warning ("target CPU does not support APCS-32" );
635 target_flags
&= ~ARM_FLAG_APCS_32
;
637 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
639 warning ("target CPU does not support APCS-26" );
640 target_flags
|= ARM_FLAG_APCS_32
;
643 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
645 warning ("target CPU does not support interworking" );
646 target_flags
&= ~ARM_FLAG_INTERWORK
;
649 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
651 warning ("target CPU does not support THUMB instructions");
652 target_flags
&= ~ARM_FLAG_THUMB
;
655 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
657 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
658 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
661 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
662 from here where no function is being compiled currently. */
663 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
665 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
667 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
668 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
670 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
671 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
673 /* If interworking is enabled then APCS-32 must be selected as well. */
674 if (TARGET_INTERWORK
)
677 warning ("interworking forces APCS-32 to be used" );
678 target_flags
|= ARM_FLAG_APCS_32
;
681 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
683 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
684 target_flags
|= ARM_FLAG_APCS_FRAME
;
687 if (TARGET_POKE_FUNCTION_NAME
)
688 target_flags
|= ARM_FLAG_APCS_FRAME
;
690 if (TARGET_APCS_REENT
&& flag_pic
)
691 error ("-fpic and -mapcs-reent are incompatible");
693 if (TARGET_APCS_REENT
)
694 warning ("APCS reentrant code not supported. Ignored");
696 /* If this target is normally configured to use APCS frames, warn if they
697 are turned off and debugging is turned on. */
699 && write_symbols
!= NO_DEBUG
700 && !TARGET_APCS_FRAME
701 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
702 warning ("-g with -mno-apcs-frame may not give sensible debugging");
704 /* If stack checking is disabled, we can use r10 as the PIC register,
705 which keeps r9 available. */
707 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
709 if (TARGET_APCS_FLOAT
)
710 warning ("passing floating point arguments in fp regs not yet supported");
712 /* Initialize boolean versions of the flags, for use in the arm.md file. */
713 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
714 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
715 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
716 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
717 arm_is_xscale
= (insn_flags
& FL_XSCALE
) != 0;
719 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
720 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
721 thumb_code
= (TARGET_ARM
== 0);
722 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
723 && !(tune_flags
& FL_ARCH4
))) != 0;
724 arm_is_cirrus
= (tune_flags
& FL_CIRRUS
) != 0;
728 arm_fpu_tune
= FPUTYPE_MAVERICK
;
730 /* Ignore -mhard-float if -mcpu=ep9312. */
731 if (TARGET_HARD_FLOAT
)
732 target_flags
^= ARM_FLAG_SOFT_FLOAT
;
735 /* Default value for floating point code... if no co-processor
736 bus, then schedule for emulated floating point. Otherwise,
737 assume the user has an FPA.
738 Note: this does not prevent use of floating point instructions,
739 -msoft-float does that. */
740 arm_fpu_tune
= (tune_flags
& FL_CO_PROC
) ? FPUTYPE_FPA
: FPUTYPE_FPA_EMU3
;
744 if (streq (target_fp_name
, "2"))
745 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
746 else if (streq (target_fp_name
, "3"))
747 arm_fpu_arch
= FPUTYPE_FPA_EMU3
;
749 error ("invalid floating point emulation option: -mfpe-%s",
753 arm_fpu_arch
= FPUTYPE_DEFAULT
;
757 if (arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
758 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
759 else if (arm_fpu_tune
== FPUTYPE_MAVERICK
)
760 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
761 else if (arm_fpu_tune
!= FPUTYPE_FPA
)
762 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
765 /* For arm2/3 there is no need to do any scheduling if there is only
766 a floating point emulator, or we are doing software floating-point. */
767 if ((TARGET_SOFT_FLOAT
|| arm_fpu_tune
!= FPUTYPE_FPA
)
768 && (tune_flags
& FL_MODE32
) == 0)
769 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
771 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
773 if (structure_size_string
!= NULL
)
775 int size
= strtol (structure_size_string
, NULL
, 0);
777 if (size
== 8 || size
== 32)
778 arm_structure_size_boundary
= size
;
780 warning ("structure size boundary can only be set to 8 or 32");
783 if (arm_pic_register_string
!= NULL
)
785 int pic_register
= decode_reg_name (arm_pic_register_string
);
788 warning ("-mpic-register= is useless without -fpic");
790 /* Prevent the user from choosing an obviously stupid PIC register. */
791 else if (pic_register
< 0 || call_used_regs
[pic_register
]
792 || pic_register
== HARD_FRAME_POINTER_REGNUM
793 || pic_register
== STACK_POINTER_REGNUM
794 || pic_register
>= PC_REGNUM
)
795 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
797 arm_pic_register
= pic_register
;
800 if (TARGET_THUMB
&& flag_schedule_insns
)
802 /* Don't warn since it's on by default in -O2. */
803 flag_schedule_insns
= 0;
806 /* If optimizing for space, don't synthesize constants.
807 For processors with load scheduling, it never costs more than 2 cycles
808 to load a constant, and the load scheduler may well reduce that to 1. */
809 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
810 arm_constant_limit
= 1;
813 arm_constant_limit
= 2;
815 /* If optimizing for size, bump the number of instructions that we
816 are prepared to conditionally execute (even on a StrongARM).
817 Otherwise for the StrongARM, which has early execution of branches,
818 a sequence that is worth skipping is shorter. */
820 max_insns_skipped
= 6;
821 else if (arm_is_strong
)
822 max_insns_skipped
= 3;
824 /* Register global variables with the garbage collector. */
831 gcc_obstack_init(&minipool_obstack
);
832 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
835 /* A table of known ARM exception types.
836 For use with the interrupt function attribute. */
840 const char *const arg
;
841 const unsigned long return_value
;
845 static const isr_attribute_arg isr_attribute_args
[] =
847 { "IRQ", ARM_FT_ISR
},
848 { "irq", ARM_FT_ISR
},
849 { "FIQ", ARM_FT_FIQ
},
850 { "fiq", ARM_FT_FIQ
},
851 { "ABORT", ARM_FT_ISR
},
852 { "abort", ARM_FT_ISR
},
853 { "ABORT", ARM_FT_ISR
},
854 { "abort", ARM_FT_ISR
},
855 { "UNDEF", ARM_FT_EXCEPTION
},
856 { "undef", ARM_FT_EXCEPTION
},
857 { "SWI", ARM_FT_EXCEPTION
},
858 { "swi", ARM_FT_EXCEPTION
},
859 { NULL
, ARM_FT_NORMAL
}
862 /* Returns the (interrupt) function type of the current
863 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
866 arm_isr_value (argument
)
869 const isr_attribute_arg
* ptr
;
872 /* No argument - default to IRQ. */
873 if (argument
== NULL_TREE
)
876 /* Get the value of the argument. */
877 if (TREE_VALUE (argument
) == NULL_TREE
878 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
879 return ARM_FT_UNKNOWN
;
881 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
883 /* Check it against the list of known arguments. */
884 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
885 if (streq (arg
, ptr
->arg
))
886 return ptr
->return_value
;
888 /* An unrecognized interrupt type. */
889 return ARM_FT_UNKNOWN
;
892 /* Computes the type of the current function. */
895 arm_compute_func_type ()
897 unsigned long type
= ARM_FT_UNKNOWN
;
901 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
904 /* Decide if the current function is volatile. Such functions
905 never return, and many memory cycles can be saved by not storing
906 register values that will never be needed again. This optimization
907 was added to speed up context switching in a kernel application. */
909 && current_function_nothrow
910 && TREE_THIS_VOLATILE (current_function_decl
))
911 type
|= ARM_FT_VOLATILE
;
913 if (current_function_needs_context
)
914 type
|= ARM_FT_NESTED
;
916 attr
= DECL_ATTRIBUTES (current_function_decl
);
918 a
= lookup_attribute ("naked", attr
);
920 type
|= ARM_FT_NAKED
;
922 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
923 type
|= ARM_FT_EXCEPTION_HANDLER
;
926 a
= lookup_attribute ("isr", attr
);
928 a
= lookup_attribute ("interrupt", attr
);
931 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
933 type
|= arm_isr_value (TREE_VALUE (a
));
939 /* Returns the type of the current function. */
942 arm_current_func_type ()
944 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
945 cfun
->machine
->func_type
= arm_compute_func_type ();
947 return cfun
->machine
->func_type
;
950 /* Return 1 if it is possible to return using a single instruction. */
953 use_return_insn (iscond
)
957 unsigned int func_type
;
958 unsigned long saved_int_regs
;
960 /* Never use a return instruction before reload has run. */
961 if (!reload_completed
)
964 func_type
= arm_current_func_type ();
966 /* Naked functions and volatile functions need special
968 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
971 /* So do interrupt functions that use the frame pointer. */
972 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
975 /* As do variadic functions. */
976 if (current_function_pretend_args_size
977 || cfun
->machine
->uses_anonymous_args
978 /* Of if the function calls __builtin_eh_return () */
979 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
980 /* Or if there is no frame pointer and there is a stack adjustment. */
981 || ((arm_get_frame_size () + current_function_outgoing_args_size
!= 0)
982 && !frame_pointer_needed
))
985 saved_int_regs
= arm_compute_save_reg_mask ();
987 /* Can't be done if interworking with Thumb, and any registers have been
989 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
992 /* On StrongARM, conditional returns are expensive if they aren't
993 taken and multiple registers have been stacked. */
994 if (iscond
&& arm_is_strong
)
996 /* Conditional return when just the LR is stored is a simple
997 conditional-load instruction, that's not expensive. */
998 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1001 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1005 /* If there are saved registers but the LR isn't saved, then we need
1006 two instructions for the return. */
1007 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1010 /* Can't be done if any of the FPA regs are pushed,
1011 since this also requires an insn. */
1012 if (TARGET_HARD_FLOAT
)
1013 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
1014 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1020 /* Return TRUE if int I is a valid immediate ARM constant. */
1023 const_ok_for_arm (i
)
1026 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1028 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1029 be all zero, or all one. */
1030 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1031 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1032 != ((~(unsigned HOST_WIDE_INT
) 0)
1033 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1036 /* Fast return for 0 and powers of 2 */
1037 if ((i
& (i
- 1)) == 0)
1042 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1045 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1046 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1048 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1053 /* Return true if I is a valid constant for the operation CODE. */
1055 const_ok_for_op (i
, code
)
1059 if (const_ok_for_arm (i
))
1065 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1067 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1073 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1080 /* Emit a sequence of insns to handle a large constant.
1081 CODE is the code of the operation required, it can be any of SET, PLUS,
1082 IOR, AND, XOR, MINUS;
1083 MODE is the mode in which the operation is being performed;
1084 VAL is the integer to operate on;
1085 SOURCE is the other operand (a register, or a null-pointer for SET);
1086 SUBTARGETS means it is safe to create scratch registers if that will
1087 either produce a simpler sequence, or we will want to cse the values.
1088 Return value is the number of insns emitted. */
1091 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
1093 enum machine_mode mode
;
1099 if (subtargets
|| code
== SET
1100 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1101 && REGNO (target
) != REGNO (source
)))
1103 /* After arm_reorg has been called, we can't fix up expensive
1104 constants by pushing them into memory so we must synthesize
1105 them in-line, regardless of the cost. This is only likely to
1106 be more costly on chips that have load delay slots and we are
1107 compiling without running the scheduler (so no splitting
1108 occurred before the final instruction emission).
1110 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1112 if (!after_arm_reorg
1113 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1114 > arm_constant_limit
+ (code
!= SET
)))
1118 /* Currently SET is the only monadic value for CODE, all
1119 the rest are diadic. */
1120 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1125 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1127 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1128 /* For MINUS, the value is subtracted from, since we never
1129 have subtraction of a constant. */
1131 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1132 gen_rtx_MINUS (mode
, temp
, source
)));
1134 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1135 gen_rtx (code
, mode
, source
, temp
)));
1141 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1145 count_insns_for_constant (remainder
, i
)
1146 HOST_WIDE_INT remainder
;
1149 HOST_WIDE_INT temp1
;
1157 if (remainder
& (3 << (i
- 2)))
1162 temp1
= remainder
& ((0x0ff << end
)
1163 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1164 remainder
&= ~temp1
;
1169 } while (remainder
);
1173 /* As above, but extra parameter GENERATE which, if clear, suppresses
1177 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
1179 enum machine_mode mode
;
1188 int can_negate_initial
= 0;
1191 int num_bits_set
= 0;
1192 int set_sign_bit_copies
= 0;
1193 int clear_sign_bit_copies
= 0;
1194 int clear_zero_bit_copies
= 0;
1195 int set_zero_bit_copies
= 0;
1197 unsigned HOST_WIDE_INT temp1
, temp2
;
1198 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1200 /* Find out which operations are safe for a given CODE. Also do a quick
1201 check for degenerate cases; these can occur when DImode operations
1213 can_negate_initial
= 1;
1217 if (remainder
== 0xffffffff)
1220 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1221 GEN_INT (ARM_SIGN_EXTEND (val
))));
1226 if (reload_completed
&& rtx_equal_p (target
, source
))
1229 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1238 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1241 if (remainder
== 0xffffffff)
1243 if (reload_completed
&& rtx_equal_p (target
, source
))
1246 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1255 if (reload_completed
&& rtx_equal_p (target
, source
))
1258 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1261 if (remainder
== 0xffffffff)
1264 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1265 gen_rtx_NOT (mode
, source
)));
1269 /* We don't know how to handle this yet below. */
1273 /* We treat MINUS as (val - source), since (source - val) is always
1274 passed as (source + (-val)). */
1278 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1279 gen_rtx_NEG (mode
, source
)));
1282 if (const_ok_for_arm (val
))
1285 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1286 gen_rtx_MINUS (mode
, GEN_INT (val
),
1298 /* If we can do it in one insn get out quickly. */
1299 if (const_ok_for_arm (val
)
1300 || (can_negate_initial
&& const_ok_for_arm (-val
))
1301 || (can_invert
&& const_ok_for_arm (~val
)))
1304 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1305 (source
? gen_rtx (code
, mode
, source
,
1311 /* Calculate a few attributes that may be useful for specific
1313 for (i
= 31; i
>= 0; i
--)
1315 if ((remainder
& (1 << i
)) == 0)
1316 clear_sign_bit_copies
++;
1321 for (i
= 31; i
>= 0; i
--)
1323 if ((remainder
& (1 << i
)) != 0)
1324 set_sign_bit_copies
++;
1329 for (i
= 0; i
<= 31; i
++)
1331 if ((remainder
& (1 << i
)) == 0)
1332 clear_zero_bit_copies
++;
1337 for (i
= 0; i
<= 31; i
++)
1339 if ((remainder
& (1 << i
)) != 0)
1340 set_zero_bit_copies
++;
1348 /* See if we can do this by sign_extending a constant that is known
1349 to be negative. This is a good, way of doing it, since the shift
1350 may well merge into a subsequent insn. */
1351 if (set_sign_bit_copies
> 1)
1353 if (const_ok_for_arm
1354 (temp1
= ARM_SIGN_EXTEND (remainder
1355 << (set_sign_bit_copies
- 1))))
1359 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1360 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1362 emit_insn (gen_ashrsi3 (target
, new_src
,
1363 GEN_INT (set_sign_bit_copies
- 1)));
1367 /* For an inverted constant, we will need to set the low bits,
1368 these will be shifted out of harm's way. */
1369 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1370 if (const_ok_for_arm (~temp1
))
1374 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1375 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1377 emit_insn (gen_ashrsi3 (target
, new_src
,
1378 GEN_INT (set_sign_bit_copies
- 1)));
1384 /* See if we can generate this by setting the bottom (or the top)
1385 16 bits, and then shifting these into the other half of the
1386 word. We only look for the simplest cases, to do more would cost
1387 too much. Be careful, however, not to generate this when the
1388 alternative would take fewer insns. */
1389 if (val
& 0xffff0000)
1391 temp1
= remainder
& 0xffff0000;
1392 temp2
= remainder
& 0x0000ffff;
1394 /* Overlaps outside this range are best done using other methods. */
1395 for (i
= 9; i
< 24; i
++)
1397 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1398 && !const_ok_for_arm (temp2
))
1400 rtx new_src
= (subtargets
1401 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1403 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1404 source
, subtargets
, generate
);
1407 emit_insn (gen_rtx_SET
1410 gen_rtx_ASHIFT (mode
, source
,
1417 /* Don't duplicate cases already considered. */
1418 for (i
= 17; i
< 24; i
++)
1420 if (((temp1
| (temp1
>> i
)) == remainder
)
1421 && !const_ok_for_arm (temp1
))
1423 rtx new_src
= (subtargets
1424 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1426 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1427 source
, subtargets
, generate
);
1431 (gen_rtx_SET (VOIDmode
, target
,
1434 gen_rtx_LSHIFTRT (mode
, source
,
1445 /* If we have IOR or XOR, and the constant can be loaded in a
1446 single instruction, and we can find a temporary to put it in,
1447 then this can be done in two instructions instead of 3-4. */
1449 /* TARGET can't be NULL if SUBTARGETS is 0 */
1450 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1452 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1456 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1458 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1459 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1460 gen_rtx (code
, mode
, source
, sub
)));
1469 if (set_sign_bit_copies
> 8
1470 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1474 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1475 rtx shift
= GEN_INT (set_sign_bit_copies
);
1477 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1479 gen_rtx_ASHIFT (mode
,
1482 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1484 gen_rtx_LSHIFTRT (mode
, sub
,
1490 if (set_zero_bit_copies
> 8
1491 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1495 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1496 rtx shift
= GEN_INT (set_zero_bit_copies
);
1498 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1500 gen_rtx_LSHIFTRT (mode
,
1503 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1505 gen_rtx_ASHIFT (mode
, sub
,
1511 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1515 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1516 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1517 gen_rtx_NOT (mode
, source
)));
1520 sub
= gen_reg_rtx (mode
);
1521 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1522 gen_rtx_AND (mode
, source
,
1524 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1525 gen_rtx_NOT (mode
, sub
)));
1532 /* See if two shifts will do 2 or more insn's worth of work. */
1533 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1535 HOST_WIDE_INT shift_mask
= ((0xffffffff
1536 << (32 - clear_sign_bit_copies
))
1539 if ((remainder
| shift_mask
) != 0xffffffff)
1543 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1544 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1545 new_src
, source
, subtargets
, 1);
1550 rtx targ
= subtargets
? NULL_RTX
: target
;
1551 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1552 targ
, source
, subtargets
, 0);
1558 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1559 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1561 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1562 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1568 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1570 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1572 if ((remainder
| shift_mask
) != 0xffffffff)
1576 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1578 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1579 new_src
, source
, subtargets
, 1);
1584 rtx targ
= subtargets
? NULL_RTX
: target
;
1586 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1587 targ
, source
, subtargets
, 0);
1593 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1594 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1596 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1597 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1609 for (i
= 0; i
< 32; i
++)
1610 if (remainder
& (1 << i
))
1613 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1614 remainder
= (~remainder
) & 0xffffffff;
1615 else if (code
== PLUS
&& num_bits_set
> 16)
1616 remainder
= (-remainder
) & 0xffffffff;
1623 /* Now try and find a way of doing the job in either two or three
1625 We start by looking for the largest block of zeros that are aligned on
1626 a 2-bit boundary, we then fill up the temps, wrapping around to the
1627 top of the word when we drop off the bottom.
1628 In the worst case this code should produce no more than four insns. */
1631 int best_consecutive_zeros
= 0;
1633 for (i
= 0; i
< 32; i
+= 2)
1635 int consecutive_zeros
= 0;
1637 if (!(remainder
& (3 << i
)))
1639 while ((i
< 32) && !(remainder
& (3 << i
)))
1641 consecutive_zeros
+= 2;
1644 if (consecutive_zeros
> best_consecutive_zeros
)
1646 best_consecutive_zeros
= consecutive_zeros
;
1647 best_start
= i
- consecutive_zeros
;
1653 /* So long as it won't require any more insns to do so, it's
1654 desirable to emit a small constant (in bits 0...9) in the last
1655 insn. This way there is more chance that it can be combined with
1656 a later addressing insn to form a pre-indexed load or store
1657 operation. Consider:
1659 *((volatile int *)0xe0000100) = 1;
1660 *((volatile int *)0xe0000110) = 2;
1662 We want this to wind up as:
1666 str rB, [rA, #0x100]
1668 str rB, [rA, #0x110]
1670 rather than having to synthesize both large constants from scratch.
1672 Therefore, we calculate how many insns would be required to emit
1673 the constant starting from `best_start', and also starting from
1674 zero (ie with bit 31 first to be output). If `best_start' doesn't
1675 yield a shorter sequence, we may as well use zero. */
1677 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1678 && (count_insns_for_constant (remainder
, 0) <=
1679 count_insns_for_constant (remainder
, best_start
)))
1682 /* Now start emitting the insns. */
1690 if (remainder
& (3 << (i
- 2)))
1695 temp1
= remainder
& ((0x0ff << end
)
1696 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1697 remainder
&= ~temp1
;
1701 rtx new_src
, temp1_rtx
;
1703 if (code
== SET
|| code
== MINUS
)
1705 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1706 if (can_invert
&& code
!= MINUS
)
1711 if (remainder
&& subtargets
)
1712 new_src
= gen_reg_rtx (mode
);
1717 else if (can_negate
)
1721 temp1
= trunc_int_for_mode (temp1
, mode
);
1722 temp1_rtx
= GEN_INT (temp1
);
1726 else if (code
== MINUS
)
1727 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1729 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1731 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1740 else if (code
== MINUS
)
1754 /* Canonicalize a comparison so that we are more likely to recognize it.
1755 This can be done for a few constant compares, where we can make the
1756 immediate value easier to load. */
1759 arm_canonicalize_comparison (code
, op1
)
1763 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1773 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1774 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1776 *op1
= GEN_INT (i
+ 1);
1777 return code
== GT
? GE
: LT
;
1783 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1784 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1786 *op1
= GEN_INT (i
- 1);
1787 return code
== GE
? GT
: LE
;
1793 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1794 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1796 *op1
= GEN_INT (i
+ 1);
1797 return code
== GTU
? GEU
: LTU
;
1804 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1806 *op1
= GEN_INT (i
- 1);
1807 return code
== GEU
? GTU
: LEU
;
1818 /* Decide whether a type should be returned in memory (true)
1819 or in a register (false). This is called by the macro
1820 RETURN_IN_MEMORY. */
1823 arm_return_in_memory (type
)
1828 if (!AGGREGATE_TYPE_P (type
))
1829 /* All simple types are returned in registers. */
1832 size
= int_size_in_bytes (type
);
1836 /* ATPCS returns aggregate types in memory only if they are
1837 larger than a word (or are variable size). */
1838 return (size
< 0 || size
> UNITS_PER_WORD
);
1841 /* For the arm-wince targets we choose to be compatible with Microsoft's
1842 ARM and Thumb compilers, which always return aggregates in memory. */
1844 /* All structures/unions bigger than one word are returned in memory.
1845 Also catch the case where int_size_in_bytes returns -1. In this case
1846 the aggregate is either huge or of variable size, and in either case
1847 we will want to return it via memory and not in a register. */
1848 if (size
< 0 || size
> UNITS_PER_WORD
)
1851 if (TREE_CODE (type
) == RECORD_TYPE
)
1855 /* For a struct the APCS says that we only return in a register
1856 if the type is 'integer like' and every addressable element
1857 has an offset of zero. For practical purposes this means
1858 that the structure can have at most one non bit-field element
1859 and that this element must be the first one in the structure. */
1861 /* Find the first field, ignoring non FIELD_DECL things which will
1862 have been created by C++. */
1863 for (field
= TYPE_FIELDS (type
);
1864 field
&& TREE_CODE (field
) != FIELD_DECL
;
1865 field
= TREE_CHAIN (field
))
1869 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1871 /* Check that the first field is valid for returning in a register. */
1873 /* ... Floats are not allowed */
1874 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1877 /* ... Aggregates that are not themselves valid for returning in
1878 a register are not allowed. */
1879 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1882 /* Now check the remaining fields, if any. Only bitfields are allowed,
1883 since they are not addressable. */
1884 for (field
= TREE_CHAIN (field
);
1886 field
= TREE_CHAIN (field
))
1888 if (TREE_CODE (field
) != FIELD_DECL
)
1891 if (!DECL_BIT_FIELD_TYPE (field
))
1898 if (TREE_CODE (type
) == UNION_TYPE
)
1902 /* Unions can be returned in registers if every element is
1903 integral, or can be returned in an integer register. */
1904 for (field
= TYPE_FIELDS (type
);
1906 field
= TREE_CHAIN (field
))
1908 if (TREE_CODE (field
) != FIELD_DECL
)
1911 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1914 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1920 #endif /* not ARM_WINCE */
1922 /* Return all other types in memory. */
1926 /* Indicate whether or not words of a double are in big-endian order. */
1929 arm_float_words_big_endian ()
1934 /* For FPA, float words are always big-endian. For VFP, floats words
1935 follow the memory system mode. */
1937 if (TARGET_HARD_FLOAT
)
1939 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1944 return (TARGET_BIG_END
? 1 : 0);
1949 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1950 for a call to a function whose data type is FNTYPE.
1951 For a library call, FNTYPE is NULL. */
1953 arm_init_cumulative_args (pcum
, fntype
, libname
, fndecl
)
1954 CUMULATIVE_ARGS
* pcum
;
1956 rtx libname ATTRIBUTE_UNUSED
;
1957 tree fndecl ATTRIBUTE_UNUSED
;
1959 /* On the ARM, the offset starts at 0. */
1960 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
))) ? 1 : 0);
1962 pcum
->call_cookie
= CALL_NORMAL
;
1964 if (TARGET_LONG_CALLS
)
1965 pcum
->call_cookie
= CALL_LONG
;
1967 /* Check for long call/short call attributes. The attributes
1968 override any command line option. */
1971 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1972 pcum
->call_cookie
= CALL_SHORT
;
1973 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1974 pcum
->call_cookie
= CALL_LONG
;
1978 /* Determine where to put an argument to a function.
1979 Value is zero to push the argument on the stack,
1980 or a hard register in which to store the argument.
1982 MODE is the argument's machine mode.
1983 TYPE is the data type of the argument (as a tree).
1984 This is null for libcalls where that information may
1986 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1987 the preceding args and about the function being called.
1988 NAMED is nonzero if this argument is a named parameter
1989 (otherwise it is an extra parameter matching an ellipsis). */
1992 arm_function_arg (pcum
, mode
, type
, named
)
1993 CUMULATIVE_ARGS
* pcum
;
1994 enum machine_mode mode
;
1995 tree type ATTRIBUTE_UNUSED
;
1998 if (mode
== VOIDmode
)
1999 /* Compute operand 2 of the call insn. */
2000 return GEN_INT (pcum
->call_cookie
);
2002 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
2005 return gen_rtx_REG (mode
, pcum
->nregs
);
2008 /* Variable sized types are passed by reference. This is a GCC
2009 extension to the ARM ABI. */
2012 arm_function_arg_pass_by_reference (cum
, mode
, type
, named
)
2013 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
2014 enum machine_mode mode ATTRIBUTE_UNUSED
;
2016 int named ATTRIBUTE_UNUSED
;
2018 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2021 /* Implement va_arg. */
2024 arm_va_arg (valist
, type
)
2027 /* Variable sized types are passed by reference. */
2028 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
2030 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
2031 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
2034 return std_expand_builtin_va_arg (valist
, type
);
2037 /* Encode the current state of the #pragma [no_]long_calls. */
2040 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2041 LONG
, /* #pragma long_calls is in effect. */
2042 SHORT
/* #pragma no_long_calls is in effect. */
2045 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2048 arm_pr_long_calls (pfile
)
2049 struct cpp_reader
* pfile ATTRIBUTE_UNUSED
;
2051 arm_pragma_long_calls
= LONG
;
2055 arm_pr_no_long_calls (pfile
)
2056 struct cpp_reader
* pfile ATTRIBUTE_UNUSED
;
2058 arm_pragma_long_calls
= SHORT
;
2062 arm_pr_long_calls_off (pfile
)
2063 struct cpp_reader
* pfile ATTRIBUTE_UNUSED
;
2065 arm_pragma_long_calls
= OFF
;
2068 /* Table of machine attributes. */
2069 const struct attribute_spec arm_attribute_table
[] =
2071 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2072 /* Function calls made to this symbol must be done indirectly, because
2073 it may lie outside of the 26 bit addressing range of a normal function
2075 { "long_call", 0, 0, false, true, true, NULL
},
2076 /* Whereas these functions are always known to reside within the 26 bit
2077 addressing range. */
2078 { "short_call", 0, 0, false, true, true, NULL
},
2079 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2080 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2081 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2082 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2084 /* ARM/PE has three new attributes:
2086 dllexport - for exporting a function/variable that will live in a dll
2087 dllimport - for importing a function/variable from a dll
2089 Microsoft allows multiple declspecs in one __declspec, separating
2090 them with spaces. We do NOT support this. Instead, use __declspec
2093 { "dllimport", 0, 0, true, false, false, NULL
},
2094 { "dllexport", 0, 0, true, false, false, NULL
},
2095 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2097 { NULL
, 0, 0, false, false, false, NULL
}
2100 /* Handle an attribute requiring a FUNCTION_DECL;
2101 arguments as in struct attribute_spec.handler. */
2104 arm_handle_fndecl_attribute (node
, name
, args
, flags
, no_add_attrs
)
2107 tree args ATTRIBUTE_UNUSED
;
2108 int flags ATTRIBUTE_UNUSED
;
2109 bool * no_add_attrs
;
2111 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2113 warning ("`%s' attribute only applies to functions",
2114 IDENTIFIER_POINTER (name
));
2115 *no_add_attrs
= true;
2121 /* Handle an "interrupt" or "isr" attribute;
2122 arguments as in struct attribute_spec.handler. */
2125 arm_handle_isr_attribute (node
, name
, args
, flags
, no_add_attrs
)
2130 bool * no_add_attrs
;
2134 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2136 warning ("`%s' attribute only applies to functions",
2137 IDENTIFIER_POINTER (name
));
2138 *no_add_attrs
= true;
2140 /* FIXME: the argument if any is checked for type attributes;
2141 should it be checked for decl ones? */
2145 if (TREE_CODE (*node
) == FUNCTION_TYPE
2146 || TREE_CODE (*node
) == METHOD_TYPE
)
2148 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2150 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2151 *no_add_attrs
= true;
2154 else if (TREE_CODE (*node
) == POINTER_TYPE
2155 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2156 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2157 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2159 *node
= build_type_copy (*node
);
2160 TREE_TYPE (*node
) = build_type_attribute_variant
2162 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2163 *no_add_attrs
= true;
2167 /* Possibly pass this attribute on from the type to a decl. */
2168 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2169 | (int) ATTR_FLAG_FUNCTION_NEXT
2170 | (int) ATTR_FLAG_ARRAY_NEXT
))
2172 *no_add_attrs
= true;
2173 return tree_cons (name
, args
, NULL_TREE
);
2177 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2185 /* Return 0 if the attributes for two types are incompatible, 1 if they
2186 are compatible, and 2 if they are nearly compatible (which causes a
2187 warning to be generated). */
2190 arm_comp_type_attributes (type1
, type2
)
2196 /* Check for mismatch of non-default calling convention. */
2197 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2200 /* Check for mismatched call attributes. */
2201 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2202 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2203 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2204 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2206 /* Only bother to check if an attribute is defined. */
2207 if (l1
| l2
| s1
| s2
)
2209 /* If one type has an attribute, the other must have the same attribute. */
2210 if ((l1
!= l2
) || (s1
!= s2
))
2213 /* Disallow mixed attributes. */
2214 if ((l1
& s2
) || (l2
& s1
))
2218 /* Check for mismatched ISR attribute. */
2219 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2221 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2222 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2224 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2231 /* Encode long_call or short_call attribute by prefixing
2232 symbol name in DECL with a special character FLAG. */
2235 arm_encode_call_attribute (decl
, flag
)
2239 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2240 int len
= strlen (str
);
2243 /* Do not allow weak functions to be treated as short call. */
2244 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2247 newstr
= alloca (len
+ 2);
2249 strcpy (newstr
+ 1, str
);
2251 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2252 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2255 /* Assigns default attributes to newly defined type. This is used to
2256 set short_call/long_call attributes for function types of
2257 functions defined inside corresponding #pragma scopes. */
2260 arm_set_default_type_attributes (type
)
2263 /* Add __attribute__ ((long_call)) to all functions, when
2264 inside #pragma long_calls or __attribute__ ((short_call)),
2265 when inside #pragma no_long_calls. */
2266 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2268 tree type_attr_list
, attr_name
;
2269 type_attr_list
= TYPE_ATTRIBUTES (type
);
2271 if (arm_pragma_long_calls
== LONG
)
2272 attr_name
= get_identifier ("long_call");
2273 else if (arm_pragma_long_calls
== SHORT
)
2274 attr_name
= get_identifier ("short_call");
2278 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2279 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2283 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2284 defined within the current compilation unit. If this cannot be
2285 determined, then 0 is returned. */
2288 current_file_function_operand (sym_ref
)
2291 /* This is a bit of a fib. A function will have a short call flag
2292 applied to its name if it has the short call attribute, or it has
2293 already been defined within the current compilation unit. */
2294 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2297 /* The current function is always defined within the current compilation
2298 unit. if it s a weak definition however, then this may not be the real
2299 definition of the function, and so we have to say no. */
2300 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2301 && !DECL_WEAK (current_function_decl
))
2304 /* We cannot make the determination - default to returning 0. */
2308 /* Return nonzero if a 32 bit "long_call" should be generated for
2309 this call. We generate a long_call if the function:
2311 a. has an __attribute__((long call))
2312 or b. is within the scope of a #pragma long_calls
2313 or c. the -mlong-calls command line switch has been specified
2315 However we do not generate a long call if the function:
2317 d. has an __attribute__ ((short_call))
2318 or e. is inside the scope of a #pragma no_long_calls
2319 or f. has an __attribute__ ((section))
2320 or g. is defined within the current compilation unit.
2322 This function will be called by C fragments contained in the machine
2323 description file. CALL_REF and CALL_COOKIE correspond to the matched
2324 rtl operands. CALL_SYMBOL is used to distinguish between
2325 two different callers of the function. It is set to 1 in the
2326 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2327 and "call_value" patterns. This is because of the difference in the
2328 SYM_REFs passed by these patterns. */
2331 arm_is_longcall_p (sym_ref
, call_cookie
, call_symbol
)
2338 if (GET_CODE (sym_ref
) != MEM
)
2341 sym_ref
= XEXP (sym_ref
, 0);
2344 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2347 if (call_cookie
& CALL_SHORT
)
2350 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2353 if (current_file_function_operand (sym_ref
))
2356 return (call_cookie
& CALL_LONG
)
2357 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2358 || TARGET_LONG_CALLS
;
2361 /* Return nonzero if it is ok to make a tail-call to DECL. */
2364 arm_function_ok_for_sibcall (decl
, exp
)
2366 tree exp ATTRIBUTE_UNUSED
;
2368 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2370 /* Never tailcall something for which we have no decl, or if we
2371 are in Thumb mode. */
2372 if (decl
== NULL
|| TARGET_THUMB
)
2375 /* Get the calling method. */
2376 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2377 call_type
= CALL_SHORT
;
2378 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2379 call_type
= CALL_LONG
;
2381 /* Cannot tail-call to long calls, since these are out of range of
2382 a branch instruction. However, if not compiling PIC, we know
2383 we can reach the symbol if it is in this compilation unit. */
2384 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2387 /* If we are interworking and the function is not declared static
2388 then we can't tail-call it unless we know that it exists in this
2389 compilation unit (since it might be a Thumb routine). */
2390 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2393 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2394 if (IS_INTERRUPT (arm_current_func_type ()))
2397 /* Everything else is ok. */
2402 /* Addressing mode support functions. */
2404 /* Return non-zero if X is a legitimate immediate operand when compiling
2407 legitimate_pic_operand_p (x
)
2412 && (GET_CODE (x
) == SYMBOL_REF
2413 || (GET_CODE (x
) == CONST
2414 && GET_CODE (XEXP (x
, 0)) == PLUS
2415 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2422 legitimize_pic_address (orig
, mode
, reg
)
2424 enum machine_mode mode
;
2427 if (GET_CODE (orig
) == SYMBOL_REF
2428 || GET_CODE (orig
) == LABEL_REF
)
2430 #ifndef AOF_ASSEMBLER
2431 rtx pic_ref
, address
;
2441 reg
= gen_reg_rtx (Pmode
);
2446 #ifdef AOF_ASSEMBLER
2447 /* The AOF assembler can generate relocations for these directly, and
2448 understands that the PIC register has to be added into the offset. */
2449 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2452 address
= gen_reg_rtx (Pmode
);
2457 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2459 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2461 if ((GET_CODE (orig
) == LABEL_REF
2462 || (GET_CODE (orig
) == SYMBOL_REF
&&
2463 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig
, 0))))
2465 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2468 pic_ref
= gen_rtx_MEM (Pmode
,
2469 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2471 RTX_UNCHANGING_P (pic_ref
) = 1;
2474 insn
= emit_move_insn (reg
, pic_ref
);
2476 current_function_uses_pic_offset_table
= 1;
2477 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2479 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2483 else if (GET_CODE (orig
) == CONST
)
2487 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2488 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2496 reg
= gen_reg_rtx (Pmode
);
2499 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2501 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2502 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2503 base
== reg
? 0 : reg
);
2508 if (GET_CODE (offset
) == CONST_INT
)
2510 /* The base register doesn't really matter, we only want to
2511 test the index for the appropriate mode. */
2512 if (!arm_legitimate_index_p (mode
, offset
, 0))
2514 if (!no_new_pseudos
)
2515 offset
= force_reg (Pmode
, offset
);
2520 if (GET_CODE (offset
) == CONST_INT
)
2521 return plus_constant (base
, INTVAL (offset
));
2524 if (GET_MODE_SIZE (mode
) > 4
2525 && (GET_MODE_CLASS (mode
) == MODE_INT
2526 || TARGET_SOFT_FLOAT
))
2528 emit_insn (gen_addsi3 (reg
, base
, offset
));
2532 return gen_rtx_PLUS (Pmode
, base
, offset
);
2538 /* Generate code to load the PIC register. PROLOGUE is true if
2539 called from arm_expand_prologue (in which case we want the
2540 generated insns at the start of the function); false if called
2541 by an exception receiver that needs the PIC register reloaded
2542 (in which case the insns are just dumped at the current location). */
2545 arm_finalize_pic (prologue
)
2546 int prologue ATTRIBUTE_UNUSED
;
2548 #ifndef AOF_ASSEMBLER
2549 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2550 rtx global_offset_table
;
2552 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2559 l1
= gen_label_rtx ();
2561 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2562 /* On the ARM the PC register contains 'dot + 8' at the time of the
2563 addition, on the Thumb it is 'dot + 4'. */
2564 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2566 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2567 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2569 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2571 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2575 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2576 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2580 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2581 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2587 emit_insn_after (seq
, get_insns ());
2591 /* Need to emit this whether or not we obey regdecls,
2592 since setjmp/longjmp can cause life info to screw up. */
2593 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2594 #endif /* AOF_ASSEMBLER */
2597 /* Return nonzero if X is valid as an ARM state addressing register. */
2599 arm_address_register_rtx_p (x
, strict_p
)
2605 if (GET_CODE (x
) != REG
)
2611 return ARM_REGNO_OK_FOR_BASE_P (regno
);
2613 return (regno
<= LAST_ARM_REGNUM
2614 || regno
>= FIRST_PSEUDO_REGISTER
2615 || regno
== FRAME_POINTER_REGNUM
2616 || regno
== ARG_POINTER_REGNUM
);
2619 /* Return nonzero if X is a valid ARM state address operand. */
2621 arm_legitimate_address_p (mode
, x
, strict_p
)
2622 enum machine_mode mode
;
2626 if (arm_address_register_rtx_p (x
, strict_p
))
2629 else if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
2630 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
2632 else if ((GET_CODE (x
) == POST_MODIFY
|| GET_CODE (x
) == PRE_MODIFY
)
2633 && GET_MODE_SIZE (mode
) <= 4
2634 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2635 && GET_CODE (XEXP (x
, 1)) == PLUS
2636 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2637 return arm_legitimate_index_p (mode
, XEXP (XEXP (x
, 1), 1), strict_p
);
2639 /* After reload constants split into minipools will have addresses
2640 from a LABEL_REF. */
2641 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2642 && (GET_CODE (x
) == LABEL_REF
2643 || (GET_CODE (x
) == CONST
2644 && GET_CODE (XEXP (x
, 0)) == PLUS
2645 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2646 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2649 else if (mode
== TImode
)
2652 else if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2654 if (GET_CODE (x
) == PLUS
2655 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2656 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2658 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2660 if (val
== 4 || val
== -4 || val
== -8)
2665 else if (GET_CODE (x
) == PLUS
)
2667 rtx xop0
= XEXP (x
, 0);
2668 rtx xop1
= XEXP (x
, 1);
2670 return ((arm_address_register_rtx_p (xop0
, strict_p
)
2671 && arm_legitimate_index_p (mode
, xop1
, strict_p
))
2672 || (arm_address_register_rtx_p (xop1
, strict_p
)
2673 && arm_legitimate_index_p (mode
, xop0
, strict_p
)));
2677 /* Reload currently can't handle MINUS, so disable this for now */
2678 else if (GET_CODE (x
) == MINUS
)
2680 rtx xop0
= XEXP (x
, 0);
2681 rtx xop1
= XEXP (x
, 1);
2683 return (arm_address_register_rtx_p (xop0
, strict_p
)
2684 && arm_legitimate_index_p (mode
, xop1
, strict_p
));
2688 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2689 && GET_CODE (x
) == SYMBOL_REF
2690 && CONSTANT_POOL_ADDRESS_P (x
)
2692 && symbol_mentioned_p (get_pool_constant (x
))))
2695 else if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_DEC
)
2696 && (GET_MODE_SIZE (mode
) <= 4)
2697 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
))
2703 /* Return nonzero if INDEX is valid for an address index operand in
2706 arm_legitimate_index_p (mode
, index
, strict_p
)
2707 enum machine_mode mode
;
2711 HOST_WIDE_INT range
;
2712 enum rtx_code code
= GET_CODE (index
);
2714 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2715 return (code
== CONST_INT
&& INTVAL (index
) < 1024
2716 && INTVAL (index
) > -1024
2717 && (INTVAL (index
) & 3) == 0);
2720 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
|| mode
== DImode
))
2721 return (code
== CONST_INT
2722 && INTVAL (index
) < 255
2723 && INTVAL (index
) > -255);
2725 if (arm_address_register_rtx_p (index
, strict_p
)
2726 && GET_MODE_SIZE (mode
) <= 4)
2729 /* XXX What about ldrsb? */
2730 if (GET_MODE_SIZE (mode
) <= 4 && code
== MULT
2731 && (!arm_arch4
|| (mode
) != HImode
))
2733 rtx xiop0
= XEXP (index
, 0);
2734 rtx xiop1
= XEXP (index
, 1);
2736 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
2737 && power_of_two_operand (xiop1
, SImode
))
2738 || (arm_address_register_rtx_p (xiop1
, strict_p
)
2739 && power_of_two_operand (xiop0
, SImode
)));
2742 if (GET_MODE_SIZE (mode
) <= 4
2743 && (code
== LSHIFTRT
|| code
== ASHIFTRT
2744 || code
== ASHIFT
|| code
== ROTATERT
)
2745 && (!arm_arch4
|| (mode
) != HImode
))
2747 rtx op
= XEXP (index
, 1);
2749 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
2750 && GET_CODE (op
) == CONST_INT
2752 && INTVAL (op
) <= 31);
2755 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2756 load, but that has a restricted addressing range and we are unable
2757 to tell here whether that is the case. To be safe we restrict all
2758 loads to that range. */
2759 range
= ((mode
) == HImode
|| (mode
) == QImode
)
2760 ? (arm_arch4
? 256 : 4095) : 4096;
2762 return (code
== CONST_INT
2763 && INTVAL (index
) < range
2764 && INTVAL (index
) > -range
);
2767 /* Return nonzero if X is valid as an ARM state addressing register. */
2769 thumb_base_register_rtx_p (x
, mode
, strict_p
)
2771 enum machine_mode mode
;
2776 if (GET_CODE (x
) != REG
)
2782 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
2784 return (regno
<= LAST_LO_REGNUM
2785 || regno
>= FIRST_PSEUDO_REGISTER
2786 || regno
== FRAME_POINTER_REGNUM
2787 || (GET_MODE_SIZE (mode
) >= 4
2788 && (regno
== STACK_POINTER_REGNUM
2789 || x
== hard_frame_pointer_rtx
2790 || x
== arg_pointer_rtx
)));
2793 /* Return nonzero if x is a legitimate index register. This is the case
2794 for any base register that can access a QImode object. */
2796 thumb_index_register_rtx_p (x
, strict_p
)
2800 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
2803 /* Return nonzero if x is a legitimate Thumb-state address.
2805 The AP may be eliminated to either the SP or the FP, so we use the
2806 least common denominator, e.g. SImode, and offsets from 0 to 64.
2808 ??? Verify whether the above is the right approach.
2810 ??? Also, the FP may be eliminated to the SP, so perhaps that
2811 needs special handling also.
2813 ??? Look at how the mips16 port solves this problem. It probably uses
2814 better ways to solve some of these problems.
2816 Although it is not incorrect, we don't accept QImode and HImode
2817 addresses based on the frame pointer or arg pointer until the
2818 reload pass starts. This is so that eliminating such addresses
2819 into stack based ones won't produce impossible code. */
2821 thumb_legitimate_address_p (mode
, x
, strict_p
)
2822 enum machine_mode mode
;
2826 /* ??? Not clear if this is right. Experiment. */
2827 if (GET_MODE_SIZE (mode
) < 4
2828 && !(reload_in_progress
|| reload_completed
)
2829 && (reg_mentioned_p (frame_pointer_rtx
, x
)
2830 || reg_mentioned_p (arg_pointer_rtx
, x
)
2831 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
2832 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
2833 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
2834 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
2837 /* Accept any base register. SP only in SImode or larger. */
2838 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
2841 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */
2842 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
2843 && GET_CODE (x
) == SYMBOL_REF
2844 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
2847 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */
2848 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2849 && (GET_CODE (x
) == LABEL_REF
2850 || (GET_CODE (x
) == CONST
2851 && GET_CODE (XEXP (x
, 0)) == PLUS
2852 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2853 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2856 /* Post-inc indexing only supported for SImode and larger. */
2857 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
2858 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
2861 else if (GET_CODE (x
) == PLUS
)
2863 /* REG+REG address can be any two index registers. */
2864 /* We disallow FRAME+REG addressing since we know that FRAME
2865 will be replaced with STACK, and SP relative addressing only
2866 permits SP+OFFSET. */
2867 if (GET_MODE_SIZE (mode
) <= 4
2868 && XEXP (x
, 0) != frame_pointer_rtx
2869 && XEXP (x
, 1) != frame_pointer_rtx
2870 && XEXP (x
, 0) != virtual_stack_vars_rtx
2871 && XEXP (x
, 1) != virtual_stack_vars_rtx
2872 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2873 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
2876 /* REG+const has 5-7 bit offset for non-SP registers. */
2877 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2878 || XEXP (x
, 0) == arg_pointer_rtx
)
2879 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2880 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
2883 /* REG+const has 10 bit offset for SP, but only SImode and
2884 larger is supported. */
2885 /* ??? Should probably check for DI/DFmode overflow here
2886 just like GO_IF_LEGITIMATE_OFFSET does. */
2887 else if (GET_CODE (XEXP (x
, 0)) == REG
2888 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
2889 && GET_MODE_SIZE (mode
) >= 4
2890 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2891 && INTVAL (XEXP (x
, 1)) >= 0
2892 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
2893 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2896 else if (GET_CODE (XEXP (x
, 0)) == REG
2897 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
2898 && GET_MODE_SIZE (mode
) >= 4
2899 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2900 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2904 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2905 && GET_CODE (x
) == SYMBOL_REF
2906 && CONSTANT_POOL_ADDRESS_P (x
)
2908 && symbol_mentioned_p (get_pool_constant (x
))))
2914 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
2915 instruction of mode MODE. */
2917 thumb_legitimate_offset_p (mode
, val
)
2918 enum machine_mode mode
;
2921 switch (GET_MODE_SIZE (mode
))
2924 return val
>= 0 && val
< 32;
2927 return val
>= 0 && val
< 64 && (val
& 1) == 0;
2931 && (val
+ GET_MODE_SIZE (mode
)) <= 128
2936 /* Try machine-dependent ways of modifying an illegitimate address
2937 to be legitimate. If we find one, return the new, valid address. */
2940 arm_legitimize_address (x
, orig_x
, mode
)
2943 enum machine_mode mode
;
2945 if (GET_CODE (x
) == PLUS
)
2947 rtx xop0
= XEXP (x
, 0);
2948 rtx xop1
= XEXP (x
, 1);
2950 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
2951 xop0
= force_reg (SImode
, xop0
);
2953 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
2954 xop1
= force_reg (SImode
, xop1
);
2956 if (ARM_BASE_REGISTER_RTX_P (xop0
)
2957 && GET_CODE (xop1
) == CONST_INT
)
2959 HOST_WIDE_INT n
, low_n
;
2963 if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2975 low_n
= ((mode
) == TImode
? 0
2976 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
2980 base_reg
= gen_reg_rtx (SImode
);
2981 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
2982 GEN_INT (n
)), NULL_RTX
);
2983 emit_move_insn (base_reg
, val
);
2984 x
= (low_n
== 0 ? base_reg
2985 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
2987 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
2988 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
2991 /* XXX We don't allow MINUS any more -- see comment in
2992 arm_legitimate_address_p (). */
2993 else if (GET_CODE (x
) == MINUS
)
2995 rtx xop0
= XEXP (x
, 0);
2996 rtx xop1
= XEXP (x
, 1);
2998 if (CONSTANT_P (xop0
))
2999 xop0
= force_reg (SImode
, xop0
);
3001 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3002 xop1
= force_reg (SImode
, xop1
);
3004 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3005 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3010 /* We need to find and carefully transform any SYMBOL and LABEL
3011 references; so go back to the original address expression. */
3012 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3014 if (new_x
!= orig_x
)
3023 #define REG_OR_SUBREG_REG(X) \
3024 (GET_CODE (X) == REG \
3025 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3027 #define REG_OR_SUBREG_RTX(X) \
3028 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3030 #ifndef COSTS_N_INSNS
3031 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3035 arm_rtx_costs_1 (x
, code
, outer
)
3038 enum rtx_code outer
;
3040 enum machine_mode mode
= GET_MODE (x
);
3041 enum rtx_code subcode
;
3057 return COSTS_N_INSNS (1);
3060 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3063 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3070 return COSTS_N_INSNS (2) + cycles
;
3072 return COSTS_N_INSNS (1) + 16;
3075 return (COSTS_N_INSNS (1)
3076 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3077 + GET_CODE (SET_DEST (x
)) == MEM
));
3082 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3084 if (thumb_shiftable_const (INTVAL (x
)))
3085 return COSTS_N_INSNS (2);
3086 return COSTS_N_INSNS (3);
3088 else if (outer
== PLUS
3089 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3091 else if (outer
== COMPARE
3092 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3094 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3095 || outer
== LSHIFTRT
)
3097 return COSTS_N_INSNS (2);
3103 return COSTS_N_INSNS (3);
3122 /* XXX another guess. */
3123 /* Memory costs quite a lot for the first word, but subsequent words
3124 load at the equivalent of a single insn each. */
3125 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3126 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3131 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3136 /* XXX still guessing. */
3137 switch (GET_MODE (XEXP (x
, 0)))
3140 return (1 + (mode
== DImode
? 4 : 0)
3141 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3144 return (4 + (mode
== DImode
? 4 : 0)
3145 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3148 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3162 fprintf (stderr
, "unexpected code for thumb in rtx_costs: %s\n",
3172 /* Memory costs quite a lot for the first word, but subsequent words
3173 load at the equivalent of a single insn each. */
3174 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3175 + (GET_CODE (x
) == SYMBOL_REF
3176 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3183 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3190 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3192 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3193 + ((GET_CODE (XEXP (x
, 0)) == REG
3194 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3195 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3197 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3198 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3199 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3201 + ((GET_CODE (XEXP (x
, 1)) == REG
3202 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3203 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3204 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3209 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3210 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3211 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3212 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3215 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3216 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3217 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3218 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3220 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3221 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3222 && const_double_rtx_ok_for_fpa (XEXP (x
, 0))))
3225 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3226 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3227 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3228 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3229 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3230 || subcode
== ROTATE
|| subcode
== ROTATERT
3232 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3233 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3234 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3235 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3236 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3237 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3238 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3243 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3244 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3245 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3246 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3247 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3251 case AND
: case XOR
: case IOR
:
3254 /* Normally the frame registers will be spilt into reg+const during
3255 reload, so it is a bad idea to combine them with other instructions,
3256 since then they might not be moved outside of loops. As a compromise
3257 we allow integration with ops that have a constant as their second
3259 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3260 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3261 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3262 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3263 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3267 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3268 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3269 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3270 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3273 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3274 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3275 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3276 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3277 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3280 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3281 return (1 + extra_cost
3282 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3283 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3284 || subcode
== ROTATE
|| subcode
== ROTATERT
3286 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3287 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3288 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3289 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3290 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3291 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3297 /* There is no point basing this on the tuning, since it is always the
3298 fast variant if it exists at all. */
3299 if (arm_fast_multiply
&& mode
== DImode
3300 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3301 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3302 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3305 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3309 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3311 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3312 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3313 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
3316 /* Tune as appropriate. */
3317 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
3319 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3321 i
>>= booth_unit_size
;
3328 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
3329 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3330 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
3333 if (arm_fast_multiply
&& mode
== SImode
3334 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3335 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3336 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3337 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3338 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3339 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3344 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3345 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3349 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3351 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3354 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3362 return 4 + (mode
== DImode
? 4 : 0);
3365 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3366 return (4 + (mode
== DImode
? 4 : 0)
3367 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3370 switch (GET_MODE (XEXP (x
, 0)))
3373 return (1 + (mode
== DImode
? 4 : 0)
3374 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3377 return (4 + (mode
== DImode
? 4 : 0)
3378 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3381 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3389 if (const_ok_for_arm (INTVAL (x
)))
3390 return outer
== SET
? 2 : -1;
3391 else if (outer
== AND
3392 && const_ok_for_arm (~INTVAL (x
)))
3394 else if ((outer
== COMPARE
3395 || outer
== PLUS
|| outer
== MINUS
)
3396 && const_ok_for_arm (-INTVAL (x
)))
3407 if (const_double_rtx_ok_for_fpa (x
))
3408 return outer
== SET
? 2 : -1;
3409 else if ((outer
== COMPARE
|| outer
== PLUS
)
3410 && neg_const_double_rtx_ok_for_fpa (x
))
3420 arm_rtx_costs (x
, code
, outer_code
, total
)
3422 int code
, outer_code
;
3425 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3429 /* All address computations that can be done are free, but rtx cost returns
3430 the same for practically all of them. So we weight the different types
3431 of address here in the order (most pref first):
3432 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3435 arm_address_cost (X
)
3438 #define ARM_ADDRESS_COST(X) \
3439 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
3440 || GET_CODE (X) == SYMBOL_REF) \
3442 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
3443 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
3445 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
3446 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
3447 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
3448 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
3449 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
3450 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
3454 #define THUMB_ADDRESS_COST(X) \
3455 ((GET_CODE (X) == REG \
3456 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
3457 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
3460 return (TARGET_ARM
? ARM_ADDRESS_COST (X
) : THUMB_ADDRESS_COST (X
));
3464 arm_adjust_cost (insn
, link
, dep
, cost
)
3472 /* Some true dependencies can have a higher cost depending
3473 on precisely how certain input operands are used. */
3475 && REG_NOTE_KIND (link
) == 0
3476 && recog_memoized (insn
) >= 0
3477 && recog_memoized (dep
) >= 0)
3479 int shift_opnum
= get_attr_shift (insn
);
3480 enum attr_type attr_type
= get_attr_type (dep
);
3482 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3483 operand for INSN. If we have a shifted input operand and the
3484 instruction we depend on is another ALU instruction, then we may
3485 have to account for an additional stall. */
3486 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
3488 rtx shifted_operand
;
3491 /* Get the shifted operand. */
3492 extract_insn (insn
);
3493 shifted_operand
= recog_data
.operand
[shift_opnum
];
3495 /* Iterate over all the operands in DEP. If we write an operand
3496 that overlaps with SHIFTED_OPERAND, then we have increase the
3497 cost of this dependency. */
3499 preprocess_constraints ();
3500 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
3502 /* We can ignore strict inputs. */
3503 if (recog_data
.operand_type
[opno
] == OP_IN
)
3506 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
3513 /* XXX This is not strictly true for the FPA. */
3514 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
3515 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3518 /* Call insns don't incur a stall, even if they follow a load. */
3519 if (REG_NOTE_KIND (link
) == 0
3520 && GET_CODE (insn
) == CALL_INSN
)
3523 if ((i_pat
= single_set (insn
)) != NULL
3524 && GET_CODE (SET_SRC (i_pat
)) == MEM
3525 && (d_pat
= single_set (dep
)) != NULL
3526 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
3528 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
3529 /* This is a load after a store, there is no conflict if the load reads
3530 from a cached area. Assume that loads from the stack, and from the
3531 constant pool are cached, and that others will miss. This is a
3534 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
3535 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
3536 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
3537 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
3544 /* This code has been fixed for cross compilation. */
3546 static int fpa_consts_inited
= 0;
3548 static const char * const strings_fpa
[8] =
3551 "4", "5", "0.5", "10"
3554 static REAL_VALUE_TYPE values_fpa
[8];
3562 for (i
= 0; i
< 8; i
++)
3564 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
3568 fpa_consts_inited
= 1;
3571 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3574 const_double_rtx_ok_for_fpa (x
)
3580 if (!fpa_consts_inited
)
3583 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3584 if (REAL_VALUE_MINUS_ZERO (r
))
3587 for (i
= 0; i
< 8; i
++)
3588 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3594 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3597 neg_const_double_rtx_ok_for_fpa (x
)
3603 if (!fpa_consts_inited
)
3606 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3607 r
= REAL_VALUE_NEGATE (r
);
3608 if (REAL_VALUE_MINUS_ZERO (r
))
3611 for (i
= 0; i
< 8; i
++)
3612 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3618 /* Predicates for `match_operand' and `match_operator'. */
3620 /* s_register_operand is the same as register_operand, but it doesn't accept
3623 This function exists because at the time it was put in it led to better
3624 code. SUBREG(MEM) always needs a reload in the places where
3625 s_register_operand is used, and this seemed to lead to excessive
3629 s_register_operand (op
, mode
)
3631 enum machine_mode mode
;
3633 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3636 if (GET_CODE (op
) == SUBREG
)
3637 op
= SUBREG_REG (op
);
3639 /* We don't consider registers whose class is NO_REGS
3640 to be a register operand. */
3641 /* XXX might have to check for lo regs only for thumb ??? */
3642 return (GET_CODE (op
) == REG
3643 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3644 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3647 /* A hard register operand (even before reload. */
3650 arm_hard_register_operand (op
, mode
)
3652 enum machine_mode mode
;
3654 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3657 return (GET_CODE (op
) == REG
3658 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3661 /* Only accept reg, subreg(reg), const_int. */
3664 reg_or_int_operand (op
, mode
)
3666 enum machine_mode mode
;
3668 if (GET_CODE (op
) == CONST_INT
)
3671 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3674 if (GET_CODE (op
) == SUBREG
)
3675 op
= SUBREG_REG (op
);
3677 /* We don't consider registers whose class is NO_REGS
3678 to be a register operand. */
3679 return (GET_CODE (op
) == REG
3680 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3681 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3684 /* Return 1 if OP is an item in memory, given that we are in reload. */
3687 arm_reload_memory_operand (op
, mode
)
3689 enum machine_mode mode ATTRIBUTE_UNUSED
;
3691 int regno
= true_regnum (op
);
3693 return (!CONSTANT_P (op
)
3695 || (GET_CODE (op
) == REG
3696 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3699 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3700 memory access (architecture V4).
3701 MODE is QImode if called when computing constraints, or VOIDmode when
3702 emitting patterns. In this latter case we cannot use memory_operand()
3703 because it will fail on badly formed MEMs, which is precisely what we are
3707 bad_signed_byte_operand (op
, mode
)
3709 enum machine_mode mode ATTRIBUTE_UNUSED
;
3712 if ((mode
== QImode
&& !memory_operand (op
, mode
)) || GET_CODE (op
) != MEM
)
3715 if (GET_CODE (op
) != MEM
)
3720 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3721 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3722 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3723 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3724 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3727 /* Big constants are also bad. */
3728 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3729 && (INTVAL (XEXP (op
, 1)) > 0xff
3730 || -INTVAL (XEXP (op
, 1)) > 0xff))
3733 /* Everything else is good, or can will automatically be made so. */
3737 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3740 arm_rhs_operand (op
, mode
)
3742 enum machine_mode mode
;
3744 return (s_register_operand (op
, mode
)
3745 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3748 /* Return TRUE for valid operands for the
3749 rhs of an ARM instruction, or a load. */
3752 arm_rhsm_operand (op
, mode
)
3754 enum machine_mode mode
;
3756 return (s_register_operand (op
, mode
)
3757 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3758 || memory_operand (op
, mode
));
3761 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3762 constant that is valid when negated. */
3765 arm_add_operand (op
, mode
)
3767 enum machine_mode mode
;
3770 return thumb_cmp_operand (op
, mode
);
3772 return (s_register_operand (op
, mode
)
3773 || (GET_CODE (op
) == CONST_INT
3774 && (const_ok_for_arm (INTVAL (op
))
3775 || const_ok_for_arm (-INTVAL (op
)))));
3779 arm_not_operand (op
, mode
)
3781 enum machine_mode mode
;
3783 return (s_register_operand (op
, mode
)
3784 || (GET_CODE (op
) == CONST_INT
3785 && (const_ok_for_arm (INTVAL (op
))
3786 || const_ok_for_arm (~INTVAL (op
)))));
3789 /* Return TRUE if the operand is a memory reference which contains an
3790 offsettable address. */
3793 offsettable_memory_operand (op
, mode
)
3795 enum machine_mode mode
;
3797 if (mode
== VOIDmode
)
3798 mode
= GET_MODE (op
);
3800 return (mode
== GET_MODE (op
)
3801 && GET_CODE (op
) == MEM
3802 && offsettable_address_p (reload_completed
| reload_in_progress
,
3803 mode
, XEXP (op
, 0)));
3806 /* Return TRUE if the operand is a memory reference which is, or can be
3807 made word aligned by adjusting the offset. */
3810 alignable_memory_operand (op
, mode
)
3812 enum machine_mode mode
;
3816 if (mode
== VOIDmode
)
3817 mode
= GET_MODE (op
);
3819 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3824 return ((GET_CODE (reg
= op
) == REG
3825 || (GET_CODE (op
) == SUBREG
3826 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3827 || (GET_CODE (op
) == PLUS
3828 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3829 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3830 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3831 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3832 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3835 /* Similar to s_register_operand, but does not allow hard integer
3839 f_register_operand (op
, mode
)
3841 enum machine_mode mode
;
3843 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3846 if (GET_CODE (op
) == SUBREG
)
3847 op
= SUBREG_REG (op
);
3849 /* We don't consider registers whose class is NO_REGS
3850 to be a register operand. */
3851 return (GET_CODE (op
) == REG
3852 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3853 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
3856 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3859 fpa_rhs_operand (op
, mode
)
3861 enum machine_mode mode
;
3863 if (s_register_operand (op
, mode
))
3866 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3869 if (GET_CODE (op
) == CONST_DOUBLE
)
3870 return const_double_rtx_ok_for_fpa (op
);
3876 fpa_add_operand (op
, mode
)
3878 enum machine_mode mode
;
3880 if (s_register_operand (op
, mode
))
3883 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3886 if (GET_CODE (op
) == CONST_DOUBLE
)
3887 return (const_double_rtx_ok_for_fpa (op
)
3888 || neg_const_double_rtx_ok_for_fpa (op
));
3893 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3896 cirrus_memory_offset (op
)
3899 /* Reject eliminable registers. */
3900 if (! (reload_in_progress
|| reload_completed
)
3901 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
3902 || reg_mentioned_p (arg_pointer_rtx
, op
)
3903 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
3904 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
3905 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
3906 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
3909 if (GET_CODE (op
) == MEM
)
3915 /* Match: (mem (reg)). */
3916 if (GET_CODE (ind
) == REG
)
3922 if (GET_CODE (ind
) == PLUS
3923 && GET_CODE (XEXP (ind
, 0)) == REG
3924 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
3925 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
3932 /* Return nonzero if OP is a Cirrus or general register. */
3935 cirrus_register_operand (op
, mode
)
3937 enum machine_mode mode
;
3939 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3942 if (GET_CODE (op
) == SUBREG
)
3943 op
= SUBREG_REG (op
);
3945 return (GET_CODE (op
) == REG
3946 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
3947 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
3950 /* Return nonzero if OP is a cirrus FP register. */
3953 cirrus_fp_register (op
, mode
)
3955 enum machine_mode mode
;
3957 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3960 if (GET_CODE (op
) == SUBREG
)
3961 op
= SUBREG_REG (op
);
3963 return (GET_CODE (op
) == REG
3964 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3965 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
3968 /* Return nonzero if OP is a 6bit constant (0..63). */
3971 cirrus_shift_const (op
, mode
)
3973 enum machine_mode mode ATTRIBUTE_UNUSED
;
3975 return (GET_CODE (op
) == CONST_INT
3977 && INTVAL (op
) < 64);
3980 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
3981 Use by the Cirrus Maverick code which has to workaround
3982 a hardware bug triggered by such instructions. */
3985 arm_memory_load_p (insn
)
3988 rtx body
, lhs
, rhs
;;
3990 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
3993 body
= PATTERN (insn
);
3995 if (GET_CODE (body
) != SET
)
3998 lhs
= XEXP (body
, 0);
3999 rhs
= XEXP (body
, 1);
4001 lhs
= REG_OR_SUBREG_RTX (lhs
);
4003 /* If the destination is not a general purpose
4004 register we do not have to worry. */
4005 if (GET_CODE (lhs
) != REG
4006 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4009 /* As well as loads from memory we also have to react
4010 to loads of invalid constants which will be turned
4011 into loads from the minipool. */
4012 return (GET_CODE (rhs
) == MEM
4013 || GET_CODE (rhs
) == SYMBOL_REF
4014 || note_invalid_constants (insn
, -1, false));
4017 /* Return TRUE if INSN is a Cirrus instruction. */
4020 arm_cirrus_insn_p (insn
)
4023 enum attr_cirrus attr
;
4025 /* get_attr aborts on USE and CLOBBER. */
4027 || GET_CODE (insn
) != INSN
4028 || GET_CODE (PATTERN (insn
)) == USE
4029 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4032 attr
= get_attr_cirrus (insn
);
4034 return attr
!= CIRRUS_NOT
;
4037 /* Cirrus reorg for invalid instruction combinations. */
4040 cirrus_reorg (first
)
4043 enum attr_cirrus attr
;
4044 rtx body
= PATTERN (first
);
4048 /* Any branch must be followed by 2 non Cirrus instructions. */
4049 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4052 t
= next_nonnote_insn (first
);
4054 if (arm_cirrus_insn_p (t
))
4057 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4061 emit_insn_after (gen_nop (), first
);
4066 /* (float (blah)) is in parallel with a clobber. */
4067 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4068 body
= XVECEXP (body
, 0, 0);
4070 if (GET_CODE (body
) == SET
)
4072 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4074 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4075 be followed by a non Cirrus insn. */
4076 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4078 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4079 emit_insn_after (gen_nop (), first
);
4083 else if (arm_memory_load_p (first
))
4085 unsigned int arm_regno
;
4087 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4088 ldr/cfmv64hr combination where the Rd field is the same
4089 in both instructions must be split with a non Cirrus
4096 /* Get Arm register number for ldr insn. */
4097 if (GET_CODE (lhs
) == REG
)
4098 arm_regno
= REGNO (lhs
);
4099 else if (GET_CODE (rhs
) == REG
)
4100 arm_regno
= REGNO (rhs
);
4105 first
= next_nonnote_insn (first
);
4107 if (! arm_cirrus_insn_p (first
))
4110 body
= PATTERN (first
);
4112 /* (float (blah)) is in parallel with a clobber. */
4113 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4114 body
= XVECEXP (body
, 0, 0);
4116 if (GET_CODE (body
) == FLOAT
)
4117 body
= XEXP (body
, 0);
4119 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4120 && GET_CODE (XEXP (body
, 1)) == REG
4121 && arm_regno
== REGNO (XEXP (body
, 1)))
4122 emit_insn_after (gen_nop (), first
);
4128 /* get_attr aborts on USE and CLOBBER. */
4130 || GET_CODE (first
) != INSN
4131 || GET_CODE (PATTERN (first
)) == USE
4132 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4135 attr
= get_attr_cirrus (first
);
4137 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4138 must be followed by a non-coprocessor instruction. */
4139 if (attr
== CIRRUS_COMPARE
)
4143 t
= next_nonnote_insn (first
);
4145 if (arm_cirrus_insn_p (t
))
4148 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4152 emit_insn_after (gen_nop (), first
);
4158 /* Return nonzero if OP is a constant power of two. */
4161 power_of_two_operand (op
, mode
)
4163 enum machine_mode mode ATTRIBUTE_UNUSED
;
4165 if (GET_CODE (op
) == CONST_INT
)
4167 HOST_WIDE_INT value
= INTVAL (op
);
4169 return value
!= 0 && (value
& (value
- 1)) == 0;
4175 /* Return TRUE for a valid operand of a DImode operation.
4176 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4177 Note that this disallows MEM(REG+REG), but allows
4178 MEM(PRE/POST_INC/DEC(REG)). */
4181 di_operand (op
, mode
)
4183 enum machine_mode mode
;
4185 if (s_register_operand (op
, mode
))
4188 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4191 if (GET_CODE (op
) == SUBREG
)
4192 op
= SUBREG_REG (op
);
4194 switch (GET_CODE (op
))
4201 return memory_address_p (DImode
, XEXP (op
, 0));
4208 /* Like di_operand, but don't accept constants. */
4211 nonimmediate_di_operand (op
, mode
)
4213 enum machine_mode mode
;
4215 if (s_register_operand (op
, mode
))
4218 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4221 if (GET_CODE (op
) == SUBREG
)
4222 op
= SUBREG_REG (op
);
4224 if (GET_CODE (op
) == MEM
)
4225 return memory_address_p (DImode
, XEXP (op
, 0));
4230 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4231 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4232 Note that this disallows MEM(REG+REG), but allows
4233 MEM(PRE/POST_INC/DEC(REG)). */
4236 soft_df_operand (op
, mode
)
4238 enum machine_mode mode
;
4240 if (s_register_operand (op
, mode
))
4243 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4246 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
4249 if (GET_CODE (op
) == SUBREG
)
4250 op
= SUBREG_REG (op
);
4252 switch (GET_CODE (op
))
4258 return memory_address_p (DFmode
, XEXP (op
, 0));
4265 /* Like soft_df_operand, but don't accept constants. */
4268 nonimmediate_soft_df_operand (op
, mode
)
4270 enum machine_mode mode
;
4272 if (s_register_operand (op
, mode
))
4275 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4278 if (GET_CODE (op
) == SUBREG
)
4279 op
= SUBREG_REG (op
);
4281 if (GET_CODE (op
) == MEM
)
4282 return memory_address_p (DFmode
, XEXP (op
, 0));
4286 /* Return TRUE for valid index operands. */
4289 index_operand (op
, mode
)
4291 enum machine_mode mode
;
4293 return (s_register_operand (op
, mode
)
4294 || (immediate_operand (op
, mode
)
4295 && (GET_CODE (op
) != CONST_INT
4296 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
4299 /* Return TRUE for valid shifts by a constant. This also accepts any
4300 power of two on the (somewhat overly relaxed) assumption that the
4301 shift operator in this case was a mult. */
4304 const_shift_operand (op
, mode
)
4306 enum machine_mode mode
;
4308 return (power_of_two_operand (op
, mode
)
4309 || (immediate_operand (op
, mode
)
4310 && (GET_CODE (op
) != CONST_INT
4311 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
4314 /* Return TRUE for arithmetic operators which can be combined with a multiply
4318 shiftable_operator (x
, mode
)
4320 enum machine_mode mode
;
4324 if (GET_MODE (x
) != mode
)
4327 code
= GET_CODE (x
);
4329 return (code
== PLUS
|| code
== MINUS
4330 || code
== IOR
|| code
== XOR
|| code
== AND
);
4333 /* Return TRUE for binary logical operators. */
4336 logical_binary_operator (x
, mode
)
4338 enum machine_mode mode
;
4342 if (GET_MODE (x
) != mode
)
4345 code
= GET_CODE (x
);
4347 return (code
== IOR
|| code
== XOR
|| code
== AND
);
4350 /* Return TRUE for shift operators. */
4353 shift_operator (x
, mode
)
4355 enum machine_mode mode
;
4359 if (GET_MODE (x
) != mode
)
4362 code
= GET_CODE (x
);
4365 return power_of_two_operand (XEXP (x
, 1), mode
);
4367 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
4368 || code
== ROTATERT
);
4371 /* Return TRUE if x is EQ or NE. */
4374 equality_operator (x
, mode
)
4376 enum machine_mode mode ATTRIBUTE_UNUSED
;
4378 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
4381 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4384 arm_comparison_operator (x
, mode
)
4386 enum machine_mode mode
;
4388 return (comparison_operator (x
, mode
)
4389 && GET_CODE (x
) != LTGT
4390 && GET_CODE (x
) != UNEQ
);
4393 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4396 minmax_operator (x
, mode
)
4398 enum machine_mode mode
;
4400 enum rtx_code code
= GET_CODE (x
);
4402 if (GET_MODE (x
) != mode
)
4405 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
4408 /* Return TRUE if this is the condition code register, if we aren't given
4409 a mode, accept any class CCmode register. */
4412 cc_register (x
, mode
)
4414 enum machine_mode mode
;
4416 if (mode
== VOIDmode
)
4418 mode
= GET_MODE (x
);
4420 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4424 if ( GET_MODE (x
) == mode
4425 && GET_CODE (x
) == REG
4426 && REGNO (x
) == CC_REGNUM
)
4432 /* Return TRUE if this is the condition code register, if we aren't given
4433 a mode, accept any class CCmode register which indicates a dominance
4437 dominant_cc_register (x
, mode
)
4439 enum machine_mode mode
;
4441 if (mode
== VOIDmode
)
4443 mode
= GET_MODE (x
);
4445 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4449 if ( mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
4450 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
4451 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
4452 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
4453 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
4456 return cc_register (x
, mode
);
4459 /* Return TRUE if X references a SYMBOL_REF. */
4462 symbol_mentioned_p (x
)
4468 if (GET_CODE (x
) == SYMBOL_REF
)
4471 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4473 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4479 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4480 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
4483 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
4490 /* Return TRUE if X references a LABEL_REF. */
4493 label_mentioned_p (x
)
4499 if (GET_CODE (x
) == LABEL_REF
)
4502 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4503 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4509 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4510 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
4513 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
4524 enum rtx_code code
= GET_CODE (x
);
4528 else if (code
== SMIN
)
4530 else if (code
== UMIN
)
4532 else if (code
== UMAX
)
4538 /* Return 1 if memory locations are adjacent. */
4541 adjacent_mem_locations (a
, b
)
4544 if ((GET_CODE (XEXP (a
, 0)) == REG
4545 || (GET_CODE (XEXP (a
, 0)) == PLUS
4546 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
4547 && (GET_CODE (XEXP (b
, 0)) == REG
4548 || (GET_CODE (XEXP (b
, 0)) == PLUS
4549 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
4551 int val0
= 0, val1
= 0;
4554 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
4556 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
4557 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
4560 reg0
= REGNO (XEXP (a
, 0));
4562 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
4564 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
4565 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
4568 reg1
= REGNO (XEXP (b
, 0));
4570 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
4575 /* Return 1 if OP is a load multiple operation. It is known to be
4576 parallel and the first section will be tested. */
4579 load_multiple_operation (op
, mode
)
4581 enum machine_mode mode ATTRIBUTE_UNUSED
;
4583 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4586 HOST_WIDE_INT i
= 1, base
= 0;
4590 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4593 /* Check to see if this might be a write-back. */
4594 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4599 /* Now check it more carefully. */
4600 if (GET_CODE (SET_DEST (elt
)) != REG
4601 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4602 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4603 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4604 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4608 /* Perform a quick check so we don't blow up below. */
4610 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4611 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
4612 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
4615 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
4616 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
4618 for (; i
< count
; i
++)
4620 elt
= XVECEXP (op
, 0, i
);
4622 if (GET_CODE (elt
) != SET
4623 || GET_CODE (SET_DEST (elt
)) != REG
4624 || GET_MODE (SET_DEST (elt
)) != SImode
4625 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
4626 || GET_CODE (SET_SRC (elt
)) != MEM
4627 || GET_MODE (SET_SRC (elt
)) != SImode
4628 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
4629 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
4630 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
4631 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
4638 /* Return 1 if OP is a store multiple operation. It is known to be
4639 parallel and the first section will be tested. */
4642 store_multiple_operation (op
, mode
)
4644 enum machine_mode mode ATTRIBUTE_UNUSED
;
4646 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4649 HOST_WIDE_INT i
= 1, base
= 0;
4653 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4656 /* Check to see if this might be a write-back. */
4657 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4662 /* Now check it more carefully. */
4663 if (GET_CODE (SET_DEST (elt
)) != REG
4664 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4665 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4666 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4667 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4671 /* Perform a quick check so we don't blow up below. */
4673 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4674 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
4675 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
4678 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
4679 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
4681 for (; i
< count
; i
++)
4683 elt
= XVECEXP (op
, 0, i
);
4685 if (GET_CODE (elt
) != SET
4686 || GET_CODE (SET_SRC (elt
)) != REG
4687 || GET_MODE (SET_SRC (elt
)) != SImode
4688 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
4689 || GET_CODE (SET_DEST (elt
)) != MEM
4690 || GET_MODE (SET_DEST (elt
)) != SImode
4691 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
4692 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
4693 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
4694 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
4702 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
4707 HOST_WIDE_INT
* load_offset
;
4709 int unsorted_regs
[4];
4710 HOST_WIDE_INT unsorted_offsets
[4];
4715 /* Can only handle 2, 3, or 4 insns at present,
4716 though could be easily extended if required. */
4717 if (nops
< 2 || nops
> 4)
4720 /* Loop over the operands and check that the memory references are
4721 suitable (ie immediate offsets from the same base register). At
4722 the same time, extract the target register, and the memory
4724 for (i
= 0; i
< nops
; i
++)
4729 /* Convert a subreg of a mem into the mem itself. */
4730 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4731 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4733 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4736 /* Don't reorder volatile memory references; it doesn't seem worth
4737 looking for the case where the order is ok anyway. */
4738 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4741 offset
= const0_rtx
;
4743 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4744 || (GET_CODE (reg
) == SUBREG
4745 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4746 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4747 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4749 || (GET_CODE (reg
) == SUBREG
4750 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4751 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4756 base_reg
= REGNO (reg
);
4757 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4758 ? REGNO (operands
[i
])
4759 : REGNO (SUBREG_REG (operands
[i
])));
4764 if (base_reg
!= (int) REGNO (reg
))
4765 /* Not addressed from the same base register. */
4768 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4769 ? REGNO (operands
[i
])
4770 : REGNO (SUBREG_REG (operands
[i
])));
4771 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4775 /* If it isn't an integer register, or if it overwrites the
4776 base register but isn't the last insn in the list, then
4777 we can't do this. */
4778 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
4779 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
4782 unsorted_offsets
[i
] = INTVAL (offset
);
4785 /* Not a suitable memory address. */
4789 /* All the useful information has now been extracted from the
4790 operands into unsorted_regs and unsorted_offsets; additionally,
4791 order[0] has been set to the lowest numbered register in the
4792 list. Sort the registers into order, and check that the memory
4793 offsets are ascending and adjacent. */
4795 for (i
= 1; i
< nops
; i
++)
4799 order
[i
] = order
[i
- 1];
4800 for (j
= 0; j
< nops
; j
++)
4801 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4802 && (order
[i
] == order
[i
- 1]
4803 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4806 /* Have we found a suitable register? if not, one must be used more
4808 if (order
[i
] == order
[i
- 1])
4811 /* Is the memory address adjacent and ascending? */
4812 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4820 for (i
= 0; i
< nops
; i
++)
4821 regs
[i
] = unsorted_regs
[order
[i
]];
4823 *load_offset
= unsorted_offsets
[order
[0]];
4826 if (unsorted_offsets
[order
[0]] == 0)
4827 return 1; /* ldmia */
4829 if (unsorted_offsets
[order
[0]] == 4)
4830 return 2; /* ldmib */
4832 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4833 return 3; /* ldmda */
4835 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4836 return 4; /* ldmdb */
4838 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4839 if the offset isn't small enough. The reason 2 ldrs are faster
4840 is because these ARMs are able to do more than one cache access
4841 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4842 whilst the ARM8 has a double bandwidth cache. This means that
4843 these cores can do both an instruction fetch and a data fetch in
4844 a single cycle, so the trick of calculating the address into a
4845 scratch register (one of the result regs) and then doing a load
4846 multiple actually becomes slower (and no smaller in code size).
4847 That is the transformation
4849 ldr rd1, [rbase + offset]
4850 ldr rd2, [rbase + offset + 4]
4854 add rd1, rbase, offset
4855 ldmia rd1, {rd1, rd2}
4857 produces worse code -- '3 cycles + any stalls on rd2' instead of
4858 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4859 access per cycle, the first sequence could never complete in less
4860 than 6 cycles, whereas the ldm sequence would only take 5 and
4861 would make better use of sequential accesses if not hitting the
4864 We cheat here and test 'arm_ld_sched' which we currently know to
4865 only be true for the ARM8, ARM9 and StrongARM. If this ever
4866 changes, then the test below needs to be reworked. */
4867 if (nops
== 2 && arm_ld_sched
)
4870 /* Can't do it without setting up the offset, only do this if it takes
4871 no more than one insn. */
4872 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4873 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4877 emit_ldm_seq (operands
, nops
)
4883 HOST_WIDE_INT offset
;
4887 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4890 strcpy (buf
, "ldm%?ia\t");
4894 strcpy (buf
, "ldm%?ib\t");
4898 strcpy (buf
, "ldm%?da\t");
4902 strcpy (buf
, "ldm%?db\t");
4907 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4908 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4911 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4912 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4914 output_asm_insn (buf
, operands
);
4916 strcpy (buf
, "ldm%?ia\t");
4923 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4924 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4926 for (i
= 1; i
< nops
; i
++)
4927 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4928 reg_names
[regs
[i
]]);
4930 strcat (buf
, "}\t%@ phole ldm");
4932 output_asm_insn (buf
, operands
);
4937 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
4942 HOST_WIDE_INT
* load_offset
;
4944 int unsorted_regs
[4];
4945 HOST_WIDE_INT unsorted_offsets
[4];
4950 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4951 extended if required. */
4952 if (nops
< 2 || nops
> 4)
4955 /* Loop over the operands and check that the memory references are
4956 suitable (ie immediate offsets from the same base register). At
4957 the same time, extract the target register, and the memory
4959 for (i
= 0; i
< nops
; i
++)
4964 /* Convert a subreg of a mem into the mem itself. */
4965 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4966 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4968 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4971 /* Don't reorder volatile memory references; it doesn't seem worth
4972 looking for the case where the order is ok anyway. */
4973 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4976 offset
= const0_rtx
;
4978 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4979 || (GET_CODE (reg
) == SUBREG
4980 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4981 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4982 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4984 || (GET_CODE (reg
) == SUBREG
4985 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4986 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4991 base_reg
= REGNO (reg
);
4992 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4993 ? REGNO (operands
[i
])
4994 : REGNO (SUBREG_REG (operands
[i
])));
4999 if (base_reg
!= (int) REGNO (reg
))
5000 /* Not addressed from the same base register. */
5003 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5004 ? REGNO (operands
[i
])
5005 : REGNO (SUBREG_REG (operands
[i
])));
5006 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5010 /* If it isn't an integer register, then we can't do this. */
5011 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5014 unsorted_offsets
[i
] = INTVAL (offset
);
5017 /* Not a suitable memory address. */
5021 /* All the useful information has now been extracted from the
5022 operands into unsorted_regs and unsorted_offsets; additionally,
5023 order[0] has been set to the lowest numbered register in the
5024 list. Sort the registers into order, and check that the memory
5025 offsets are ascending and adjacent. */
5027 for (i
= 1; i
< nops
; i
++)
5031 order
[i
] = order
[i
- 1];
5032 for (j
= 0; j
< nops
; j
++)
5033 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5034 && (order
[i
] == order
[i
- 1]
5035 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5038 /* Have we found a suitable register? if not, one must be used more
5040 if (order
[i
] == order
[i
- 1])
5043 /* Is the memory address adjacent and ascending? */
5044 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5052 for (i
= 0; i
< nops
; i
++)
5053 regs
[i
] = unsorted_regs
[order
[i
]];
5055 *load_offset
= unsorted_offsets
[order
[0]];
5058 if (unsorted_offsets
[order
[0]] == 0)
5059 return 1; /* stmia */
5061 if (unsorted_offsets
[order
[0]] == 4)
5062 return 2; /* stmib */
5064 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5065 return 3; /* stmda */
5067 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5068 return 4; /* stmdb */
5074 emit_stm_seq (operands
, nops
)
5080 HOST_WIDE_INT offset
;
5084 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5087 strcpy (buf
, "stm%?ia\t");
5091 strcpy (buf
, "stm%?ib\t");
5095 strcpy (buf
, "stm%?da\t");
5099 strcpy (buf
, "stm%?db\t");
5106 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5107 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5109 for (i
= 1; i
< nops
; i
++)
5110 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5111 reg_names
[regs
[i
]]);
5113 strcat (buf
, "}\t%@ phole stm");
5115 output_asm_insn (buf
, operands
);
5120 multi_register_push (op
, mode
)
5122 enum machine_mode mode ATTRIBUTE_UNUSED
;
5124 if (GET_CODE (op
) != PARALLEL
5125 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5126 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5127 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5133 /* Routines for use in generating RTL. */
5136 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
5137 in_struct_p
, scalar_p
)
5149 int sign
= up
? 1 : -1;
5152 /* XScale has load-store double instructions, but they have stricter
5153 alignment requirements than load-store multiple, so we can not
5156 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5157 the pipeline until completion.
5165 An ldr instruction takes 1-3 cycles, but does not block the
5174 Best case ldr will always win. However, the more ldr instructions
5175 we issue, the less likely we are to be able to schedule them well.
5176 Using ldr instructions also increases code size.
5178 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5179 for counts of 3 or 4 regs. */
5180 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
5186 for (i
= 0; i
< count
; i
++)
5188 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5189 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5190 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5191 MEM_SCALAR_P (mem
) = scalar_p
;
5192 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5196 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5204 result
= gen_rtx_PARALLEL (VOIDmode
,
5205 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5208 XVECEXP (result
, 0, 0)
5209 = gen_rtx_SET (GET_MODE (from
), from
,
5210 plus_constant (from
, count
* 4 * sign
));
5215 for (j
= 0; i
< count
; i
++, j
++)
5217 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5218 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5219 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5220 MEM_SCALAR_P (mem
) = scalar_p
;
5221 XVECEXP (result
, 0, i
)
5222 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5229 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
5230 in_struct_p
, scalar_p
)
5242 int sign
= up
? 1 : -1;
5245 /* See arm_gen_load_multiple for discussion of
5246 the pros/cons of ldm/stm usage for XScale. */
5247 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
5253 for (i
= 0; i
< count
; i
++)
5255 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5256 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5257 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5258 MEM_SCALAR_P (mem
) = scalar_p
;
5259 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5263 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5271 result
= gen_rtx_PARALLEL (VOIDmode
,
5272 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5275 XVECEXP (result
, 0, 0)
5276 = gen_rtx_SET (GET_MODE (to
), to
,
5277 plus_constant (to
, count
* 4 * sign
));
5282 for (j
= 0; i
< count
; i
++, j
++)
5284 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5285 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5286 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5287 MEM_SCALAR_P (mem
) = scalar_p
;
5289 XVECEXP (result
, 0, i
)
5290 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5297 arm_gen_movstrqi (operands
)
5300 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5303 rtx st_src
, st_dst
, fin_src
, fin_dst
;
5304 rtx part_bytes_reg
= NULL
;
5306 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
5307 int dst_scalar_p
, src_scalar_p
;
5309 if (GET_CODE (operands
[2]) != CONST_INT
5310 || GET_CODE (operands
[3]) != CONST_INT
5311 || INTVAL (operands
[2]) > 64
5312 || INTVAL (operands
[3]) & 3)
5315 st_dst
= XEXP (operands
[0], 0);
5316 st_src
= XEXP (operands
[1], 0);
5318 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
5319 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
5320 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
5321 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
5322 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
5323 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
5325 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
5326 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
5328 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5329 out_words_to_go
= INTVAL (operands
[2]) / 4;
5330 last_bytes
= INTVAL (operands
[2]) & 3;
5332 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5333 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5335 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5337 if (in_words_to_go
> 4)
5338 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5343 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5344 FALSE
, src_unchanging_p
,
5345 src_in_struct_p
, src_scalar_p
));
5347 if (out_words_to_go
)
5349 if (out_words_to_go
> 4)
5350 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5354 else if (out_words_to_go
!= 1)
5355 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
5364 mem
= gen_rtx_MEM (SImode
, dst
);
5365 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5366 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5367 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5368 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
5369 if (last_bytes
!= 0)
5370 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
5374 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
5375 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
5378 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5379 if (out_words_to_go
)
5383 mem
= gen_rtx_MEM (SImode
, src
);
5384 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5385 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5386 MEM_SCALAR_P (mem
) = src_scalar_p
;
5387 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
5388 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
5390 mem
= gen_rtx_MEM (SImode
, dst
);
5391 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5392 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5393 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5394 emit_move_insn (mem
, sreg
);
5395 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
5398 if (in_words_to_go
) /* Sanity check */
5404 if (in_words_to_go
< 0)
5407 mem
= gen_rtx_MEM (SImode
, src
);
5408 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5409 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5410 MEM_SCALAR_P (mem
) = src_scalar_p
;
5411 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
5414 if (last_bytes
&& part_bytes_reg
== NULL
)
5417 if (BYTES_BIG_ENDIAN
&& last_bytes
)
5419 rtx tmp
= gen_reg_rtx (SImode
);
5421 /* The bytes we want are in the top end of the word. */
5422 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
5423 GEN_INT (8 * (4 - last_bytes
))));
5424 part_bytes_reg
= tmp
;
5428 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
5429 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5430 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5431 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5432 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5436 tmp
= gen_reg_rtx (SImode
);
5437 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
5438 part_bytes_reg
= tmp
;
5447 mem
= gen_rtx_MEM (HImode
, dst
);
5448 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5449 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5450 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5451 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
5455 rtx tmp
= gen_reg_rtx (SImode
);
5457 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
5458 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
5459 part_bytes_reg
= tmp
;
5465 mem
= gen_rtx_MEM (QImode
, dst
);
5466 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5467 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5468 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5469 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5476 /* Generate a memory reference for a half word, such that it will be loaded
5477 into the top 16 bits of the word. We can assume that the address is
5478 known to be alignable and of the form reg, or plus (reg, const). */
5481 arm_gen_rotated_half_load (memref
)
5484 HOST_WIDE_INT offset
= 0;
5485 rtx base
= XEXP (memref
, 0);
5487 if (GET_CODE (base
) == PLUS
)
5489 offset
= INTVAL (XEXP (base
, 1));
5490 base
= XEXP (base
, 0);
5493 /* If we aren't allowed to generate unaligned addresses, then fail. */
5494 if (TARGET_MMU_TRAPS
5495 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
5498 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
5500 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
5503 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
5506 /* Select a dominance comparison mode if possible for a test of the general
5507 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5508 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5509 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5510 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5511 In all cases OP will be either EQ or NE, but we don't need to know which
5512 here. If we are unable to support a dominance comparison we return
5513 CC mode. This will then fail to match for the RTL expressions that
5514 generate this call. */
5517 arm_select_dominance_cc_mode (x
, y
, cond_or
)
5520 HOST_WIDE_INT cond_or
;
5522 enum rtx_code cond1
, cond2
;
5525 /* Currently we will probably get the wrong result if the individual
5526 comparisons are not simple. This also ensures that it is safe to
5527 reverse a comparison if necessary. */
5528 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
5530 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
5534 /* The if_then_else variant of this tests the second condition if the
5535 first passes, but is true if the first fails. Reverse the first
5536 condition to get a true "inclusive-or" expression. */
5537 if (cond_or
== DOM_CC_NX_OR_Y
)
5538 cond1
= reverse_condition (cond1
);
5540 /* If the comparisons are not equal, and one doesn't dominate the other,
5541 then we can't do this. */
5543 && !comparison_dominates_p (cond1
, cond2
)
5544 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
5549 enum rtx_code temp
= cond1
;
5557 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
5562 case LE
: return CC_DLEmode
;
5563 case LEU
: return CC_DLEUmode
;
5564 case GE
: return CC_DGEmode
;
5565 case GEU
: return CC_DGEUmode
;
5572 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
5581 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
5590 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
5599 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
5607 /* The remaining cases only occur when both comparisons are the
5632 arm_select_cc_mode (op
, x
, y
)
5637 /* All floating point compares return CCFP if it is an equality
5638 comparison, and CCFPE otherwise. */
5639 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5668 /* A compare with a shifted operand. Because of canonicalization, the
5669 comparison will have to be swapped when we emit the assembler. */
5670 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
5671 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5672 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
5673 || GET_CODE (x
) == ROTATERT
))
5676 /* This is a special case that is used by combine to allow a
5677 comparison of a shifted byte load to be split into a zero-extend
5678 followed by a comparison of the shifted integer (only valid for
5679 equalities and unsigned inequalities). */
5680 if (GET_MODE (x
) == SImode
5681 && GET_CODE (x
) == ASHIFT
5682 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
5683 && GET_CODE (XEXP (x
, 0)) == SUBREG
5684 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
5685 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
5686 && (op
== EQ
|| op
== NE
5687 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
5688 && GET_CODE (y
) == CONST_INT
)
5691 /* A construct for a conditional compare, if the false arm contains
5692 0, then both conditions must be true, otherwise either condition
5693 must be true. Not all conditions are possible, so CCmode is
5694 returned if it can't be done. */
5695 if (GET_CODE (x
) == IF_THEN_ELSE
5696 && (XEXP (x
, 2) == const0_rtx
5697 || XEXP (x
, 2) == const1_rtx
)
5698 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5699 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5700 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5701 INTVAL (XEXP (x
, 2)));
5703 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5704 if (GET_CODE (x
) == AND
5705 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5706 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5707 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5710 if (GET_CODE (x
) == IOR
5711 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5712 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5713 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5716 /* An operation that sets the condition codes as a side-effect, the
5717 V flag is not set correctly, so we can only use comparisons where
5718 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5720 if (GET_MODE (x
) == SImode
5722 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
5723 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
5724 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
5725 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
5726 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
5727 || GET_CODE (x
) == LSHIFTRT
5728 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5729 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
5732 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
5735 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
5736 && GET_CODE (x
) == PLUS
5737 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
5743 /* X and Y are two things to compare using CODE. Emit the compare insn and
5744 return the rtx for register 0 in the proper mode. FP means this is a
5745 floating point compare: I don't think that it is needed on the arm. */
5748 arm_gen_compare_reg (code
, x
, y
)
5752 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
5753 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
5755 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
5756 gen_rtx_COMPARE (mode
, x
, y
)));
5761 /* Generate a sequence of insns that will generate the correct return
5762 address mask depending on the physical architecture that the program
5766 arm_gen_return_addr_mask ()
5768 rtx reg
= gen_reg_rtx (Pmode
);
5770 emit_insn (gen_return_addr_mask (reg
));
5775 arm_reload_in_hi (operands
)
5778 rtx ref
= operands
[1];
5780 HOST_WIDE_INT offset
= 0;
5782 if (GET_CODE (ref
) == SUBREG
)
5784 offset
= SUBREG_BYTE (ref
);
5785 ref
= SUBREG_REG (ref
);
5788 if (GET_CODE (ref
) == REG
)
5790 /* We have a pseudo which has been spilt onto the stack; there
5791 are two cases here: the first where there is a simple
5792 stack-slot replacement and a second where the stack-slot is
5793 out of range, or is used as a subreg. */
5794 if (reg_equiv_mem
[REGNO (ref
)])
5796 ref
= reg_equiv_mem
[REGNO (ref
)];
5797 base
= find_replacement (&XEXP (ref
, 0));
5800 /* The slot is out of range, or was dressed up in a SUBREG. */
5801 base
= reg_equiv_address
[REGNO (ref
)];
5804 base
= find_replacement (&XEXP (ref
, 0));
5806 /* Handle the case where the address is too complex to be offset by 1. */
5807 if (GET_CODE (base
) == MINUS
5808 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5810 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5812 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5815 else if (GET_CODE (base
) == PLUS
)
5817 /* The addend must be CONST_INT, or we would have dealt with it above. */
5818 HOST_WIDE_INT hi
, lo
;
5820 offset
+= INTVAL (XEXP (base
, 1));
5821 base
= XEXP (base
, 0);
5823 /* Rework the address into a legal sequence of insns. */
5824 /* Valid range for lo is -4095 -> 4095 */
5827 : -((-offset
) & 0xfff));
5829 /* Corner case, if lo is the max offset then we would be out of range
5830 once we have added the additional 1 below, so bump the msb into the
5831 pre-loading insn(s). */
5835 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5836 ^ (HOST_WIDE_INT
) 0x80000000)
5837 - (HOST_WIDE_INT
) 0x80000000);
5839 if (hi
+ lo
!= offset
)
5844 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5846 /* Get the base address; addsi3 knows how to handle constants
5847 that require more than one insn. */
5848 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5854 /* Operands[2] may overlap operands[0] (though it won't overlap
5855 operands[1]), that's why we asked for a DImode reg -- so we can
5856 use the bit that does not overlap. */
5857 if (REGNO (operands
[2]) == REGNO (operands
[0]))
5858 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5860 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5862 emit_insn (gen_zero_extendqisi2 (scratch
,
5863 gen_rtx_MEM (QImode
,
5864 plus_constant (base
,
5866 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
5867 gen_rtx_MEM (QImode
,
5868 plus_constant (base
,
5870 if (!BYTES_BIG_ENDIAN
)
5871 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5872 gen_rtx_IOR (SImode
,
5875 gen_rtx_SUBREG (SImode
, operands
[0], 0),
5879 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5880 gen_rtx_IOR (SImode
,
5881 gen_rtx_ASHIFT (SImode
, scratch
,
5883 gen_rtx_SUBREG (SImode
, operands
[0],
5887 /* Handle storing a half-word to memory during reload by synthesising as two
5888 byte stores. Take care not to clobber the input values until after we
5889 have moved them somewhere safe. This code assumes that if the DImode
5890 scratch in operands[2] overlaps either the input value or output address
5891 in some way, then that value must die in this insn (we absolutely need
5892 two scratch registers for some corner cases). */
5895 arm_reload_out_hi (operands
)
5898 rtx ref
= operands
[0];
5899 rtx outval
= operands
[1];
5901 HOST_WIDE_INT offset
= 0;
5903 if (GET_CODE (ref
) == SUBREG
)
5905 offset
= SUBREG_BYTE (ref
);
5906 ref
= SUBREG_REG (ref
);
5909 if (GET_CODE (ref
) == REG
)
5911 /* We have a pseudo which has been spilt onto the stack; there
5912 are two cases here: the first where there is a simple
5913 stack-slot replacement and a second where the stack-slot is
5914 out of range, or is used as a subreg. */
5915 if (reg_equiv_mem
[REGNO (ref
)])
5917 ref
= reg_equiv_mem
[REGNO (ref
)];
5918 base
= find_replacement (&XEXP (ref
, 0));
5921 /* The slot is out of range, or was dressed up in a SUBREG. */
5922 base
= reg_equiv_address
[REGNO (ref
)];
5925 base
= find_replacement (&XEXP (ref
, 0));
5927 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5929 /* Handle the case where the address is too complex to be offset by 1. */
5930 if (GET_CODE (base
) == MINUS
5931 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5933 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5935 /* Be careful not to destroy OUTVAL. */
5936 if (reg_overlap_mentioned_p (base_plus
, outval
))
5938 /* Updating base_plus might destroy outval, see if we can
5939 swap the scratch and base_plus. */
5940 if (!reg_overlap_mentioned_p (scratch
, outval
))
5943 scratch
= base_plus
;
5948 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5950 /* Be conservative and copy OUTVAL into the scratch now,
5951 this should only be necessary if outval is a subreg
5952 of something larger than a word. */
5953 /* XXX Might this clobber base? I can't see how it can,
5954 since scratch is known to overlap with OUTVAL, and
5955 must be wider than a word. */
5956 emit_insn (gen_movhi (scratch_hi
, outval
));
5957 outval
= scratch_hi
;
5961 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5964 else if (GET_CODE (base
) == PLUS
)
5966 /* The addend must be CONST_INT, or we would have dealt with it above. */
5967 HOST_WIDE_INT hi
, lo
;
5969 offset
+= INTVAL (XEXP (base
, 1));
5970 base
= XEXP (base
, 0);
5972 /* Rework the address into a legal sequence of insns. */
5973 /* Valid range for lo is -4095 -> 4095 */
5976 : -((-offset
) & 0xfff));
5978 /* Corner case, if lo is the max offset then we would be out of range
5979 once we have added the additional 1 below, so bump the msb into the
5980 pre-loading insn(s). */
5984 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5985 ^ (HOST_WIDE_INT
) 0x80000000)
5986 - (HOST_WIDE_INT
) 0x80000000);
5988 if (hi
+ lo
!= offset
)
5993 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5995 /* Be careful not to destroy OUTVAL. */
5996 if (reg_overlap_mentioned_p (base_plus
, outval
))
5998 /* Updating base_plus might destroy outval, see if we
5999 can swap the scratch and base_plus. */
6000 if (!reg_overlap_mentioned_p (scratch
, outval
))
6003 scratch
= base_plus
;
6008 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6010 /* Be conservative and copy outval into scratch now,
6011 this should only be necessary if outval is a
6012 subreg of something larger than a word. */
6013 /* XXX Might this clobber base? I can't see how it
6014 can, since scratch is known to overlap with
6016 emit_insn (gen_movhi (scratch_hi
, outval
));
6017 outval
= scratch_hi
;
6021 /* Get the base address; addsi3 knows how to handle constants
6022 that require more than one insn. */
6023 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6029 if (BYTES_BIG_ENDIAN
)
6031 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6032 plus_constant (base
, offset
+ 1)),
6033 gen_lowpart (QImode
, outval
)));
6034 emit_insn (gen_lshrsi3 (scratch
,
6035 gen_rtx_SUBREG (SImode
, outval
, 0),
6037 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6038 gen_lowpart (QImode
, scratch
)));
6042 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6043 gen_lowpart (QImode
, outval
)));
6044 emit_insn (gen_lshrsi3 (scratch
,
6045 gen_rtx_SUBREG (SImode
, outval
, 0),
6047 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6048 plus_constant (base
, offset
+ 1)),
6049 gen_lowpart (QImode
, scratch
)));
6053 /* Print a symbolic form of X to the debug file, F. */
6056 arm_print_value (f
, x
)
6060 switch (GET_CODE (x
))
6063 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6067 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6071 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6075 fprintf (f
, "`%s'", XSTR (x
, 0));
6079 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6083 arm_print_value (f
, XEXP (x
, 0));
6087 arm_print_value (f
, XEXP (x
, 0));
6089 arm_print_value (f
, XEXP (x
, 1));
6097 fprintf (f
, "????");
6102 /* Routines for manipulation of the constant pool. */
6104 /* Arm instructions cannot load a large constant directly into a
6105 register; they have to come from a pc relative load. The constant
6106 must therefore be placed in the addressable range of the pc
6107 relative load. Depending on the precise pc relative load
6108 instruction the range is somewhere between 256 bytes and 4k. This
6109 means that we often have to dump a constant inside a function, and
6110 generate code to branch around it.
6112 It is important to minimize this, since the branches will slow
6113 things down and make the code larger.
6115 Normally we can hide the table after an existing unconditional
6116 branch so that there is no interruption of the flow, but in the
6117 worst case the code looks like this:
6135 We fix this by performing a scan after scheduling, which notices
6136 which instructions need to have their operands fetched from the
6137 constant table and builds the table.
6139 The algorithm starts by building a table of all the constants that
6140 need fixing up and all the natural barriers in the function (places
6141 where a constant table can be dropped without breaking the flow).
6142 For each fixup we note how far the pc-relative replacement will be
6143 able to reach and the offset of the instruction into the function.
6145 Having built the table we then group the fixes together to form
6146 tables that are as large as possible (subject to addressing
6147 constraints) and emit each table of constants after the last
6148 barrier that is within range of all the instructions in the group.
6149 If a group does not contain a barrier, then we forcibly create one
6150 by inserting a jump instruction into the flow. Once the table has
6151 been inserted, the insns are then modified to reference the
6152 relevant entry in the pool.
6154 Possible enhancements to the algorithm (not implemented) are:
6156 1) For some processors and object formats, there may be benefit in
6157 aligning the pools to the start of cache lines; this alignment
6158 would need to be taken into account when calculating addressability
6161 /* These typedefs are located at the start of this file, so that
6162 they can be used in the prototypes there. This comment is to
6163 remind readers of that fact so that the following structures
6164 can be understood more easily.
6166 typedef struct minipool_node Mnode;
6167 typedef struct minipool_fixup Mfix; */
6169 struct minipool_node
6171 /* Doubly linked chain of entries. */
6174 /* The maximum offset into the code that this entry can be placed. While
6175 pushing fixes for forward references, all entries are sorted in order
6176 of increasing max_address. */
6177 HOST_WIDE_INT max_address
;
6178 /* Similarly for an entry inserted for a backwards ref. */
6179 HOST_WIDE_INT min_address
;
6180 /* The number of fixes referencing this entry. This can become zero
6181 if we "unpush" an entry. In this case we ignore the entry when we
6182 come to emit the code. */
6184 /* The offset from the start of the minipool. */
6185 HOST_WIDE_INT offset
;
6186 /* The value in table. */
6188 /* The mode of value. */
6189 enum machine_mode mode
;
6193 struct minipool_fixup
6197 HOST_WIDE_INT address
;
6199 enum machine_mode mode
;
6203 HOST_WIDE_INT forwards
;
6204 HOST_WIDE_INT backwards
;
6207 /* Fixes less than a word need padding out to a word boundary. */
6208 #define MINIPOOL_FIX_SIZE(mode) \
6209 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6211 static Mnode
* minipool_vector_head
;
6212 static Mnode
* minipool_vector_tail
;
6213 static rtx minipool_vector_label
;
6215 /* The linked list of all minipool fixes required for this function. */
6216 Mfix
* minipool_fix_head
;
6217 Mfix
* minipool_fix_tail
;
6218 /* The fix entry for the current minipool, once it has been placed. */
6219 Mfix
* minipool_barrier
;
6221 /* Determines if INSN is the start of a jump table. Returns the end
6222 of the TABLE or NULL_RTX. */
6225 is_jump_table (insn
)
6230 if (GET_CODE (insn
) == JUMP_INSN
6231 && JUMP_LABEL (insn
) != NULL
6232 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6233 == next_real_insn (insn
))
6235 && GET_CODE (table
) == JUMP_INSN
6236 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6237 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6243 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6244 #define JUMP_TABLES_IN_TEXT_SECTION 0
6247 static HOST_WIDE_INT
6248 get_jump_table_size (insn
)
6251 /* ADDR_VECs only take room if read-only data does into the text
6253 if (JUMP_TABLES_IN_TEXT_SECTION
6254 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6259 rtx body
= PATTERN (insn
);
6260 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6262 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6268 /* Move a minipool fix MP from its current location to before MAX_MP.
6269 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6270 contrains may need updating. */
6273 move_minipool_fix_forward_ref (mp
, max_mp
, max_address
)
6276 HOST_WIDE_INT max_address
;
6278 /* This should never be true and the code below assumes these are
6285 if (max_address
< mp
->max_address
)
6286 mp
->max_address
= max_address
;
6290 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6291 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6293 mp
->max_address
= max_address
;
6295 /* Unlink MP from its current position. Since max_mp is non-null,
6296 mp->prev must be non-null. */
6297 mp
->prev
->next
= mp
->next
;
6298 if (mp
->next
!= NULL
)
6299 mp
->next
->prev
= mp
->prev
;
6301 minipool_vector_tail
= mp
->prev
;
6303 /* Re-insert it before MAX_MP. */
6305 mp
->prev
= max_mp
->prev
;
6308 if (mp
->prev
!= NULL
)
6309 mp
->prev
->next
= mp
;
6311 minipool_vector_head
= mp
;
6314 /* Save the new entry. */
6317 /* Scan over the preceding entries and adjust their addresses as
6319 while (mp
->prev
!= NULL
6320 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6322 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6329 /* Add a constant to the minipool for a forward reference. Returns the
6330 node added or NULL if the constant will not fit in this pool. */
6333 add_minipool_forward_ref (fix
)
6336 /* If set, max_mp is the first pool_entry that has a lower
6337 constraint than the one we are trying to add. */
6338 Mnode
* max_mp
= NULL
;
6339 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6342 /* If this fix's address is greater than the address of the first
6343 entry, then we can't put the fix in this pool. We subtract the
6344 size of the current fix to ensure that if the table is fully
6345 packed we still have enough room to insert this value by suffling
6346 the other fixes forwards. */
6347 if (minipool_vector_head
&&
6348 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6351 /* Scan the pool to see if a constant with the same value has
6352 already been added. While we are doing this, also note the
6353 location where we must insert the constant if it doesn't already
6355 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6357 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6358 && fix
->mode
== mp
->mode
6359 && (GET_CODE (fix
->value
) != CODE_LABEL
6360 || (CODE_LABEL_NUMBER (fix
->value
)
6361 == CODE_LABEL_NUMBER (mp
->value
)))
6362 && rtx_equal_p (fix
->value
, mp
->value
))
6364 /* More than one fix references this entry. */
6366 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
6369 /* Note the insertion point if necessary. */
6371 && mp
->max_address
> max_address
)
6375 /* The value is not currently in the minipool, so we need to create
6376 a new entry for it. If MAX_MP is NULL, the entry will be put on
6377 the end of the list since the placement is less constrained than
6378 any existing entry. Otherwise, we insert the new fix before
6379 MAX_MP and, if necessary, adjust the constraints on the other
6381 mp
= xmalloc (sizeof (* mp
));
6382 mp
->fix_size
= fix
->fix_size
;
6383 mp
->mode
= fix
->mode
;
6384 mp
->value
= fix
->value
;
6386 /* Not yet required for a backwards ref. */
6387 mp
->min_address
= -65536;
6391 mp
->max_address
= max_address
;
6393 mp
->prev
= minipool_vector_tail
;
6395 if (mp
->prev
== NULL
)
6397 minipool_vector_head
= mp
;
6398 minipool_vector_label
= gen_label_rtx ();
6401 mp
->prev
->next
= mp
;
6403 minipool_vector_tail
= mp
;
6407 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6408 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6410 mp
->max_address
= max_address
;
6413 mp
->prev
= max_mp
->prev
;
6415 if (mp
->prev
!= NULL
)
6416 mp
->prev
->next
= mp
;
6418 minipool_vector_head
= mp
;
6421 /* Save the new entry. */
6424 /* Scan over the preceding entries and adjust their addresses as
6426 while (mp
->prev
!= NULL
6427 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6429 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6437 move_minipool_fix_backward_ref (mp
, min_mp
, min_address
)
6440 HOST_WIDE_INT min_address
;
6442 HOST_WIDE_INT offset
;
6444 /* This should never be true, and the code below assumes these are
6451 if (min_address
> mp
->min_address
)
6452 mp
->min_address
= min_address
;
6456 /* We will adjust this below if it is too loose. */
6457 mp
->min_address
= min_address
;
6459 /* Unlink MP from its current position. Since min_mp is non-null,
6460 mp->next must be non-null. */
6461 mp
->next
->prev
= mp
->prev
;
6462 if (mp
->prev
!= NULL
)
6463 mp
->prev
->next
= mp
->next
;
6465 minipool_vector_head
= mp
->next
;
6467 /* Reinsert it after MIN_MP. */
6469 mp
->next
= min_mp
->next
;
6471 if (mp
->next
!= NULL
)
6472 mp
->next
->prev
= mp
;
6474 minipool_vector_tail
= mp
;
6480 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6482 mp
->offset
= offset
;
6483 if (mp
->refcount
> 0)
6484 offset
+= mp
->fix_size
;
6486 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6487 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6493 /* Add a constant to the minipool for a backward reference. Returns the
6494 node added or NULL if the constant will not fit in this pool.
6496 Note that the code for insertion for a backwards reference can be
6497 somewhat confusing because the calculated offsets for each fix do
6498 not take into account the size of the pool (which is still under
6502 add_minipool_backward_ref (fix
)
6505 /* If set, min_mp is the last pool_entry that has a lower constraint
6506 than the one we are trying to add. */
6507 Mnode
* min_mp
= NULL
;
6508 /* This can be negative, since it is only a constraint. */
6509 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
6512 /* If we can't reach the current pool from this insn, or if we can't
6513 insert this entry at the end of the pool without pushing other
6514 fixes out of range, then we don't try. This ensures that we
6515 can't fail later on. */
6516 if (min_address
>= minipool_barrier
->address
6517 || (minipool_vector_tail
->min_address
+ fix
->fix_size
6518 >= minipool_barrier
->address
))
6521 /* Scan the pool to see if a constant with the same value has
6522 already been added. While we are doing this, also note the
6523 location where we must insert the constant if it doesn't already
6525 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
6527 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6528 && fix
->mode
== mp
->mode
6529 && (GET_CODE (fix
->value
) != CODE_LABEL
6530 || (CODE_LABEL_NUMBER (fix
->value
)
6531 == CODE_LABEL_NUMBER (mp
->value
)))
6532 && rtx_equal_p (fix
->value
, mp
->value
)
6533 /* Check that there is enough slack to move this entry to the
6534 end of the table (this is conservative). */
6536 > (minipool_barrier
->address
6537 + minipool_vector_tail
->offset
6538 + minipool_vector_tail
->fix_size
)))
6541 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
6545 mp
->min_address
+= fix
->fix_size
;
6548 /* Note the insertion point if necessary. */
6549 if (mp
->min_address
< min_address
)
6551 else if (mp
->max_address
6552 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
6554 /* Inserting before this entry would push the fix beyond
6555 its maximum address (which can happen if we have
6556 re-located a forwards fix); force the new fix to come
6559 min_address
= mp
->min_address
+ fix
->fix_size
;
6564 /* We need to create a new entry. */
6565 mp
= xmalloc (sizeof (* mp
));
6566 mp
->fix_size
= fix
->fix_size
;
6567 mp
->mode
= fix
->mode
;
6568 mp
->value
= fix
->value
;
6570 mp
->max_address
= minipool_barrier
->address
+ 65536;
6572 mp
->min_address
= min_address
;
6577 mp
->next
= minipool_vector_head
;
6579 if (mp
->next
== NULL
)
6581 minipool_vector_tail
= mp
;
6582 minipool_vector_label
= gen_label_rtx ();
6585 mp
->next
->prev
= mp
;
6587 minipool_vector_head
= mp
;
6591 mp
->next
= min_mp
->next
;
6595 if (mp
->next
!= NULL
)
6596 mp
->next
->prev
= mp
;
6598 minipool_vector_tail
= mp
;
6601 /* Save the new entry. */
6609 /* Scan over the following entries and adjust their offsets. */
6610 while (mp
->next
!= NULL
)
6612 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6613 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6616 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
6618 mp
->next
->offset
= mp
->offset
;
6627 assign_minipool_offsets (barrier
)
6630 HOST_WIDE_INT offset
= 0;
6633 minipool_barrier
= barrier
;
6635 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6637 mp
->offset
= offset
;
6639 if (mp
->refcount
> 0)
6640 offset
+= mp
->fix_size
;
6644 /* Output the literal table */
6646 dump_minipool (scan
)
6653 fprintf (rtl_dump_file
,
6654 ";; Emitting minipool after insn %u; address %ld\n",
6655 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
);
6657 scan
= emit_label_after (gen_label_rtx (), scan
);
6658 scan
= emit_insn_after (gen_align_4 (), scan
);
6659 scan
= emit_label_after (minipool_vector_label
, scan
);
6661 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
6663 if (mp
->refcount
> 0)
6667 fprintf (rtl_dump_file
,
6668 ";; Offset %u, min %ld, max %ld ",
6669 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
6670 (unsigned long) mp
->max_address
);
6671 arm_print_value (rtl_dump_file
, mp
->value
);
6672 fputc ('\n', rtl_dump_file
);
6675 switch (mp
->fix_size
)
6677 #ifdef HAVE_consttable_1
6679 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
6683 #ifdef HAVE_consttable_2
6685 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
6689 #ifdef HAVE_consttable_4
6691 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
6695 #ifdef HAVE_consttable_8
6697 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
6711 minipool_vector_head
= minipool_vector_tail
= NULL
;
6712 scan
= emit_insn_after (gen_consttable_end (), scan
);
6713 scan
= emit_barrier_after (scan
);
6716 /* Return the cost of forcibly inserting a barrier after INSN. */
6719 arm_barrier_cost (insn
)
6722 /* Basing the location of the pool on the loop depth is preferable,
6723 but at the moment, the basic block information seems to be
6724 corrupt by this stage of the compilation. */
6726 rtx next
= next_nonnote_insn (insn
);
6728 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
6731 switch (GET_CODE (insn
))
6734 /* It will always be better to place the table before the label, rather
6743 return base_cost
- 10;
6746 return base_cost
+ 10;
6750 /* Find the best place in the insn stream in the range
6751 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6752 Create the barrier by inserting a jump and add a new fix entry for
6756 create_fix_barrier (fix
, max_address
)
6758 HOST_WIDE_INT max_address
;
6760 HOST_WIDE_INT count
= 0;
6762 rtx from
= fix
->insn
;
6763 rtx selected
= from
;
6765 HOST_WIDE_INT selected_address
;
6767 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
6768 rtx label
= gen_label_rtx ();
6770 selected_cost
= arm_barrier_cost (from
);
6771 selected_address
= fix
->address
;
6773 while (from
&& count
< max_count
)
6778 /* This code shouldn't have been called if there was a natural barrier
6780 if (GET_CODE (from
) == BARRIER
)
6783 /* Count the length of this insn. */
6784 count
+= get_attr_length (from
);
6786 /* If there is a jump table, add its length. */
6787 tmp
= is_jump_table (from
);
6790 count
+= get_jump_table_size (tmp
);
6792 /* Jump tables aren't in a basic block, so base the cost on
6793 the dispatch insn. If we select this location, we will
6794 still put the pool after the table. */
6795 new_cost
= arm_barrier_cost (from
);
6797 if (count
< max_count
&& new_cost
<= selected_cost
)
6800 selected_cost
= new_cost
;
6801 selected_address
= fix
->address
+ count
;
6804 /* Continue after the dispatch table. */
6805 from
= NEXT_INSN (tmp
);
6809 new_cost
= arm_barrier_cost (from
);
6811 if (count
< max_count
&& new_cost
<= selected_cost
)
6814 selected_cost
= new_cost
;
6815 selected_address
= fix
->address
+ count
;
6818 from
= NEXT_INSN (from
);
6821 /* Create a new JUMP_INSN that branches around a barrier. */
6822 from
= emit_jump_insn_after (gen_jump (label
), selected
);
6823 JUMP_LABEL (from
) = label
;
6824 barrier
= emit_barrier_after (from
);
6825 emit_label_after (label
, barrier
);
6827 /* Create a minipool barrier entry for the new barrier. */
6828 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
6829 new_fix
->insn
= barrier
;
6830 new_fix
->address
= selected_address
;
6831 new_fix
->next
= fix
->next
;
6832 fix
->next
= new_fix
;
6837 /* Record that there is a natural barrier in the insn stream at
6840 push_minipool_barrier (insn
, address
)
6842 HOST_WIDE_INT address
;
6844 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6847 fix
->address
= address
;
6850 if (minipool_fix_head
!= NULL
)
6851 minipool_fix_tail
->next
= fix
;
6853 minipool_fix_head
= fix
;
6855 minipool_fix_tail
= fix
;
6858 /* Record INSN, which will need fixing up to load a value from the
6859 minipool. ADDRESS is the offset of the insn since the start of the
6860 function; LOC is a pointer to the part of the insn which requires
6861 fixing; VALUE is the constant that must be loaded, which is of type
6864 push_minipool_fix (insn
, address
, loc
, mode
, value
)
6866 HOST_WIDE_INT address
;
6868 enum machine_mode mode
;
6871 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6873 #ifdef AOF_ASSEMBLER
6874 /* PIC symbol refereneces need to be converted into offsets into the
6876 /* XXX This shouldn't be done here. */
6877 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
6878 value
= aof_pic_entry (value
);
6879 #endif /* AOF_ASSEMBLER */
6882 fix
->address
= address
;
6885 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
6887 fix
->forwards
= get_attr_pool_range (insn
);
6888 fix
->backwards
= get_attr_neg_pool_range (insn
);
6889 fix
->minipool
= NULL
;
6891 /* If an insn doesn't have a range defined for it, then it isn't
6892 expecting to be reworked by this code. Better to abort now than
6893 to generate duff assembly code. */
6894 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6899 fprintf (rtl_dump_file
,
6900 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6901 GET_MODE_NAME (mode
),
6902 INSN_UID (insn
), (unsigned long) address
,
6903 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6904 arm_print_value (rtl_dump_file
, fix
->value
);
6905 fprintf (rtl_dump_file
, "\n");
6908 /* Add it to the chain of fixes. */
6911 if (minipool_fix_head
!= NULL
)
6912 minipool_fix_tail
->next
= fix
;
6914 minipool_fix_head
= fix
;
6916 minipool_fix_tail
= fix
;
6919 /* Scan INSN and note any of its operands that need fixing.
6920 If DO_PUSHES is false we do not actually push any of the fixups
6921 needed. The function returns TRUE is any fixups were needed/pushed.
6922 This is used by arm_memory_load_p() which needs to know about loads
6923 of constants that will be converted into minipool loads. */
6926 note_invalid_constants (insn
, address
, do_pushes
)
6928 HOST_WIDE_INT address
;
6931 bool result
= false;
6934 extract_insn (insn
);
6936 if (!constrain_operands (1))
6937 fatal_insn_not_found (insn
);
6939 /* Fill in recog_op_alt with information about the constraints of this insn. */
6940 preprocess_constraints ();
6942 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6944 /* Things we need to fix can only occur in inputs. */
6945 if (recog_data
.operand_type
[opno
] != OP_IN
)
6948 /* If this alternative is a memory reference, then any mention
6949 of constants in this alternative is really to fool reload
6950 into allowing us to accept one there. We need to fix them up
6951 now so that we output the right code. */
6952 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6954 rtx op
= recog_data
.operand
[opno
];
6956 if (CONSTANT_P (op
))
6959 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6960 recog_data
.operand_mode
[opno
], op
);
6963 else if (GET_CODE (op
) == MEM
6964 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6965 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6968 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6969 recog_data
.operand_mode
[opno
],
6970 get_pool_constant (XEXP (op
, 0)));
6985 HOST_WIDE_INT address
= 0;
6988 minipool_fix_head
= minipool_fix_tail
= NULL
;
6990 /* The first insn must always be a note, or the code below won't
6991 scan it properly. */
6992 if (GET_CODE (first
) != NOTE
)
6995 /* Scan all the insns and record the operands that will need fixing. */
6996 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
6998 if (TARGET_CIRRUS_FIX_INVALID_INSNS
6999 && (arm_cirrus_insn_p (insn
)
7000 || GET_CODE (insn
) == JUMP_INSN
7001 || arm_memory_load_p (insn
)))
7002 cirrus_reorg (insn
);
7004 if (GET_CODE (insn
) == BARRIER
)
7005 push_minipool_barrier (insn
, address
);
7006 else if (INSN_P (insn
))
7010 note_invalid_constants (insn
, address
, true);
7011 address
+= get_attr_length (insn
);
7013 /* If the insn is a vector jump, add the size of the table
7014 and skip the table. */
7015 if ((table
= is_jump_table (insn
)) != NULL
)
7017 address
+= get_jump_table_size (table
);
7023 fix
= minipool_fix_head
;
7025 /* Now scan the fixups and perform the required changes. */
7030 Mfix
* last_added_fix
;
7031 Mfix
* last_barrier
= NULL
;
7034 /* Skip any further barriers before the next fix. */
7035 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7038 /* No more fixes. */
7042 last_added_fix
= NULL
;
7044 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7046 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7048 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7051 last_barrier
= ftmp
;
7053 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7056 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7059 /* If we found a barrier, drop back to that; any fixes that we
7060 could have reached but come after the barrier will now go in
7061 the next mini-pool. */
7062 if (last_barrier
!= NULL
)
7064 /* Reduce the refcount for those fixes that won't go into this
7066 for (fdel
= last_barrier
->next
;
7067 fdel
&& fdel
!= ftmp
;
7070 fdel
->minipool
->refcount
--;
7071 fdel
->minipool
= NULL
;
7074 ftmp
= last_barrier
;
7078 /* ftmp is first fix that we can't fit into this pool and
7079 there no natural barriers that we could use. Insert a
7080 new barrier in the code somewhere between the previous
7081 fix and this one, and arrange to jump around it. */
7082 HOST_WIDE_INT max_address
;
7084 /* The last item on the list of fixes must be a barrier, so
7085 we can never run off the end of the list of fixes without
7086 last_barrier being set. */
7090 max_address
= minipool_vector_head
->max_address
;
7091 /* Check that there isn't another fix that is in range that
7092 we couldn't fit into this pool because the pool was
7093 already too large: we need to put the pool before such an
7095 if (ftmp
->address
< max_address
)
7096 max_address
= ftmp
->address
;
7098 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7101 assign_minipool_offsets (last_barrier
);
7105 if (GET_CODE (ftmp
->insn
) != BARRIER
7106 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7113 /* Scan over the fixes we have identified for this pool, fixing them
7114 up and adding the constants to the pool itself. */
7115 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7116 this_fix
= this_fix
->next
)
7117 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7120 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7121 minipool_vector_label
),
7122 this_fix
->minipool
->offset
);
7123 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7126 dump_minipool (last_barrier
->insn
);
7130 /* From now on we must synthesize any constants that we can't handle
7131 directly. This can happen if the RTL gets split during final
7132 instruction generation. */
7133 after_arm_reorg
= 1;
7135 /* Free the minipool memory. */
7136 obstack_free (&minipool_obstack
, minipool_startobj
);
7139 /* Routines to output assembly language. */
7141 /* If the rtx is the correct value then return the string of the number.
7142 In this way we can ensure that valid double constants are generated even
7143 when cross compiling. */
7146 fp_immediate_constant (x
)
7152 if (!fpa_consts_inited
)
7155 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7156 for (i
= 0; i
< 8; i
++)
7157 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
7158 return strings_fpa
[i
];
7163 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7166 fp_const_from_val (r
)
7167 REAL_VALUE_TYPE
* r
;
7171 if (!fpa_consts_inited
)
7174 for (i
= 0; i
< 8; i
++)
7175 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
7176 return strings_fpa
[i
];
7181 /* Output the operands of a LDM/STM instruction to STREAM.
7182 MASK is the ARM register set mask of which only bits 0-15 are important.
7183 REG is the base register, either the frame pointer or the stack pointer,
7184 INSTR is the possibly suffixed load or store instruction. */
7187 print_multi_reg (stream
, instr
, reg
, mask
)
7194 int not_first
= FALSE
;
7196 fputc ('\t', stream
);
7197 asm_fprintf (stream
, instr
, reg
);
7198 fputs (", {", stream
);
7200 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7201 if (mask
& (1 << i
))
7204 fprintf (stream
, ", ");
7206 asm_fprintf (stream
, "%r", i
);
7210 fprintf (stream
, "}");
7212 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7213 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7214 Strictly speaking the instruction would be unpredicatble only if
7215 we were writing back the base register as well, but since we never
7216 want to generate an LDM type 2 instruction (register bank switching)
7217 which is what you get if the PC is not being loaded, we do not need
7218 to check for writeback. */
7219 if (! TARGET_APCS_32
7220 && ((mask
& (1 << PC_REGNUM
)) != 0))
7221 fprintf (stream
, "^");
7223 fprintf (stream
, "\n");
7226 /* Output a 'call' insn. */
7229 output_call (operands
)
7232 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7234 if (REGNO (operands
[0]) == LR_REGNUM
)
7236 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
7237 output_asm_insn ("mov%?\t%0, %|lr", operands
);
7240 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7242 if (TARGET_INTERWORK
)
7243 output_asm_insn ("bx%?\t%0", operands
);
7245 output_asm_insn ("mov%?\t%|pc, %0", operands
);
7254 int something_changed
= 0;
7256 int code
= GET_CODE (x0
);
7263 if (REGNO (x0
) == LR_REGNUM
)
7265 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
7270 /* Scan through the sub-elements and change any references there. */
7271 fmt
= GET_RTX_FORMAT (code
);
7273 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7275 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
7276 else if (fmt
[i
] == 'E')
7277 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
7278 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
7280 return something_changed
;
7284 /* Output a 'call' insn that is a reference in memory. */
7287 output_call_mem (operands
)
7290 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful. */
7291 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
7292 if (eliminate_lr2ip (&operands
[0]))
7293 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
7295 if (TARGET_INTERWORK
)
7297 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7298 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7299 output_asm_insn ("bx%?\t%|ip", operands
);
7303 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7304 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
7311 /* Output a move from arm registers to an fpa registers.
7312 OPERANDS[0] is an fpa register.
7313 OPERANDS[1] is the first registers of an arm register pair. */
7316 output_mov_long_double_fpa_from_arm (operands
)
7319 int arm_reg0
= REGNO (operands
[1]);
7322 if (arm_reg0
== IP_REGNUM
)
7325 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7326 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7327 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7329 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7330 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
7335 /* Output a move from an fpa register to arm registers.
7336 OPERANDS[0] is the first registers of an arm register pair.
7337 OPERANDS[1] is an fpa register. */
7340 output_mov_long_double_arm_from_fpa (operands
)
7343 int arm_reg0
= REGNO (operands
[0]);
7346 if (arm_reg0
== IP_REGNUM
)
7349 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7350 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7351 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7353 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
7354 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7358 /* Output a move from arm registers to arm registers of a long double
7359 OPERANDS[0] is the destination.
7360 OPERANDS[1] is the source. */
7363 output_mov_long_double_arm_from_arm (operands
)
7366 /* We have to be careful here because the two might overlap. */
7367 int dest_start
= REGNO (operands
[0]);
7368 int src_start
= REGNO (operands
[1]);
7372 if (dest_start
< src_start
)
7374 for (i
= 0; i
< 3; i
++)
7376 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7377 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7378 output_asm_insn ("mov%?\t%0, %1", ops
);
7383 for (i
= 2; i
>= 0; i
--)
7385 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7386 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7387 output_asm_insn ("mov%?\t%0, %1", ops
);
7395 /* Output a move from arm registers to an fpa registers.
7396 OPERANDS[0] is an fpa register.
7397 OPERANDS[1] is the first registers of an arm register pair. */
7400 output_mov_double_fpa_from_arm (operands
)
7403 int arm_reg0
= REGNO (operands
[1]);
7406 if (arm_reg0
== IP_REGNUM
)
7409 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7410 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7411 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
7412 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
7416 /* Output a move from an fpa register to arm registers.
7417 OPERANDS[0] is the first registers of an arm register pair.
7418 OPERANDS[1] is an fpa register. */
7421 output_mov_double_arm_from_fpa (operands
)
7424 int arm_reg0
= REGNO (operands
[0]);
7427 if (arm_reg0
== IP_REGNUM
)
7430 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7431 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7432 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
7433 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
7437 /* Output a move between double words.
7438 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7439 or MEM<-REG and all MEMs must be offsettable addresses. */
7442 output_move_double (operands
)
7445 enum rtx_code code0
= GET_CODE (operands
[0]);
7446 enum rtx_code code1
= GET_CODE (operands
[1]);
7451 int reg0
= REGNO (operands
[0]);
7453 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
7457 int reg1
= REGNO (operands
[1]);
7458 if (reg1
== IP_REGNUM
)
7461 /* Ensure the second source is not overwritten. */
7462 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
7463 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
7465 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
7467 else if (code1
== CONST_DOUBLE
)
7469 if (GET_MODE (operands
[1]) == DFmode
)
7474 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
7475 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
7476 otherops
[1] = GEN_INT (l
[1]);
7477 operands
[1] = GEN_INT (l
[0]);
7479 else if (GET_MODE (operands
[1]) != VOIDmode
)
7481 else if (WORDS_BIG_ENDIAN
)
7483 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7484 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7488 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7489 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7492 output_mov_immediate (operands
);
7493 output_mov_immediate (otherops
);
7495 else if (code1
== CONST_INT
)
7497 #if HOST_BITS_PER_WIDE_INT > 32
7498 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7499 what the upper word is. */
7500 if (WORDS_BIG_ENDIAN
)
7502 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7503 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7507 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7508 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7511 /* Sign extend the intval into the high-order word. */
7512 if (WORDS_BIG_ENDIAN
)
7514 otherops
[1] = operands
[1];
7515 operands
[1] = (INTVAL (operands
[1]) < 0
7516 ? constm1_rtx
: const0_rtx
);
7519 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
7521 output_mov_immediate (otherops
);
7522 output_mov_immediate (operands
);
7524 else if (code1
== MEM
)
7526 switch (GET_CODE (XEXP (operands
[1], 0)))
7529 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
7533 abort (); /* Should never happen now. */
7537 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
7541 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
7545 abort (); /* Should never happen now. */
7550 output_asm_insn ("adr%?\t%0, %1", operands
);
7551 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
7555 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
7556 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
7558 otherops
[0] = operands
[0];
7559 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
7560 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
7562 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
7564 if (GET_CODE (otherops
[2]) == CONST_INT
)
7566 switch ((int) INTVAL (otherops
[2]))
7569 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
7572 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
7575 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
7579 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
7580 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
7582 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7585 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7588 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
7590 return "ldm%?ia\t%0, %M0";
7594 otherops
[1] = adjust_address (operands
[1], VOIDmode
, 4);
7595 /* Take care of overlapping base/data reg. */
7596 if (reg_mentioned_p (operands
[0], operands
[1]))
7598 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7599 output_asm_insn ("ldr%?\t%0, %1", operands
);
7603 output_asm_insn ("ldr%?\t%0, %1", operands
);
7604 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7610 abort (); /* Constraints should prevent this. */
7612 else if (code0
== MEM
&& code1
== REG
)
7614 if (REGNO (operands
[1]) == IP_REGNUM
)
7617 switch (GET_CODE (XEXP (operands
[0], 0)))
7620 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
7624 abort (); /* Should never happen now. */
7628 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
7632 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
7636 abort (); /* Should never happen now. */
7640 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
7642 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
7645 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
7649 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
7653 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
7660 otherops
[0] = adjust_address (operands
[0], VOIDmode
, 4);
7661 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
7662 output_asm_insn ("str%?\t%1, %0", operands
);
7663 output_asm_insn ("str%?\t%1, %0", otherops
);
7667 /* Constraints should prevent this. */
7674 /* Output an arbitrary MOV reg, #n.
7675 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7678 output_mov_immediate (operands
)
7681 HOST_WIDE_INT n
= INTVAL (operands
[1]);
7683 /* Try to use one MOV. */
7684 if (const_ok_for_arm (n
))
7685 output_asm_insn ("mov%?\t%0, %1", operands
);
7687 /* Try to use one MVN. */
7688 else if (const_ok_for_arm (~n
))
7690 operands
[1] = GEN_INT (~n
);
7691 output_asm_insn ("mvn%?\t%0, %1", operands
);
7698 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7699 for (i
= 0; i
< 32; i
++)
7703 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
7704 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
7706 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
7712 /* Output an ADD r, s, #n where n may be too big for one instruction.
7713 If adding zero to one register, output nothing. */
7716 output_add_immediate (operands
)
7719 HOST_WIDE_INT n
= INTVAL (operands
[2]);
7721 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
7724 output_multi_immediate (operands
,
7725 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7728 output_multi_immediate (operands
,
7729 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7736 /* Output a multiple immediate operation.
7737 OPERANDS is the vector of operands referred to in the output patterns.
7738 INSTR1 is the output pattern to use for the first constant.
7739 INSTR2 is the output pattern to use for subsequent constants.
7740 IMMED_OP is the index of the constant slot in OPERANDS.
7741 N is the constant value. */
7744 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
7746 const char * instr1
;
7747 const char * instr2
;
7751 #if HOST_BITS_PER_WIDE_INT > 32
7757 /* Quick and easy output. */
7758 operands
[immed_op
] = const0_rtx
;
7759 output_asm_insn (instr1
, operands
);
7764 const char * instr
= instr1
;
7766 /* Note that n is never zero here (which would give no output). */
7767 for (i
= 0; i
< 32; i
+= 2)
7771 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
7772 output_asm_insn (instr
, operands
);
7782 /* Return the appropriate ARM instruction for the operation code.
7783 The returned result should not be overwritten. OP is the rtx of the
7784 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7788 arithmetic_instr (op
, shift_first_arg
)
7790 int shift_first_arg
;
7792 switch (GET_CODE (op
))
7798 return shift_first_arg
? "rsb" : "sub";
7814 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7815 for the operation code. The returned result should not be overwritten.
7816 OP is the rtx code of the shift.
7817 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7821 shift_op (op
, amountp
)
7823 HOST_WIDE_INT
*amountp
;
7826 enum rtx_code code
= GET_CODE (op
);
7828 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
7830 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
7831 *amountp
= INTVAL (XEXP (op
, 1));
7854 /* We never have to worry about the amount being other than a
7855 power of 2, since this case can never be reloaded from a reg. */
7857 *amountp
= int_log2 (*amountp
);
7868 /* This is not 100% correct, but follows from the desire to merge
7869 multiplication by a power of 2 with the recognizer for a
7870 shift. >=32 is not a valid shift for "asl", so we must try and
7871 output a shift that produces the correct arithmetical result.
7872 Using lsr #32 is identical except for the fact that the carry bit
7873 is not set correctly if we set the flags; but we never use the
7874 carry bit from such an operation, so we can ignore that. */
7875 if (code
== ROTATERT
)
7876 /* Rotate is just modulo 32. */
7878 else if (*amountp
!= (*amountp
& 31))
7885 /* Shifts of 0 are no-ops. */
7893 /* Obtain the shift from the POWER of two. */
7895 static HOST_WIDE_INT
7897 HOST_WIDE_INT power
;
7899 HOST_WIDE_INT shift
= 0;
7901 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
7911 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7912 /bin/as is horribly restrictive. */
7913 #define MAX_ASCII_LEN 51
7916 output_ascii_pseudo_op (stream
, p
, len
)
7918 const unsigned char * p
;
7924 fputs ("\t.ascii\t\"", stream
);
7926 for (i
= 0; i
< len
; i
++)
7930 if (len_so_far
>= MAX_ASCII_LEN
)
7932 fputs ("\"\n\t.ascii\t\"", stream
);
7939 fputs ("\\t", stream
);
7944 fputs ("\\f", stream
);
7949 fputs ("\\b", stream
);
7954 fputs ("\\r", stream
);
7958 case TARGET_NEWLINE
:
7959 fputs ("\\n", stream
);
7961 if ((c
>= ' ' && c
<= '~')
7963 /* This is a good place for a line break. */
7964 len_so_far
= MAX_ASCII_LEN
;
7971 putc ('\\', stream
);
7976 if (c
>= ' ' && c
<= '~')
7983 fprintf (stream
, "\\%03o", c
);
7990 fputs ("\"\n", stream
);
7993 /* Compute the register sabe mask for registers 0 through 12
7994 inclusive. This code is used by both arm_compute_save_reg_mask
7995 and arm_compute_initial_elimination_offset. */
7997 static unsigned long
7998 arm_compute_save_reg0_reg12_mask ()
8000 unsigned long func_type
= arm_current_func_type ();
8001 unsigned int save_reg_mask
= 0;
8004 if (IS_INTERRUPT (func_type
))
8006 unsigned int max_reg
;
8007 /* Interrupt functions must not corrupt any registers,
8008 even call clobbered ones. If this is a leaf function
8009 we can just examine the registers used by the RTL, but
8010 otherwise we have to assume that whatever function is
8011 called might clobber anything, and so we have to save
8012 all the call-clobbered registers as well. */
8013 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8014 /* FIQ handlers have registers r8 - r12 banked, so
8015 we only need to check r0 - r7, Normal ISRs only
8016 bank r14 and r15, so we must check up to r12.
8017 r13 is the stack pointer which is always preserved,
8018 so we do not need to consider it here. */
8023 for (reg
= 0; reg
<= max_reg
; reg
++)
8024 if (regs_ever_live
[reg
]
8025 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8026 save_reg_mask
|= (1 << reg
);
8030 /* In the normal case we only need to save those registers
8031 which are call saved and which are used by this function. */
8032 for (reg
= 0; reg
<= 10; reg
++)
8033 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8034 save_reg_mask
|= (1 << reg
);
8036 /* Handle the frame pointer as a special case. */
8037 if (! TARGET_APCS_FRAME
8038 && ! frame_pointer_needed
8039 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8040 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8041 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8043 /* If we aren't loading the PIC register,
8044 don't stack it even though it may be live. */
8046 && ! TARGET_SINGLE_PIC_BASE
8047 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
8048 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8051 return save_reg_mask
;
8054 /* Compute a bit mask of which registers need to be
8055 saved on the stack for the current function. */
8057 static unsigned long
8058 arm_compute_save_reg_mask ()
8060 unsigned int save_reg_mask
= 0;
8061 unsigned long func_type
= arm_current_func_type ();
8063 if (IS_NAKED (func_type
))
8064 /* This should never really happen. */
8067 /* If we are creating a stack frame, then we must save the frame pointer,
8068 IP (which will hold the old stack pointer), LR and the PC. */
8069 if (frame_pointer_needed
)
8071 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
8076 /* Volatile functions do not return, so there
8077 is no need to save any other registers. */
8078 if (IS_VOLATILE (func_type
))
8079 return save_reg_mask
;
8081 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
8083 /* Decide if we need to save the link register.
8084 Interrupt routines have their own banked link register,
8085 so they never need to save it.
8086 Otherwise if we do not use the link register we do not need to save
8087 it. If we are pushing other registers onto the stack however, we
8088 can save an instruction in the epilogue by pushing the link register
8089 now and then popping it back into the PC. This incurs extra memory
8090 accesses though, so we only do it when optimising for size, and only
8091 if we know that we will not need a fancy return sequence. */
8092 if (regs_ever_live
[LR_REGNUM
]
8095 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
8096 save_reg_mask
|= 1 << LR_REGNUM
;
8098 if (cfun
->machine
->lr_save_eliminated
)
8099 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8101 return save_reg_mask
;
8104 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
8105 everything bar the final return instruction. */
8108 output_return_instruction (operand
, really_return
, reverse
)
8113 char conditional
[10];
8116 unsigned long live_regs_mask
;
8117 unsigned long func_type
;
8119 func_type
= arm_current_func_type ();
8121 if (IS_NAKED (func_type
))
8124 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8126 /* If this function was declared non-returning, and we have found a tail
8127 call, then we have to trust that the called function won't return. */
8132 /* Otherwise, trap an attempted return by aborting. */
8134 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
8136 assemble_external_libcall (ops
[1]);
8137 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
8143 if (current_function_calls_alloca
&& !really_return
)
8146 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
8148 return_used_this_function
= 1;
8150 live_regs_mask
= arm_compute_save_reg_mask ();
8154 const char * return_reg
;
8156 /* If we do not have any special requirements for function exit
8157 (eg interworking, or ISR) then we can load the return address
8158 directly into the PC. Otherwise we must load it into LR. */
8160 && ! TARGET_INTERWORK
)
8161 return_reg
= reg_names
[PC_REGNUM
];
8163 return_reg
= reg_names
[LR_REGNUM
];
8165 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
8166 /* There are two possible reasons for the IP register being saved.
8167 Either a stack frame was created, in which case IP contains the
8168 old stack pointer, or an ISR routine corrupted it. If this in an
8169 ISR routine then just restore IP, otherwise restore IP into SP. */
8170 if (! IS_INTERRUPT (func_type
))
8172 live_regs_mask
&= ~ (1 << IP_REGNUM
);
8173 live_regs_mask
|= (1 << SP_REGNUM
);
8176 /* On some ARM architectures it is faster to use LDR rather than
8177 LDM to load a single register. On other architectures, the
8178 cost is the same. In 26 bit mode, or for exception handlers,
8179 we have to use LDM to load the PC so that the CPSR is also
8181 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8183 if (live_regs_mask
== (unsigned int)(1 << reg
))
8186 if (reg
<= LAST_ARM_REGNUM
8187 && (reg
!= LR_REGNUM
8189 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
8191 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
8192 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
8199 /* Generate the load multiple instruction to restore the registers. */
8200 if (frame_pointer_needed
)
8201 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
8202 else if (live_regs_mask
& (1 << SP_REGNUM
))
8203 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
8205 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
8207 p
= instr
+ strlen (instr
);
8209 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
8210 if (live_regs_mask
& (1 << reg
))
8212 int l
= strlen (reg_names
[reg
]);
8218 memcpy (p
, ", ", 2);
8222 memcpy (p
, "%|", 2);
8223 memcpy (p
+ 2, reg_names
[reg
], l
);
8227 if (live_regs_mask
& (1 << LR_REGNUM
))
8229 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
8230 /* Decide if we need to add the ^ symbol to the end of the
8231 register list. This causes the saved condition codes
8232 register to be copied into the current condition codes
8233 register. We do the copy if we are conforming to the 32-bit
8234 ABI and this is an interrupt function, or if we are
8235 conforming to the 26-bit ABI. There is a special case for
8236 the 26-bit ABI however, which is if we are writing back the
8237 stack pointer but not loading the PC. In this case adding
8238 the ^ symbol would create a type 2 LDM instruction, where
8239 writeback is UNPREDICTABLE. We are safe in leaving the ^
8240 character off in this case however, since the actual return
8241 instruction will be a MOVS which will restore the CPSR. */
8242 if ((TARGET_APCS_32
&& IS_INTERRUPT (func_type
))
8243 || (! TARGET_APCS_32
&& really_return
))
8250 output_asm_insn (instr
, & operand
);
8252 /* See if we need to generate an extra instruction to
8253 perform the actual function return. */
8255 && func_type
!= ARM_FT_INTERWORKED
8256 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8258 /* The return has already been handled
8259 by loading the LR into the PC. */
8266 switch ((int) ARM_FUNC_TYPE (func_type
))
8270 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
8273 case ARM_FT_INTERWORKED
:
8274 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8277 case ARM_FT_EXCEPTION
:
8278 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
8282 /* ARMv5 implementations always provide BX, so interworking
8283 is the default unless APCS-26 is in use. */
8284 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
8285 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8287 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
8288 conditional
, TARGET_APCS_32
? "" : "s");
8292 output_asm_insn (instr
, & operand
);
8298 /* Write the function name into the code section, directly preceding
8299 the function prologue.
8301 Code will be output similar to this:
8303 .ascii "arm_poke_function_name", 0
8306 .word 0xff000000 + (t1 - t0)
8307 arm_poke_function_name
8309 stmfd sp!, {fp, ip, lr, pc}
8312 When performing a stack backtrace, code can inspect the value
8313 of 'pc' stored at 'fp' + 0. If the trace function then looks
8314 at location pc - 12 and the top 8 bits are set, then we know
8315 that there is a function name embedded immediately preceding this
8316 location and has length ((pc[-3]) & 0xff000000).
8318 We assume that pc is declared as a pointer to an unsigned long.
8320 It is of no benefit to output the function name if we are assembling
8321 a leaf function. These function types will not contain a stack
8322 backtrace structure, therefore it is not possible to determine the
8326 arm_poke_function_name (stream
, name
)
8330 unsigned long alignlength
;
8331 unsigned long length
;
8334 length
= strlen (name
) + 1;
8335 alignlength
= ROUND_UP_WORD (length
);
8337 ASM_OUTPUT_ASCII (stream
, name
, length
);
8338 ASM_OUTPUT_ALIGN (stream
, 2);
8339 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
8340 assemble_aligned_integer (UNITS_PER_WORD
, x
);
8343 /* Place some comments into the assembler stream
8344 describing the current function. */
8347 arm_output_function_prologue (f
, frame_size
)
8349 HOST_WIDE_INT frame_size
;
8351 unsigned long func_type
;
8355 thumb_output_function_prologue (f
, frame_size
);
8360 if (arm_ccfsm_state
|| arm_target_insn
)
8363 func_type
= arm_current_func_type ();
8365 switch ((int) ARM_FUNC_TYPE (func_type
))
8370 case ARM_FT_INTERWORKED
:
8371 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
8373 case ARM_FT_EXCEPTION_HANDLER
:
8374 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
8377 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
8380 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
8382 case ARM_FT_EXCEPTION
:
8383 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
8387 if (IS_NAKED (func_type
))
8388 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8390 if (IS_VOLATILE (func_type
))
8391 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
8393 if (IS_NESTED (func_type
))
8394 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
8396 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
8397 current_function_args_size
,
8398 current_function_pretend_args_size
, frame_size
);
8400 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8401 frame_pointer_needed
,
8402 cfun
->machine
->uses_anonymous_args
);
8404 if (cfun
->machine
->lr_save_eliminated
)
8405 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
8407 #ifdef AOF_ASSEMBLER
8409 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
8412 return_used_this_function
= 0;
8416 arm_output_epilogue (really_return
)
8420 unsigned long saved_regs_mask
;
8421 unsigned long func_type
;
8422 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8423 frame that is $fp + 4 for a non-variadic function. */
8424 int floats_offset
= 0;
8426 int frame_size
= arm_get_frame_size ();
8427 FILE * f
= asm_out_file
;
8428 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
8430 /* If we have already generated the return instruction
8431 then it is futile to generate anything else. */
8432 if (use_return_insn (FALSE
) && return_used_this_function
)
8435 func_type
= arm_current_func_type ();
8437 if (IS_NAKED (func_type
))
8438 /* Naked functions don't have epilogues. */
8441 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8445 /* A volatile function should never return. Call abort. */
8446 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
8447 assemble_external_libcall (op
);
8448 output_asm_insn ("bl\t%a0", &op
);
8453 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
8455 /* If we are throwing an exception, then we really must
8456 be doing a return, so we can't tail-call. */
8459 saved_regs_mask
= arm_compute_save_reg_mask ();
8461 /* XXX We should adjust floats_offset for any anonymous args, and then
8462 re-adjust vfp_offset below to compensate. */
8464 /* Compute how far away the floats will be. */
8465 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8466 if (saved_regs_mask
& (1 << reg
))
8469 if (frame_pointer_needed
)
8473 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8475 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8476 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8478 floats_offset
+= 12;
8479 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
8480 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8485 int start_reg
= LAST_ARM_FP_REGNUM
;
8487 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8489 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8491 floats_offset
+= 12;
8493 /* We can't unstack more than four registers at once. */
8494 if (start_reg
- reg
== 3)
8496 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
8497 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8498 start_reg
= reg
- 1;
8503 if (reg
!= start_reg
)
8504 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8505 reg
+ 1, start_reg
- reg
,
8506 FP_REGNUM
, floats_offset
- vfp_offset
);
8507 start_reg
= reg
- 1;
8511 /* Just in case the last register checked also needs unstacking. */
8512 if (reg
!= start_reg
)
8513 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8514 reg
+ 1, start_reg
- reg
,
8515 FP_REGNUM
, floats_offset
- vfp_offset
);
8518 /* saved_regs_mask should contain the IP, which at the time of stack
8519 frame generation actually contains the old stack pointer. So a
8520 quick way to unwind the stack is just pop the IP register directly
8521 into the stack pointer. */
8522 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
8524 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
8525 saved_regs_mask
|= (1 << SP_REGNUM
);
8527 /* There are two registers left in saved_regs_mask - LR and PC. We
8528 only need to restore the LR register (the return address), but to
8529 save time we can load it directly into the PC, unless we need a
8530 special function exit sequence, or we are not really returning. */
8531 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
8532 /* Delete the LR from the register mask, so that the LR on
8533 the stack is loaded into the PC in the register mask. */
8534 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8536 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
8538 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
8540 if (IS_INTERRUPT (func_type
))
8541 /* Interrupt handlers will have pushed the
8542 IP onto the stack, so restore it now. */
8543 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
8547 /* Restore stack pointer if necessary. */
8548 if (frame_size
+ current_function_outgoing_args_size
!= 0)
8550 operands
[0] = operands
[1] = stack_pointer_rtx
;
8551 operands
[2] = GEN_INT (frame_size
8552 + current_function_outgoing_args_size
);
8553 output_add_immediate (operands
);
8556 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8558 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8559 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8560 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
8565 int start_reg
= FIRST_ARM_FP_REGNUM
;
8567 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8569 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8571 if (reg
- start_reg
== 3)
8573 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
8574 start_reg
, SP_REGNUM
);
8575 start_reg
= reg
+ 1;
8580 if (reg
!= start_reg
)
8581 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8582 start_reg
, reg
- start_reg
,
8585 start_reg
= reg
+ 1;
8589 /* Just in case the last register checked also needs unstacking. */
8590 if (reg
!= start_reg
)
8591 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8592 start_reg
, reg
- start_reg
, SP_REGNUM
);
8595 /* If we can, restore the LR into the PC. */
8596 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8598 && current_function_pretend_args_size
== 0
8599 && saved_regs_mask
& (1 << LR_REGNUM
))
8601 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8602 saved_regs_mask
|= (1 << PC_REGNUM
);
8605 /* Load the registers off the stack. If we only have one register
8606 to load use the LDR instruction - it is faster. */
8607 if (saved_regs_mask
== (1 << LR_REGNUM
))
8609 /* The exception handler ignores the LR, so we do
8610 not really need to load it off the stack. */
8612 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
8614 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
8616 else if (saved_regs_mask
)
8618 if (saved_regs_mask
& (1 << SP_REGNUM
))
8619 /* Note - write back to the stack register is not enabled
8620 (ie "ldmfd sp!..."). We know that the stack pointer is
8621 in the list of registers and if we add writeback the
8622 instruction becomes UNPREDICTABLE. */
8623 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
8625 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
8628 if (current_function_pretend_args_size
)
8630 /* Unwind the pre-pushed regs. */
8631 operands
[0] = operands
[1] = stack_pointer_rtx
;
8632 operands
[2] = GEN_INT (current_function_pretend_args_size
);
8633 output_add_immediate (operands
);
8638 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
)
8639 /* Adjust the stack to remove the exception handler stuff. */
8640 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
8645 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8646 && current_function_pretend_args_size
== 0
8647 && saved_regs_mask
& (1 << PC_REGNUM
)))
8650 /* Generate the return instruction. */
8651 switch ((int) ARM_FUNC_TYPE (func_type
))
8653 case ARM_FT_EXCEPTION_HANDLER
:
8654 /* Even in 26-bit mode we do a mov (rather than a movs)
8655 because we don't have the PSR bits set in the address. */
8656 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
8661 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
8664 case ARM_FT_EXCEPTION
:
8665 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8668 case ARM_FT_INTERWORKED
:
8669 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
8673 if (frame_pointer_needed
)
8674 /* If we used the frame pointer then the return address
8675 will have been loaded off the stack directly into the
8676 PC, so there is no need to issue a MOV instruction
8679 else if (current_function_pretend_args_size
== 0
8680 && (saved_regs_mask
& (1 << LR_REGNUM
)))
8681 /* Similarly we may have been able to load LR into the PC
8682 even if we did not create a stack frame. */
8684 else if (TARGET_APCS_32
)
8685 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8687 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8695 arm_output_function_epilogue (file
, frame_size
)
8696 FILE *file ATTRIBUTE_UNUSED
;
8697 HOST_WIDE_INT frame_size
;
8701 /* ??? Probably not safe to set this here, since it assumes that a
8702 function will be emitted as assembly immediately after we generate
8703 RTL for it. This does not happen for inline functions. */
8704 return_used_this_function
= 0;
8708 /* We need to take into account any stack-frame rounding. */
8709 frame_size
= arm_get_frame_size ();
8711 if (use_return_insn (FALSE
)
8712 && return_used_this_function
8713 && (frame_size
+ current_function_outgoing_args_size
) != 0
8714 && !frame_pointer_needed
)
8717 /* Reset the ARM-specific per-function variables. */
8718 after_arm_reorg
= 0;
8722 /* Generate and emit an insn that we will recognize as a push_multi.
8723 Unfortunately, since this insn does not reflect very well the actual
8724 semantics of the operation, we need to annotate the insn for the benefit
8725 of DWARF2 frame unwind information. */
8728 emit_multi_reg_push (mask
)
8736 int dwarf_par_index
;
8739 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8740 if (mask
& (1 << i
))
8743 if (num_regs
== 0 || num_regs
> 16)
8746 /* We don't record the PC in the dwarf frame information. */
8747 num_dwarf_regs
= num_regs
;
8748 if (mask
& (1 << PC_REGNUM
))
8751 /* For the body of the insn we are going to generate an UNSPEC in
8752 parallel with several USEs. This allows the insn to be recognized
8753 by the push_multi pattern in the arm.md file. The insn looks
8754 something like this:
8757 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8758 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8759 (use (reg:SI 11 fp))
8760 (use (reg:SI 12 ip))
8761 (use (reg:SI 14 lr))
8762 (use (reg:SI 15 pc))
8765 For the frame note however, we try to be more explicit and actually
8766 show each register being stored into the stack frame, plus a (single)
8767 decrement of the stack pointer. We do it this way in order to be
8768 friendly to the stack unwinding code, which only wants to see a single
8769 stack decrement per instruction. The RTL we generate for the note looks
8770 something like this:
8773 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8774 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8775 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8776 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8777 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8780 This sequence is used both by the code to support stack unwinding for
8781 exceptions handlers and the code to generate dwarf2 frame debugging. */
8783 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
8784 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
8785 dwarf_par_index
= 1;
8787 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8789 if (mask
& (1 << i
))
8791 reg
= gen_rtx_REG (SImode
, i
);
8794 = gen_rtx_SET (VOIDmode
,
8795 gen_rtx_MEM (BLKmode
,
8796 gen_rtx_PRE_DEC (BLKmode
,
8797 stack_pointer_rtx
)),
8798 gen_rtx_UNSPEC (BLKmode
,
8804 tmp
= gen_rtx_SET (VOIDmode
,
8805 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
8807 RTX_FRAME_RELATED_P (tmp
) = 1;
8808 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
8816 for (j
= 1, i
++; j
< num_regs
; i
++)
8818 if (mask
& (1 << i
))
8820 reg
= gen_rtx_REG (SImode
, i
);
8822 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
8826 tmp
= gen_rtx_SET (VOIDmode
,
8827 gen_rtx_MEM (SImode
,
8828 plus_constant (stack_pointer_rtx
,
8831 RTX_FRAME_RELATED_P (tmp
) = 1;
8832 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
8839 par
= emit_insn (par
);
8841 tmp
= gen_rtx_SET (SImode
,
8843 gen_rtx_PLUS (SImode
,
8845 GEN_INT (-4 * num_regs
)));
8846 RTX_FRAME_RELATED_P (tmp
) = 1;
8847 XVECEXP (dwarf
, 0, 0) = tmp
;
8849 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8855 emit_sfm (base_reg
, count
)
8864 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8865 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8867 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8870 = gen_rtx_SET (VOIDmode
,
8871 gen_rtx_MEM (BLKmode
,
8872 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8873 gen_rtx_UNSPEC (BLKmode
,
8877 = gen_rtx_SET (VOIDmode
,
8878 gen_rtx_MEM (XFmode
,
8879 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8881 RTX_FRAME_RELATED_P (tmp
) = 1;
8882 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
8884 for (i
= 1; i
< count
; i
++)
8886 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8887 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8889 tmp
= gen_rtx_SET (VOIDmode
,
8890 gen_rtx_MEM (XFmode
,
8891 gen_rtx_PRE_DEC (BLKmode
,
8892 stack_pointer_rtx
)),
8894 RTX_FRAME_RELATED_P (tmp
) = 1;
8895 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
8898 par
= emit_insn (par
);
8899 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8904 /* Compute the distance from register FROM to register TO.
8905 These can be the arg pointer (26), the soft frame pointer (25),
8906 the stack pointer (13) or the hard frame pointer (11).
8907 Typical stack layout looks like this:
8909 old stack pointer -> | |
8912 | | saved arguments for
8913 | | vararg functions
8916 hard FP & arg pointer -> | | \
8924 soft frame pointer -> | | /
8934 current stack pointer -> | | /
8937 For a given function some or all of these stack components
8938 may not be needed, giving rise to the possibility of
8939 eliminating some of the registers.
8941 The values returned by this function must reflect the behavior
8942 of arm_expand_prologue() and arm_compute_save_reg_mask().
8944 The sign of the number returned reflects the direction of stack
8945 growth, so the values are positive for all eliminations except
8946 from the soft frame pointer to the hard frame pointer. */
8949 arm_compute_initial_elimination_offset (from
, to
)
8953 unsigned int local_vars
= arm_get_frame_size ();
8954 unsigned int outgoing_args
= current_function_outgoing_args_size
;
8955 unsigned int stack_frame
;
8956 unsigned int call_saved_registers
;
8957 unsigned long func_type
;
8959 func_type
= arm_current_func_type ();
8961 /* Volatile functions never return, so there is
8962 no need to save call saved registers. */
8963 call_saved_registers
= 0;
8964 if (! IS_VOLATILE (func_type
))
8966 unsigned int reg_mask
;
8969 /* Make sure that we compute which registers will be saved
8970 on the stack using the same algorithm that is used by
8971 arm_compute_save_reg_mask(). */
8972 reg_mask
= arm_compute_save_reg0_reg12_mask ();
8974 /* Now count the number of bits set in save_reg_mask.
8975 For each set bit we need 4 bytes of stack space. */
8978 call_saved_registers
+= 4;
8979 reg_mask
= reg_mask
& ~ (reg_mask
& - reg_mask
);
8982 if ((regs_ever_live
[LR_REGNUM
]
8983 /* If optimizing for size, then we save the link register if
8984 any other integer register is saved. This gives a smaller
8986 || (optimize_size
&& call_saved_registers
> 0))
8987 /* But if a stack frame is going to be created, the LR will
8988 be saved as part of that, so we do not need to allow for
8990 && ! frame_pointer_needed
)
8991 call_saved_registers
+= 4;
8993 /* If the hard floating point registers are going to be
8994 used then they must be saved on the stack as well.
8995 Each register occupies 12 bytes of stack space. */
8996 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8997 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8998 call_saved_registers
+= 12;
9001 /* The stack frame contains 4 registers - the old frame pointer,
9002 the old stack pointer, the return address and PC of the start
9004 stack_frame
= frame_pointer_needed
? 16 : 0;
9006 /* OK, now we have enough information to compute the distances.
9007 There must be an entry in these switch tables for each pair
9008 of registers in ELIMINABLE_REGS, even if some of the entries
9009 seem to be redundant or useless. */
9012 case ARG_POINTER_REGNUM
:
9015 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9018 case FRAME_POINTER_REGNUM
:
9019 /* This is the reverse of the soft frame pointer
9020 to hard frame pointer elimination below. */
9021 if (call_saved_registers
== 0 && stack_frame
== 0)
9023 return (call_saved_registers
+ stack_frame
- 4);
9025 case ARM_HARD_FRAME_POINTER_REGNUM
:
9026 /* If there is no stack frame then the hard
9027 frame pointer and the arg pointer coincide. */
9028 if (stack_frame
== 0 && call_saved_registers
!= 0)
9030 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9031 return (frame_pointer_needed
9032 && current_function_needs_context
9033 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
9035 case STACK_POINTER_REGNUM
:
9036 /* If nothing has been pushed on the stack at all
9037 then this will return -4. This *is* correct! */
9038 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
9045 case FRAME_POINTER_REGNUM
:
9048 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9051 case ARM_HARD_FRAME_POINTER_REGNUM
:
9052 /* The hard frame pointer points to the top entry in the
9053 stack frame. The soft frame pointer to the bottom entry
9054 in the stack frame. If there is no stack frame at all,
9055 then they are identical. */
9056 if (call_saved_registers
== 0 && stack_frame
== 0)
9058 return - (call_saved_registers
+ stack_frame
- 4);
9060 case STACK_POINTER_REGNUM
:
9061 return local_vars
+ outgoing_args
;
9069 /* You cannot eliminate from the stack pointer.
9070 In theory you could eliminate from the hard frame
9071 pointer to the stack pointer, but this will never
9072 happen, since if a stack frame is not needed the
9073 hard frame pointer will never be used. */
9078 /* Calculate the size of the stack frame, taking into account any
9079 padding that is required to ensure stack-alignment. */
9082 arm_get_frame_size ()
9086 int base_size
= ROUND_UP_WORD (get_frame_size ());
9088 unsigned long func_type
= arm_current_func_type ();
9097 /* We need to know if we are a leaf function. Unfortunately, it
9098 is possible to be called after start_sequence has been called,
9099 which causes get_insns to return the insns for the sequence,
9100 not the function, which will cause leaf_function_p to return
9101 the incorrect result.
9103 To work around this, we cache the computed frame size. This
9104 works because we will only be calling RTL expanders that need
9105 to know about leaf functions once reload has completed, and the
9106 frame size cannot be changed after that time, so we can safely
9107 use the cached value. */
9109 if (reload_completed
)
9110 return cfun
->machine
->frame_size
;
9112 leaf
= leaf_function_p ();
9114 /* A leaf function does not need any stack alignment if it has nothing
9116 if (leaf
&& base_size
== 0)
9118 cfun
->machine
->frame_size
= 0;
9122 /* We know that SP will be word aligned on entry, and we must
9123 preserve that condition at any subroutine call. But those are
9124 the only constraints. */
9126 /* Space for variadic functions. */
9127 if (current_function_pretend_args_size
)
9128 entry_size
+= current_function_pretend_args_size
;
9130 /* Space for saved registers. */
9131 entry_size
+= bit_count (arm_compute_save_reg_mask ()) * 4;
9133 /* Space for saved FPA registers. */
9134 if (! IS_VOLATILE (func_type
))
9136 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
9137 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9141 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9143 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9146 cfun
->machine
->frame_size
= base_size
;
9151 /* Generate the prologue instructions for entry into an ARM function. */
9154 arm_expand_prologue ()
9160 unsigned long live_regs_mask
;
9161 unsigned long func_type
;
9163 int saved_pretend_args
= 0;
9164 unsigned int args_to_push
;
9166 func_type
= arm_current_func_type ();
9168 /* Naked functions don't have prologues. */
9169 if (IS_NAKED (func_type
))
9172 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9173 args_to_push
= current_function_pretend_args_size
;
9175 /* Compute which register we will have to save onto the stack. */
9176 live_regs_mask
= arm_compute_save_reg_mask ();
9178 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
9180 if (frame_pointer_needed
)
9182 if (IS_INTERRUPT (func_type
))
9184 /* Interrupt functions must not corrupt any registers.
9185 Creating a frame pointer however, corrupts the IP
9186 register, so we must push it first. */
9187 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
9189 /* Do not set RTX_FRAME_RELATED_P on this insn.
9190 The dwarf stack unwinding code only wants to see one
9191 stack decrement per function, and this is not it. If
9192 this instruction is labeled as being part of the frame
9193 creation sequence then dwarf2out_frame_debug_expr will
9194 abort when it encounters the assignment of IP to FP
9195 later on, since the use of SP here establishes SP as
9196 the CFA register and not IP.
9198 Anyway this instruction is not really part of the stack
9199 frame creation although it is part of the prologue. */
9201 else if (IS_NESTED (func_type
))
9203 /* The Static chain register is the same as the IP register
9204 used as a scratch register during stack frame creation.
9205 To get around this need to find somewhere to store IP
9206 whilst the frame is being created. We try the following
9209 1. The last argument register.
9210 2. A slot on the stack above the frame. (This only
9211 works if the function is not a varargs function).
9212 3. Register r3, after pushing the argument registers
9215 Note - we only need to tell the dwarf2 backend about the SP
9216 adjustment in the second variant; the static chain register
9217 doesn't need to be unwound, as it doesn't contain a value
9218 inherited from the caller. */
9220 if (regs_ever_live
[3] == 0)
9222 insn
= gen_rtx_REG (SImode
, 3);
9223 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9224 insn
= emit_insn (insn
);
9226 else if (args_to_push
== 0)
9229 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
9230 insn
= gen_rtx_MEM (SImode
, insn
);
9231 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
9232 insn
= emit_insn (insn
);
9236 /* Just tell the dwarf backend that we adjusted SP. */
9237 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9238 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
9239 GEN_INT (-fp_offset
)));
9240 RTX_FRAME_RELATED_P (insn
) = 1;
9241 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9242 dwarf
, REG_NOTES (insn
));
9246 /* Store the args on the stack. */
9247 if (cfun
->machine
->uses_anonymous_args
)
9248 insn
= emit_multi_reg_push
9249 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9252 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9253 GEN_INT (- args_to_push
)));
9255 RTX_FRAME_RELATED_P (insn
) = 1;
9257 saved_pretend_args
= 1;
9258 fp_offset
= args_to_push
;
9261 /* Now reuse r3 to preserve IP. */
9262 insn
= gen_rtx_REG (SImode
, 3);
9263 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9264 (void) emit_insn (insn
);
9270 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
9271 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
9274 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
9276 insn
= emit_insn (insn
);
9277 RTX_FRAME_RELATED_P (insn
) = 1;
9282 /* Push the argument registers, or reserve space for them. */
9283 if (cfun
->machine
->uses_anonymous_args
)
9284 insn
= emit_multi_reg_push
9285 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9288 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9289 GEN_INT (- args_to_push
)));
9290 RTX_FRAME_RELATED_P (insn
) = 1;
9293 /* If this is an interrupt service routine, and the link register
9294 is going to be pushed, and we are not creating a stack frame,
9295 (which would involve an extra push of IP and a pop in the epilogue)
9296 subtracting four from LR now will mean that the function return
9297 can be done with a single instruction. */
9298 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
9299 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
9300 && ! frame_pointer_needed
)
9301 emit_insn (gen_rtx_SET (SImode
,
9302 gen_rtx_REG (SImode
, LR_REGNUM
),
9303 gen_rtx_PLUS (SImode
,
9304 gen_rtx_REG (SImode
, LR_REGNUM
),
9309 insn
= emit_multi_reg_push (live_regs_mask
);
9310 RTX_FRAME_RELATED_P (insn
) = 1;
9313 if (! IS_VOLATILE (func_type
))
9315 /* Save any floating point call-saved registers used by this
9317 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9319 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9320 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9322 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
9323 insn
= gen_rtx_MEM (XFmode
, insn
);
9324 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9325 gen_rtx_REG (XFmode
, reg
)));
9326 RTX_FRAME_RELATED_P (insn
) = 1;
9331 int start_reg
= LAST_ARM_FP_REGNUM
;
9333 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9335 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9337 if (start_reg
- reg
== 3)
9339 insn
= emit_sfm (reg
, 4);
9340 RTX_FRAME_RELATED_P (insn
) = 1;
9341 start_reg
= reg
- 1;
9346 if (start_reg
!= reg
)
9348 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9349 RTX_FRAME_RELATED_P (insn
) = 1;
9351 start_reg
= reg
- 1;
9355 if (start_reg
!= reg
)
9357 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9358 RTX_FRAME_RELATED_P (insn
) = 1;
9363 if (frame_pointer_needed
)
9365 /* Create the new frame pointer. */
9366 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
9367 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
9368 RTX_FRAME_RELATED_P (insn
) = 1;
9370 if (IS_NESTED (func_type
))
9372 /* Recover the static chain register. */
9373 if (regs_ever_live
[3] == 0
9374 || saved_pretend_args
)
9375 insn
= gen_rtx_REG (SImode
, 3);
9376 else /* if (current_function_pretend_args_size == 0) */
9378 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
9380 insn
= gen_rtx_MEM (SImode
, insn
);
9383 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
9384 /* Add a USE to stop propagate_one_insn() from barfing. */
9385 emit_insn (gen_prologue_use (ip_rtx
));
9389 amount
= GEN_INT (-(arm_get_frame_size ()
9390 + current_function_outgoing_args_size
));
9392 if (amount
!= const0_rtx
)
9394 /* This add can produce multiple insns for a large constant, so we
9395 need to get tricky. */
9396 rtx last
= get_last_insn ();
9397 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9401 last
= last
? NEXT_INSN (last
) : get_insns ();
9402 RTX_FRAME_RELATED_P (last
) = 1;
9404 while (last
!= insn
);
9406 /* If the frame pointer is needed, emit a special barrier that
9407 will prevent the scheduler from moving stores to the frame
9408 before the stack adjustment. */
9409 if (frame_pointer_needed
)
9410 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
9411 hard_frame_pointer_rtx
));
9414 /* If we are profiling, make sure no instructions are scheduled before
9415 the call to mcount. Similarly if the user has requested no
9416 scheduling in the prolog. */
9417 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
9418 emit_insn (gen_blockage ());
9420 /* If the link register is being kept alive, with the return address in it,
9421 then make sure that it does not get reused by the ce2 pass. */
9422 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
9424 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
9425 cfun
->machine
->lr_save_eliminated
= 1;
9429 /* If CODE is 'd', then the X is a condition operand and the instruction
9430 should only be executed if the condition is true.
9431 if CODE is 'D', then the X is a condition operand and the instruction
9432 should only be executed if the condition is false: however, if the mode
9433 of the comparison is CCFPEmode, then always execute the instruction -- we
9434 do this because in these circumstances !GE does not necessarily imply LT;
9435 in these cases the instruction pattern will take care to make sure that
9436 an instruction containing %d will follow, thereby undoing the effects of
9437 doing this instruction unconditionally.
9438 If CODE is 'N' then X is a floating point operand that must be negated
9440 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9441 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9444 arm_print_operand (stream
, x
, code
)
9452 fputs (ASM_COMMENT_START
, stream
);
9456 fputs (user_label_prefix
, stream
);
9460 fputs (REGISTER_PREFIX
, stream
);
9464 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
9466 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
9469 fputs (arm_condition_codes
[arm_current_cc
], stream
);
9471 else if (current_insn_predicate
)
9473 enum arm_cond_code code
;
9478 code
= get_arm_condition_code (current_insn_predicate
);
9479 fputs (arm_condition_codes
[code
], stream
);
9486 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
9487 r
= REAL_VALUE_NEGATE (r
);
9488 fprintf (stream
, "%s", fp_const_from_val (&r
));
9493 if (GET_CODE (x
) == CONST_INT
)
9496 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
9497 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
9502 output_addr_const (stream
, x
);
9507 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
9510 /* Truncate Cirrus shift counts. */
9512 if (GET_CODE (x
) == CONST_INT
)
9514 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
9517 arm_print_operand (stream
, x
, 0);
9521 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
9527 const char * shift
= shift_op (x
, &val
);
9531 fprintf (stream
, ", %s ", shift_op (x
, &val
));
9533 arm_print_operand (stream
, XEXP (x
, 1), 0);
9536 fputc ('#', stream
);
9537 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
9543 /* An explanation of the 'Q', 'R' and 'H' register operands:
9545 In a pair of registers containing a DI or DF value the 'Q'
9546 operand returns the register number of the register containing
9547 the least signficant part of the value. The 'R' operand returns
9548 the register number of the register containing the most
9549 significant part of the value.
9551 The 'H' operand returns the higher of the two register numbers.
9552 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9553 same as the 'Q' operand, since the most signficant part of the
9554 value is held in the lower number register. The reverse is true
9555 on systems where WORDS_BIG_ENDIAN is false.
9557 The purpose of these operands is to distinguish between cases
9558 where the endian-ness of the values is important (for example
9559 when they are added together), and cases where the endian-ness
9560 is irrelevant, but the order of register operations is important.
9561 For example when loading a value from memory into a register
9562 pair, the endian-ness does not matter. Provided that the value
9563 from the lower memory address is put into the lower numbered
9564 register, and the value from the higher address is put into the
9565 higher numbered register, the load will work regardless of whether
9566 the value being loaded is big-wordian or little-wordian. The
9567 order of the two register loads can matter however, if the address
9568 of the memory location is actually held in one of the registers
9569 being overwritten by the load. */
9571 if (REGNO (x
) > LAST_ARM_REGNUM
)
9573 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
9577 if (REGNO (x
) > LAST_ARM_REGNUM
)
9579 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
9583 if (REGNO (x
) > LAST_ARM_REGNUM
)
9585 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
9589 asm_fprintf (stream
, "%r",
9590 GET_CODE (XEXP (x
, 0)) == REG
9591 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
9595 asm_fprintf (stream
, "{%r-%r}",
9597 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
9601 /* CONST_TRUE_RTX means always -- that's the default. */
9602 if (x
== const_true_rtx
)
9606 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
9609 fputs (thumb_condition_code (x
, 0), stream
);
9613 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9615 if (x
== const_true_rtx
)
9619 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
9620 (get_arm_condition_code (x
))],
9623 fputs (thumb_condition_code (x
, 1), stream
);
9627 /* Cirrus registers can be accessed in a variety of ways:
9628 single floating point (f)
9629 double floating point (d)
9631 64bit integer (dx). */
9632 case 'W': /* Cirrus register in F mode. */
9633 case 'X': /* Cirrus register in D mode. */
9634 case 'Y': /* Cirrus register in FX mode. */
9635 case 'Z': /* Cirrus register in DX mode. */
9636 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9639 fprintf (stream
, "mv%s%s",
9642 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
9646 /* Print cirrus register in the mode specified by the register's mode. */
9649 int mode
= GET_MODE (x
);
9651 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9654 fprintf (stream
, "mv%s%s",
9655 mode
== DFmode
? "d"
9656 : mode
== SImode
? "fx"
9657 : mode
== DImode
? "dx"
9658 : "f", reg_names
[REGNO (x
)] + 2);
9667 if (GET_CODE (x
) == REG
)
9668 asm_fprintf (stream
, "%r", REGNO (x
));
9669 else if (GET_CODE (x
) == MEM
)
9671 output_memory_reference_mode
= GET_MODE (x
);
9672 output_address (XEXP (x
, 0));
9674 else if (GET_CODE (x
) == CONST_DOUBLE
)
9675 fprintf (stream
, "#%s", fp_immediate_constant (x
));
9676 else if (GET_CODE (x
) == NEG
)
9677 abort (); /* This should never happen now. */
9680 fputc ('#', stream
);
9681 output_addr_const (stream
, x
);
9686 #ifndef AOF_ASSEMBLER
9687 /* Target hook for assembling integer objects. The ARM version needs to
9688 handle word-sized values specially. */
9691 arm_assemble_integer (x
, size
, aligned_p
)
9696 if (size
== UNITS_PER_WORD
&& aligned_p
)
9698 fputs ("\t.word\t", asm_out_file
);
9699 output_addr_const (asm_out_file
, x
);
9701 /* Mark symbols as position independent. We only do this in the
9702 .text segment, not in the .data segment. */
9703 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
9704 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
9706 if (GET_CODE (x
) == SYMBOL_REF
9707 && (CONSTANT_POOL_ADDRESS_P (x
)
9708 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x
, 0))))
9709 fputs ("(GOTOFF)", asm_out_file
);
9710 else if (GET_CODE (x
) == LABEL_REF
)
9711 fputs ("(GOTOFF)", asm_out_file
);
9713 fputs ("(GOT)", asm_out_file
);
9715 fputc ('\n', asm_out_file
);
9719 return default_assemble_integer (x
, size
, aligned_p
);
9723 /* A finite state machine takes care of noticing whether or not instructions
9724 can be conditionally executed, and thus decrease execution time and code
9725 size by deleting branch instructions. The fsm is controlled by
9726 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9728 /* The state of the fsm controlling condition codes are:
9729 0: normal, do nothing special
9730 1: make ASM_OUTPUT_OPCODE not output this instruction
9731 2: make ASM_OUTPUT_OPCODE not output this instruction
9732 3: make instructions conditional
9733 4: make instructions conditional
9735 State transitions (state->state by whom under condition):
9736 0 -> 1 final_prescan_insn if the `target' is a label
9737 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9738 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9739 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9740 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9741 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9742 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9743 (the target insn is arm_target_insn).
9745 If the jump clobbers the conditions then we use states 2 and 4.
9747 A similar thing can be done with conditional return insns.
9749 XXX In case the `target' is an unconditional branch, this conditionalising
9750 of the instructions always reduces code size, but not always execution
9751 time. But then, I want to reduce the code size to somewhere near what
9752 /bin/cc produces. */
9754 /* Returns the index of the ARM condition code string in
9755 `arm_condition_codes'. COMPARISON should be an rtx like
9756 `(eq (...) (...))'. */
9758 static enum arm_cond_code
9759 get_arm_condition_code (comparison
)
9762 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
9764 enum rtx_code comp_code
= GET_CODE (comparison
);
9766 if (GET_MODE_CLASS (mode
) != MODE_CC
)
9767 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
9768 XEXP (comparison
, 1));
9772 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
9773 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
9774 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
9775 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
9776 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
9777 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
9778 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
9779 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
9780 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
9781 case CC_DLTUmode
: code
= ARM_CC
;
9784 if (comp_code
!= EQ
&& comp_code
!= NE
)
9787 if (comp_code
== EQ
)
9788 return ARM_INVERSE_CONDITION_CODE (code
);
9794 case NE
: return ARM_NE
;
9795 case EQ
: return ARM_EQ
;
9796 case GE
: return ARM_PL
;
9797 case LT
: return ARM_MI
;
9804 case NE
: return ARM_NE
;
9805 case EQ
: return ARM_EQ
;
9811 /* These encodings assume that AC=1 in the FPA system control
9812 byte. This allows us to handle all cases except UNEQ and
9816 case GE
: return ARM_GE
;
9817 case GT
: return ARM_GT
;
9818 case LE
: return ARM_LS
;
9819 case LT
: return ARM_MI
;
9820 case NE
: return ARM_NE
;
9821 case EQ
: return ARM_EQ
;
9822 case ORDERED
: return ARM_VC
;
9823 case UNORDERED
: return ARM_VS
;
9824 case UNLT
: return ARM_LT
;
9825 case UNLE
: return ARM_LE
;
9826 case UNGT
: return ARM_HI
;
9827 case UNGE
: return ARM_PL
;
9828 /* UNEQ and LTGT do not have a representation. */
9829 case UNEQ
: /* Fall through. */
9830 case LTGT
: /* Fall through. */
9837 case NE
: return ARM_NE
;
9838 case EQ
: return ARM_EQ
;
9839 case GE
: return ARM_LE
;
9840 case GT
: return ARM_LT
;
9841 case LE
: return ARM_GE
;
9842 case LT
: return ARM_GT
;
9843 case GEU
: return ARM_LS
;
9844 case GTU
: return ARM_CC
;
9845 case LEU
: return ARM_CS
;
9846 case LTU
: return ARM_HI
;
9853 case LTU
: return ARM_CS
;
9854 case GEU
: return ARM_CC
;
9861 case NE
: return ARM_NE
;
9862 case EQ
: return ARM_EQ
;
9863 case GE
: return ARM_GE
;
9864 case GT
: return ARM_GT
;
9865 case LE
: return ARM_LE
;
9866 case LT
: return ARM_LT
;
9867 case GEU
: return ARM_CS
;
9868 case GTU
: return ARM_HI
;
9869 case LEU
: return ARM_LS
;
9870 case LTU
: return ARM_CC
;
9882 arm_final_prescan_insn (insn
)
9885 /* BODY will hold the body of INSN. */
9886 rtx body
= PATTERN (insn
);
9888 /* This will be 1 if trying to repeat the trick, and things need to be
9889 reversed if it appears to fail. */
9892 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9893 taken are clobbered, even if the rtl suggests otherwise. It also
9894 means that we have to grub around within the jump expression to find
9895 out what the conditions are when the jump isn't taken. */
9896 int jump_clobbers
= 0;
9898 /* If we start with a return insn, we only succeed if we find another one. */
9899 int seeking_return
= 0;
9901 /* START_INSN will hold the insn from where we start looking. This is the
9902 first insn after the following code_label if REVERSE is true. */
9903 rtx start_insn
= insn
;
9905 /* If in state 4, check if the target branch is reached, in order to
9906 change back to state 0. */
9907 if (arm_ccfsm_state
== 4)
9909 if (insn
== arm_target_insn
)
9911 arm_target_insn
= NULL
;
9912 arm_ccfsm_state
= 0;
9917 /* If in state 3, it is possible to repeat the trick, if this insn is an
9918 unconditional branch to a label, and immediately following this branch
9919 is the previous target label which is only used once, and the label this
9920 branch jumps to is not too far off. */
9921 if (arm_ccfsm_state
== 3)
9923 if (simplejump_p (insn
))
9925 start_insn
= next_nonnote_insn (start_insn
);
9926 if (GET_CODE (start_insn
) == BARRIER
)
9928 /* XXX Isn't this always a barrier? */
9929 start_insn
= next_nonnote_insn (start_insn
);
9931 if (GET_CODE (start_insn
) == CODE_LABEL
9932 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
9933 && LABEL_NUSES (start_insn
) == 1)
9938 else if (GET_CODE (body
) == RETURN
)
9940 start_insn
= next_nonnote_insn (start_insn
);
9941 if (GET_CODE (start_insn
) == BARRIER
)
9942 start_insn
= next_nonnote_insn (start_insn
);
9943 if (GET_CODE (start_insn
) == CODE_LABEL
9944 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
9945 && LABEL_NUSES (start_insn
) == 1)
9957 if (arm_ccfsm_state
!= 0 && !reverse
)
9959 if (GET_CODE (insn
) != JUMP_INSN
)
9962 /* This jump might be paralleled with a clobber of the condition codes
9963 the jump should always come first */
9964 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
9965 body
= XVECEXP (body
, 0, 0);
9968 /* If this is a conditional return then we don't want to know */
9969 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
9970 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
9971 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
9972 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
9977 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
9978 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
9981 int fail
= FALSE
, succeed
= FALSE
;
9982 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
9983 int then_not_else
= TRUE
;
9984 rtx this_insn
= start_insn
, label
= 0;
9986 /* If the jump cannot be done with one instruction, we cannot
9987 conditionally execute the instruction in the inverse case. */
9988 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
9994 /* Register the insn jumped to. */
9997 if (!seeking_return
)
9998 label
= XEXP (SET_SRC (body
), 0);
10000 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
10001 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
10002 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
10004 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
10005 then_not_else
= FALSE
;
10007 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
10008 seeking_return
= 1;
10009 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
10011 seeking_return
= 1;
10012 then_not_else
= FALSE
;
10017 /* See how many insns this branch skips, and what kind of insns. If all
10018 insns are okay, and the label or unconditional branch to the same
10019 label is not too far away, succeed. */
10020 for (insns_skipped
= 0;
10021 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
10025 this_insn
= next_nonnote_insn (this_insn
);
10029 switch (GET_CODE (this_insn
))
10032 /* Succeed if it is the target label, otherwise fail since
10033 control falls in from somewhere else. */
10034 if (this_insn
== label
)
10038 arm_ccfsm_state
= 2;
10039 this_insn
= next_nonnote_insn (this_insn
);
10042 arm_ccfsm_state
= 1;
10050 /* Succeed if the following insn is the target label.
10052 If return insns are used then the last insn in a function
10053 will be a barrier. */
10054 this_insn
= next_nonnote_insn (this_insn
);
10055 if (this_insn
&& this_insn
== label
)
10059 arm_ccfsm_state
= 2;
10060 this_insn
= next_nonnote_insn (this_insn
);
10063 arm_ccfsm_state
= 1;
10071 /* If using 32-bit addresses the cc is not preserved over
10073 if (TARGET_APCS_32
)
10075 /* Succeed if the following insn is the target label,
10076 or if the following two insns are a barrier and
10077 the target label. */
10078 this_insn
= next_nonnote_insn (this_insn
);
10079 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
10080 this_insn
= next_nonnote_insn (this_insn
);
10082 if (this_insn
&& this_insn
== label
10083 && insns_skipped
< max_insns_skipped
)
10087 arm_ccfsm_state
= 2;
10088 this_insn
= next_nonnote_insn (this_insn
);
10091 arm_ccfsm_state
= 1;
10100 /* If this is an unconditional branch to the same label, succeed.
10101 If it is to another label, do nothing. If it is conditional,
10103 /* XXX Probably, the tests for SET and the PC are unnecessary. */
10105 scanbody
= PATTERN (this_insn
);
10106 if (GET_CODE (scanbody
) == SET
10107 && GET_CODE (SET_DEST (scanbody
)) == PC
)
10109 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
10110 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
10112 arm_ccfsm_state
= 2;
10115 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
10118 /* Fail if a conditional return is undesirable (eg on a
10119 StrongARM), but still allow this if optimizing for size. */
10120 else if (GET_CODE (scanbody
) == RETURN
10121 && !use_return_insn (TRUE
)
10124 else if (GET_CODE (scanbody
) == RETURN
10127 arm_ccfsm_state
= 2;
10130 else if (GET_CODE (scanbody
) == PARALLEL
)
10132 switch (get_attr_conds (this_insn
))
10142 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
10147 /* Instructions using or affecting the condition codes make it
10149 scanbody
= PATTERN (this_insn
);
10150 if (!(GET_CODE (scanbody
) == SET
10151 || GET_CODE (scanbody
) == PARALLEL
)
10152 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
10155 /* A conditional cirrus instruction must be followed by
10156 a non Cirrus instruction. However, since we
10157 conditionalize instructions in this function and by
10158 the time we get here we can't add instructions
10159 (nops), because shorten_branches() has already been
10160 called, we will disable conditionalizing Cirrus
10161 instructions to be safe. */
10162 if (GET_CODE (scanbody
) != USE
10163 && GET_CODE (scanbody
) != CLOBBER
10164 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
10174 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
10175 arm_target_label
= CODE_LABEL_NUMBER (label
);
10176 else if (seeking_return
|| arm_ccfsm_state
== 2)
10178 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
10180 this_insn
= next_nonnote_insn (this_insn
);
10181 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
10182 || GET_CODE (this_insn
) == CODE_LABEL
))
10187 /* Oh, dear! we ran off the end.. give up */
10188 recog (PATTERN (insn
), insn
, NULL
);
10189 arm_ccfsm_state
= 0;
10190 arm_target_insn
= NULL
;
10193 arm_target_insn
= this_insn
;
10202 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
10204 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
10205 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10206 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
10207 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10211 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10214 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
10218 if (reverse
|| then_not_else
)
10219 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10222 /* Restore recog_data (getting the attributes of other insns can
10223 destroy this array, but final.c assumes that it remains intact
10224 across this call; since the insn has been recognized already we
10225 call recog direct). */
10226 recog (PATTERN (insn
), insn
, NULL
);
10230 /* Returns true if REGNO is a valid register
10231 for holding a quantity of tyoe MODE. */
10234 arm_hard_regno_mode_ok (regno
, mode
)
10235 unsigned int regno
;
10236 enum machine_mode mode
;
10238 if (GET_MODE_CLASS (mode
) == MODE_CC
)
10239 return regno
== CC_REGNUM
;
10242 /* For the Thumb we only allow values bigger than SImode in
10243 registers 0 - 6, so that there is always a second low
10244 register available to hold the upper part of the value.
10245 We probably we ought to ensure that the register is the
10246 start of an even numbered register pair. */
10247 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
10249 if (IS_CIRRUS_REGNUM (regno
))
10250 /* We have outlawed SI values in Cirrus registers because they
10251 reside in the lower 32 bits, but SF values reside in the
10252 upper 32 bits. This causes gcc all sorts of grief. We can't
10253 even split the registers into pairs because Cirrus SI values
10254 get sign extended to 64bits-- aldyh. */
10255 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
10257 if (regno
<= LAST_ARM_REGNUM
)
10258 /* We allow any value to be stored in the general regisetrs. */
10261 if ( regno
== FRAME_POINTER_REGNUM
10262 || regno
== ARG_POINTER_REGNUM
)
10263 /* We only allow integers in the fake hard registers. */
10264 return GET_MODE_CLASS (mode
) == MODE_INT
;
10266 /* The only registers left are the FPA registers
10267 which we only allow to hold FP values. */
10268 return GET_MODE_CLASS (mode
) == MODE_FLOAT
10269 && regno
>= FIRST_ARM_FP_REGNUM
10270 && regno
<= LAST_ARM_FP_REGNUM
;
10274 arm_regno_class (regno
)
10279 if (regno
== STACK_POINTER_REGNUM
)
10281 if (regno
== CC_REGNUM
)
10288 if ( regno
<= LAST_ARM_REGNUM
10289 || regno
== FRAME_POINTER_REGNUM
10290 || regno
== ARG_POINTER_REGNUM
)
10291 return GENERAL_REGS
;
10293 if (regno
== CC_REGNUM
)
10296 if (IS_CIRRUS_REGNUM (regno
))
10297 return CIRRUS_REGS
;
10302 /* Handle a special case when computing the offset
10303 of an argument from the frame pointer. */
10306 arm_debugger_arg_offset (value
, addr
)
10312 /* We are only interested if dbxout_parms() failed to compute the offset. */
10316 /* We can only cope with the case where the address is held in a register. */
10317 if (GET_CODE (addr
) != REG
)
10320 /* If we are using the frame pointer to point at the argument, then
10321 an offset of 0 is correct. */
10322 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
10325 /* If we are using the stack pointer to point at the
10326 argument, then an offset of 0 is correct. */
10327 if ((TARGET_THUMB
|| !frame_pointer_needed
)
10328 && REGNO (addr
) == SP_REGNUM
)
10331 /* Oh dear. The argument is pointed to by a register rather
10332 than being held in a register, or being stored at a known
10333 offset from the frame pointer. Since GDB only understands
10334 those two kinds of argument we must translate the address
10335 held in the register into an offset from the frame pointer.
10336 We do this by searching through the insns for the function
10337 looking to see where this register gets its value. If the
10338 register is initialized from the frame pointer plus an offset
10339 then we are in luck and we can continue, otherwise we give up.
10341 This code is exercised by producing debugging information
10342 for a function with arguments like this:
10344 double func (double a, double b, int c, double d) {return d;}
10346 Without this code the stab for parameter 'd' will be set to
10347 an offset of 0 from the frame pointer, rather than 8. */
10349 /* The if() statement says:
10351 If the insn is a normal instruction
10352 and if the insn is setting the value in a register
10353 and if the register being set is the register holding the address of the argument
10354 and if the address is computing by an addition
10355 that involves adding to a register
10356 which is the frame pointer
10361 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10363 if ( GET_CODE (insn
) == INSN
10364 && GET_CODE (PATTERN (insn
)) == SET
10365 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
10366 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
10367 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
10368 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10369 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
10372 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
10381 warning ("unable to compute real location of stacked parameter");
10382 value
= 8; /* XXX magic hack */
10388 /* Recursively search through all of the blocks in a function
10389 checking to see if any of the variables created in that
10390 function match the RTX called 'orig'. If they do then
10391 replace them with the RTX called 'new'. */
10394 replace_symbols_in_block (block
, orig
, new)
10399 for (; block
; block
= BLOCK_CHAIN (block
))
10403 if (!TREE_USED (block
))
10406 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
10408 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
10409 || DECL_IGNORED_P (sym
)
10410 || TREE_CODE (sym
) != VAR_DECL
10411 || DECL_EXTERNAL (sym
)
10412 || !rtx_equal_p (DECL_RTL (sym
), orig
)
10416 SET_DECL_RTL (sym
, new);
10419 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
10423 /* Return the number (counting from 0) of
10424 the least significant set bit in MASK. */
10430 number_of_first_bit_set (mask
)
10436 (mask
& (1 << bit
)) == 0;
10443 /* Generate code to return from a thumb function.
10444 If 'reg_containing_return_addr' is -1, then the return address is
10445 actually on the stack, at the stack pointer. */
10447 thumb_exit (f
, reg_containing_return_addr
, eh_ofs
)
10449 int reg_containing_return_addr
;
10452 unsigned regs_available_for_popping
;
10453 unsigned regs_to_pop
;
10455 unsigned available
;
10459 int restore_a4
= FALSE
;
10461 /* Compute the registers we need to pop. */
10465 /* There is an assumption here, that if eh_ofs is not NULL, the
10466 normal return address will have been pushed. */
10467 if (reg_containing_return_addr
== -1 || eh_ofs
)
10469 /* When we are generating a return for __builtin_eh_return,
10470 reg_containing_return_addr must specify the return regno. */
10471 if (eh_ofs
&& reg_containing_return_addr
== -1)
10474 regs_to_pop
|= 1 << LR_REGNUM
;
10478 if (TARGET_BACKTRACE
)
10480 /* Restore the (ARM) frame pointer and stack pointer. */
10481 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
10485 /* If there is nothing to pop then just emit the BX instruction and
10487 if (pops_needed
== 0)
10490 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
10492 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
10495 /* Otherwise if we are not supporting interworking and we have not created
10496 a backtrace structure and the function was not entered in ARM mode then
10497 just pop the return address straight into the PC. */
10498 else if (!TARGET_INTERWORK
10499 && !TARGET_BACKTRACE
10500 && !is_called_in_ARM_mode (current_function_decl
))
10504 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
10505 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
10506 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
10509 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
10514 /* Find out how many of the (return) argument registers we can corrupt. */
10515 regs_available_for_popping
= 0;
10517 /* If returning via __builtin_eh_return, the bottom three registers
10518 all contain information needed for the return. */
10524 /* If we can deduce the registers used from the function's
10525 return value. This is more reliable that examining
10526 regs_ever_live[] because that will be set if the register is
10527 ever used in the function, not just if the register is used
10528 to hold a return value. */
10530 if (current_function_return_rtx
!= 0)
10531 mode
= GET_MODE (current_function_return_rtx
);
10534 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10536 size
= GET_MODE_SIZE (mode
);
10540 /* In a void function we can use any argument register.
10541 In a function that returns a structure on the stack
10542 we can use the second and third argument registers. */
10543 if (mode
== VOIDmode
)
10544 regs_available_for_popping
=
10545 (1 << ARG_REGISTER (1))
10546 | (1 << ARG_REGISTER (2))
10547 | (1 << ARG_REGISTER (3));
10549 regs_available_for_popping
=
10550 (1 << ARG_REGISTER (2))
10551 | (1 << ARG_REGISTER (3));
10553 else if (size
<= 4)
10554 regs_available_for_popping
=
10555 (1 << ARG_REGISTER (2))
10556 | (1 << ARG_REGISTER (3));
10557 else if (size
<= 8)
10558 regs_available_for_popping
=
10559 (1 << ARG_REGISTER (3));
10562 /* Match registers to be popped with registers into which we pop them. */
10563 for (available
= regs_available_for_popping
,
10564 required
= regs_to_pop
;
10565 required
!= 0 && available
!= 0;
10566 available
&= ~(available
& - available
),
10567 required
&= ~(required
& - required
))
10570 /* If we have any popping registers left over, remove them. */
10572 regs_available_for_popping
&= ~available
;
10574 /* Otherwise if we need another popping register we can use
10575 the fourth argument register. */
10576 else if (pops_needed
)
10578 /* If we have not found any free argument registers and
10579 reg a4 contains the return address, we must move it. */
10580 if (regs_available_for_popping
== 0
10581 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
10583 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
10584 reg_containing_return_addr
= LR_REGNUM
;
10586 else if (size
> 12)
10588 /* Register a4 is being used to hold part of the return value,
10589 but we have dire need of a free, low register. */
10592 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
10595 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
10597 /* The fourth argument register is available. */
10598 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
10604 /* Pop as many registers as we can. */
10605 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
10607 /* Process the registers we popped. */
10608 if (reg_containing_return_addr
== -1)
10610 /* The return address was popped into the lowest numbered register. */
10611 regs_to_pop
&= ~(1 << LR_REGNUM
);
10613 reg_containing_return_addr
=
10614 number_of_first_bit_set (regs_available_for_popping
);
10616 /* Remove this register for the mask of available registers, so that
10617 the return address will not be corrupted by further pops. */
10618 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
10621 /* If we popped other registers then handle them here. */
10622 if (regs_available_for_popping
)
10626 /* Work out which register currently contains the frame pointer. */
10627 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
10629 /* Move it into the correct place. */
10630 asm_fprintf (f
, "\tmov\t%r, %r\n",
10631 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
10633 /* (Temporarily) remove it from the mask of popped registers. */
10634 regs_available_for_popping
&= ~(1 << frame_pointer
);
10635 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
10637 if (regs_available_for_popping
)
10641 /* We popped the stack pointer as well,
10642 find the register that contains it. */
10643 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
10645 /* Move it into the stack register. */
10646 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
10648 /* At this point we have popped all necessary registers, so
10649 do not worry about restoring regs_available_for_popping
10650 to its correct value:
10652 assert (pops_needed == 0)
10653 assert (regs_available_for_popping == (1 << frame_pointer))
10654 assert (regs_to_pop == (1 << STACK_POINTER)) */
10658 /* Since we have just move the popped value into the frame
10659 pointer, the popping register is available for reuse, and
10660 we know that we still have the stack pointer left to pop. */
10661 regs_available_for_popping
|= (1 << frame_pointer
);
10665 /* If we still have registers left on the stack, but we no longer have
10666 any registers into which we can pop them, then we must move the return
10667 address into the link register and make available the register that
10669 if (regs_available_for_popping
== 0 && pops_needed
> 0)
10671 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
10673 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
10674 reg_containing_return_addr
);
10676 reg_containing_return_addr
= LR_REGNUM
;
10679 /* If we have registers left on the stack then pop some more.
10680 We know that at most we will want to pop FP and SP. */
10681 if (pops_needed
> 0)
10686 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
10688 /* We have popped either FP or SP.
10689 Move whichever one it is into the correct register. */
10690 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
10691 move_to
= number_of_first_bit_set (regs_to_pop
);
10693 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
10695 regs_to_pop
&= ~(1 << move_to
);
10700 /* If we still have not popped everything then we must have only
10701 had one register available to us and we are now popping the SP. */
10702 if (pops_needed
> 0)
10706 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
10708 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
10710 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
10712 assert (regs_to_pop == (1 << STACK_POINTER))
10713 assert (pops_needed == 1)
10717 /* If necessary restore the a4 register. */
10720 if (reg_containing_return_addr
!= LR_REGNUM
)
10722 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
10723 reg_containing_return_addr
= LR_REGNUM
;
10726 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
10730 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
10732 /* Return to caller. */
10733 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
10736 /* Emit code to push or pop registers to or from the stack. */
10739 thumb_pushpop (f
, mask
, push
)
10745 int lo_mask
= mask
& 0xFF;
10747 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
10749 /* Special case. Do not generate a POP PC statement here, do it in
10751 thumb_exit (f
, -1, NULL_RTX
);
10755 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
10757 /* Look at the low registers first. */
10758 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
10762 asm_fprintf (f
, "%r", regno
);
10764 if ((lo_mask
& ~1) != 0)
10769 if (push
&& (mask
& (1 << LR_REGNUM
)))
10771 /* Catch pushing the LR. */
10775 asm_fprintf (f
, "%r", LR_REGNUM
);
10777 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
10779 /* Catch popping the PC. */
10780 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
10782 /* The PC is never poped directly, instead
10783 it is popped into r3 and then BX is used. */
10784 fprintf (f
, "}\n");
10786 thumb_exit (f
, -1, NULL_RTX
);
10795 asm_fprintf (f
, "%r", PC_REGNUM
);
10799 fprintf (f
, "}\n");
10803 thumb_final_prescan_insn (insn
)
10806 if (flag_print_asm_name
)
10807 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
10808 INSN_ADDRESSES (INSN_UID (insn
)));
10812 thumb_shiftable_const (val
)
10813 unsigned HOST_WIDE_INT val
;
10815 unsigned HOST_WIDE_INT mask
= 0xff;
10818 if (val
== 0) /* XXX */
10821 for (i
= 0; i
< 25; i
++)
10822 if ((val
& (mask
<< i
)) == val
)
10828 /* Returns nonzero if the current function contains,
10829 or might contain a far jump. */
10832 thumb_far_jump_used_p (in_prologue
)
10837 /* This test is only important for leaf functions. */
10838 /* assert (!leaf_function_p ()); */
10840 /* If we have already decided that far jumps may be used,
10841 do not bother checking again, and always return true even if
10842 it turns out that they are not being used. Once we have made
10843 the decision that far jumps are present (and that hence the link
10844 register will be pushed onto the stack) we cannot go back on it. */
10845 if (cfun
->machine
->far_jump_used
)
10848 /* If this function is not being called from the prologue/epilogue
10849 generation code then it must be being called from the
10850 INITIAL_ELIMINATION_OFFSET macro. */
10853 /* In this case we know that we are being asked about the elimination
10854 of the arg pointer register. If that register is not being used,
10855 then there are no arguments on the stack, and we do not have to
10856 worry that a far jump might force the prologue to push the link
10857 register, changing the stack offsets. In this case we can just
10858 return false, since the presence of far jumps in the function will
10859 not affect stack offsets.
10861 If the arg pointer is live (or if it was live, but has now been
10862 eliminated and so set to dead) then we do have to test to see if
10863 the function might contain a far jump. This test can lead to some
10864 false negatives, since before reload is completed, then length of
10865 branch instructions is not known, so gcc defaults to returning their
10866 longest length, which in turn sets the far jump attribute to true.
10868 A false negative will not result in bad code being generated, but it
10869 will result in a needless push and pop of the link register. We
10870 hope that this does not occur too often. */
10871 if (regs_ever_live
[ARG_POINTER_REGNUM
])
10872 cfun
->machine
->arg_pointer_live
= 1;
10873 else if (!cfun
->machine
->arg_pointer_live
)
10877 /* Check to see if the function contains a branch
10878 insn with the far jump attribute set. */
10879 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10881 if (GET_CODE (insn
) == JUMP_INSN
10882 /* Ignore tablejump patterns. */
10883 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
10884 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
10885 && get_attr_far_jump (insn
) == FAR_JUMP_YES
10888 /* Record the fact that we have decied that
10889 the function does use far jumps. */
10890 cfun
->machine
->far_jump_used
= 1;
10898 /* Return nonzero if FUNC must be entered in ARM mode. */
10901 is_called_in_ARM_mode (func
)
10904 if (TREE_CODE (func
) != FUNCTION_DECL
)
10907 /* Ignore the problem about functions whoes address is taken. */
10908 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
10912 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
10918 /* The bits which aren't usefully expanded as rtl. */
10921 thumb_unexpanded_epilogue ()
10924 int live_regs_mask
= 0;
10925 int high_regs_pushed
= 0;
10926 int leaf_function
= leaf_function_p ();
10927 int had_to_push_lr
;
10928 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
10930 if (return_used_this_function
)
10933 if (IS_NAKED (arm_current_func_type ()))
10936 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10937 if (THUMB_REG_PUSHED_P (regno
))
10938 live_regs_mask
|= 1 << regno
;
10940 for (regno
= 8; regno
< 13; regno
++)
10941 if (THUMB_REG_PUSHED_P (regno
))
10942 high_regs_pushed
++;
10944 /* The prolog may have pushed some high registers to use as
10945 work registers. eg the testuite file:
10946 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
10947 compiles to produce:
10948 push {r4, r5, r6, r7, lr}
10952 as part of the prolog. We have to undo that pushing here. */
10954 if (high_regs_pushed
)
10956 int mask
= live_regs_mask
;
10962 /* If we can deduce the registers used from the function's return value.
10963 This is more reliable that examining regs_ever_live[] because that
10964 will be set if the register is ever used in the function, not just if
10965 the register is used to hold a return value. */
10967 if (current_function_return_rtx
!= 0)
10968 mode
= GET_MODE (current_function_return_rtx
);
10971 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10973 size
= GET_MODE_SIZE (mode
);
10975 /* Unless we are returning a type of size > 12 register r3 is
10981 /* Oh dear! We have no low registers into which we can pop
10984 ("no low registers available for popping high registers");
10986 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
10987 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10990 while (high_regs_pushed
)
10992 /* Find lo register(s) into which the high register(s) can
10994 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10996 if (mask
& (1 << regno
))
10997 high_regs_pushed
--;
10998 if (high_regs_pushed
== 0)
11002 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
11004 /* Pop the values into the low register(s). */
11005 thumb_pushpop (asm_out_file
, mask
, 0);
11007 /* Move the value(s) into the high registers. */
11008 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11010 if (mask
& (1 << regno
))
11012 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
11015 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
11016 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11023 had_to_push_lr
= (live_regs_mask
|| !leaf_function
11024 || thumb_far_jump_used_p (1));
11026 if (TARGET_BACKTRACE
11027 && ((live_regs_mask
& 0xFF) == 0)
11028 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11030 /* The stack backtrace structure creation code had to
11031 push R7 in order to get a work register, so we pop
11033 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
11036 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
11039 && !is_called_in_ARM_mode (current_function_decl
)
11041 live_regs_mask
|= 1 << PC_REGNUM
;
11043 /* Either no argument registers were pushed or a backtrace
11044 structure was created which includes an adjusted stack
11045 pointer, so just pop everything. */
11046 if (live_regs_mask
)
11047 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11050 thumb_exit (asm_out_file
, 2, eh_ofs
);
11051 /* We have either just popped the return address into the
11052 PC or it is was kept in LR for the entire function or
11053 it is still on the stack because we do not want to
11054 return by doing a pop {pc}. */
11055 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
11056 thumb_exit (asm_out_file
,
11058 && is_called_in_ARM_mode (current_function_decl
)) ?
11059 -1 : LR_REGNUM
, NULL_RTX
);
11063 /* Pop everything but the return address. */
11064 live_regs_mask
&= ~(1 << PC_REGNUM
);
11066 if (live_regs_mask
)
11067 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11069 if (had_to_push_lr
)
11070 /* Get the return address into a temporary register. */
11071 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
11073 /* Remove the argument registers that were pushed onto the stack. */
11074 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
11075 SP_REGNUM
, SP_REGNUM
,
11076 current_function_pretend_args_size
);
11079 thumb_exit (asm_out_file
, 2, eh_ofs
);
11081 thumb_exit (asm_out_file
,
11082 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
11088 /* Functions to save and restore machine-specific function data. */
11090 static struct machine_function
*
11091 arm_init_machine_status ()
11093 struct machine_function
*machine
;
11094 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
11096 #if ARM_FT_UNKNOWN != 0
11097 machine
->func_type
= ARM_FT_UNKNOWN
;
11102 /* Return an RTX indicating where the return address to the
11103 calling function can be found. */
11106 arm_return_addr (count
, frame
)
11108 rtx frame ATTRIBUTE_UNUSED
;
11113 if (TARGET_APCS_32
)
11114 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
11117 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
11118 GEN_INT (RETURN_ADDR_MASK26
));
11119 return get_func_hard_reg_initial_val (cfun
, lr
);
11123 /* Do anything needed before RTL is emitted for each function. */
11126 arm_init_expanders ()
11128 /* Arrange to initialize and mark the machine per-function status. */
11129 init_machine_status
= arm_init_machine_status
;
11133 thumb_get_frame_size ()
11137 int base_size
= ROUND_UP_WORD (get_frame_size ());
11138 int count_regs
= 0;
11139 int entry_size
= 0;
11142 if (! TARGET_THUMB
)
11145 if (! TARGET_ATPCS
)
11148 /* We need to know if we are a leaf function. Unfortunately, it
11149 is possible to be called after start_sequence has been called,
11150 which causes get_insns to return the insns for the sequence,
11151 not the function, which will cause leaf_function_p to return
11152 the incorrect result.
11154 To work around this, we cache the computed frame size. This
11155 works because we will only be calling RTL expanders that need
11156 to know about leaf functions once reload has completed, and the
11157 frame size cannot be changed after that time, so we can safely
11158 use the cached value. */
11160 if (reload_completed
)
11161 return cfun
->machine
->frame_size
;
11163 leaf
= leaf_function_p ();
11165 /* A leaf function does not need any stack alignment if it has nothing
11167 if (leaf
&& base_size
== 0)
11169 cfun
->machine
->frame_size
= 0;
11173 /* We know that SP will be word aligned on entry, and we must
11174 preserve that condition at any subroutine call. But those are
11175 the only constraints. */
11177 /* Space for variadic functions. */
11178 if (current_function_pretend_args_size
)
11179 entry_size
+= current_function_pretend_args_size
;
11181 /* Space for pushed lo registers. */
11182 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11183 if (THUMB_REG_PUSHED_P (regno
))
11186 /* Space for backtrace structure. */
11187 if (TARGET_BACKTRACE
)
11189 if (count_regs
== 0 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11195 if (count_regs
|| !leaf
|| thumb_far_jump_used_p (1))
11196 count_regs
++; /* LR */
11198 entry_size
+= count_regs
* 4;
11201 /* Space for pushed hi regs. */
11202 for (regno
= 8; regno
< 13; regno
++)
11203 if (THUMB_REG_PUSHED_P (regno
))
11206 entry_size
+= count_regs
* 4;
11208 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
11210 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
11213 cfun
->machine
->frame_size
= base_size
;
11218 /* Generate the rest of a function's prologue. */
11221 thumb_expand_prologue ()
11223 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
11224 + current_function_outgoing_args_size
);
11225 unsigned long func_type
;
11227 func_type
= arm_current_func_type ();
11229 /* Naked functions don't have prologues. */
11230 if (IS_NAKED (func_type
))
11233 if (IS_INTERRUPT (func_type
))
11235 error ("interrupt Service Routines cannot be coded in Thumb mode");
11239 if (frame_pointer_needed
)
11240 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
11244 amount
= ROUND_UP_WORD (amount
);
11247 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11248 GEN_INT (- amount
)));
11254 /* The stack decrement is too big for an immediate value in a single
11255 insn. In theory we could issue multiple subtracts, but after
11256 three of them it becomes more space efficient to place the full
11257 value in the constant pool and load into a register. (Also the
11258 ARM debugger really likes to see only one stack decrement per
11259 function). So instead we look for a scratch register into which
11260 we can load the decrement, and then we subtract this from the
11261 stack pointer. Unfortunately on the thumb the only available
11262 scratch registers are the argument registers, and we cannot use
11263 these as they may hold arguments to the function. Instead we
11264 attempt to locate a call preserved register which is used by this
11265 function. If we can find one, then we know that it will have
11266 been pushed at the start of the prologue and so we can corrupt
11268 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
11269 if (THUMB_REG_PUSHED_P (regno
)
11270 && !(frame_pointer_needed
11271 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
11274 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
11276 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
11278 /* Choose an arbitrary, non-argument low register. */
11279 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
11281 /* Save it by copying it into a high, scratch register. */
11282 emit_insn (gen_movsi (spare
, reg
));
11283 /* Add a USE to stop propagate_one_insn() from barfing. */
11284 emit_insn (gen_prologue_use (spare
));
11286 /* Decrement the stack. */
11287 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
11288 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11291 /* Restore the low register's original value. */
11292 emit_insn (gen_movsi (reg
, spare
));
11294 /* Emit a USE of the restored scratch register, so that flow
11295 analysis will not consider the restore redundant. The
11296 register won't be used again in this function and isn't
11297 restored by the epilogue. */
11298 emit_insn (gen_prologue_use (reg
));
11302 reg
= gen_rtx (REG
, SImode
, regno
);
11304 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
11305 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11311 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
11312 emit_insn (gen_blockage ());
11316 thumb_expand_epilogue ()
11318 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
11319 + current_function_outgoing_args_size
);
11321 /* Naked functions don't have prologues. */
11322 if (IS_NAKED (arm_current_func_type ()))
11325 if (frame_pointer_needed
)
11326 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
11329 amount
= ROUND_UP_WORD (amount
);
11332 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11333 GEN_INT (amount
)));
11336 /* r3 is always free in the epilogue. */
11337 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
11339 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
11340 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
11344 /* Emit a USE (stack_pointer_rtx), so that
11345 the stack adjustment will not be deleted. */
11346 emit_insn (gen_prologue_use (stack_pointer_rtx
));
11348 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
11349 emit_insn (gen_blockage ());
11353 thumb_output_function_prologue (f
, size
)
11355 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
11357 int live_regs_mask
= 0;
11358 int high_regs_pushed
= 0;
11361 if (IS_NAKED (arm_current_func_type ()))
11364 if (is_called_in_ARM_mode (current_function_decl
))
11368 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
11370 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
11372 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11374 /* Generate code sequence to switch us into Thumb mode. */
11375 /* The .code 32 directive has already been emitted by
11376 ASM_DECLARE_FUNCTION_NAME. */
11377 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
11378 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
11380 /* Generate a label, so that the debugger will notice the
11381 change in instruction sets. This label is also used by
11382 the assembler to bypass the ARM code when this function
11383 is called from a Thumb encoded function elsewhere in the
11384 same file. Hence the definition of STUB_NAME here must
11385 agree with the definition in gas/config/tc-arm.c */
11387 #define STUB_NAME ".real_start_of"
11389 fprintf (f
, "\t.code\t16\n");
11391 if (arm_dllexport_name_p (name
))
11392 name
= arm_strip_name_encoding (name
);
11394 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
11395 fprintf (f
, "\t.thumb_func\n");
11396 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
11399 if (current_function_pretend_args_size
)
11401 if (cfun
->machine
->uses_anonymous_args
)
11405 fprintf (f
, "\tpush\t{");
11407 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
11409 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
11410 regno
<= LAST_ARG_REGNUM
;
11412 asm_fprintf (f
, "%r%s", regno
,
11413 regno
== LAST_ARG_REGNUM
? "" : ", ");
11415 fprintf (f
, "}\n");
11418 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
11419 SP_REGNUM
, SP_REGNUM
,
11420 current_function_pretend_args_size
);
11423 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11424 if (THUMB_REG_PUSHED_P (regno
))
11425 live_regs_mask
|= 1 << regno
;
11427 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
11428 live_regs_mask
|= 1 << LR_REGNUM
;
11430 if (TARGET_BACKTRACE
)
11433 int work_register
= 0;
11436 /* We have been asked to create a stack backtrace structure.
11437 The code looks like this:
11441 0 sub SP, #16 Reserve space for 4 registers.
11442 2 push {R7} Get a work register.
11443 4 add R7, SP, #20 Get the stack pointer before the push.
11444 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
11445 8 mov R7, PC Get hold of the start of this code plus 12.
11446 10 str R7, [SP, #16] Store it.
11447 12 mov R7, FP Get hold of the current frame pointer.
11448 14 str R7, [SP, #4] Store it.
11449 16 mov R7, LR Get hold of the current return address.
11450 18 str R7, [SP, #12] Store it.
11451 20 add R7, SP, #16 Point at the start of the backtrace structure.
11452 22 mov FP, R7 Put this value into the frame pointer. */
11454 if ((live_regs_mask
& 0xFF) == 0)
11456 /* See if the a4 register is free. */
11458 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
11459 work_register
= LAST_ARG_REGNUM
;
11460 else /* We must push a register of our own */
11461 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
11464 if (work_register
== 0)
11466 /* Select a register from the list that will be pushed to
11467 use as our work register. */
11468 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
11469 if ((1 << work_register
) & live_regs_mask
)
11474 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
11475 SP_REGNUM
, SP_REGNUM
);
11477 if (live_regs_mask
)
11478 thumb_pushpop (f
, live_regs_mask
, 1);
11480 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
11481 if (wr
& live_regs_mask
)
11484 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
11485 offset
+ 16 + current_function_pretend_args_size
);
11487 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
11490 /* Make sure that the instruction fetching the PC is in the right place
11491 to calculate "start of backtrace creation code + 12". */
11492 if (live_regs_mask
)
11494 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
11495 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
11497 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
11498 ARM_HARD_FRAME_POINTER_REGNUM
);
11499 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
11504 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
11505 ARM_HARD_FRAME_POINTER_REGNUM
);
11506 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
11508 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
11509 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
11513 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
11514 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
11516 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
11518 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
11519 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
11521 else if (live_regs_mask
)
11522 thumb_pushpop (f
, live_regs_mask
, 1);
11524 for (regno
= 8; regno
< 13; regno
++)
11525 if (THUMB_REG_PUSHED_P (regno
))
11526 high_regs_pushed
++;
11528 if (high_regs_pushed
)
11530 int pushable_regs
= 0;
11531 int mask
= live_regs_mask
& 0xff;
11534 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
11535 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11538 pushable_regs
= mask
;
11540 if (pushable_regs
== 0)
11542 /* Desperation time -- this probably will never happen. */
11543 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
11544 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
11545 mask
= 1 << LAST_ARG_REGNUM
;
11548 while (high_regs_pushed
> 0)
11550 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
11552 if (mask
& (1 << regno
))
11554 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
11556 high_regs_pushed
--;
11558 if (high_regs_pushed
)
11560 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
11562 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11567 mask
&= ~((1 << regno
) - 1);
11573 thumb_pushpop (f
, mask
, 1);
11576 if (pushable_regs
== 0
11577 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
11578 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
11582 /* Handle the case of a double word load into a low register from
11583 a computed memory address. The computed address may involve a
11584 register which is overwritten by the load. */
11587 thumb_load_double_from_address (operands
)
11596 if (GET_CODE (operands
[0]) != REG
)
11599 if (GET_CODE (operands
[1]) != MEM
)
11602 /* Get the memory address. */
11603 addr
= XEXP (operands
[1], 0);
11605 /* Work out how the memory address is computed. */
11606 switch (GET_CODE (addr
))
11609 operands
[2] = gen_rtx (MEM
, SImode
,
11610 plus_constant (XEXP (operands
[1], 0), 4));
11612 if (REGNO (operands
[0]) == REGNO (addr
))
11614 output_asm_insn ("ldr\t%H0, %2", operands
);
11615 output_asm_insn ("ldr\t%0, %1", operands
);
11619 output_asm_insn ("ldr\t%0, %1", operands
);
11620 output_asm_insn ("ldr\t%H0, %2", operands
);
11625 /* Compute <address> + 4 for the high order load. */
11626 operands
[2] = gen_rtx (MEM
, SImode
,
11627 plus_constant (XEXP (operands
[1], 0), 4));
11629 output_asm_insn ("ldr\t%0, %1", operands
);
11630 output_asm_insn ("ldr\t%H0, %2", operands
);
11634 arg1
= XEXP (addr
, 0);
11635 arg2
= XEXP (addr
, 1);
11637 if (CONSTANT_P (arg1
))
11638 base
= arg2
, offset
= arg1
;
11640 base
= arg1
, offset
= arg2
;
11642 if (GET_CODE (base
) != REG
)
11645 /* Catch the case of <address> = <reg> + <reg> */
11646 if (GET_CODE (offset
) == REG
)
11648 int reg_offset
= REGNO (offset
);
11649 int reg_base
= REGNO (base
);
11650 int reg_dest
= REGNO (operands
[0]);
11652 /* Add the base and offset registers together into the
11653 higher destination register. */
11654 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
11655 reg_dest
+ 1, reg_base
, reg_offset
);
11657 /* Load the lower destination register from the address in
11658 the higher destination register. */
11659 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
11660 reg_dest
, reg_dest
+ 1);
11662 /* Load the higher destination register from its own address
11664 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
11665 reg_dest
+ 1, reg_dest
+ 1);
11669 /* Compute <address> + 4 for the high order load. */
11670 operands
[2] = gen_rtx (MEM
, SImode
,
11671 plus_constant (XEXP (operands
[1], 0), 4));
11673 /* If the computed address is held in the low order register
11674 then load the high order register first, otherwise always
11675 load the low order register first. */
11676 if (REGNO (operands
[0]) == REGNO (base
))
11678 output_asm_insn ("ldr\t%H0, %2", operands
);
11679 output_asm_insn ("ldr\t%0, %1", operands
);
11683 output_asm_insn ("ldr\t%0, %1", operands
);
11684 output_asm_insn ("ldr\t%H0, %2", operands
);
11690 /* With no registers to worry about we can just load the value
11692 operands
[2] = gen_rtx (MEM
, SImode
,
11693 plus_constant (XEXP (operands
[1], 0), 4));
11695 output_asm_insn ("ldr\t%H0, %2", operands
);
11696 output_asm_insn ("ldr\t%0, %1", operands
);
11709 thumb_output_move_mem_multiple (n
, operands
)
11718 if (REGNO (operands
[4]) > REGNO (operands
[5]))
11721 operands
[4] = operands
[5];
11724 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
11725 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
11729 if (REGNO (operands
[4]) > REGNO (operands
[5]))
11732 operands
[4] = operands
[5];
11735 if (REGNO (operands
[5]) > REGNO (operands
[6]))
11738 operands
[5] = operands
[6];
11741 if (REGNO (operands
[4]) > REGNO (operands
[5]))
11744 operands
[4] = operands
[5];
11748 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
11749 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
11759 /* Routines for generating rtl. */
11762 thumb_expand_movstrqi (operands
)
11765 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
11766 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
11767 HOST_WIDE_INT len
= INTVAL (operands
[2]);
11768 HOST_WIDE_INT offset
= 0;
11772 emit_insn (gen_movmem12b (out
, in
, out
, in
));
11778 emit_insn (gen_movmem8b (out
, in
, out
, in
));
11784 rtx reg
= gen_reg_rtx (SImode
);
11785 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
11786 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
11793 rtx reg
= gen_reg_rtx (HImode
);
11794 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
11795 plus_constant (in
, offset
))));
11796 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
11804 rtx reg
= gen_reg_rtx (QImode
);
11805 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
11806 plus_constant (in
, offset
))));
11807 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
11813 thumb_cmp_operand (op
, mode
)
11815 enum machine_mode mode
;
11817 return ((GET_CODE (op
) == CONST_INT
11818 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
11819 || register_operand (op
, mode
));
11822 static const char *
11823 thumb_condition_code (x
, invert
)
11827 static const char * const conds
[] =
11829 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
11830 "hi", "ls", "ge", "lt", "gt", "le"
11834 switch (GET_CODE (x
))
11836 case EQ
: val
= 0; break;
11837 case NE
: val
= 1; break;
11838 case GEU
: val
= 2; break;
11839 case LTU
: val
= 3; break;
11840 case GTU
: val
= 8; break;
11841 case LEU
: val
= 9; break;
11842 case GE
: val
= 10; break;
11843 case LT
: val
= 11; break;
11844 case GT
: val
= 12; break;
11845 case LE
: val
= 13; break;
11850 return conds
[val
^ invert
];
11853 /* Handle storing a half-word to memory during reload. */
11856 thumb_reload_out_hi (operands
)
11859 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
11862 /* Handle storing a half-word to memory during reload. */
11865 thumb_reload_in_hi (operands
)
11866 rtx
* operands ATTRIBUTE_UNUSED
;
11871 /* Return the length of a function name prefix
11872 that starts with the character 'c'. */
11875 arm_get_strip_length (c
)
11880 ARM_NAME_ENCODING_LENGTHS
11885 /* Return a pointer to a function's name with any
11886 and all prefix encodings stripped from it. */
11889 arm_strip_name_encoding (name
)
11894 while ((skip
= arm_get_strip_length (* name
)))
11900 /* If there is a '*' anywhere in the name's prefix, then
11901 emit the stripped name verbatim, otherwise prepend an
11902 underscore if leading underscores are being used. */
11905 arm_asm_output_labelref (stream
, name
)
11912 while ((skip
= arm_get_strip_length (* name
)))
11914 verbatim
|= (*name
== '*');
11919 fputs (name
, stream
);
11921 asm_fprintf (stream
, "%U%s", name
);
11926 #ifdef AOF_ASSEMBLER
11927 /* Special functions only needed when producing AOF syntax assembler. */
11931 struct pic_chain
* next
;
11932 const char * symname
;
11935 static struct pic_chain
* aof_pic_chain
= NULL
;
11941 struct pic_chain
** chainp
;
11944 if (aof_pic_label
== NULL_RTX
)
11946 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
11949 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
11950 offset
+= 4, chainp
= &(*chainp
)->next
)
11951 if ((*chainp
)->symname
== XSTR (x
, 0))
11952 return plus_constant (aof_pic_label
, offset
);
11954 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
11955 (*chainp
)->next
= NULL
;
11956 (*chainp
)->symname
= XSTR (x
, 0);
11957 return plus_constant (aof_pic_label
, offset
);
11961 aof_dump_pic_table (f
)
11964 struct pic_chain
* chain
;
11966 if (aof_pic_chain
== NULL
)
11969 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
11970 PIC_OFFSET_TABLE_REGNUM
,
11971 PIC_OFFSET_TABLE_REGNUM
);
11972 fputs ("|x$adcons|\n", f
);
11974 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
11976 fputs ("\tDCD\t", f
);
11977 assemble_name (f
, chain
->symname
);
11982 int arm_text_section_count
= 1;
11985 aof_text_section ()
11987 static char buf
[100];
11988 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
11989 arm_text_section_count
++);
11991 strcat (buf
, ", PIC, REENTRANT");
11995 static int arm_data_section_count
= 1;
11998 aof_data_section ()
12000 static char buf
[100];
12001 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
12005 /* The AOF assembler is religiously strict about declarations of
12006 imported and exported symbols, so that it is impossible to declare
12007 a function as imported near the beginning of the file, and then to
12008 export it later on. It is, however, possible to delay the decision
12009 until all the functions in the file have been compiled. To get
12010 around this, we maintain a list of the imports and exports, and
12011 delete from it any that are subsequently defined. At the end of
12012 compilation we spit the remainder of the list out before the END
12017 struct import
* next
;
12021 static struct import
* imports_list
= NULL
;
12024 aof_add_import (name
)
12027 struct import
* new;
12029 for (new = imports_list
; new; new = new->next
)
12030 if (new->name
== name
)
12033 new = (struct import
*) xmalloc (sizeof (struct import
));
12034 new->next
= imports_list
;
12035 imports_list
= new;
12040 aof_delete_import (name
)
12043 struct import
** old
;
12045 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
12047 if ((*old
)->name
== name
)
12049 *old
= (*old
)->next
;
12055 int arm_main_function
= 0;
12058 aof_dump_imports (f
)
12061 /* The AOF assembler needs this to cause the startup code to be extracted
12062 from the library. Brining in __main causes the whole thing to work
12064 if (arm_main_function
)
12067 fputs ("\tIMPORT __main\n", f
);
12068 fputs ("\tDCD __main\n", f
);
12071 /* Now dump the remaining imports. */
12072 while (imports_list
)
12074 fprintf (f
, "\tIMPORT\t");
12075 assemble_name (f
, imports_list
->name
);
12077 imports_list
= imports_list
->next
;
12082 aof_globalize_label (stream
, name
)
12086 default_globalize_label (stream
, name
);
12087 if (! strcmp (name
, "main"))
12088 arm_main_function
= 1;
12090 #endif /* AOF_ASSEMBLER */
12092 #ifdef OBJECT_FORMAT_ELF
12093 /* Switch to an arbitrary section NAME with attributes as specified
12094 by FLAGS. ALIGN specifies any known alignment requirements for
12095 the section; 0 if the default should be used.
12097 Differs from the default elf version only in the prefix character
12098 used before the section type. */
12101 arm_elf_asm_named_section (name
, flags
)
12103 unsigned int flags
;
12105 char flagchars
[10], *f
= flagchars
;
12107 if (! named_section_first_declaration (name
))
12109 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
12113 if (!(flags
& SECTION_DEBUG
))
12115 if (flags
& SECTION_WRITE
)
12117 if (flags
& SECTION_CODE
)
12119 if (flags
& SECTION_SMALL
)
12121 if (flags
& SECTION_MERGE
)
12123 if (flags
& SECTION_STRINGS
)
12125 if (flags
& SECTION_TLS
)
12129 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
12131 if (!(flags
& SECTION_NOTYPE
))
12135 if (flags
& SECTION_BSS
)
12140 fprintf (asm_out_file
, ",%%%s", type
);
12142 if (flags
& SECTION_ENTSIZE
)
12143 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
12146 putc ('\n', asm_out_file
);
12151 /* Symbols in the text segment can be accessed without indirecting via the
12152 constant pool; it may take an extra binary operation, but this is still
12153 faster than indirecting via memory. Don't do this when not optimizing,
12154 since we won't be calculating al of the offsets necessary to do this
12158 arm_encode_section_info (decl
, rtl
, first
)
12163 /* This doesn't work with AOF syntax, since the string table may be in
12164 a different AREA. */
12165 #ifndef AOF_ASSEMBLER
12166 if (optimize
> 0 && TREE_CONSTANT (decl
)
12167 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
12168 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
12171 /* If we are referencing a function that is weak then encode a long call
12172 flag in the function name, otherwise if the function is static or
12173 or known to be defined in this file then encode a short call flag. */
12174 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
12176 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
12177 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
12178 else if (! TREE_PUBLIC (decl
))
12179 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
12182 #endif /* !ARM_PE */
12185 arm_internal_label (stream
, prefix
, labelno
)
12187 const char *prefix
;
12188 unsigned long labelno
;
12190 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
12191 && !strcmp (prefix
, "L"))
12193 arm_ccfsm_state
= 0;
12194 arm_target_insn
= NULL
;
12196 default_internal_label (stream
, prefix
, labelno
);
12199 /* Output code to add DELTA to the first argument, and then jump
12200 to FUNCTION. Used for C++ multiple inheritance. */
12203 arm_output_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
)
12205 tree thunk ATTRIBUTE_UNUSED
;
12206 HOST_WIDE_INT delta
;
12207 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
12210 int mi_delta
= delta
;
12211 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
12213 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)))
12216 mi_delta
= - mi_delta
;
12217 while (mi_delta
!= 0)
12219 if ((mi_delta
& (3 << shift
)) == 0)
12223 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
12224 mi_op
, this_regno
, this_regno
,
12225 mi_delta
& (0xff << shift
));
12226 mi_delta
&= ~(0xff << shift
);
12230 fputs ("\tb\t", file
);
12231 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
12232 if (NEED_PLT_RELOC
)
12233 fputs ("(PLT)", file
);
12234 fputc ('\n', file
);