gcc/testsuite/gcc.target/aarch64/sve/vcond_3.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize" } */
   3
   4 #include <stdint.h>
   5
   6 #define DEF_SEL_IMM(TYPE, SUFFIX, IMM)                                  \
   7 void                                                                    \
   8 sel_##TYPE##_##SUFFIX (TYPE *restrict a, TYPE *restrict b, int n)       \
   9 {                                                                       \
  10   for (int i = 0; i < n; i++)                                           \
  11     a[i] = b[i] != 0 ? IMM : 0;                                         \
  12 }
  13
  14 #define DEF_SEL_VAR(TYPE)                                               \
  15 void                                                                    \
  16 sel_##TYPE##_var (TYPE *restrict a, TYPE *restrict b, TYPE val, int n)  \
  17 {                                                                       \
  18   for (int i = 0; i < n; i++)                                           \
  19     a[i] = b[i] != 0 ? val : 0;                                         \
  20 }
  21
  22 #define TEST_TYPE8(TYPE)                        \
  23   DEF_SEL_VAR (TYPE)                            \
  24   DEF_SEL_IMM (TYPE, m128, -128)                \
  25   DEF_SEL_IMM (TYPE, m127, -127)                \
  26   DEF_SEL_IMM (TYPE, 2, 2)                      \
  27   DEF_SEL_IMM (TYPE, 127, 127)
  28
  29 #define TEST_TYPE16(TYPE)                       \
  30   TEST_TYPE8 (TYPE)                             \
  31   DEF_SEL_IMM (TYPE, m32768, -32768)            \
  32   DEF_SEL_IMM (TYPE, m32767, -32767)            \
  33   DEF_SEL_IMM (TYPE, m32512, -32512)            \
  34   DEF_SEL_IMM (TYPE, m32511, -32511)            \
  35   DEF_SEL_IMM (TYPE, m256, -256)                \
  36   DEF_SEL_IMM (TYPE, m255, -255)                \
  37   DEF_SEL_IMM (TYPE, m129, -129)                \
  38   DEF_SEL_IMM (TYPE, 128, 128)                  \
  39   DEF_SEL_IMM (TYPE, 256, 256)                  \
  40   DEF_SEL_IMM (TYPE, 32511, 32511)              \
  41   DEF_SEL_IMM (TYPE, 32512, 32512)              \
  42   DEF_SEL_IMM (TYPE, 32767, 32767)
  43
  44 #define TEST_TYPE32(TYPE)                       \
  45   TEST_TYPE16 (TYPE)                            \
  46   DEF_SEL_IMM (TYPE, m65536, -65536)            \
  47   DEF_SEL_IMM (TYPE, m32769, -32769)            \
  48   DEF_SEL_IMM (TYPE, 32768, 32768)
  49
  50 TEST_TYPE8 (int8_t)
  51 TEST_TYPE16 (int16_t)
  52 TEST_TYPE32 (int32_t)
  53 TEST_TYPE32 (int64_t)
  54
  55 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #-128\n} 1 } } */
  56 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #-127\n} 1 } } */
  57 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #2\n} 1 } } */
  58 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #127\n} 1 } } */
  59
  60 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-32768\n} 3 } } */
  61 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-32512\n} 3 } } */
  62 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-256\n} 3 } } */
  63 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-128\n} 3 } } */
  64 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-127\n} 3 } } */
  65 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #2\n} 3 } } */
  66 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #127\n} 3 } } */
  67 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #256\n} 3 } } */
  68 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #32512\n} 3 } } */