gcc/testsuite/gcc.target/aarch64/sve/uzp2_1_run.c

   1 /* { dg-do run { target aarch64_sve_hw } } */
   2 /* { dg-options "-O" } */
   3
   4 #include "uzp2_1.c"
   5
   6 #define TEST_UZP2(TYPE, EXPECTED_RESULT, VALUES1, VALUES2)              \
   7 {                                                                       \
   8   TYPE expected_result = EXPECTED_RESULT;                               \
   9   TYPE values1 = VALUES1;                                               \
  10   TYPE values2 = VALUES2;                                               \
  11   TYPE dest;                                                            \
  12   dest = uzp2_##TYPE (values1, values2);                                \
  13   if (__builtin_memcmp (&dest, &expected_result, sizeof (TYPE)) != 0)   \
  14     __builtin_abort ();                                                 \
  15 }
  16
  17 int main (void)
  18 {
  19   TEST_UZP2 (vnx2di,
  20              ((vnx2di) { 5, 7, 24, 48 }),
  21              ((vnx2di) { 4, 5, 6, 7 }),
  22              ((vnx2di) { 12, 24, 36, 48 }));
  23   TEST_UZP2 (vnx4si,
  24              ((vnx4si) { 4, 6, 8, 10, 34, 36, 38, 40 }),
  25              ((vnx4si) { 3, 4, 5, 6, 7, 8, 9, 10 }),
  26              ((vnx4si) { 33, 34, 35, 36, 37, 38, 39, 40 }));
  27   TEST_UZP2 (vnx8hi,
  28              ((vnx8hi) { 4, 6, 8, 10, 12, 14, 16, 18,
  29                          34, 36, 38, 40, 42, 44, 46, 48 }),
  30              ((vnx8hi) { 3, 4, 5, 6, 7, 8, 9, 10,
  31                          11, 12, 13, 14, 15, 16, 17, 18 }),
  32              ((vnx8hi) { 33, 34, 35, 36, 37, 38, 39, 40,
  33                          41, 42, 43, 44, 45, 46, 47, 48 }));
  34   TEST_UZP2 (vnx16qi,
  35              ((vnx16qi) { 5, 7, 5, 7, 5, 7, 5, 7,
  36                           5, 7, 5, 7, 5, 7, 5, 7,
  37                           24, 48, 24, 48, 24, 48, 24, 48,
  38                           24, 48, 24, 48, 24, 48, 24, 48 }),
  39              ((vnx16qi) { 4, 5, 6, 7, 4, 5, 6, 7,
  40                           4, 5, 6, 7, 4, 5, 6, 7,
  41                           4, 5, 6, 7, 4, 5, 6, 7,
  42                           4, 5, 6, 7, 4, 5, 6, 7 }),
  43              ((vnx16qi) { 12, 24, 36, 48, 12, 24, 36, 48,
  44                           12, 24, 36, 48, 12, 24, 36, 48,
  45                           12, 24, 36, 48, 12, 24, 36, 48,
  46                           12, 24, 36, 48, 12, 24, 36, 48 }));
  47   TEST_UZP2 (vnx2df,
  48              ((vnx2df) { 5.0, 7.0, 24.0, 48.0 }),
  49              ((vnx2df) { 4.0, 5.0, 6.0, 7.0 }),
  50              ((vnx2df) { 12.0, 24.0, 36.0, 48.0 }));
  51   TEST_UZP2 (vnx4sf,
  52              ((vnx4sf) { 4.0, 6.0, 8.0, 10.0, 34.0, 36.0, 38.0, 40.0 }),
  53              ((vnx4sf) { 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 }),
  54              ((vnx4sf) { 33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0, 40.0 }));
  55   TEST_UZP2 (vnx8hf,
  56              ((vnx8hf) { 4.0, 6.0, 8.0, 10.0, 12.0, 14.0, 16.0, 18.0,
  57                          34.0, 36.0, 38.0, 40.0, 42.0, 44.0, 46.0, 48.0 }),
  58              ((vnx8hf) { 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0,
  59                          11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0 }),
  60              ((vnx8hf) { 33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0, 40.0,
  61                          41.0, 42.0, 43.0, 44.0, 45.0, 46.0, 47.0, 48.0 }));
  62   return 0;
  63 }