gcc/testsuite/gcc.target/aarch64/sve/struct_move_1.c

   1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
   2 /* { dg-options "-O -msve-vector-bits=256 -mbig-endian --save-temps" } */
   3
   4 typedef char vnx16qi __attribute__((vector_size(32)));
   5 typedef struct { vnx16qi a[2]; } vnx32qi;
   6
   7 typedef short vnx8hi __attribute__((vector_size(32)));
   8 typedef struct { vnx8hi a[2]; } vnx16hi;
   9
  10 typedef int vnx4si __attribute__((vector_size(32)));
  11 typedef struct { vnx4si a[2]; } vnx8si;
  12
  13 typedef long vnx2di __attribute__((vector_size(32)));
  14 typedef struct { vnx2di a[2]; } vnx4di;
  15
  16 typedef _Float16 vnx8hf __attribute__((vector_size(32)));
  17 typedef struct { vnx8hf a[2]; } vnx16hf;
  18
  19 typedef float vnx4sf __attribute__((vector_size(32)));
  20 typedef struct { vnx4sf a[2]; } vnx8sf;
  21
  22 typedef double vnx2df __attribute__((vector_size(32)));
  23 typedef struct { vnx2df a[2]; } vnx4df;
  24
  25 #define TEST_TYPE(TYPE, REG1, REG2)                     \
  26   void                                                  \
  27   f1_##TYPE (TYPE *a)                                   \
  28   {                                                     \
  29     register TYPE x asm (#REG1) = a[0];                 \
  30     asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \
  31     register TYPE y asm (#REG2) = x;                    \
  32     asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2"    \
  33                   : "=&w" (x) : "0" (x), "w" (y));      \
  34     a[1] = x;                                           \
  35   }                                                     \
  36   /* This must compile, but we don't care how.  */      \
  37   void                                                  \
  38   f2_##TYPE (TYPE *a)                                   \
  39   {                                                     \
  40     TYPE x = a[0];                                      \
  41     x.a[0][3] = 1;                                      \
  42     x.a[1][2] = 12;                                     \
  43     asm volatile ("# %0" :: "w" (x));                   \
  44   }                                                     \
  45   void                                                  \
  46   f3_##TYPE (TYPE *a, int i)                            \
  47   {                                                     \
  48     TYPE x = a[0];                                      \
  49     x.a[0][i] = 1;                                      \
  50     asm volatile ("# %0" :: "w" (x));                   \
  51   }                                                     \
  52   void                                                  \
  53   f4_##TYPE (TYPE *a, int i, int j)                     \
  54   {                                                     \
  55     TYPE x = a[0];                                      \
  56     x.a[i][j] = 44;                                     \
  57     asm volatile ("# %0" :: "w" (x));                   \
  58   }
  59
  60 TEST_TYPE (vnx32qi, z0, z2)
  61 TEST_TYPE (vnx16hi, z5, z7)
  62 TEST_TYPE (vnx8si, z10, z12)
  63 TEST_TYPE (vnx4di, z15, z17)
  64 TEST_TYPE (vnx16hf, z18, z20)
  65 TEST_TYPE (vnx8sf, z21, z23)
  66 TEST_TYPE (vnx4df, z28, z30)
  67
  68 /* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */
  69 /* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
  70 /* { dg-final { scan-assembler { test vnx32qi 1 z0\n} } } */
  71 /* { dg-final { scan-assembler {\tmov\tz2.d, z0.d\n} } } */
  72 /* { dg-final { scan-assembler {\tmov\tz3.d, z1.d\n} } } */
  73 /* { dg-final { scan-assembler { test vnx32qi 2 z0, z0, z2\n} } } */
  74 /* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #2, mul vl\]\n} } } */
  75 /* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #3, mul vl\]\n} } } */
  76
  77 /* { dg-final { scan-assembler {\tld1h\tz5.h, p[0-7]/z, \[x0\]\n} } } */
  78 /* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
  79 /* { dg-final { scan-assembler { test vnx16hi 1 z5\n} } } */
  80 /* { dg-final { scan-assembler {\tmov\tz7.d, z5.d\n} } } */
  81 /* { dg-final { scan-assembler {\tmov\tz8.d, z6.d\n} } } */
  82 /* { dg-final { scan-assembler { test vnx16hi 2 z5, z5, z7\n} } } */
  83 /* { dg-final { scan-assembler {\tst1h\tz5.h, p[0-7], \[x0, #2, mul vl\]\n} } } */
  84 /* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #3, mul vl\]\n} } } */
  85
  86 /* { dg-final { scan-assembler {\tld1w\tz10.s, p[0-7]/z, \[x0\]\n} } } */
  87 /* { dg-final { scan-assembler {\tld1w\tz11.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
  88 /* { dg-final { scan-assembler { test vnx8si 1 z10\n} } } */
  89 /* { dg-final { scan-assembler {\tmov\tz12.d, z10.d\n} } } */
  90 /* { dg-final { scan-assembler {\tmov\tz13.d, z11.d\n} } } */
  91 /* { dg-final { scan-assembler { test vnx8si 2 z10, z10, z12\n} } } */
  92 /* { dg-final { scan-assembler {\tst1w\tz10.s, p[0-7], \[x0, #2, mul vl\]\n} } } */
  93 /* { dg-final { scan-assembler {\tst1w\tz11.s, p[0-7], \[x0, #3, mul vl\]\n} } } */
  94
  95 /* { dg-final { scan-assembler {\tld1d\tz15.d, p[0-7]/z, \[x0\]\n} } } */
  96 /* { dg-final { scan-assembler {\tld1d\tz16.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
  97 /* { dg-final { scan-assembler { test vnx4di 1 z15\n} } } */
  98 /* { dg-final { scan-assembler {\tmov\tz17.d, z15.d\n} } } */
  99 /* { dg-final { scan-assembler {\tmov\tz18.d, z16.d\n} } } */
 100 /* { dg-final { scan-assembler { test vnx4di 2 z15, z15, z17\n} } } */
 101 /* { dg-final { scan-assembler {\tst1d\tz15.d, p[0-7], \[x0, #2, mul vl\]\n} } } */
 102 /* { dg-final { scan-assembler {\tst1d\tz16.d, p[0-7], \[x0, #3, mul vl\]\n} } } */
 103
 104 /* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */
 105 /* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
 106 /* { dg-final { scan-assembler { test vnx16hf 1 z18\n} } } */
 107 /* { dg-final { scan-assembler {\tmov\tz20.d, z18.d\n} } } */
 108 /* { dg-final { scan-assembler {\tmov\tz21.d, z19.d\n} } } */
 109 /* { dg-final { scan-assembler { test vnx16hf 2 z18, z18, z20\n} } } */
 110 /* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #2, mul vl\]\n} } } */
 111 /* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #3, mul vl\]\n} } } */
 112
 113 /* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0\]\n} } } */
 114 /* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
 115 /* { dg-final { scan-assembler { test vnx8sf 1 z21\n} } } */
 116 /* { dg-final { scan-assembler {\tmov\tz23.d, z21.d\n} } } */
 117 /* { dg-final { scan-assembler {\tmov\tz24.d, z22.d\n} } } */
 118 /* { dg-final { scan-assembler { test vnx8sf 2 z21, z21, z23\n} } } */
 119 /* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #2, mul vl\]\n} } } */
 120 /* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #3, mul vl\]\n} } } */
 121
 122 /* { dg-final { scan-assembler {\tld1d\tz28.d, p[0-7]/z, \[x0\]\n} } } */
 123 /* { dg-final { scan-assembler {\tld1d\tz29.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */
 124 /* { dg-final { scan-assembler { test vnx4df 1 z28\n} } } */
 125 /* { dg-final { scan-assembler {\tmov\tz30.d, z28.d\n} } } */
 126 /* { dg-final { scan-assembler {\tmov\tz31.d, z29.d\n} } } */
 127 /* { dg-final { scan-assembler { test vnx4df 2 z28, z28, z30\n} } } */
 128 /* { dg-final { scan-assembler {\tst1d\tz28.d, p[0-7], \[x0, #2, mul vl\]\n} } } */
 129 /* { dg-final { scan-assembler {\tst1d\tz29.d, p[0-7], \[x0, #3, mul vl\]\n} } } */