gcc/testsuite/gcc.target/aarch64/sve/slp_5.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable -ffast-math" } */
   3
   4 #include <stdint.h>
   5
   6 #define VEC_PERM(TYPE)                                          \
   7 void __attribute__ ((noinline, noclone))                        \
   8 vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b, int n)      \
   9 {                                                               \
  10   TYPE x0 = b[0];                                               \
  11   TYPE x1 = b[1];                                               \
  12   for (int i = 0; i < n; ++i)                                   \
  13     {                                                           \
  14       x0 += a[i * 2];                                           \
  15       x1 += a[i * 2 + 1];                                       \
  16     }                                                           \
  17   b[0] = x0;                                                    \
  18   b[1] = x1;                                                    \
  19 }
  20
  21 #define TEST_ALL(T)                             \
  22   T (int8_t)                                    \
  23   T (uint8_t)                                   \
  24   T (int16_t)                                   \
  25   T (uint16_t)                                  \
  26   T (int32_t)                                   \
  27   T (uint32_t)                                  \
  28   T (int64_t)                                   \
  29   T (uint64_t)                                  \
  30   T (_Float16)                                  \
  31   T (float)                                     \
  32   T (double)
  33
  34 TEST_ALL (VEC_PERM)
  35
  36 /* ??? We don't think it's worth using SLP for the 64-bit loops and fall
  37    back to the less efficient non-SLP implementation instead.  */
  38 /* ??? At present we don't treat the int8_t and int16_t loops as
  39    reductions.  */
  40 /* { dg-final { scan-assembler-times {\tld1b\t} 2 { xfail *-*-* } } } */
  41 /* { dg-final { scan-assembler-times {\tld1h\t} 3 { xfail *-*-* } } } */
  42 /* { dg-final { scan-assembler-times {\tld1b\t} 1 } } */
  43 /* { dg-final { scan-assembler-times {\tld1h\t} 2 } } */
  44 /* { dg-final { scan-assembler-times {\tld1w\t} 3 } } */
  45 /* { dg-final { scan-assembler-times {\tld1d\t} 3 { xfail *-*-* } } } */
  46 /* { dg-final { scan-assembler-not {\tld2b\t} } } */
  47 /* { dg-final { scan-assembler-not {\tld2h\t} } } */
  48 /* { dg-final { scan-assembler-not {\tld2w\t} } } */
  49 /* { dg-final { scan-assembler-not {\tld2d\t} { xfail *-*-* } } } */
  50 /* { dg-final { scan-assembler-times {\tuaddv\td[0-9]+, p[0-7], z[0-9]+\.b} 4 { xfail *-*-* } } } */
  51 /* { dg-final { scan-assembler-times {\tuaddv\td[0-9]+, p[0-7], z[0-9]+\.h} 4 { xfail *-*-* } } } */
  52 /* { dg-final { scan-assembler-times {\tuaddv\td[0-9]+, p[0-7], z[0-9]+\.b} 2 } } */
  53 /* { dg-final { scan-assembler-times {\tuaddv\td[0-9]+, p[0-7], z[0-9]+\.h} 2 } } */
  54 /* { dg-final { scan-assembler-times {\tuaddv\td[0-9]+, p[0-7], z[0-9]+\.s} 4 } } */
  55 /* { dg-final { scan-assembler-times {\tuaddv\td[0-9]+, p[0-7], z[0-9]+\.d} 4 } } */
  56 /* { dg-final { scan-assembler-times {\tfaddv\th[0-9]+, p[0-7], z[0-9]+\.h} 2 } } */
  57 /* { dg-final { scan-assembler-times {\tfaddv\ts[0-9]+, p[0-7], z[0-9]+\.s} 2 } } */
  58 /* { dg-final { scan-assembler-times {\tfaddv\td[0-9]+, p[0-7], z[0-9]+\.d} 2 } } */
  59
  60 /* Should be 4 and 6 respectively, if we used reductions for int8_t and
  61    int16_t.  */
  62 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.b} 2 } } */
  63 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h} 4 } } */
  64 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 6 } } */
  65 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 6 } } */
  66
  67 /* { dg-final { scan-assembler-not {\tuqdec} } } */