Add support for conditional reductions using SVE CLASTB
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / slp_12.c
blob0b9f8d9bdfaaf868ba0bd73ae83894c68e1613f8
1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable" } */
4 #include <stdint.h>
6 #define N1 (19 * 2)
8 #define VEC_PERM(TYPE) \
9 void __attribute__ ((noinline, noclone)) \
10 vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b) \
11 { \
12 for (int i = 0; i < N1; ++i) \
13 { \
14 a[i] += 1; \
15 b[i * 4] += 2; \
16 b[i * 4 + 1] += 3; \
17 b[i * 4 + 2] += 4; \
18 b[i * 4 + 3] += 5; \
19 } \
22 #define TEST_ALL(T) \
23 T (int8_t) \
24 T (uint8_t) \
25 T (int16_t) \
26 T (uint16_t) \
27 T (int32_t) \
28 T (uint32_t) \
29 T (int64_t) \
30 T (uint64_t) \
31 T (float) \
32 T (double)
34 TEST_ALL (VEC_PERM)
36 /* The loop should be fully-masked. */
37 /* { dg-final { scan-assembler-times {\tld1b\t} 10 } } */
38 /* { dg-final { scan-assembler-times {\tst1b\t} 10 } } */
39 /* { dg-final { scan-assembler-times {\tld1h\t} 10 } } */
40 /* { dg-final { scan-assembler-times {\tst1h\t} 10 } } */
41 /* { dg-final { scan-assembler-times {\tld1w\t} 15 } } */
42 /* { dg-final { scan-assembler-times {\tst1w\t} 15 } } */
43 /* { dg-final { scan-assembler-times {\tld1d\t} 15 } } */
44 /* { dg-final { scan-assembler-times {\tst1d\t} 15 } } */
45 /* { dg-final { scan-assembler-not {\tldr} } } */
46 /* { dg-final { scan-assembler-not {\tstr} } } */
48 /* We should use WHILEs for all accesses. */
49 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.b} 20 } } */
50 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h} 20 } } */
51 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 30 } } */
52 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 30 } } */
54 /* 6 for the 8-bit types and 2 for the 16-bit types. */
55 /* { dg-final { scan-assembler-times {\tuqdecb\t} 8 } } */
56 /* 4 for the 16-bit types and 3 for the 32-bit types. */
57 /* { dg-final { scan-assembler-times {\tuqdech\t} 7 } } */
58 /* 6 for the 32-bit types and 3 for the 64-bit types. */
59 /* { dg-final { scan-assembler-times {\tuqdecw\t} 9 } } */
60 /* { dg-final { scan-assembler-times {\tuqdecd\t} 6 } } */