Add support for conditional reductions using SVE CLASTB
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / single_2.c
blob1ef72b62e0a4a0d72ae184005ed53137f6a91eb5
1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -fopenmp-simd -msve-vector-bits=512" } */
4 #define N 64
5 #include "single_1.c"
7 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, #1\n} 1 } } */
8 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, #2\n} 1 } } */
9 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, #3\n} 1 } } */
10 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, #4\n} 1 } } */
11 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, #5\n} 1 } } */
12 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, #6\n} 1 } } */
13 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #7\n} 1 } } */
14 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #8\n} 1 } } */
15 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, #15360\n} 1 } } */
16 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0e\+0\n} 1 } } */
17 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3\.0e\+0\n} 1 } } */
19 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl64\n} 2 } } */
20 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.h, vl32\n} 3 } } */
21 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s, vl16\n} 3 } } */
22 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d, vl8\n} 3 } } */
24 /* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b,} 2 } } */
25 /* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 } } */
26 /* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
27 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
29 /* { dg-final { scan-assembler-not {\twhile} } } */
30 /* { dg-final { scan-assembler-not {\tb} } } */
31 /* { dg-final { scan-assembler-not {\tcmp} } } */
32 /* { dg-final { scan-assembler-not {\tindex} } } */