Add support for conditional reductions using SVE CLASTB
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / single_1.c
bloba5dd5ebfaedb4d3ae7c54a965d05b28ed48fcc8f
1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -fopenmp-simd -msve-vector-bits=256" } */
4 #ifndef N
5 #define N 32
6 #endif
8 #include <stdint.h>
10 #define TEST_LOOP(TYPE, VALUE) \
11 void \
12 test_##TYPE (TYPE *data) \
13 { \
14 _Pragma ("omp simd") \
15 for (int i = 0; i < N / sizeof (TYPE); ++i) \
16 data[i] = VALUE; \
19 TEST_LOOP (uint8_t, 1)
20 TEST_LOOP (int8_t, 2)
21 TEST_LOOP (uint16_t, 3)
22 TEST_LOOP (int16_t, 4)
23 TEST_LOOP (uint32_t, 5)
24 TEST_LOOP (int32_t, 6)
25 TEST_LOOP (uint64_t, 7)
26 TEST_LOOP (int64_t, 8)
27 TEST_LOOP (_Float16, 1.0f)
28 TEST_LOOP (float, 2.0f)
29 TEST_LOOP (double, 3.0)
31 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, #1\n} 1 } } */
32 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, #2\n} 1 } } */
33 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, #3\n} 1 } } */
34 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, #4\n} 1 } } */
35 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, #5\n} 1 } } */
36 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, #6\n} 1 } } */
37 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #7\n} 1 } } */
38 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #8\n} 1 } } */
39 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, #15360\n} 1 } } */
40 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0e\+0\n} 1 } } */
41 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3\.0e\+0\n} 1 } } */
43 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl32\n} 2 } } */
44 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.h, vl16\n} 3 } } */
45 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s, vl8\n} 3 } } */
46 /* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d, vl4\n} 3 } } */
48 /* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b,} 2 } } */
49 /* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 } } */
50 /* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
51 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
53 /* { dg-final { scan-assembler-not {\twhile} } } */
54 /* { dg-final { scan-assembler-not {\tb} } } */
55 /* { dg-final { scan-assembler-not {\tcmp} } } */
56 /* { dg-final { scan-assembler-not {\tindex} } } */