gcc/testsuite/gcc.target/aarch64/sve/rev_1.c

   1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
   2 /* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
   3
   4 #include <stdint.h>
   5
   6 typedef int8_t vnx16qi __attribute__((vector_size (32)));
   7 typedef int16_t vnx8hi __attribute__((vector_size (32)));
   8 typedef int32_t vnx4si __attribute__((vector_size (32)));
   9 typedef int64_t vnx2di __attribute__((vector_size (32)));
  10 typedef _Float16 vnx8hf __attribute__((vector_size (32)));
  11 typedef float vnx4sf __attribute__((vector_size (32)));
  12 typedef double vnx2df __attribute__((vector_size (32)));
  13
  14 #define MASK_2(X, Y) (Y) - 1 - (X), (Y) - 2 - (X)
  15 #define MASK_4(X, Y) MASK_2 (X, Y), MASK_2 (X + 2, Y)
  16 #define MASK_8(X, Y) MASK_4 (X, Y), MASK_4 (X + 4, Y)
  17 #define MASK_16(X, Y) MASK_8 (X, Y), MASK_8 (X + 8, Y)
  18 #define MASK_32(X, Y) MASK_16 (X, Y), MASK_16 (X + 16, Y)
  19
  20 #define INDEX_32 vnx16qi
  21 #define INDEX_16 vnx8hi
  22 #define INDEX_8 vnx4si
  23 #define INDEX_4 vnx2di
  24
  25 #define PERMUTE(TYPE, NUNITS)                                           \
  26   TYPE permute_##TYPE (TYPE values1, TYPE values2)                      \
  27   {                                                                     \
  28     return __builtin_shuffle                                            \
  29       (values1, values2,                                                \
  30        ((INDEX_##NUNITS) { MASK_##NUNITS (0, NUNITS) }));               \
  31   }
  32
  33 #define TEST_ALL(T)                             \
  34   T (vnx16qi, 32)                               \
  35   T (vnx8hi, 16)                                \
  36   T (vnx4si, 8)                                 \
  37   T (vnx2di, 4)                                 \
  38   T (vnx8hf, 16)                                \
  39   T (vnx4sf, 8)                                 \
  40   T (vnx2df, 4)
  41
  42 TEST_ALL (PERMUTE)
  43
  44 /* { dg-final { scan-assembler-not {\ttbl\t} } } */
  45
  46 /* { dg-final { scan-assembler-times {\trev\tz[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
  47 /* { dg-final { scan-assembler-times {\trev\tz[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
  48 /* { dg-final { scan-assembler-times {\trev\tz[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
  49 /* { dg-final { scan-assembler-times {\trev\tz[0-9]+\.d, z[0-9]+\.d\n} 2 } } */