gcc/testsuite/gcc.target/aarch64/sve/mask_struct_load_3.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
   3
   4 #define TEST_LOOP(NAME, OUTTYPE, INTYPE, MASKTYPE)              \
   5   void __attribute__ ((noinline, noclone))                      \
   6   NAME##_4 (OUTTYPE *__restrict dest, INTYPE *__restrict src,   \
   7             MASKTYPE *__restrict cond, int n)                   \
   8   {                                                             \
   9     for (int i = 0; i < n; ++i)                                 \
  10       if (cond[i])                                              \
  11         dest[i] = (src[i * 4]                                   \
  12                    + src[i * 4 + 1]                             \
  13                    + src[i * 4 + 2]                             \
  14                    + src[i * 4 + 3]);                           \
  15   }
  16
  17 #define TEST2(NAME, OUTTYPE, INTYPE) \
  18   TEST_LOOP (NAME##_i8, OUTTYPE, INTYPE, signed char) \
  19   TEST_LOOP (NAME##_i16, OUTTYPE, INTYPE, unsigned short) \
  20   TEST_LOOP (NAME##_f32, OUTTYPE, INTYPE, float) \
  21   TEST_LOOP (NAME##_f64, OUTTYPE, INTYPE, double)
  22
  23 #define TEST1(NAME, OUTTYPE) \
  24   TEST2 (NAME##_i8, OUTTYPE, signed char) \
  25   TEST2 (NAME##_i16, OUTTYPE, unsigned short) \
  26   TEST2 (NAME##_i32, OUTTYPE, int) \
  27   TEST2 (NAME##_i64, OUTTYPE, unsigned long)
  28
  29 #define TEST(NAME) \
  30   TEST1 (NAME##_i8, signed char) \
  31   TEST1 (NAME##_i16, unsigned short) \
  32   TEST1 (NAME##_i32, int) \
  33   TEST1 (NAME##_i64, unsigned long) \
  34   TEST2 (NAME##_f16_f16, _Float16, _Float16) \
  35   TEST2 (NAME##_f32_f32, float, float) \
  36   TEST2 (NAME##_f64_f64, double, double)
  37
  38 TEST (test)
  39
  40 /*    Mask |  8 16 32 64
  41     -------+------------
  42     Out  8 |  1  1  1  1
  43         16 |  1  1  1  1
  44         32 |  1  1  1  1
  45         64 |  1  1  1  1.  */
  46 /* { dg-final { scan-assembler-times {\tld4b\t.z[0-9]} 16 } } */
  47
  48 /*    Mask |  8 16 32 64
  49     -------+------------
  50     Out  8 |  2  2  2  2
  51         16 |  2  1  1  1 x2 (for half float)
  52         32 |  2  1  1  1
  53         64 |  2  1  1  1.  */
  54 /* { dg-final { scan-assembler-times {\tld4h\t.z[0-9]} 28 } } */
  55
  56 /*    Mask |  8 16 32 64
  57     -------+------------
  58     Out  8 |  4  4  4  4
  59         16 |  4  2  2  2
  60         32 |  4  2  1  1 x2 (for float)
  61         64 |  4  2  1  1.  */
  62 /* { dg-final { scan-assembler-times {\tld4w\t.z[0-9]} 50 } } */
  63
  64 /*    Mask |  8 16 32 64
  65     -------+------------
  66     Out  8 |  8  8  8  8
  67         16 |  8  4  4  4
  68         32 |  8  4  2  2
  69         64 |  8  4  2  1 x2 (for double).  */
  70 /* { dg-final { scan-assembler-times {\tld4d\t.z[0-9]} 98 } } */