gcc/testsuite/gcc.target/aarch64/sve/mad_1.c

   1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
   2 /* { dg-options "-O3 -msve-vector-bits=256 --save-temps" } */
   3
   4 #include <stdint.h>
   5
   6 typedef int8_t vnx16qi __attribute__((vector_size(32)));
   7 typedef int16_t vnx8hi __attribute__((vector_size(32)));
   8 typedef int32_t vnx4si __attribute__((vector_size(32)));
   9 typedef int64_t vnx2di __attribute__((vector_size(32)));
  10
  11 #define DO_OP(TYPE)                                             \
  12 void vmla_##TYPE (TYPE *x, TYPE y, TYPE z)                      \
  13 {                                                               \
  14   register TYPE dst  asm("z0");                                 \
  15   register TYPE src1 asm("z2");                                 \
  16   register TYPE src2 asm("z4");                                 \
  17   dst = *x;                                                     \
  18   src1 = y;                                                     \
  19   src2 = z;                                                     \
  20   asm volatile ("" :: "w" (dst), "w" (src1), "w" (src2));       \
  21   dst = (dst * src1) + src2;                                    \
  22   asm volatile ("" :: "w" (dst));                               \
  23   *x = dst;                                                     \
  24 }
  25
  26 DO_OP (vnx16qi)
  27 DO_OP (vnx8hi)
  28 DO_OP (vnx4si)
  29 DO_OP (vnx2di)
  30
  31 /* { dg-final { scan-assembler-times {\tmad\tz0\.b, p[0-7]/m, z2\.b, z4\.b} 1 } } */
  32 /* { dg-final { scan-assembler-times {\tmad\tz0\.h, p[0-7]/m, z2\.h, z4\.h} 1 } } */
  33 /* { dg-final { scan-assembler-times {\tmad\tz0\.s, p[0-7]/m, z2\.s, z4\.s} 1 } } */
  34 /* { dg-final { scan-assembler-times {\tmad\tz0\.d, p[0-7]/m, z2\.d, z4\.d} 1 } } */