gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_1.c

   1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
   2 /* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
   3
   4 #include <stdint.h>
   5
   6 typedef int64_t vnx2di __attribute__ ((vector_size (32)));
   7 typedef int32_t vnx4si __attribute__ ((vector_size (32)));
   8 typedef int16_t vnx8hi __attribute__ ((vector_size (32)));
   9 typedef int8_t vnx16qi __attribute__ ((vector_size (32)));
  10
  11 #define TEST_TYPE(TYPE)                                         \
  12   void sve_load_##TYPE##_neg9 (TYPE *a)                         \
  13   {                                                             \
  14     register TYPE x asm ("z0") = a[-9];                         \
  15     asm volatile ("" :: "w" (x));                               \
  16   }                                                             \
  17                                                                 \
  18   void sve_load_##TYPE##_neg8 (TYPE *a)                         \
  19   {                                                             \
  20     register TYPE x asm ("z0") = a[-8];                         \
  21     asm volatile ("" :: "w" (x));                               \
  22   }                                                             \
  23                                                                 \
  24   void sve_load_##TYPE##_0 (TYPE *a)                            \
  25   {                                                             \
  26     register TYPE x asm ("z0") = a[0];                          \
  27     asm volatile ("" :: "w" (x));                               \
  28   }                                                             \
  29                                                                 \
  30   void sve_load_##TYPE##_unaligned (TYPE *a)                    \
  31   {                                                             \
  32     register TYPE x asm ("z0") = *(TYPE *) ((char *) a + 16);   \
  33     asm volatile ("" :: "w" (x));                               \
  34   }                                                             \
  35                                                                 \
  36   void sve_load_##TYPE##_7 (TYPE *a)                            \
  37   {                                                             \
  38     register TYPE x asm ("z0") = a[7];                          \
  39     asm volatile ("" :: "w" (x));                               \
  40   }                                                             \
  41                                                                 \
  42   void sve_load_##TYPE##_8 (TYPE *a)                            \
  43   {                                                             \
  44     register TYPE x asm ("z0") = a[8];                          \
  45     asm volatile ("" :: "w" (x));                               \
  46   }
  47
  48 TEST_TYPE (vnx2di)
  49 TEST_TYPE (vnx4si)
  50 TEST_TYPE (vnx8hi)
  51 TEST_TYPE (vnx16qi)
  52
  53 /* { dg-final { scan-assembler-times {\tsub\tx[0-9]+, x0, #288\n} 4 } } */
  54 /* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x0, 16\n} 4 } } */
  55 /* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x0, 256\n} 4 } } */
  56
  57 /* { dg-final { scan-assembler-not {\tld1d\tz0\.d, p[0-7]/z, \[x0, #-9, mul vl\]\n} } } */
  58 /* { dg-final { scan-assembler-times {\tld1d\tz0\.d, p[0-7]/z, \[x0, #-8, mul vl\]\n} 1 } } */
  59 /* { dg-final { scan-assembler-times {\tld1d\tz0\.d, p[0-7]/z, \[x0\]\n} 4 } } */
  60 /* { dg-final { scan-assembler-times {\tld1d\tz0\.d, p[0-7]/z, \[x0, #7, mul vl\]\n} 1 } } */
  61 /* { dg-final { scan-assembler-not {\tld1d\tz0\.d, p[0-7]/z, \[x0, #8, mul vl\]\n} } } */
  62
  63 /* { dg-final { scan-assembler-not {\tld1w\tz0\.s, p[0-7]/z, \[x0, #-9, mul vl\]\n} } } */
  64 /* { dg-final { scan-assembler-times {\tld1w\tz0\.s, p[0-7]/z, \[x0, #-8, mul vl\]\n} 1 } } */
  65 /* { dg-final { scan-assembler-times {\tld1w\tz0\.s, p[0-7]/z, \[x0\]\n} 4 } } */
  66 /* { dg-final { scan-assembler-times {\tld1w\tz0\.s, p[0-7]/z, \[x0, #7, mul vl\]\n} 1 } } */
  67 /* { dg-final { scan-assembler-not {\tld1w\tz0\.s, p[0-7]/z, \[x0, #8, mul vl\]\n} } } */
  68
  69 /* { dg-final { scan-assembler-not {\tld1h\tz0\.h, p[0-7]/z, \[x0, #-9, mul vl\]\n} } } */
  70 /* { dg-final { scan-assembler-times {\tld1h\tz0\.h, p[0-7]/z, \[x0, #-8, mul vl\]\n} 1 } } */
  71 /* { dg-final { scan-assembler-times {\tld1h\tz0\.h, p[0-7]/z, \[x0\]\n} 4 } } */
  72 /* { dg-final { scan-assembler-times {\tld1h\tz0\.h, p[0-7]/z, \[x0, #7, mul vl\]\n} 1 } } */
  73 /* { dg-final { scan-assembler-not {\tld1h\tz0\.h, p[0-7]/z, \[x0, #8, mul vl\]\n} } } */
  74
  75 /* { dg-final { scan-assembler-not {\tld1b\tz0\.b, p[0-7]/z, \[x0, #-9, mul vl\]\n} } } */
  76 /* { dg-final { scan-assembler-times {\tld1b\tz0\.b, p[0-7]/z, \[x0, #-8, mul vl\]\n} 1 } } */
  77 /* { dg-final { scan-assembler-times {\tld1b\tz0\.b, p[0-7]/z, \[x0\]\n} 4 } } */
  78 /* { dg-final { scan-assembler-times {\tld1b\tz0\.b, p[0-7]/z, \[x0, #7, mul vl\]\n} 1 } } */
  79 /* { dg-final { scan-assembler-not {\tld1b\tz0\.b, p[0-7]/z, \[x0, #8, mul vl\]\n} } } */