Add support for conditional reductions using SVE CLASTB
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / fdiv_1.c
bloba930ec542d0f8624e1bde0d97ff9105d01657528
1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
2 /* { dg-options "-O3 -msve-vector-bits=256 --save-temps" } */
4 typedef _Float16 vnx8hf __attribute__((vector_size(32)));
5 typedef float vnx4sf __attribute__((vector_size(32)));
6 typedef double vnx2df __attribute__((vector_size(32)));
8 #define DO_OP(TYPE) \
9 void vdiv_##TYPE (TYPE *x, TYPE y) \
10 { \
11 register TYPE dst asm("z0"); \
12 register TYPE src asm("z2"); \
13 dst = *x; \
14 src = y; \
15 asm volatile ("" :: "w" (dst), "w" (src)); \
16 dst = dst / src; \
17 asm volatile ("" :: "w" (dst)); \
18 *x = dst; \
19 } \
20 void vdivr_##TYPE (TYPE *x, TYPE y) \
21 { \
22 register TYPE dst asm("z0"); \
23 register TYPE src asm("z2"); \
24 dst = *x; \
25 src = y; \
26 asm volatile ("" :: "w" (dst), "w" (src)); \
27 dst = src / dst; \
28 asm volatile ("" :: "w" (dst)); \
29 *x = dst; \
32 DO_OP (vnx8hf)
33 DO_OP (vnx4sf)
34 DO_OP (vnx2df)
36 /* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
37 /* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
39 /* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
40 /* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
42 /* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
43 /* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */