Add support for conditional reductions using SVE CLASTB
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / fcvtz_unsigned_1.c
blob9d735a8520c1db9b3e30ba0e596640b3c479e8f5
1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
2 /* { dg-options "-O3 --save-temps" } */
4 #include <stdint.h>
6 void __attribute__ ((noinline, noclone))
7 vfcvtz_16 (uint16_t *dst, _Float16 *src1, int size)
9 for (int i = 0; i < size; i++)
10 dst[i] = (uint16_t) src1[i];
13 void __attribute__ ((noinline, noclone))
14 vfcvtz_32 (uint32_t *dst, float *src1, int size)
16 for (int i = 0; i < size; i++)
17 dst[i] = (uint32_t) src1[i];
20 void __attribute__ ((noinline, noclone))
21 vfcvtz_64 (uint64_t *dst, double *src1, int size)
23 for (int i = 0; i < size; i++)
24 dst[i] = (uint64_t) src1[i];
27 /* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 1 } } */
28 /* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
29 /* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 1 } } */