1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 /* The maximum number of insns skipped which will be conditionalised if
46 static int max_insns_skipped
= 5;
48 extern FILE * asm_out_file
;
49 /* Some function declarations. */
51 static HOST_WIDE_INT int_log2
PROTO ((HOST_WIDE_INT
));
52 static char * output_multi_immediate
PROTO ((rtx
*, char *, char *, int,
54 static int arm_gen_constant
PROTO ((enum rtx_code
, enum machine_mode
,
55 HOST_WIDE_INT
, rtx
, rtx
, int, int));
56 static int arm_naked_function_p
PROTO ((tree
));
57 static void init_fpa_table
PROTO ((void));
58 static enum machine_mode select_dominance_cc_mode
PROTO ((rtx
, rtx
,
60 static HOST_WIDE_INT add_minipool_constant
PROTO ((rtx
, enum machine_mode
));
61 static void dump_minipool
PROTO ((rtx
));
62 static rtx find_barrier
PROTO ((rtx
, int));
63 static void push_minipool_fix
PROTO ((rtx
, int, rtx
*, enum machine_mode
,
65 static void push_minipool_barrier
PROTO ((rtx
, int));
66 static void note_invalid_constants
PROTO ((rtx
, int));
67 static char * fp_const_from_val
PROTO ((REAL_VALUE_TYPE
*));
68 static int eliminate_lr2ip
PROTO ((rtx
*));
69 static char * shift_op
PROTO ((rtx
, HOST_WIDE_INT
*));
70 static int pattern_really_clobbers_lr
PROTO ((rtx
));
71 static int function_really_clobbers_lr
PROTO ((rtx
));
72 static void emit_multi_reg_push
PROTO ((int));
73 static void emit_sfm
PROTO ((int, int));
74 static enum arm_cond_code get_arm_condition_code
PROTO ((rtx
));
75 static int const_ok_for_op
RTX_CODE_PROTO ((HOST_WIDE_INT
, Rcode
));
76 static void arm_add_gc_roots
PROTO ((void));
78 /* True if we are currently building a constant table. */
79 int making_const_table
;
81 /* Define the information needed to generate branch insns. This is
82 stored from the compare operation. */
83 rtx arm_compare_op0
, arm_compare_op1
;
85 /* What type of floating point are we tuning for? */
86 enum floating_point_type arm_fpu
;
88 /* What type of floating point instructions are available? */
89 enum floating_point_type arm_fpu_arch
;
91 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
92 enum prog_mode_type arm_prgmode
;
94 /* Set by the -mfp=... option */
95 const char * target_fp_name
= NULL
;
97 /* Used to parse -mstructure_size_boundary command line option. */
98 const char * structure_size_string
= NULL
;
99 int arm_structure_size_boundary
= 32; /* Used to be 8 */
101 /* Bit values used to identify processor capabilities. */
102 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
103 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
104 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
105 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
106 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
107 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
108 #define FL_THUMB (1 << 6) /* Thumb aware */
109 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
110 #define FL_STRONG (1 << 8) /* StrongARM */
112 /* The bits in this mask specify which instructions we are allowed to
114 static int insn_flags
= 0;
115 /* The bits in this mask specify which instruction scheduling options should
116 be used. Note - there is an overlap with the FL_FAST_MULT. For some
117 hardware we want to be able to generate the multiply instructions, but to
118 tune as if they were not present in the architecture. */
119 static int tune_flags
= 0;
121 /* The following are used in the arm.md file as equivalents to bits
122 in the above two flag variables. */
124 /* Nonzero if this is an "M" variant of the processor. */
125 int arm_fast_multiply
= 0;
127 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
130 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
133 /* Nonzero if this chip can benefit from load scheduling. */
134 int arm_ld_sched
= 0;
136 /* Nonzero if this chip is a StrongARM. */
137 int arm_is_strong
= 0;
139 /* Nonzero if this chip is a an ARM6 or an ARM7. */
140 int arm_is_6_or_7
= 0;
142 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
143 must report the mode of the memory reference from PRINT_OPERAND to
144 PRINT_OPERAND_ADDRESS. */
145 enum machine_mode output_memory_reference_mode
;
147 /* Nonzero if the prologue must setup `fp'. */
148 int current_function_anonymous_args
;
150 /* The register number to be used for the PIC offset register. */
151 const char * arm_pic_register_string
= NULL
;
152 int arm_pic_register
= 9;
154 /* Set to one if we think that lr is only saved because of subroutine calls,
155 but all of these can be `put after' return insns */
156 int lr_save_eliminated
;
158 /* Set to 1 when a return insn is output, this means that the epilogue
160 static int return_used_this_function
;
162 /* Set to 1 after arm_reorg has started. Reset to start at the start of
163 the next function. */
164 static int after_arm_reorg
= 0;
166 /* The maximum number of insns to be used when loading a constant. */
167 static int arm_constant_limit
= 3;
169 /* For an explanation of these variables, see final_prescan_insn below. */
171 enum arm_cond_code arm_current_cc
;
173 int arm_target_label
;
175 /* The condition codes of the ARM, and the inverse function. */
176 char * arm_condition_codes
[] =
178 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
179 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
182 static enum arm_cond_code
get_arm_condition_code ();
184 #define streq(string1, string2) (strcmp (string1, string2) == 0)
186 /* Initialization code */
194 /* Not all of these give usefully different compilation alternatives,
195 but there is no simple way of generalizing them. */
196 static struct processors all_cores
[] =
200 {"arm2", FL_CO_PROC
| FL_MODE26
},
201 {"arm250", FL_CO_PROC
| FL_MODE26
},
202 {"arm3", FL_CO_PROC
| FL_MODE26
},
203 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
204 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
205 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
206 {"arm610", FL_MODE26
| FL_MODE32
},
207 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
208 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
209 /* arm7m doesn't exist on its own, but only with D, (and I), but
210 those don't alter the code, so arm7m is sometimes used. */
211 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
212 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
213 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
214 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
215 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
216 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
217 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
218 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
219 {"arm710", FL_MODE26
| FL_MODE32
},
220 {"arm710c", FL_MODE26
| FL_MODE32
},
221 {"arm7100", FL_MODE26
| FL_MODE32
},
222 {"arm7500", FL_MODE26
| FL_MODE32
},
223 /* Doesn't have an external co-proc, but does have embedded fpu. */
224 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
225 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
226 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
227 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
228 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
229 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
230 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
231 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
232 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
233 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
234 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
239 static struct processors all_architectures
[] =
241 /* ARM Architectures */
243 { "armv2", FL_CO_PROC
| FL_MODE26
},
244 { "armv2a", FL_CO_PROC
| FL_MODE26
},
245 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
246 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
247 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
248 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
249 implementations that support it, so we will leave it out for now. */
250 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
251 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
255 /* This is a magic stucture. The 'string' field is magically filled in
256 with a pointer to the value specified by the user on the command line
257 assuming that the user has specified such a value. */
259 struct arm_cpu_select arm_select
[] =
261 /* string name processors */
262 { NULL
, "-mcpu=", all_cores
},
263 { NULL
, "-march=", all_architectures
},
264 { NULL
, "-mtune=", all_cores
}
267 /* Return the number of bits set in value' */
272 unsigned int count
= 0;
276 value
&= ~(value
& - value
);
283 /* Fix up any incompatible options that the user has specified.
284 This has now turned into a maze. */
286 arm_override_options ()
290 /* Set up the flags based on the cpu/architecture selected by the user. */
291 for (i
= sizeof (arm_select
) / sizeof (arm_select
[0]); i
--;)
293 struct arm_cpu_select
* ptr
= arm_select
+ i
;
295 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
297 const struct processors
* sel
;
299 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
300 if (streq (ptr
->string
, sel
->name
))
303 tune_flags
= sel
->flags
;
306 /* If we have been given an architecture and a processor
307 make sure that they are compatible. We only generate
308 a warning though, and we prefer the CPU over the
310 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
311 warning ("switch -mcpu=%s conflicts with -march= switch",
314 insn_flags
= sel
->flags
;
320 if (sel
->name
== NULL
)
321 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
325 /* If the user did not specify a processor, choose one for them. */
328 struct processors
* sel
;
330 static struct cpu_default
337 { TARGET_CPU_arm2
, "arm2" },
338 { TARGET_CPU_arm6
, "arm6" },
339 { TARGET_CPU_arm610
, "arm610" },
340 { TARGET_CPU_arm710
, "arm710" },
341 { TARGET_CPU_arm7m
, "arm7m" },
342 { TARGET_CPU_arm7500fe
, "arm7500fe" },
343 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
344 { TARGET_CPU_arm8
, "arm8" },
345 { TARGET_CPU_arm810
, "arm810" },
346 { TARGET_CPU_arm9
, "arm9" },
347 { TARGET_CPU_strongarm
, "strongarm" },
348 { TARGET_CPU_generic
, "arm" },
351 struct cpu_default
* def
;
353 /* Find the default. */
354 for (def
= cpu_defaults
; def
->name
; def
++)
355 if (def
->cpu
== TARGET_CPU_DEFAULT
)
358 /* Make sure we found the default CPU. */
359 if (def
->name
== NULL
)
362 /* Find the default CPU's flags. */
363 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
364 if (streq (def
->name
, sel
->name
))
367 if (sel
->name
== NULL
)
370 insn_flags
= sel
->flags
;
372 /* Now check to see if the user has specified some command line
373 switch that require certain abilities from the cpu. */
376 if (TARGET_INTERWORK
)
378 sought
|= (FL_THUMB
| FL_MODE32
);
380 /* Force apcs-32 to be used for interworking. */
381 target_flags
|= ARM_FLAG_APCS_32
;
383 /* There are no ARM processor that supports both APCS-26 and
384 interworking. Therefore we force FL_MODE26 to be removed
385 from insn_flags here (if it was set), so that the search
386 below will always be able to find a compatible processor. */
387 insn_flags
&= ~ FL_MODE26
;
390 if (! TARGET_APCS_32
)
393 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
395 /* Try to locate a CPU type that supports all of the abilities
396 of the default CPU, plus the extra abilities requested by
398 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
399 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
402 if (sel
->name
== NULL
)
404 unsigned int current_bit_count
= 0;
405 struct processors
* best_fit
= NULL
;
407 /* Ideally we would like to issue an error message here
408 saying that it was not possible to find a CPU compatible
409 with the default CPU, but which also supports the command
410 line options specified by the programmer, and so they
411 ought to use the -mcpu=<name> command line option to
412 override the default CPU type.
414 Unfortunately this does not work with multilibing. We
415 need to be able to support multilibs for -mapcs-26 and for
416 -mthumb-interwork and there is no CPU that can support both
417 options. Instead if we cannot find a cpu that has both the
418 characteristics of the default cpu and the given command line
419 options we scan the array again looking for a best match. */
420 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
421 if ((sel
->flags
& sought
) == sought
)
425 count
= bit_count (sel
->flags
& insn_flags
);
427 if (count
>= current_bit_count
)
430 current_bit_count
= count
;
434 if (best_fit
== NULL
)
440 insn_flags
= sel
->flags
;
444 /* If tuning has not been specified, tune for whichever processor or
445 architecture has been selected. */
447 tune_flags
= insn_flags
;
449 /* Make sure that the processor choice does not conflict with any of the
450 other command line choices. */
451 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
453 /* If APCS-32 was not the default then it must have been set by the
454 user, so issue a warning message. If the user has specified
455 "-mapcs-32 -mcpu=arm2" then we loose here. */
456 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
457 warning ("target CPU does not support APCS-32" );
458 target_flags
&= ~ ARM_FLAG_APCS_32
;
460 else if (! TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
462 warning ("target CPU does not support APCS-26" );
463 target_flags
|= ARM_FLAG_APCS_32
;
466 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
468 warning ("target CPU does not support interworking" );
469 target_flags
&= ~ARM_FLAG_INTERWORK
;
472 /* If interworking is enabled then APCS-32 must be selected as well. */
473 if (TARGET_INTERWORK
)
475 if (! TARGET_APCS_32
)
476 warning ("interworking forces APCS-32 to be used" );
477 target_flags
|= ARM_FLAG_APCS_32
;
480 if (TARGET_APCS_STACK
&& ! TARGET_APCS
)
482 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
483 target_flags
|= ARM_FLAG_APCS_FRAME
;
486 if (TARGET_POKE_FUNCTION_NAME
)
487 target_flags
|= ARM_FLAG_APCS_FRAME
;
489 if (TARGET_APCS_REENT
&& flag_pic
)
490 fatal ("-fpic and -mapcs-reent are incompatible");
492 if (TARGET_APCS_REENT
)
493 warning ("APCS reentrant code not supported. Ignored");
495 if (write_symbols
!= NO_DEBUG
&& flag_omit_frame_pointer
)
496 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
498 /* If stack checking is disabled, we can use r10 as the PIC register,
499 which keeps r9 available. */
500 if (flag_pic
&& ! TARGET_APCS_STACK
)
501 arm_pic_register
= 10;
503 if (TARGET_APCS_FLOAT
)
504 warning ("Passing floating point arguments in fp regs not yet supported");
506 /* Initialise boolean versions of the flags, for use in the arm.md file. */
507 arm_fast_multiply
= insn_flags
& FL_FAST_MULT
;
508 arm_arch4
= insn_flags
& FL_ARCH4
;
509 arm_arch5
= insn_flags
& FL_ARCH5
;
511 arm_ld_sched
= tune_flags
& FL_LDSCHED
;
512 arm_is_strong
= tune_flags
& FL_STRONG
;
513 arm_is_6_or_7
= ((tune_flags
& (FL_MODE26
| FL_MODE32
))
514 && !(tune_flags
& FL_ARCH4
));
516 /* Default value for floating point code... if no co-processor
517 bus, then schedule for emulated floating point. Otherwise,
518 assume the user has an FPA.
519 Note: this does not prevent use of floating point instructions,
520 -msoft-float does that. */
521 arm_fpu
= (tune_flags
& FL_CO_PROC
) ? FP_HARD
: FP_SOFT3
;
525 if (streq (target_fp_name
, "2"))
526 arm_fpu_arch
= FP_SOFT2
;
527 else if (streq (target_fp_name
, "3"))
528 arm_fpu_arch
= FP_SOFT3
;
530 fatal ("Invalid floating point emulation option: -mfpe-%s",
534 arm_fpu_arch
= FP_DEFAULT
;
536 if (TARGET_FPE
&& arm_fpu
!= FP_HARD
)
539 /* For arm2/3 there is no need to do any scheduling if there is only
540 a floating point emulator, or we are doing software floating-point. */
541 if ((TARGET_SOFT_FLOAT
|| arm_fpu
!= FP_HARD
)
542 && (tune_flags
& FL_MODE32
) == 0)
543 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
545 arm_prog_mode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
547 if (structure_size_string
!= NULL
)
549 int size
= strtol (structure_size_string
, NULL
, 0);
551 if (size
== 8 || size
== 32)
552 arm_structure_size_boundary
= size
;
554 warning ("Structure size boundary can only be set to 8 or 32");
557 if (arm_pic_register_string
!= NULL
)
562 warning ("-mpic-register= is useless without -fpic");
564 pic_register
= decode_reg_name (arm_pic_register_string
);
566 /* Prevent the user from choosing an obviously stupid PIC register. */
567 if (pic_register
< 0 || call_used_regs
[pic_register
]
568 || pic_register
== HARD_FRAME_POINTER_REGNUM
569 || pic_register
== STACK_POINTER_REGNUM
570 || pic_register
>= PC_REGNUM
)
571 error ("Unable to use '%s' for PIC register", arm_pic_register_string
);
573 arm_pic_register
= pic_register
;
576 /* If optimizing for space, don't synthesize constants.
577 For processors with load scheduling, it never costs more than 2 cycles
578 to load a constant, and the load scheduler may well reduce that to 1. */
579 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
580 arm_constant_limit
= 1;
582 /* If optimizing for size, bump the number of instructions that we
583 are prepared to conditionally execute (even on a StrongARM).
584 Otherwise for the StrongARM, which has early execution of branches,
585 a sequence that is worth skipping is shorter. */
587 max_insns_skipped
= 6;
588 else if (arm_is_strong
)
589 max_insns_skipped
= 3;
591 /* Register global variables with the garbage collector. */
598 ggc_add_rtx_root (&arm_compare_op0
, 1);
599 ggc_add_rtx_root (&arm_compare_op1
, 1);
600 ggc_add_rtx_root (&arm_target_insn
, 1); /* Not sure this is really a root */
601 /* XXX: What about the minipool tables? */
605 /* Return 1 if it is possible to return using a single instruction */
608 use_return_insn (iscond
)
613 if (!reload_completed
614 || current_function_pretend_args_size
615 || current_function_anonymous_args
616 || ((get_frame_size () + current_function_outgoing_args_size
!= 0)
617 && !(TARGET_APCS
&& frame_pointer_needed
)))
620 /* Can't be done if interworking with Thumb, and any registers have been
621 stacked. Similarly, on StrongARM, conditional returns are expensive
622 if they aren't taken and registers have been stacked. */
623 if (iscond
&& arm_is_strong
&& frame_pointer_needed
)
625 if ((iscond
&& arm_is_strong
)
628 for (regno
= 0; regno
< 16; regno
++)
629 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
632 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
636 /* Can't be done if any of the FPU regs are pushed, since this also
638 for (regno
= 16; regno
< 24; regno
++)
639 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
642 /* If a function is naked, don't use the "return" insn. */
643 if (arm_naked_function_p (current_function_decl
))
649 /* Return TRUE if int I is a valid immediate ARM constant. */
655 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
657 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
658 be all zero, or all one. */
659 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
660 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
661 != ((~(unsigned HOST_WIDE_INT
) 0)
662 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
665 /* Fast return for 0 and powers of 2 */
666 if ((i
& (i
- 1)) == 0)
671 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
674 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
675 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT
) 0xffffffff);
676 } while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
681 /* Return true if I is a valid constant for the operation CODE. */
683 const_ok_for_op (i
, code
)
687 if (const_ok_for_arm (i
))
693 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
695 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
701 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
708 /* Emit a sequence of insns to handle a large constant.
709 CODE is the code of the operation required, it can be any of SET, PLUS,
710 IOR, AND, XOR, MINUS;
711 MODE is the mode in which the operation is being performed;
712 VAL is the integer to operate on;
713 SOURCE is the other operand (a register, or a null-pointer for SET);
714 SUBTARGETS means it is safe to create scratch registers if that will
715 either produce a simpler sequence, or we will want to cse the values.
716 Return value is the number of insns emitted. */
719 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
721 enum machine_mode mode
;
727 if (subtargets
|| code
== SET
728 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
729 && REGNO (target
) != REGNO (source
)))
731 /* After arm_reorg has been called, we can't fix up expensive
732 constants by pushing them into memory so we must synthesise
733 them in-line, regardless of the cost. This is only likely to
734 be more costly on chips that have load delay slots and we are
735 compiling without running the scheduler (so no splitting
736 occurred before the final instruction emission).
738 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
740 if (! after_arm_reorg
741 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
742 > arm_constant_limit
+ (code
!= SET
)))
746 /* Currently SET is the only monadic value for CODE, all
747 the rest are diadic. */
748 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
753 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
755 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
756 /* For MINUS, the value is subtracted from, since we never
757 have subtraction of a constant. */
759 emit_insn (gen_rtx_SET (VOIDmode
, target
,
760 gen_rtx (code
, mode
, temp
, source
)));
762 emit_insn (gen_rtx_SET (VOIDmode
, target
,
763 gen_rtx (code
, mode
, source
, temp
)));
769 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
772 /* As above, but extra parameter GENERATE which, if clear, suppresses
775 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
777 enum machine_mode mode
;
786 int can_negate_initial
= 0;
789 int num_bits_set
= 0;
790 int set_sign_bit_copies
= 0;
791 int clear_sign_bit_copies
= 0;
792 int clear_zero_bit_copies
= 0;
793 int set_zero_bit_copies
= 0;
795 unsigned HOST_WIDE_INT temp1
, temp2
;
796 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
798 /* find out which operations are safe for a given CODE. Also do a quick
799 check for degenerate cases; these can occur when DImode operations
811 can_negate_initial
= 1;
815 if (remainder
== 0xffffffff)
818 emit_insn (gen_rtx_SET (VOIDmode
, target
,
819 GEN_INT (ARM_SIGN_EXTEND (val
))));
824 if (reload_completed
&& rtx_equal_p (target
, source
))
827 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
836 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
839 if (remainder
== 0xffffffff)
841 if (reload_completed
&& rtx_equal_p (target
, source
))
844 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
853 if (reload_completed
&& rtx_equal_p (target
, source
))
856 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
859 if (remainder
== 0xffffffff)
862 emit_insn (gen_rtx_SET (VOIDmode
, target
,
863 gen_rtx_NOT (mode
, source
)));
867 /* We don't know how to handle this yet below. */
871 /* We treat MINUS as (val - source), since (source - val) is always
872 passed as (source + (-val)). */
876 emit_insn (gen_rtx_SET (VOIDmode
, target
,
877 gen_rtx_NEG (mode
, source
)));
880 if (const_ok_for_arm (val
))
883 emit_insn (gen_rtx_SET (VOIDmode
, target
,
884 gen_rtx_MINUS (mode
, GEN_INT (val
),
896 /* If we can do it in one insn get out quickly */
897 if (const_ok_for_arm (val
)
898 || (can_negate_initial
&& const_ok_for_arm (-val
))
899 || (can_invert
&& const_ok_for_arm (~val
)))
902 emit_insn (gen_rtx_SET (VOIDmode
, target
,
903 (source
? gen_rtx (code
, mode
, source
,
910 /* Calculate a few attributes that may be useful for specific
913 for (i
= 31; i
>= 0; i
--)
915 if ((remainder
& (1 << i
)) == 0)
916 clear_sign_bit_copies
++;
921 for (i
= 31; i
>= 0; i
--)
923 if ((remainder
& (1 << i
)) != 0)
924 set_sign_bit_copies
++;
929 for (i
= 0; i
<= 31; i
++)
931 if ((remainder
& (1 << i
)) == 0)
932 clear_zero_bit_copies
++;
937 for (i
= 0; i
<= 31; i
++)
939 if ((remainder
& (1 << i
)) != 0)
940 set_zero_bit_copies
++;
948 /* See if we can do this by sign_extending a constant that is known
949 to be negative. This is a good, way of doing it, since the shift
950 may well merge into a subsequent insn. */
951 if (set_sign_bit_copies
> 1)
954 (temp1
= ARM_SIGN_EXTEND (remainder
955 << (set_sign_bit_copies
- 1))))
959 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
960 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
962 emit_insn (gen_ashrsi3 (target
, new_src
,
963 GEN_INT (set_sign_bit_copies
- 1)));
967 /* For an inverted constant, we will need to set the low bits,
968 these will be shifted out of harm's way. */
969 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
970 if (const_ok_for_arm (~temp1
))
974 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
975 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
977 emit_insn (gen_ashrsi3 (target
, new_src
,
978 GEN_INT (set_sign_bit_copies
- 1)));
984 /* See if we can generate this by setting the bottom (or the top)
985 16 bits, and then shifting these into the other half of the
986 word. We only look for the simplest cases, to do more would cost
987 too much. Be careful, however, not to generate this when the
988 alternative would take fewer insns. */
989 if (val
& 0xffff0000)
991 temp1
= remainder
& 0xffff0000;
992 temp2
= remainder
& 0x0000ffff;
994 /* Overlaps outside this range are best done using other methods. */
995 for (i
= 9; i
< 24; i
++)
997 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
998 && ! const_ok_for_arm (temp2
))
1000 rtx new_src
= (subtargets
1001 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1003 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1004 source
, subtargets
, generate
);
1007 emit_insn (gen_rtx_SET
1010 gen_rtx_ASHIFT (mode
, source
,
1017 /* Don't duplicate cases already considered. */
1018 for (i
= 17; i
< 24; i
++)
1020 if (((temp1
| (temp1
>> i
)) == remainder
)
1021 && ! const_ok_for_arm (temp1
))
1023 rtx new_src
= (subtargets
1024 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1026 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1027 source
, subtargets
, generate
);
1031 (gen_rtx_SET (VOIDmode
, target
,
1034 gen_rtx_LSHIFTRT (mode
, source
,
1045 /* If we have IOR or XOR, and the constant can be loaded in a
1046 single instruction, and we can find a temporary to put it in,
1047 then this can be done in two instructions instead of 3-4. */
1049 /* TARGET can't be NULL if SUBTARGETS is 0 */
1050 || (reload_completed
&& ! reg_mentioned_p (target
, source
)))
1052 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val
)))
1056 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1058 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1059 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1060 gen_rtx (code
, mode
, source
, sub
)));
1069 if (set_sign_bit_copies
> 8
1070 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1074 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1075 rtx shift
= GEN_INT (set_sign_bit_copies
);
1077 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1079 gen_rtx_ASHIFT (mode
,
1082 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1084 gen_rtx_LSHIFTRT (mode
, sub
,
1090 if (set_zero_bit_copies
> 8
1091 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1095 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1096 rtx shift
= GEN_INT (set_zero_bit_copies
);
1098 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1100 gen_rtx_LSHIFTRT (mode
,
1103 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1105 gen_rtx_ASHIFT (mode
, sub
,
1111 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~ val
)))
1115 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1116 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1117 gen_rtx_NOT (mode
, source
)));
1120 sub
= gen_reg_rtx (mode
);
1121 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1122 gen_rtx_AND (mode
, source
,
1124 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1125 gen_rtx_NOT (mode
, sub
)));
1132 /* See if two shifts will do 2 or more insn's worth of work. */
1133 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1135 HOST_WIDE_INT shift_mask
= ((0xffffffff
1136 << (32 - clear_sign_bit_copies
))
1139 if ((remainder
| shift_mask
) != 0xffffffff)
1143 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1144 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1145 new_src
, source
, subtargets
, 1);
1150 rtx targ
= subtargets
? NULL_RTX
: target
;
1151 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1152 targ
, source
, subtargets
, 0);
1158 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1159 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1161 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1162 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1168 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1170 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1172 if ((remainder
| shift_mask
) != 0xffffffff)
1176 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1178 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1179 new_src
, source
, subtargets
, 1);
1184 rtx targ
= subtargets
? NULL_RTX
: target
;
1186 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1187 targ
, source
, subtargets
, 0);
1193 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1194 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1196 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1197 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1209 for (i
= 0; i
< 32; i
++)
1210 if (remainder
& (1 << i
))
1213 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1214 remainder
= (~remainder
) & 0xffffffff;
1215 else if (code
== PLUS
&& num_bits_set
> 16)
1216 remainder
= (-remainder
) & 0xffffffff;
1223 /* Now try and find a way of doing the job in either two or three
1225 We start by looking for the largest block of zeros that are aligned on
1226 a 2-bit boundary, we then fill up the temps, wrapping around to the
1227 top of the word when we drop off the bottom.
1228 In the worst case this code should produce no more than four insns. */
1231 int best_consecutive_zeros
= 0;
1233 for (i
= 0; i
< 32; i
+= 2)
1235 int consecutive_zeros
= 0;
1237 if (! (remainder
& (3 << i
)))
1239 while ((i
< 32) && ! (remainder
& (3 << i
)))
1241 consecutive_zeros
+= 2;
1244 if (consecutive_zeros
> best_consecutive_zeros
)
1246 best_consecutive_zeros
= consecutive_zeros
;
1247 best_start
= i
- consecutive_zeros
;
1253 /* Now start emitting the insns, starting with the one with the highest
1254 bit set: we do this so that the smallest number will be emitted last;
1255 this is more likely to be combinable with addressing insns. */
1263 if (remainder
& (3 << (i
- 2)))
1268 temp1
= remainder
& ((0x0ff << end
)
1269 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1270 remainder
&= ~temp1
;
1277 emit_insn (gen_rtx_SET (VOIDmode
,
1278 new_src
= (subtargets
1279 ? gen_reg_rtx (mode
)
1282 ? ~temp1
: temp1
)));
1283 else if (code
== MINUS
)
1284 emit_insn (gen_rtx_SET (VOIDmode
,
1285 new_src
= (subtargets
1286 ? gen_reg_rtx (mode
)
1288 gen_rtx (code
, mode
, GEN_INT (temp1
),
1291 emit_insn (gen_rtx_SET (VOIDmode
,
1292 new_src
= (remainder
1294 ? gen_reg_rtx (mode
)
1297 gen_rtx (code
, mode
, source
,
1298 GEN_INT (can_invert
? ~temp1
1310 else if (code
== MINUS
)
1317 } while (remainder
);
1322 /* Canonicalize a comparison so that we are more likely to recognize it.
1323 This can be done for a few constant compares, where we can make the
1324 immediate value easier to load. */
1326 arm_canonicalize_comparison (code
, op1
)
1330 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1340 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1342 && (const_ok_for_arm (i
+1) || const_ok_for_arm (- (i
+1))))
1344 *op1
= GEN_INT (i
+1);
1345 return code
== GT
? GE
: LT
;
1351 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1352 && (const_ok_for_arm (i
-1) || const_ok_for_arm (- (i
-1))))
1354 *op1
= GEN_INT (i
-1);
1355 return code
== GE
? GT
: LE
;
1361 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1362 && (const_ok_for_arm (i
+1) || const_ok_for_arm (- (i
+1))))
1364 *op1
= GEN_INT (i
+ 1);
1365 return code
== GTU
? GEU
: LTU
;
1372 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (- (i
- 1))))
1374 *op1
= GEN_INT (i
- 1);
1375 return code
== GEU
? GTU
: LEU
;
1386 /* Decide whether a type should be returned in memory (true)
1387 or in a register (false). This is called by the macro
1388 RETURN_IN_MEMORY. */
1390 arm_return_in_memory (type
)
1393 if (! AGGREGATE_TYPE_P (type
))
1395 /* All simple types are returned in registers. */
1398 else if (int_size_in_bytes (type
) > 4)
1400 /* All structures/unions bigger than one word are returned in memory. */
1403 else if (TREE_CODE (type
) == RECORD_TYPE
)
1407 /* For a struct the APCS says that we only return in a register
1408 if the type is 'integer like' and every addressable element
1409 has an offset of zero. For practical purposes this means
1410 that the structure can have at most one non bit-field element
1411 and that this element must be the first one in the structure. */
1413 /* Find the first field, ignoring non FIELD_DECL things which will
1414 have been created by C++. */
1415 for (field
= TYPE_FIELDS (type
);
1416 field
&& TREE_CODE (field
) != FIELD_DECL
;
1417 field
= TREE_CHAIN (field
))
1421 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1423 /* Check that the first field is valid for returning in a register... */
1425 /* ... Floats are not allowed */
1426 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1429 /* ... Aggregates that are not themselves valid for returning in
1430 a register are not allowed. */
1431 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1434 /* Now check the remaining fields, if any. Only bitfields are allowed,
1435 since they are not addressable. */
1436 for (field
= TREE_CHAIN (field
);
1438 field
= TREE_CHAIN (field
))
1440 if (TREE_CODE (field
) != FIELD_DECL
)
1443 if (! DECL_BIT_FIELD_TYPE (field
))
1449 else if (TREE_CODE (type
) == UNION_TYPE
)
1453 /* Unions can be returned in registers if every element is
1454 integral, or can be returned in an integer register. */
1455 for (field
= TYPE_FIELDS (type
);
1457 field
= TREE_CHAIN (field
))
1459 if (TREE_CODE (field
) != FIELD_DECL
)
1462 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1465 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1472 /* XXX Not sure what should be done for other aggregates, so put them in
1478 legitimate_pic_operand_p (x
)
1481 if (CONSTANT_P (x
) && flag_pic
1482 && (GET_CODE (x
) == SYMBOL_REF
1483 || (GET_CODE (x
) == CONST
1484 && GET_CODE (XEXP (x
, 0)) == PLUS
1485 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
1492 legitimize_pic_address (orig
, mode
, reg
)
1494 enum machine_mode mode
;
1497 if (GET_CODE (orig
) == SYMBOL_REF
)
1499 rtx pic_ref
, address
;
1505 if (reload_in_progress
|| reload_completed
)
1508 reg
= gen_reg_rtx (Pmode
);
1513 #ifdef AOF_ASSEMBLER
1514 /* The AOF assembler can generate relocations for these directly, and
1515 understands that the PIC register has to be added into the offset.
1517 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
1520 address
= gen_reg_rtx (Pmode
);
1524 emit_insn (gen_pic_load_addr (address
, orig
));
1526 pic_ref
= gen_rtx_MEM (Pmode
,
1527 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
1529 RTX_UNCHANGING_P (pic_ref
) = 1;
1530 insn
= emit_move_insn (reg
, pic_ref
);
1532 current_function_uses_pic_offset_table
= 1;
1533 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1535 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
1539 else if (GET_CODE (orig
) == CONST
)
1543 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1544 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1549 if (reload_in_progress
|| reload_completed
)
1552 reg
= gen_reg_rtx (Pmode
);
1555 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1557 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1558 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1559 base
== reg
? 0 : reg
);
1564 if (GET_CODE (offset
) == CONST_INT
)
1566 /* The base register doesn't really matter, we only want to
1567 test the index for the appropriate mode. */
1568 GO_IF_LEGITIMATE_INDEX (mode
, 0, offset
, win
);
1570 if (! reload_in_progress
&& ! reload_completed
)
1571 offset
= force_reg (Pmode
, offset
);
1576 if (GET_CODE (offset
) == CONST_INT
)
1577 return plus_constant_for_output (base
, INTVAL (offset
));
1580 if (GET_MODE_SIZE (mode
) > 4
1581 && (GET_MODE_CLASS (mode
) == MODE_INT
1582 || TARGET_SOFT_FLOAT
))
1584 emit_insn (gen_addsi3 (reg
, base
, offset
));
1588 return gen_rtx_PLUS (Pmode
, base
, offset
);
1590 else if (GET_CODE (orig
) == LABEL_REF
)
1591 current_function_uses_pic_offset_table
= 1;
1610 #ifndef AOF_ASSEMBLER
1611 rtx l1
, pic_tmp
, pic_tmp2
, seq
;
1612 rtx global_offset_table
;
1614 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
1621 l1
= gen_label_rtx ();
1623 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1624 /* On the ARM the PC register contains 'dot + 8' at the time of the
1626 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), 8);
1628 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
1629 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
1631 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
1633 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
1635 emit_insn (gen_pic_load_addr (pic_offset_table_rtx
, pic_rtx
));
1636 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
1638 seq
= gen_sequence ();
1640 emit_insn_after (seq
, get_insns ());
1642 /* Need to emit this whether or not we obey regdecls,
1643 since setjmp/longjmp can cause life info to screw up. */
1644 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
1645 #endif /* AOF_ASSEMBLER */
1648 #define REG_OR_SUBREG_REG(X) \
1649 (GET_CODE (X) == REG \
1650 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1652 #define REG_OR_SUBREG_RTX(X) \
1653 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1655 #define ARM_FRAME_RTX(X) \
1656 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1657 || (X) == arg_pointer_rtx)
1660 arm_rtx_costs (x
, code
)
1664 enum machine_mode mode
= GET_MODE (x
);
1665 enum rtx_code subcode
;
1671 /* Memory costs quite a lot for the first word, but subsequent words
1672 load at the equivalent of a single insn each. */
1673 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
1674 + (CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
1681 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
1688 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
1690 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
1691 + ((GET_CODE (XEXP (x
, 0)) == REG
1692 || (GET_CODE (XEXP (x
, 0)) == SUBREG
1693 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
1695 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
1696 || (GET_CODE (XEXP (x
, 0)) == SUBREG
1697 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
1699 + ((GET_CODE (XEXP (x
, 1)) == REG
1700 || (GET_CODE (XEXP (x
, 1)) == SUBREG
1701 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
1702 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
1707 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
1708 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
1709 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
1710 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
1713 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1714 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1715 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
1716 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
1718 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
1719 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
1720 && const_double_rtx_ok_for_fpu (XEXP (x
, 0))))
1723 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
1724 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
1725 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
1726 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
1727 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
1728 || subcode
== ROTATE
|| subcode
== ROTATERT
1730 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
1731 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
1732 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
1733 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
1734 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
1735 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
1736 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
1741 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1742 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
1743 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1744 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
1745 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
1749 case AND
: case XOR
: case IOR
:
1752 /* Normally the frame registers will be spilt into reg+const during
1753 reload, so it is a bad idea to combine them with other instructions,
1754 since then they might not be moved outside of loops. As a compromise
1755 we allow integration with ops that have a constant as their second
1757 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
1758 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
1759 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1760 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
1761 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
1765 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
1766 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1767 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
1768 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
1771 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
1772 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
1773 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1774 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
1775 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
1778 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
1779 return (1 + extra_cost
1780 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
1781 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
1782 || subcode
== ROTATE
|| subcode
== ROTATERT
1784 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1785 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
1786 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
1787 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
1788 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
1789 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
1795 /* There is no point basing this on the tuning, since it is always the
1796 fast variant if it exists at all */
1797 if (arm_fast_multiply
&& mode
== DImode
1798 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
1799 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1800 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
1803 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1807 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1809 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
1810 & (unsigned HOST_WIDE_INT
) 0xffffffff);
1811 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
1813 /* Tune as appropriate */
1814 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
1816 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
1818 i
>>= booth_unit_size
;
1825 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
1826 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
1827 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
1830 if (arm_fast_multiply
&& mode
== SImode
1831 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
1832 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1833 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
1834 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
1835 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
1836 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
1841 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1842 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
1846 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
1848 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
1851 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
1859 return 4 + (mode
== DImode
? 4 : 0);
1862 if (GET_MODE (XEXP (x
, 0)) == QImode
)
1863 return (4 + (mode
== DImode
? 4 : 0)
1864 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
1867 switch (GET_MODE (XEXP (x
, 0)))
1870 return (1 + (mode
== DImode
? 4 : 0)
1871 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
1874 return (4 + (mode
== DImode
? 4 : 0)
1875 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
1878 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
1891 arm_adjust_cost (insn
, link
, dep
, cost
)
1899 /* XXX This is not strictly true for the FPA. */
1900 if (REG_NOTE_KIND(link
) == REG_DEP_ANTI
1901 || REG_NOTE_KIND(link
) == REG_DEP_OUTPUT
)
1904 if ((i_pat
= single_set (insn
)) != NULL
1905 && GET_CODE (SET_SRC (i_pat
)) == MEM
1906 && (d_pat
= single_set (dep
)) != NULL
1907 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
1909 /* This is a load after a store, there is no conflict if the load reads
1910 from a cached area. Assume that loads from the stack, and from the
1911 constant pool are cached, and that others will miss. This is a
1914 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat
), 0))
1915 || reg_mentioned_p (stack_pointer_rtx
, XEXP (SET_SRC (i_pat
), 0))
1916 || reg_mentioned_p (frame_pointer_rtx
, XEXP (SET_SRC (i_pat
), 0))
1917 || reg_mentioned_p (hard_frame_pointer_rtx
,
1918 XEXP (SET_SRC (i_pat
), 0)))
1925 /* This code has been fixed for cross compilation. */
1927 static int fpa_consts_inited
= 0;
1929 char * strings_fpa
[8] =
1932 "4", "5", "0.5", "10"
1935 static REAL_VALUE_TYPE values_fpa
[8];
1943 for (i
= 0; i
< 8; i
++)
1945 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
1949 fpa_consts_inited
= 1;
1952 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1955 const_double_rtx_ok_for_fpu (x
)
1961 if (!fpa_consts_inited
)
1964 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1965 if (REAL_VALUE_MINUS_ZERO (r
))
1968 for (i
= 0; i
< 8; i
++)
1969 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
1975 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1978 neg_const_double_rtx_ok_for_fpu (x
)
1984 if (!fpa_consts_inited
)
1987 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1988 r
= REAL_VALUE_NEGATE (r
);
1989 if (REAL_VALUE_MINUS_ZERO (r
))
1992 for (i
= 0; i
< 8; i
++)
1993 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
1999 /* Predicates for `match_operand' and `match_operator'. */
2001 /* s_register_operand is the same as register_operand, but it doesn't accept
2004 This function exists because at the time it was put in it led to better
2005 code. SUBREG(MEM) always needs a reload in the places where
2006 s_register_operand is used, and this seemed to lead to excessive
2010 s_register_operand (op
, mode
)
2012 enum machine_mode mode
;
2014 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2017 if (GET_CODE (op
) == SUBREG
)
2018 op
= SUBREG_REG (op
);
2020 /* We don't consider registers whose class is NO_REGS
2021 to be a register operand. */
2022 return (GET_CODE (op
) == REG
2023 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2024 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
2027 /* Only accept reg, subreg(reg), const_int. */
2030 reg_or_int_operand (op
, mode
)
2032 enum machine_mode mode
;
2034 if (GET_CODE (op
) == CONST_INT
)
2037 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2040 if (GET_CODE (op
) == SUBREG
)
2041 op
= SUBREG_REG (op
);
2043 /* We don't consider registers whose class is NO_REGS
2044 to be a register operand. */
2045 return (GET_CODE (op
) == REG
2046 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2047 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
2050 /* Return 1 if OP is an item in memory, given that we are in reload. */
2053 reload_memory_operand (op
, mode
)
2055 enum machine_mode mode ATTRIBUTE_UNUSED
;
2057 int regno
= true_regnum (op
);
2059 return (! CONSTANT_P (op
)
2061 || (GET_CODE (op
) == REG
2062 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
2065 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2066 memory access (architecture V4) */
2068 bad_signed_byte_operand (op
, mode
)
2070 enum machine_mode mode
;
2072 if (! memory_operand (op
, mode
) || GET_CODE (op
) != MEM
)
2077 /* A sum of anything more complex than reg + reg or reg + const is bad */
2078 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
2079 && (! s_register_operand (XEXP (op
, 0), VOIDmode
)
2080 || (! s_register_operand (XEXP (op
, 1), VOIDmode
)
2081 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
2084 /* Big constants are also bad */
2085 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
2086 && (INTVAL (XEXP (op
, 1)) > 0xff
2087 || -INTVAL (XEXP (op
, 1)) > 0xff))
2090 /* Everything else is good, or can will automatically be made so. */
2094 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2097 arm_rhs_operand (op
, mode
)
2099 enum machine_mode mode
;
2101 return (s_register_operand (op
, mode
)
2102 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
2105 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2109 arm_rhsm_operand (op
, mode
)
2111 enum machine_mode mode
;
2113 return (s_register_operand (op
, mode
)
2114 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
2115 || memory_operand (op
, mode
));
2118 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2119 constant that is valid when negated. */
2122 arm_add_operand (op
, mode
)
2124 enum machine_mode mode
;
2126 return (s_register_operand (op
, mode
)
2127 || (GET_CODE (op
) == CONST_INT
2128 && (const_ok_for_arm (INTVAL (op
))
2129 || const_ok_for_arm (-INTVAL (op
)))));
2133 arm_not_operand (op
, mode
)
2135 enum machine_mode mode
;
2137 return (s_register_operand (op
, mode
)
2138 || (GET_CODE (op
) == CONST_INT
2139 && (const_ok_for_arm (INTVAL (op
))
2140 || const_ok_for_arm (~INTVAL (op
)))));
2143 /* Return TRUE if the operand is a memory reference which contains an
2144 offsettable address. */
2146 offsettable_memory_operand (op
, mode
)
2148 enum machine_mode mode
;
2150 if (mode
== VOIDmode
)
2151 mode
= GET_MODE (op
);
2153 return (mode
== GET_MODE (op
)
2154 && GET_CODE (op
) == MEM
2155 && offsettable_address_p (reload_completed
| reload_in_progress
,
2156 mode
, XEXP (op
, 0)));
2159 /* Return TRUE if the operand is a memory reference which is, or can be
2160 made word aligned by adjusting the offset. */
2162 alignable_memory_operand (op
, mode
)
2164 enum machine_mode mode
;
2168 if (mode
== VOIDmode
)
2169 mode
= GET_MODE (op
);
2171 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
2176 return ((GET_CODE (reg
= op
) == REG
2177 || (GET_CODE (op
) == SUBREG
2178 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
2179 || (GET_CODE (op
) == PLUS
2180 && GET_CODE (XEXP (op
, 1)) == CONST_INT
2181 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
2182 || (GET_CODE (XEXP (op
, 0)) == SUBREG
2183 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
2184 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 4);
2187 /* Similar to s_register_operand, but does not allow hard integer
2190 f_register_operand (op
, mode
)
2192 enum machine_mode mode
;
2194 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2197 if (GET_CODE (op
) == SUBREG
)
2198 op
= SUBREG_REG (op
);
2200 /* We don't consider registers whose class is NO_REGS
2201 to be a register operand. */
2202 return (GET_CODE (op
) == REG
2203 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2204 || REGNO_REG_CLASS (REGNO (op
)) == FPU_REGS
));
2207 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2210 fpu_rhs_operand (op
, mode
)
2212 enum machine_mode mode
;
2214 if (s_register_operand (op
, mode
))
2216 else if (GET_CODE (op
) == CONST_DOUBLE
)
2217 return (const_double_rtx_ok_for_fpu (op
));
2223 fpu_add_operand (op
, mode
)
2225 enum machine_mode mode
;
2227 if (s_register_operand (op
, mode
))
2229 else if (GET_CODE (op
) == CONST_DOUBLE
)
2230 return (const_double_rtx_ok_for_fpu (op
)
2231 || neg_const_double_rtx_ok_for_fpu (op
));
2236 /* Return nonzero if OP is a constant power of two. */
2239 power_of_two_operand (op
, mode
)
2241 enum machine_mode mode ATTRIBUTE_UNUSED
;
2243 if (GET_CODE (op
) == CONST_INT
)
2245 HOST_WIDE_INT value
= INTVAL(op
);
2246 return value
!= 0 && (value
& (value
- 1)) == 0;
2251 /* Return TRUE for a valid operand of a DImode operation.
2252 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2253 Note that this disallows MEM(REG+REG), but allows
2254 MEM(PRE/POST_INC/DEC(REG)). */
2257 di_operand (op
, mode
)
2259 enum machine_mode mode
;
2261 if (s_register_operand (op
, mode
))
2264 if (GET_CODE (op
) == SUBREG
)
2265 op
= SUBREG_REG (op
);
2267 switch (GET_CODE (op
))
2274 return memory_address_p (DImode
, XEXP (op
, 0));
2281 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2282 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2283 Note that this disallows MEM(REG+REG), but allows
2284 MEM(PRE/POST_INC/DEC(REG)). */
2287 soft_df_operand (op
, mode
)
2289 enum machine_mode mode
;
2291 if (s_register_operand (op
, mode
))
2294 if (GET_CODE (op
) == SUBREG
)
2295 op
= SUBREG_REG (op
);
2297 switch (GET_CODE (op
))
2303 return memory_address_p (DFmode
, XEXP (op
, 0));
2310 /* Return TRUE for valid index operands. */
2313 index_operand (op
, mode
)
2315 enum machine_mode mode
;
2317 return (s_register_operand(op
, mode
)
2318 || (immediate_operand (op
, mode
)
2319 && INTVAL (op
) < 4096 && INTVAL (op
) > -4096));
2322 /* Return TRUE for valid shifts by a constant. This also accepts any
2323 power of two on the (somewhat overly relaxed) assumption that the
2324 shift operator in this case was a mult. */
2327 const_shift_operand (op
, mode
)
2329 enum machine_mode mode
;
2331 return (power_of_two_operand (op
, mode
)
2332 || (immediate_operand (op
, mode
)
2333 && (INTVAL (op
) < 32 && INTVAL (op
) > 0)));
2336 /* Return TRUE for arithmetic operators which can be combined with a multiply
2340 shiftable_operator (x
, mode
)
2342 enum machine_mode mode
;
2344 if (GET_MODE (x
) != mode
)
2348 enum rtx_code code
= GET_CODE (x
);
2350 return (code
== PLUS
|| code
== MINUS
2351 || code
== IOR
|| code
== XOR
|| code
== AND
);
2355 /* Return TRUE for shift operators. */
2358 shift_operator (x
, mode
)
2360 enum machine_mode mode
;
2362 if (GET_MODE (x
) != mode
)
2366 enum rtx_code code
= GET_CODE (x
);
2369 return power_of_two_operand (XEXP (x
, 1), mode
);
2371 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
2372 || code
== ROTATERT
);
2376 int equality_operator (x
, mode
)
2378 enum machine_mode mode ATTRIBUTE_UNUSED
;
2380 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
2383 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2386 minmax_operator (x
, mode
)
2388 enum machine_mode mode
;
2390 enum rtx_code code
= GET_CODE (x
);
2392 if (GET_MODE (x
) != mode
)
2395 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
2398 /* return TRUE if x is EQ or NE */
2400 /* Return TRUE if this is the condition code register, if we aren't given
2401 a mode, accept any class CCmode register */
2404 cc_register (x
, mode
)
2406 enum machine_mode mode
;
2408 if (mode
== VOIDmode
)
2410 mode
= GET_MODE (x
);
2411 if (GET_MODE_CLASS (mode
) != MODE_CC
)
2415 if (mode
== GET_MODE (x
) && GET_CODE (x
) == REG
&& REGNO (x
) == 24)
2421 /* Return TRUE if this is the condition code register, if we aren't given
2422 a mode, accept any class CCmode register which indicates a dominance
2426 dominant_cc_register (x
, mode
)
2428 enum machine_mode mode
;
2430 if (mode
== VOIDmode
)
2432 mode
= GET_MODE (x
);
2433 if (GET_MODE_CLASS (mode
) != MODE_CC
)
2437 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
2438 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
2439 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
2440 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
2441 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
2444 if (mode
== GET_MODE (x
) && GET_CODE (x
) == REG
&& REGNO (x
) == 24)
2450 /* Return TRUE if X references a SYMBOL_REF. */
2452 symbol_mentioned_p (x
)
2455 register const char * fmt
;
2458 if (GET_CODE (x
) == SYMBOL_REF
)
2461 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2462 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2468 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2469 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
2472 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
2479 /* Return TRUE if X references a LABEL_REF. */
2481 label_mentioned_p (x
)
2484 register const char * fmt
;
2487 if (GET_CODE (x
) == LABEL_REF
)
2490 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2491 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2497 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2498 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
2501 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
2512 enum rtx_code code
= GET_CODE (x
);
2516 else if (code
== SMIN
)
2518 else if (code
== UMIN
)
2520 else if (code
== UMAX
)
2526 /* Return 1 if memory locations are adjacent */
2529 adjacent_mem_locations (a
, b
)
2532 int val0
= 0, val1
= 0;
2535 if ((GET_CODE (XEXP (a
, 0)) == REG
2536 || (GET_CODE (XEXP (a
, 0)) == PLUS
2537 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
2538 && (GET_CODE (XEXP (b
, 0)) == REG
2539 || (GET_CODE (XEXP (b
, 0)) == PLUS
2540 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
2542 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
2544 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
2545 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
2548 reg0
= REGNO (XEXP (a
, 0));
2549 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
2551 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
2552 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
2555 reg1
= REGNO (XEXP (b
, 0));
2556 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
2561 /* Return 1 if OP is a load multiple operation. It is known to be
2562 parallel and the first section will be tested. */
2565 load_multiple_operation (op
, mode
)
2567 enum machine_mode mode ATTRIBUTE_UNUSED
;
2569 HOST_WIDE_INT count
= XVECLEN (op
, 0);
2572 HOST_WIDE_INT i
= 1, base
= 0;
2576 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
2579 /* Check to see if this might be a write-back */
2580 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
2585 /* Now check it more carefully */
2586 if (GET_CODE (SET_DEST (elt
)) != REG
2587 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
2588 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
2589 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
2590 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 2) * 4
2591 || GET_CODE (XVECEXP (op
, 0, count
- 1)) != CLOBBER
2592 || GET_CODE (XEXP (XVECEXP (op
, 0, count
- 1), 0)) != REG
2593 || REGNO (XEXP (XVECEXP (op
, 0, count
- 1), 0))
2594 != REGNO (SET_DEST (elt
)))
2600 /* Perform a quick check so we don't blow up below. */
2602 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
2603 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
2604 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
2607 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
2608 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
2610 for (; i
< count
; i
++)
2612 elt
= XVECEXP (op
, 0, i
);
2614 if (GET_CODE (elt
) != SET
2615 || GET_CODE (SET_DEST (elt
)) != REG
2616 || GET_MODE (SET_DEST (elt
)) != SImode
2617 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
- base
2618 || GET_CODE (SET_SRC (elt
)) != MEM
2619 || GET_MODE (SET_SRC (elt
)) != SImode
2620 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
2621 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
2622 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
2623 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
2630 /* Return 1 if OP is a store multiple operation. It is known to be
2631 parallel and the first section will be tested. */
2634 store_multiple_operation (op
, mode
)
2636 enum machine_mode mode ATTRIBUTE_UNUSED
;
2638 HOST_WIDE_INT count
= XVECLEN (op
, 0);
2641 HOST_WIDE_INT i
= 1, base
= 0;
2645 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
2648 /* Check to see if this might be a write-back */
2649 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
2654 /* Now check it more carefully */
2655 if (GET_CODE (SET_DEST (elt
)) != REG
2656 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
2657 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
2658 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
2659 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 2) * 4
2660 || GET_CODE (XVECEXP (op
, 0, count
- 1)) != CLOBBER
2661 || GET_CODE (XEXP (XVECEXP (op
, 0, count
- 1), 0)) != REG
2662 || REGNO (XEXP (XVECEXP (op
, 0, count
- 1), 0))
2663 != REGNO (SET_DEST (elt
)))
2669 /* Perform a quick check so we don't blow up below. */
2671 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
2672 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
2673 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
2676 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
2677 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
2679 for (; i
< count
; i
++)
2681 elt
= XVECEXP (op
, 0, i
);
2683 if (GET_CODE (elt
) != SET
2684 || GET_CODE (SET_SRC (elt
)) != REG
2685 || GET_MODE (SET_SRC (elt
)) != SImode
2686 || REGNO (SET_SRC (elt
)) != src_regno
+ i
- base
2687 || GET_CODE (SET_DEST (elt
)) != MEM
2688 || GET_MODE (SET_DEST (elt
)) != SImode
2689 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
2690 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
2691 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
2692 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
2700 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
2705 HOST_WIDE_INT
* load_offset
;
2707 int unsorted_regs
[4];
2708 HOST_WIDE_INT unsorted_offsets
[4];
2713 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2714 extended if required. */
2715 if (nops
< 2 || nops
> 4)
2718 /* Loop over the operands and check that the memory references are
2719 suitable (ie immediate offsets from the same base register). At
2720 the same time, extract the target register, and the memory
2722 for (i
= 0; i
< nops
; i
++)
2727 /* Convert a subreg of a mem into the mem itself. */
2728 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
2729 operands
[nops
+ i
] = alter_subreg(operands
[nops
+ i
]);
2731 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
2734 /* Don't reorder volatile memory references; it doesn't seem worth
2735 looking for the case where the order is ok anyway. */
2736 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
2739 offset
= const0_rtx
;
2741 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
2742 || (GET_CODE (reg
) == SUBREG
2743 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
2744 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
2745 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
2747 || (GET_CODE (reg
) == SUBREG
2748 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
2749 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
2754 base_reg
= REGNO(reg
);
2755 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
2756 ? REGNO (operands
[i
])
2757 : REGNO (SUBREG_REG (operands
[i
])));
2762 if (base_reg
!= REGNO (reg
))
2763 /* Not addressed from the same base register. */
2766 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
2767 ? REGNO (operands
[i
])
2768 : REGNO (SUBREG_REG (operands
[i
])));
2769 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
2773 /* If it isn't an integer register, or if it overwrites the
2774 base register but isn't the last insn in the list, then
2775 we can't do this. */
2776 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
2777 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
2780 unsorted_offsets
[i
] = INTVAL (offset
);
2783 /* Not a suitable memory address. */
2787 /* All the useful information has now been extracted from the
2788 operands into unsorted_regs and unsorted_offsets; additionally,
2789 order[0] has been set to the lowest numbered register in the
2790 list. Sort the registers into order, and check that the memory
2791 offsets are ascending and adjacent. */
2793 for (i
= 1; i
< nops
; i
++)
2797 order
[i
] = order
[i
- 1];
2798 for (j
= 0; j
< nops
; j
++)
2799 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
2800 && (order
[i
] == order
[i
- 1]
2801 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
2804 /* Have we found a suitable register? if not, one must be used more
2806 if (order
[i
] == order
[i
- 1])
2809 /* Is the memory address adjacent and ascending? */
2810 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
2818 for (i
= 0; i
< nops
; i
++)
2819 regs
[i
] = unsorted_regs
[order
[i
]];
2821 *load_offset
= unsorted_offsets
[order
[0]];
2824 if (unsorted_offsets
[order
[0]] == 0)
2825 return 1; /* ldmia */
2827 if (unsorted_offsets
[order
[0]] == 4)
2828 return 2; /* ldmib */
2830 if (unsorted_offsets
[order
[nops
- 1]] == 0)
2831 return 3; /* ldmda */
2833 if (unsorted_offsets
[order
[nops
- 1]] == -4)
2834 return 4; /* ldmdb */
2836 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
2837 if the offset isn't small enough. The reason 2 ldrs are faster
2838 is because these ARMs are able to do more than one cache access
2839 in a single cycle. The ARM9 and StrongARM have Harvard caches,
2840 whilst the ARM8 has a double bandwidth cache. This means that
2841 these cores can do both an instruction fetch and a data fetch in
2842 a single cycle, so the trick of calculating the address into a
2843 scratch register (one of the result regs) and then doing a load
2844 multiple actually becomes slower (and no smaller in code size).
2845 That is the transformation
2847 ldr rd1, [rbase + offset]
2848 ldr rd2, [rbase + offset + 4]
2852 add rd1, rbase, offset
2853 ldmia rd1, {rd1, rd2}
2855 produces worse code -- '3 cycles + any stalls on rd2' instead of
2856 '2 cycles + any stalls on rd2'. On ARMs with only one cache
2857 access per cycle, the first sequence could never complete in less
2858 than 6 cycles, whereas the ldm sequence would only take 5 and
2859 would make better use of sequential accesses if not hitting the
2862 We cheat here and test 'arm_ld_sched' which we currently know to
2863 only be true for the ARM8, ARM9 and StrongARM. If this ever
2864 changes, then the test below needs to be reworked. */
2865 if (nops
== 2 && arm_ld_sched
)
2868 /* Can't do it without setting up the offset, only do this if it takes
2869 no more than one insn. */
2870 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
2871 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
2875 emit_ldm_seq (operands
, nops
)
2881 HOST_WIDE_INT offset
;
2885 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
2888 strcpy (buf
, "ldm%?ia\t");
2892 strcpy (buf
, "ldm%?ib\t");
2896 strcpy (buf
, "ldm%?da\t");
2900 strcpy (buf
, "ldm%?db\t");
2905 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
2906 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
2909 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
2910 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
2912 output_asm_insn (buf
, operands
);
2914 strcpy (buf
, "ldm%?ia\t");
2921 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
2922 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
2924 for (i
= 1; i
< nops
; i
++)
2925 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
2926 reg_names
[regs
[i
]]);
2928 strcat (buf
, "}\t%@ phole ldm");
2930 output_asm_insn (buf
, operands
);
2935 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
2940 HOST_WIDE_INT
* load_offset
;
2942 int unsorted_regs
[4];
2943 HOST_WIDE_INT unsorted_offsets
[4];
2948 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2949 extended if required. */
2950 if (nops
< 2 || nops
> 4)
2953 /* Loop over the operands and check that the memory references are
2954 suitable (ie immediate offsets from the same base register). At
2955 the same time, extract the target register, and the memory
2957 for (i
= 0; i
< nops
; i
++)
2962 /* Convert a subreg of a mem into the mem itself. */
2963 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
2964 operands
[nops
+ i
] = alter_subreg(operands
[nops
+ i
]);
2966 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
2969 /* Don't reorder volatile memory references; it doesn't seem worth
2970 looking for the case where the order is ok anyway. */
2971 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
2974 offset
= const0_rtx
;
2976 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
2977 || (GET_CODE (reg
) == SUBREG
2978 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
2979 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
2980 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
2982 || (GET_CODE (reg
) == SUBREG
2983 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
2984 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
2989 base_reg
= REGNO (reg
);
2990 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
2991 ? REGNO (operands
[i
])
2992 : REGNO (SUBREG_REG (operands
[i
])));
2997 if (base_reg
!= REGNO (reg
))
2998 /* Not addressed from the same base register. */
3001 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
3002 ? REGNO (operands
[i
])
3003 : REGNO (SUBREG_REG (operands
[i
])));
3004 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
3008 /* If it isn't an integer register, then we can't do this. */
3009 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
3012 unsorted_offsets
[i
] = INTVAL (offset
);
3015 /* Not a suitable memory address. */
3019 /* All the useful information has now been extracted from the
3020 operands into unsorted_regs and unsorted_offsets; additionally,
3021 order[0] has been set to the lowest numbered register in the
3022 list. Sort the registers into order, and check that the memory
3023 offsets are ascending and adjacent. */
3025 for (i
= 1; i
< nops
; i
++)
3029 order
[i
] = order
[i
- 1];
3030 for (j
= 0; j
< nops
; j
++)
3031 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3032 && (order
[i
] == order
[i
- 1]
3033 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3036 /* Have we found a suitable register? if not, one must be used more
3038 if (order
[i
] == order
[i
- 1])
3041 /* Is the memory address adjacent and ascending? */
3042 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3050 for (i
= 0; i
< nops
; i
++)
3051 regs
[i
] = unsorted_regs
[order
[i
]];
3053 *load_offset
= unsorted_offsets
[order
[0]];
3056 if (unsorted_offsets
[order
[0]] == 0)
3057 return 1; /* stmia */
3059 if (unsorted_offsets
[order
[0]] == 4)
3060 return 2; /* stmib */
3062 if (unsorted_offsets
[order
[nops
- 1]] == 0)
3063 return 3; /* stmda */
3065 if (unsorted_offsets
[order
[nops
- 1]] == -4)
3066 return 4; /* stmdb */
3072 emit_stm_seq (operands
, nops
)
3078 HOST_WIDE_INT offset
;
3082 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
3085 strcpy (buf
, "stm%?ia\t");
3089 strcpy (buf
, "stm%?ib\t");
3093 strcpy (buf
, "stm%?da\t");
3097 strcpy (buf
, "stm%?db\t");
3104 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
3105 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
3107 for (i
= 1; i
< nops
; i
++)
3108 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
3109 reg_names
[regs
[i
]]);
3111 strcat (buf
, "}\t%@ phole stm");
3113 output_asm_insn (buf
, operands
);
3118 multi_register_push (op
, mode
)
3120 enum machine_mode mode ATTRIBUTE_UNUSED
;
3122 if (GET_CODE (op
) != PARALLEL
3123 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3124 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
3125 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != 2))
3132 /* Routines for use with attributes */
3134 /* Return nonzero if ATTR is a valid attribute for DECL.
3135 ATTRIBUTES are any existing attributes and ARGS are the arguments
3138 Supported attributes:
3140 naked: don't output any prologue or epilogue code, the user is assumed
3141 to do the right thing. */
3144 arm_valid_machine_decl_attribute (decl
, attr
, args
)
3149 if (args
!= NULL_TREE
)
3152 if (is_attribute_p ("naked", attr
))
3153 return TREE_CODE (decl
) == FUNCTION_DECL
;
3157 /* Return non-zero if FUNC is a naked function. */
3160 arm_naked_function_p (func
)
3165 if (TREE_CODE (func
) != FUNCTION_DECL
)
3168 a
= lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func
));
3169 return a
!= NULL_TREE
;
3172 /* Routines for use in generating RTL */
3175 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
3176 in_struct_p
, scalar_p
)
3188 int sign
= up
? 1 : -1;
3191 result
= gen_rtx_PARALLEL (VOIDmode
,
3192 rtvec_alloc (count
+ (write_back
? 2 : 0)));
3195 XVECEXP (result
, 0, 0)
3196 = gen_rtx_SET (GET_MODE (from
), from
,
3197 plus_constant (from
, count
* 4 * sign
));
3202 for (j
= 0; i
< count
; i
++, j
++)
3204 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
3205 RTX_UNCHANGING_P (mem
) = unchanging_p
;
3206 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
3207 MEM_SCALAR_P (mem
) = scalar_p
;
3208 XVECEXP (result
, 0, i
)
3209 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
3213 XVECEXP (result
, 0, i
) = gen_rtx_CLOBBER (SImode
, from
);
3219 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
3220 in_struct_p
, scalar_p
)
3232 int sign
= up
? 1 : -1;
3235 result
= gen_rtx_PARALLEL (VOIDmode
,
3236 rtvec_alloc (count
+ (write_back
? 2 : 0)));
3239 XVECEXP (result
, 0, 0)
3240 = gen_rtx_SET (GET_MODE (to
), to
,
3241 plus_constant (to
, count
* 4 * sign
));
3246 for (j
= 0; i
< count
; i
++, j
++)
3248 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
3249 RTX_UNCHANGING_P (mem
) = unchanging_p
;
3250 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
3251 MEM_SCALAR_P (mem
) = scalar_p
;
3253 XVECEXP (result
, 0, i
)
3254 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
3258 XVECEXP (result
, 0, i
) = gen_rtx_CLOBBER (SImode
, to
);
3264 arm_gen_movstrqi (operands
)
3267 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
3270 rtx st_src
, st_dst
, fin_src
, fin_dst
;
3271 rtx part_bytes_reg
= NULL
;
3273 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
3274 int dst_scalar_p
, src_scalar_p
;
3276 if (GET_CODE (operands
[2]) != CONST_INT
3277 || GET_CODE (operands
[3]) != CONST_INT
3278 || INTVAL (operands
[2]) > 64
3279 || INTVAL (operands
[3]) & 3)
3282 st_dst
= XEXP (operands
[0], 0);
3283 st_src
= XEXP (operands
[1], 0);
3285 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
3286 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
3287 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
3288 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
3289 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
3290 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
3292 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
3293 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
3295 in_words_to_go
= (INTVAL (operands
[2]) + 3) / 4;
3296 out_words_to_go
= INTVAL (operands
[2]) / 4;
3297 last_bytes
= INTVAL (operands
[2]) & 3;
3299 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
3300 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
3302 for (i
= 0; in_words_to_go
>= 2; i
+=4)
3304 if (in_words_to_go
> 4)
3305 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
3310 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
3311 FALSE
, src_unchanging_p
,
3312 src_in_struct_p
, src_scalar_p
));
3314 if (out_words_to_go
)
3316 if (out_words_to_go
> 4)
3317 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
3321 else if (out_words_to_go
!= 1)
3322 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
3331 mem
= gen_rtx_MEM (SImode
, dst
);
3332 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3333 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3334 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3335 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
3336 if (last_bytes
!= 0)
3337 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
3341 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
3342 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
3345 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3346 if (out_words_to_go
)
3350 mem
= gen_rtx_MEM (SImode
, src
);
3351 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
3352 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
3353 MEM_SCALAR_P (mem
) = src_scalar_p
;
3354 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
3355 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
3357 mem
= gen_rtx_MEM (SImode
, dst
);
3358 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3359 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3360 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3361 emit_move_insn (mem
, sreg
);
3362 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
3365 if (in_words_to_go
) /* Sanity check */
3371 if (in_words_to_go
< 0)
3374 mem
= gen_rtx_MEM (SImode
, src
);
3375 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
3376 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
3377 MEM_SCALAR_P (mem
) = src_scalar_p
;
3378 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
3381 if (BYTES_BIG_ENDIAN
&& last_bytes
)
3383 rtx tmp
= gen_reg_rtx (SImode
);
3385 if (part_bytes_reg
== NULL
)
3388 /* The bytes we want are in the top end of the word */
3389 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
3390 GEN_INT (8 * (4 - last_bytes
))));
3391 part_bytes_reg
= tmp
;
3395 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
3396 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3397 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3398 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3399 emit_move_insn (mem
, gen_rtx_SUBREG (QImode
, part_bytes_reg
, 0));
3403 tmp
= gen_reg_rtx (SImode
);
3404 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
3405 part_bytes_reg
= tmp
;
3414 if (part_bytes_reg
== NULL
)
3417 mem
= gen_rtx_MEM (QImode
, dst
);
3418 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3419 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3420 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3421 emit_move_insn (mem
, gen_rtx_SUBREG (QImode
, part_bytes_reg
, 0));
3425 rtx tmp
= gen_reg_rtx (SImode
);
3427 emit_insn (gen_addsi3 (dst
, dst
, const1_rtx
));
3428 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
3429 part_bytes_reg
= tmp
;
3437 /* Generate a memory reference for a half word, such that it will be loaded
3438 into the top 16 bits of the word. We can assume that the address is
3439 known to be alignable and of the form reg, or plus (reg, const). */
3441 gen_rotated_half_load (memref
)
3444 HOST_WIDE_INT offset
= 0;
3445 rtx base
= XEXP (memref
, 0);
3447 if (GET_CODE (base
) == PLUS
)
3449 offset
= INTVAL (XEXP (base
, 1));
3450 base
= XEXP (base
, 0);
3453 /* If we aren't allowed to generate unaligned addresses, then fail. */
3454 if (TARGET_SHORT_BY_BYTES
3455 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
3458 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
3460 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
3463 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
3466 static enum machine_mode
3467 select_dominance_cc_mode (x
, y
, cond_or
)
3470 HOST_WIDE_INT cond_or
;
3472 enum rtx_code cond1
, cond2
;
3475 /* Currently we will probably get the wrong result if the individual
3476 comparisons are not simple. This also ensures that it is safe to
3477 reverse a comparison if necessary. */
3478 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
3480 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
3485 cond1
= reverse_condition (cond1
);
3487 /* If the comparisons are not equal, and one doesn't dominate the other,
3488 then we can't do this. */
3490 && ! comparison_dominates_p (cond1
, cond2
)
3491 && (swapped
= 1, ! comparison_dominates_p (cond2
, cond1
)))
3496 enum rtx_code temp
= cond1
;
3504 if (cond2
== EQ
|| ! cond_or
)
3509 case LE
: return CC_DLEmode
;
3510 case LEU
: return CC_DLEUmode
;
3511 case GE
: return CC_DGEmode
;
3512 case GEU
: return CC_DGEUmode
;
3519 if (cond2
== LT
|| ! cond_or
)
3528 if (cond2
== GT
|| ! cond_or
)
3537 if (cond2
== LTU
|| ! cond_or
)
3546 if (cond2
== GTU
|| ! cond_or
)
3554 /* The remaining cases only occur when both comparisons are the
3579 arm_select_cc_mode (op
, x
, y
)
3584 /* All floating point compares return CCFP if it is an equality
3585 comparison, and CCFPE otherwise. */
3586 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3587 return (op
== EQ
|| op
== NE
) ? CCFPmode
: CCFPEmode
;
3589 /* A compare with a shifted operand. Because of canonicalization, the
3590 comparison will have to be swapped when we emit the assembler. */
3591 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
3592 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
3593 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
3594 || GET_CODE (x
) == ROTATERT
))
3597 /* This is a special case that is used by combine to allow a
3598 comparison of a shifted byte load to be split into a zero-extend
3599 followed by a comparison of the shifted integer (only valid for
3600 equalities and unsigned inequalities). */
3601 if (GET_MODE (x
) == SImode
3602 && GET_CODE (x
) == ASHIFT
3603 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
3604 && GET_CODE (XEXP (x
, 0)) == SUBREG
3605 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
3606 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
3607 && (op
== EQ
|| op
== NE
3608 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
3609 && GET_CODE (y
) == CONST_INT
)
3612 /* An operation that sets the condition codes as a side-effect, the
3613 V flag is not set correctly, so we can only use comparisons where
3614 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3616 if (GET_MODE (x
) == SImode
3618 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
3619 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
3620 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
3621 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
3622 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
3623 || GET_CODE (x
) == LSHIFTRT
3624 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
3625 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
3628 /* A construct for a conditional compare, if the false arm contains
3629 0, then both conditions must be true, otherwise either condition
3630 must be true. Not all conditions are possible, so CCmode is
3631 returned if it can't be done. */
3632 if (GET_CODE (x
) == IF_THEN_ELSE
3633 && (XEXP (x
, 2) == const0_rtx
3634 || XEXP (x
, 2) == const1_rtx
)
3635 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3636 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
3637 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
3638 INTVAL (XEXP (x
, 2)));
3640 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
3643 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
3644 && GET_CODE (x
) == PLUS
3645 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
3651 /* X and Y are two things to compare using CODE. Emit the compare insn and
3652 return the rtx for register 0 in the proper mode. FP means this is a
3653 floating point compare: I don't think that it is needed on the arm. */
3656 gen_compare_reg (code
, x
, y
)
3660 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
3661 rtx cc_reg
= gen_rtx_REG (mode
, 24);
3663 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
3664 gen_rtx_COMPARE (mode
, x
, y
)));
3670 arm_reload_in_hi (operands
)
3673 rtx ref
= operands
[1];
3675 HOST_WIDE_INT offset
= 0;
3677 if (GET_CODE (ref
) == SUBREG
)
3679 offset
= SUBREG_WORD (ref
) * UNITS_PER_WORD
;
3680 if (BYTES_BIG_ENDIAN
)
3681 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (ref
)))
3682 - MIN (UNITS_PER_WORD
,
3683 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref
)))));
3684 ref
= SUBREG_REG (ref
);
3687 if (GET_CODE (ref
) == REG
)
3689 /* We have a pseudo which has been spilt onto the stack; there
3690 are two cases here: the first where there is a simple
3691 stack-slot replacement and a second where the stack-slot is
3692 out of range, or is used as a subreg. */
3693 if (reg_equiv_mem
[REGNO (ref
)])
3695 ref
= reg_equiv_mem
[REGNO (ref
)];
3696 base
= find_replacement (&XEXP (ref
, 0));
3699 /* The slot is out of range, or was dressed up in a SUBREG */
3700 base
= reg_equiv_address
[REGNO (ref
)];
3703 base
= find_replacement (&XEXP (ref
, 0));
3705 /* Handle the case where the address is too complex to be offset by 1. */
3706 if (GET_CODE (base
) == MINUS
3707 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
3709 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
3711 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
3714 else if (GET_CODE (base
) == PLUS
)
3716 /* The addend must be CONST_INT, or we would have dealt with it above */
3717 HOST_WIDE_INT hi
, lo
;
3719 offset
+= INTVAL (XEXP (base
, 1));
3720 base
= XEXP (base
, 0);
3722 /* Rework the address into a legal sequence of insns */
3723 /* Valid range for lo is -4095 -> 4095 */
3726 : -((-offset
) & 0xfff));
3728 /* Corner case, if lo is the max offset then we would be out of range
3729 once we have added the additional 1 below, so bump the msb into the
3730 pre-loading insn(s). */
3734 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xFFFFFFFF)
3735 ^ (HOST_WIDE_INT
) 0x80000000)
3736 - (HOST_WIDE_INT
) 0x80000000);
3738 if (hi
+ lo
!= offset
)
3743 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
3745 /* Get the base address; addsi3 knows how to handle constants
3746 that require more than one insn */
3747 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
3753 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
3754 emit_insn (gen_zero_extendqisi2 (scratch
,
3755 gen_rtx_MEM (QImode
,
3756 plus_constant (base
,
3758 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
3759 gen_rtx_MEM (QImode
,
3760 plus_constant (base
,
3762 if (! BYTES_BIG_ENDIAN
)
3763 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
3764 gen_rtx_IOR (SImode
,
3767 gen_rtx_SUBREG (SImode
, operands
[0], 0),
3771 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
3772 gen_rtx_IOR (SImode
,
3773 gen_rtx_ASHIFT (SImode
, scratch
,
3775 gen_rtx_SUBREG (SImode
, operands
[0],
3779 /* Handle storing a half-word to memory during reload by synthesising as two
3780 byte stores. Take care not to clobber the input values until after we
3781 have moved them somewhere safe. This code assumes that if the DImode
3782 scratch in operands[2] overlaps either the input value or output address
3783 in some way, then that value must die in this insn (we absolutely need
3784 two scratch registers for some corner cases). */
3786 arm_reload_out_hi (operands
)
3789 rtx ref
= operands
[0];
3790 rtx outval
= operands
[1];
3792 HOST_WIDE_INT offset
= 0;
3794 if (GET_CODE (ref
) == SUBREG
)
3796 offset
= SUBREG_WORD (ref
) * UNITS_PER_WORD
;
3797 if (BYTES_BIG_ENDIAN
)
3798 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (ref
)))
3799 - MIN (UNITS_PER_WORD
,
3800 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref
)))));
3801 ref
= SUBREG_REG (ref
);
3805 if (GET_CODE (ref
) == REG
)
3807 /* We have a pseudo which has been spilt onto the stack; there
3808 are two cases here: the first where there is a simple
3809 stack-slot replacement and a second where the stack-slot is
3810 out of range, or is used as a subreg. */
3811 if (reg_equiv_mem
[REGNO (ref
)])
3813 ref
= reg_equiv_mem
[REGNO (ref
)];
3814 base
= find_replacement (&XEXP (ref
, 0));
3817 /* The slot is out of range, or was dressed up in a SUBREG */
3818 base
= reg_equiv_address
[REGNO (ref
)];
3821 base
= find_replacement (&XEXP (ref
, 0));
3823 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
3825 /* Handle the case where the address is too complex to be offset by 1. */
3826 if (GET_CODE (base
) == MINUS
3827 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
3829 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
3831 /* Be careful not to destroy OUTVAL. */
3832 if (reg_overlap_mentioned_p (base_plus
, outval
))
3834 /* Updating base_plus might destroy outval, see if we can
3835 swap the scratch and base_plus. */
3836 if (! reg_overlap_mentioned_p (scratch
, outval
))
3839 scratch
= base_plus
;
3844 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
3846 /* Be conservative and copy OUTVAL into the scratch now,
3847 this should only be necessary if outval is a subreg
3848 of something larger than a word. */
3849 /* XXX Might this clobber base? I can't see how it can,
3850 since scratch is known to overlap with OUTVAL, and
3851 must be wider than a word. */
3852 emit_insn (gen_movhi (scratch_hi
, outval
));
3853 outval
= scratch_hi
;
3857 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
3860 else if (GET_CODE (base
) == PLUS
)
3862 /* The addend must be CONST_INT, or we would have dealt with it above */
3863 HOST_WIDE_INT hi
, lo
;
3865 offset
+= INTVAL (XEXP (base
, 1));
3866 base
= XEXP (base
, 0);
3868 /* Rework the address into a legal sequence of insns */
3869 /* Valid range for lo is -4095 -> 4095 */
3872 : -((-offset
) & 0xfff));
3874 /* Corner case, if lo is the max offset then we would be out of range
3875 once we have added the additional 1 below, so bump the msb into the
3876 pre-loading insn(s). */
3880 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xFFFFFFFF)
3881 ^ (HOST_WIDE_INT
) 0x80000000)
3882 - (HOST_WIDE_INT
) 0x80000000);
3884 if (hi
+ lo
!= offset
)
3889 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
3891 /* Be careful not to destroy OUTVAL. */
3892 if (reg_overlap_mentioned_p (base_plus
, outval
))
3894 /* Updating base_plus might destroy outval, see if we
3895 can swap the scratch and base_plus. */
3896 if (! reg_overlap_mentioned_p (scratch
, outval
))
3899 scratch
= base_plus
;
3904 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
3906 /* Be conservative and copy outval into scratch now,
3907 this should only be necessary if outval is a
3908 subreg of something larger than a word. */
3909 /* XXX Might this clobber base? I can't see how it
3910 can, since scratch is known to overlap with
3912 emit_insn (gen_movhi (scratch_hi
, outval
));
3913 outval
= scratch_hi
;
3917 /* Get the base address; addsi3 knows how to handle constants
3918 that require more than one insn */
3919 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
3925 if (BYTES_BIG_ENDIAN
)
3927 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
3928 plus_constant (base
, offset
+ 1)),
3929 gen_rtx_SUBREG (QImode
, outval
, 0)));
3930 emit_insn (gen_lshrsi3 (scratch
,
3931 gen_rtx_SUBREG (SImode
, outval
, 0),
3933 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
3934 gen_rtx_SUBREG (QImode
, scratch
, 0)));
3938 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
3939 gen_rtx_SUBREG (QImode
, outval
, 0)));
3940 emit_insn (gen_lshrsi3 (scratch
,
3941 gen_rtx_SUBREG (SImode
, outval
, 0),
3943 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
3944 plus_constant (base
, offset
+ 1)),
3945 gen_rtx_SUBREG (QImode
, scratch
, 0)));
3949 /* Routines for manipulation of the constant pool. */
3951 /* Arm instructions cannot load a large constant directly into a
3952 register; they have to come from a pc relative load. The constant
3953 must therefore be placed in the addressable range of the pc
3954 relative load. Depending on the precise pc relative load
3955 instruction the range is somewhere between 256 bytes and 4k. This
3956 means that we often have to dump a constant inside a function, and
3957 generate code to branch around it.
3959 It is important to minimize this, since the branches will slow
3960 things down and make the code larger.
3962 Normally we can hide the table after an existing unconditional
3963 branch so that there is no interruption of the flow, but in the
3964 worst case the code looks like this:
3982 We fix this by performing a scan after scheduling, which notices
3983 which instructions need to have their operands fetched from the
3984 constant table and builds the table.
3986 The algorithm starts by building a table of all the constants that
3987 need fixing up and all the natural barriers in the function (places
3988 where a constant table can be dropped without breaking the flow).
3989 For each fixup we note how far the pc-relative replacement will be
3990 able to reach and the offset of the instruction into the function.
3992 Having built the table we then group the fixes together to form
3993 tables that are as large as possible (subject to addressing
3994 constraints) and emit each table of constants after the last
3995 barrier that is within range of all the instructions in the group.
3996 If a group does not contain a barrier, then we forcibly create one
3997 by inserting a jump instruction into the flow. Once the table has
3998 been inserted, the insns are then modified to reference the
3999 relevant entry in the pool.
4001 Possible enhancements to the alogorithm (not implemented) are:
4003 1) ARM instructions (but not thumb) can use negative offsets, so we
4004 could reference back to a previous pool rather than forwards to a
4005 new one. For large functions this may reduce the number of pools
4008 2) For some processors and object formats, there may be benefit in
4009 aligning the pools to the start of cache lines; this alignment
4010 would need to be taken into account when calculating addressability
4017 rtx value
; /* Value in table */
4018 HOST_WIDE_INT next_offset
;
4019 enum machine_mode mode
; /* Mode of value */
4022 /* The maximum number of constants that can fit into one pool, since
4023 the pc relative range is 0...4092 bytes and constants are at least 4
4026 #define MAX_MINIPOOL_SIZE (4092/4)
4027 static minipool_node minipool_vector
[MAX_MINIPOOL_SIZE
];
4028 static int minipool_size
;
4029 static rtx minipool_vector_label
;
4031 /* Add a constant to the pool and return its offset within the current
4034 X is the rtx we want to replace. MODE is its mode. On return,
4035 ADDRESS_ONLY will be non-zero if we really want the address of such
4036 a constant, not the constant itself. */
4037 static HOST_WIDE_INT
4038 add_minipool_constant (x
, mode
)
4040 enum machine_mode mode
;
4043 HOST_WIDE_INT offset
;
4045 /* First, see if we've already got it. */
4046 for (i
= 0; i
< minipool_size
; i
++)
4048 if (GET_CODE (x
) == minipool_vector
[i
].value
->code
4049 && mode
== minipool_vector
[i
].mode
)
4051 if (GET_CODE (x
) == CODE_LABEL
)
4053 if (XINT (x
, 3) != XINT (minipool_vector
[i
].value
, 3))
4056 if (rtx_equal_p (x
, minipool_vector
[i
].value
))
4057 return minipool_vector
[i
].next_offset
- GET_MODE_SIZE (mode
);
4061 /* Need a new one */
4062 minipool_vector
[minipool_size
].next_offset
= GET_MODE_SIZE (mode
);
4064 if (minipool_size
== 0)
4065 minipool_vector_label
= gen_label_rtx ();
4067 minipool_vector
[minipool_size
].next_offset
4068 += (offset
= minipool_vector
[minipool_size
- 1].next_offset
);
4070 minipool_vector
[minipool_size
].value
= x
;
4071 minipool_vector
[minipool_size
].mode
= mode
;
4076 /* Output the literal table */
4078 dump_minipool (scan
)
4083 scan
= emit_label_after (gen_label_rtx (), scan
);
4084 scan
= emit_insn_after (gen_align_4 (), scan
);
4085 scan
= emit_label_after (minipool_vector_label
, scan
);
4087 for (i
= 0; i
< minipool_size
; i
++)
4089 minipool_node
*p
= minipool_vector
+ i
;
4091 switch (GET_MODE_SIZE (p
->mode
))
4094 scan
= emit_insn_after (gen_consttable_4 (p
->value
), scan
);
4098 scan
= emit_insn_after (gen_consttable_8 (p
->value
), scan
);
4107 scan
= emit_insn_after (gen_consttable_end (), scan
);
4108 scan
= emit_barrier_after (scan
);
4112 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4115 find_barrier (from
, max_count
)
4120 rtx found_barrier
= 0;
4123 while (from
&& count
< max_count
)
4127 if (GET_CODE (from
) == BARRIER
)
4128 found_barrier
= from
;
4130 /* Count the length of this insn */
4131 if (GET_CODE (from
) == JUMP_INSN
4132 && JUMP_LABEL (from
) != 0
4133 && ((tmp
= next_real_insn (JUMP_LABEL (from
)))
4134 == next_real_insn (from
))
4136 && GET_CODE (tmp
) == JUMP_INSN
4137 && (GET_CODE (PATTERN (tmp
)) == ADDR_VEC
4138 || GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
))
4140 int elt
= GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
? 1 : 0;
4141 count
+= (get_attr_length (from
)
4142 + GET_MODE_SIZE (SImode
) * XVECLEN (PATTERN (tmp
), elt
));
4143 /* Continue after the dispatch table. */
4145 from
= NEXT_INSN (tmp
);
4149 count
+= get_attr_length (from
);
4152 from
= NEXT_INSN (from
);
4155 if (! found_barrier
)
4157 /* We didn't find a barrier in time to
4158 dump our stuff, so we'll make one. */
4159 rtx label
= gen_label_rtx ();
4162 from
= PREV_INSN (last
);
4164 from
= get_last_insn ();
4166 /* Walk back to be just before any jump. */
4167 while (GET_CODE (from
) == JUMP_INSN
4168 || GET_CODE (from
) == NOTE
4169 || GET_CODE (from
) == CODE_LABEL
)
4170 from
= PREV_INSN (from
);
4172 from
= emit_jump_insn_after (gen_jump (label
), from
);
4173 JUMP_LABEL (from
) = label
;
4174 found_barrier
= emit_barrier_after (from
);
4175 emit_label_after (label
, found_barrier
);
4178 return found_barrier
;
4181 struct minipool_fixup
4183 struct minipool_fixup
*next
;
4187 enum machine_mode mode
;
4192 struct minipool_fixup
*minipool_fix_head
;
4193 struct minipool_fixup
*minipool_fix_tail
;
4196 push_minipool_barrier (insn
, address
)
4200 struct minipool_fixup
*fix
4201 = (struct minipool_fixup
*) oballoc (sizeof (struct minipool_fixup
));
4204 fix
->address
= address
;
4207 if (minipool_fix_head
!= NULL
)
4208 minipool_fix_tail
->next
= fix
;
4210 minipool_fix_head
= fix
;
4212 minipool_fix_tail
= fix
;
4216 push_minipool_fix (insn
, address
, loc
, mode
, value
)
4220 enum machine_mode mode
;
4223 struct minipool_fixup
*fix
4224 = (struct minipool_fixup
*) oballoc (sizeof (struct minipool_fixup
));
4226 #ifdef AOF_ASSEMBLER
4227 /* PIC symbol refereneces need to be converted into offsets into the
4229 if (flag_pic
&& GET_MODE
== SYMBOL_REF
)
4230 value
= aof_pic_entry (value
);
4231 #endif /* AOF_ASSEMBLER */
4234 fix
->address
= address
;
4238 fix
->range
= get_attr_pool_range (insn
);
4240 /* If an insn doesn't have a range defined for it, then it isn't
4241 expecting to be reworked by this code. Better to abort now than
4242 to generate duff assembly code. */
4243 if (fix
->range
== 0)
4246 /* Add it to the chain of fixes */
4248 if (minipool_fix_head
!= NULL
)
4249 minipool_fix_tail
->next
= fix
;
4251 minipool_fix_head
= fix
;
4253 minipool_fix_tail
= fix
;
4257 note_invalid_constants (insn
, address
)
4263 /* Extract the operands of the insn */
4266 /* Find the alternative selected */
4267 if (! constrain_operands (1))
4268 fatal_insn_not_found (insn
);
4270 /* Preprocess the constraints, to extract some useful information. */
4271 preprocess_constraints ();
4273 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4275 /* Things we need to fix can only occur in inputs */
4276 if (recog_data
.operand_type
[opno
] != OP_IN
)
4279 /* If this alternative is a memory reference, then any mention
4280 of constants in this alternative is really to fool reload
4281 into allowing us to accept one there. We need to fix them up
4282 now so that we output the right code. */
4283 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
4285 rtx op
= recog_data
.operand
[opno
];
4287 if (CONSTANT_P (op
))
4288 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
4289 recog_data
.operand_mode
[opno
], op
);
4290 #ifndef AOF_ASSEMBLER
4291 else if (GET_CODE (op
) == UNSPEC
&& XINT (op
, 1) == 3)
4292 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
4293 recog_data
.operand_mode
[opno
],
4294 XVECEXP (op
, 0, 0));
4296 else if (recog_data
.operand_mode
[opno
] == SImode
4297 && GET_CODE (op
) == MEM
4298 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
4299 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
4300 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
4301 recog_data
.operand_mode
[opno
],
4302 get_pool_constant (XEXP (op
, 0)));
4313 struct minipool_fixup
*fix
;
4315 minipool_fix_head
= minipool_fix_tail
= NULL
;
4317 /* The first insn must always be a note, or the code below won't
4318 scan it properly. */
4319 if (GET_CODE (first
) != NOTE
)
4322 /* Scan all the insns and record the operands that will need fixing. */
4323 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
4326 if (GET_CODE (insn
) == BARRIER
)
4327 push_minipool_barrier(insn
, address
);
4328 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
4329 || GET_CODE (insn
) == JUMP_INSN
)
4333 note_invalid_constants (insn
, address
);
4334 address
+= get_attr_length (insn
);
4335 /* If the insn is a vector jump, add the size of the table
4336 and skip the table. */
4337 if (GET_CODE (insn
) == JUMP_INSN
4338 && JUMP_LABEL (insn
) != NULL
4339 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
4340 == next_real_insn (insn
))
4342 && GET_CODE (table
) == JUMP_INSN
4343 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
4344 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
4346 int elt
= GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
? 1 : 0;
4348 address
+= GET_MODE_SIZE (SImode
) * XVECLEN (PATTERN (table
),
4355 /* Now scan the fixups and perform the required changes. */
4356 for (fix
= minipool_fix_head
; fix
; fix
= fix
->next
)
4358 struct minipool_fixup
*ftmp
;
4359 struct minipool_fixup
*last_barrier
= NULL
;
4362 struct minipool_fixup
*this_fix
;
4363 int new_minipool_size
= 0;
4365 /* Skip any further barriers before the next fix. */
4366 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
4373 max_range
= fix
->address
+ fix
->range
;
4375 /* Find all the other fixes that can live in the same pool. */
4376 while (ftmp
->next
&& ftmp
->next
->address
< max_range
4377 && (GET_CODE (ftmp
->next
->insn
) == BARRIER
4378 /* Ensure we can reach the constant inside the pool. */
4379 || ftmp
->next
->range
> new_minipool_size
))
4382 if (GET_CODE (ftmp
->insn
) == BARRIER
)
4383 last_barrier
= ftmp
;
4386 /* Does this fix constrain the range we can search? */
4387 if (ftmp
->address
+ ftmp
->range
- new_minipool_size
< max_range
)
4388 max_range
= ftmp
->address
+ ftmp
->range
- new_minipool_size
;
4390 new_minipool_size
+= GET_MODE_SIZE (ftmp
->mode
);
4394 /* If we found a barrier, drop back to that; any fixes that we could
4395 have reached but come after the barrier will now go in the next
4397 if (last_barrier
!= NULL
)
4399 barrier
= last_barrier
->insn
;
4400 ftmp
= last_barrier
;
4402 /* ftmp is last fix that we can fit into this pool and we
4403 failed to find a barrier that we could use. Insert a new
4404 barrier in the code and arrange to jump around it. */
4407 /* Check that there isn't another fix that is in range that
4408 we couldn't fit into this pool because the pool was
4409 already too large: we need to put the pool before such an
4411 if (ftmp
->next
&& ftmp
->next
->address
< max_range
)
4412 max_range
= ftmp
->address
;
4414 barrier
= find_barrier (ftmp
->insn
, max_range
- ftmp
->address
);
4417 /* Scan over the fixes we have identified for this pool, fixing them
4418 up and adding the constants to the pool itself. */
4419 for (this_fix
= fix
; this_fix
&& ftmp
->next
!= this_fix
;
4420 this_fix
= this_fix
->next
)
4421 if (GET_CODE (this_fix
->insn
) != BARRIER
)
4423 int offset
= add_minipool_constant (this_fix
->value
,
4426 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
4427 minipool_vector_label
),
4429 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
4432 dump_minipool (barrier
);
4436 /* From now on we must synthesize any constants that we can't handle
4437 directly. This can happen if the RTL gets split during final
4438 instruction generation. */
4439 after_arm_reorg
= 1;
4443 /* Routines to output assembly language. */
4445 /* If the rtx is the correct value then return the string of the number.
4446 In this way we can ensure that valid double constants are generated even
4447 when cross compiling. */
4449 fp_immediate_constant (x
)
4455 if (!fpa_consts_inited
)
4458 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4459 for (i
= 0; i
< 8; i
++)
4460 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
4461 return strings_fpa
[i
];
4466 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4468 fp_const_from_val (r
)
4469 REAL_VALUE_TYPE
* r
;
4473 if (! fpa_consts_inited
)
4476 for (i
= 0; i
< 8; i
++)
4477 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
4478 return strings_fpa
[i
];
4483 /* Output the operands of a LDM/STM instruction to STREAM.
4484 MASK is the ARM register set mask of which only bits 0-15 are important.
4485 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4486 must follow the register list. */
4489 print_multi_reg (stream
, instr
, reg
, mask
, hat
)
4497 int not_first
= FALSE
;
4499 fputc ('\t', stream
);
4500 asm_fprintf (stream
, instr
, reg
);
4501 fputs (", {", stream
);
4503 for (i
= 0; i
< 16; i
++)
4504 if (mask
& (1 << i
))
4507 fprintf (stream
, ", ");
4509 asm_fprintf (stream
, "%r", i
);
4513 fprintf (stream
, "}%s\n", hat
? "^" : "");
4516 /* Output a 'call' insn. */
4519 output_call (operands
)
4522 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4524 if (REGNO (operands
[0]) == LR_REGNUM
)
4526 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
4527 output_asm_insn ("mov%?\t%0, %|lr", operands
);
4530 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
4532 if (TARGET_INTERWORK
)
4533 output_asm_insn ("bx%?\t%0", operands
);
4535 output_asm_insn ("mov%?\t%|pc, %0", operands
);
4544 int something_changed
= 0;
4546 int code
= GET_CODE (x0
);
4548 register const char * fmt
;
4553 if (REGNO (x0
) == LR_REGNUM
)
4555 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
4560 /* Scan through the sub-elements and change any references there */
4561 fmt
= GET_RTX_FORMAT (code
);
4563 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4565 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
4566 else if (fmt
[i
] == 'E')
4567 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
4568 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
4570 return something_changed
;
4574 /* Output a 'call' insn that is a reference in memory. */
4577 output_call_mem (operands
)
4580 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful */
4581 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4583 if (eliminate_lr2ip (&operands
[0]))
4584 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
4586 if (TARGET_INTERWORK
)
4588 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
4589 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
4590 output_asm_insn ("bx%?\t%|ip", operands
);
4594 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
4595 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
4602 /* Output a move from arm registers to an fpu registers.
4603 OPERANDS[0] is an fpu register.
4604 OPERANDS[1] is the first registers of an arm register pair. */
4607 output_mov_long_double_fpu_from_arm (operands
)
4610 int arm_reg0
= REGNO (operands
[1]);
4613 if (arm_reg0
== IP_REGNUM
)
4616 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4617 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4618 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
4620 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
4621 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
4626 /* Output a move from an fpu register to arm registers.
4627 OPERANDS[0] is the first registers of an arm register pair.
4628 OPERANDS[1] is an fpu register. */
4631 output_mov_long_double_arm_from_fpu (operands
)
4634 int arm_reg0
= REGNO (operands
[0]);
4637 if (arm_reg0
== IP_REGNUM
)
4640 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4641 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4642 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
4644 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
4645 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
4649 /* Output a move from arm registers to arm registers of a long double
4650 OPERANDS[0] is the destination.
4651 OPERANDS[1] is the source. */
4653 output_mov_long_double_arm_from_arm (operands
)
4656 /* We have to be careful here because the two might overlap */
4657 int dest_start
= REGNO (operands
[0]);
4658 int src_start
= REGNO (operands
[1]);
4662 if (dest_start
< src_start
)
4664 for (i
= 0; i
< 3; i
++)
4666 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
4667 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
4668 output_asm_insn ("mov%?\t%0, %1", ops
);
4673 for (i
= 2; i
>= 0; i
--)
4675 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
4676 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
4677 output_asm_insn ("mov%?\t%0, %1", ops
);
4685 /* Output a move from arm registers to an fpu registers.
4686 OPERANDS[0] is an fpu register.
4687 OPERANDS[1] is the first registers of an arm register pair. */
4690 output_mov_double_fpu_from_arm (operands
)
4693 int arm_reg0
= REGNO (operands
[1]);
4696 if (arm_reg0
== IP_REGNUM
)
4699 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4700 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4701 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
4702 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
4706 /* Output a move from an fpu register to arm registers.
4707 OPERANDS[0] is the first registers of an arm register pair.
4708 OPERANDS[1] is an fpu register. */
4711 output_mov_double_arm_from_fpu (operands
)
4714 int arm_reg0
= REGNO (operands
[0]);
4717 if (arm_reg0
== IP_REGNUM
)
4720 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4721 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4722 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
4723 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
4727 /* Output a move between double words.
4728 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4729 or MEM<-REG and all MEMs must be offsettable addresses. */
4732 output_move_double (operands
)
4735 enum rtx_code code0
= GET_CODE (operands
[0]);
4736 enum rtx_code code1
= GET_CODE (operands
[1]);
4741 int reg0
= REGNO (operands
[0]);
4743 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
4747 int reg1
= REGNO (operands
[1]);
4748 if (reg1
== IP_REGNUM
)
4751 /* Ensure the second source is not overwritten */
4752 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
4753 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
4755 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
4757 else if (code1
== CONST_DOUBLE
)
4759 if (GET_MODE (operands
[1]) == DFmode
)
4762 union real_extract u
;
4764 bcopy ((char *) &CONST_DOUBLE_LOW (operands
[1]), (char *) &u
,
4766 REAL_VALUE_TO_TARGET_DOUBLE (u
.d
, l
);
4767 otherops
[1] = GEN_INT(l
[1]);
4768 operands
[1] = GEN_INT(l
[0]);
4770 else if (GET_MODE (operands
[1]) != VOIDmode
)
4772 else if (WORDS_BIG_ENDIAN
)
4775 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
4776 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
4781 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
4782 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
4785 output_mov_immediate (operands
);
4786 output_mov_immediate (otherops
);
4788 else if (code1
== CONST_INT
)
4790 #if HOST_BITS_PER_WIDE_INT > 32
4791 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4792 what the upper word is. */
4793 if (WORDS_BIG_ENDIAN
)
4795 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
4796 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
4800 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
4801 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
4804 /* Sign extend the intval into the high-order word */
4805 if (WORDS_BIG_ENDIAN
)
4807 otherops
[1] = operands
[1];
4808 operands
[1] = (INTVAL (operands
[1]) < 0
4809 ? constm1_rtx
: const0_rtx
);
4812 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
4814 output_mov_immediate (otherops
);
4815 output_mov_immediate (operands
);
4817 else if (code1
== MEM
)
4819 switch (GET_CODE (XEXP (operands
[1], 0)))
4822 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
4826 abort (); /* Should never happen now */
4830 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
4834 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
4838 abort (); /* Should never happen now */
4843 output_asm_insn ("adr%?\t%0, %1", operands
);
4844 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
4848 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
4849 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
4851 otherops
[0] = operands
[0];
4852 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
4853 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
4854 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
4856 if (GET_CODE (otherops
[2]) == CONST_INT
)
4858 switch (INTVAL (otherops
[2]))
4861 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
4864 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
4867 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
4870 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
4871 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
4873 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
4876 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
4879 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
4881 return "ldm%?ia\t%0, %M0";
4885 otherops
[1] = adj_offsettable_operand (operands
[1], 4);
4886 /* Take care of overlapping base/data reg. */
4887 if (reg_mentioned_p (operands
[0], operands
[1]))
4889 output_asm_insn ("ldr%?\t%0, %1", otherops
);
4890 output_asm_insn ("ldr%?\t%0, %1", operands
);
4894 output_asm_insn ("ldr%?\t%0, %1", operands
);
4895 output_asm_insn ("ldr%?\t%0, %1", otherops
);
4901 abort (); /* Constraints should prevent this */
4903 else if (code0
== MEM
&& code1
== REG
)
4905 if (REGNO (operands
[1]) == IP_REGNUM
)
4908 switch (GET_CODE (XEXP (operands
[0], 0)))
4911 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
4915 abort (); /* Should never happen now */
4919 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
4923 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
4927 abort (); /* Should never happen now */
4931 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
4933 switch (INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
4936 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
4940 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
4944 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
4951 otherops
[0] = adj_offsettable_operand (operands
[0], 4);
4952 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
4953 output_asm_insn ("str%?\t%1, %0", operands
);
4954 output_asm_insn ("str%?\t%1, %0", otherops
);
4958 abort (); /* Constraints should prevent this */
4964 /* Output an arbitrary MOV reg, #n.
4965 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4968 output_mov_immediate (operands
)
4971 HOST_WIDE_INT n
= INTVAL (operands
[1]);
4975 /* Try to use one MOV */
4976 if (const_ok_for_arm (n
))
4978 output_asm_insn ("mov%?\t%0, %1", operands
);
4982 /* Try to use one MVN */
4983 if (const_ok_for_arm (~n
))
4985 operands
[1] = GEN_INT (~n
);
4986 output_asm_insn ("mvn%?\t%0, %1", operands
);
4990 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4992 for (i
=0; i
< 32; i
++)
4996 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
4997 output_multi_immediate(operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
5000 output_multi_immediate(operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
5007 /* Output an ADD r, s, #n where n may be too big for one instruction. If
5008 adding zero to one register, output nothing. */
5011 output_add_immediate (operands
)
5014 HOST_WIDE_INT n
= INTVAL (operands
[2]);
5016 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
5019 output_multi_immediate (operands
,
5020 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
5023 output_multi_immediate (operands
,
5024 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
5031 /* Output a multiple immediate operation.
5032 OPERANDS is the vector of operands referred to in the output patterns.
5033 INSTR1 is the output pattern to use for the first constant.
5034 INSTR2 is the output pattern to use for subsequent constants.
5035 IMMED_OP is the index of the constant slot in OPERANDS.
5036 N is the constant value. */
5039 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
5041 char * instr1
, * instr2
;
5045 #if HOST_BITS_PER_WIDE_INT > 32
5051 operands
[immed_op
] = const0_rtx
;
5052 output_asm_insn (instr1
, operands
); /* Quick and easy output */
5057 char *instr
= instr1
;
5059 /* Note that n is never zero here (which would give no output) */
5060 for (i
= 0; i
< 32; i
+= 2)
5064 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
5065 output_asm_insn (instr
, operands
);
5075 /* Return the appropriate ARM instruction for the operation code.
5076 The returned result should not be overwritten. OP is the rtx of the
5077 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5081 arithmetic_instr (op
, shift_first_arg
)
5083 int shift_first_arg
;
5085 switch (GET_CODE (op
))
5091 return shift_first_arg
? "rsb" : "sub";
5108 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5109 for the operation code. The returned result should not be overwritten.
5110 OP is the rtx code of the shift.
5111 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5115 shift_op (op
, amountp
)
5117 HOST_WIDE_INT
*amountp
;
5120 enum rtx_code code
= GET_CODE (op
);
5122 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
5124 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5125 *amountp
= INTVAL (XEXP (op
, 1));
5148 /* We never have to worry about the amount being other than a
5149 power of 2, since this case can never be reloaded from a reg. */
5151 *amountp
= int_log2 (*amountp
);
5162 /* This is not 100% correct, but follows from the desire to merge
5163 multiplication by a power of 2 with the recognizer for a
5164 shift. >=32 is not a valid shift for "asl", so we must try and
5165 output a shift that produces the correct arithmetical result.
5166 Using lsr #32 is identical except for the fact that the carry bit
5167 is not set correctly if we set the flags; but we never use the
5168 carry bit from such an operation, so we can ignore that. */
5169 if (code
== ROTATERT
)
5170 *amountp
&= 31; /* Rotate is just modulo 32 */
5171 else if (*amountp
!= (*amountp
& 31))
5178 /* Shifts of 0 are no-ops. */
5187 /* Obtain the shift from the POWER of two. */
5189 static HOST_WIDE_INT
5191 HOST_WIDE_INT power
;
5193 HOST_WIDE_INT shift
= 0;
5195 while (((((HOST_WIDE_INT
) 1) << shift
) & power
) == 0)
5205 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5206 /bin/as is horribly restrictive. */
5207 #define MAX_ASCII_LEN 51
5210 output_ascii_pseudo_op (stream
, p
, len
)
5218 fputs ("\t.ascii\t\"", stream
);
5220 for (i
= 0; i
< len
; i
++)
5222 register int c
= p
[i
];
5224 if (len_so_far
>= MAX_ASCII_LEN
)
5226 fputs ("\"\n\t.ascii\t\"", stream
);
5233 fputs ("\\t", stream
);
5238 fputs ("\\f", stream
);
5243 fputs ("\\b", stream
);
5248 fputs ("\\r", stream
);
5252 case TARGET_NEWLINE
:
5253 fputs ("\\n", stream
);
5255 if ((c
>= ' ' && c
<= '~')
5257 /* This is a good place for a line break. */
5258 len_so_far
= MAX_ASCII_LEN
;
5265 putc ('\\', stream
);
5270 if (c
>= ' ' && c
<= '~')
5277 fprintf (stream
, "\\%03o", c
);
5284 fputs ("\"\n", stream
);
5288 /* Try to determine whether a pattern really clobbers the link register.
5289 This information is useful when peepholing, so that lr need not be pushed
5290 if we combine a call followed by a return.
5291 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5292 such a check should not be needed because these only update an existing
5293 value within a register; the register must still be set elsewhere within
5297 pattern_really_clobbers_lr (x
)
5302 switch (GET_CODE (x
))
5305 switch (GET_CODE (SET_DEST (x
)))
5308 return REGNO (SET_DEST (x
)) == LR_REGNUM
;
5311 if (GET_CODE (XEXP (SET_DEST (x
), 0)) == REG
)
5312 return REGNO (XEXP (SET_DEST (x
), 0)) == LR_REGNUM
;
5314 if (GET_CODE (XEXP (SET_DEST (x
), 0)) == MEM
)
5323 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
5324 if (pattern_really_clobbers_lr (XVECEXP (x
, 0, i
)))
5329 switch (GET_CODE (XEXP (x
, 0)))
5332 return REGNO (XEXP (x
, 0)) == LR_REGNUM
;
5335 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
)
5336 return REGNO (XEXP (XEXP (x
, 0), 0)) == LR_REGNUM
;
5352 function_really_clobbers_lr (first
)
5357 for (insn
= first
; insn
; insn
= next_nonnote_insn (insn
))
5359 switch (GET_CODE (insn
))
5364 case JUMP_INSN
: /* Jump insns only change the PC (and conds) */
5368 if (pattern_really_clobbers_lr (PATTERN (insn
)))
5373 /* Don't yet know how to handle those calls that are not to a
5375 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
5378 switch (GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)))
5381 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn
), 0, 0), 0), 0))
5387 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn
),
5393 default: /* Don't recognize it, be safe */
5397 /* A call can be made (by peepholing) not to clobber lr iff it is
5398 followed by a return. There may, however, be a use insn iff
5399 we are returning the result of the call.
5400 If we run off the end of the insn chain, then that means the
5401 call was at the end of the function. Unfortunately we don't
5402 have a return insn for the peephole to recognize, so we
5403 must reject this. (Can this be fixed by adding our own insn?) */
5404 if ((next
= next_nonnote_insn (insn
)) == NULL
)
5407 /* No need to worry about lr if the call never returns */
5408 if (GET_CODE (next
) == BARRIER
)
5411 if (GET_CODE (next
) == INSN
&& GET_CODE (PATTERN (next
)) == USE
5412 && (GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
5413 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn
), 0, 0)))
5414 == REGNO (XEXP (PATTERN (next
), 0))))
5415 if ((next
= next_nonnote_insn (next
)) == NULL
)
5418 if (GET_CODE (next
) == JUMP_INSN
5419 && GET_CODE (PATTERN (next
)) == RETURN
)
5428 /* We have reached the end of the chain so lr was _not_ clobbered */
5433 output_return_instruction (operand
, really_return
, reverse
)
5439 int reg
, live_regs
= 0;
5440 int volatile_func
= (optimize
> 0
5441 && TREE_THIS_VOLATILE (current_function_decl
));
5443 return_used_this_function
= 1;
5445 if (TARGET_ABORT_NORETURN
&& volatile_func
)
5448 /* If this function was declared non-returning, and we have found a tail
5449 call, then we have to trust that the called function won't return. */
5450 if (! really_return
)
5453 /* Otherwise, trap an attempted return by aborting. */
5455 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
5457 assemble_external_libcall (ops
[1]);
5458 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
5462 if (current_function_calls_alloca
&& ! really_return
)
5465 for (reg
= 0; reg
<= 10; reg
++)
5466 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5469 if (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5470 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5473 if (live_regs
|| (regs_ever_live
[LR_REGNUM
] && ! lr_save_eliminated
))
5476 if (frame_pointer_needed
)
5481 if (lr_save_eliminated
|| ! regs_ever_live
[LR_REGNUM
])
5484 if (frame_pointer_needed
)
5486 reverse
? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5489 reverse
? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5491 for (reg
= 0; reg
<= 10; reg
++)
5492 if (regs_ever_live
[reg
]
5493 && (! call_used_regs
[reg
]
5494 || (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5495 && reg
== PIC_OFFSET_TABLE_REGNUM
)))
5497 strcat (instr
, "%|");
5498 strcat (instr
, reg_names
[reg
]);
5500 strcat (instr
, ", ");
5503 if (frame_pointer_needed
)
5505 strcat (instr
, "%|");
5506 strcat (instr
, reg_names
[11]);
5507 strcat (instr
, ", ");
5508 strcat (instr
, "%|");
5509 strcat (instr
, reg_names
[13]);
5510 strcat (instr
, ", ");
5511 strcat (instr
, "%|");
5512 strcat (instr
, TARGET_INTERWORK
|| (! really_return
)
5513 ? reg_names
[LR_REGNUM
] : reg_names
[PC_REGNUM
] );
5517 strcat (instr
, "%|");
5518 if (TARGET_INTERWORK
&& really_return
)
5519 strcat (instr
, reg_names
[IP_REGNUM
]);
5521 strcat (instr
, really_return
? reg_names
[PC_REGNUM
] : reg_names
[LR_REGNUM
]);
5523 strcat (instr
, (TARGET_APCS_32
|| !really_return
) ? "}" : "}^");
5524 output_asm_insn (instr
, &operand
);
5526 if (TARGET_INTERWORK
&& really_return
)
5528 strcpy (instr
, "bx%?");
5529 strcat (instr
, reverse
? "%D0" : "%d0");
5530 strcat (instr
, "\t%|");
5531 strcat (instr
, frame_pointer_needed
? "lr" : "ip");
5533 output_asm_insn (instr
, & operand
);
5536 else if (really_return
)
5538 if (TARGET_INTERWORK
)
5539 sprintf (instr
, "bx%%?%%%s0\t%%|lr", reverse
? "D" : "d");
5541 sprintf (instr
, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5542 reverse
? "D" : "d", TARGET_APCS_32
? "" : "s");
5544 output_asm_insn (instr
, & operand
);
5550 /* Return nonzero if optimizing and the current function is volatile.
5551 Such functions never return, and many memory cycles can be saved
5552 by not storing register values that will never be needed again.
5553 This optimization was added to speed up context switching in a
5554 kernel application. */
5557 arm_volatile_func ()
5559 return (optimize
> 0 && TREE_THIS_VOLATILE (current_function_decl
));
5562 /* Write the function name into the code section, directly preceding
5563 the function prologue.
5565 Code will be output similar to this:
5567 .ascii "arm_poke_function_name", 0
5570 .word 0xff000000 + (t1 - t0)
5571 arm_poke_function_name
5573 stmfd sp!, {fp, ip, lr, pc}
5576 When performing a stack backtrace, code can inspect the value
5577 of 'pc' stored at 'fp' + 0. If the trace function then looks
5578 at location pc - 12 and the top 8 bits are set, then we know
5579 that there is a function name embedded immediately preceding this
5580 location and has length ((pc[-3]) & 0xff000000).
5582 We assume that pc is declared as a pointer to an unsigned long.
5584 It is of no benefit to output the function name if we are assembling
5585 a leaf function. These function types will not contain a stack
5586 backtrace structure, therefore it is not possible to determine the
5590 arm_poke_function_name (stream
, name
)
5594 unsigned long alignlength
;
5595 unsigned long length
;
5598 length
= strlen (name
) + 1;
5599 alignlength
= (length
+ 3) & ~3;
5601 ASM_OUTPUT_ASCII (stream
, name
, length
);
5602 ASM_OUTPUT_ALIGN (stream
, 2);
5603 x
= GEN_INT (0xff000000UL
+ alignlength
);
5604 ASM_OUTPUT_INT (stream
, x
);
5607 /* The amount of stack adjustment that happens here, in output_return and in
5608 output_epilogue must be exactly the same as was calculated during reload,
5609 or things will point to the wrong place. The only time we can safely
5610 ignore this constraint is when a function has no arguments on the stack,
5611 no stack frame requirement and no live registers execpt for `lr'. If we
5612 can guarantee that by making all function calls into tail calls and that
5613 lr is not clobbered in any other way, then there is no need to push lr
5617 output_func_prologue (f
, frame_size
)
5621 int reg
, live_regs_mask
= 0;
5622 int volatile_func
= (optimize
> 0
5623 && TREE_THIS_VOLATILE (current_function_decl
));
5625 /* Nonzero if we must stuff some register arguments onto the stack as if
5626 they were passed there. */
5627 int store_arg_regs
= 0;
5629 if (arm_ccfsm_state
|| arm_target_insn
)
5630 abort (); /* Sanity check */
5632 if (arm_naked_function_p (current_function_decl
))
5635 return_used_this_function
= 0;
5636 lr_save_eliminated
= 0;
5638 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
5639 current_function_args_size
,
5640 current_function_pretend_args_size
, frame_size
);
5641 asm_fprintf (f
, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
5642 frame_pointer_needed
,
5643 current_function_anonymous_args
);
5646 asm_fprintf (f
, "\t%@ Volatile function.\n");
5648 if (current_function_anonymous_args
&& current_function_pretend_args_size
)
5651 for (reg
= 0; reg
<= 10; reg
++)
5652 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5653 live_regs_mask
|= (1 << reg
);
5655 if (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5656 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5657 live_regs_mask
|= (1 << PIC_OFFSET_TABLE_REGNUM
);
5659 if (frame_pointer_needed
)
5660 live_regs_mask
|= 0xD800;
5661 else if (regs_ever_live
[LR_REGNUM
])
5663 if (! current_function_args_size
5664 && ! function_really_clobbers_lr (get_insns ()))
5665 lr_save_eliminated
= 1;
5667 live_regs_mask
|= 1 << LR_REGNUM
;
5672 /* if a di mode load/store multiple is used, and the base register
5673 is r3, then r4 can become an ever live register without lr
5674 doing so, in this case we need to push lr as well, or we
5675 will fail to get a proper return. */
5677 live_regs_mask
|= 1 << LR_REGNUM
;
5678 lr_save_eliminated
= 0;
5682 if (lr_save_eliminated
)
5683 asm_fprintf (f
,"\t%@ I don't think this function clobbers lr\n");
5685 #ifdef AOF_ASSEMBLER
5687 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
5692 arm_output_epilogue ()
5695 int live_regs_mask
= 0;
5696 /* If we need this, then it will always be at least this much */
5697 int floats_offset
= 12;
5699 int frame_size
= get_frame_size ();
5700 FILE *f
= asm_out_file
;
5701 int volatile_func
= (optimize
> 0
5702 && TREE_THIS_VOLATILE (current_function_decl
));
5704 if (use_return_insn (FALSE
) && return_used_this_function
)
5707 /* Naked functions don't have epilogues. */
5708 if (arm_naked_function_p (current_function_decl
))
5711 /* A volatile function should never return. Call abort. */
5712 if (TARGET_ABORT_NORETURN
&& volatile_func
)
5715 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
5716 assemble_external_libcall (op
);
5717 output_asm_insn ("bl\t%a0", &op
);
5721 for (reg
= 0; reg
<= 10; reg
++)
5722 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5724 live_regs_mask
|= (1 << reg
);
5728 /* If we aren't loading the PIC register, don't stack it even though it may
5730 if (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5731 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5733 live_regs_mask
|= (1 << PIC_OFFSET_TABLE_REGNUM
);
5737 if (frame_pointer_needed
)
5739 if (arm_fpu_arch
== FP_SOFT2
)
5741 for (reg
= 23; reg
> 15; reg
--)
5742 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5744 floats_offset
+= 12;
5745 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
5746 reg
, FP_REGNUM
, floats_offset
);
5753 for (reg
= 23; reg
> 15; reg
--)
5755 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5757 floats_offset
+= 12;
5759 /* We can't unstack more than four registers at once */
5760 if (start_reg
- reg
== 3)
5762 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
5763 reg
, FP_REGNUM
, floats_offset
);
5764 start_reg
= reg
- 1;
5769 if (reg
!= start_reg
)
5770 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
5771 reg
+ 1, start_reg
- reg
,
5772 FP_REGNUM
, floats_offset
);
5773 start_reg
= reg
- 1;
5777 /* Just in case the last register checked also needs unstacking. */
5778 if (reg
!= start_reg
)
5779 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
5780 reg
+ 1, start_reg
- reg
,
5781 FP_REGNUM
, floats_offset
);
5784 if (TARGET_INTERWORK
)
5786 live_regs_mask
|= 0x6800;
5787 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, live_regs_mask
, FALSE
);
5788 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
5792 live_regs_mask
|= 0xA800;
5793 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, live_regs_mask
,
5794 TARGET_APCS_32
? FALSE
: TRUE
);
5799 /* Restore stack pointer if necessary. */
5800 if (frame_size
+ current_function_outgoing_args_size
!= 0)
5802 operands
[0] = operands
[1] = stack_pointer_rtx
;
5803 operands
[2] = GEN_INT (frame_size
5804 + current_function_outgoing_args_size
);
5805 output_add_immediate (operands
);
5808 if (arm_fpu_arch
== FP_SOFT2
)
5810 for (reg
= 16; reg
< 24; reg
++)
5811 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5812 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
5819 for (reg
= 16; reg
< 24; reg
++)
5821 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5823 if (reg
- start_reg
== 3)
5825 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
5826 start_reg
, SP_REGNUM
);
5827 start_reg
= reg
+ 1;
5832 if (reg
!= start_reg
)
5833 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
5834 start_reg
, reg
- start_reg
,
5837 start_reg
= reg
+ 1;
5841 /* Just in case the last register checked also needs unstacking. */
5842 if (reg
!= start_reg
)
5843 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
5844 start_reg
, reg
- start_reg
, SP_REGNUM
);
5847 if (current_function_pretend_args_size
== 0 && regs_ever_live
[LR_REGNUM
])
5849 if (TARGET_INTERWORK
)
5851 if (! lr_save_eliminated
)
5852 live_regs_mask
|= 1 << LR_REGNUM
;
5854 if (live_regs_mask
!= 0)
5855 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, live_regs_mask
, FALSE
);
5857 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
5859 else if (lr_save_eliminated
)
5860 asm_fprintf (f
, "\tmov%c\t%r, %r\n",
5861 TARGET_APCS_32
? ' ' : 's',
5862 PC_REGNUM
, LR_REGNUM
);
5864 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, live_regs_mask
| 0x8000,
5865 TARGET_APCS_32
? FALSE
: TRUE
);
5869 if (live_regs_mask
|| regs_ever_live
[LR_REGNUM
])
5871 /* Restore the integer regs, and the return address into lr */
5872 if (! lr_save_eliminated
)
5873 live_regs_mask
|= 1 << LR_REGNUM
;
5875 if (live_regs_mask
!= 0)
5876 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, live_regs_mask
, FALSE
);
5879 if (current_function_pretend_args_size
)
5881 /* Unwind the pre-pushed regs */
5882 operands
[0] = operands
[1] = stack_pointer_rtx
;
5883 operands
[2] = GEN_INT (current_function_pretend_args_size
);
5884 output_add_immediate (operands
);
5886 /* And finally, go home */
5887 if (TARGET_INTERWORK
)
5888 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
5889 else if (TARGET_APCS_32
)
5890 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
5892 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
5900 output_func_epilogue (f
, frame_size
)
5901 FILE *f ATTRIBUTE_UNUSED
;
5904 if (use_return_insn (FALSE
) && return_used_this_function
5905 && (frame_size
+ current_function_outgoing_args_size
) != 0
5906 && ! (frame_pointer_needed
&& TARGET_APCS
))
5909 /* Reset the ARM-specific per-function variables. */
5910 current_function_anonymous_args
= 0;
5911 after_arm_reorg
= 0;
5915 emit_multi_reg_push (mask
)
5922 for (i
= 0; i
< 16; i
++)
5923 if (mask
& (1 << i
))
5926 if (num_regs
== 0 || num_regs
> 16)
5929 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
5931 for (i
= 0; i
< 16; i
++)
5933 if (mask
& (1 << i
))
5936 = gen_rtx_SET (VOIDmode
,
5937 gen_rtx_MEM (BLKmode
,
5938 gen_rtx_PRE_DEC (BLKmode
,
5939 stack_pointer_rtx
)),
5940 gen_rtx_UNSPEC (BLKmode
,
5942 gen_rtx_REG (SImode
, i
)),
5948 for (j
= 1, i
++; j
< num_regs
; i
++)
5950 if (mask
& (1 << i
))
5953 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, i
));
5962 emit_sfm (base_reg
, count
)
5969 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
5972 = gen_rtx_SET (VOIDmode
,
5973 gen_rtx_MEM (BLKmode
,
5974 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
5975 gen_rtx_UNSPEC (BLKmode
,
5976 gen_rtvec (1, gen_rtx_REG (XFmode
,
5979 for (i
= 1; i
< count
; i
++)
5980 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
,
5981 gen_rtx_REG (XFmode
, base_reg
++));
5987 arm_expand_prologue ()
5990 rtx amount
= GEN_INT (-(get_frame_size ()
5991 + current_function_outgoing_args_size
));
5992 int live_regs_mask
= 0;
5993 int store_arg_regs
= 0;
5994 /* If this function doesn't return, then there is no need to push
5995 the call-saved regs. */
5996 int volatile_func
= (optimize
> 0
5997 && TREE_THIS_VOLATILE (current_function_decl
));
5999 /* Naked functions don't have prologues. */
6000 if (arm_naked_function_p (current_function_decl
))
6003 if (current_function_anonymous_args
&& current_function_pretend_args_size
)
6006 if (! volatile_func
)
6008 for (reg
= 0; reg
<= 10; reg
++)
6009 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6010 live_regs_mask
|= 1 << reg
;
6012 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
6013 live_regs_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
6015 if (regs_ever_live
[LR_REGNUM
])
6016 live_regs_mask
|= 1 << LR_REGNUM
;
6019 if (frame_pointer_needed
)
6021 live_regs_mask
|= 0xD800;
6022 emit_insn (gen_movsi (gen_rtx_REG (SImode
, IP_REGNUM
),
6023 stack_pointer_rtx
));
6026 if (current_function_pretend_args_size
)
6029 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size
/ 4))
6032 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6033 GEN_INT (-current_function_pretend_args_size
)));
6038 /* If we have to push any regs, then we must push lr as well, or
6039 we won't get a proper return. */
6040 live_regs_mask
|= 1 << LR_REGNUM
;
6041 emit_multi_reg_push (live_regs_mask
);
6044 /* For now the integer regs are still pushed in output_func_epilogue (). */
6046 if (! volatile_func
)
6048 if (arm_fpu_arch
== FP_SOFT2
)
6050 for (reg
= 23; reg
> 15; reg
--)
6051 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6052 emit_insn (gen_rtx_SET
6054 gen_rtx_MEM (XFmode
,
6055 gen_rtx_PRE_DEC (XFmode
,
6056 stack_pointer_rtx
)),
6057 gen_rtx_REG (XFmode
, reg
)));
6063 for (reg
= 23; reg
> 15; reg
--)
6065 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6067 if (start_reg
- reg
== 3)
6070 start_reg
= reg
- 1;
6075 if (start_reg
!= reg
)
6076 emit_sfm (reg
+ 1, start_reg
- reg
);
6077 start_reg
= reg
- 1;
6081 if (start_reg
!= reg
)
6082 emit_sfm (reg
+ 1, start_reg
- reg
);
6086 if (frame_pointer_needed
)
6087 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, gen_rtx_REG (SImode
, IP_REGNUM
),
6089 (-(4 + current_function_pretend_args_size
)))));
6091 if (amount
!= const0_rtx
)
6093 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, amount
));
6094 emit_insn (gen_rtx_CLOBBER (VOIDmode
,
6095 gen_rtx_MEM (BLKmode
, stack_pointer_rtx
)));
6098 /* If we are profiling, make sure no instructions are scheduled before
6099 the call to mcount. Similarly if the user has requested no
6100 scheduling in the prolog. */
6101 if (profile_flag
|| profile_block_flag
|| TARGET_NO_SCHED_PRO
)
6102 emit_insn (gen_blockage ());
6106 /* If CODE is 'd', then the X is a condition operand and the instruction
6107 should only be executed if the condition is true.
6108 if CODE is 'D', then the X is a condition operand and the instruction
6109 should only be executed if the condition is false: however, if the mode
6110 of the comparison is CCFPEmode, then always execute the instruction -- we
6111 do this because in these circumstances !GE does not necessarily imply LT;
6112 in these cases the instruction pattern will take care to make sure that
6113 an instruction containing %d will follow, thereby undoing the effects of
6114 doing this instruction unconditionally.
6115 If CODE is 'N' then X is a floating point operand that must be negated
6117 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6118 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6121 arm_print_operand (stream
, x
, code
)
6129 fputs (ASM_COMMENT_START
, stream
);
6133 fputs (REGISTER_PREFIX
, stream
);
6137 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
6138 fputs (arm_condition_codes
[arm_current_cc
], stream
);
6144 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6145 r
= REAL_VALUE_NEGATE (r
);
6146 fprintf (stream
, "%s", fp_const_from_val (&r
));
6151 if (GET_CODE (x
) == CONST_INT
)
6154 val
= ARM_SIGN_EXTEND (~ INTVAL (x
));
6155 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
6160 output_addr_const (stream
, x
);
6165 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
6169 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
6175 char * shift
= shift_op (x
, & val
);
6179 fprintf (stream
, ", %s ", shift_op (x
, & val
));
6181 arm_print_operand (stream
, XEXP (x
, 1), 0);
6184 fputc ('#', stream
);
6185 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
6194 fputs (REGISTER_PREFIX
, stream
);
6195 fputs (reg_names
[REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0)], stream
);
6201 fputs (REGISTER_PREFIX
, stream
);
6202 fputs (reg_names
[REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1)], stream
);
6206 fputs (REGISTER_PREFIX
, stream
);
6207 if (GET_CODE (XEXP (x
, 0)) == REG
)
6208 fputs (reg_names
[REGNO (XEXP (x
, 0))], stream
);
6210 fputs (reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))], stream
);
6214 asm_fprintf (stream
, "{%r-%r}",
6215 REGNO (x
), REGNO (x
) + NUM_REGS (GET_MODE (x
)) - 1);
6220 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
6226 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
6227 (get_arm_condition_code (x
))],
6235 if (GET_CODE (x
) == REG
)
6237 fputs (REGISTER_PREFIX
, stream
);
6238 fputs (reg_names
[REGNO (x
)], stream
);
6240 else if (GET_CODE (x
) == MEM
)
6242 output_memory_reference_mode
= GET_MODE (x
);
6243 output_address (XEXP (x
, 0));
6245 else if (GET_CODE (x
) == CONST_DOUBLE
)
6246 fprintf (stream
, "#%s", fp_immediate_constant (x
));
6247 else if (GET_CODE (x
) == NEG
)
6248 abort (); /* This should never happen now. */
6251 fputc ('#', stream
);
6252 output_addr_const (stream
, x
);
6257 /* A finite state machine takes care of noticing whether or not instructions
6258 can be conditionally executed, and thus decrease execution time and code
6259 size by deleting branch instructions. The fsm is controlled by
6260 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6262 /* The state of the fsm controlling condition codes are:
6263 0: normal, do nothing special
6264 1: make ASM_OUTPUT_OPCODE not output this instruction
6265 2: make ASM_OUTPUT_OPCODE not output this instruction
6266 3: make instructions conditional
6267 4: make instructions conditional
6269 State transitions (state->state by whom under condition):
6270 0 -> 1 final_prescan_insn if the `target' is a label
6271 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6272 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6273 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6274 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6275 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6276 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6277 (the target insn is arm_target_insn).
6279 If the jump clobbers the conditions then we use states 2 and 4.
6281 A similar thing can be done with conditional return insns.
6283 XXX In case the `target' is an unconditional branch, this conditionalising
6284 of the instructions always reduces code size, but not always execution
6285 time. But then, I want to reduce the code size to somewhere near what
6286 /bin/cc produces. */
6288 /* Returns the index of the ARM condition code string in
6289 `arm_condition_codes'. COMPARISON should be an rtx like
6290 `(eq (...) (...))'. */
6292 static enum arm_cond_code
6293 get_arm_condition_code (comparison
)
6296 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
6298 register enum rtx_code comp_code
= GET_CODE (comparison
);
6300 if (GET_MODE_CLASS (mode
) != MODE_CC
)
6301 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
6302 XEXP (comparison
, 1));
6306 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
6307 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
6308 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
6309 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
6310 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
6311 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
6312 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
6313 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
6314 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
6315 case CC_DLTUmode
: code
= ARM_CC
;
6318 if (comp_code
!= EQ
&& comp_code
!= NE
)
6321 if (comp_code
== EQ
)
6322 return ARM_INVERSE_CONDITION_CODE (code
);
6328 case NE
: return ARM_NE
;
6329 case EQ
: return ARM_EQ
;
6330 case GE
: return ARM_PL
;
6331 case LT
: return ARM_MI
;
6339 case NE
: return ARM_NE
;
6340 case EQ
: return ARM_EQ
;
6347 case GE
: return ARM_GE
;
6348 case GT
: return ARM_GT
;
6349 case LE
: return ARM_LS
;
6350 case LT
: return ARM_MI
;
6357 case NE
: return ARM_NE
;
6358 case EQ
: return ARM_EQ
;
6359 case GE
: return ARM_LE
;
6360 case GT
: return ARM_LT
;
6361 case LE
: return ARM_GE
;
6362 case LT
: return ARM_GT
;
6363 case GEU
: return ARM_LS
;
6364 case GTU
: return ARM_CC
;
6365 case LEU
: return ARM_CS
;
6366 case LTU
: return ARM_HI
;
6373 case LTU
: return ARM_CS
;
6374 case GEU
: return ARM_CC
;
6381 case NE
: return ARM_NE
;
6382 case EQ
: return ARM_EQ
;
6383 case GE
: return ARM_GE
;
6384 case GT
: return ARM_GT
;
6385 case LE
: return ARM_LE
;
6386 case LT
: return ARM_LT
;
6387 case GEU
: return ARM_CS
;
6388 case GTU
: return ARM_HI
;
6389 case LEU
: return ARM_LS
;
6390 case LTU
: return ARM_CC
;
6402 arm_final_prescan_insn (insn
)
6405 /* BODY will hold the body of INSN. */
6406 register rtx body
= PATTERN (insn
);
6408 /* This will be 1 if trying to repeat the trick, and things need to be
6409 reversed if it appears to fail. */
6412 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6413 taken are clobbered, even if the rtl suggests otherwise. It also
6414 means that we have to grub around within the jump expression to find
6415 out what the conditions are when the jump isn't taken. */
6416 int jump_clobbers
= 0;
6418 /* If we start with a return insn, we only succeed if we find another one. */
6419 int seeking_return
= 0;
6421 /* START_INSN will hold the insn from where we start looking. This is the
6422 first insn after the following code_label if REVERSE is true. */
6423 rtx start_insn
= insn
;
6425 /* If in state 4, check if the target branch is reached, in order to
6426 change back to state 0. */
6427 if (arm_ccfsm_state
== 4)
6429 if (insn
== arm_target_insn
)
6431 arm_target_insn
= NULL
;
6432 arm_ccfsm_state
= 0;
6437 /* If in state 3, it is possible to repeat the trick, if this insn is an
6438 unconditional branch to a label, and immediately following this branch
6439 is the previous target label which is only used once, and the label this
6440 branch jumps to is not too far off. */
6441 if (arm_ccfsm_state
== 3)
6443 if (simplejump_p (insn
))
6445 start_insn
= next_nonnote_insn (start_insn
);
6446 if (GET_CODE (start_insn
) == BARRIER
)
6448 /* XXX Isn't this always a barrier? */
6449 start_insn
= next_nonnote_insn (start_insn
);
6451 if (GET_CODE (start_insn
) == CODE_LABEL
6452 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
6453 && LABEL_NUSES (start_insn
) == 1)
6458 else if (GET_CODE (body
) == RETURN
)
6460 start_insn
= next_nonnote_insn (start_insn
);
6461 if (GET_CODE (start_insn
) == BARRIER
)
6462 start_insn
= next_nonnote_insn (start_insn
);
6463 if (GET_CODE (start_insn
) == CODE_LABEL
6464 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
6465 && LABEL_NUSES (start_insn
) == 1)
6477 if (arm_ccfsm_state
!= 0 && !reverse
)
6479 if (GET_CODE (insn
) != JUMP_INSN
)
6482 /* This jump might be paralleled with a clobber of the condition codes
6483 the jump should always come first */
6484 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
6485 body
= XVECEXP (body
, 0, 0);
6488 /* If this is a conditional return then we don't want to know */
6489 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
6490 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
6491 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
6492 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
6497 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
6498 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
6501 int fail
= FALSE
, succeed
= FALSE
;
6502 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6503 int then_not_else
= TRUE
;
6504 rtx this_insn
= start_insn
, label
= 0;
6506 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
6508 /* The code below is wrong for these, and I haven't time to
6509 fix it now. So we just do the safe thing and return. This
6510 whole function needs re-writing anyway. */
6515 /* Register the insn jumped to. */
6518 if (!seeking_return
)
6519 label
= XEXP (SET_SRC (body
), 0);
6521 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
6522 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
6523 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
6525 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
6526 then_not_else
= FALSE
;
6528 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
6530 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
6533 then_not_else
= FALSE
;
6538 /* See how many insns this branch skips, and what kind of insns. If all
6539 insns are okay, and the label or unconditional branch to the same
6540 label is not too far away, succeed. */
6541 for (insns_skipped
= 0;
6542 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
6546 this_insn
= next_nonnote_insn (this_insn
);
6550 switch (GET_CODE (this_insn
))
6553 /* Succeed if it is the target label, otherwise fail since
6554 control falls in from somewhere else. */
6555 if (this_insn
== label
)
6559 arm_ccfsm_state
= 2;
6560 this_insn
= next_nonnote_insn (this_insn
);
6563 arm_ccfsm_state
= 1;
6571 /* Succeed if the following insn is the target label.
6573 If return insns are used then the last insn in a function
6574 will be a barrier. */
6575 this_insn
= next_nonnote_insn (this_insn
);
6576 if (this_insn
&& this_insn
== label
)
6580 arm_ccfsm_state
= 2;
6581 this_insn
= next_nonnote_insn (this_insn
);
6584 arm_ccfsm_state
= 1;
6592 /* If using 32-bit addresses the cc is not preserved over
6596 /* Succeed if the following insn is the target label,
6597 or if the following two insns are a barrier and
6598 the target label. */
6599 this_insn
= next_nonnote_insn (this_insn
);
6600 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
6601 this_insn
= next_nonnote_insn (this_insn
);
6603 if (this_insn
&& this_insn
== label
6604 && insns_skipped
< max_insns_skipped
)
6608 arm_ccfsm_state
= 2;
6609 this_insn
= next_nonnote_insn (this_insn
);
6612 arm_ccfsm_state
= 1;
6621 /* If this is an unconditional branch to the same label, succeed.
6622 If it is to another label, do nothing. If it is conditional,
6624 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6626 scanbody
= PATTERN (this_insn
);
6627 if (GET_CODE (scanbody
) == SET
6628 && GET_CODE (SET_DEST (scanbody
)) == PC
)
6630 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
6631 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
6633 arm_ccfsm_state
= 2;
6636 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
6639 /* Fail if a conditional return is undesirable (eg on a
6640 StrongARM), but still allow this if optimizing for size. */
6641 else if (GET_CODE (scanbody
) == RETURN
6642 && ! use_return_insn (TRUE
)
6645 else if (GET_CODE (scanbody
) == RETURN
6648 arm_ccfsm_state
= 2;
6651 else if (GET_CODE (scanbody
) == PARALLEL
)
6653 switch (get_attr_conds (this_insn
))
6665 /* Instructions using or affecting the condition codes make it
6667 scanbody
= PATTERN (this_insn
);
6668 if (! (GET_CODE (scanbody
) == SET
6669 || GET_CODE (scanbody
) == PARALLEL
)
6670 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
6680 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
6681 arm_target_label
= CODE_LABEL_NUMBER (label
);
6682 else if (seeking_return
|| arm_ccfsm_state
== 2)
6684 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
6686 this_insn
= next_nonnote_insn (this_insn
);
6687 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
6688 || GET_CODE (this_insn
) == CODE_LABEL
))
6693 /* Oh, dear! we ran off the end.. give up */
6694 recog (PATTERN (insn
), insn
, NULL_PTR
);
6695 arm_ccfsm_state
= 0;
6696 arm_target_insn
= NULL
;
6699 arm_target_insn
= this_insn
;
6708 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
6710 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
6711 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
6712 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
6713 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
6717 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6720 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
6724 if (reverse
|| then_not_else
)
6725 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
6728 /* Restore recog_data (getting the attributes of other insns can
6729 destroy this array, but final.c assumes that it remains intact
6730 across this call; since the insn has been recognized already we
6731 call recog direct). */
6732 recog (PATTERN (insn
), insn
, NULL_PTR
);
6736 #ifdef AOF_ASSEMBLER
6737 /* Special functions only needed when producing AOF syntax assembler. */
6739 rtx aof_pic_label
= NULL_RTX
;
6742 struct pic_chain
* next
;
6746 static struct pic_chain
* aof_pic_chain
= NULL
;
6752 struct pic_chain
** chainp
;
6755 if (aof_pic_label
== NULL_RTX
)
6757 /* We mark this here and not in arm_add_gc_roots() to avoid
6758 polluting even more code with ifdefs, and because it never
6759 contains anything useful until we assign to it here. */
6760 ggc_add_rtx_root (&aof_pic_label
, 1);
6761 /* This needs to persist throughout the compilation. */
6762 end_temporary_allocation ();
6763 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
6764 resume_temporary_allocation ();
6767 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
6768 offset
+= 4, chainp
= &(*chainp
)->next
)
6769 if ((*chainp
)->symname
== XSTR (x
, 0))
6770 return plus_constant (aof_pic_label
, offset
);
6772 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
6773 (*chainp
)->next
= NULL
;
6774 (*chainp
)->symname
= XSTR (x
, 0);
6775 return plus_constant (aof_pic_label
, offset
);
6779 aof_dump_pic_table (f
)
6782 struct pic_chain
* chain
;
6784 if (aof_pic_chain
== NULL
)
6787 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
6788 PIC_OFFSET_TABLE_REGNUM
,
6789 PIC_OFFSET_TABLE_REGNUM
);
6790 fputs ("|x$adcons|\n", f
);
6792 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
6794 fputs ("\tDCD\t", f
);
6795 assemble_name (f
, chain
->symname
);
6800 int arm_text_section_count
= 1;
6805 static char buf
[100];
6806 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
6807 arm_text_section_count
++);
6809 strcat (buf
, ", PIC, REENTRANT");
6813 static int arm_data_section_count
= 1;
6818 static char buf
[100];
6819 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
6823 /* The AOF assembler is religiously strict about declarations of
6824 imported and exported symbols, so that it is impossible to declare
6825 a function as imported near the beginning of the file, and then to
6826 export it later on. It is, however, possible to delay the decision
6827 until all the functions in the file have been compiled. To get
6828 around this, we maintain a list of the imports and exports, and
6829 delete from it any that are subsequently defined. At the end of
6830 compilation we spit the remainder of the list out before the END
6835 struct import
* next
;
6839 static struct import
* imports_list
= NULL
;
6842 aof_add_import (name
)
6845 struct import
* new;
6847 for (new = imports_list
; new; new = new->next
)
6848 if (new->name
== name
)
6851 new = (struct import
*) xmalloc (sizeof (struct import
));
6852 new->next
= imports_list
;
6858 aof_delete_import (name
)
6861 struct import
** old
;
6863 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
6865 if ((*old
)->name
== name
)
6867 *old
= (*old
)->next
;
6873 int arm_main_function
= 0;
6876 aof_dump_imports (f
)
6879 /* The AOF assembler needs this to cause the startup code to be extracted
6880 from the library. Brining in __main causes the whole thing to work
6882 if (arm_main_function
)
6885 fputs ("\tIMPORT __main\n", f
);
6886 fputs ("\tDCD __main\n", f
);
6889 /* Now dump the remaining imports. */
6890 while (imports_list
)
6892 fprintf (f
, "\tIMPORT\t");
6893 assemble_name (f
, imports_list
->name
);
6895 imports_list
= imports_list
->next
;
6898 #endif /* AOF_ASSEMBLER */