| blob | 4e299e66c2194e699dcb331f1198316486d69c2a |
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #ifndef GCC_MCORE_H
24 #define GCC_MCORE_H
26 /* RBE: need to move these elsewhere. */
27 #undef LIKE_PPC_ABI
28 #define MCORE_STRUCT_ARGS
29 /* RBE: end of "move elsewhere". */
31 /* Run-time Target Specification. */
32 #define TARGET_MCORE
34 /* Get tree.c to declare a target-specific specialization of
35 merge_decl_attributes. */
36 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1
38 #define TARGET_CPU_CPP_BUILTINS() \
39 do \
40 { \
43 if (TARGET_LITTLE_END) \
45 else \
47 if (TARGET_M340) \
49 else \
51 } \
52 while (0)
54 /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
55 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}. */
56 #undef CPP_SPEC
59 /* We don't have a -lg library, so don't put it in the list. */
60 #undef LIB_SPEC
63 #undef ASM_SPEC
66 #undef LINK_SPEC
69 /* Can only count on 16 bits of availability; change to long would affect
70 many architecture specific files (other architectures...). */
84 #define TARGET_DEFAULT \
85 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
87 #ifndef MULTILIB_DEFAULTS
89 #endif
91 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
92 /* The ability to have 4 byte alignment is being suppressed for now.
93 If this ability is reenabled, you must enable the definition below
94 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
95 #if 0
96 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
97 #else
98 #define TARGET_8ALIGN 1
99 #endif
100 #define TARGET_DIV (target_flags & DIV_BIT)
101 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
102 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
103 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
104 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
105 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
106 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
107 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
108 #define TARGET_M340 (target_flags & M340_BIT)
111 #define TARGET_SWITCHES \
155 }
159 /* Target specific options (as opposed to the switches above). */
162 #define TARGET_OPTIONS \
163 { \
166 }
168 /* The MCore ABI says that bitfields are unsigned by default. */
171 /* What options are we going to default to specific settings when
172 -O* happens; the user can subsequently override these settings.
174 Omitting the frame pointer is a very good idea on the MCore.
175 Scheduling isn't worth anything on the current MCore implementation. */
176 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
177 { \
178 if (LEVEL) \
179 { \
180 flag_no_function_cse = 1; \
181 flag_omit_frame_pointer = 1; \
182 \
183 if (LEVEL >= 2) \
184 { \
185 flag_caller_saves = 0; \
186 flag_schedule_insns = 0; \
187 flag_schedule_insns_after_reload = 0; \
188 } \
189 } \
190 if (SIZE) \
191 { \
192 target_flags &= ~ HARDLIT_BIT; \
193 } \
194 }
196 /* What options are we going to force to specific settings,
197 regardless of what the user thought he wanted.
198 We also use this for some post-processing of options. */
199 #define OVERRIDE_OPTIONS mcore_override_options ()
201 /* Target machine storage Layout. */
203 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
204 if (GET_MODE_CLASS (MODE) == MODE_INT \
205 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
206 { \
207 (MODE) = SImode; \
208 (UNSIGNEDP) = 1; \
209 }
211 /* Define this if most significant bit is lowest numbered
212 in instructions that operate on numbered bit-fields. */
213 #define BITS_BIG_ENDIAN 0
215 /* Define this if most significant byte of a word is the lowest numbered. */
216 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
218 /* Define this if most significant word of a multiword number is the lowest
219 numbered. */
220 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
222 #define LIBGCC2_WORDS_BIG_ENDIAN 1
223 #ifdef __MCORELE__
224 #undef LIBGCC2_WORDS_BIG_ENDIAN
225 #define LIBGCC2_WORDS_BIG_ENDIAN 0
226 #endif
228 #define MAX_BITS_PER_WORD 32
230 /* Width of a word, in units (bytes). */
231 #define UNITS_PER_WORD 4
233 /* A C expression for the size in bits of the type `long long' on the
234 target machine. If you don't define this, the default is two
235 words. */
236 #define LONG_LONG_TYPE_SIZE 64
238 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
239 #define PARM_BOUNDARY 32
241 /* Doubles must be aligned to an 8 byte boundary. */
242 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
243 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
244 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
246 /* Boundary (in *bits*) on which stack pointer should be aligned. */
247 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
249 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
251 #define STACK_UNITS_MAXSTEP 4096
253 /* Allocation boundary (in *bits*) for the code of a function. */
254 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
256 /* Alignment of field after `int : 0' in a structure. */
257 #define EMPTY_FIELD_BOUNDARY 32
259 /* No data type wants to be aligned rounder than this. */
260 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
262 /* The best alignment to use in cases where we have a choice. */
263 #define FASTEST_ALIGNMENT 32
265 /* Every structures size must be a multiple of 8 bits. */
266 #define STRUCTURE_SIZE_BOUNDARY 8
268 /* Look at the fundamental type that is used for a bit-field and use
269 that to impose alignment on the enclosing structure.
270 struct s {int a:8}; should have same alignment as "int", not "char". */
271 #define PCC_BITFIELD_TYPE_MATTERS 1
273 /* Largest integer machine mode for structures. If undefined, the default
274 is GET_MODE_SIZE(DImode). */
275 #define MAX_FIXED_MODE_SIZE 32
277 /* Make strings word-aligned so strcpy from constants will be faster. */
278 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
279 ((TREE_CODE (EXP) == STRING_CST \
280 && (ALIGN) < FASTEST_ALIGNMENT) \
281 ? FASTEST_ALIGNMENT : (ALIGN))
283 /* Make arrays of chars word-aligned for the same reasons. */
284 #define DATA_ALIGNMENT(TYPE, ALIGN) \
285 (TREE_CODE (TYPE) == ARRAY_TYPE \
286 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
287 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
289 /* Set this nonzero if move instructions will actually fail to work
290 when given unaligned data. */
291 #define STRICT_ALIGNMENT 1
293 /* Standard register usage. */
295 /* Register allocation for our first guess
297 r0 stack pointer
298 r1 scratch, target reg for xtrb?
299 r2-r7 arguments.
300 r8-r14 call saved
301 r15 link register
302 ap arg pointer (doesn't really exist, always eliminated)
303 c c bit
304 fp frame pointer (doesn't really exist, always eliminated)
305 x19 two control registers. */
307 /* Number of actual hardware registers.
308 The hardware registers are assigned numbers for the compiler
309 from 0 to just below FIRST_PSEUDO_REGISTER.
310 All registers that the compiler knows about must be given numbers,
311 even those that are not normally considered general registers.
313 MCore has 16 integer registers and 2 control registers + the arg
314 pointer. */
316 #define FIRST_PSEUDO_REGISTER 20
321 /* RBE: mcore.md depends on CC_REG being set to 17. */
325 /* Specify the registers used for certain standard purposes.
326 The values of these macros are register numbers. */
333 /* The assembler's names for the registers. RFP need not always be used as
334 the Real framepointer; it can also be used as a normal general register.
335 Note that the name `fp' is horribly misleading since `fp' is in fact only
336 the argument-and-return-context pointer. */
337 #define REGISTER_NAMES \
338 { \
342 }
344 /* 1 for registers that have pervasive standard uses
345 and are not available for the register allocator. */
346 #define FIXED_REGISTERS \
348 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
350 /* 1 for registers not available across function calls.
351 These must include the FIXED_REGISTERS and also any
352 registers that can be used without being saved.
353 The latter must include the registers where values are returned
354 and the register where structure-value addresses are passed.
355 Aside from that, you can include as many other registers as you like. */
357 /* RBE: r15 {link register} not available across calls,
358 But we don't mark it that way here.... */
359 #define CALL_USED_REGISTERS \
361 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
363 /* The order in which register should be allocated. */
364 #define REG_ALLOC_ORDER \
366 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
368 /* Return number of consecutive hard regs needed starting at reg REGNO
369 to hold something of mode MODE.
370 This is ordinarily the length in words of a value of mode MODE
371 but can be less for certain modes in special long registers.
373 On the MCore regs are UNITS_PER_WORD bits wide; */
374 #define HARD_REGNO_NREGS(REGNO, MODE) \
375 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
377 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
378 We may keep double values in even registers. */
379 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
380 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
382 /* Value is 1 if it is a good idea to tie two pseudo registers
383 when one has mode MODE1 and one has mode MODE2.
384 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
385 for any hard reg, then this must be 0 for correct output. */
386 #define MODES_TIEABLE_P(MODE1, MODE2) \
387 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
389 /* Value should be nonzero if functions must have frame pointers.
390 Zero means the frame pointer need not be set up (and parms may be accessed
391 via the stack pointer) in functions that seem suitable. */
392 #define FRAME_POINTER_REQUIRED 0
394 /* Definitions for register eliminations.
396 We have two registers that can be eliminated on the MCore. First, the
397 frame pointer register can often be eliminated in favor of the stack
398 pointer register. Secondly, the argument pointer register can always be
399 eliminated; it is replaced with either the stack or frame pointer. */
401 /* Base register for access to arguments of the function. */
402 #define ARG_POINTER_REGNUM 16
404 /* Register in which the static-chain is passed to a function. */
405 #define STATIC_CHAIN_REGNUM 1
407 /* This is an array of structures. Each structure initializes one pair
408 of eliminable registers. The "from" register number is given first,
409 followed by "to". Eliminations of the same "from" register are listed
410 in order of preference. */
411 #define ELIMINABLE_REGS \
412 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
413 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
414 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
416 /* Given FROM and TO register numbers, say whether this elimination
417 is allowed. */
418 #define CAN_ELIMINATE(FROM, TO) \
419 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
421 /* Define the offset between two registers, one to be eliminated, and the other
422 its replacement, at the start of a routine. */
423 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
424 OFFSET = mcore_initial_elimination_offset (FROM, TO)
426 /* Define the classes of registers for register constraints in the
427 machine description. Also define ranges of constants.
429 One of the classes must always be named ALL_REGS and include all hard regs.
430 If there is more than one class, another class must be named NO_REGS
431 and contain no registers.
433 The name GENERAL_REGS must be the name of a class (or an alias for
434 another name such as ALL_REGS). This is the class of registers
435 that is allowed by "g" or "r" in a register constraint.
436 Also, registers outside this class are allocated only when
437 instructions express preferences for them.
439 The classes must be numbered in nondecreasing order; that is,
440 a larger-numbered class must never be contained completely
441 in a smaller-numbered class.
443 For any two classes, it is very desirable that there be another
444 class that represents their union. */
446 /* The MCore has only general registers. There are
447 also some special purpose registers: the T bit register, the
448 procedure Link and the Count Registers. */
449 enum reg_class
450 {
451 NO_REGS,
452 ONLYR1_REGS,
453 LRW_REGS,
454 GENERAL_REGS,
455 C_REGS,
456 ALL_REGS,
457 LIM_REG_CLASSES
458 };
460 #define N_REG_CLASSES (int) LIM_REG_CLASSES
462 /* Give names of register classes as strings for dump file. */
463 #define REG_CLASS_NAMES \
464 { \
471 }
473 /* Define which registers fit in which classes.
474 This is an initializer for a vector of HARD_REG_SET
475 of length N_REG_CLASSES. */
477 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
478 #define REG_CLASS_CONTENTS \
479 { \
486 }
488 /* The same information, inverted:
489 Return the class number of the smallest class containing
490 reg number REGNO. This could be a conditional expression
491 or could index an array. */
494 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
496 /* When defined, the compiler allows registers explicitly used in the
497 rtl to be used as spill registers but prevents the compiler from
498 extending the lifetime of these registers. */
499 #define SMALL_REGISTER_CLASSES 1
501 /* The class value for index registers, and the one for base regs. */
502 #define INDEX_REG_CLASS NO_REGS
503 #define BASE_REG_CLASS GENERAL_REGS
505 /* Get reg_class from a letter such as appears in the machine
506 description. */
509 #define REG_CLASS_FROM_LETTER(C) \
512 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
513 can be used to stand for particular ranges of immediate operands.
514 This macro defines what the ranges are.
515 C is the letter, and VALUE is a constant value.
516 Return 1 if VALUE is in the range specified by C.
517 I: loadable by movi (0..127)
518 J: arithmetic operand 1..32
519 K: shift operand 0..31
520 L: negative arithmetic operand -1..-32
521 M: powers of two, constants loadable by bgeni
522 N: powers of two minus 1, constants loadable by bmaski, including -1
523 O: allowed by cmov with two constants +/- 1 of each other
524 P: values we will generate 'inline' -- without an 'lrw'
526 Others defined for use after reload
527 Q: constant 1
528 R: a label
529 S: 0/1/2 cleared bits out of 32 [for bclri's]
530 T: 2 set bits out of 32 [for bseti's]
531 U: constant 0
532 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
533 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
534 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
535 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
536 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
537 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
538 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
539 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
540 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
541 CONST_OK_FOR_M(VALUE) || \
542 CONST_OK_FOR_N(VALUE) || \
543 CONST_OK_FOR_M((int)(VALUE) - 1) || \
544 CONST_OK_FOR_N((int)(VALUE) + 1))
546 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
548 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
557 : 0)
559 /* Similar, but for floating constants, and defining letters G and H.
560 Here VALUE is the CONST_DOUBLE rtx itself. */
561 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
563 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
564 : 0)
566 /* Letters in the range `Q' through `U' in a register constraint string
567 may be defined in a machine-dependent fashion to stand for arbitrary
568 operand types. */
569 #define EXTRA_CONSTRAINT(OP, C) \
571 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
573 && mcore_num_zeros (INTVAL (OP)) <= 2) \
575 && mcore_num_ones (INTVAL (OP)) == 2) \
577 && INTVAL(OP) == 1) \
579 && INTVAL(OP) == 0) \
580 : 0)
582 /* Given an rtx X being reloaded into a reg required to be
583 in class CLASS, return the class of reg to actually use.
584 In general this is just CLASS; but on some machines
585 in some cases it is preferable to use a more restrictive class. */
586 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
588 /* Return the register class of a scratch register needed to copy IN into
589 or out of a register in CLASS in MODE. If it can be done directly,
590 NO_REGS is returned. */
591 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
592 mcore_secondary_reload_class (CLASS, MODE, X)
594 /* Return the maximum number of consecutive registers
595 needed to represent mode MODE in a register of class CLASS.
597 On MCore this is the size of MODE in words. */
598 #define CLASS_MAX_NREGS(CLASS, MODE) \
599 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
601 /* Stack layout; function entry, exit and calling. */
603 /* Define the number of register that can hold parameters.
604 These two macros are used only in other macro definitions below. */
605 #define NPARM_REGS 6
606 #define FIRST_PARM_REG 2
607 #define FIRST_RET_REG 2
609 /* Define this if pushing a word on the stack
610 makes the stack pointer a smaller address. */
611 #define STACK_GROWS_DOWNWARD
613 /* Offset within stack frame to start allocating local variables at.
614 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
615 first local allocated. Otherwise, it is the offset to the BEGINNING
616 of the first local allocated. */
617 #define STARTING_FRAME_OFFSET 0
619 /* If defined, the maximum amount of space required for outgoing arguments
620 will be computed and placed into the variable
621 `current_function_outgoing_args_size'. No space will be pushed
622 onto the stack for each call; instead, the function prologue should
623 increase the stack frame size by this amount. */
624 #define ACCUMULATE_OUTGOING_ARGS 1
626 /* Offset of first parameter from the argument pointer register value. */
627 #define FIRST_PARM_OFFSET(FNDECL) 0
629 /* Value is the number of byte of arguments automatically
630 popped when returning from a subroutine call.
631 FUNTYPE is the data type of the function (as a tree),
632 or for a library call it is an identifier node for the subroutine name.
633 SIZE is the number of bytes of arguments passed on the stack.
635 On the MCore, the callee does not pop any of its arguments that were passed
636 on the stack. */
637 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
639 /* Define how to find the value returned by a function.
640 VALTYPE is the data type of the value (as a tree).
641 If the precise function being called is known, FUNC is its FUNCTION_DECL;
642 otherwise, FUNC is 0. */
643 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
645 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
646 we want to retain compatibility with older gcc versions. */
647 #define DEFAULT_PCC_STRUCT_RETURN 0
649 /* Define how to find the value returned by a library function
650 assuming the value has mode MODE. */
651 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG)
653 /* 1 if N is a possible register number for a function value.
654 On the MCore, only r4 can return results. */
655 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
657 /* 1 if N is a possible register number for function argument passing. */
658 #define FUNCTION_ARG_REGNO_P(REGNO) \
659 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
661 /* Define a data type for recording info about an argument list
662 during the scan of that argument list. This data type should
663 hold all necessary information about the function itself
664 and about the args processed so far, enough to enable macros
665 such as FUNCTION_ARG to determine where the next arg should go.
667 On MCore, this is a single integer, which is a number of words
668 of arguments scanned so far (including the invisible argument,
669 if any, which holds the structure-value-address).
670 Thus NARGREGS or more means all following args should go on the stack. */
671 #define CUMULATIVE_ARGS int
673 #define ROUND_ADVANCE(SIZE) \
674 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
676 /* Round a register number up to a proper boundary for an arg of mode
677 MODE.
679 We round to an even reg for things larger than a word. */
680 #define ROUND_REG(X, MODE) \
681 ((TARGET_8ALIGN \
682 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
683 ? ((X) + ((X) & 1)) : (X))
686 /* Initialize a variable CUM of type CUMULATIVE_ARGS
687 for a call to a function whose data type is FNTYPE.
688 For a library call, FNTYPE is 0.
690 On MCore, the offset always starts at 0: the first parm reg is always
691 the same reg. */
692 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
693 ((CUM) = 0)
695 /* Update the data in CUM to advance over an argument
696 of mode MODE and data type TYPE.
697 (TYPE is null for libcalls where that information may not be
698 available.) */
699 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
700 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
701 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
703 /* Define where to put the arguments to a function. */
704 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
705 mcore_function_arg (CUM, MODE, TYPE, NAMED)
707 /* For an arg passed partly in registers and partly in memory,
708 this is the number of registers used.
709 For args passed entirely in registers or entirely in memory, zero.
710 Any arg that starts in the first NPARM_REGS regs but won't entirely
711 fit in them needs partial registers on the MCore. */
712 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
713 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
715 /* Call the function profiler with a given profile label. */
716 #define FUNCTION_PROFILER(STREAM,LABELNO) \
717 { \
721 }
723 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
724 the stack pointer does not matter. The value is tested only in
725 functions that have frame pointers.
726 No definition is equivalent to always zero. */
727 #define EXIT_IGNORE_STACK 0
729 /* Output assembler code for a block containing the constant parts
730 of a trampoline, leaving space for the variable parts.
732 On the MCore, the trampoline looks like:
733 lrw r1, function
734 lrw r13, area
735 jmp r13
736 or r0, r0
737 .literals */
738 #define TRAMPOLINE_TEMPLATE(FILE) \
739 { \
746 }
748 /* Length in units of the trampoline for entering a nested function. */
749 #define TRAMPOLINE_SIZE 12
751 /* Alignment required for a trampoline in bits. */
752 #define TRAMPOLINE_ALIGNMENT 32
754 /* Emit RTL insns to initialize the variable parts of a trampoline.
755 FNADDR is an RTX for the address of the function's pure code.
756 CXT is an RTX for the static chain value for the function. */
757 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
758 { \
759 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
760 (CXT)); \
761 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
762 (FNADDR)); \
763 }
765 /* Macros to check register numbers against specific register classes. */
767 /* These assume that REGNO is a hard or pseudo reg number.
768 They give nonzero only if REGNO is a hard reg of the suitable class
769 or a pseudo reg currently allocated to a suitable hard reg.
770 Since they use reg_renumber, they are safe only once reg_renumber
771 has been allocated, which happens in local-alloc.c. */
772 #define REGNO_OK_FOR_BASE_P(REGNO) \
773 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
775 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
777 /* Maximum number of registers that can appear in a valid memory
778 address. */
779 #define MAX_REGS_PER_ADDRESS 1
781 /* Recognize any constant value that is a valid address. */
782 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
784 /* Nonzero if the constant value X is a legitimate general operand.
785 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
787 On the MCore, allow anything but a double. */
788 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
790 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
791 and check its validity for a certain class.
792 We have two alternate definitions for each of them.
793 The usual definition accepts all pseudo regs; the other rejects
794 them unless they have been allocated suitable hard regs.
795 The symbol REG_OK_STRICT causes the latter definition to be used. */
796 #ifndef REG_OK_STRICT
798 /* Nonzero if X is a hard reg that can be used as a base reg
799 or if it is a pseudo reg. */
800 #define REG_OK_FOR_BASE_P(X) \
801 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
803 /* Nonzero if X is a hard reg that can be used as an index
804 or if it is a pseudo reg. */
805 #define REG_OK_FOR_INDEX_P(X) 0
807 #else
809 /* Nonzero if X is a hard reg that can be used as a base reg. */
810 #define REG_OK_FOR_BASE_P(X) \
811 REGNO_OK_FOR_BASE_P (REGNO (X))
813 /* Nonzero if X is a hard reg that can be used as an index. */
814 #define REG_OK_FOR_INDEX_P(X) 0
816 #endif
817 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
818 that is a valid memory address for an instruction.
819 The MODE argument is the machine mode for the MEM expression
820 that wants to use this address.
822 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
823 #define BASE_REGISTER_RTX_P(X) \
824 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
826 #define INDEX_REGISTER_RTX_P(X) \
827 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
830 /* Jump to LABEL if X is a valid address RTX. This must also take
831 REG_OK_STRICT into account when deciding about valid registers, but it uses
832 the above macros so we are in luck.
834 Allow REG
835 REG+disp
837 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
838 and for DI is 0..56 because we use two SI loads, etc. */
839 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
840 do \
841 { \
842 if (GET_CODE (OP) == CONST_INT) \
843 { \
844 if (GET_MODE_SIZE (MODE) >= 4 \
845 && (((unsigned)INTVAL (OP)) % 4) == 0 \
846 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
847 goto LABEL; \
848 if (GET_MODE_SIZE (MODE) == 2 \
849 && (((unsigned)INTVAL (OP)) % 2) == 0 \
850 && ((unsigned)INTVAL (OP)) <= 30) \
851 goto LABEL; \
852 if (GET_MODE_SIZE (MODE) == 1 \
853 && ((unsigned)INTVAL (OP)) <= 15) \
854 goto LABEL; \
855 } \
856 } \
857 while (0)
859 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
860 { \
861 if (BASE_REGISTER_RTX_P (X)) \
862 goto LABEL; \
863 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
864 { \
865 rtx xop0 = XEXP (X,0); \
866 rtx xop1 = XEXP (X,1); \
867 if (BASE_REGISTER_RTX_P (xop0)) \
868 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
869 if (BASE_REGISTER_RTX_P (xop1)) \
870 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
871 } \
872 }
874 /* Go to LABEL if ADDR (a legitimate address expression)
875 has an effect that depends on the machine mode it is used for. */
876 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
877 { \
878 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
879 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
880 goto LABEL; \
881 }
883 /* Specify the machine mode that this machine uses
884 for the index in the tablejump instruction. */
885 #define CASE_VECTOR_MODE SImode
887 /* 'char' is signed by default. */
888 #define DEFAULT_SIGNED_CHAR 0
890 /* The type of size_t unsigned int. */
893 /* Max number of bytes we can move from memory to memory
894 in one reasonably fast instruction. */
895 #define MOVE_MAX 4
897 /* Define if operations between registers always perform the operation
898 on the full register even if a narrower mode is specified. */
899 #define WORD_REGISTER_OPERATIONS
901 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
902 will either zero-extend or sign-extend. The value of this macro should
903 be the code that says which one of the two operations is implicitly
904 done, NIL if none. */
905 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
907 /* Nonzero if access to memory by bytes is slow and undesirable. */
908 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
910 /* Immediate shift counts are truncated by the output routines (or was it
911 the assembler?). Shift counts in a register are truncated by ARM. Note
912 that the native compiler puts too large (> 32) immediate shift counts
913 into a register and shifts by the register, letting the ARM decide what
914 to do instead of doing that itself. */
915 #define SHIFT_COUNT_TRUNCATED 1
917 /* All integers have the same format so truncation is easy. */
918 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
920 /* Define this if addresses of constant functions
921 shouldn't be put through pseudo regs where they can be cse'd.
922 Desirable on machines where ordinary constants are expensive
923 but a CALL with constant address is cheap. */
924 /* Why is this defined??? -- dac */
925 #define NO_FUNCTION_CSE 1
927 /* The machine modes of pointers and functions. */
928 #define Pmode SImode
929 #define FUNCTION_MODE Pmode
931 /* Compute extra cost of moving data between one register class
932 and another. All register moves are cheap. */
933 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
935 #define WORD_REGISTER_OPERATIONS
937 /* Assembler output control. */
945 /* Switch to the text or data segment. */
949 #undef EXTRA_SECTIONS
950 #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS
952 #undef EXTRA_SECTION_FUNCTIONS
953 #define EXTRA_SECTION_FUNCTIONS \
954 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
955 SWITCH_SECTION_FUNCTION
957 /* Switch to SECTION (an `enum in_section').
959 ??? This facility should be provided by GCC proper.
960 The problem is that we want to temporarily switch sections in
961 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
962 afterwards. */
963 #define SWITCH_SECTION_FUNCTION \
964 static void switch_to_section (enum in_section, tree); \
965 static void \
966 switch_to_section (enum in_section section, tree decl) \
967 { \
968 switch (section) \
969 { \
970 case in_text: text_section (); break; \
971 case in_data: data_section (); break; \
972 case in_named: named_section (decl, NULL, 0); break; \
973 SUBTARGET_SWITCH_SECTIONS \
974 default: abort (); break; \
975 } \
976 }
978 /* Switch into a generic section. */
979 #undef TARGET_ASM_NAMED_SECTION
980 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
982 /* This is how to output an insn to push a register on the stack.
983 It need not be very fast code. */
984 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
986 reg_names[STACK_POINTER_REGNUM], \
987 (STACK_BOUNDARY / BITS_PER_UNIT), \
988 reg_names[REGNO], \
989 reg_names[STACK_POINTER_REGNUM])
991 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
992 #define REG_PUSH_LENGTH 2
994 /* This is how to output an insn to pop a register from the stack. */
995 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
997 reg_names[REGNO], \
998 reg_names[STACK_POINTER_REGNUM], \
999 reg_names[STACK_POINTER_REGNUM], \
1000 (STACK_BOUNDARY / BITS_PER_UNIT))
1003 /* Output a reference to a label. */
1004 #undef ASM_OUTPUT_LABELREF
1005 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1007 (* targetm.strip_name_encoding) (NAME))
1009 /* This is how to output an assembler line
1010 that says to advance the location counter
1011 to a multiple of 2**LOG bytes. */
1012 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1013 if ((LOG) != 0) \
1016 #ifndef ASM_DECLARE_RESULT
1017 #define ASM_DECLARE_RESULT(FILE, RESULT)
1018 #endif
1020 #define MULTIPLE_SYMBOL_SPACES 1
1022 #define SUPPORTS_ONE_ONLY 1
1024 /* A pair of macros to output things for the callgraph data.
1025 VALUE means (to the tools that reads this info later):
1026 0 a call from src to dst
1027 1 the call is special (e.g. dst is "unknown" or "alloca")
1028 2 the call is special (e.g., the src is a table instead of routine)
1030 Frame sizes are augmented with timestamps to help later tools
1031 differentiate between static entities with same names in different
1032 files. */
1034 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1035 do \
1036 { \
1037 if (mcore_current_compilation_timestamp == 0) \
1038 mcore_current_compilation_timestamp = time (0); \
1040 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1041 } \
1042 while (0)
1044 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1045 do \
1046 { \
1048 (SRCNAME), (DSTNAME), (VALUE)); \
1049 } \
1050 while (0)
1052 /* Globalizing directive for a label. */
1055 /* The prefix to add to user-visible assembler symbols. */
1056 #undef USER_LABEL_PREFIX
1059 /* Make an internal label into a string. */
1060 #undef ASM_GENERATE_INTERNAL_LABEL
1061 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1064 /* Jump tables must be 32 bit aligned. */
1065 #undef ASM_OUTPUT_CASE_LABEL
1066 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1069 /* Output a relative address. Not needed since jump tables are absolute
1070 but we must define it anyway. */
1071 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1074 /* Output an element of a dispatch table. */
1075 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1078 /* Output various types of constants. */
1080 /* This is how to output an assembler line
1081 that says to advance the location counter by SIZE bytes. */
1082 #undef ASM_OUTPUT_SKIP
1083 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1086 /* This says how to output an assembler line
1087 to define a global common symbol, with alignment information. */
1088 /* XXX - for now we ignore the alignment. */
1089 #undef ASM_OUTPUT_ALIGNED_COMMON
1090 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1091 do \
1092 { \
1093 if (mcore_dllexport_name_p (NAME)) \
1094 MCORE_EXPORT_NAME (FILE, NAME) \
1095 if (! mcore_dllimport_name_p (NAME)) \
1096 { \
1098 assemble_name (FILE, NAME); \
1100 } \
1101 } \
1102 while (0)
1104 /* This says how to output an assembler line
1105 to define a local common symbol.... */
1106 #undef ASM_OUTPUT_LOCAL
1107 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1109 assemble_name (FILE, NAME), \
1112 /* ... and how to define a local common symbol whose alignment
1113 we wish to specify. ALIGN comes in as bits, we have to turn
1114 it into bytes. */
1115 #undef ASM_OUTPUT_ALIGNED_LOCAL
1116 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1117 do \
1118 { \
1120 assemble_name ((FILE), (NAME)); \
1122 } \
1123 while (0)
1125 /* Print operand X (an rtx) in assembler syntax to file FILE.
1126 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1127 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1128 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1130 /* Print a memory address as an operand to reference that memory location. */
1131 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1133 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1136 #define PREDICATE_CODES \