1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2012 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
53 #include "sched-int.h"
55 #include "tree-flow.h"
58 #include "tm-constrs.h"
60 #include "tree-vectorizer.h"
63 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66 #include "gstab.h" /* for N_SLINE */
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
73 #define min(A,B) ((A) < (B) ? (A) : (B))
74 #define max(A,B) ((A) > (B) ? (A) : (B))
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack
{
78 int reload_completed
; /* stack info won't change from here on */
79 int first_gp_reg_save
; /* first callee saved GP register used */
80 int first_fp_reg_save
; /* first callee saved FP register used */
81 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
82 int lr_save_p
; /* true if the link reg needs to be saved */
83 int cr_save_p
; /* true if the CR reg needs to be saved */
84 unsigned int vrsave_mask
; /* mask of vec registers to save */
85 int push_p
; /* true if we need to allocate stack space */
86 int calls_p
; /* true if the function makes any calls */
87 int world_save_p
; /* true if we're saving *everything*:
88 r13-r31, cr, f14-f31, vrsave, v20-v31 */
89 enum rs6000_abi abi
; /* which ABI to use */
90 int gp_save_offset
; /* offset to save GP regs from initial SP */
91 int fp_save_offset
; /* offset to save FP regs from initial SP */
92 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
93 int lr_save_offset
; /* offset to save LR from initial SP */
94 int cr_save_offset
; /* offset to save CR from initial SP */
95 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
96 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
97 int varargs_save_offset
; /* offset to save the varargs registers */
98 int ehrd_offset
; /* offset to EH return data */
99 int reg_size
; /* register size (4 or 8) */
100 HOST_WIDE_INT vars_size
; /* variable save area size */
101 int parm_size
; /* outgoing parameter size */
102 int save_size
; /* save area size */
103 int fixed_size
; /* fixed size of stack frame */
104 int gp_size
; /* size of saved GP registers */
105 int fp_size
; /* size of saved FP registers */
106 int altivec_size
; /* size of saved AltiVec registers */
107 int cr_size
; /* size to hold CR if not in save_size */
108 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size
; /* size of altivec alignment padding if
111 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size
;
113 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
114 int spe_64bit_regs_used
;
118 /* A C structure for machine-specific, per-function data.
119 This is added to the cfun structure. */
120 typedef struct GTY(()) machine_function
122 /* Some local-dynamic symbol. */
123 const char *some_ld_name
;
124 /* Whether the instruction chain has been scanned already. */
125 int insn_chain_scanned_p
;
126 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
127 int ra_needs_full_frame
;
128 /* Flags if __builtin_return_address (0) was used. */
130 /* Cache lr_save_p after expansion of builtin_eh_return. */
132 /* Whether we need to save the TOC to the reserved stack location in the
133 function prologue. */
134 bool save_toc_in_prologue
;
135 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
136 varargs save area. */
137 HOST_WIDE_INT varargs_save_offset
;
138 /* Temporary stack slot to use for SDmode copies. This slot is
139 64-bits wide and is allocated early enough so that the offset
140 does not overflow the 16-bit load/store offset field. */
141 rtx sdmode_stack_slot
;
144 /* Support targetm.vectorize.builtin_mask_for_load. */
145 static GTY(()) tree altivec_builtin_mask_for_load
;
147 /* Set to nonzero once AIX common-mode calls have been defined. */
148 static GTY(()) int common_mode_defined
;
150 /* Label number of label created for -mrelocatable, to call to so we can
151 get the address of the GOT section */
152 static int rs6000_pic_labelno
;
155 /* Counter for labels which are to be placed in .fixup. */
156 int fixuplabelno
= 0;
159 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
162 /* Specify the machine mode that pointers have. After generation of rtl, the
163 compiler makes no further distinction between pointers and any other objects
164 of this machine mode. The type is unsigned since not all things that
165 include rs6000.h also include machmode.h. */
166 unsigned rs6000_pmode
;
168 /* Width in bits of a pointer. */
169 unsigned rs6000_pointer_size
;
171 #ifdef HAVE_AS_GNU_ATTRIBUTE
172 /* Flag whether floating point values have been passed/returned. */
173 static bool rs6000_passes_float
;
174 /* Flag whether vector values have been passed/returned. */
175 static bool rs6000_passes_vector
;
176 /* Flag whether small (<= 8 byte) structures have been returned. */
177 static bool rs6000_returns_struct
;
180 /* Value is TRUE if register/mode pair is acceptable. */
181 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
183 /* Maximum number of registers needed for a given register class and mode. */
184 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
186 /* How many registers are needed for a given register and mode. */
187 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
189 /* Map register number to register class. */
190 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
192 /* Reload functions based on the type and the vector unit. */
193 static enum insn_code rs6000_vector_reload
[NUM_MACHINE_MODES
][2];
195 static int dbg_cost_ctrl
;
197 /* Built in types. */
198 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
199 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
201 /* Flag to say the TOC is initialized */
203 char toc_label_name
[10];
205 /* Cached value of rs6000_variable_issue. This is cached in
206 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
207 static short cached_can_issue_more
;
209 static GTY(()) section
*read_only_data_section
;
210 static GTY(()) section
*private_data_section
;
211 static GTY(()) section
*tls_data_section
;
212 static GTY(()) section
*tls_private_data_section
;
213 static GTY(()) section
*read_only_private_data_section
;
214 static GTY(()) section
*sdata2_section
;
215 static GTY(()) section
*toc_section
;
217 struct builtin_description
219 const HOST_WIDE_INT mask
;
220 const enum insn_code icode
;
221 const char *const name
;
222 const enum rs6000_builtins code
;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
227 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align
[NUM_MACHINE_MODES
];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask
{
246 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
247 RECIP_DF_DIV
= 0x002,
248 RECIP_V4SF_DIV
= 0x004,
249 RECIP_V2DF_DIV
= 0x008,
251 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT
= 0x020,
253 RECIP_V4SF_RSQRT
= 0x040,
254 RECIP_V2DF_RSQRT
= 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
262 RECIP_HIGH_PRECISION
= RECIP_ALL
,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
269 /* -mrecip options. */
272 const char *string
; /* option name */
273 unsigned int mask
; /* mask bits to set */
274 } recip_options
[] = {
275 { "all", RECIP_ALL
},
276 { "none", RECIP_NONE
},
277 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
280 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
281 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT
) },
283 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
284 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t
) (rtx
, rtx
, rtx
);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
296 /* Target cpu costs. */
298 struct processor_costs
{
299 const int mulsi
; /* cost of SImode multiplication. */
300 const int mulsi_const
; /* cost of SImode multiplication by constant. */
301 const int mulsi_const9
; /* cost of SImode mult by short constant. */
302 const int muldi
; /* cost of DImode multiplication. */
303 const int divsi
; /* cost of SImode division. */
304 const int divdi
; /* cost of DImode division. */
305 const int fp
; /* cost of simple SFmode and DFmode insns. */
306 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
307 const int sdiv
; /* cost of SFmode division (fdivs). */
308 const int ddiv
; /* cost of DFmode division (fdiv). */
309 const int cache_line_size
; /* cache line size in bytes. */
310 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
311 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
312 const int simultaneous_prefetches
; /* number of parallel prefetch
316 const struct processor_costs
*rs6000_cost
;
318 /* Processor costs (relative to an add) */
320 /* Instruction size costs on 32bit processors. */
322 struct processor_costs size32_cost
= {
323 COSTS_N_INSNS (1), /* mulsi */
324 COSTS_N_INSNS (1), /* mulsi_const */
325 COSTS_N_INSNS (1), /* mulsi_const9 */
326 COSTS_N_INSNS (1), /* muldi */
327 COSTS_N_INSNS (1), /* divsi */
328 COSTS_N_INSNS (1), /* divdi */
329 COSTS_N_INSNS (1), /* fp */
330 COSTS_N_INSNS (1), /* dmul */
331 COSTS_N_INSNS (1), /* sdiv */
332 COSTS_N_INSNS (1), /* ddiv */
339 /* Instruction size costs on 64bit processors. */
341 struct processor_costs size64_cost
= {
342 COSTS_N_INSNS (1), /* mulsi */
343 COSTS_N_INSNS (1), /* mulsi_const */
344 COSTS_N_INSNS (1), /* mulsi_const9 */
345 COSTS_N_INSNS (1), /* muldi */
346 COSTS_N_INSNS (1), /* divsi */
347 COSTS_N_INSNS (1), /* divdi */
348 COSTS_N_INSNS (1), /* fp */
349 COSTS_N_INSNS (1), /* dmul */
350 COSTS_N_INSNS (1), /* sdiv */
351 COSTS_N_INSNS (1), /* ddiv */
358 /* Instruction costs on RS64A processors. */
360 struct processor_costs rs64a_cost
= {
361 COSTS_N_INSNS (20), /* mulsi */
362 COSTS_N_INSNS (12), /* mulsi_const */
363 COSTS_N_INSNS (8), /* mulsi_const9 */
364 COSTS_N_INSNS (34), /* muldi */
365 COSTS_N_INSNS (65), /* divsi */
366 COSTS_N_INSNS (67), /* divdi */
367 COSTS_N_INSNS (4), /* fp */
368 COSTS_N_INSNS (4), /* dmul */
369 COSTS_N_INSNS (31), /* sdiv */
370 COSTS_N_INSNS (31), /* ddiv */
371 128, /* cache line size */
377 /* Instruction costs on MPCCORE processors. */
379 struct processor_costs mpccore_cost
= {
380 COSTS_N_INSNS (2), /* mulsi */
381 COSTS_N_INSNS (2), /* mulsi_const */
382 COSTS_N_INSNS (2), /* mulsi_const9 */
383 COSTS_N_INSNS (2), /* muldi */
384 COSTS_N_INSNS (6), /* divsi */
385 COSTS_N_INSNS (6), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (5), /* dmul */
388 COSTS_N_INSNS (10), /* sdiv */
389 COSTS_N_INSNS (17), /* ddiv */
390 32, /* cache line size */
396 /* Instruction costs on PPC403 processors. */
398 struct processor_costs ppc403_cost
= {
399 COSTS_N_INSNS (4), /* mulsi */
400 COSTS_N_INSNS (4), /* mulsi_const */
401 COSTS_N_INSNS (4), /* mulsi_const9 */
402 COSTS_N_INSNS (4), /* muldi */
403 COSTS_N_INSNS (33), /* divsi */
404 COSTS_N_INSNS (33), /* divdi */
405 COSTS_N_INSNS (11), /* fp */
406 COSTS_N_INSNS (11), /* dmul */
407 COSTS_N_INSNS (11), /* sdiv */
408 COSTS_N_INSNS (11), /* ddiv */
409 32, /* cache line size */
415 /* Instruction costs on PPC405 processors. */
417 struct processor_costs ppc405_cost
= {
418 COSTS_N_INSNS (5), /* mulsi */
419 COSTS_N_INSNS (4), /* mulsi_const */
420 COSTS_N_INSNS (3), /* mulsi_const9 */
421 COSTS_N_INSNS (5), /* muldi */
422 COSTS_N_INSNS (35), /* divsi */
423 COSTS_N_INSNS (35), /* divdi */
424 COSTS_N_INSNS (11), /* fp */
425 COSTS_N_INSNS (11), /* dmul */
426 COSTS_N_INSNS (11), /* sdiv */
427 COSTS_N_INSNS (11), /* ddiv */
428 32, /* cache line size */
434 /* Instruction costs on PPC440 processors. */
436 struct processor_costs ppc440_cost
= {
437 COSTS_N_INSNS (3), /* mulsi */
438 COSTS_N_INSNS (2), /* mulsi_const */
439 COSTS_N_INSNS (2), /* mulsi_const9 */
440 COSTS_N_INSNS (3), /* muldi */
441 COSTS_N_INSNS (34), /* divsi */
442 COSTS_N_INSNS (34), /* divdi */
443 COSTS_N_INSNS (5), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (19), /* sdiv */
446 COSTS_N_INSNS (33), /* ddiv */
447 32, /* cache line size */
453 /* Instruction costs on PPC476 processors. */
455 struct processor_costs ppc476_cost
= {
456 COSTS_N_INSNS (4), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (4), /* mulsi_const9 */
459 COSTS_N_INSNS (4), /* muldi */
460 COSTS_N_INSNS (11), /* divsi */
461 COSTS_N_INSNS (11), /* divdi */
462 COSTS_N_INSNS (6), /* fp */
463 COSTS_N_INSNS (6), /* dmul */
464 COSTS_N_INSNS (19), /* sdiv */
465 COSTS_N_INSNS (33), /* ddiv */
466 32, /* l1 cache line size */
472 /* Instruction costs on PPC601 processors. */
474 struct processor_costs ppc601_cost
= {
475 COSTS_N_INSNS (5), /* mulsi */
476 COSTS_N_INSNS (5), /* mulsi_const */
477 COSTS_N_INSNS (5), /* mulsi_const9 */
478 COSTS_N_INSNS (5), /* muldi */
479 COSTS_N_INSNS (36), /* divsi */
480 COSTS_N_INSNS (36), /* divdi */
481 COSTS_N_INSNS (4), /* fp */
482 COSTS_N_INSNS (5), /* dmul */
483 COSTS_N_INSNS (17), /* sdiv */
484 COSTS_N_INSNS (31), /* ddiv */
485 32, /* cache line size */
491 /* Instruction costs on PPC603 processors. */
493 struct processor_costs ppc603_cost
= {
494 COSTS_N_INSNS (5), /* mulsi */
495 COSTS_N_INSNS (3), /* mulsi_const */
496 COSTS_N_INSNS (2), /* mulsi_const9 */
497 COSTS_N_INSNS (5), /* muldi */
498 COSTS_N_INSNS (37), /* divsi */
499 COSTS_N_INSNS (37), /* divdi */
500 COSTS_N_INSNS (3), /* fp */
501 COSTS_N_INSNS (4), /* dmul */
502 COSTS_N_INSNS (18), /* sdiv */
503 COSTS_N_INSNS (33), /* ddiv */
504 32, /* cache line size */
510 /* Instruction costs on PPC604 processors. */
512 struct processor_costs ppc604_cost
= {
513 COSTS_N_INSNS (4), /* mulsi */
514 COSTS_N_INSNS (4), /* mulsi_const */
515 COSTS_N_INSNS (4), /* mulsi_const9 */
516 COSTS_N_INSNS (4), /* muldi */
517 COSTS_N_INSNS (20), /* divsi */
518 COSTS_N_INSNS (20), /* divdi */
519 COSTS_N_INSNS (3), /* fp */
520 COSTS_N_INSNS (3), /* dmul */
521 COSTS_N_INSNS (18), /* sdiv */
522 COSTS_N_INSNS (32), /* ddiv */
523 32, /* cache line size */
529 /* Instruction costs on PPC604e processors. */
531 struct processor_costs ppc604e_cost
= {
532 COSTS_N_INSNS (2), /* mulsi */
533 COSTS_N_INSNS (2), /* mulsi_const */
534 COSTS_N_INSNS (2), /* mulsi_const9 */
535 COSTS_N_INSNS (2), /* muldi */
536 COSTS_N_INSNS (20), /* divsi */
537 COSTS_N_INSNS (20), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (18), /* sdiv */
541 COSTS_N_INSNS (32), /* ddiv */
542 32, /* cache line size */
548 /* Instruction costs on PPC620 processors. */
550 struct processor_costs ppc620_cost
= {
551 COSTS_N_INSNS (5), /* mulsi */
552 COSTS_N_INSNS (4), /* mulsi_const */
553 COSTS_N_INSNS (3), /* mulsi_const9 */
554 COSTS_N_INSNS (7), /* muldi */
555 COSTS_N_INSNS (21), /* divsi */
556 COSTS_N_INSNS (37), /* divdi */
557 COSTS_N_INSNS (3), /* fp */
558 COSTS_N_INSNS (3), /* dmul */
559 COSTS_N_INSNS (18), /* sdiv */
560 COSTS_N_INSNS (32), /* ddiv */
561 128, /* cache line size */
567 /* Instruction costs on PPC630 processors. */
569 struct processor_costs ppc630_cost
= {
570 COSTS_N_INSNS (5), /* mulsi */
571 COSTS_N_INSNS (4), /* mulsi_const */
572 COSTS_N_INSNS (3), /* mulsi_const9 */
573 COSTS_N_INSNS (7), /* muldi */
574 COSTS_N_INSNS (21), /* divsi */
575 COSTS_N_INSNS (37), /* divdi */
576 COSTS_N_INSNS (3), /* fp */
577 COSTS_N_INSNS (3), /* dmul */
578 COSTS_N_INSNS (17), /* sdiv */
579 COSTS_N_INSNS (21), /* ddiv */
580 128, /* cache line size */
586 /* Instruction costs on Cell processor. */
587 /* COSTS_N_INSNS (1) ~ one add. */
589 struct processor_costs ppccell_cost
= {
590 COSTS_N_INSNS (9/2)+2, /* mulsi */
591 COSTS_N_INSNS (6/2), /* mulsi_const */
592 COSTS_N_INSNS (6/2), /* mulsi_const9 */
593 COSTS_N_INSNS (15/2)+2, /* muldi */
594 COSTS_N_INSNS (38/2), /* divsi */
595 COSTS_N_INSNS (70/2), /* divdi */
596 COSTS_N_INSNS (10/2), /* fp */
597 COSTS_N_INSNS (10/2), /* dmul */
598 COSTS_N_INSNS (74/2), /* sdiv */
599 COSTS_N_INSNS (74/2), /* ddiv */
600 128, /* cache line size */
606 /* Instruction costs on PPC750 and PPC7400 processors. */
608 struct processor_costs ppc750_cost
= {
609 COSTS_N_INSNS (5), /* mulsi */
610 COSTS_N_INSNS (3), /* mulsi_const */
611 COSTS_N_INSNS (2), /* mulsi_const9 */
612 COSTS_N_INSNS (5), /* muldi */
613 COSTS_N_INSNS (17), /* divsi */
614 COSTS_N_INSNS (17), /* divdi */
615 COSTS_N_INSNS (3), /* fp */
616 COSTS_N_INSNS (3), /* dmul */
617 COSTS_N_INSNS (17), /* sdiv */
618 COSTS_N_INSNS (31), /* ddiv */
619 32, /* cache line size */
625 /* Instruction costs on PPC7450 processors. */
627 struct processor_costs ppc7450_cost
= {
628 COSTS_N_INSNS (4), /* mulsi */
629 COSTS_N_INSNS (3), /* mulsi_const */
630 COSTS_N_INSNS (3), /* mulsi_const9 */
631 COSTS_N_INSNS (4), /* muldi */
632 COSTS_N_INSNS (23), /* divsi */
633 COSTS_N_INSNS (23), /* divdi */
634 COSTS_N_INSNS (5), /* fp */
635 COSTS_N_INSNS (5), /* dmul */
636 COSTS_N_INSNS (21), /* sdiv */
637 COSTS_N_INSNS (35), /* ddiv */
638 32, /* cache line size */
644 /* Instruction costs on PPC8540 processors. */
646 struct processor_costs ppc8540_cost
= {
647 COSTS_N_INSNS (4), /* mulsi */
648 COSTS_N_INSNS (4), /* mulsi_const */
649 COSTS_N_INSNS (4), /* mulsi_const9 */
650 COSTS_N_INSNS (4), /* muldi */
651 COSTS_N_INSNS (19), /* divsi */
652 COSTS_N_INSNS (19), /* divdi */
653 COSTS_N_INSNS (4), /* fp */
654 COSTS_N_INSNS (4), /* dmul */
655 COSTS_N_INSNS (29), /* sdiv */
656 COSTS_N_INSNS (29), /* ddiv */
657 32, /* cache line size */
660 1, /* prefetch streams /*/
663 /* Instruction costs on E300C2 and E300C3 cores. */
665 struct processor_costs ppce300c2c3_cost
= {
666 COSTS_N_INSNS (4), /* mulsi */
667 COSTS_N_INSNS (4), /* mulsi_const */
668 COSTS_N_INSNS (4), /* mulsi_const9 */
669 COSTS_N_INSNS (4), /* muldi */
670 COSTS_N_INSNS (19), /* divsi */
671 COSTS_N_INSNS (19), /* divdi */
672 COSTS_N_INSNS (3), /* fp */
673 COSTS_N_INSNS (4), /* dmul */
674 COSTS_N_INSNS (18), /* sdiv */
675 COSTS_N_INSNS (33), /* ddiv */
679 1, /* prefetch streams /*/
682 /* Instruction costs on PPCE500MC processors. */
684 struct processor_costs ppce500mc_cost
= {
685 COSTS_N_INSNS (4), /* mulsi */
686 COSTS_N_INSNS (4), /* mulsi_const */
687 COSTS_N_INSNS (4), /* mulsi_const9 */
688 COSTS_N_INSNS (4), /* muldi */
689 COSTS_N_INSNS (14), /* divsi */
690 COSTS_N_INSNS (14), /* divdi */
691 COSTS_N_INSNS (8), /* fp */
692 COSTS_N_INSNS (10), /* dmul */
693 COSTS_N_INSNS (36), /* sdiv */
694 COSTS_N_INSNS (66), /* ddiv */
695 64, /* cache line size */
698 1, /* prefetch streams /*/
701 /* Instruction costs on PPCE500MC64 processors. */
703 struct processor_costs ppce500mc64_cost
= {
704 COSTS_N_INSNS (4), /* mulsi */
705 COSTS_N_INSNS (4), /* mulsi_const */
706 COSTS_N_INSNS (4), /* mulsi_const9 */
707 COSTS_N_INSNS (4), /* muldi */
708 COSTS_N_INSNS (14), /* divsi */
709 COSTS_N_INSNS (14), /* divdi */
710 COSTS_N_INSNS (4), /* fp */
711 COSTS_N_INSNS (10), /* dmul */
712 COSTS_N_INSNS (36), /* sdiv */
713 COSTS_N_INSNS (66), /* ddiv */
714 64, /* cache line size */
717 1, /* prefetch streams /*/
720 /* Instruction costs on PPCE5500 processors. */
722 struct processor_costs ppce5500_cost
= {
723 COSTS_N_INSNS (5), /* mulsi */
724 COSTS_N_INSNS (5), /* mulsi_const */
725 COSTS_N_INSNS (4), /* mulsi_const9 */
726 COSTS_N_INSNS (5), /* muldi */
727 COSTS_N_INSNS (14), /* divsi */
728 COSTS_N_INSNS (14), /* divdi */
729 COSTS_N_INSNS (7), /* fp */
730 COSTS_N_INSNS (10), /* dmul */
731 COSTS_N_INSNS (36), /* sdiv */
732 COSTS_N_INSNS (66), /* ddiv */
733 64, /* cache line size */
736 1, /* prefetch streams /*/
739 /* Instruction costs on PPCE6500 processors. */
741 struct processor_costs ppce6500_cost
= {
742 COSTS_N_INSNS (5), /* mulsi */
743 COSTS_N_INSNS (5), /* mulsi_const */
744 COSTS_N_INSNS (4), /* mulsi_const9 */
745 COSTS_N_INSNS (5), /* muldi */
746 COSTS_N_INSNS (14), /* divsi */
747 COSTS_N_INSNS (14), /* divdi */
748 COSTS_N_INSNS (7), /* fp */
749 COSTS_N_INSNS (10), /* dmul */
750 COSTS_N_INSNS (36), /* sdiv */
751 COSTS_N_INSNS (66), /* ddiv */
752 64, /* cache line size */
755 1, /* prefetch streams /*/
758 /* Instruction costs on AppliedMicro Titan processors. */
760 struct processor_costs titan_cost
= {
761 COSTS_N_INSNS (5), /* mulsi */
762 COSTS_N_INSNS (5), /* mulsi_const */
763 COSTS_N_INSNS (5), /* mulsi_const9 */
764 COSTS_N_INSNS (5), /* muldi */
765 COSTS_N_INSNS (18), /* divsi */
766 COSTS_N_INSNS (18), /* divdi */
767 COSTS_N_INSNS (10), /* fp */
768 COSTS_N_INSNS (10), /* dmul */
769 COSTS_N_INSNS (46), /* sdiv */
770 COSTS_N_INSNS (72), /* ddiv */
771 32, /* cache line size */
774 1, /* prefetch streams /*/
777 /* Instruction costs on POWER4 and POWER5 processors. */
779 struct processor_costs power4_cost
= {
780 COSTS_N_INSNS (3), /* mulsi */
781 COSTS_N_INSNS (2), /* mulsi_const */
782 COSTS_N_INSNS (2), /* mulsi_const9 */
783 COSTS_N_INSNS (4), /* muldi */
784 COSTS_N_INSNS (18), /* divsi */
785 COSTS_N_INSNS (34), /* divdi */
786 COSTS_N_INSNS (3), /* fp */
787 COSTS_N_INSNS (3), /* dmul */
788 COSTS_N_INSNS (17), /* sdiv */
789 COSTS_N_INSNS (17), /* ddiv */
790 128, /* cache line size */
793 8, /* prefetch streams /*/
796 /* Instruction costs on POWER6 processors. */
798 struct processor_costs power6_cost
= {
799 COSTS_N_INSNS (8), /* mulsi */
800 COSTS_N_INSNS (8), /* mulsi_const */
801 COSTS_N_INSNS (8), /* mulsi_const9 */
802 COSTS_N_INSNS (8), /* muldi */
803 COSTS_N_INSNS (22), /* divsi */
804 COSTS_N_INSNS (28), /* divdi */
805 COSTS_N_INSNS (3), /* fp */
806 COSTS_N_INSNS (3), /* dmul */
807 COSTS_N_INSNS (13), /* sdiv */
808 COSTS_N_INSNS (16), /* ddiv */
809 128, /* cache line size */
812 16, /* prefetch streams */
815 /* Instruction costs on POWER7 processors. */
817 struct processor_costs power7_cost
= {
818 COSTS_N_INSNS (2), /* mulsi */
819 COSTS_N_INSNS (2), /* mulsi_const */
820 COSTS_N_INSNS (2), /* mulsi_const9 */
821 COSTS_N_INSNS (2), /* muldi */
822 COSTS_N_INSNS (18), /* divsi */
823 COSTS_N_INSNS (34), /* divdi */
824 COSTS_N_INSNS (3), /* fp */
825 COSTS_N_INSNS (3), /* dmul */
826 COSTS_N_INSNS (13), /* sdiv */
827 COSTS_N_INSNS (16), /* ddiv */
828 128, /* cache line size */
831 12, /* prefetch streams */
834 /* Instruction costs on POWER A2 processors. */
836 struct processor_costs ppca2_cost
= {
837 COSTS_N_INSNS (16), /* mulsi */
838 COSTS_N_INSNS (16), /* mulsi_const */
839 COSTS_N_INSNS (16), /* mulsi_const9 */
840 COSTS_N_INSNS (16), /* muldi */
841 COSTS_N_INSNS (22), /* divsi */
842 COSTS_N_INSNS (28), /* divdi */
843 COSTS_N_INSNS (3), /* fp */
844 COSTS_N_INSNS (3), /* dmul */
845 COSTS_N_INSNS (59), /* sdiv */
846 COSTS_N_INSNS (72), /* ddiv */
850 16, /* prefetch streams */
854 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
855 #undef RS6000_BUILTIN_1
856 #undef RS6000_BUILTIN_2
857 #undef RS6000_BUILTIN_3
858 #undef RS6000_BUILTIN_A
859 #undef RS6000_BUILTIN_D
860 #undef RS6000_BUILTIN_E
861 #undef RS6000_BUILTIN_P
862 #undef RS6000_BUILTIN_Q
863 #undef RS6000_BUILTIN_S
864 #undef RS6000_BUILTIN_X
866 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
867 { NAME, ICODE, MASK, ATTR },
869 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
870 { NAME, ICODE, MASK, ATTR },
872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
873 { NAME, ICODE, MASK, ATTR },
875 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
876 { NAME, ICODE, MASK, ATTR },
878 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
879 { NAME, ICODE, MASK, ATTR },
881 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
882 { NAME, ICODE, MASK, ATTR },
884 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
885 { NAME, ICODE, MASK, ATTR },
887 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
888 { NAME, ICODE, MASK, ATTR },
890 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
891 { NAME, ICODE, MASK, ATTR },
893 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
894 { NAME, ICODE, MASK, ATTR },
896 struct rs6000_builtin_info_type
{
898 const enum insn_code icode
;
899 const HOST_WIDE_INT mask
;
903 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
905 #include "rs6000-builtin.def"
908 #undef RS6000_BUILTIN_1
909 #undef RS6000_BUILTIN_2
910 #undef RS6000_BUILTIN_3
911 #undef RS6000_BUILTIN_A
912 #undef RS6000_BUILTIN_D
913 #undef RS6000_BUILTIN_E
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
919 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
920 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
923 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
924 static bool spe_func_has_64bit_regs_p (void);
925 static struct machine_function
* rs6000_init_machine_status (void);
926 static int rs6000_ra_ever_killed (void);
927 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
928 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
929 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
930 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
931 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
932 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
933 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
934 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
936 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
937 static bool is_microcoded_insn (rtx
);
938 static bool is_nonpipeline_insn (rtx
);
939 static bool is_cracked_insn (rtx
);
940 static bool is_load_insn (rtx
, rtx
*);
941 static bool is_store_insn (rtx
, rtx
*);
942 static bool set_to_load_agen (rtx
,rtx
);
943 static bool insn_terminates_group_p (rtx
, enum group_termination
);
944 static bool insn_must_be_first_in_group (rtx
);
945 static bool insn_must_be_last_in_group (rtx
);
946 static void altivec_init_builtins (void);
947 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
948 enum machine_mode
, enum machine_mode
,
949 enum rs6000_builtins
, const char *name
);
950 static void rs6000_common_init_builtins (void);
951 static void paired_init_builtins (void);
952 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
953 static void spe_init_builtins (void);
954 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
955 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
956 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
957 static rs6000_stack_t
*rs6000_stack_info (void);
958 static void is_altivec_return_reg (rtx
, void *);
959 int easy_vector_constant (rtx
, enum machine_mode
);
960 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
961 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
962 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
963 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
964 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
967 static void macho_branch_islands (void);
969 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
971 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
973 static bool rs6000_mode_dependent_address (const_rtx
);
974 static bool rs6000_debug_mode_dependent_address (const_rtx
);
975 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
976 enum machine_mode
, rtx
);
977 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
980 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
981 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
983 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
985 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
988 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
991 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
994 static bool rs6000_save_toc_in_prologue_p (void);
996 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
998 = rs6000_legitimize_reload_address
;
1000 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1001 = rs6000_mode_dependent_address
;
1003 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1004 enum machine_mode
, rtx
)
1005 = rs6000_secondary_reload_class
;
1007 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1008 = rs6000_preferred_reload_class
;
1010 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1012 = rs6000_secondary_memory_needed
;
1014 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1017 = rs6000_cannot_change_mode_class
;
1019 const int INSN_NOT_AVAILABLE
= -1;
1021 static void rs6000_print_isa_options (FILE *, int, const char *,
1023 static void rs6000_print_builtin_options (FILE *, int, const char *,
1026 /* Hash table stuff for keeping track of TOC entries. */
1028 struct GTY(()) toc_hash_struct
1030 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1031 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1033 enum machine_mode key_mode
;
1037 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1039 /* Hash table to keep track of the argument types for builtin functions. */
1041 struct GTY(()) builtin_hash_struct
1044 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1045 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1048 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1051 /* Default register names. */
1052 char rs6000_reg_names
[][8] =
1054 "0", "1", "2", "3", "4", "5", "6", "7",
1055 "8", "9", "10", "11", "12", "13", "14", "15",
1056 "16", "17", "18", "19", "20", "21", "22", "23",
1057 "24", "25", "26", "27", "28", "29", "30", "31",
1058 "0", "1", "2", "3", "4", "5", "6", "7",
1059 "8", "9", "10", "11", "12", "13", "14", "15",
1060 "16", "17", "18", "19", "20", "21", "22", "23",
1061 "24", "25", "26", "27", "28", "29", "30", "31",
1062 "mq", "lr", "ctr","ap",
1063 "0", "1", "2", "3", "4", "5", "6", "7",
1065 /* AltiVec registers. */
1066 "0", "1", "2", "3", "4", "5", "6", "7",
1067 "8", "9", "10", "11", "12", "13", "14", "15",
1068 "16", "17", "18", "19", "20", "21", "22", "23",
1069 "24", "25", "26", "27", "28", "29", "30", "31",
1071 /* SPE registers. */
1072 "spe_acc", "spefscr",
1073 /* Soft frame pointer. */
1077 #ifdef TARGET_REGNAMES
1078 static const char alt_reg_names
[][8] =
1080 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1081 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1082 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1083 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1084 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1085 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1086 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1087 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1088 "mq", "lr", "ctr", "ap",
1089 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1091 /* AltiVec registers. */
1092 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1093 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1094 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1095 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1097 /* SPE registers. */
1098 "spe_acc", "spefscr",
1099 /* Soft frame pointer. */
1104 /* Table of valid machine attributes. */
1106 static const struct attribute_spec rs6000_attribute_table
[] =
1108 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1109 affects_type_identity } */
1110 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1112 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1114 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1116 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1118 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1120 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1121 SUBTARGET_ATTRIBUTE_TABLE
,
1123 { NULL
, 0, 0, false, false, false, NULL
, false }
1126 #ifndef TARGET_PROFILE_KERNEL
1127 #define TARGET_PROFILE_KERNEL 0
1130 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1131 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1133 /* Initialize the GCC target structure. */
1134 #undef TARGET_ATTRIBUTE_TABLE
1135 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1136 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1137 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1138 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1139 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1141 #undef TARGET_ASM_ALIGNED_DI_OP
1142 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1144 /* Default unaligned ops are only provided for ELF. Find the ops needed
1145 for non-ELF systems. */
1146 #ifndef OBJECT_FORMAT_ELF
1148 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1150 #undef TARGET_ASM_UNALIGNED_HI_OP
1151 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1152 #undef TARGET_ASM_UNALIGNED_SI_OP
1153 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1154 #undef TARGET_ASM_UNALIGNED_DI_OP
1155 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1158 #undef TARGET_ASM_UNALIGNED_HI_OP
1159 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1160 #undef TARGET_ASM_UNALIGNED_SI_OP
1161 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1162 #undef TARGET_ASM_UNALIGNED_DI_OP
1163 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1164 #undef TARGET_ASM_ALIGNED_DI_OP
1165 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1169 /* This hook deals with fixups for relocatable code and DI-mode objects
1171 #undef TARGET_ASM_INTEGER
1172 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1174 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1175 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1176 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1179 #undef TARGET_SET_UP_BY_PROLOGUE
1180 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1182 #undef TARGET_HAVE_TLS
1183 #define TARGET_HAVE_TLS HAVE_AS_TLS
1185 #undef TARGET_CANNOT_FORCE_CONST_MEM
1186 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1188 #undef TARGET_DELEGITIMIZE_ADDRESS
1189 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1191 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1192 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1194 #undef TARGET_ASM_FUNCTION_PROLOGUE
1195 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1196 #undef TARGET_ASM_FUNCTION_EPILOGUE
1197 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1199 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1200 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1202 #undef TARGET_LEGITIMIZE_ADDRESS
1203 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1205 #undef TARGET_SCHED_VARIABLE_ISSUE
1206 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1208 #undef TARGET_SCHED_ISSUE_RATE
1209 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1210 #undef TARGET_SCHED_ADJUST_COST
1211 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1212 #undef TARGET_SCHED_ADJUST_PRIORITY
1213 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1214 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1215 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1216 #undef TARGET_SCHED_INIT
1217 #define TARGET_SCHED_INIT rs6000_sched_init
1218 #undef TARGET_SCHED_FINISH
1219 #define TARGET_SCHED_FINISH rs6000_sched_finish
1220 #undef TARGET_SCHED_REORDER
1221 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1222 #undef TARGET_SCHED_REORDER2
1223 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1225 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1226 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1228 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1229 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1231 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1232 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1233 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1234 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1235 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1236 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1237 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1238 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1240 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1241 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1242 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1243 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1244 rs6000_builtin_support_vector_misalignment
1245 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1246 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1247 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1248 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1249 rs6000_builtin_vectorization_cost
1250 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1251 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1252 rs6000_preferred_simd_mode
1253 #undef TARGET_VECTORIZE_INIT_COST
1254 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1255 #undef TARGET_VECTORIZE_ADD_STMT_COST
1256 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1257 #undef TARGET_VECTORIZE_FINISH_COST
1258 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1259 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1260 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1262 #undef TARGET_INIT_BUILTINS
1263 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1264 #undef TARGET_BUILTIN_DECL
1265 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1267 #undef TARGET_EXPAND_BUILTIN
1268 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1270 #undef TARGET_MANGLE_TYPE
1271 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1273 #undef TARGET_INIT_LIBFUNCS
1274 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1277 #undef TARGET_BINDS_LOCAL_P
1278 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1281 #undef TARGET_MS_BITFIELD_LAYOUT_P
1282 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1284 #undef TARGET_ASM_OUTPUT_MI_THUNK
1285 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1287 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1288 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1290 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1291 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1293 #undef TARGET_INVALID_WITHIN_DOLOOP
1294 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1296 #undef TARGET_REGISTER_MOVE_COST
1297 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1298 #undef TARGET_MEMORY_MOVE_COST
1299 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1300 #undef TARGET_RTX_COSTS
1301 #define TARGET_RTX_COSTS rs6000_rtx_costs
1302 #undef TARGET_ADDRESS_COST
1303 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1305 #undef TARGET_DWARF_REGISTER_SPAN
1306 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1308 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1309 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1311 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1312 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1314 /* On rs6000, function arguments are promoted, as are function return
1316 #undef TARGET_PROMOTE_FUNCTION_MODE
1317 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1319 #undef TARGET_RETURN_IN_MEMORY
1320 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1322 #undef TARGET_SETUP_INCOMING_VARARGS
1323 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1325 /* Always strict argument naming on rs6000. */
1326 #undef TARGET_STRICT_ARGUMENT_NAMING
1327 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1328 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1329 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1330 #undef TARGET_SPLIT_COMPLEX_ARG
1331 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1332 #undef TARGET_MUST_PASS_IN_STACK
1333 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1334 #undef TARGET_PASS_BY_REFERENCE
1335 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1336 #undef TARGET_ARG_PARTIAL_BYTES
1337 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1338 #undef TARGET_FUNCTION_ARG_ADVANCE
1339 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1340 #undef TARGET_FUNCTION_ARG
1341 #define TARGET_FUNCTION_ARG rs6000_function_arg
1342 #undef TARGET_FUNCTION_ARG_BOUNDARY
1343 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1345 #undef TARGET_BUILD_BUILTIN_VA_LIST
1346 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1348 #undef TARGET_EXPAND_BUILTIN_VA_START
1349 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1351 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1352 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1354 #undef TARGET_EH_RETURN_FILTER_MODE
1355 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1357 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1358 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1360 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1361 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1363 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1364 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1366 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1367 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1369 #undef TARGET_OPTION_OVERRIDE
1370 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1372 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1373 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1374 rs6000_builtin_vectorized_function
1377 #undef TARGET_STACK_PROTECT_FAIL
1378 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1381 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1382 The PowerPC architecture requires only weak consistency among
1383 processors--that is, memory accesses between processors need not be
1384 sequentially consistent and memory accesses among processors can occur
1385 in any order. The ability to order memory accesses weakly provides
1386 opportunities for more efficient use of the system bus. Unless a
1387 dependency exists, the 604e allows read operations to precede store
1389 #undef TARGET_RELAXED_ORDERING
1390 #define TARGET_RELAXED_ORDERING true
1393 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1394 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1397 /* Use a 32-bit anchor range. This leads to sequences like:
1399 addis tmp,anchor,high
1402 where tmp itself acts as an anchor, and can be shared between
1403 accesses to the same 64k page. */
1404 #undef TARGET_MIN_ANCHOR_OFFSET
1405 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1406 #undef TARGET_MAX_ANCHOR_OFFSET
1407 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1408 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1409 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1410 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1411 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1413 #undef TARGET_BUILTIN_RECIPROCAL
1414 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1416 #undef TARGET_EXPAND_TO_RTL_HOOK
1417 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1419 #undef TARGET_INSTANTIATE_DECLS
1420 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1422 #undef TARGET_SECONDARY_RELOAD
1423 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1425 #undef TARGET_LEGITIMATE_ADDRESS_P
1426 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1428 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1429 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1431 #undef TARGET_CAN_ELIMINATE
1432 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1434 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1435 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1437 #undef TARGET_TRAMPOLINE_INIT
1438 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1440 #undef TARGET_FUNCTION_VALUE
1441 #define TARGET_FUNCTION_VALUE rs6000_function_value
1443 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1444 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1446 #undef TARGET_OPTION_SAVE
1447 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1449 #undef TARGET_OPTION_RESTORE
1450 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1452 #undef TARGET_OPTION_PRINT
1453 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1455 #undef TARGET_CAN_INLINE_P
1456 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1458 #undef TARGET_SET_CURRENT_FUNCTION
1459 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1461 #undef TARGET_LEGITIMATE_CONSTANT_P
1462 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1464 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1465 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1468 /* Processor table. */
1471 const char *const name
; /* Canonical processor name. */
1472 const enum processor_type processor
; /* Processor type enum value. */
1473 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1476 static struct rs6000_ptt
const processor_target_table
[] =
1478 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1479 #include "rs6000-cpus.def"
1483 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1487 rs6000_cpu_name_lookup (const char *name
)
1493 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1494 if (! strcmp (name
, processor_target_table
[i
].name
))
1502 /* Return number of consecutive hard regs needed starting at reg REGNO
1503 to hold something of mode MODE.
1504 This is ordinarily the length in words of a value of mode MODE
1505 but can be less for certain modes in special long registers.
1507 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1508 scalar instructions. The upper 32 bits are only available to the
1511 POWER and PowerPC GPRs hold 32 bits worth;
1512 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1515 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1517 unsigned HOST_WIDE_INT reg_size
;
1519 if (FP_REGNO_P (regno
))
1520 reg_size
= (VECTOR_MEM_VSX_P (mode
)
1521 ? UNITS_PER_VSX_WORD
1522 : UNITS_PER_FP_WORD
);
1524 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1525 reg_size
= UNITS_PER_SPE_WORD
;
1527 else if (ALTIVEC_REGNO_P (regno
))
1528 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1530 /* The value returned for SCmode in the E500 double case is 2 for
1531 ABI compatibility; storing an SCmode value in a single register
1532 would require function_arg and rs6000_spe_function_arg to handle
1533 SCmode so as to pass the value correctly in a pair of
1535 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1536 && !DECIMAL_FLOAT_MODE_P (mode
))
1537 reg_size
= UNITS_PER_FP_WORD
;
1540 reg_size
= UNITS_PER_WORD
;
1542 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1545 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1548 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1550 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1552 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1553 implementations. Don't allow an item to be split between a FP register
1554 and an Altivec register. */
1555 if (VECTOR_MEM_VSX_P (mode
))
1557 if (FP_REGNO_P (regno
))
1558 return FP_REGNO_P (last_regno
);
1560 if (ALTIVEC_REGNO_P (regno
))
1561 return ALTIVEC_REGNO_P (last_regno
);
1564 /* The GPRs can hold any mode, but values bigger than one register
1565 cannot go past R31. */
1566 if (INT_REGNO_P (regno
))
1567 return INT_REGNO_P (last_regno
);
1569 /* The float registers (except for VSX vector modes) can only hold floating
1570 modes and DImode. This excludes the 32-bit decimal float mode for
1572 if (FP_REGNO_P (regno
))
1574 if (SCALAR_FLOAT_MODE_P (mode
)
1575 && (mode
!= TDmode
|| (regno
% 2) == 0)
1576 && FP_REGNO_P (last_regno
))
1579 if (GET_MODE_CLASS (mode
) == MODE_INT
1580 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1583 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1584 && PAIRED_VECTOR_MODE (mode
))
1590 /* The CR register can only hold CC modes. */
1591 if (CR_REGNO_P (regno
))
1592 return GET_MODE_CLASS (mode
) == MODE_CC
;
1594 if (CA_REGNO_P (regno
))
1595 return mode
== BImode
;
1597 /* AltiVec only in AldyVec registers. */
1598 if (ALTIVEC_REGNO_P (regno
))
1599 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1601 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1602 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1605 /* We cannot put TImode anywhere except general register and it must be able
1606 to fit within the register set. In the future, allow TImode in the
1607 Altivec or VSX registers. */
1609 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1612 /* Print interesting facts about registers. */
1614 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1618 for (r
= first_regno
; r
<= last_regno
; ++r
)
1620 const char *comma
= "";
1623 if (first_regno
== last_regno
)
1624 fprintf (stderr
, "%s:\t", reg_name
);
1626 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1629 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1630 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1634 fprintf (stderr
, ",\n\t");
1639 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1640 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1641 rs6000_hard_regno_nregs
[m
][r
]);
1643 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1648 if (call_used_regs
[r
])
1652 fprintf (stderr
, ",\n\t");
1657 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1665 fprintf (stderr
, ",\n\t");
1670 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1676 fprintf (stderr
, ",\n\t");
1680 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1684 #define DEBUG_FMT_ID "%-32s= "
1685 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1686 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1687 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1689 /* Print various interesting information with -mdebug=reg. */
1691 rs6000_debug_reg_global (void)
1693 static const char *const tf
[2] = { "false", "true" };
1694 const char *nl
= (const char *)0;
1696 char costly_num
[20];
1698 char flags_buffer
[40];
1699 const char *costly_str
;
1700 const char *nop_str
;
1701 const char *trace_str
;
1702 const char *abi_str
;
1703 const char *cmodel_str
;
1704 struct cl_target_option cl_opts
;
1706 /* Map enum rs6000_vector to string. */
1707 static const char *rs6000_debug_vector_unit
[] = {
1716 fprintf (stderr
, "Register information: (last virtual reg = %d)\n",
1717 LAST_VIRTUAL_REGISTER
);
1718 rs6000_debug_reg_print (0, 31, "gr");
1719 rs6000_debug_reg_print (32, 63, "fp");
1720 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
1723 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
1724 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
1725 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
1726 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
1727 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
1728 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
1729 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
1730 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
1734 "d reg_class = %s\n"
1735 "f reg_class = %s\n"
1736 "v reg_class = %s\n"
1737 "wa reg_class = %s\n"
1738 "wd reg_class = %s\n"
1739 "wf reg_class = %s\n"
1740 "ws reg_class = %s\n\n",
1741 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
1742 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
1743 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
1744 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
1745 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
1746 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
1747 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]]);
1749 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1750 if (rs6000_vector_unit
[m
] || rs6000_vector_mem
[m
])
1753 fprintf (stderr
, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1755 rs6000_debug_vector_unit
[ rs6000_vector_unit
[m
] ],
1756 rs6000_debug_vector_unit
[ rs6000_vector_mem
[m
] ]);
1762 if (rs6000_recip_control
)
1764 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
1766 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1767 if (rs6000_recip_bits
[m
])
1770 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1772 (RS6000_RECIP_AUTO_RE_P (m
)
1774 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
1775 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
1777 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
1780 fputs ("\n", stderr
);
1783 if (rs6000_cpu_index
>= 0)
1785 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
1787 = processor_target_table
[rs6000_cpu_index
].target_enable
;
1789 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
1790 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1793 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
1795 if (rs6000_tune_index
>= 0)
1797 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
1799 = processor_target_table
[rs6000_tune_index
].target_enable
;
1801 sprintf (flags_buffer
, "-mtune=%s flags", name
);
1802 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1805 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
1807 cl_target_option_save (&cl_opts
, &global_options
);
1808 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
1811 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
1812 rs6000_isa_flags_explicit
);
1814 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
1815 rs6000_builtin_mask
);
1817 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
1819 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
1820 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
1822 switch (rs6000_sched_costly_dep
)
1824 case max_dep_latency
:
1825 costly_str
= "max_dep_latency";
1829 costly_str
= "no_dep_costly";
1832 case all_deps_costly
:
1833 costly_str
= "all_deps_costly";
1836 case true_store_to_load_dep_costly
:
1837 costly_str
= "true_store_to_load_dep_costly";
1840 case store_to_load_dep_costly
:
1841 costly_str
= "store_to_load_dep_costly";
1845 costly_str
= costly_num
;
1846 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
1850 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
1852 switch (rs6000_sched_insert_nops
)
1854 case sched_finish_regroup_exact
:
1855 nop_str
= "sched_finish_regroup_exact";
1858 case sched_finish_pad_groups
:
1859 nop_str
= "sched_finish_pad_groups";
1862 case sched_finish_none
:
1863 nop_str
= "sched_finish_none";
1868 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
1872 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
1874 switch (rs6000_sdata
)
1881 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
1885 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
1889 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
1894 switch (rs6000_traceback
)
1896 case traceback_default
: trace_str
= "default"; break;
1897 case traceback_none
: trace_str
= "none"; break;
1898 case traceback_part
: trace_str
= "part"; break;
1899 case traceback_full
: trace_str
= "full"; break;
1900 default: trace_str
= "unknown"; break;
1903 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
1905 switch (rs6000_current_cmodel
)
1907 case CMODEL_SMALL
: cmodel_str
= "small"; break;
1908 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
1909 case CMODEL_LARGE
: cmodel_str
= "large"; break;
1910 default: cmodel_str
= "unknown"; break;
1913 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
1915 switch (rs6000_current_abi
)
1917 case ABI_NONE
: abi_str
= "none"; break;
1918 case ABI_AIX
: abi_str
= "aix"; break;
1919 case ABI_V4
: abi_str
= "V4"; break;
1920 case ABI_DARWIN
: abi_str
= "darwin"; break;
1921 default: abi_str
= "unknown"; break;
1924 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
1926 if (rs6000_altivec_abi
)
1927 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
1930 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
1932 if (rs6000_darwin64_abi
)
1933 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
1935 if (rs6000_float_gprs
)
1936 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
1938 if (TARGET_LINK_STACK
)
1939 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
1941 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
1942 TARGET_SECURE_PLT
? "secure" : "bss");
1943 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
1944 aix_struct_return
? "aix" : "sysv");
1945 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
1946 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
1947 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
1948 tf
[!!rs6000_align_branch_targets
]);
1949 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
1950 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
1951 rs6000_long_double_type_size
);
1952 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
1953 (int)rs6000_sched_restricted_insns_priority
);
1954 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
1956 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
1957 (int)RS6000_BUILTIN_COUNT
);
1960 /* Initialize the various global tables that are based on register size. */
1962 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
1968 /* Precalculate REGNO_REG_CLASS. */
1969 rs6000_regno_regclass
[0] = GENERAL_REGS
;
1970 for (r
= 1; r
< 32; ++r
)
1971 rs6000_regno_regclass
[r
] = BASE_REGS
;
1973 for (r
= 32; r
< 64; ++r
)
1974 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
1976 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1977 rs6000_regno_regclass
[r
] = NO_REGS
;
1979 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
1980 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
1982 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
1983 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
1984 rs6000_regno_regclass
[r
] = CR_REGS
;
1986 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
1987 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
1988 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
1989 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
1990 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
1991 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
1992 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
1993 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
1994 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
1996 /* Precalculate vector information, this must be set up before the
1997 rs6000_hard_regno_nregs_internal below. */
1998 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2000 rs6000_vector_unit
[m
] = rs6000_vector_mem
[m
] = VECTOR_NONE
;
2001 rs6000_vector_reload
[m
][0] = CODE_FOR_nothing
;
2002 rs6000_vector_reload
[m
][1] = CODE_FOR_nothing
;
2005 for (c
= 0; c
< (int)(int)RS6000_CONSTRAINT_MAX
; c
++)
2006 rs6000_constraints
[c
] = NO_REGS
;
2008 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2009 believes it can use native alignment or still uses 128-bit alignment. */
2010 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2021 /* V2DF mode, VSX only. */
2024 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2025 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2026 rs6000_vector_align
[V2DFmode
] = align64
;
2029 /* V4SF mode, either VSX or Altivec. */
2032 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2033 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2034 rs6000_vector_align
[V4SFmode
] = align32
;
2036 else if (TARGET_ALTIVEC
)
2038 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2039 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2040 rs6000_vector_align
[V4SFmode
] = align32
;
2043 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2047 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2048 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2049 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2050 rs6000_vector_align
[V4SImode
] = align32
;
2051 rs6000_vector_align
[V8HImode
] = align32
;
2052 rs6000_vector_align
[V16QImode
] = align32
;
2056 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2057 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2058 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2062 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2063 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2064 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2068 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2069 Altivec doesn't have 64-bit support. */
2072 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2073 rs6000_vector_unit
[V2DImode
] = VECTOR_NONE
;
2074 rs6000_vector_align
[V2DImode
] = align64
;
2077 /* DFmode, see if we want to use the VSX unit. */
2078 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2080 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2081 rs6000_vector_mem
[DFmode
]
2082 = (TARGET_VSX_SCALAR_MEMORY
? VECTOR_VSX
: VECTOR_NONE
);
2083 rs6000_vector_align
[DFmode
] = align64
;
2086 /* TODO add SPE and paired floating point vector support. */
2088 /* Register class constraints for the constraints that depend on compile
2090 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2091 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2093 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2094 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2098 /* At present, we just use VSX_REGS, but we have different constraints
2099 based on the use, in case we want to fine tune the default register
2100 class used. wa = any VSX register, wf = register class to use for
2101 V4SF, wd = register class to use for V2DF, and ws = register classs to
2102 use for DF scalars. */
2103 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2104 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2105 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2106 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = (TARGET_VSX_SCALAR_MEMORY
2112 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2114 /* Set up the reload helper functions. */
2115 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2119 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_di_store
;
2120 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_di_load
;
2121 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_di_store
;
2122 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_di_load
;
2123 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_di_store
;
2124 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_di_load
;
2125 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_di_store
;
2126 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_di_load
;
2127 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_di_store
;
2128 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_di_load
;
2129 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_di_store
;
2130 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_di_load
;
2131 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2133 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_di_store
;
2134 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_di_load
;
2139 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_si_store
;
2140 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_si_load
;
2141 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_si_store
;
2142 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_si_load
;
2143 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_si_store
;
2144 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_si_load
;
2145 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_si_store
;
2146 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_si_load
;
2147 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_si_store
;
2148 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_si_load
;
2149 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_si_store
;
2150 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_si_load
;
2151 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2153 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_si_store
;
2154 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_si_load
;
2159 /* Precalculate HARD_REGNO_NREGS. */
2160 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2161 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2162 rs6000_hard_regno_nregs
[m
][r
]
2163 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2165 /* Precalculate HARD_REGNO_MODE_OK. */
2166 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2167 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2168 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2169 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2171 /* Precalculate CLASS_MAX_NREGS sizes. */
2172 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2176 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2177 reg_size
= UNITS_PER_VSX_WORD
;
2179 else if (c
== ALTIVEC_REGS
)
2180 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2182 else if (c
== FLOAT_REGS
)
2183 reg_size
= UNITS_PER_FP_WORD
;
2186 reg_size
= UNITS_PER_WORD
;
2188 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2189 rs6000_class_max_nregs
[m
][c
]
2190 = (GET_MODE_SIZE (m
) + reg_size
- 1) / reg_size
;
2193 if (TARGET_E500_DOUBLE
)
2194 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2196 /* Calculate which modes to automatically generate code to use a the
2197 reciprocal divide and square root instructions. In the future, possibly
2198 automatically generate the instructions even if the user did not specify
2199 -mrecip. The older machines double precision reciprocal sqrt estimate is
2200 not accurate enough. */
2201 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2203 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2205 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2206 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2207 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2208 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2209 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2211 if (TARGET_FRSQRTES
)
2212 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2214 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2215 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2216 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2217 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2218 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2220 if (rs6000_recip_control
)
2222 if (!flag_finite_math_only
)
2223 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2224 if (flag_trapping_math
)
2225 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2226 if (!flag_reciprocal_math
)
2227 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2228 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2230 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2231 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2232 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2234 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2235 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2236 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2238 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2239 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2240 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2242 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2243 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2244 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2246 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2247 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2248 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2250 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2251 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2252 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2254 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2255 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2256 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2258 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2259 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2260 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2264 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2266 if (TARGET_DEBUG_REG
)
2267 rs6000_debug_reg_global ();
2269 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2271 "SImode variable mult cost = %d\n"
2272 "SImode constant mult cost = %d\n"
2273 "SImode short constant mult cost = %d\n"
2274 "DImode multipliciation cost = %d\n"
2275 "SImode division cost = %d\n"
2276 "DImode division cost = %d\n"
2277 "Simple fp operation cost = %d\n"
2278 "DFmode multiplication cost = %d\n"
2279 "SFmode division cost = %d\n"
2280 "DFmode division cost = %d\n"
2281 "cache line size = %d\n"
2282 "l1 cache size = %d\n"
2283 "l2 cache size = %d\n"
2284 "simultaneous prefetches = %d\n"
2287 rs6000_cost
->mulsi_const
,
2288 rs6000_cost
->mulsi_const9
,
2296 rs6000_cost
->cache_line_size
,
2297 rs6000_cost
->l1_cache_size
,
2298 rs6000_cost
->l2_cache_size
,
2299 rs6000_cost
->simultaneous_prefetches
);
2304 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2307 darwin_rs6000_override_options (void)
2309 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2311 rs6000_altivec_abi
= 1;
2312 TARGET_ALTIVEC_VRSAVE
= 1;
2313 rs6000_current_abi
= ABI_DARWIN
;
2315 if (DEFAULT_ABI
== ABI_DARWIN
2317 darwin_one_byte_bool
= 1;
2319 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2321 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2322 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2326 rs6000_default_long_calls
= 1;
2327 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2330 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2332 if (!flag_mkernel
&& !flag_apple_kext
2334 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2335 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2337 /* Unless the user (not the configurer) has explicitly overridden
2338 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2339 G4 unless targeting the kernel. */
2342 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2343 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2344 && ! global_options_set
.x_rs6000_cpu_index
)
2346 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2351 /* If not otherwise specified by a target, make 'long double' equivalent to
2354 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2355 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2358 /* Return the builtin mask of the various options used that could affect which
2359 builtins were used. In the past we used target_flags, but we've run out of
2360 bits, and some options like SPE and PAIRED are no longer in
2364 rs6000_builtin_mask_calculate (void)
2366 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2367 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2368 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2369 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2370 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2371 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2372 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2373 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2374 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2375 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0));
2378 /* Override command line options. Mostly we process the processor type and
2379 sometimes adjust other TARGET_ options. */
2382 rs6000_option_override_internal (bool global_init_p
)
2385 bool have_cpu
= false;
2387 /* The default cpu requested at configure time, if any. */
2388 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
2390 HOST_WIDE_INT set_masks
;
2393 struct cl_target_option
*main_target_opt
2394 = ((global_init_p
|| target_option_default_node
== NULL
)
2395 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
2397 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2398 library functions, so warn about it. The flag may be useful for
2399 performance studies from time to time though, so don't disable it
2401 if (global_options_set
.x_rs6000_alignment_flags
2402 && rs6000_alignment_flags
== MASK_ALIGN_POWER
2403 && DEFAULT_ABI
== ABI_DARWIN
2405 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2406 " it is incompatible with the installed C and C++ libraries");
2408 /* Numerous experiment shows that IRA based loop pressure
2409 calculation works better for RTL loop invariant motion on targets
2410 with enough (>= 32) registers. It is an expensive optimization.
2411 So it is on only for peak performance. */
2412 if (optimize
>= 3 && global_init_p
)
2413 flag_ira_loop_pressure
= 1;
2415 /* Set the pointer size. */
2418 rs6000_pmode
= (int)DImode
;
2419 rs6000_pointer_size
= 64;
2423 rs6000_pmode
= (int)SImode
;
2424 rs6000_pointer_size
= 32;
2427 /* Some OSs don't support saving the high part of 64-bit registers on context
2428 switch. Other OSs don't support saving Altivec registers. On those OSs,
2429 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
2430 if the user wants either, the user must explicitly specify them and we
2431 won't interfere with the user's specification. */
2433 set_masks
= POWERPC_MASKS
;
2434 #ifdef OS_MISSING_POWERPC64
2435 if (OS_MISSING_POWERPC64
)
2436 set_masks
&= ~OPTION_MASK_POWERPC64
;
2438 #ifdef OS_MISSING_ALTIVEC
2439 if (OS_MISSING_ALTIVEC
)
2440 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
2443 /* Don't override by the processor default if given explicitly. */
2444 set_masks
&= ~rs6000_isa_flags_explicit
;
2446 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2447 the cpu in a target attribute or pragma, but did not specify a tuning
2448 option, use the cpu for the tuning option rather than the option specified
2449 with -mtune on the command line. Process a '--with-cpu' configuration
2450 request as an implicit --cpu. */
2451 if (rs6000_cpu_index
>= 0)
2453 cpu_index
= rs6000_cpu_index
;
2456 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
2458 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
2461 else if (implicit_cpu
)
2463 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
2468 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
2469 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
2473 gcc_assert (cpu_index
>= 0);
2475 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
2476 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
2477 with those from the cpu, except for options that were explicitly set. If
2478 we don't have a cpu, do not override the target bits set in
2482 rs6000_isa_flags
&= ~set_masks
;
2483 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2487 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2488 & ~rs6000_isa_flags_explicit
);
2490 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
2491 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
2492 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
2493 to using rs6000_isa_flags, we need to do the initialization here. */
2495 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
2497 if (rs6000_tune_index
>= 0)
2498 tune_index
= rs6000_tune_index
;
2500 rs6000_tune_index
= tune_index
= cpu_index
;
2504 enum processor_type tune_proc
2505 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
2508 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2509 if (processor_target_table
[i
].processor
== tune_proc
)
2511 rs6000_tune_index
= tune_index
= i
;
2516 gcc_assert (tune_index
>= 0);
2517 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
2519 /* Pick defaults for SPE related control flags. Do this early to make sure
2520 that the TARGET_ macros are representative ASAP. */
2522 int spe_capable_cpu
=
2523 (rs6000_cpu
== PROCESSOR_PPC8540
2524 || rs6000_cpu
== PROCESSOR_PPC8548
);
2526 if (!global_options_set
.x_rs6000_spe_abi
)
2527 rs6000_spe_abi
= spe_capable_cpu
;
2529 if (!global_options_set
.x_rs6000_spe
)
2530 rs6000_spe
= spe_capable_cpu
;
2532 if (!global_options_set
.x_rs6000_float_gprs
)
2534 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
2535 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
2539 if (global_options_set
.x_rs6000_spe_abi
2542 error ("not configured for SPE ABI");
2544 if (global_options_set
.x_rs6000_spe
2547 error ("not configured for SPE instruction set");
2549 if (main_target_opt
!= NULL
2550 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
2551 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
2552 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
2553 error ("target attribute or pragma changes SPE ABI");
2555 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
2556 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
2557 || rs6000_cpu
== PROCESSOR_PPCE5500
)
2560 error ("AltiVec not supported in this target");
2562 error ("SPE not supported in this target");
2564 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
2567 error ("SPE not supported in this target");
2570 /* Disable Cell microcode if we are optimizing for the Cell
2571 and not optimizing for size. */
2572 if (rs6000_gen_cell_microcode
== -1)
2573 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
2576 /* If we are optimizing big endian systems for space and it's OK to
2577 use instructions that would be microcoded on the Cell, use the
2578 load/store multiple and string instructions. */
2579 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
2580 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
2581 | OPTION_MASK_STRING
);
2583 /* Don't allow -mmultiple or -mstring on little endian systems
2584 unless the cpu is a 750, because the hardware doesn't support the
2585 instructions used in little endian mode, and causes an alignment
2586 trap. The 750 does not cause an alignment trap (except when the
2587 target is unaligned). */
2589 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
2591 if (TARGET_MULTIPLE
)
2593 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
2594 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
2595 warning (0, "-mmultiple is not supported on little endian systems");
2600 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
2601 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
2602 warning (0, "-mstring is not supported on little endian systems");
2606 /* Add some warnings for VSX. */
2609 const char *msg
= NULL
;
2610 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
2611 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
2613 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2614 msg
= N_("-mvsx requires hardware floating point");
2616 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2618 else if (TARGET_PAIRED_FLOAT
)
2619 msg
= N_("-mvsx and -mpaired are incompatible");
2620 /* The hardware will allow VSX and little endian, but until we make sure
2621 things like vector select, etc. work don't allow VSX on little endian
2622 systems at this point. */
2623 else if (!BYTES_BIG_ENDIAN
)
2624 msg
= N_("-mvsx used with little endian code");
2625 else if (TARGET_AVOID_XFORM
> 0)
2626 msg
= N_("-mvsx needs indexed addressing");
2627 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
2628 & OPTION_MASK_ALTIVEC
))
2630 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2631 msg
= N_("-mvsx and -mno-altivec are incompatible");
2633 msg
= N_("-mno-altivec disables vsx");
2639 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2640 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
2644 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2645 unless the user explicitly used the -mno-<option> to disable the code. */
2647 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
2648 else if (TARGET_POPCNTD
)
2649 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
2650 else if (TARGET_DFP
)
2651 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
2652 else if (TARGET_CMPB
)
2653 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
2654 else if (TARGET_FPRND
)
2655 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
2656 else if (TARGET_POPCNTB
)
2657 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
2658 else if (TARGET_ALTIVEC
)
2659 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
2661 /* E500mc does "better" if we inline more aggressively. Respect the
2662 user's opinion, though. */
2663 if (rs6000_block_move_inline_limit
== 0
2664 && (rs6000_cpu
== PROCESSOR_PPCE500MC
2665 || rs6000_cpu
== PROCESSOR_PPCE500MC64
2666 || rs6000_cpu
== PROCESSOR_PPCE5500
2667 || rs6000_cpu
== PROCESSOR_PPCE6500
))
2668 rs6000_block_move_inline_limit
= 128;
2670 /* store_one_arg depends on expand_block_move to handle at least the
2671 size of reg_parm_stack_space. */
2672 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
2673 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
2677 /* If the appropriate debug option is enabled, replace the target hooks
2678 with debug versions that call the real version and then prints
2679 debugging information. */
2680 if (TARGET_DEBUG_COST
)
2682 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
2683 targetm
.address_cost
= rs6000_debug_address_cost
;
2684 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
2687 if (TARGET_DEBUG_ADDR
)
2689 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
2690 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
2691 rs6000_secondary_reload_class_ptr
2692 = rs6000_debug_secondary_reload_class
;
2693 rs6000_secondary_memory_needed_ptr
2694 = rs6000_debug_secondary_memory_needed
;
2695 rs6000_cannot_change_mode_class_ptr
2696 = rs6000_debug_cannot_change_mode_class
;
2697 rs6000_preferred_reload_class_ptr
2698 = rs6000_debug_preferred_reload_class
;
2699 rs6000_legitimize_reload_address_ptr
2700 = rs6000_debug_legitimize_reload_address
;
2701 rs6000_mode_dependent_address_ptr
2702 = rs6000_debug_mode_dependent_address
;
2705 if (rs6000_veclibabi_name
)
2707 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
2708 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
2711 error ("unknown vectorization library ABI type (%s) for "
2712 "-mveclibabi= switch", rs6000_veclibabi_name
);
2718 if (!global_options_set
.x_rs6000_long_double_type_size
)
2720 if (main_target_opt
!= NULL
2721 && (main_target_opt
->x_rs6000_long_double_type_size
2722 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
2723 error ("target attribute or pragma changes long double size");
2725 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2728 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2729 if (!global_options_set
.x_rs6000_ieeequad
)
2730 rs6000_ieeequad
= 1;
2733 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2734 target attribute or pragma which automatically enables both options,
2735 unless the altivec ABI was set. This is set by default for 64-bit, but
2737 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
2738 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
2739 & ~rs6000_isa_flags_explicit
);
2741 /* Enable Altivec ABI for AIX -maltivec. */
2742 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
2744 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
2745 error ("target attribute or pragma changes AltiVec ABI");
2747 rs6000_altivec_abi
= 1;
2750 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2751 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2752 be explicitly overridden in either case. */
2755 if (!global_options_set
.x_rs6000_altivec_abi
2756 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
2758 if (main_target_opt
!= NULL
&&
2759 !main_target_opt
->x_rs6000_altivec_abi
)
2760 error ("target attribute or pragma changes AltiVec ABI");
2762 rs6000_altivec_abi
= 1;
2766 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2767 So far, the only darwin64 targets are also MACH-O. */
2769 && DEFAULT_ABI
== ABI_DARWIN
2772 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
2773 error ("target attribute or pragma changes darwin64 ABI");
2776 rs6000_darwin64_abi
= 1;
2777 /* Default to natural alignment, for better performance. */
2778 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2782 /* Place FP constants in the constant pool instead of TOC
2783 if section anchors enabled. */
2784 if (flag_section_anchors
)
2785 TARGET_NO_FP_IN_TOC
= 1;
2787 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2788 SUBTARGET_OVERRIDE_OPTIONS
;
2790 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2791 SUBSUBTARGET_OVERRIDE_OPTIONS
;
2793 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2794 SUB3TARGET_OVERRIDE_OPTIONS
;
2797 /* For the E500 family of cores, reset the single/double FP flags to let us
2798 check that they remain constant across attributes or pragmas. Also,
2799 clear a possible request for string instructions, not supported and which
2800 we might have silently queried above for -Os.
2802 For other families, clear ISEL in case it was set implicitly.
2807 case PROCESSOR_PPC8540
:
2808 case PROCESSOR_PPC8548
:
2809 case PROCESSOR_PPCE500MC
:
2810 case PROCESSOR_PPCE500MC64
:
2811 case PROCESSOR_PPCE5500
:
2812 case PROCESSOR_PPCE6500
:
2814 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
2815 rs6000_double_float
= TARGET_E500_DOUBLE
;
2817 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
2823 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
2824 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
2829 if (main_target_opt
)
2831 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
2832 error ("target attribute or pragma changes single precision floating "
2834 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
2835 error ("target attribute or pragma changes double precision floating "
2839 /* Detect invalid option combinations with E500. */
2842 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
2843 && rs6000_cpu
!= PROCESSOR_POWER5
2844 && rs6000_cpu
!= PROCESSOR_POWER6
2845 && rs6000_cpu
!= PROCESSOR_POWER7
2846 && rs6000_cpu
!= PROCESSOR_PPCA2
2847 && rs6000_cpu
!= PROCESSOR_CELL
2848 && rs6000_cpu
!= PROCESSOR_PPC476
);
2849 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
2850 || rs6000_cpu
== PROCESSOR_POWER5
2851 || rs6000_cpu
== PROCESSOR_POWER7
);
2852 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
2853 || rs6000_cpu
== PROCESSOR_POWER5
2854 || rs6000_cpu
== PROCESSOR_POWER6
2855 || rs6000_cpu
== PROCESSOR_POWER7
2856 || rs6000_cpu
== PROCESSOR_PPCE500MC
2857 || rs6000_cpu
== PROCESSOR_PPCE500MC64
2858 || rs6000_cpu
== PROCESSOR_PPCE5500
2859 || rs6000_cpu
== PROCESSOR_PPCE6500
);
2861 /* Allow debug switches to override the above settings. These are set to -1
2862 in rs6000.opt to indicate the user hasn't directly set the switch. */
2863 if (TARGET_ALWAYS_HINT
>= 0)
2864 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
2866 if (TARGET_SCHED_GROUPS
>= 0)
2867 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
2869 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
2870 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
2872 rs6000_sched_restricted_insns_priority
2873 = (rs6000_sched_groups
? 1 : 0);
2875 /* Handle -msched-costly-dep option. */
2876 rs6000_sched_costly_dep
2877 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
2879 if (rs6000_sched_costly_dep_str
)
2881 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
2882 rs6000_sched_costly_dep
= no_dep_costly
;
2883 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
2884 rs6000_sched_costly_dep
= all_deps_costly
;
2885 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
2886 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
2887 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
2888 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
2890 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
2891 atoi (rs6000_sched_costly_dep_str
));
2894 /* Handle -minsert-sched-nops option. */
2895 rs6000_sched_insert_nops
2896 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
2898 if (rs6000_sched_insert_nops_str
)
2900 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
2901 rs6000_sched_insert_nops
= sched_finish_none
;
2902 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
2903 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
2904 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
2905 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
2907 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
2908 atoi (rs6000_sched_insert_nops_str
));
2913 #ifdef TARGET_REGNAMES
2914 /* If the user desires alternate register names, copy in the
2915 alternate names now. */
2916 if (TARGET_REGNAMES
)
2917 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
2920 /* Set aix_struct_return last, after the ABI is determined.
2921 If -maix-struct-return or -msvr4-struct-return was explicitly
2922 used, don't override with the ABI default. */
2923 if (!global_options_set
.x_aix_struct_return
)
2924 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
2927 /* IBM XL compiler defaults to unsigned bitfields. */
2928 if (TARGET_XL_COMPAT
)
2929 flag_signed_bitfields
= 0;
2932 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
2933 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
2936 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
2938 /* We can only guarantee the availability of DI pseudo-ops when
2939 assembling for 64-bit targets. */
2942 targetm
.asm_out
.aligned_op
.di
= NULL
;
2943 targetm
.asm_out
.unaligned_op
.di
= NULL
;
2947 /* Set branch target alignment, if not optimizing for size. */
2950 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
2951 aligned 8byte to avoid misprediction by the branch predictor. */
2952 if (rs6000_cpu
== PROCESSOR_TITAN
2953 || rs6000_cpu
== PROCESSOR_CELL
)
2955 if (align_functions
<= 0)
2956 align_functions
= 8;
2957 if (align_jumps
<= 0)
2959 if (align_loops
<= 0)
2962 if (rs6000_align_branch_targets
)
2964 if (align_functions
<= 0)
2965 align_functions
= 16;
2966 if (align_jumps
<= 0)
2968 if (align_loops
<= 0)
2970 can_override_loop_align
= 1;
2974 if (align_jumps_max_skip
<= 0)
2975 align_jumps_max_skip
= 15;
2976 if (align_loops_max_skip
<= 0)
2977 align_loops_max_skip
= 15;
2980 /* Arrange to save and restore machine status around nested functions. */
2981 init_machine_status
= rs6000_init_machine_status
;
2983 /* We should always be splitting complex arguments, but we can't break
2984 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
2985 if (DEFAULT_ABI
!= ABI_AIX
)
2986 targetm
.calls
.split_complex_arg
= NULL
;
2989 /* Initialize rs6000_cost with the appropriate target costs. */
2991 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
2995 case PROCESSOR_RS64A
:
2996 rs6000_cost
= &rs64a_cost
;
2999 case PROCESSOR_MPCCORE
:
3000 rs6000_cost
= &mpccore_cost
;
3003 case PROCESSOR_PPC403
:
3004 rs6000_cost
= &ppc403_cost
;
3007 case PROCESSOR_PPC405
:
3008 rs6000_cost
= &ppc405_cost
;
3011 case PROCESSOR_PPC440
:
3012 rs6000_cost
= &ppc440_cost
;
3015 case PROCESSOR_PPC476
:
3016 rs6000_cost
= &ppc476_cost
;
3019 case PROCESSOR_PPC601
:
3020 rs6000_cost
= &ppc601_cost
;
3023 case PROCESSOR_PPC603
:
3024 rs6000_cost
= &ppc603_cost
;
3027 case PROCESSOR_PPC604
:
3028 rs6000_cost
= &ppc604_cost
;
3031 case PROCESSOR_PPC604e
:
3032 rs6000_cost
= &ppc604e_cost
;
3035 case PROCESSOR_PPC620
:
3036 rs6000_cost
= &ppc620_cost
;
3039 case PROCESSOR_PPC630
:
3040 rs6000_cost
= &ppc630_cost
;
3043 case PROCESSOR_CELL
:
3044 rs6000_cost
= &ppccell_cost
;
3047 case PROCESSOR_PPC750
:
3048 case PROCESSOR_PPC7400
:
3049 rs6000_cost
= &ppc750_cost
;
3052 case PROCESSOR_PPC7450
:
3053 rs6000_cost
= &ppc7450_cost
;
3056 case PROCESSOR_PPC8540
:
3057 case PROCESSOR_PPC8548
:
3058 rs6000_cost
= &ppc8540_cost
;
3061 case PROCESSOR_PPCE300C2
:
3062 case PROCESSOR_PPCE300C3
:
3063 rs6000_cost
= &ppce300c2c3_cost
;
3066 case PROCESSOR_PPCE500MC
:
3067 rs6000_cost
= &ppce500mc_cost
;
3070 case PROCESSOR_PPCE500MC64
:
3071 rs6000_cost
= &ppce500mc64_cost
;
3074 case PROCESSOR_PPCE5500
:
3075 rs6000_cost
= &ppce5500_cost
;
3078 case PROCESSOR_PPCE6500
:
3079 rs6000_cost
= &ppce6500_cost
;
3082 case PROCESSOR_TITAN
:
3083 rs6000_cost
= &titan_cost
;
3086 case PROCESSOR_POWER4
:
3087 case PROCESSOR_POWER5
:
3088 rs6000_cost
= &power4_cost
;
3091 case PROCESSOR_POWER6
:
3092 rs6000_cost
= &power6_cost
;
3095 case PROCESSOR_POWER7
:
3096 rs6000_cost
= &power7_cost
;
3099 case PROCESSOR_PPCA2
:
3100 rs6000_cost
= &ppca2_cost
;
3109 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3110 rs6000_cost
->simultaneous_prefetches
,
3111 global_options
.x_param_values
,
3112 global_options_set
.x_param_values
);
3113 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3114 global_options
.x_param_values
,
3115 global_options_set
.x_param_values
);
3116 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3117 rs6000_cost
->cache_line_size
,
3118 global_options
.x_param_values
,
3119 global_options_set
.x_param_values
);
3120 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3121 global_options
.x_param_values
,
3122 global_options_set
.x_param_values
);
3124 /* Increase loop peeling limits based on performance analysis. */
3125 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3126 global_options
.x_param_values
,
3127 global_options_set
.x_param_values
);
3128 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3129 global_options
.x_param_values
,
3130 global_options_set
.x_param_values
);
3132 /* If using typedef char *va_list, signal that
3133 __builtin_va_start (&ap, 0) can be optimized to
3134 ap = __builtin_next_arg (0). */
3135 if (DEFAULT_ABI
!= ABI_V4
)
3136 targetm
.expand_builtin_va_start
= NULL
;
3139 /* Set up single/double float flags.
3140 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3141 then set both flags. */
3142 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3143 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3144 rs6000_single_float
= rs6000_double_float
= 1;
3146 /* If not explicitly specified via option, decide whether to generate indexed
3147 load/store instructions. */
3148 if (TARGET_AVOID_XFORM
== -1)
3149 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3150 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3151 need indexed accesses and the type used is the scalar type of the element
3152 being loaded or stored. */
3153 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3154 && !TARGET_ALTIVEC
);
3156 /* Set the -mrecip options. */
3157 if (rs6000_recip_name
)
3159 char *p
= ASTRDUP (rs6000_recip_name
);
3161 unsigned int mask
, i
;
3164 while ((q
= strtok (p
, ",")) != NULL
)
3175 if (!strcmp (q
, "default"))
3176 mask
= ((TARGET_RECIP_PRECISION
)
3177 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3180 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3181 if (!strcmp (q
, recip_options
[i
].string
))
3183 mask
= recip_options
[i
].mask
;
3187 if (i
== ARRAY_SIZE (recip_options
))
3189 error ("unknown option for -mrecip=%s", q
);
3197 rs6000_recip_control
&= ~mask
;
3199 rs6000_recip_control
|= mask
;
3203 /* Set the builtin mask of the various options used that could affect which
3204 builtins were used. In the past we used target_flags, but we've run out
3205 of bits, and some options like SPE and PAIRED are no longer in
3207 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3208 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3211 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3212 rs6000_builtin_mask
);
3213 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3216 /* Initialize all of the registers. */
3217 rs6000_init_hard_regno_mode_ok (global_init_p
);
3219 /* Save the initial options in case the user does function specific options */
3221 target_option_default_node
= target_option_current_node
3222 = build_target_option_node ();
3224 /* If not explicitly specified via option, decide whether to generate the
3225 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3226 if (TARGET_LINK_STACK
== -1)
3227 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3232 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3233 define the target cpu type. */
3236 rs6000_option_override (void)
3238 (void) rs6000_option_override_internal (true);
3242 /* Implement targetm.vectorize.builtin_mask_for_load. */
3244 rs6000_builtin_mask_for_load (void)
3246 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3247 return altivec_builtin_mask_for_load
;
3252 /* Implement LOOP_ALIGN. */
3254 rs6000_loop_align (rtx label
)
3259 /* Don't override loop alignment if -falign-loops was specified. */
3260 if (!can_override_loop_align
)
3261 return align_loops_log
;
3263 bb
= BLOCK_FOR_INSN (label
);
3264 ninsns
= num_loop_insns(bb
->loop_father
);
3266 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3267 if (ninsns
> 4 && ninsns
<= 8
3268 && (rs6000_cpu
== PROCESSOR_POWER4
3269 || rs6000_cpu
== PROCESSOR_POWER5
3270 || rs6000_cpu
== PROCESSOR_POWER6
3271 || rs6000_cpu
== PROCESSOR_POWER7
))
3274 return align_loops_log
;
3277 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3279 rs6000_loop_align_max_skip (rtx label
)
3281 return (1 << rs6000_loop_align (label
)) - 1;
3284 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3285 after applying N number of iterations. This routine does not determine
3286 how may iterations are required to reach desired alignment. */
3289 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
3296 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
3299 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
3309 /* Assuming that all other types are naturally aligned. CHECKME! */
3314 /* Return true if the vector misalignment factor is supported by the
3317 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
3324 /* Return if movmisalign pattern is not supported for this mode. */
3325 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
3328 if (misalignment
== -1)
3330 /* Misalignment factor is unknown at compile time but we know
3331 it's word aligned. */
3332 if (rs6000_vector_alignment_reachable (type
, is_packed
))
3334 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
3336 if (element_size
== 64 || element_size
== 32)
3343 /* VSX supports word-aligned vector. */
3344 if (misalignment
% 4 == 0)
3350 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3352 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3353 tree vectype
, int misalign
)
3358 switch (type_of_cost
)
3368 case cond_branch_not_taken
:
3377 case vec_promote_demote
:
3383 case cond_branch_taken
:
3386 case unaligned_load
:
3387 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3389 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3391 /* Double word aligned. */
3399 /* Double word aligned. */
3403 /* Unknown misalignment. */
3416 /* Misaligned loads are not supported. */
3421 case unaligned_store
:
3422 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3424 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3426 /* Double word aligned. */
3434 /* Double word aligned. */
3438 /* Unknown misalignment. */
3451 /* Misaligned stores are not supported. */
3457 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3458 elem_type
= TREE_TYPE (vectype
);
3459 /* 32-bit vectors loaded into registers are stored as double
3460 precision, so we need n/2 converts in addition to the usual
3461 n/2 merges to construct a vector of short floats from them. */
3462 if (SCALAR_FLOAT_TYPE_P (elem_type
)
3463 && TYPE_PRECISION (elem_type
) == 32)
3464 return elements
+ 1;
3466 return elements
/ 2 + 1;
3473 /* Implement targetm.vectorize.preferred_simd_mode. */
3475 static enum machine_mode
3476 rs6000_preferred_simd_mode (enum machine_mode mode
)
3485 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3509 if (TARGET_PAIRED_FLOAT
3515 typedef struct _rs6000_cost_data
3517 struct loop
*loop_info
;
3521 /* Test for likely overcommitment of vector hardware resources. If a
3522 loop iteration is relatively large, and too large a percentage of
3523 instructions in the loop are vectorized, the cost model may not
3524 adequately reflect delays from unavailable vector resources.
3525 Penalize the loop body cost for this case. */
3528 rs6000_density_test (rs6000_cost_data
*data
)
3530 const int DENSITY_PCT_THRESHOLD
= 85;
3531 const int DENSITY_SIZE_THRESHOLD
= 70;
3532 const int DENSITY_PENALTY
= 10;
3533 struct loop
*loop
= data
->loop_info
;
3534 basic_block
*bbs
= get_loop_body (loop
);
3535 int nbbs
= loop
->num_nodes
;
3536 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
3539 for (i
= 0; i
< nbbs
; i
++)
3541 basic_block bb
= bbs
[i
];
3542 gimple_stmt_iterator gsi
;
3544 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
3546 gimple stmt
= gsi_stmt (gsi
);
3547 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
3549 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
3550 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
3556 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
3558 if (density_pct
> DENSITY_PCT_THRESHOLD
3559 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
3561 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
3562 if (dump_enabled_p ())
3563 dump_printf_loc (MSG_NOTE
, vect_location
,
3564 "density %d%%, cost %d exceeds threshold, penalizing "
3565 "loop body cost by %d%%", density_pct
,
3566 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
3570 /* Implement targetm.vectorize.init_cost. */
3573 rs6000_init_cost (struct loop
*loop_info
)
3575 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
3576 data
->loop_info
= loop_info
;
3577 data
->cost
[vect_prologue
] = 0;
3578 data
->cost
[vect_body
] = 0;
3579 data
->cost
[vect_epilogue
] = 0;
3583 /* Implement targetm.vectorize.add_stmt_cost. */
3586 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
3587 struct _stmt_vec_info
*stmt_info
, int misalign
,
3588 enum vect_cost_model_location where
)
3590 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
3591 unsigned retval
= 0;
3593 if (flag_vect_cost_model
)
3595 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
3596 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
3598 /* Statements in an inner loop relative to the loop being
3599 vectorized are weighted more heavily. The value here is
3600 arbitrary and could potentially be improved with analysis. */
3601 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
3602 count
*= 50; /* FIXME. */
3604 retval
= (unsigned) (count
* stmt_cost
);
3605 cost_data
->cost
[where
] += retval
;
3611 /* Implement targetm.vectorize.finish_cost. */
3614 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
3615 unsigned *body_cost
, unsigned *epilogue_cost
)
3617 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
3619 if (cost_data
->loop_info
)
3620 rs6000_density_test (cost_data
);
3622 *prologue_cost
= cost_data
->cost
[vect_prologue
];
3623 *body_cost
= cost_data
->cost
[vect_body
];
3624 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
3627 /* Implement targetm.vectorize.destroy_cost_data. */
3630 rs6000_destroy_cost_data (void *data
)
3635 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3636 library with vectorized intrinsics. */
3639 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
3642 const char *suffix
= NULL
;
3643 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
3646 enum machine_mode el_mode
, in_mode
;
3649 /* Libmass is suitable for unsafe math only as it does not correctly support
3650 parts of IEEE with the required precision such as denormals. Only support
3651 it if we have VSX to use the simd d2 or f4 functions.
3652 XXX: Add variable length support. */
3653 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
3656 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
3657 n
= TYPE_VECTOR_SUBPARTS (type_out
);
3658 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
3659 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
3660 if (el_mode
!= in_mode
3664 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
3666 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
3669 case BUILT_IN_ATAN2
:
3670 case BUILT_IN_HYPOT
:
3676 case BUILT_IN_ACOSH
:
3678 case BUILT_IN_ASINH
:
3680 case BUILT_IN_ATANH
:
3688 case BUILT_IN_EXPM1
:
3689 case BUILT_IN_LGAMMA
:
3690 case BUILT_IN_LOG10
:
3691 case BUILT_IN_LOG1P
:
3699 bdecl
= builtin_decl_implicit (fn
);
3700 suffix
= "d2"; /* pow -> powd2 */
3701 if (el_mode
!= DFmode
3706 case BUILT_IN_ATAN2F
:
3707 case BUILT_IN_HYPOTF
:
3712 case BUILT_IN_ACOSF
:
3713 case BUILT_IN_ACOSHF
:
3714 case BUILT_IN_ASINF
:
3715 case BUILT_IN_ASINHF
:
3716 case BUILT_IN_ATANF
:
3717 case BUILT_IN_ATANHF
:
3718 case BUILT_IN_CBRTF
:
3720 case BUILT_IN_COSHF
:
3722 case BUILT_IN_ERFCF
:
3723 case BUILT_IN_EXP2F
:
3725 case BUILT_IN_EXPM1F
:
3726 case BUILT_IN_LGAMMAF
:
3727 case BUILT_IN_LOG10F
:
3728 case BUILT_IN_LOG1PF
:
3729 case BUILT_IN_LOG2F
:
3732 case BUILT_IN_SINHF
:
3733 case BUILT_IN_SQRTF
:
3735 case BUILT_IN_TANHF
:
3736 bdecl
= builtin_decl_implicit (fn
);
3737 suffix
= "4"; /* powf -> powf4 */
3738 if (el_mode
!= SFmode
3750 gcc_assert (suffix
!= NULL
);
3751 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
3752 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
3753 strcat (name
, suffix
);
3756 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
3757 else if (n_args
== 2)
3758 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
3762 /* Build a function declaration for the vectorized function. */
3763 new_fndecl
= build_decl (BUILTINS_LOCATION
,
3764 FUNCTION_DECL
, get_identifier (name
), fntype
);
3765 TREE_PUBLIC (new_fndecl
) = 1;
3766 DECL_EXTERNAL (new_fndecl
) = 1;
3767 DECL_IS_NOVOPS (new_fndecl
) = 1;
3768 TREE_READONLY (new_fndecl
) = 1;
3773 /* Returns a function decl for a vectorized version of the builtin function
3774 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3775 if it is not available. */
3778 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
3781 enum machine_mode in_mode
, out_mode
;
3784 if (TARGET_DEBUG_BUILTIN
)
3785 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3786 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
3787 GET_MODE_NAME (TYPE_MODE (type_out
)),
3788 GET_MODE_NAME (TYPE_MODE (type_in
)));
3790 if (TREE_CODE (type_out
) != VECTOR_TYPE
3791 || TREE_CODE (type_in
) != VECTOR_TYPE
3792 || !TARGET_VECTORIZE_BUILTINS
)
3795 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
3796 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
3797 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
3798 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
3800 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
3802 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
3805 case BUILT_IN_COPYSIGN
:
3806 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3807 && out_mode
== DFmode
&& out_n
== 2
3808 && in_mode
== DFmode
&& in_n
== 2)
3809 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
3811 case BUILT_IN_COPYSIGNF
:
3812 if (out_mode
!= SFmode
|| out_n
!= 4
3813 || in_mode
!= SFmode
|| in_n
!= 4)
3815 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3816 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
3817 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3818 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
3821 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3822 && out_mode
== DFmode
&& out_n
== 2
3823 && in_mode
== DFmode
&& in_n
== 2)
3824 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
3826 case BUILT_IN_SQRTF
:
3827 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3828 && out_mode
== SFmode
&& out_n
== 4
3829 && in_mode
== SFmode
&& in_n
== 4)
3830 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
3833 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3834 && out_mode
== DFmode
&& out_n
== 2
3835 && in_mode
== DFmode
&& in_n
== 2)
3836 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
3838 case BUILT_IN_CEILF
:
3839 if (out_mode
!= SFmode
|| out_n
!= 4
3840 || in_mode
!= SFmode
|| in_n
!= 4)
3842 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3843 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
3844 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3845 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
3847 case BUILT_IN_FLOOR
:
3848 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3849 && out_mode
== DFmode
&& out_n
== 2
3850 && in_mode
== DFmode
&& in_n
== 2)
3851 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
3853 case BUILT_IN_FLOORF
:
3854 if (out_mode
!= SFmode
|| out_n
!= 4
3855 || in_mode
!= SFmode
|| in_n
!= 4)
3857 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3858 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
3859 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3860 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
3863 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3864 && out_mode
== DFmode
&& out_n
== 2
3865 && in_mode
== DFmode
&& in_n
== 2)
3866 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
3869 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3870 && out_mode
== SFmode
&& out_n
== 4
3871 && in_mode
== SFmode
&& in_n
== 4)
3872 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
3873 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
3874 && out_mode
== SFmode
&& out_n
== 4
3875 && in_mode
== SFmode
&& in_n
== 4)
3876 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
3878 case BUILT_IN_TRUNC
:
3879 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3880 && out_mode
== DFmode
&& out_n
== 2
3881 && in_mode
== DFmode
&& in_n
== 2)
3882 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
3884 case BUILT_IN_TRUNCF
:
3885 if (out_mode
!= SFmode
|| out_n
!= 4
3886 || in_mode
!= SFmode
|| in_n
!= 4)
3888 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3889 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
3890 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3891 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
3893 case BUILT_IN_NEARBYINT
:
3894 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3895 && flag_unsafe_math_optimizations
3896 && out_mode
== DFmode
&& out_n
== 2
3897 && in_mode
== DFmode
&& in_n
== 2)
3898 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
3900 case BUILT_IN_NEARBYINTF
:
3901 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3902 && flag_unsafe_math_optimizations
3903 && out_mode
== SFmode
&& out_n
== 4
3904 && in_mode
== SFmode
&& in_n
== 4)
3905 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
3908 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3909 && !flag_trapping_math
3910 && out_mode
== DFmode
&& out_n
== 2
3911 && in_mode
== DFmode
&& in_n
== 2)
3912 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
3914 case BUILT_IN_RINTF
:
3915 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3916 && !flag_trapping_math
3917 && out_mode
== SFmode
&& out_n
== 4
3918 && in_mode
== SFmode
&& in_n
== 4)
3919 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
3926 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
3928 enum rs6000_builtins fn
3929 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
3932 case RS6000_BUILTIN_RSQRTF
:
3933 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
3934 && out_mode
== SFmode
&& out_n
== 4
3935 && in_mode
== SFmode
&& in_n
== 4)
3936 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
3938 case RS6000_BUILTIN_RSQRT
:
3939 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3940 && out_mode
== DFmode
&& out_n
== 2
3941 && in_mode
== DFmode
&& in_n
== 2)
3942 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
3944 case RS6000_BUILTIN_RECIPF
:
3945 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
3946 && out_mode
== SFmode
&& out_n
== 4
3947 && in_mode
== SFmode
&& in_n
== 4)
3948 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
3950 case RS6000_BUILTIN_RECIP
:
3951 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3952 && out_mode
== DFmode
&& out_n
== 2
3953 && in_mode
== DFmode
&& in_n
== 2)
3954 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
3961 /* Generate calls to libmass if appropriate. */
3962 if (rs6000_veclib_handler
)
3963 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
3968 /* Default CPU string for rs6000*_file_start functions. */
3969 static const char *rs6000_default_cpu
;
3971 /* Do anything needed at the start of the asm file. */
3974 rs6000_file_start (void)
3977 const char *start
= buffer
;
3978 FILE *file
= asm_out_file
;
3980 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
3982 default_file_start ();
3984 if (flag_verbose_asm
)
3986 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
3988 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
3990 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
3994 if (global_options_set
.x_rs6000_cpu_index
)
3996 fprintf (file
, "%s -mcpu=%s", start
,
3997 processor_target_table
[rs6000_cpu_index
].name
);
4001 if (global_options_set
.x_rs6000_tune_index
)
4003 fprintf (file
, "%s -mtune=%s", start
,
4004 processor_target_table
[rs6000_tune_index
].name
);
4008 if (PPC405_ERRATUM77
)
4010 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4014 #ifdef USING_ELFOS_H
4015 switch (rs6000_sdata
)
4017 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4018 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4019 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4020 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4023 if (rs6000_sdata
&& g_switch_value
)
4025 fprintf (file
, "%s -G %d", start
,
4035 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
4037 switch_to_section (toc_section
);
4038 switch_to_section (text_section
);
4043 /* Return nonzero if this function is known to have a null epilogue. */
4046 direct_return (void)
4048 if (reload_completed
)
4050 rs6000_stack_t
*info
= rs6000_stack_info ();
4052 if (info
->first_gp_reg_save
== 32
4053 && info
->first_fp_reg_save
== 64
4054 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4055 && ! info
->lr_save_p
4056 && ! info
->cr_save_p
4057 && info
->vrsave_mask
== 0
4065 /* Return the number of instructions it takes to form a constant in an
4066 integer register. */
4069 num_insns_constant_wide (HOST_WIDE_INT value
)
4071 /* signed constant loadable with addi */
4072 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4075 /* constant loadable with addis */
4076 else if ((value
& 0xffff) == 0
4077 && (value
>> 31 == -1 || value
>> 31 == 0))
4080 #if HOST_BITS_PER_WIDE_INT == 64
4081 else if (TARGET_POWERPC64
)
4083 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4084 HOST_WIDE_INT high
= value
>> 31;
4086 if (high
== 0 || high
== -1)
4092 return num_insns_constant_wide (high
) + 1;
4094 return num_insns_constant_wide (low
) + 1;
4096 return (num_insns_constant_wide (high
)
4097 + num_insns_constant_wide (low
) + 1);
4106 num_insns_constant (rtx op
, enum machine_mode mode
)
4108 HOST_WIDE_INT low
, high
;
4110 switch (GET_CODE (op
))
4113 #if HOST_BITS_PER_WIDE_INT == 64
4114 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4115 && mask64_operand (op
, mode
))
4119 return num_insns_constant_wide (INTVAL (op
));
4122 if (mode
== SFmode
|| mode
== SDmode
)
4127 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4128 if (DECIMAL_FLOAT_MODE_P (mode
))
4129 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4131 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4132 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4135 if (mode
== VOIDmode
|| mode
== DImode
)
4137 high
= CONST_DOUBLE_HIGH (op
);
4138 low
= CONST_DOUBLE_LOW (op
);
4145 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4146 if (DECIMAL_FLOAT_MODE_P (mode
))
4147 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4149 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4150 high
= l
[WORDS_BIG_ENDIAN
== 0];
4151 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4155 return (num_insns_constant_wide (low
)
4156 + num_insns_constant_wide (high
));
4159 if ((high
== 0 && low
>= 0)
4160 || (high
== -1 && low
< 0))
4161 return num_insns_constant_wide (low
);
4163 else if (mask64_operand (op
, mode
))
4167 return num_insns_constant_wide (high
) + 1;
4170 return (num_insns_constant_wide (high
)
4171 + num_insns_constant_wide (low
) + 1);
4179 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4180 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4181 corresponding element of the vector, but for V4SFmode and V2SFmode,
4182 the corresponding "float" is interpreted as an SImode integer. */
4185 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4189 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4190 gcc_assert (GET_MODE (op
) != V2DImode
4191 && GET_MODE (op
) != V2DFmode
);
4193 tmp
= CONST_VECTOR_ELT (op
, elt
);
4194 if (GET_MODE (op
) == V4SFmode
4195 || GET_MODE (op
) == V2SFmode
)
4196 tmp
= gen_lowpart (SImode
, tmp
);
4197 return INTVAL (tmp
);
4200 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4201 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4202 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4203 all items are set to the same value and contain COPIES replicas of the
4204 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4205 operand and the others are set to the value of the operand's msb. */
4208 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4210 enum machine_mode mode
= GET_MODE (op
);
4211 enum machine_mode inner
= GET_MODE_INNER (mode
);
4219 HOST_WIDE_INT splat_val
;
4220 HOST_WIDE_INT msb_val
;
4222 if (mode
== V2DImode
|| mode
== V2DFmode
)
4225 nunits
= GET_MODE_NUNITS (mode
);
4226 bitsize
= GET_MODE_BITSIZE (inner
);
4227 mask
= GET_MODE_MASK (inner
);
4229 val
= const_vector_elt_as_int (op
, nunits
- 1);
4231 msb_val
= val
> 0 ? 0 : -1;
4233 /* Construct the value to be splatted, if possible. If not, return 0. */
4234 for (i
= 2; i
<= copies
; i
*= 2)
4236 HOST_WIDE_INT small_val
;
4238 small_val
= splat_val
>> bitsize
;
4240 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4242 splat_val
= small_val
;
4245 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4246 if (EASY_VECTOR_15 (splat_val
))
4249 /* Also check if we can splat, and then add the result to itself. Do so if
4250 the value is positive, of if the splat instruction is using OP's mode;
4251 for splat_val < 0, the splat and the add should use the same mode. */
4252 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4253 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4256 /* Also check if are loading up the most significant bit which can be done by
4257 loading up -1 and shifting the value left by -1. */
4258 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4264 /* Check if VAL is present in every STEP-th element, and the
4265 other elements are filled with its most significant bit. */
4266 for (i
= 0; i
< nunits
- 1; ++i
)
4268 HOST_WIDE_INT desired_val
;
4269 if (((i
+ 1) & (step
- 1)) == 0)
4272 desired_val
= msb_val
;
4274 if (desired_val
!= const_vector_elt_as_int (op
, i
))
4282 /* Return true if OP is of the given MODE and can be synthesized
4283 with a vspltisb, vspltish or vspltisw. */
4286 easy_altivec_constant (rtx op
, enum machine_mode mode
)
4288 unsigned step
, copies
;
4290 if (mode
== VOIDmode
)
4291 mode
= GET_MODE (op
);
4292 else if (mode
!= GET_MODE (op
))
4295 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4297 if (mode
== V2DFmode
)
4298 return zero_constant (op
, mode
);
4300 if (mode
== V2DImode
)
4302 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4304 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
4305 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
4308 if (zero_constant (op
, mode
))
4311 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
4312 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
4318 /* Start with a vspltisw. */
4319 step
= GET_MODE_NUNITS (mode
) / 4;
4322 if (vspltis_constant (op
, step
, copies
))
4325 /* Then try with a vspltish. */
4331 if (vspltis_constant (op
, step
, copies
))
4334 /* And finally a vspltisb. */
4340 if (vspltis_constant (op
, step
, copies
))
4346 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4347 result is OP. Abort if it is not possible. */
4350 gen_easy_altivec_constant (rtx op
)
4352 enum machine_mode mode
= GET_MODE (op
);
4353 int nunits
= GET_MODE_NUNITS (mode
);
4354 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
4355 unsigned step
= nunits
/ 4;
4356 unsigned copies
= 1;
4358 /* Start with a vspltisw. */
4359 if (vspltis_constant (op
, step
, copies
))
4360 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
4362 /* Then try with a vspltish. */
4368 if (vspltis_constant (op
, step
, copies
))
4369 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
4371 /* And finally a vspltisb. */
4377 if (vspltis_constant (op
, step
, copies
))
4378 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
4384 output_vec_const_move (rtx
*operands
)
4387 enum machine_mode mode
;
4392 mode
= GET_MODE (dest
);
4396 if (zero_constant (vec
, mode
))
4397 return "xxlxor %x0,%x0,%x0";
4399 if (mode
== V2DImode
4400 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
4401 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
4402 return "vspltisw %0,-1";
4408 if (zero_constant (vec
, mode
))
4409 return "vxor %0,%0,%0";
4411 splat_vec
= gen_easy_altivec_constant (vec
);
4412 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
4413 operands
[1] = XEXP (splat_vec
, 0);
4414 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
4417 switch (GET_MODE (splat_vec
))
4420 return "vspltisw %0,%1";
4423 return "vspltish %0,%1";
4426 return "vspltisb %0,%1";
4433 gcc_assert (TARGET_SPE
);
4435 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4436 pattern of V1DI, V4HI, and V2SF.
4438 FIXME: We should probably return # and add post reload
4439 splitters for these, but this way is so easy ;-). */
4440 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
4441 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
4442 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
4443 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
4445 return "li %0,%1\n\tevmergelo %0,%0,%0";
4447 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4450 /* Initialize TARGET of vector PAIRED to VALS. */
4453 paired_expand_vector_init (rtx target
, rtx vals
)
4455 enum machine_mode mode
= GET_MODE (target
);
4456 int n_elts
= GET_MODE_NUNITS (mode
);
4458 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
4461 for (i
= 0; i
< n_elts
; ++i
)
4463 x
= XVECEXP (vals
, 0, i
);
4464 if (!(CONST_INT_P (x
)
4465 || GET_CODE (x
) == CONST_DOUBLE
4466 || GET_CODE (x
) == CONST_FIXED
))
4471 /* Load from constant pool. */
4472 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
4478 /* The vector is initialized only with non-constants. */
4479 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
4480 XVECEXP (vals
, 0, 1));
4482 emit_move_insn (target
, new_rtx
);
4486 /* One field is non-constant and the other one is a constant. Load the
4487 constant from the constant pool and use ps_merge instruction to
4488 construct the whole vector. */
4489 op1
= XVECEXP (vals
, 0, 0);
4490 op2
= XVECEXP (vals
, 0, 1);
4492 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
4494 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
4495 emit_move_insn (tmp
, constant_op
);
4497 if (CONSTANT_P (op1
))
4498 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
4500 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
4502 emit_move_insn (target
, new_rtx
);
4506 paired_expand_vector_move (rtx operands
[])
4508 rtx op0
= operands
[0], op1
= operands
[1];
4510 emit_move_insn (op0
, op1
);
4513 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4514 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4515 operands for the relation operation COND. This is a recursive
4519 paired_emit_vector_compare (enum rtx_code rcode
,
4520 rtx dest
, rtx op0
, rtx op1
,
4521 rtx cc_op0
, rtx cc_op1
)
4523 rtx tmp
= gen_reg_rtx (V2SFmode
);
4526 gcc_assert (TARGET_PAIRED_FLOAT
);
4527 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
4533 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4537 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4538 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
4542 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
4545 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4548 tmp1
= gen_reg_rtx (V2SFmode
);
4549 max
= gen_reg_rtx (V2SFmode
);
4550 min
= gen_reg_rtx (V2SFmode
);
4551 gen_reg_rtx (V2SFmode
);
4553 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4554 emit_insn (gen_selv2sf4
4555 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4556 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
4557 emit_insn (gen_selv2sf4
4558 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4559 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
4560 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
4563 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4566 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4569 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4572 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4575 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4584 /* Emit vector conditional expression.
4585 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4586 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4589 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
4590 rtx cond
, rtx cc_op0
, rtx cc_op1
)
4592 enum rtx_code rcode
= GET_CODE (cond
);
4594 if (!TARGET_PAIRED_FLOAT
)
4597 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
4602 /* Initialize vector TARGET to VALS. */
4605 rs6000_expand_vector_init (rtx target
, rtx vals
)
4607 enum machine_mode mode
= GET_MODE (target
);
4608 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4609 int n_elts
= GET_MODE_NUNITS (mode
);
4610 int n_var
= 0, one_var
= -1;
4611 bool all_same
= true, all_const_zero
= true;
4615 for (i
= 0; i
< n_elts
; ++i
)
4617 x
= XVECEXP (vals
, 0, i
);
4618 if (!(CONST_INT_P (x
)
4619 || GET_CODE (x
) == CONST_DOUBLE
4620 || GET_CODE (x
) == CONST_FIXED
))
4621 ++n_var
, one_var
= i
;
4622 else if (x
!= CONST0_RTX (inner_mode
))
4623 all_const_zero
= false;
4625 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
4631 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
4632 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
4633 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
4635 /* Zero register. */
4636 emit_insn (gen_rtx_SET (VOIDmode
, target
,
4637 gen_rtx_XOR (mode
, target
, target
)));
4640 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
4642 /* Splat immediate. */
4643 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
4648 /* Load from constant pool. */
4649 emit_move_insn (target
, const_vec
);
4654 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4655 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
4657 rtx op0
= XVECEXP (vals
, 0, 0);
4658 rtx op1
= XVECEXP (vals
, 0, 1);
4661 if (!MEM_P (op0
) && !REG_P (op0
))
4662 op0
= force_reg (inner_mode
, op0
);
4663 if (mode
== V2DFmode
)
4664 emit_insn (gen_vsx_splat_v2df (target
, op0
));
4666 emit_insn (gen_vsx_splat_v2di (target
, op0
));
4670 op0
= force_reg (inner_mode
, op0
);
4671 op1
= force_reg (inner_mode
, op1
);
4672 if (mode
== V2DFmode
)
4673 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
4675 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
4680 /* With single precision floating point on VSX, know that internally single
4681 precision is actually represented as a double, and either make 2 V2DF
4682 vectors, and convert these vectors to single precision, or do one
4683 conversion, and splat the result to the other elements. */
4684 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
4688 rtx freg
= gen_reg_rtx (V4SFmode
);
4689 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
4691 emit_insn (gen_vsx_xscvdpsp_scalar (freg
, sreg
));
4692 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
4696 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
4697 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
4698 rtx flt_even
= gen_reg_rtx (V4SFmode
);
4699 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
4700 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
4701 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
4702 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
4703 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
4705 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
4706 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
4707 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
4708 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
4709 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
4714 /* Store value to stack temp. Load vector element. Splat. However, splat
4715 of 64-bit items is not supported on Altivec. */
4716 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
4718 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
4719 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
4720 XVECEXP (vals
, 0, 0));
4721 x
= gen_rtx_UNSPEC (VOIDmode
,
4722 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
4723 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4725 gen_rtx_SET (VOIDmode
,
4728 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
4729 gen_rtx_PARALLEL (VOIDmode
,
4730 gen_rtvec (1, const0_rtx
)));
4731 emit_insn (gen_rtx_SET (VOIDmode
, target
,
4732 gen_rtx_VEC_DUPLICATE (mode
, x
)));
4736 /* One field is non-constant. Load constant then overwrite
4740 rtx copy
= copy_rtx (vals
);
4742 /* Load constant part of vector, substitute neighboring value for
4744 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
4745 rs6000_expand_vector_init (target
, copy
);
4747 /* Insert variable. */
4748 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
4752 /* Construct the vector in memory one field at a time
4753 and load the whole vector. */
4754 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
4755 for (i
= 0; i
< n_elts
; i
++)
4756 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
4757 i
* GET_MODE_SIZE (inner_mode
)),
4758 XVECEXP (vals
, 0, i
));
4759 emit_move_insn (target
, mem
);
4762 /* Set field ELT of TARGET to VAL. */
4765 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
4767 enum machine_mode mode
= GET_MODE (target
);
4768 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4769 rtx reg
= gen_reg_rtx (mode
);
4771 int width
= GET_MODE_SIZE (inner_mode
);
4774 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
4776 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
4777 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
4778 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
4782 /* Load single variable value. */
4783 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
4784 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
4785 x
= gen_rtx_UNSPEC (VOIDmode
,
4786 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
4787 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4789 gen_rtx_SET (VOIDmode
,
4793 /* Linear sequence. */
4794 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
4795 for (i
= 0; i
< 16; ++i
)
4796 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
4798 /* Set permute mask to insert element into target. */
4799 for (i
= 0; i
< width
; ++i
)
4800 XVECEXP (mask
, 0, elt
*width
+ i
)
4801 = GEN_INT (i
+ 0x10);
4802 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
4803 x
= gen_rtx_UNSPEC (mode
,
4804 gen_rtvec (3, target
, reg
,
4805 force_reg (V16QImode
, x
)),
4807 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
4810 /* Extract field ELT from VEC into TARGET. */
4813 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
4815 enum machine_mode mode
= GET_MODE (vec
);
4816 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4819 if (VECTOR_MEM_VSX_P (mode
))
4826 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
4829 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
4832 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
4837 /* Allocate mode-sized buffer. */
4838 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
4840 emit_move_insn (mem
, vec
);
4842 /* Add offset to field within buffer matching vector element. */
4843 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
4845 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
4848 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4849 implement ANDing by the mask IN. */
4851 build_mask64_2_operands (rtx in
, rtx
*out
)
4853 #if HOST_BITS_PER_WIDE_INT >= 64
4854 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
4857 gcc_assert (GET_CODE (in
) == CONST_INT
);
4862 /* Assume c initially something like 0x00fff000000fffff. The idea
4863 is to rotate the word so that the middle ^^^^^^ group of zeros
4864 is at the MS end and can be cleared with an rldicl mask. We then
4865 rotate back and clear off the MS ^^ group of zeros with a
4867 c
= ~c
; /* c == 0xff000ffffff00000 */
4868 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
4869 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
4870 c
= ~c
; /* c == 0x00fff000000fffff */
4871 c
&= -lsb
; /* c == 0x00fff00000000000 */
4872 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
4873 c
= ~c
; /* c == 0xff000fffffffffff */
4874 c
&= -lsb
; /* c == 0xff00000000000000 */
4876 while ((lsb
>>= 1) != 0)
4877 shift
++; /* shift == 44 on exit from loop */
4878 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
4879 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
4880 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
4884 /* Assume c initially something like 0xff000f0000000000. The idea
4885 is to rotate the word so that the ^^^ middle group of zeros
4886 is at the LS end and can be cleared with an rldicr mask. We then
4887 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4889 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
4890 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
4891 c
= ~c
; /* c == 0x00fff0ffffffffff */
4892 c
&= -lsb
; /* c == 0x00fff00000000000 */
4893 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
4894 c
= ~c
; /* c == 0xff000fffffffffff */
4895 c
&= -lsb
; /* c == 0xff00000000000000 */
4897 while ((lsb
>>= 1) != 0)
4898 shift
++; /* shift == 44 on exit from loop */
4899 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
4900 m1
>>= shift
; /* m1 == 0x0000000000000fff */
4901 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
4904 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4905 masks will be all 1's. We are guaranteed more than one transition. */
4906 out
[0] = GEN_INT (64 - shift
);
4907 out
[1] = GEN_INT (m1
);
4908 out
[2] = GEN_INT (shift
);
4909 out
[3] = GEN_INT (m2
);
4917 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4920 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
4922 if (TARGET_E500_DOUBLE
)
4924 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4925 subreg:TI and reg:TF. Decimal float modes are like integer
4926 modes (only low part of each register used) for this
4928 if (GET_CODE (op
) == SUBREG
4929 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
4930 || mode
== DDmode
|| mode
== TDmode
)
4931 && REG_P (SUBREG_REG (op
))
4932 && (GET_MODE (SUBREG_REG (op
)) == DFmode
4933 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
4936 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4938 if (GET_CODE (op
) == SUBREG
4939 && (mode
== DFmode
|| mode
== TFmode
)
4940 && REG_P (SUBREG_REG (op
))
4941 && (GET_MODE (SUBREG_REG (op
)) == DImode
4942 || GET_MODE (SUBREG_REG (op
)) == TImode
4943 || GET_MODE (SUBREG_REG (op
)) == DDmode
4944 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
4949 && GET_CODE (op
) == SUBREG
4951 && REG_P (SUBREG_REG (op
))
4952 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
4958 /* AIX increases natural record alignment to doubleword if the first
4959 field is an FP double while the FP fields remain word aligned. */
4962 rs6000_special_round_type_align (tree type
, unsigned int computed
,
4963 unsigned int specified
)
4965 unsigned int align
= MAX (computed
, specified
);
4966 tree field
= TYPE_FIELDS (type
);
4968 /* Skip all non field decls */
4969 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
4970 field
= DECL_CHAIN (field
);
4972 if (field
!= NULL
&& field
!= type
)
4974 type
= TREE_TYPE (field
);
4975 while (TREE_CODE (type
) == ARRAY_TYPE
)
4976 type
= TREE_TYPE (type
);
4978 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
4979 align
= MAX (align
, 64);
4985 /* Darwin increases record alignment to the natural alignment of
4989 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
4990 unsigned int specified
)
4992 unsigned int align
= MAX (computed
, specified
);
4994 if (TYPE_PACKED (type
))
4997 /* Find the first field, looking down into aggregates. */
4999 tree field
= TYPE_FIELDS (type
);
5000 /* Skip all non field decls */
5001 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5002 field
= DECL_CHAIN (field
);
5005 /* A packed field does not contribute any extra alignment. */
5006 if (DECL_PACKED (field
))
5008 type
= TREE_TYPE (field
);
5009 while (TREE_CODE (type
) == ARRAY_TYPE
)
5010 type
= TREE_TYPE (type
);
5011 } while (AGGREGATE_TYPE_P (type
));
5013 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5014 align
= MAX (align
, TYPE_ALIGN (type
));
5019 /* Return 1 for an operand in small memory on V.4/eabi. */
5022 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5023 enum machine_mode mode ATTRIBUTE_UNUSED
)
5028 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5031 if (DEFAULT_ABI
!= ABI_V4
)
5034 /* Vector and float memory instructions have a limited offset on the
5035 SPE, so using a vector or float variable directly as an operand is
5038 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5041 if (GET_CODE (op
) == SYMBOL_REF
)
5044 else if (GET_CODE (op
) != CONST
5045 || GET_CODE (XEXP (op
, 0)) != PLUS
5046 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5047 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5052 rtx sum
= XEXP (op
, 0);
5053 HOST_WIDE_INT summand
;
5055 /* We have to be careful here, because it is the referenced address
5056 that must be 32k from _SDA_BASE_, not just the symbol. */
5057 summand
= INTVAL (XEXP (sum
, 1));
5058 if (summand
< 0 || summand
> g_switch_value
)
5061 sym_ref
= XEXP (sum
, 0);
5064 return SYMBOL_REF_SMALL_P (sym_ref
);
5070 /* Return true if either operand is a general purpose register. */
5073 gpr_or_gpr_p (rtx op0
, rtx op1
)
5075 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5076 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5079 /* Given an address, return a constant offset term if one exists. */
5082 address_offset (rtx op
)
5084 if (GET_CODE (op
) == PRE_INC
5085 || GET_CODE (op
) == PRE_DEC
)
5087 else if (GET_CODE (op
) == PRE_MODIFY
5088 || GET_CODE (op
) == LO_SUM
)
5091 if (GET_CODE (op
) == CONST
)
5094 if (GET_CODE (op
) == PLUS
)
5097 if (CONST_INT_P (op
))
5103 /* Return true if the MEM operand is a memory operand suitable for use
5104 with a (full width, possibly multiple) gpr load/store. On
5105 powerpc64 this means the offset must be divisible by 4.
5106 Implements 'Y' constraint.
5108 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5109 a constraint function we know the operand has satisfied a suitable
5110 memory predicate. Also accept some odd rtl generated by reload
5111 (see rs6000_legitimize_reload_address for various forms). It is
5112 important that reload rtl be accepted by appropriate constraints
5113 but not by the operand predicate.
5115 Offsetting a lo_sum should not be allowed, except where we know by
5116 alignment that a 32k boundary is not crossed, but see the ???
5117 comment in rs6000_legitimize_reload_address. Note that by
5118 "offsetting" here we mean a further offset to access parts of the
5119 MEM. It's fine to have a lo_sum where the inner address is offset
5120 from a sym, since the same sym+offset will appear in the high part
5121 of the address calculation. */
5124 mem_operand_gpr (rtx op
, enum machine_mode mode
)
5126 unsigned HOST_WIDE_INT offset
;
5128 rtx addr
= XEXP (op
, 0);
5130 op
= address_offset (addr
);
5134 offset
= INTVAL (op
);
5135 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
5138 if (GET_CODE (addr
) == LO_SUM
)
5139 /* We know by alignment that ABI_AIX medium/large model toc refs
5140 will not cross a 32k boundary, since all entries in the
5141 constant pool are naturally aligned and we check alignment for
5142 other medium model toc-relative addresses. For ABI_V4 and
5143 ABI_DARWIN lo_sum addresses, we just check that 64-bit
5144 offsets are 4-byte aligned. */
5147 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
5148 gcc_assert (extra
>= 0);
5149 return offset
+ 0x8000 < 0x10000u
- extra
;
5152 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5155 reg_offset_addressing_ok_p (enum machine_mode mode
)
5165 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5166 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
5174 /* Paired vector modes. Only reg+reg addressing is valid. */
5175 if (TARGET_PAIRED_FLOAT
)
5187 virtual_stack_registers_memory_p (rtx op
)
5191 if (GET_CODE (op
) == REG
)
5192 regnum
= REGNO (op
);
5194 else if (GET_CODE (op
) == PLUS
5195 && GET_CODE (XEXP (op
, 0)) == REG
5196 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5197 regnum
= REGNO (XEXP (op
, 0));
5202 return (regnum
>= FIRST_VIRTUAL_REGISTER
5203 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
5206 /* Return true if memory accesses to OP are known to never straddle
5210 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
5211 enum machine_mode mode
)
5214 unsigned HOST_WIDE_INT dsize
, dalign
;
5216 if (GET_CODE (op
) != SYMBOL_REF
)
5219 decl
= SYMBOL_REF_DECL (op
);
5222 if (GET_MODE_SIZE (mode
) == 0)
5225 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5226 replacing memory addresses with an anchor plus offset. We
5227 could find the decl by rummaging around in the block->objects
5228 VEC for the given offset but that seems like too much work. */
5230 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
5231 && SYMBOL_REF_ANCHOR_P (op
)
5232 && SYMBOL_REF_BLOCK (op
) != NULL
)
5234 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
5235 HOST_WIDE_INT lsb
, mask
;
5237 /* Given the alignment of the block.. */
5238 dalign
= block
->alignment
;
5239 mask
= dalign
/ BITS_PER_UNIT
- 1;
5241 /* ..and the combined offset of the anchor and any offset
5242 to this block object.. */
5243 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
5244 lsb
= offset
& -offset
;
5246 /* ..find how many bits of the alignment we know for the
5251 return dalign
>= GET_MODE_SIZE (mode
);
5256 if (TREE_CODE (decl
) == FUNCTION_DECL
)
5259 if (!DECL_SIZE_UNIT (decl
))
5262 if (!host_integerp (DECL_SIZE_UNIT (decl
), 1))
5265 dsize
= tree_low_cst (DECL_SIZE_UNIT (decl
), 1);
5269 dalign
= DECL_ALIGN_UNIT (decl
);
5270 return dalign
>= dsize
;
5273 type
= TREE_TYPE (decl
);
5275 if (TREE_CODE (decl
) == STRING_CST
)
5276 dsize
= TREE_STRING_LENGTH (decl
);
5277 else if (TYPE_SIZE_UNIT (type
)
5278 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5279 dsize
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
5285 dalign
= TYPE_ALIGN (type
);
5286 if (CONSTANT_CLASS_P (decl
))
5287 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
5289 dalign
= DATA_ALIGNMENT (decl
, dalign
);
5290 dalign
/= BITS_PER_UNIT
;
5291 return dalign
>= dsize
;
5295 constant_pool_expr_p (rtx op
)
5299 split_const (op
, &base
, &offset
);
5300 return (GET_CODE (base
) == SYMBOL_REF
5301 && CONSTANT_POOL_ADDRESS_P (base
)
5302 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
5305 static const_rtx tocrel_base
, tocrel_offset
;
5307 /* Return true if OP is a toc pointer relative address (the output
5308 of create_TOC_reference). If STRICT, do not match high part or
5309 non-split -mcmodel=large/medium toc pointer relative addresses. */
5312 toc_relative_expr_p (const_rtx op
, bool strict
)
5317 if (TARGET_CMODEL
!= CMODEL_SMALL
)
5319 /* Only match the low part. */
5320 if (GET_CODE (op
) == LO_SUM
5321 && REG_P (XEXP (op
, 0))
5322 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
5329 tocrel_offset
= const0_rtx
;
5330 if (GET_CODE (op
) == PLUS
&& CONST_INT_P (XEXP (op
, 1)))
5332 tocrel_base
= XEXP (op
, 0);
5333 tocrel_offset
= XEXP (op
, 1);
5336 return (GET_CODE (tocrel_base
) == UNSPEC
5337 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
5340 /* Return true if X is a constant pool address, and also for cmodel=medium
5341 if X is a toc-relative address known to be offsettable within MODE. */
5344 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
5347 return (toc_relative_expr_p (x
, strict
)
5348 && (TARGET_CMODEL
!= CMODEL_MEDIUM
5349 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
5351 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
5352 INTVAL (tocrel_offset
), mode
)));
5356 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
5358 return (DEFAULT_ABI
== ABI_V4
5359 && !flag_pic
&& !TARGET_TOC
5360 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
5361 && small_data_operand (x
, mode
));
5364 /* SPE offset addressing is limited to 5-bits worth of double words. */
5365 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5368 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
5369 bool strict
, bool worst_case
)
5371 unsigned HOST_WIDE_INT offset
;
5374 if (GET_CODE (x
) != PLUS
)
5376 if (!REG_P (XEXP (x
, 0)))
5378 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5380 if (!reg_offset_addressing_ok_p (mode
))
5381 return virtual_stack_registers_memory_p (x
);
5382 if (legitimate_constant_pool_address_p (x
, mode
, strict
))
5384 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5387 offset
= INTVAL (XEXP (x
, 1));
5395 /* SPE vector modes. */
5396 return SPE_CONST_OFFSET_OK (offset
);
5401 /* On e500v2, we may have:
5403 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5405 Which gets addressed with evldd instructions. */
5406 if (TARGET_E500_DOUBLE
)
5407 return SPE_CONST_OFFSET_OK (offset
);
5409 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5411 if (mode
== DFmode
&& VECTOR_MEM_VSX_P (DFmode
))
5416 if (!TARGET_POWERPC64
)
5418 else if (offset
& 3)
5425 if (TARGET_E500_DOUBLE
)
5426 return (SPE_CONST_OFFSET_OK (offset
)
5427 && SPE_CONST_OFFSET_OK (offset
+ 8));
5432 if (!TARGET_POWERPC64
)
5434 else if (offset
& 3)
5443 return offset
< 0x10000 - extra
;
5447 legitimate_indexed_address_p (rtx x
, int strict
)
5451 if (GET_CODE (x
) != PLUS
)
5457 /* Recognize the rtl generated by reload which we know will later be
5458 replaced with proper base and index regs. */
5460 && reload_in_progress
5461 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
5465 return (REG_P (op0
) && REG_P (op1
)
5466 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
5467 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
5468 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
5469 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
5473 avoiding_indexed_address_p (enum machine_mode mode
)
5475 /* Avoid indexed addressing for modes that have non-indexed
5476 load/store instruction forms. */
5477 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
5481 legitimate_indirect_address_p (rtx x
, int strict
)
5483 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
5487 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
5489 if (!TARGET_MACHO
|| !flag_pic
5490 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
5494 if (GET_CODE (x
) != LO_SUM
)
5496 if (GET_CODE (XEXP (x
, 0)) != REG
)
5498 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
5502 return CONSTANT_P (x
);
5506 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
5508 if (GET_CODE (x
) != LO_SUM
)
5510 if (GET_CODE (XEXP (x
, 0)) != REG
)
5512 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5514 /* Restrict addressing for DI because of our SUBREG hackery. */
5515 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
5519 if (TARGET_ELF
|| TARGET_MACHO
)
5521 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
5525 if (GET_MODE_NUNITS (mode
) != 1)
5527 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
5528 && !(/* ??? Assume floating point reg based on mode? */
5529 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
5530 && (mode
== DFmode
|| mode
== DDmode
)))
5533 return CONSTANT_P (x
);
5540 /* Try machine-dependent ways of modifying an illegitimate address
5541 to be legitimate. If we find one, return the new, valid address.
5542 This is used from only one place: `memory_address' in explow.c.
5544 OLDX is the address as it was before break_out_memory_refs was
5545 called. In some cases it is useful to look at this to decide what
5548 It is always safe for this function to do nothing. It exists to
5549 recognize opportunities to optimize the output.
5551 On RS/6000, first check for the sum of a register with a constant
5552 integer that is out of range. If so, generate code to add the
5553 constant with the low-order 16 bits masked to the register and force
5554 this result into another register (this can be done with `cau').
5555 Then generate an address of REG+(CONST&0xffff), allowing for the
5556 possibility of bit 16 being a one.
5558 Then check for the sum of a register and something not constant, try to
5559 load the other things into a register and return the sum. */
5562 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
5563 enum machine_mode mode
)
5567 if (!reg_offset_addressing_ok_p (mode
))
5569 if (virtual_stack_registers_memory_p (x
))
5572 /* In theory we should not be seeing addresses of the form reg+0,
5573 but just in case it is generated, optimize it away. */
5574 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
5575 return force_reg (Pmode
, XEXP (x
, 0));
5577 /* Make sure both operands are registers. */
5578 else if (GET_CODE (x
) == PLUS
)
5579 return gen_rtx_PLUS (Pmode
,
5580 force_reg (Pmode
, XEXP (x
, 0)),
5581 force_reg (Pmode
, XEXP (x
, 1)));
5583 return force_reg (Pmode
, x
);
5585 if (GET_CODE (x
) == SYMBOL_REF
)
5587 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
5589 return rs6000_legitimize_tls_address (x
, model
);
5598 /* As in legitimate_offset_address_p we do not assume
5599 worst-case. The mode here is just a hint as to the registers
5600 used. A TImode is usually in gprs, but may actually be in
5601 fprs. Leave worst-case scenario for reload to handle via
5602 insn constraints. */
5609 if (GET_CODE (x
) == PLUS
5610 && GET_CODE (XEXP (x
, 0)) == REG
5611 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5612 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
5614 && !(SPE_VECTOR_MODE (mode
)
5615 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
5617 HOST_WIDE_INT high_int
, low_int
;
5619 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5620 if (low_int
>= 0x8000 - extra
)
5622 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
5623 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5624 GEN_INT (high_int
)), 0);
5625 return plus_constant (Pmode
, sum
, low_int
);
5627 else if (GET_CODE (x
) == PLUS
5628 && GET_CODE (XEXP (x
, 0)) == REG
5629 && GET_CODE (XEXP (x
, 1)) != CONST_INT
5630 && GET_MODE_NUNITS (mode
) == 1
5631 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
5632 || (/* ??? Assume floating point reg based on mode? */
5633 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5634 && (mode
== DFmode
|| mode
== DDmode
)))
5635 && !avoiding_indexed_address_p (mode
))
5637 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5638 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
5640 else if (SPE_VECTOR_MODE (mode
)
5641 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
5645 /* We accept [reg + reg] and [reg + OFFSET]. */
5647 if (GET_CODE (x
) == PLUS
)
5649 rtx op1
= XEXP (x
, 0);
5650 rtx op2
= XEXP (x
, 1);
5653 op1
= force_reg (Pmode
, op1
);
5655 if (GET_CODE (op2
) != REG
5656 && (GET_CODE (op2
) != CONST_INT
5657 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
5658 || (GET_MODE_SIZE (mode
) > 8
5659 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
5660 op2
= force_reg (Pmode
, op2
);
5662 /* We can't always do [reg + reg] for these, because [reg +
5663 reg + offset] is not a legitimate addressing mode. */
5664 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
5666 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
5667 return force_reg (Pmode
, y
);
5672 return force_reg (Pmode
, x
);
5674 else if ((TARGET_ELF
5676 || !MACHO_DYNAMIC_NO_PIC_P
5682 && GET_CODE (x
) != CONST_INT
5683 && GET_CODE (x
) != CONST_DOUBLE
5685 && GET_MODE_NUNITS (mode
) == 1
5686 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
5687 || (/* ??? Assume floating point reg based on mode? */
5688 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5689 && (mode
== DFmode
|| mode
== DDmode
))))
5691 rtx reg
= gen_reg_rtx (Pmode
);
5693 emit_insn (gen_elf_high (reg
, x
));
5695 emit_insn (gen_macho_high (reg
, x
));
5696 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
5699 && GET_CODE (x
) == SYMBOL_REF
5700 && constant_pool_expr_p (x
)
5701 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
5702 return create_TOC_reference (x
, NULL_RTX
);
5707 /* Debug version of rs6000_legitimize_address. */
5709 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
5715 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
5716 insns
= get_insns ();
5722 "\nrs6000_legitimize_address: mode %s, old code %s, "
5723 "new code %s, modified\n",
5724 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
5725 GET_RTX_NAME (GET_CODE (ret
)));
5727 fprintf (stderr
, "Original address:\n");
5730 fprintf (stderr
, "oldx:\n");
5733 fprintf (stderr
, "New address:\n");
5738 fprintf (stderr
, "Insns added:\n");
5739 debug_rtx_list (insns
, 20);
5745 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5746 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
5757 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5758 We need to emit DTP-relative relocations. */
5760 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
5762 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5767 fputs ("\t.long\t", file
);
5770 fputs (DOUBLE_INT_ASM_OP
, file
);
5775 output_addr_const (file
, x
);
5776 fputs ("@dtprel+0x8000", file
);
5779 /* In the name of slightly smaller debug output, and to cater to
5780 general assembler lossage, recognize various UNSPEC sequences
5781 and turn them back into a direct symbol reference. */
5784 rs6000_delegitimize_address (rtx orig_x
)
5788 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5794 if (TARGET_CMODEL
!= CMODEL_SMALL
5795 && GET_CODE (y
) == LO_SUM
)
5799 if (GET_CODE (y
) == PLUS
5800 && GET_MODE (y
) == Pmode
5801 && CONST_INT_P (XEXP (y
, 1)))
5803 offset
= XEXP (y
, 1);
5807 if (GET_CODE (y
) == UNSPEC
5808 && XINT (y
, 1) == UNSPEC_TOCREL
)
5810 #ifdef ENABLE_CHECKING
5811 if (REG_P (XVECEXP (y
, 0, 1))
5812 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
5816 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
5818 /* Weirdness alert. df_note_compute can replace r2 with a
5819 debug_expr when this unspec is in a debug_insn.
5820 Seen in gcc.dg/pr51957-1.c */
5828 y
= XVECEXP (y
, 0, 0);
5829 if (offset
!= NULL_RTX
)
5830 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
5831 if (!MEM_P (orig_x
))
5834 return replace_equiv_address_nv (orig_x
, y
);
5838 && GET_CODE (orig_x
) == LO_SUM
5839 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
5841 y
= XEXP (XEXP (orig_x
, 1), 0);
5842 if (GET_CODE (y
) == UNSPEC
5843 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
5844 return XVECEXP (y
, 0, 0);
5850 /* Return true if X shouldn't be emitted into the debug info.
5851 The linker doesn't like .toc section references from
5852 .debug_* sections, so reject .toc section symbols. */
5855 rs6000_const_not_ok_for_debug_p (rtx x
)
5857 if (GET_CODE (x
) == SYMBOL_REF
5858 && CONSTANT_POOL_ADDRESS_P (x
))
5860 rtx c
= get_pool_constant (x
);
5861 enum machine_mode cmode
= get_pool_mode (x
);
5862 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
5869 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5871 static GTY(()) rtx rs6000_tls_symbol
;
5873 rs6000_tls_get_addr (void)
5875 if (!rs6000_tls_symbol
)
5876 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
5878 return rs6000_tls_symbol
;
5881 /* Construct the SYMBOL_REF for TLS GOT references. */
5883 static GTY(()) rtx rs6000_got_symbol
;
5885 rs6000_got_sym (void)
5887 if (!rs6000_got_symbol
)
5889 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
5890 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
5891 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
5894 return rs6000_got_symbol
;
5897 /* AIX Thread-Local Address support. */
5900 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
5902 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
;
5904 /* Place addr into TOC constant pool. */
5905 sym
= force_const_mem (GET_MODE (addr
), addr
);
5907 /* Output the TOC entry and create the MEM referencing the value. */
5908 if (constant_pool_expr_p (XEXP (sym
, 0))
5909 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
5911 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
5912 mem
= gen_const_mem (Pmode
, tocref
);
5913 set_mem_alias_set (mem
, get_TOC_alias_set ());
5918 /* Use global-dynamic for local-dynamic. */
5919 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
5920 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
5922 rtx module
= gen_reg_rtx (Pmode
);
5923 /* Create new TOC reference for @m symbol. */
5924 const char *name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
5925 char *name2
= XALLOCAVEC (char, strlen (name
) + 1);
5926 strcpy (name2
, "*LCM");
5927 strcat (name2
, name
+ 3);
5928 tocref
= create_TOC_reference (gen_rtx_SYMBOL_REF (Pmode
,
5929 ggc_alloc_string (name2
,
5932 rtx mem2
= gen_const_mem (Pmode
, tocref
);
5933 set_mem_alias_set (mem2
, get_TOC_alias_set ());
5935 dest
= gen_reg_rtx (Pmode
);
5936 tmpreg
= gen_reg_rtx (Pmode
);
5937 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
5938 emit_insn (gen_rtx_SET (VOIDmode
, module
, mem2
));
5940 emit_insn (gen_tls_get_addrsi (dest
, module
, tmpreg
));
5942 emit_insn (gen_tls_get_addrdi (dest
, module
, tmpreg
));
5945 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
5946 else if (TARGET_32BIT
)
5948 tlsreg
= gen_reg_rtx (SImode
);
5949 emit_insn (gen_tls_get_tpointer (tlsreg
));
5952 tlsreg
= gen_rtx_REG (DImode
, 13);
5954 /* Load the TOC value into temporary register. */
5955 tmpreg
= gen_reg_rtx (Pmode
);
5956 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
5957 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
5958 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
5960 /* Add TOC symbol value to TLS pointer. */
5961 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
5966 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5967 this (thread-local) address. */
5970 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
5975 return rs6000_legitimize_tls_address_aix (addr
, model
);
5977 dest
= gen_reg_rtx (Pmode
);
5978 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
5984 tlsreg
= gen_rtx_REG (Pmode
, 13);
5985 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
5989 tlsreg
= gen_rtx_REG (Pmode
, 2);
5990 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
5994 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
5998 tmp
= gen_reg_rtx (Pmode
);
6001 tlsreg
= gen_rtx_REG (Pmode
, 13);
6002 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6006 tlsreg
= gen_rtx_REG (Pmode
, 2);
6007 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6011 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6013 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6018 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6020 /* We currently use relocations like @got@tlsgd for tls, which
6021 means the linker will handle allocation of tls entries, placing
6022 them in the .got section. So use a pointer to the .got section,
6023 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6024 or to secondary GOT sections used by 32-bit -fPIC. */
6026 got
= gen_rtx_REG (Pmode
, 2);
6030 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6033 rtx gsym
= rs6000_got_sym ();
6034 got
= gen_reg_rtx (Pmode
);
6036 rs6000_emit_move (got
, gsym
, Pmode
);
6041 tmp1
= gen_reg_rtx (Pmode
);
6042 tmp2
= gen_reg_rtx (Pmode
);
6043 mem
= gen_const_mem (Pmode
, tmp1
);
6044 lab
= gen_label_rtx ();
6045 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6046 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6047 if (TARGET_LINK_STACK
)
6048 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6049 emit_move_insn (tmp2
, mem
);
6050 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6051 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
6056 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
6058 tga
= rs6000_tls_get_addr ();
6059 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
6060 1, const0_rtx
, Pmode
);
6062 r3
= gen_rtx_REG (Pmode
, 3);
6063 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6064 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
6065 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6066 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
6067 else if (DEFAULT_ABI
== ABI_V4
)
6068 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
6071 call_insn
= last_call_insn ();
6072 PATTERN (call_insn
) = insn
;
6073 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6074 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6075 pic_offset_table_rtx
);
6077 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
6079 tga
= rs6000_tls_get_addr ();
6080 tmp1
= gen_reg_rtx (Pmode
);
6081 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
6082 1, const0_rtx
, Pmode
);
6084 r3
= gen_rtx_REG (Pmode
, 3);
6085 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6086 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
6087 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6088 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
6089 else if (DEFAULT_ABI
== ABI_V4
)
6090 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
6093 call_insn
= last_call_insn ();
6094 PATTERN (call_insn
) = insn
;
6095 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6096 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6097 pic_offset_table_rtx
);
6099 if (rs6000_tls_size
== 16)
6102 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
6104 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
6106 else if (rs6000_tls_size
== 32)
6108 tmp2
= gen_reg_rtx (Pmode
);
6110 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
6112 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
6115 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
6117 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
6121 tmp2
= gen_reg_rtx (Pmode
);
6123 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
6125 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
6127 insn
= gen_rtx_SET (Pmode
, dest
,
6128 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
6134 /* IE, or 64-bit offset LE. */
6135 tmp2
= gen_reg_rtx (Pmode
);
6137 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
6139 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
6142 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
6144 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
6152 /* Return 1 if X contains a thread-local symbol. */
6155 rs6000_tls_referenced_p (rtx x
)
6157 if (! TARGET_HAVE_TLS
)
6160 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
6163 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6166 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6168 if (GET_CODE (x
) == HIGH
6169 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6172 /* A TLS symbol in the TOC cannot contain a sum. */
6173 if (GET_CODE (x
) == CONST
6174 && GET_CODE (XEXP (x
, 0)) == PLUS
6175 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
6176 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
6179 /* Do not place an ELF TLS symbol in the constant pool. */
6180 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
6183 /* Return 1 if *X is a thread-local symbol. This is the same as
6184 rs6000_tls_symbol_ref except for the type of the unused argument. */
6187 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6189 return RS6000_SYMBOL_REF_TLS_P (*x
);
6192 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
6193 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
6194 can be addressed relative to the toc pointer. */
6197 use_toc_relative_ref (rtx sym
)
6199 return ((constant_pool_expr_p (sym
)
6200 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
6201 get_pool_mode (sym
)))
6202 || (TARGET_CMODEL
== CMODEL_MEDIUM
6203 && !CONSTANT_POOL_ADDRESS_P (sym
)
6204 && SYMBOL_REF_LOCAL_P (sym
)));
6207 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6208 replace the input X, or the original X if no replacement is called for.
6209 The output parameter *WIN is 1 if the calling macro should goto WIN,
6212 For RS/6000, we wish to handle large displacements off a base
6213 register by splitting the addend across an addiu/addis and the mem insn.
6214 This cuts number of extra insns needed from 3 to 1.
6216 On Darwin, we use this to generate code for floating point constants.
6217 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6218 The Darwin code is inside #if TARGET_MACHO because only then are the
6219 machopic_* functions defined. */
6221 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6222 int opnum
, int type
,
6223 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
6225 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6227 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6228 DFmode/DImode MEM. */
6231 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
6232 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
6233 reg_offset_p
= false;
6235 /* We must recognize output that we have already generated ourselves. */
6236 if (GET_CODE (x
) == PLUS
6237 && GET_CODE (XEXP (x
, 0)) == PLUS
6238 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6239 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6240 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6242 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6243 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6244 opnum
, (enum reload_type
) type
);
6249 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6250 if (GET_CODE (x
) == LO_SUM
6251 && GET_CODE (XEXP (x
, 0)) == HIGH
)
6253 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6254 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6255 opnum
, (enum reload_type
) type
);
6261 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
6262 && GET_CODE (x
) == LO_SUM
6263 && GET_CODE (XEXP (x
, 0)) == PLUS
6264 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
6265 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
6266 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
6267 && machopic_operand_p (XEXP (x
, 1)))
6269 /* Result of previous invocation of this function on Darwin
6270 floating point constant. */
6271 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6272 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6273 opnum
, (enum reload_type
) type
);
6279 if (TARGET_CMODEL
!= CMODEL_SMALL
6281 && small_toc_ref (x
, VOIDmode
))
6283 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
6284 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
6285 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6286 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6287 opnum
, (enum reload_type
) type
);
6292 if (GET_CODE (x
) == PLUS
6293 && GET_CODE (XEXP (x
, 0)) == REG
6294 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
6295 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
6296 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6298 && !SPE_VECTOR_MODE (mode
)
6299 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
6300 || mode
== DDmode
|| mode
== TDmode
6302 && VECTOR_MEM_NONE_P (mode
))
6304 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
6305 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
6307 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6309 /* Check for 32-bit overflow. */
6310 if (high
+ low
!= val
)
6316 /* Reload the high part into a base reg; leave the low part
6317 in the mem directly. */
6319 x
= gen_rtx_PLUS (GET_MODE (x
),
6320 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
6324 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6325 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6326 opnum
, (enum reload_type
) type
);
6331 if (GET_CODE (x
) == SYMBOL_REF
6333 && VECTOR_MEM_NONE_P (mode
)
6334 && !SPE_VECTOR_MODE (mode
)
6336 && DEFAULT_ABI
== ABI_DARWIN
6337 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
6338 && machopic_symbol_defined_p (x
)
6340 && DEFAULT_ABI
== ABI_V4
6343 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6344 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6346 ??? Assume floating point reg based on mode? This assumption is
6347 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
6348 where reload ends up doing a DFmode load of a constant from
6349 mem using two gprs. Unfortunately, at this point reload
6350 hasn't yet selected regs so poking around in reload data
6351 won't help and even if we could figure out the regs reliably,
6352 we'd still want to allow this transformation when the mem is
6353 naturally aligned. Since we say the address is good here, we
6354 can't disable offsets from LO_SUMs in mem_operand_gpr.
6355 FIXME: Allow offset from lo_sum for other modes too, when
6356 mem is sufficiently aligned. */
6359 && (mode
!= DImode
|| TARGET_POWERPC64
)
6360 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
6361 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
6366 rtx offset
= machopic_gen_offset (x
);
6367 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6368 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
6369 gen_rtx_HIGH (Pmode
, offset
)), offset
);
6373 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6374 gen_rtx_HIGH (Pmode
, x
), x
);
6376 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6377 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6378 opnum
, (enum reload_type
) type
);
6383 /* Reload an offset address wrapped by an AND that represents the
6384 masking of the lower bits. Strip the outer AND and let reload
6385 convert the offset address into an indirect address. For VSX,
6386 force reload to create the address with an AND in a separate
6387 register, because we can't guarantee an altivec register will
6389 if (VECTOR_MEM_ALTIVEC_P (mode
)
6390 && GET_CODE (x
) == AND
6391 && GET_CODE (XEXP (x
, 0)) == PLUS
6392 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6393 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6394 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6395 && INTVAL (XEXP (x
, 1)) == -16)
6404 && GET_CODE (x
) == SYMBOL_REF
6405 && use_toc_relative_ref (x
))
6407 x
= create_TOC_reference (x
, NULL_RTX
);
6408 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6409 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6410 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6411 opnum
, (enum reload_type
) type
);
6419 /* Debug version of rs6000_legitimize_reload_address. */
6421 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6422 int opnum
, int type
,
6423 int ind_levels
, int *win
)
6425 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
6428 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6429 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6430 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
6434 fprintf (stderr
, "Same address returned\n");
6436 fprintf (stderr
, "NULL returned\n");
6439 fprintf (stderr
, "New address:\n");
6446 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6447 that is a valid memory address for an instruction.
6448 The MODE argument is the machine mode for the MEM expression
6449 that wants to use this address.
6451 On the RS/6000, there are four valid address: a SYMBOL_REF that
6452 refers to a constant pool entry of an address (or the sum of it
6453 plus a constant), a short (16-bit signed) constant plus a register,
6454 the sum of two registers, or a register indirect, possibly with an
6455 auto-increment. For DFmode, DDmode and DImode with a constant plus
6456 register, we must ensure that both words are addressable or PowerPC64
6457 with offset word aligned.
6459 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6460 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6461 because adjacent memory cells are accessed by adding word-sized offsets
6462 during assembly output. */
6464 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
6466 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6468 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6469 if (VECTOR_MEM_ALTIVEC_P (mode
)
6470 && GET_CODE (x
) == AND
6471 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6472 && INTVAL (XEXP (x
, 1)) == -16)
6475 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
6477 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
6479 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
6480 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
6481 && !SPE_VECTOR_MODE (mode
)
6484 /* Restrict addressing for DI because of our SUBREG hackery. */
6485 && !(TARGET_E500_DOUBLE
6486 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
6488 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
6490 if (virtual_stack_registers_memory_p (x
))
6492 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
6495 && legitimate_constant_pool_address_p (x
, mode
, reg_ok_strict
))
6497 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6500 && GET_CODE (x
) == PLUS
6501 && GET_CODE (XEXP (x
, 0)) == REG
6502 && (XEXP (x
, 0) == virtual_stack_vars_rtx
6503 || XEXP (x
, 0) == arg_pointer_rtx
)
6504 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6506 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
6511 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6513 || (mode
!= DFmode
&& mode
!= DDmode
)
6514 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
6515 && (TARGET_POWERPC64
|| mode
!= DImode
)
6516 && !avoiding_indexed_address_p (mode
)
6517 && legitimate_indexed_address_p (x
, reg_ok_strict
))
6519 if (GET_CODE (x
) == PRE_MODIFY
6523 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6525 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
6526 && (TARGET_POWERPC64
|| mode
!= DImode
)
6527 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
6528 && !SPE_VECTOR_MODE (mode
)
6529 /* Restrict addressing for DI because of our SUBREG hackery. */
6530 && !(TARGET_E500_DOUBLE
6531 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
6533 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
6534 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
6535 reg_ok_strict
, false)
6536 || (!avoiding_indexed_address_p (mode
)
6537 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
6538 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6540 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
6545 /* Debug version of rs6000_legitimate_address_p. */
6547 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
6550 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
6552 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6553 "strict = %d, code = %s\n",
6554 ret
? "true" : "false",
6555 GET_MODE_NAME (mode
),
6557 GET_RTX_NAME (GET_CODE (x
)));
6563 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6566 rs6000_mode_dependent_address_p (const_rtx addr
,
6567 addr_space_t as ATTRIBUTE_UNUSED
)
6569 return rs6000_mode_dependent_address_ptr (addr
);
6572 /* Go to LABEL if ADDR (a legitimate address expression)
6573 has an effect that depends on the machine mode it is used for.
6575 On the RS/6000 this is true of all integral offsets (since AltiVec
6576 and VSX modes don't allow them) or is a pre-increment or decrement.
6578 ??? Except that due to conceptual problems in offsettable_address_p
6579 we can't really report the problems of integral offsets. So leave
6580 this assuming that the adjustable offset must be valid for the
6581 sub-words of a TFmode operand, which is what we had before. */
6584 rs6000_mode_dependent_address (const_rtx addr
)
6586 switch (GET_CODE (addr
))
6589 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6590 is considered a legitimate address before reload, so there
6591 are no offset restrictions in that case. Note that this
6592 condition is safe in strict mode because any address involving
6593 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6594 been rejected as illegitimate. */
6595 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
6596 && XEXP (addr
, 0) != arg_pointer_rtx
6597 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6599 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
6600 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
6605 /* Anything in the constant pool is sufficiently aligned that
6606 all bytes have the same high part address. */
6607 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
6609 /* Auto-increment cases are now treated generically in recog.c. */
6611 return TARGET_UPDATE
;
6613 /* AND is only allowed in Altivec loads. */
6624 /* Debug version of rs6000_mode_dependent_address. */
6626 rs6000_debug_mode_dependent_address (const_rtx addr
)
6628 bool ret
= rs6000_mode_dependent_address (addr
);
6630 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
6631 ret
? "true" : "false");
6637 /* Implement FIND_BASE_TERM. */
6640 rs6000_find_base_term (rtx op
)
6645 if (GET_CODE (base
) == CONST
)
6646 base
= XEXP (base
, 0);
6647 if (GET_CODE (base
) == PLUS
)
6648 base
= XEXP (base
, 0);
6649 if (GET_CODE (base
) == UNSPEC
)
6650 switch (XINT (base
, 1))
6653 case UNSPEC_MACHOPIC_OFFSET
:
6654 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6655 for aliasing purposes. */
6656 return XVECEXP (base
, 0, 0);
6662 /* More elaborate version of recog's offsettable_memref_p predicate
6663 that works around the ??? note of rs6000_mode_dependent_address.
6664 In particular it accepts
6666 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6668 in 32-bit mode, that the recog predicate rejects. */
6671 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
6678 /* First mimic offsettable_memref_p. */
6679 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
6682 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6683 the latter predicate knows nothing about the mode of the memory
6684 reference and, therefore, assumes that it is the largest supported
6685 mode (TFmode). As a consequence, legitimate offsettable memory
6686 references are rejected. rs6000_legitimate_offset_address_p contains
6687 the correct logic for the PLUS case of rs6000_mode_dependent_address,
6688 at least with a little bit of help here given that we know the
6689 actual registers used. */
6690 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
6691 || GET_MODE_SIZE (reg_mode
) == 4);
6692 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
6696 /* Change register usage conditional on target flags. */
6698 rs6000_conditional_register_usage (void)
6702 if (TARGET_DEBUG_TARGET
)
6703 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
6705 /* Set MQ register fixed (already call_used) so that it will not be
6709 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6711 fixed_regs
[13] = call_used_regs
[13]
6712 = call_really_used_regs
[13] = 1;
6714 /* Conditionally disable FPRs. */
6715 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
6716 for (i
= 32; i
< 64; i
++)
6717 fixed_regs
[i
] = call_used_regs
[i
]
6718 = call_really_used_regs
[i
] = 1;
6720 /* The TOC register is not killed across calls in a way that is
6721 visible to the compiler. */
6722 if (DEFAULT_ABI
== ABI_AIX
)
6723 call_really_used_regs
[2] = 0;
6725 if (DEFAULT_ABI
== ABI_V4
6726 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
6728 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6730 if (DEFAULT_ABI
== ABI_V4
6731 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
6733 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6734 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6735 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6737 if (DEFAULT_ABI
== ABI_DARWIN
6738 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
6739 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6740 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6741 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6743 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
6744 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6745 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6749 global_regs
[SPEFSCR_REGNO
] = 1;
6750 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6751 registers in prologues and epilogues. We no longer use r14
6752 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6753 pool for link-compatibility with older versions of GCC. Once
6754 "old" code has died out, we can return r14 to the allocation
6757 = call_used_regs
[14]
6758 = call_really_used_regs
[14] = 1;
6761 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
6763 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
6764 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6765 call_really_used_regs
[VRSAVE_REGNO
] = 1;
6768 if (TARGET_ALTIVEC
|| TARGET_VSX
)
6769 global_regs
[VSCR_REGNO
] = 1;
6771 if (TARGET_ALTIVEC_ABI
)
6773 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
6774 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6776 /* AIX reserves VR20:31 in non-extended ABI mode. */
6778 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
6779 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6783 /* Try to output insns to set TARGET equal to the constant C if it can
6784 be done in less than N insns. Do all computations in MODE.
6785 Returns the place where the output has been placed if it can be
6786 done and the insns have been emitted. If it would take more than N
6787 insns, zero is returned and no insns and emitted. */
6790 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
6791 rtx source
, int n ATTRIBUTE_UNUSED
)
6793 rtx result
, insn
, set
;
6794 HOST_WIDE_INT c0
, c1
;
6801 dest
= gen_reg_rtx (mode
);
6802 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
6806 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
6808 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
6809 GEN_INT (INTVAL (source
)
6810 & (~ (HOST_WIDE_INT
) 0xffff))));
6811 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
6812 gen_rtx_IOR (SImode
, copy_rtx (result
),
6813 GEN_INT (INTVAL (source
) & 0xffff))));
6818 switch (GET_CODE (source
))
6821 c0
= INTVAL (source
);
6826 #if HOST_BITS_PER_WIDE_INT >= 64
6827 c0
= CONST_DOUBLE_LOW (source
);
6830 c0
= CONST_DOUBLE_LOW (source
);
6831 c1
= CONST_DOUBLE_HIGH (source
);
6839 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
6846 insn
= get_last_insn ();
6847 set
= single_set (insn
);
6848 if (! CONSTANT_P (SET_SRC (set
)))
6849 set_unique_reg_note (insn
, REG_EQUAL
, source
);
6854 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6855 fall back to a straight forward decomposition. We do this to avoid
6856 exponential run times encountered when looking for longer sequences
6857 with rs6000_emit_set_const. */
6859 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
6861 if (!TARGET_POWERPC64
)
6863 rtx operand1
, operand2
;
6865 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
6867 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
6869 emit_move_insn (operand1
, GEN_INT (c1
));
6870 emit_move_insn (operand2
, GEN_INT (c2
));
6874 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
6877 ud2
= (c1
& 0xffff0000) >> 16;
6878 #if HOST_BITS_PER_WIDE_INT >= 64
6882 ud4
= (c2
& 0xffff0000) >> 16;
6884 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
6885 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
6888 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
6890 emit_move_insn (dest
, GEN_INT (ud1
));
6893 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
6894 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
6897 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
6900 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
6902 emit_move_insn (copy_rtx (dest
),
6903 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6906 else if (ud3
== 0 && ud4
== 0)
6908 gcc_assert (ud2
& 0x8000);
6909 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
6912 emit_move_insn (copy_rtx (dest
),
6913 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6915 emit_move_insn (copy_rtx (dest
),
6916 gen_rtx_ZERO_EXTEND (DImode
,
6917 gen_lowpart (SImode
,
6920 else if ((ud4
== 0xffff && (ud3
& 0x8000))
6921 || (ud4
== 0 && ! (ud3
& 0x8000)))
6924 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
6927 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
6930 emit_move_insn (copy_rtx (dest
),
6931 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6933 emit_move_insn (copy_rtx (dest
),
6934 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
6937 emit_move_insn (copy_rtx (dest
),
6938 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6944 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
6947 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
6950 emit_move_insn (copy_rtx (dest
),
6951 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6954 emit_move_insn (copy_rtx (dest
),
6955 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
6958 emit_move_insn (copy_rtx (dest
),
6959 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6960 GEN_INT (ud2
<< 16)));
6962 emit_move_insn (copy_rtx (dest
),
6963 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
6969 /* Helper for the following. Get rid of [r+r] memory refs
6970 in cases where it won't work (TImode, TFmode, TDmode). */
6973 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
6975 if (reload_in_progress
)
6978 if (GET_CODE (operands
[0]) == MEM
6979 && GET_CODE (XEXP (operands
[0], 0)) != REG
6980 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
6981 GET_MODE (operands
[0]), false))
6983 = replace_equiv_address (operands
[0],
6984 copy_addr_to_reg (XEXP (operands
[0], 0)));
6986 if (GET_CODE (operands
[1]) == MEM
6987 && GET_CODE (XEXP (operands
[1], 0)) != REG
6988 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
6989 GET_MODE (operands
[1]), false))
6991 = replace_equiv_address (operands
[1],
6992 copy_addr_to_reg (XEXP (operands
[1], 0)));
6995 /* Emit a move from SOURCE to DEST in mode MODE. */
6997 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
7001 operands
[1] = source
;
7003 if (TARGET_DEBUG_ADDR
)
7006 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
7007 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
7008 GET_MODE_NAME (mode
),
7011 can_create_pseudo_p ());
7013 fprintf (stderr
, "source:\n");
7017 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
7018 if (GET_CODE (operands
[1]) == CONST_DOUBLE
7019 && ! FLOAT_MODE_P (mode
)
7020 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
7022 /* FIXME. This should never happen. */
7023 /* Since it seems that it does, do the safe thing and convert
7025 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
7027 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
7028 || FLOAT_MODE_P (mode
)
7029 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
7030 || CONST_DOUBLE_LOW (operands
[1]) < 0)
7031 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
7032 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
7034 /* Check if GCC is setting up a block move that will end up using FP
7035 registers as temporaries. We must make sure this is acceptable. */
7036 if (GET_CODE (operands
[0]) == MEM
7037 && GET_CODE (operands
[1]) == MEM
7039 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
7040 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
7041 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
7042 ? 32 : MEM_ALIGN (operands
[0])))
7043 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
7045 : MEM_ALIGN (operands
[1]))))
7046 && ! MEM_VOLATILE_P (operands
[0])
7047 && ! MEM_VOLATILE_P (operands
[1]))
7049 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
7050 adjust_address (operands
[1], SImode
, 0));
7051 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
7052 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
7056 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
7057 && !gpc_reg_operand (operands
[1], mode
))
7058 operands
[1] = force_reg (mode
, operands
[1]);
7060 /* Recognize the case where operand[1] is a reference to thread-local
7061 data and load its address to a register. */
7062 if (rs6000_tls_referenced_p (operands
[1]))
7064 enum tls_model model
;
7065 rtx tmp
= operands
[1];
7068 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
7070 addend
= XEXP (XEXP (tmp
, 0), 1);
7071 tmp
= XEXP (XEXP (tmp
, 0), 0);
7074 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
7075 model
= SYMBOL_REF_TLS_MODEL (tmp
);
7076 gcc_assert (model
!= 0);
7078 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
7081 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
7082 tmp
= force_operand (tmp
, operands
[0]);
7087 /* Handle the case where reload calls us with an invalid address. */
7088 if (reload_in_progress
&& mode
== Pmode
7089 && (! general_operand (operands
[1], mode
)
7090 || ! nonimmediate_operand (operands
[0], mode
)))
7093 /* 128-bit constant floating-point values on Darwin should really be
7094 loaded as two parts. */
7095 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
7096 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
7098 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
7099 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
7101 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
7102 GET_MODE_SIZE (DFmode
)),
7103 simplify_gen_subreg (DFmode
, operands
[1], mode
,
7104 GET_MODE_SIZE (DFmode
)),
7109 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
7110 cfun
->machine
->sdmode_stack_slot
=
7111 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
7113 if (reload_in_progress
7115 && MEM_P (operands
[0])
7116 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
7117 && REG_P (operands
[1]))
7119 if (FP_REGNO_P (REGNO (operands
[1])))
7121 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
7122 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7123 emit_insn (gen_movsd_store (mem
, operands
[1]));
7125 else if (INT_REGNO_P (REGNO (operands
[1])))
7127 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
7128 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7129 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
7135 if (reload_in_progress
7137 && REG_P (operands
[0])
7138 && MEM_P (operands
[1])
7139 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
7141 if (FP_REGNO_P (REGNO (operands
[0])))
7143 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
7144 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7145 emit_insn (gen_movsd_load (operands
[0], mem
));
7147 else if (INT_REGNO_P (REGNO (operands
[0])))
7149 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
7150 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7151 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
7158 /* FIXME: In the long term, this switch statement should go away
7159 and be replaced by a sequence of tests based on things like
7165 if (CONSTANT_P (operands
[1])
7166 && GET_CODE (operands
[1]) != CONST_INT
)
7167 operands
[1] = force_const_mem (mode
, operands
[1]);
7172 rs6000_eliminate_indexed_memrefs (operands
);
7179 if (CONSTANT_P (operands
[1])
7180 && ! easy_fp_constant (operands
[1], mode
))
7181 operands
[1] = force_const_mem (mode
, operands
[1]);
7194 if (CONSTANT_P (operands
[1])
7195 && !easy_vector_constant (operands
[1], mode
))
7196 operands
[1] = force_const_mem (mode
, operands
[1]);
7201 /* Use default pattern for address of ELF small data */
7204 && DEFAULT_ABI
== ABI_V4
7205 && (GET_CODE (operands
[1]) == SYMBOL_REF
7206 || GET_CODE (operands
[1]) == CONST
)
7207 && small_data_operand (operands
[1], mode
))
7209 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7213 if (DEFAULT_ABI
== ABI_V4
7214 && mode
== Pmode
&& mode
== SImode
7215 && flag_pic
== 1 && got_operand (operands
[1], mode
))
7217 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
7221 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
7225 && CONSTANT_P (operands
[1])
7226 && GET_CODE (operands
[1]) != HIGH
7227 && GET_CODE (operands
[1]) != CONST_INT
)
7229 rtx target
= (!can_create_pseudo_p ()
7231 : gen_reg_rtx (mode
));
7233 /* If this is a function address on -mcall-aixdesc,
7234 convert it to the address of the descriptor. */
7235 if (DEFAULT_ABI
== ABI_AIX
7236 && GET_CODE (operands
[1]) == SYMBOL_REF
7237 && XSTR (operands
[1], 0)[0] == '.')
7239 const char *name
= XSTR (operands
[1], 0);
7241 while (*name
== '.')
7243 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
7244 CONSTANT_POOL_ADDRESS_P (new_ref
)
7245 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
7246 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
7247 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
7248 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
7249 operands
[1] = new_ref
;
7252 if (DEFAULT_ABI
== ABI_DARWIN
)
7255 if (MACHO_DYNAMIC_NO_PIC_P
)
7257 /* Take care of any required data indirection. */
7258 operands
[1] = rs6000_machopic_legitimize_pic_address (
7259 operands
[1], mode
, operands
[0]);
7260 if (operands
[0] != operands
[1])
7261 emit_insn (gen_rtx_SET (VOIDmode
,
7262 operands
[0], operands
[1]));
7266 emit_insn (gen_macho_high (target
, operands
[1]));
7267 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
7271 emit_insn (gen_elf_high (target
, operands
[1]));
7272 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
7276 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7277 and we have put it in the TOC, we just need to make a TOC-relative
7280 && GET_CODE (operands
[1]) == SYMBOL_REF
7281 && use_toc_relative_ref (operands
[1]))
7282 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
7283 else if (mode
== Pmode
7284 && CONSTANT_P (operands
[1])
7285 && GET_CODE (operands
[1]) != HIGH
7286 && ((GET_CODE (operands
[1]) != CONST_INT
7287 && ! easy_fp_constant (operands
[1], mode
))
7288 || (GET_CODE (operands
[1]) == CONST_INT
7289 && (num_insns_constant (operands
[1], mode
)
7290 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
7291 || (GET_CODE (operands
[0]) == REG
7292 && FP_REGNO_P (REGNO (operands
[0]))))
7293 && !toc_relative_expr_p (operands
[1], false)
7294 && (TARGET_CMODEL
== CMODEL_SMALL
7295 || can_create_pseudo_p ()
7296 || (REG_P (operands
[0])
7297 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
7301 /* Darwin uses a special PIC legitimizer. */
7302 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
7305 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
7307 if (operands
[0] != operands
[1])
7308 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7313 /* If we are to limit the number of things we put in the TOC and
7314 this is a symbol plus a constant we can add in one insn,
7315 just put the symbol in the TOC and add the constant. Don't do
7316 this if reload is in progress. */
7317 if (GET_CODE (operands
[1]) == CONST
7318 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
7319 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
7320 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
7321 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
7322 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
7323 && ! side_effects_p (operands
[0]))
7326 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
7327 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
7329 sym
= force_reg (mode
, sym
);
7330 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
7334 operands
[1] = force_const_mem (mode
, operands
[1]);
7337 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
7338 && constant_pool_expr_p (XEXP (operands
[1], 0))
7339 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7340 get_pool_constant (XEXP (operands
[1], 0)),
7341 get_pool_mode (XEXP (operands
[1], 0))))
7343 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
7345 operands
[1] = gen_const_mem (mode
, tocref
);
7346 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
7352 rs6000_eliminate_indexed_memrefs (operands
);
7356 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
7359 /* Above, we may have called force_const_mem which may have returned
7360 an invalid address. If we can, fix this up; otherwise, reload will
7361 have to deal with it. */
7362 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
7363 operands
[1] = validize_mem (operands
[1]);
7366 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7369 /* Return true if a structure, union or array containing FIELD should be
7370 accessed using `BLKMODE'.
7372 For the SPE, simd types are V2SI, and gcc can be tempted to put the
7373 entire thing in a DI and use subregs to access the internals.
7374 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
7375 back-end. Because a single GPR can hold a V2SI, but not a DI, the
7376 best thing to do is set structs to BLKmode and avoid Severe Tire
7379 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
7380 fit into 1, whereas DI still needs two. */
7383 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
7385 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
7386 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
7389 /* Nonzero if we can use a floating-point register to pass this arg. */
7390 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7391 (SCALAR_FLOAT_MODE_P (MODE) \
7392 && (CUM)->fregno <= FP_ARG_MAX_REG \
7393 && TARGET_HARD_FLOAT && TARGET_FPRS)
7395 /* Nonzero if we can use an AltiVec register to pass this arg. */
7396 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7397 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7398 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7399 && TARGET_ALTIVEC_ABI \
7402 /* Return a nonzero value to say to return the function value in
7403 memory, just as large structures are always returned. TYPE will be
7404 the data type of the value, and FNTYPE will be the type of the
7405 function doing the returning, or @code{NULL} for libcalls.
7407 The AIX ABI for the RS/6000 specifies that all structures are
7408 returned in memory. The Darwin ABI does the same.
7410 For the Darwin 64 Bit ABI, a function result can be returned in
7411 registers or in memory, depending on the size of the return data
7412 type. If it is returned in registers, the value occupies the same
7413 registers as it would if it were the first and only function
7414 argument. Otherwise, the function places its result in memory at
7415 the location pointed to by GPR3.
7417 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7418 but a draft put them in memory, and GCC used to implement the draft
7419 instead of the final standard. Therefore, aix_struct_return
7420 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7421 compatibility can change DRAFT_V4_STRUCT_RET to override the
7422 default, and -m switches get the final word. See
7423 rs6000_option_override_internal for more details.
7425 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7426 long double support is enabled. These values are returned in memory.
7428 int_size_in_bytes returns -1 for variable size objects, which go in
7429 memory always. The cast to unsigned makes -1 > 8. */
7432 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7434 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7436 && rs6000_darwin64_abi
7437 && TREE_CODE (type
) == RECORD_TYPE
7438 && int_size_in_bytes (type
) > 0)
7440 CUMULATIVE_ARGS valcum
;
7444 valcum
.fregno
= FP_ARG_MIN_REG
;
7445 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
7446 /* Do a trial code generation as if this were going to be passed
7447 as an argument; if any part goes in memory, we return NULL. */
7448 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
7451 /* Otherwise fall through to more conventional ABI rules. */
7454 if (AGGREGATE_TYPE_P (type
)
7455 && (aix_struct_return
7456 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
7459 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7460 modes only exist for GCC vector types if -maltivec. */
7461 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
7462 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
7465 /* Return synthetic vectors in memory. */
7466 if (TREE_CODE (type
) == VECTOR_TYPE
7467 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
7469 static bool warned_for_return_big_vectors
= false;
7470 if (!warned_for_return_big_vectors
)
7472 warning (0, "GCC vector returned by reference: "
7473 "non-standard ABI extension with no compatibility guarantee");
7474 warned_for_return_big_vectors
= true;
7479 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
7485 #ifdef HAVE_AS_GNU_ATTRIBUTE
7486 /* Return TRUE if a call to function FNDECL may be one that
7487 potentially affects the function calling ABI of the object file. */
7490 call_ABI_of_interest (tree fndecl
)
7492 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
7494 struct cgraph_node
*c_node
;
7496 /* Libcalls are always interesting. */
7497 if (fndecl
== NULL_TREE
)
7500 /* Any call to an external function is interesting. */
7501 if (DECL_EXTERNAL (fndecl
))
7504 /* Interesting functions that we are emitting in this object file. */
7505 c_node
= cgraph_get_node (fndecl
);
7506 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
7507 return !cgraph_only_called_directly_p (c_node
);
7513 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7514 for a call to a function whose data type is FNTYPE.
7515 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7517 For incoming args we set the number of arguments in the prototype large
7518 so we never return a PARALLEL. */
7521 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
7522 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
7523 int libcall
, int n_named_args
,
7524 tree fndecl ATTRIBUTE_UNUSED
,
7525 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
7527 static CUMULATIVE_ARGS zero_cumulative
;
7529 *cum
= zero_cumulative
;
7531 cum
->fregno
= FP_ARG_MIN_REG
;
7532 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
7533 cum
->prototype
= (fntype
&& prototype_p (fntype
));
7534 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
7535 ? CALL_LIBCALL
: CALL_NORMAL
);
7536 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
7537 cum
->stdarg
= stdarg_p (fntype
);
7539 cum
->nargs_prototype
= 0;
7540 if (incoming
|| cum
->prototype
)
7541 cum
->nargs_prototype
= n_named_args
;
7543 /* Check for a longcall attribute. */
7544 if ((!fntype
&& rs6000_default_long_calls
)
7546 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
7547 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
7548 cum
->call_cookie
|= CALL_LONG
;
7550 if (TARGET_DEBUG_ARG
)
7552 fprintf (stderr
, "\ninit_cumulative_args:");
7555 tree ret_type
= TREE_TYPE (fntype
);
7556 fprintf (stderr
, " ret code = %s,",
7557 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
7560 if (cum
->call_cookie
& CALL_LONG
)
7561 fprintf (stderr
, " longcall,");
7563 fprintf (stderr
, " proto = %d, nargs = %d\n",
7564 cum
->prototype
, cum
->nargs_prototype
);
7567 #ifdef HAVE_AS_GNU_ATTRIBUTE
7568 if (DEFAULT_ABI
== ABI_V4
)
7570 cum
->escapes
= call_ABI_of_interest (fndecl
);
7577 return_type
= TREE_TYPE (fntype
);
7578 return_mode
= TYPE_MODE (return_type
);
7581 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
7583 if (return_type
!= NULL
)
7585 if (TREE_CODE (return_type
) == RECORD_TYPE
7586 && TYPE_TRANSPARENT_AGGR (return_type
))
7588 return_type
= TREE_TYPE (first_field (return_type
));
7589 return_mode
= TYPE_MODE (return_type
);
7591 if (AGGREGATE_TYPE_P (return_type
)
7592 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
7594 rs6000_returns_struct
= true;
7596 if (SCALAR_FLOAT_MODE_P (return_mode
))
7597 rs6000_passes_float
= true;
7598 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
7599 || SPE_VECTOR_MODE (return_mode
))
7600 rs6000_passes_vector
= true;
7607 && TARGET_ALTIVEC_ABI
7608 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
7610 error ("cannot return value in vector register because"
7611 " altivec instructions are disabled, use -maltivec"
7616 /* Return true if TYPE must be passed on the stack and not in registers. */
7619 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
7621 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
7622 return must_pass_in_stack_var_size (mode
, type
);
7624 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7627 /* If defined, a C expression which determines whether, and in which
7628 direction, to pad out an argument with extra space. The value
7629 should be of type `enum direction': either `upward' to pad above
7630 the argument, `downward' to pad below, or `none' to inhibit
7633 For the AIX ABI structs are always stored left shifted in their
7637 function_arg_padding (enum machine_mode mode
, const_tree type
)
7639 #ifndef AGGREGATE_PADDING_FIXED
7640 #define AGGREGATE_PADDING_FIXED 0
7642 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7643 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7646 if (!AGGREGATE_PADDING_FIXED
)
7648 /* GCC used to pass structures of the same size as integer types as
7649 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7650 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7651 passed padded downward, except that -mstrict-align further
7652 muddied the water in that multi-component structures of 2 and 4
7653 bytes in size were passed padded upward.
7655 The following arranges for best compatibility with previous
7656 versions of gcc, but removes the -mstrict-align dependency. */
7657 if (BYTES_BIG_ENDIAN
)
7659 HOST_WIDE_INT size
= 0;
7661 if (mode
== BLKmode
)
7663 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
7664 size
= int_size_in_bytes (type
);
7667 size
= GET_MODE_SIZE (mode
);
7669 if (size
== 1 || size
== 2 || size
== 4)
7675 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
7677 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
7681 /* Fall back to the default. */
7682 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7685 /* If defined, a C expression that gives the alignment boundary, in bits,
7686 of an argument with the specified mode and type. If it is not defined,
7687 PARM_BOUNDARY is used for all arguments.
7689 V.4 wants long longs and doubles to be double word aligned. Just
7690 testing the mode size is a boneheaded way to do this as it means
7691 that other types such as complex int are also double word aligned.
7692 However, we're stuck with this because changing the ABI might break
7693 existing library interfaces.
7695 Doubleword align SPE vectors.
7696 Quadword align Altivec/VSX vectors.
7697 Quadword align large synthetic vector types. */
7700 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
7702 if (DEFAULT_ABI
== ABI_V4
7703 && (GET_MODE_SIZE (mode
) == 8
7704 || (TARGET_HARD_FLOAT
7706 && (mode
== TFmode
|| mode
== TDmode
))))
7708 else if (SPE_VECTOR_MODE (mode
)
7709 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7710 && int_size_in_bytes (type
) >= 8
7711 && int_size_in_bytes (type
) < 16))
7713 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7714 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7715 && int_size_in_bytes (type
) >= 16))
7717 else if (TARGET_MACHO
7718 && rs6000_darwin64_abi
7720 && type
&& TYPE_ALIGN (type
) > 64)
7723 return PARM_BOUNDARY
;
7726 /* For a function parm of MODE and TYPE, return the starting word in
7727 the parameter area. NWORDS of the parameter area are already used. */
7730 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
7731 unsigned int nwords
)
7734 unsigned int parm_offset
;
7736 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
7737 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
7738 return nwords
+ (-(parm_offset
+ nwords
) & align
);
7741 /* Compute the size (in words) of a function argument. */
7743 static unsigned long
7744 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
7748 if (mode
!= BLKmode
)
7749 size
= GET_MODE_SIZE (mode
);
7751 size
= int_size_in_bytes (type
);
7754 return (size
+ 3) >> 2;
7756 return (size
+ 7) >> 3;
7759 /* Use this to flush pending int fields. */
7762 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
7763 HOST_WIDE_INT bitpos
, int final
)
7765 unsigned int startbit
, endbit
;
7766 int intregs
, intoffset
;
7767 enum machine_mode mode
;
7769 /* Handle the situations where a float is taking up the first half
7770 of the GPR, and the other half is empty (typically due to
7771 alignment restrictions). We can detect this by a 8-byte-aligned
7772 int field, or by seeing that this is the final flush for this
7773 argument. Count the word and continue on. */
7774 if (cum
->floats_in_gpr
== 1
7775 && (cum
->intoffset
% 64 == 0
7776 || (cum
->intoffset
== -1 && final
)))
7779 cum
->floats_in_gpr
= 0;
7782 if (cum
->intoffset
== -1)
7785 intoffset
= cum
->intoffset
;
7786 cum
->intoffset
= -1;
7787 cum
->floats_in_gpr
= 0;
7789 if (intoffset
% BITS_PER_WORD
!= 0)
7791 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
7793 if (mode
== BLKmode
)
7795 /* We couldn't find an appropriate mode, which happens,
7796 e.g., in packed structs when there are 3 bytes to load.
7797 Back intoffset back to the beginning of the word in this
7799 intoffset
= intoffset
& -BITS_PER_WORD
;
7803 startbit
= intoffset
& -BITS_PER_WORD
;
7804 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
7805 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
7806 cum
->words
+= intregs
;
7807 /* words should be unsigned. */
7808 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
7810 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
7815 /* The darwin64 ABI calls for us to recurse down through structs,
7816 looking for elements passed in registers. Unfortunately, we have
7817 to track int register count here also because of misalignments
7818 in powerpc alignment mode. */
7821 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
7823 HOST_WIDE_INT startbitpos
)
7827 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
7828 if (TREE_CODE (f
) == FIELD_DECL
)
7830 HOST_WIDE_INT bitpos
= startbitpos
;
7831 tree ftype
= TREE_TYPE (f
);
7832 enum machine_mode mode
;
7833 if (ftype
== error_mark_node
)
7835 mode
= TYPE_MODE (ftype
);
7837 if (DECL_SIZE (f
) != 0
7838 && host_integerp (bit_position (f
), 1))
7839 bitpos
+= int_bit_position (f
);
7841 /* ??? FIXME: else assume zero offset. */
7843 if (TREE_CODE (ftype
) == RECORD_TYPE
)
7844 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
7845 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
7847 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
7848 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
7849 cum
->fregno
+= n_fpregs
;
7850 /* Single-precision floats present a special problem for
7851 us, because they are smaller than an 8-byte GPR, and so
7852 the structure-packing rules combined with the standard
7853 varargs behavior mean that we want to pack float/float
7854 and float/int combinations into a single register's
7855 space. This is complicated by the arg advance flushing,
7856 which works on arbitrarily large groups of int-type
7860 if (cum
->floats_in_gpr
== 1)
7862 /* Two floats in a word; count the word and reset
7865 cum
->floats_in_gpr
= 0;
7867 else if (bitpos
% 64 == 0)
7869 /* A float at the beginning of an 8-byte word;
7870 count it and put off adjusting cum->words until
7871 we see if a arg advance flush is going to do it
7873 cum
->floats_in_gpr
++;
7877 /* The float is at the end of a word, preceded
7878 by integer fields, so the arg advance flush
7879 just above has already set cum->words and
7880 everything is taken care of. */
7884 cum
->words
+= n_fpregs
;
7886 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
7888 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
7892 else if (cum
->intoffset
== -1)
7893 cum
->intoffset
= bitpos
;
7897 /* Check for an item that needs to be considered specially under the darwin 64
7898 bit ABI. These are record types where the mode is BLK or the structure is
7901 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
7903 return rs6000_darwin64_abi
7904 && ((mode
== BLKmode
7905 && TREE_CODE (type
) == RECORD_TYPE
7906 && int_size_in_bytes (type
) > 0)
7907 || (type
&& TREE_CODE (type
) == RECORD_TYPE
7908 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
7911 /* Update the data in CUM to advance over an argument
7912 of mode MODE and data type TYPE.
7913 (TYPE is null for libcalls where that information may not be available.)
7915 Note that for args passed by reference, function_arg will be called
7916 with MODE and TYPE set to that of the pointer to the arg, not the arg
7920 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
7921 const_tree type
, bool named
, int depth
)
7923 /* Only tick off an argument if we're not recursing. */
7925 cum
->nargs_prototype
--;
7927 #ifdef HAVE_AS_GNU_ATTRIBUTE
7928 if (DEFAULT_ABI
== ABI_V4
7931 if (SCALAR_FLOAT_MODE_P (mode
))
7932 rs6000_passes_float
= true;
7933 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
7934 rs6000_passes_vector
= true;
7935 else if (SPE_VECTOR_MODE (mode
)
7937 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
7938 rs6000_passes_vector
= true;
7942 if (TARGET_ALTIVEC_ABI
7943 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7944 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7945 && int_size_in_bytes (type
) == 16)))
7949 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
7952 if (!TARGET_ALTIVEC
)
7953 error ("cannot pass argument in vector register because"
7954 " altivec instructions are disabled, use -maltivec"
7957 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7958 even if it is going to be passed in a vector register.
7959 Darwin does the same for variable-argument functions. */
7960 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
7961 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
7971 /* Vector parameters must be 16-byte aligned. This places
7972 them at 2 mod 4 in terms of words in 32-bit mode, since
7973 the parameter save area starts at offset 24 from the
7974 stack. In 64-bit mode, they just have to start on an
7975 even word, since the parameter save area is 16-byte
7976 aligned. Space for GPRs is reserved even if the argument
7977 will be passed in memory. */
7979 align
= (2 - cum
->words
) & 3;
7981 align
= cum
->words
& 1;
7982 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
7984 if (TARGET_DEBUG_ARG
)
7986 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
7988 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
7989 cum
->nargs_prototype
, cum
->prototype
,
7990 GET_MODE_NAME (mode
));
7994 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
7996 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
7999 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8001 int size
= int_size_in_bytes (type
);
8002 /* Variable sized types have size == -1 and are
8003 treated as if consisting entirely of ints.
8004 Pad to 16 byte boundary if needed. */
8005 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8006 && (cum
->words
% 2) != 0)
8008 /* For varargs, we can just go up by the size of the struct. */
8010 cum
->words
+= (size
+ 7) / 8;
8013 /* It is tempting to say int register count just goes up by
8014 sizeof(type)/8, but this is wrong in a case such as
8015 { int; double; int; } [powerpc alignment]. We have to
8016 grovel through the fields for these too. */
8018 cum
->floats_in_gpr
= 0;
8019 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
8020 rs6000_darwin64_record_arg_advance_flush (cum
,
8021 size
* BITS_PER_UNIT
, 1);
8023 if (TARGET_DEBUG_ARG
)
8025 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
8026 cum
->words
, TYPE_ALIGN (type
), size
);
8028 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
8029 cum
->nargs_prototype
, cum
->prototype
,
8030 GET_MODE_NAME (mode
));
8033 else if (DEFAULT_ABI
== ABI_V4
)
8035 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8036 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8037 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8038 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8039 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8041 /* _Decimal128 must use an even/odd register pair. This assumes
8042 that the register number is odd when fregno is odd. */
8043 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8046 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8047 <= FP_ARG_V4_MAX_REG
)
8048 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8051 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
8052 if (mode
== DFmode
|| mode
== TFmode
8053 || mode
== DDmode
|| mode
== TDmode
)
8054 cum
->words
+= cum
->words
& 1;
8055 cum
->words
+= rs6000_arg_size (mode
, type
);
8060 int n_words
= rs6000_arg_size (mode
, type
);
8061 int gregno
= cum
->sysv_gregno
;
8063 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8064 (r7,r8) or (r9,r10). As does any other 2 word item such
8065 as complex int due to a historical mistake. */
8067 gregno
+= (1 - gregno
) & 1;
8069 /* Multi-reg args are not split between registers and stack. */
8070 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8072 /* Long long and SPE vectors are aligned on the stack.
8073 So are other 2 word items such as complex int due to
8074 a historical mistake. */
8076 cum
->words
+= cum
->words
& 1;
8077 cum
->words
+= n_words
;
8080 /* Note: continuing to accumulate gregno past when we've started
8081 spilling to the stack indicates the fact that we've started
8082 spilling to the stack to expand_builtin_saveregs. */
8083 cum
->sysv_gregno
= gregno
+ n_words
;
8086 if (TARGET_DEBUG_ARG
)
8088 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8089 cum
->words
, cum
->fregno
);
8090 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
8091 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
8092 fprintf (stderr
, "mode = %4s, named = %d\n",
8093 GET_MODE_NAME (mode
), named
);
8098 int n_words
= rs6000_arg_size (mode
, type
);
8099 int start_words
= cum
->words
;
8100 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
8102 cum
->words
= align_words
+ n_words
;
8104 if (SCALAR_FLOAT_MODE_P (mode
)
8105 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8107 /* _Decimal128 must be passed in an even/odd float register pair.
8108 This assumes that the register number is odd when fregno is
8110 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8112 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8115 if (TARGET_DEBUG_ARG
)
8117 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8118 cum
->words
, cum
->fregno
);
8119 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
8120 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
8121 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
8122 named
, align_words
- start_words
, depth
);
8128 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
8129 const_tree type
, bool named
)
8131 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
8136 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
8143 r1
= gen_rtx_REG (DImode
, gregno
);
8144 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8145 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
8149 r1
= gen_rtx_REG (DImode
, gregno
);
8150 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8151 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8152 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8153 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
8156 r1
= gen_rtx_REG (DImode
, gregno
);
8157 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8158 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8159 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8160 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
8161 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
8162 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
8163 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
8164 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
8171 /* Determine where to put a SIMD argument on the SPE. */
8173 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8176 int gregno
= cum
->sysv_gregno
;
8178 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8179 are passed and returned in a pair of GPRs for ABI compatibility. */
8180 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
8181 || mode
== DCmode
|| mode
== TCmode
))
8183 int n_words
= rs6000_arg_size (mode
, type
);
8185 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8187 gregno
+= (1 - gregno
) & 1;
8189 /* Multi-reg args are not split between registers and stack. */
8190 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8193 return spe_build_register_parallel (mode
, gregno
);
8197 int n_words
= rs6000_arg_size (mode
, type
);
8199 /* SPE vectors are put in odd registers. */
8200 if (n_words
== 2 && (gregno
& 1) == 0)
8203 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
8206 enum machine_mode m
= SImode
;
8208 r1
= gen_rtx_REG (m
, gregno
);
8209 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
8210 r2
= gen_rtx_REG (m
, gregno
+ 1);
8211 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
8212 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
8219 if (gregno
<= GP_ARG_MAX_REG
)
8220 return gen_rtx_REG (mode
, gregno
);
8226 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8227 structure between cum->intoffset and bitpos to integer registers. */
8230 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
8231 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
8233 enum machine_mode mode
;
8235 unsigned int startbit
, endbit
;
8236 int this_regno
, intregs
, intoffset
;
8239 if (cum
->intoffset
== -1)
8242 intoffset
= cum
->intoffset
;
8243 cum
->intoffset
= -1;
8245 /* If this is the trailing part of a word, try to only load that
8246 much into the register. Otherwise load the whole register. Note
8247 that in the latter case we may pick up unwanted bits. It's not a
8248 problem at the moment but may wish to revisit. */
8250 if (intoffset
% BITS_PER_WORD
!= 0)
8252 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8254 if (mode
== BLKmode
)
8256 /* We couldn't find an appropriate mode, which happens,
8257 e.g., in packed structs when there are 3 bytes to load.
8258 Back intoffset back to the beginning of the word in this
8260 intoffset
= intoffset
& -BITS_PER_WORD
;
8267 startbit
= intoffset
& -BITS_PER_WORD
;
8268 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8269 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8270 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
8272 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
8275 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
8279 intoffset
/= BITS_PER_UNIT
;
8282 regno
= GP_ARG_MIN_REG
+ this_regno
;
8283 reg
= gen_rtx_REG (mode
, regno
);
8285 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
8288 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
8292 while (intregs
> 0);
8295 /* Recursive workhorse for the following. */
8298 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
8299 HOST_WIDE_INT startbitpos
, rtx rvec
[],
8304 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8305 if (TREE_CODE (f
) == FIELD_DECL
)
8307 HOST_WIDE_INT bitpos
= startbitpos
;
8308 tree ftype
= TREE_TYPE (f
);
8309 enum machine_mode mode
;
8310 if (ftype
== error_mark_node
)
8312 mode
= TYPE_MODE (ftype
);
8314 if (DECL_SIZE (f
) != 0
8315 && host_integerp (bit_position (f
), 1))
8316 bitpos
+= int_bit_position (f
);
8318 /* ??? FIXME: else assume zero offset. */
8320 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8321 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
8322 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8324 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8328 case SCmode
: mode
= SFmode
; break;
8329 case DCmode
: mode
= DFmode
; break;
8330 case TCmode
: mode
= TFmode
; break;
8334 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8335 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8337 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8338 && (mode
== TFmode
|| mode
== TDmode
));
8339 /* Long double or _Decimal128 split over regs and memory. */
8340 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
8344 = gen_rtx_EXPR_LIST (VOIDmode
,
8345 gen_rtx_REG (mode
, cum
->fregno
++),
8346 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8347 if (mode
== TFmode
|| mode
== TDmode
)
8350 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
8352 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8354 = gen_rtx_EXPR_LIST (VOIDmode
,
8355 gen_rtx_REG (mode
, cum
->vregno
++),
8356 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8358 else if (cum
->intoffset
== -1)
8359 cum
->intoffset
= bitpos
;
8363 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8364 the register(s) to be used for each field and subfield of a struct
8365 being passed by value, along with the offset of where the
8366 register's value may be found in the block. FP fields go in FP
8367 register, vector fields go in vector registers, and everything
8368 else goes in int registers, packed as in memory.
8370 This code is also used for function return values. RETVAL indicates
8371 whether this is the case.
8373 Much of this is taken from the SPARC V9 port, which has a similar
8374 calling convention. */
8377 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
8378 bool named
, bool retval
)
8380 rtx rvec
[FIRST_PSEUDO_REGISTER
];
8381 int k
= 1, kbase
= 1;
8382 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
8383 /* This is a copy; modifications are not visible to our caller. */
8384 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
8385 CUMULATIVE_ARGS
*cum
= ©_cum
;
8387 /* Pad to 16 byte boundary if needed. */
8388 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8389 && (cum
->words
% 2) != 0)
8396 /* Put entries into rvec[] for individual FP and vector fields, and
8397 for the chunks of memory that go in int regs. Note we start at
8398 element 1; 0 is reserved for an indication of using memory, and
8399 may or may not be filled in below. */
8400 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
8401 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
8403 /* If any part of the struct went on the stack put all of it there.
8404 This hack is because the generic code for
8405 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8406 parts of the struct are not at the beginning. */
8410 return NULL_RTX
; /* doesn't go in registers at all */
8412 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8414 if (k
> 1 || cum
->use_stack
)
8415 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
8420 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8423 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
8428 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8430 if (align_words
>= GP_ARG_NUM_REG
)
8433 n_units
= rs6000_arg_size (mode
, type
);
8435 /* Optimize the simple case where the arg fits in one gpr, except in
8436 the case of BLKmode due to assign_parms assuming that registers are
8437 BITS_PER_WORD wide. */
8439 || (n_units
== 1 && mode
!= BLKmode
))
8440 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8443 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
8444 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8445 using a magic NULL_RTX component.
8446 This is not strictly correct. Only some of the arg belongs in
8447 memory, not all of it. However, the normal scheme using
8448 function_arg_partial_nregs can result in unusual subregs, eg.
8449 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8450 store the whole arg to memory is often more efficient than code
8451 to store pieces, and we know that space is available in the right
8452 place for the whole arg. */
8453 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8458 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
8459 rtx off
= GEN_INT (i
++ * 4);
8460 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
8462 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
8464 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
8467 /* Determine where to put an argument to a function.
8468 Value is zero to push the argument on the stack,
8469 or a hard register in which to store the argument.
8471 MODE is the argument's machine mode.
8472 TYPE is the data type of the argument (as a tree).
8473 This is null for libcalls where that information may
8475 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8476 the preceding args and about the function being called. It is
8477 not modified in this routine.
8478 NAMED is nonzero if this argument is a named parameter
8479 (otherwise it is an extra parameter matching an ellipsis).
8481 On RS/6000 the first eight words of non-FP are normally in registers
8482 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8483 Under V.4, the first 8 FP args are in registers.
8485 If this is floating-point and no prototype is specified, we use
8486 both an FP and integer register (or possibly FP reg and stack). Library
8487 functions (when CALL_LIBCALL is set) always have the proper types for args,
8488 so we can pass the FP value just in one register. emit_library_function
8489 doesn't support PARALLEL anyway.
8491 Note that for args passed by reference, function_arg will be called
8492 with MODE and TYPE set to that of the pointer to the arg, not the arg
8496 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
8497 const_tree type
, bool named
)
8499 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8500 enum rs6000_abi abi
= DEFAULT_ABI
;
8502 /* Return a marker to indicate whether CR1 needs to set or clear the
8503 bit that V.4 uses to say fp args were passed in registers.
8504 Assume that we don't need the marker for software floating point,
8505 or compiler generated library calls. */
8506 if (mode
== VOIDmode
)
8509 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
8511 || (cum
->nargs_prototype
< 0
8512 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
8514 /* For the SPE, we need to crxor CR6 always. */
8516 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
8517 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8518 return GEN_INT (cum
->call_cookie
8519 | ((cum
->fregno
== FP_ARG_MIN_REG
)
8520 ? CALL_V4_SET_FP_ARGS
8521 : CALL_V4_CLEAR_FP_ARGS
));
8524 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
8527 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8529 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
8530 if (rslt
!= NULL_RTX
)
8532 /* Else fall through to usual handling. */
8535 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
8536 if (TARGET_64BIT
&& ! cum
->prototype
)
8538 /* Vector parameters get passed in vector register
8539 and also in GPRs or memory, in absence of prototype. */
8542 align_words
= (cum
->words
+ 1) & ~1;
8544 if (align_words
>= GP_ARG_NUM_REG
)
8550 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8552 return gen_rtx_PARALLEL (mode
,
8554 gen_rtx_EXPR_LIST (VOIDmode
,
8556 gen_rtx_EXPR_LIST (VOIDmode
,
8557 gen_rtx_REG (mode
, cum
->vregno
),
8561 return gen_rtx_REG (mode
, cum
->vregno
);
8562 else if (TARGET_ALTIVEC_ABI
8563 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8564 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8565 && int_size_in_bytes (type
) == 16)))
8567 if (named
|| abi
== ABI_V4
)
8571 /* Vector parameters to varargs functions under AIX or Darwin
8572 get passed in memory and possibly also in GPRs. */
8573 int align
, align_words
, n_words
;
8574 enum machine_mode part_mode
;
8576 /* Vector parameters must be 16-byte aligned. This places them at
8577 2 mod 4 in terms of words in 32-bit mode, since the parameter
8578 save area starts at offset 24 from the stack. In 64-bit mode,
8579 they just have to start on an even word, since the parameter
8580 save area is 16-byte aligned. */
8582 align
= (2 - cum
->words
) & 3;
8584 align
= cum
->words
& 1;
8585 align_words
= cum
->words
+ align
;
8587 /* Out of registers? Memory, then. */
8588 if (align_words
>= GP_ARG_NUM_REG
)
8591 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8592 return rs6000_mixed_function_arg (mode
, type
, align_words
);
8594 /* The vector value goes in GPRs. Only the part of the
8595 value in GPRs is reported here. */
8597 n_words
= rs6000_arg_size (mode
, type
);
8598 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
8599 /* Fortunately, there are only two possibilities, the value
8600 is either wholly in GPRs or half in GPRs and half not. */
8603 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
8606 else if (TARGET_SPE_ABI
&& TARGET_SPE
8607 && (SPE_VECTOR_MODE (mode
)
8608 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
8611 || mode
== TCmode
))))
8612 return rs6000_spe_function_arg (cum
, mode
, type
);
8614 else if (abi
== ABI_V4
)
8616 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8617 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8618 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8619 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8620 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8622 /* _Decimal128 must use an even/odd register pair. This assumes
8623 that the register number is odd when fregno is odd. */
8624 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8627 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8628 <= FP_ARG_V4_MAX_REG
)
8629 return gen_rtx_REG (mode
, cum
->fregno
);
8635 int n_words
= rs6000_arg_size (mode
, type
);
8636 int gregno
= cum
->sysv_gregno
;
8638 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8639 (r7,r8) or (r9,r10). As does any other 2 word item such
8640 as complex int due to a historical mistake. */
8642 gregno
+= (1 - gregno
) & 1;
8644 /* Multi-reg args are not split between registers and stack. */
8645 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8648 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8649 return rs6000_mixed_function_arg (mode
, type
,
8650 gregno
- GP_ARG_MIN_REG
);
8651 return gen_rtx_REG (mode
, gregno
);
8656 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
8658 /* _Decimal128 must be passed in an even/odd float register pair.
8659 This assumes that the register number is odd when fregno is odd. */
8660 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8663 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
8665 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8669 enum machine_mode fmode
= mode
;
8670 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8672 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8674 /* Currently, we only ever need one reg here because complex
8675 doubles are split. */
8676 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8677 && (fmode
== TFmode
|| fmode
== TDmode
));
8679 /* Long double or _Decimal128 split over regs and memory. */
8680 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
8683 /* Do we also need to pass this arg in the parameter save
8686 && (cum
->nargs_prototype
<= 0
8687 || (DEFAULT_ABI
== ABI_AIX
8689 && align_words
>= GP_ARG_NUM_REG
)));
8691 if (!needs_psave
&& mode
== fmode
)
8692 return gen_rtx_REG (fmode
, cum
->fregno
);
8697 /* Describe the part that goes in gprs or the stack.
8698 This piece must come first, before the fprs. */
8699 if (align_words
< GP_ARG_NUM_REG
)
8701 unsigned long n_words
= rs6000_arg_size (mode
, type
);
8703 if (align_words
+ n_words
> GP_ARG_NUM_REG
8704 || (TARGET_32BIT
&& TARGET_POWERPC64
))
8706 /* If this is partially on the stack, then we only
8707 include the portion actually in registers here. */
8708 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
8711 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
8712 /* Not all of the arg fits in gprs. Say that it
8713 goes in memory too, using a magic NULL_RTX
8714 component. Also see comment in
8715 rs6000_mixed_function_arg for why the normal
8716 function_arg_partial_nregs scheme doesn't work
8718 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
8722 r
= gen_rtx_REG (rmode
,
8723 GP_ARG_MIN_REG
+ align_words
);
8724 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
8725 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
8727 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
8731 /* The whole arg fits in gprs. */
8732 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8733 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
8737 /* It's entirely in memory. */
8738 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8741 /* Describe where this piece goes in the fprs. */
8742 r
= gen_rtx_REG (fmode
, cum
->fregno
);
8743 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
8745 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
8747 else if (align_words
< GP_ARG_NUM_REG
)
8749 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8750 return rs6000_mixed_function_arg (mode
, type
, align_words
);
8752 if (mode
== BLKmode
)
8755 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8762 /* For an arg passed partly in registers and partly in memory, this is
8763 the number of bytes passed in registers. For args passed entirely in
8764 registers or entirely in memory, zero. When an arg is described by a
8765 PARALLEL, perhaps using more than one register type, this function
8766 returns the number of bytes used by the first element of the PARALLEL. */
8769 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
8770 tree type
, bool named
)
8772 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8776 if (DEFAULT_ABI
== ABI_V4
)
8779 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
8780 && cum
->nargs_prototype
>= 0)
8783 /* In this complicated case we just disable the partial_nregs code. */
8784 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8787 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
8789 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
8791 /* If we are passing this arg in the fixed parameter save area
8792 (gprs or memory) as well as fprs, then this function should
8793 return the number of partial bytes passed in the parameter
8794 save area rather than partial bytes passed in fprs. */
8796 && (cum
->nargs_prototype
<= 0
8797 || (DEFAULT_ABI
== ABI_AIX
8799 && align_words
>= GP_ARG_NUM_REG
)))
8801 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
8802 > FP_ARG_MAX_REG
+ 1)
8803 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
8804 else if (cum
->nargs_prototype
>= 0)
8808 if (align_words
< GP_ARG_NUM_REG
8809 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
8810 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
8812 if (ret
!= 0 && TARGET_DEBUG_ARG
)
8813 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
8818 /* A C expression that indicates when an argument must be passed by
8819 reference. If nonzero for an argument, a copy of that argument is
8820 made in memory and a pointer to the argument is passed instead of
8821 the argument itself. The pointer is passed in whatever way is
8822 appropriate for passing a pointer to that type.
8824 Under V.4, aggregates and long double are passed by reference.
8826 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8827 reference unless the AltiVec vector extension ABI is in force.
8829 As an extension to all ABIs, variable sized types are passed by
8833 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
8834 enum machine_mode mode
, const_tree type
,
8835 bool named ATTRIBUTE_UNUSED
)
8837 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
8839 if (TARGET_DEBUG_ARG
)
8840 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
8847 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
8849 if (TARGET_DEBUG_ARG
)
8850 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
8854 if (int_size_in_bytes (type
) < 0)
8856 if (TARGET_DEBUG_ARG
)
8857 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
8861 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8862 modes only exist for GCC vector types if -maltivec. */
8863 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
8865 if (TARGET_DEBUG_ARG
)
8866 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
8870 /* Pass synthetic vectors in memory. */
8871 if (TREE_CODE (type
) == VECTOR_TYPE
8872 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8874 static bool warned_for_pass_big_vectors
= false;
8875 if (TARGET_DEBUG_ARG
)
8876 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
8877 if (!warned_for_pass_big_vectors
)
8879 warning (0, "GCC vector passed by reference: "
8880 "non-standard ABI extension with no compatibility guarantee");
8881 warned_for_pass_big_vectors
= true;
8890 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
8893 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
8898 for (i
= 0; i
< nregs
; i
++)
8900 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
8901 if (reload_completed
)
8903 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
8906 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
8907 i
* GET_MODE_SIZE (reg_mode
));
8910 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
8914 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
8918 /* Perform any needed actions needed for a function that is receiving a
8919 variable number of arguments.
8923 MODE and TYPE are the mode and type of the current parameter.
8925 PRETEND_SIZE is a variable that should be set to the amount of stack
8926 that must be pushed by the prolog to pretend that our caller pushed
8929 Normally, this macro will push all remaining incoming registers on the
8930 stack and set PRETEND_SIZE to the length of the registers pushed. */
8933 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
8934 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
8937 CUMULATIVE_ARGS next_cum
;
8938 int reg_size
= TARGET_32BIT
? 4 : 8;
8939 rtx save_area
= NULL_RTX
, mem
;
8940 int first_reg_offset
;
8943 /* Skip the last named argument. */
8944 next_cum
= *get_cumulative_args (cum
);
8945 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
8947 if (DEFAULT_ABI
== ABI_V4
)
8949 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
8953 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
8954 HOST_WIDE_INT offset
= 0;
8956 /* Try to optimize the size of the varargs save area.
8957 The ABI requires that ap.reg_save_area is doubleword
8958 aligned, but we don't need to allocate space for all
8959 the bytes, only those to which we actually will save
8961 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
8962 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
8963 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8964 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
8965 && cfun
->va_list_fpr_size
)
8968 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
8969 * UNITS_PER_FP_WORD
;
8970 if (cfun
->va_list_fpr_size
8971 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
8972 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
8974 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
8975 * UNITS_PER_FP_WORD
;
8979 offset
= -((first_reg_offset
* reg_size
) & ~7);
8980 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
8982 gpr_reg_num
= cfun
->va_list_gpr_size
;
8983 if (reg_size
== 4 && (first_reg_offset
& 1))
8986 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
8989 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
8991 - (int) (GP_ARG_NUM_REG
* reg_size
);
8993 if (gpr_size
+ fpr_size
)
8996 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
8997 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
8998 reg_save_area
= XEXP (reg_save_area
, 0);
8999 if (GET_CODE (reg_save_area
) == PLUS
)
9001 gcc_assert (XEXP (reg_save_area
, 0)
9002 == virtual_stack_vars_rtx
);
9003 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
9004 offset
+= INTVAL (XEXP (reg_save_area
, 1));
9007 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
9010 cfun
->machine
->varargs_save_offset
= offset
;
9011 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
9016 first_reg_offset
= next_cum
.words
;
9017 save_area
= virtual_incoming_args_rtx
;
9019 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
9020 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
9023 set
= get_varargs_alias_set ();
9024 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
9025 && cfun
->va_list_gpr_size
)
9027 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
9029 if (va_list_gpr_counter_field
)
9031 /* V4 va_list_gpr_size counts number of registers needed. */
9032 if (nregs
> cfun
->va_list_gpr_size
)
9033 nregs
= cfun
->va_list_gpr_size
;
9037 /* char * va_list instead counts number of bytes needed. */
9038 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
9039 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
9042 mem
= gen_rtx_MEM (BLKmode
,
9043 plus_constant (Pmode
, save_area
,
9044 first_reg_offset
* reg_size
));
9045 MEM_NOTRAP_P (mem
) = 1;
9046 set_mem_alias_set (mem
, set
);
9047 set_mem_align (mem
, BITS_PER_WORD
);
9049 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
9053 /* Save FP registers if needed. */
9054 if (DEFAULT_ABI
== ABI_V4
9055 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9057 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9058 && cfun
->va_list_fpr_size
)
9060 int fregno
= next_cum
.fregno
, nregs
;
9061 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
9062 rtx lab
= gen_label_rtx ();
9063 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
9064 * UNITS_PER_FP_WORD
);
9067 (gen_rtx_SET (VOIDmode
,
9069 gen_rtx_IF_THEN_ELSE (VOIDmode
,
9070 gen_rtx_NE (VOIDmode
, cr1
,
9072 gen_rtx_LABEL_REF (VOIDmode
, lab
),
9076 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
9077 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
9079 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9081 plus_constant (Pmode
, save_area
, off
));
9082 MEM_NOTRAP_P (mem
) = 1;
9083 set_mem_alias_set (mem
, set
);
9084 set_mem_align (mem
, GET_MODE_ALIGNMENT (
9085 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9086 ? DFmode
: SFmode
));
9087 emit_move_insn (mem
, gen_rtx_REG (
9088 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9089 ? DFmode
: SFmode
, fregno
));
9096 /* Create the va_list data type. */
9099 rs6000_build_builtin_va_list (void)
9101 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
9103 /* For AIX, prefer 'char *' because that's what the system
9104 header files like. */
9105 if (DEFAULT_ABI
!= ABI_V4
)
9106 return build_pointer_type (char_type_node
);
9108 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
9109 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
9110 get_identifier ("__va_list_tag"), record
);
9112 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
9113 unsigned_char_type_node
);
9114 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
9115 unsigned_char_type_node
);
9116 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9118 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9119 get_identifier ("reserved"), short_unsigned_type_node
);
9120 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9121 get_identifier ("overflow_arg_area"),
9123 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9124 get_identifier ("reg_save_area"),
9127 va_list_gpr_counter_field
= f_gpr
;
9128 va_list_fpr_counter_field
= f_fpr
;
9130 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9131 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9132 DECL_FIELD_CONTEXT (f_res
) = record
;
9133 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9134 DECL_FIELD_CONTEXT (f_sav
) = record
;
9136 TYPE_STUB_DECL (record
) = type_decl
;
9137 TYPE_NAME (record
) = type_decl
;
9138 TYPE_FIELDS (record
) = f_gpr
;
9139 DECL_CHAIN (f_gpr
) = f_fpr
;
9140 DECL_CHAIN (f_fpr
) = f_res
;
9141 DECL_CHAIN (f_res
) = f_ovf
;
9142 DECL_CHAIN (f_ovf
) = f_sav
;
9144 layout_type (record
);
9146 /* The correct type is an array type of one element. */
9147 return build_array_type (record
, build_index_type (size_zero_node
));
9150 /* Implement va_start. */
9153 rs6000_va_start (tree valist
, rtx nextarg
)
9155 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
9156 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9157 tree gpr
, fpr
, ovf
, sav
, t
;
9159 /* Only SVR4 needs something special. */
9160 if (DEFAULT_ABI
!= ABI_V4
)
9162 std_expand_builtin_va_start (valist
, nextarg
);
9166 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9167 f_fpr
= DECL_CHAIN (f_gpr
);
9168 f_res
= DECL_CHAIN (f_fpr
);
9169 f_ovf
= DECL_CHAIN (f_res
);
9170 f_sav
= DECL_CHAIN (f_ovf
);
9172 valist
= build_simple_mem_ref (valist
);
9173 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9174 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9176 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9178 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9181 /* Count number of gp and fp argument registers used. */
9182 words
= crtl
->args
.info
.words
;
9183 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
9185 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
9188 if (TARGET_DEBUG_ARG
)
9189 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
9190 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
9191 words
, n_gpr
, n_fpr
);
9193 if (cfun
->va_list_gpr_size
)
9195 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9196 build_int_cst (NULL_TREE
, n_gpr
));
9197 TREE_SIDE_EFFECTS (t
) = 1;
9198 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9201 if (cfun
->va_list_fpr_size
)
9203 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9204 build_int_cst (NULL_TREE
, n_fpr
));
9205 TREE_SIDE_EFFECTS (t
) = 1;
9206 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9208 #ifdef HAVE_AS_GNU_ATTRIBUTE
9209 if (call_ABI_of_interest (cfun
->decl
))
9210 rs6000_passes_float
= true;
9214 /* Find the overflow area. */
9215 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9217 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
9218 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9219 TREE_SIDE_EFFECTS (t
) = 1;
9220 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9222 /* If there were no va_arg invocations, don't set up the register
9224 if (!cfun
->va_list_gpr_size
9225 && !cfun
->va_list_fpr_size
9226 && n_gpr
< GP_ARG_NUM_REG
9227 && n_fpr
< FP_ARG_V4_MAX_REG
)
9230 /* Find the register save area. */
9231 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
9232 if (cfun
->machine
->varargs_save_offset
)
9233 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
9234 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9235 TREE_SIDE_EFFECTS (t
) = 1;
9236 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9239 /* Implement va_arg. */
9242 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9245 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9246 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9247 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
9248 tree lab_false
, lab_over
, addr
;
9250 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9254 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9256 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
9257 return build_va_arg_indirect_ref (t
);
9260 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9261 earlier version of gcc, with the property that it always applied alignment
9262 adjustments to the va-args (even for zero-sized types). The cheapest way
9263 to deal with this is to replicate the effect of the part of
9264 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9266 We don't need to check for pass-by-reference because of the test above.
9267 We can return a simplifed answer, since we know there's no offset to add. */
9270 && rs6000_darwin64_abi
9271 && integer_zerop (TYPE_SIZE (type
)))
9273 unsigned HOST_WIDE_INT align
, boundary
;
9274 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
9275 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
9276 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
9277 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
9278 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
9279 boundary
/= BITS_PER_UNIT
;
9280 if (boundary
> align
)
9283 /* This updates arg ptr by the amount that would be necessary
9284 to align the zero-sized (but not zero-alignment) item. */
9285 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9286 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
9287 gimplify_and_add (t
, pre_p
);
9289 t
= fold_convert (sizetype
, valist_tmp
);
9290 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9291 fold_convert (TREE_TYPE (valist
),
9292 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
9293 size_int (-boundary
))));
9294 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
9295 gimplify_and_add (t
, pre_p
);
9297 /* Since it is zero-sized there's no increment for the item itself. */
9298 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
9299 return build_va_arg_indirect_ref (valist_tmp
);
9302 if (DEFAULT_ABI
!= ABI_V4
)
9304 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
9306 tree elem_type
= TREE_TYPE (type
);
9307 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
9308 int elem_size
= GET_MODE_SIZE (elem_mode
);
9310 if (elem_size
< UNITS_PER_WORD
)
9312 tree real_part
, imag_part
;
9313 gimple_seq post
= NULL
;
9315 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9317 /* Copy the value into a temporary, lest the formal temporary
9318 be reused out from under us. */
9319 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
9320 gimple_seq_add_seq (pre_p
, post
);
9322 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9325 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
9329 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
9332 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9333 f_fpr
= DECL_CHAIN (f_gpr
);
9334 f_res
= DECL_CHAIN (f_fpr
);
9335 f_ovf
= DECL_CHAIN (f_res
);
9336 f_sav
= DECL_CHAIN (f_ovf
);
9338 valist
= build_va_arg_indirect_ref (valist
);
9339 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9340 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9342 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9344 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9347 size
= int_size_in_bytes (type
);
9348 rsize
= (size
+ 3) / 4;
9351 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9352 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
9353 || (TARGET_DOUBLE_FLOAT
9354 && (TYPE_MODE (type
) == DFmode
9355 || TYPE_MODE (type
) == TFmode
9356 || TYPE_MODE (type
) == SDmode
9357 || TYPE_MODE (type
) == DDmode
9358 || TYPE_MODE (type
) == TDmode
))))
9360 /* FP args go in FP registers, if present. */
9362 n_reg
= (size
+ 7) / 8;
9363 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
9364 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
9365 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
9370 /* Otherwise into GP registers. */
9379 /* Pull the value out of the saved registers.... */
9382 addr
= create_tmp_var (ptr_type_node
, "addr");
9384 /* AltiVec vectors never go in registers when -mabi=altivec. */
9385 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9389 lab_false
= create_artificial_label (input_location
);
9390 lab_over
= create_artificial_label (input_location
);
9392 /* Long long and SPE vectors are aligned in the registers.
9393 As are any other 2 gpr item such as complex int due to a
9394 historical mistake. */
9396 if (n_reg
== 2 && reg
== gpr
)
9399 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9400 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
9401 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
9402 unshare_expr (reg
), u
);
9404 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9405 reg number is 0 for f1, so we want to make it odd. */
9406 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
9408 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9409 build_int_cst (TREE_TYPE (reg
), 1));
9410 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
9413 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
9414 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
9415 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9416 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9417 gimplify_and_add (t
, pre_p
);
9421 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9423 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9424 build_int_cst (TREE_TYPE (reg
), n_reg
));
9425 u
= fold_convert (sizetype
, u
);
9426 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
9427 t
= fold_build_pointer_plus (t
, u
);
9429 /* _Decimal32 varargs are located in the second word of the 64-bit
9430 FP register for 32-bit binaries. */
9431 if (!TARGET_POWERPC64
9432 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9433 && TYPE_MODE (type
) == SDmode
)
9434 t
= fold_build_pointer_plus_hwi (t
, size
);
9436 gimplify_assign (addr
, t
, pre_p
);
9438 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9440 stmt
= gimple_build_label (lab_false
);
9441 gimple_seq_add_stmt (pre_p
, stmt
);
9443 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
9445 /* Ensure that we don't find any more args in regs.
9446 Alignment has taken care of for special cases. */
9447 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
9451 /* ... otherwise out of the overflow area. */
9453 /* Care for on-stack alignment if needed. */
9457 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
9458 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
9459 build_int_cst (TREE_TYPE (t
), -align
));
9461 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9463 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
9465 t
= fold_build_pointer_plus_hwi (t
, size
);
9466 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
9470 stmt
= gimple_build_label (lab_over
);
9471 gimple_seq_add_stmt (pre_p
, stmt
);
9474 if (STRICT_ALIGNMENT
9475 && (TYPE_ALIGN (type
)
9476 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
9478 /* The value (of type complex double, for example) may not be
9479 aligned in memory in the saved registers, so copy via a
9480 temporary. (This is the same code as used for SPARC.) */
9481 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
9482 tree dest_addr
= build_fold_addr_expr (tmp
);
9484 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
9485 3, dest_addr
, addr
, size_int (rsize
* 4));
9487 gimplify_and_add (copy
, pre_p
);
9491 addr
= fold_convert (ptrtype
, addr
);
9492 return build_va_arg_indirect_ref (addr
);
9498 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
9501 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
9502 const char *attr_string
= "";
9504 gcc_assert (name
!= NULL
);
9505 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
9507 if (rs6000_builtin_decls
[(int)code
])
9508 fatal_error ("internal error: builtin function %s already processed", name
);
9510 rs6000_builtin_decls
[(int)code
] = t
=
9511 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
9513 /* Set any special attributes. */
9514 if ((classify
& RS6000_BTC_CONST
) != 0)
9516 /* const function, function only depends on the inputs. */
9517 TREE_READONLY (t
) = 1;
9518 TREE_NOTHROW (t
) = 1;
9519 attr_string
= ", pure";
9521 else if ((classify
& RS6000_BTC_PURE
) != 0)
9523 /* pure function, function can read global memory, but does not set any
9525 DECL_PURE_P (t
) = 1;
9526 TREE_NOTHROW (t
) = 1;
9527 attr_string
= ", const";
9529 else if ((classify
& RS6000_BTC_FP
) != 0)
9531 /* Function is a math function. If rounding mode is on, then treat the
9532 function as not reading global memory, but it can have arbitrary side
9533 effects. If it is off, then assume the function is a const function.
9534 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9535 builtin-attribute.def that is used for the math functions. */
9536 TREE_NOTHROW (t
) = 1;
9537 if (flag_rounding_math
)
9539 DECL_PURE_P (t
) = 1;
9540 DECL_IS_NOVOPS (t
) = 1;
9541 attr_string
= ", fp, pure";
9545 TREE_READONLY (t
) = 1;
9546 attr_string
= ", fp, const";
9549 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
9552 if (TARGET_DEBUG_BUILTIN
)
9553 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
9554 (int)code
, name
, attr_string
);
9557 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9559 #undef RS6000_BUILTIN_1
9560 #undef RS6000_BUILTIN_2
9561 #undef RS6000_BUILTIN_3
9562 #undef RS6000_BUILTIN_A
9563 #undef RS6000_BUILTIN_D
9564 #undef RS6000_BUILTIN_E
9565 #undef RS6000_BUILTIN_P
9566 #undef RS6000_BUILTIN_Q
9567 #undef RS6000_BUILTIN_S
9568 #undef RS6000_BUILTIN_X
9570 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9571 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9572 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9573 { MASK, ICODE, NAME, ENUM },
9575 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9576 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9577 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9578 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9579 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9580 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9581 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9583 static const struct builtin_description bdesc_3arg
[] =
9585 #include "rs6000-builtin.def"
9588 /* DST operations: void foo (void *, const int, const char). */
9590 #undef RS6000_BUILTIN_1
9591 #undef RS6000_BUILTIN_2
9592 #undef RS6000_BUILTIN_3
9593 #undef RS6000_BUILTIN_A
9594 #undef RS6000_BUILTIN_D
9595 #undef RS6000_BUILTIN_E
9596 #undef RS6000_BUILTIN_P
9597 #undef RS6000_BUILTIN_Q
9598 #undef RS6000_BUILTIN_S
9599 #undef RS6000_BUILTIN_X
9601 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9602 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9603 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9604 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9605 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9606 { MASK, ICODE, NAME, ENUM },
9608 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9609 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9610 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9611 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9612 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9614 static const struct builtin_description bdesc_dst
[] =
9616 #include "rs6000-builtin.def"
9619 /* Simple binary operations: VECc = foo (VECa, VECb). */
9621 #undef RS6000_BUILTIN_1
9622 #undef RS6000_BUILTIN_2
9623 #undef RS6000_BUILTIN_3
9624 #undef RS6000_BUILTIN_A
9625 #undef RS6000_BUILTIN_D
9626 #undef RS6000_BUILTIN_E
9627 #undef RS6000_BUILTIN_P
9628 #undef RS6000_BUILTIN_Q
9629 #undef RS6000_BUILTIN_S
9630 #undef RS6000_BUILTIN_X
9632 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9633 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9634 { MASK, ICODE, NAME, ENUM },
9636 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9637 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9638 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9639 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9640 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9641 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9642 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9643 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9645 static const struct builtin_description bdesc_2arg
[] =
9647 #include "rs6000-builtin.def"
9650 #undef RS6000_BUILTIN_1
9651 #undef RS6000_BUILTIN_2
9652 #undef RS6000_BUILTIN_3
9653 #undef RS6000_BUILTIN_A
9654 #undef RS6000_BUILTIN_D
9655 #undef RS6000_BUILTIN_E
9656 #undef RS6000_BUILTIN_P
9657 #undef RS6000_BUILTIN_Q
9658 #undef RS6000_BUILTIN_S
9659 #undef RS6000_BUILTIN_X
9661 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9662 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9663 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9664 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9665 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9666 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9667 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9668 { MASK, ICODE, NAME, ENUM },
9670 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9671 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9672 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9674 /* AltiVec predicates. */
9676 static const struct builtin_description bdesc_altivec_preds
[] =
9678 #include "rs6000-builtin.def"
9681 /* SPE predicates. */
9682 #undef RS6000_BUILTIN_1
9683 #undef RS6000_BUILTIN_2
9684 #undef RS6000_BUILTIN_3
9685 #undef RS6000_BUILTIN_A
9686 #undef RS6000_BUILTIN_D
9687 #undef RS6000_BUILTIN_E
9688 #undef RS6000_BUILTIN_P
9689 #undef RS6000_BUILTIN_Q
9690 #undef RS6000_BUILTIN_S
9691 #undef RS6000_BUILTIN_X
9693 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9694 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9695 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9696 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9697 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9698 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9699 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9700 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9701 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9702 { MASK, ICODE, NAME, ENUM },
9704 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9706 static const struct builtin_description bdesc_spe_predicates
[] =
9708 #include "rs6000-builtin.def"
9711 /* SPE evsel predicates. */
9712 #undef RS6000_BUILTIN_1
9713 #undef RS6000_BUILTIN_2
9714 #undef RS6000_BUILTIN_3
9715 #undef RS6000_BUILTIN_A
9716 #undef RS6000_BUILTIN_D
9717 #undef RS6000_BUILTIN_E
9718 #undef RS6000_BUILTIN_P
9719 #undef RS6000_BUILTIN_Q
9720 #undef RS6000_BUILTIN_S
9721 #undef RS6000_BUILTIN_X
9723 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9724 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9725 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9726 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9727 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9728 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9729 { MASK, ICODE, NAME, ENUM },
9731 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9732 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9733 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9734 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9736 static const struct builtin_description bdesc_spe_evsel
[] =
9738 #include "rs6000-builtin.def"
9741 /* PAIRED predicates. */
9742 #undef RS6000_BUILTIN_1
9743 #undef RS6000_BUILTIN_2
9744 #undef RS6000_BUILTIN_3
9745 #undef RS6000_BUILTIN_A
9746 #undef RS6000_BUILTIN_D
9747 #undef RS6000_BUILTIN_E
9748 #undef RS6000_BUILTIN_P
9749 #undef RS6000_BUILTIN_Q
9750 #undef RS6000_BUILTIN_S
9751 #undef RS6000_BUILTIN_X
9753 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9754 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9755 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9756 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9757 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9758 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9759 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9760 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9761 { MASK, ICODE, NAME, ENUM },
9763 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9764 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9766 static const struct builtin_description bdesc_paired_preds
[] =
9768 #include "rs6000-builtin.def"
9771 /* ABS* operations. */
9773 #undef RS6000_BUILTIN_1
9774 #undef RS6000_BUILTIN_2
9775 #undef RS6000_BUILTIN_3
9776 #undef RS6000_BUILTIN_A
9777 #undef RS6000_BUILTIN_D
9778 #undef RS6000_BUILTIN_E
9779 #undef RS6000_BUILTIN_P
9780 #undef RS6000_BUILTIN_Q
9781 #undef RS6000_BUILTIN_S
9782 #undef RS6000_BUILTIN_X
9784 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9785 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9786 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9787 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9788 { MASK, ICODE, NAME, ENUM },
9790 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9791 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9792 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9793 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9794 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9795 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9797 static const struct builtin_description bdesc_abs
[] =
9799 #include "rs6000-builtin.def"
9802 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9805 #undef RS6000_BUILTIN_1
9806 #undef RS6000_BUILTIN_2
9807 #undef RS6000_BUILTIN_3
9808 #undef RS6000_BUILTIN_A
9809 #undef RS6000_BUILTIN_E
9810 #undef RS6000_BUILTIN_D
9811 #undef RS6000_BUILTIN_P
9812 #undef RS6000_BUILTIN_Q
9813 #undef RS6000_BUILTIN_S
9814 #undef RS6000_BUILTIN_X
9816 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9817 { MASK, ICODE, NAME, ENUM },
9819 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9820 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9821 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9822 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9823 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9824 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9825 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9826 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9827 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9829 static const struct builtin_description bdesc_1arg
[] =
9831 #include "rs6000-builtin.def"
9834 #undef RS6000_BUILTIN_1
9835 #undef RS6000_BUILTIN_2
9836 #undef RS6000_BUILTIN_3
9837 #undef RS6000_BUILTIN_A
9838 #undef RS6000_BUILTIN_D
9839 #undef RS6000_BUILTIN_E
9840 #undef RS6000_BUILTIN_P
9841 #undef RS6000_BUILTIN_Q
9842 #undef RS6000_BUILTIN_S
9843 #undef RS6000_BUILTIN_X
9845 /* Return true if a builtin function is overloaded. */
9847 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
9849 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
9852 /* Expand an expression EXP that calls a builtin without arguments. */
9854 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
9857 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9859 if (icode
== CODE_FOR_nothing
)
9860 /* Builtin not supported on this processor. */
9864 || GET_MODE (target
) != tmode
9865 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9866 target
= gen_reg_rtx (tmode
);
9868 pat
= GEN_FCN (icode
) (target
);
9878 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
9881 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9882 rtx op0
= expand_normal (arg0
);
9883 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9884 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9886 if (icode
== CODE_FOR_nothing
)
9887 /* Builtin not supported on this processor. */
9890 /* If we got invalid arguments bail out before generating bad rtl. */
9891 if (arg0
== error_mark_node
)
9894 if (icode
== CODE_FOR_altivec_vspltisb
9895 || icode
== CODE_FOR_altivec_vspltish
9896 || icode
== CODE_FOR_altivec_vspltisw
9897 || icode
== CODE_FOR_spe_evsplatfi
9898 || icode
== CODE_FOR_spe_evsplati
)
9900 /* Only allow 5-bit *signed* literals. */
9901 if (GET_CODE (op0
) != CONST_INT
9902 || INTVAL (op0
) > 15
9903 || INTVAL (op0
) < -16)
9905 error ("argument 1 must be a 5-bit signed literal");
9911 || GET_MODE (target
) != tmode
9912 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9913 target
= gen_reg_rtx (tmode
);
9915 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9916 op0
= copy_to_mode_reg (mode0
, op0
);
9918 pat
= GEN_FCN (icode
) (target
, op0
);
9927 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
9929 rtx pat
, scratch1
, scratch2
;
9930 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9931 rtx op0
= expand_normal (arg0
);
9932 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9933 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9935 /* If we have invalid arguments, bail out before generating bad rtl. */
9936 if (arg0
== error_mark_node
)
9940 || GET_MODE (target
) != tmode
9941 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9942 target
= gen_reg_rtx (tmode
);
9944 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9945 op0
= copy_to_mode_reg (mode0
, op0
);
9947 scratch1
= gen_reg_rtx (mode0
);
9948 scratch2
= gen_reg_rtx (mode0
);
9950 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
9959 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
9962 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9963 tree arg1
= CALL_EXPR_ARG (exp
, 1);
9964 rtx op0
= expand_normal (arg0
);
9965 rtx op1
= expand_normal (arg1
);
9966 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9967 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9968 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9970 if (icode
== CODE_FOR_nothing
)
9971 /* Builtin not supported on this processor. */
9974 /* If we got invalid arguments bail out before generating bad rtl. */
9975 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
9978 if (icode
== CODE_FOR_altivec_vcfux
9979 || icode
== CODE_FOR_altivec_vcfsx
9980 || icode
== CODE_FOR_altivec_vctsxs
9981 || icode
== CODE_FOR_altivec_vctuxs
9982 || icode
== CODE_FOR_altivec_vspltb
9983 || icode
== CODE_FOR_altivec_vsplth
9984 || icode
== CODE_FOR_altivec_vspltw
9985 || icode
== CODE_FOR_spe_evaddiw
9986 || icode
== CODE_FOR_spe_evldd
9987 || icode
== CODE_FOR_spe_evldh
9988 || icode
== CODE_FOR_spe_evldw
9989 || icode
== CODE_FOR_spe_evlhhesplat
9990 || icode
== CODE_FOR_spe_evlhhossplat
9991 || icode
== CODE_FOR_spe_evlhhousplat
9992 || icode
== CODE_FOR_spe_evlwhe
9993 || icode
== CODE_FOR_spe_evlwhos
9994 || icode
== CODE_FOR_spe_evlwhou
9995 || icode
== CODE_FOR_spe_evlwhsplat
9996 || icode
== CODE_FOR_spe_evlwwsplat
9997 || icode
== CODE_FOR_spe_evrlwi
9998 || icode
== CODE_FOR_spe_evslwi
9999 || icode
== CODE_FOR_spe_evsrwis
10000 || icode
== CODE_FOR_spe_evsubifw
10001 || icode
== CODE_FOR_spe_evsrwiu
)
10003 /* Only allow 5-bit unsigned literals. */
10005 if (TREE_CODE (arg1
) != INTEGER_CST
10006 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
10008 error ("argument 2 must be a 5-bit unsigned literal");
10014 || GET_MODE (target
) != tmode
10015 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10016 target
= gen_reg_rtx (tmode
);
10018 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10019 op0
= copy_to_mode_reg (mode0
, op0
);
10020 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10021 op1
= copy_to_mode_reg (mode1
, op1
);
10023 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
10032 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
10035 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
10036 tree arg0
= CALL_EXPR_ARG (exp
, 1);
10037 tree arg1
= CALL_EXPR_ARG (exp
, 2);
10038 rtx op0
= expand_normal (arg0
);
10039 rtx op1
= expand_normal (arg1
);
10040 enum machine_mode tmode
= SImode
;
10041 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10042 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10045 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
10047 error ("argument 1 of __builtin_altivec_predicate must be a constant");
10051 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
10053 gcc_assert (mode0
== mode1
);
10055 /* If we have invalid arguments, bail out before generating bad rtl. */
10056 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10060 || GET_MODE (target
) != tmode
10061 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10062 target
= gen_reg_rtx (tmode
);
10064 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10065 op0
= copy_to_mode_reg (mode0
, op0
);
10066 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10067 op1
= copy_to_mode_reg (mode1
, op1
);
10069 scratch
= gen_reg_rtx (mode0
);
10071 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
10076 /* The vec_any* and vec_all* predicates use the same opcodes for two
10077 different operations, but the bits in CR6 will be different
10078 depending on what information we want. So we have to play tricks
10079 with CR6 to get the right bits out.
10081 If you think this is disgusting, look at the specs for the
10082 AltiVec predicates. */
10084 switch (cr6_form_int
)
10087 emit_insn (gen_cr6_test_for_zero (target
));
10090 emit_insn (gen_cr6_test_for_zero_reverse (target
));
10093 emit_insn (gen_cr6_test_for_lt (target
));
10096 emit_insn (gen_cr6_test_for_lt_reverse (target
));
10099 error ("argument 1 of __builtin_altivec_predicate is out of range");
10107 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
10110 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10111 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10112 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10113 enum machine_mode mode0
= Pmode
;
10114 enum machine_mode mode1
= Pmode
;
10115 rtx op0
= expand_normal (arg0
);
10116 rtx op1
= expand_normal (arg1
);
10118 if (icode
== CODE_FOR_nothing
)
10119 /* Builtin not supported on this processor. */
10122 /* If we got invalid arguments bail out before generating bad rtl. */
10123 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10127 || GET_MODE (target
) != tmode
10128 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10129 target
= gen_reg_rtx (tmode
);
10131 op1
= copy_to_mode_reg (mode1
, op1
);
10133 if (op0
== const0_rtx
)
10135 addr
= gen_rtx_MEM (tmode
, op1
);
10139 op0
= copy_to_mode_reg (mode0
, op0
);
10140 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10143 pat
= GEN_FCN (icode
) (target
, addr
);
10153 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
10156 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10157 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10158 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10159 enum machine_mode mode0
= Pmode
;
10160 enum machine_mode mode1
= Pmode
;
10161 rtx op0
= expand_normal (arg0
);
10162 rtx op1
= expand_normal (arg1
);
10164 if (icode
== CODE_FOR_nothing
)
10165 /* Builtin not supported on this processor. */
10168 /* If we got invalid arguments bail out before generating bad rtl. */
10169 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10173 || GET_MODE (target
) != tmode
10174 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10175 target
= gen_reg_rtx (tmode
);
10177 op1
= copy_to_mode_reg (mode1
, op1
);
10179 if (op0
== const0_rtx
)
10181 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
10185 op0
= copy_to_mode_reg (mode0
, op0
);
10186 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10189 pat
= GEN_FCN (icode
) (target
, addr
);
10199 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
10201 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10202 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10203 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10204 rtx op0
= expand_normal (arg0
);
10205 rtx op1
= expand_normal (arg1
);
10206 rtx op2
= expand_normal (arg2
);
10208 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
10209 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
10210 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
10212 /* Invalid arguments. Bail before doing anything stoopid! */
10213 if (arg0
== error_mark_node
10214 || arg1
== error_mark_node
10215 || arg2
== error_mark_node
)
10218 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
10219 op0
= copy_to_mode_reg (mode2
, op0
);
10220 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
10221 op1
= copy_to_mode_reg (mode0
, op1
);
10222 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
10223 op2
= copy_to_mode_reg (mode1
, op2
);
10225 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
10232 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
10234 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10235 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10236 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10237 rtx op0
= expand_normal (arg0
);
10238 rtx op1
= expand_normal (arg1
);
10239 rtx op2
= expand_normal (arg2
);
10241 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10242 enum machine_mode mode1
= Pmode
;
10243 enum machine_mode mode2
= Pmode
;
10245 /* Invalid arguments. Bail before doing anything stoopid! */
10246 if (arg0
== error_mark_node
10247 || arg1
== error_mark_node
10248 || arg2
== error_mark_node
)
10251 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
10252 op0
= copy_to_mode_reg (tmode
, op0
);
10254 op2
= copy_to_mode_reg (mode2
, op2
);
10256 if (op1
== const0_rtx
)
10258 addr
= gen_rtx_MEM (tmode
, op2
);
10262 op1
= copy_to_mode_reg (mode1
, op1
);
10263 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10266 pat
= GEN_FCN (icode
) (addr
, op0
);
10273 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
10275 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10276 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10277 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10278 rtx op0
= expand_normal (arg0
);
10279 rtx op1
= expand_normal (arg1
);
10280 rtx op2
= expand_normal (arg2
);
10282 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10283 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
10284 enum machine_mode mode1
= Pmode
;
10285 enum machine_mode mode2
= Pmode
;
10287 /* Invalid arguments. Bail before doing anything stoopid! */
10288 if (arg0
== error_mark_node
10289 || arg1
== error_mark_node
10290 || arg2
== error_mark_node
)
10293 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
10294 op0
= copy_to_mode_reg (smode
, op0
);
10296 op2
= copy_to_mode_reg (mode2
, op2
);
10298 if (op1
== const0_rtx
)
10300 addr
= gen_rtx_MEM (tmode
, op2
);
10304 op1
= copy_to_mode_reg (mode1
, op1
);
10305 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10308 pat
= GEN_FCN (icode
) (addr
, op0
);
10315 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10318 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10319 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10320 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10321 rtx op0
= expand_normal (arg0
);
10322 rtx op1
= expand_normal (arg1
);
10323 rtx op2
= expand_normal (arg2
);
10324 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10325 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10326 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10327 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
10329 if (icode
== CODE_FOR_nothing
)
10330 /* Builtin not supported on this processor. */
10333 /* If we got invalid arguments bail out before generating bad rtl. */
10334 if (arg0
== error_mark_node
10335 || arg1
== error_mark_node
10336 || arg2
== error_mark_node
)
10339 /* Check and prepare argument depending on the instruction code.
10341 Note that a switch statement instead of the sequence of tests
10342 would be incorrect as many of the CODE_FOR values could be
10343 CODE_FOR_nothing and that would yield multiple alternatives
10344 with identical values. We'd never reach here at runtime in
10346 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
10347 || icode
== CODE_FOR_altivec_vsldoi_v4si
10348 || icode
== CODE_FOR_altivec_vsldoi_v8hi
10349 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
10351 /* Only allow 4-bit unsigned literals. */
10353 if (TREE_CODE (arg2
) != INTEGER_CST
10354 || TREE_INT_CST_LOW (arg2
) & ~0xf)
10356 error ("argument 3 must be a 4-bit unsigned literal");
10360 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
10361 || icode
== CODE_FOR_vsx_xxpermdi_v2di
10362 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
10363 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
10364 || icode
== CODE_FOR_vsx_xxsldwi_v4si
10365 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
10366 || icode
== CODE_FOR_vsx_xxsldwi_v2di
10367 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
10369 /* Only allow 2-bit unsigned literals. */
10371 if (TREE_CODE (arg2
) != INTEGER_CST
10372 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10374 error ("argument 3 must be a 2-bit unsigned literal");
10378 else if (icode
== CODE_FOR_vsx_set_v2df
10379 || icode
== CODE_FOR_vsx_set_v2di
)
10381 /* Only allow 1-bit unsigned literals. */
10383 if (TREE_CODE (arg2
) != INTEGER_CST
10384 || TREE_INT_CST_LOW (arg2
) & ~0x1)
10386 error ("argument 3 must be a 1-bit unsigned literal");
10392 || GET_MODE (target
) != tmode
10393 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10394 target
= gen_reg_rtx (tmode
);
10396 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10397 op0
= copy_to_mode_reg (mode0
, op0
);
10398 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10399 op1
= copy_to_mode_reg (mode1
, op1
);
10400 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
10401 op2
= copy_to_mode_reg (mode2
, op2
);
10403 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
10404 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
10406 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
10414 /* Expand the lvx builtins. */
10416 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
10418 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10419 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10421 enum machine_mode tmode
, mode0
;
10423 enum insn_code icode
;
10427 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
10428 icode
= CODE_FOR_vector_altivec_load_v16qi
;
10430 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
10431 icode
= CODE_FOR_vector_altivec_load_v8hi
;
10433 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
10434 icode
= CODE_FOR_vector_altivec_load_v4si
;
10436 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
10437 icode
= CODE_FOR_vector_altivec_load_v4sf
;
10439 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
10440 icode
= CODE_FOR_vector_altivec_load_v2df
;
10442 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
10443 icode
= CODE_FOR_vector_altivec_load_v2di
;
10446 *expandedp
= false;
10452 arg0
= CALL_EXPR_ARG (exp
, 0);
10453 op0
= expand_normal (arg0
);
10454 tmode
= insn_data
[icode
].operand
[0].mode
;
10455 mode0
= insn_data
[icode
].operand
[1].mode
;
10458 || GET_MODE (target
) != tmode
10459 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10460 target
= gen_reg_rtx (tmode
);
10462 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10463 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10465 pat
= GEN_FCN (icode
) (target
, op0
);
10472 /* Expand the stvx builtins. */
10474 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
10477 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10478 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10480 enum machine_mode mode0
, mode1
;
10482 enum insn_code icode
;
10486 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
10487 icode
= CODE_FOR_vector_altivec_store_v16qi
;
10489 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
10490 icode
= CODE_FOR_vector_altivec_store_v8hi
;
10492 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
10493 icode
= CODE_FOR_vector_altivec_store_v4si
;
10495 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
10496 icode
= CODE_FOR_vector_altivec_store_v4sf
;
10498 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
10499 icode
= CODE_FOR_vector_altivec_store_v2df
;
10501 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
10502 icode
= CODE_FOR_vector_altivec_store_v2di
;
10505 *expandedp
= false;
10509 arg0
= CALL_EXPR_ARG (exp
, 0);
10510 arg1
= CALL_EXPR_ARG (exp
, 1);
10511 op0
= expand_normal (arg0
);
10512 op1
= expand_normal (arg1
);
10513 mode0
= insn_data
[icode
].operand
[0].mode
;
10514 mode1
= insn_data
[icode
].operand
[1].mode
;
10516 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10517 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10518 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
10519 op1
= copy_to_mode_reg (mode1
, op1
);
10521 pat
= GEN_FCN (icode
) (op0
, op1
);
10529 /* Expand the dst builtins. */
10531 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
10534 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10535 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10536 tree arg0
, arg1
, arg2
;
10537 enum machine_mode mode0
, mode1
;
10538 rtx pat
, op0
, op1
, op2
;
10539 const struct builtin_description
*d
;
10542 *expandedp
= false;
10544 /* Handle DST variants. */
10546 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
10547 if (d
->code
== fcode
)
10549 arg0
= CALL_EXPR_ARG (exp
, 0);
10550 arg1
= CALL_EXPR_ARG (exp
, 1);
10551 arg2
= CALL_EXPR_ARG (exp
, 2);
10552 op0
= expand_normal (arg0
);
10553 op1
= expand_normal (arg1
);
10554 op2
= expand_normal (arg2
);
10555 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10556 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10558 /* Invalid arguments, bail out before generating bad rtl. */
10559 if (arg0
== error_mark_node
10560 || arg1
== error_mark_node
10561 || arg2
== error_mark_node
)
10566 if (TREE_CODE (arg2
) != INTEGER_CST
10567 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10569 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
10573 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
10574 op0
= copy_to_mode_reg (Pmode
, op0
);
10575 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
10576 op1
= copy_to_mode_reg (mode1
, op1
);
10578 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
10588 /* Expand vec_init builtin. */
10590 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
10592 enum machine_mode tmode
= TYPE_MODE (type
);
10593 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
10594 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
10595 rtvec v
= rtvec_alloc (n_elt
);
10597 gcc_assert (VECTOR_MODE_P (tmode
));
10598 gcc_assert (n_elt
== call_expr_nargs (exp
));
10600 for (i
= 0; i
< n_elt
; ++i
)
10602 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
10603 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
10606 if (!target
|| !register_operand (target
, tmode
))
10607 target
= gen_reg_rtx (tmode
);
10609 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
10613 /* Return the integer constant in ARG. Constrain it to be in the range
10614 of the subparts of VEC_TYPE; issue an error if not. */
10617 get_element_number (tree vec_type
, tree arg
)
10619 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
10621 if (!host_integerp (arg
, 1)
10622 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
10624 error ("selector must be an integer constant in the range 0..%wi", max
);
10631 /* Expand vec_set builtin. */
10633 altivec_expand_vec_set_builtin (tree exp
)
10635 enum machine_mode tmode
, mode1
;
10636 tree arg0
, arg1
, arg2
;
10640 arg0
= CALL_EXPR_ARG (exp
, 0);
10641 arg1
= CALL_EXPR_ARG (exp
, 1);
10642 arg2
= CALL_EXPR_ARG (exp
, 2);
10644 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
10645 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
10646 gcc_assert (VECTOR_MODE_P (tmode
));
10648 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
10649 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
10650 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
10652 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
10653 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
10655 op0
= force_reg (tmode
, op0
);
10656 op1
= force_reg (mode1
, op1
);
10658 rs6000_expand_vector_set (op0
, op1
, elt
);
10663 /* Expand vec_ext builtin. */
10665 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
10667 enum machine_mode tmode
, mode0
;
10672 arg0
= CALL_EXPR_ARG (exp
, 0);
10673 arg1
= CALL_EXPR_ARG (exp
, 1);
10675 op0
= expand_normal (arg0
);
10676 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
10678 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
10679 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
10680 gcc_assert (VECTOR_MODE_P (mode0
));
10682 op0
= force_reg (mode0
, op0
);
10684 if (optimize
|| !target
|| !register_operand (target
, tmode
))
10685 target
= gen_reg_rtx (tmode
);
10687 rs6000_expand_vector_extract (target
, op0
, elt
);
10692 /* Expand the builtin in EXP and store the result in TARGET. Store
10693 true in *EXPANDEDP if we found a builtin to expand. */
10695 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
10697 const struct builtin_description
*d
;
10699 enum insn_code icode
;
10700 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10703 enum machine_mode tmode
, mode0
;
10704 enum rs6000_builtins fcode
10705 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10707 if (rs6000_overloaded_builtin_p (fcode
))
10710 error ("unresolved overload for Altivec builtin %qF", fndecl
);
10712 /* Given it is invalid, just generate a normal call. */
10713 return expand_call (exp
, target
, false);
10716 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
10720 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
10724 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
10732 case ALTIVEC_BUILTIN_STVX
:
10733 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
10734 case ALTIVEC_BUILTIN_STVEBX
:
10735 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
10736 case ALTIVEC_BUILTIN_STVEHX
:
10737 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
10738 case ALTIVEC_BUILTIN_STVEWX
:
10739 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
10740 case ALTIVEC_BUILTIN_STVXL
:
10741 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
10743 case ALTIVEC_BUILTIN_STVLX
:
10744 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
10745 case ALTIVEC_BUILTIN_STVLXL
:
10746 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
10747 case ALTIVEC_BUILTIN_STVRX
:
10748 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
10749 case ALTIVEC_BUILTIN_STVRXL
:
10750 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
10752 case VSX_BUILTIN_STXVD2X_V2DF
:
10753 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
10754 case VSX_BUILTIN_STXVD2X_V2DI
:
10755 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
10756 case VSX_BUILTIN_STXVW4X_V4SF
:
10757 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
10758 case VSX_BUILTIN_STXVW4X_V4SI
:
10759 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
10760 case VSX_BUILTIN_STXVW4X_V8HI
:
10761 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
10762 case VSX_BUILTIN_STXVW4X_V16QI
:
10763 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
10765 case ALTIVEC_BUILTIN_MFVSCR
:
10766 icode
= CODE_FOR_altivec_mfvscr
;
10767 tmode
= insn_data
[icode
].operand
[0].mode
;
10770 || GET_MODE (target
) != tmode
10771 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10772 target
= gen_reg_rtx (tmode
);
10774 pat
= GEN_FCN (icode
) (target
);
10780 case ALTIVEC_BUILTIN_MTVSCR
:
10781 icode
= CODE_FOR_altivec_mtvscr
;
10782 arg0
= CALL_EXPR_ARG (exp
, 0);
10783 op0
= expand_normal (arg0
);
10784 mode0
= insn_data
[icode
].operand
[0].mode
;
10786 /* If we got invalid arguments bail out before generating bad rtl. */
10787 if (arg0
== error_mark_node
)
10790 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10791 op0
= copy_to_mode_reg (mode0
, op0
);
10793 pat
= GEN_FCN (icode
) (op0
);
10798 case ALTIVEC_BUILTIN_DSSALL
:
10799 emit_insn (gen_altivec_dssall ());
10802 case ALTIVEC_BUILTIN_DSS
:
10803 icode
= CODE_FOR_altivec_dss
;
10804 arg0
= CALL_EXPR_ARG (exp
, 0);
10806 op0
= expand_normal (arg0
);
10807 mode0
= insn_data
[icode
].operand
[0].mode
;
10809 /* If we got invalid arguments bail out before generating bad rtl. */
10810 if (arg0
== error_mark_node
)
10813 if (TREE_CODE (arg0
) != INTEGER_CST
10814 || TREE_INT_CST_LOW (arg0
) & ~0x3)
10816 error ("argument to dss must be a 2-bit unsigned literal");
10820 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10821 op0
= copy_to_mode_reg (mode0
, op0
);
10823 emit_insn (gen_altivec_dss (op0
));
10826 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
10827 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
10828 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
10829 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
10830 case VSX_BUILTIN_VEC_INIT_V2DF
:
10831 case VSX_BUILTIN_VEC_INIT_V2DI
:
10832 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
10834 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
10835 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
10836 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
10837 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
10838 case VSX_BUILTIN_VEC_SET_V2DF
:
10839 case VSX_BUILTIN_VEC_SET_V2DI
:
10840 return altivec_expand_vec_set_builtin (exp
);
10842 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
10843 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
10844 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
10845 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
10846 case VSX_BUILTIN_VEC_EXT_V2DF
:
10847 case VSX_BUILTIN_VEC_EXT_V2DI
:
10848 return altivec_expand_vec_ext_builtin (exp
, target
);
10852 /* Fall through. */
10855 /* Expand abs* operations. */
10857 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
10858 if (d
->code
== fcode
)
10859 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
10861 /* Expand the AltiVec predicates. */
10862 d
= bdesc_altivec_preds
;
10863 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
10864 if (d
->code
== fcode
)
10865 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
10867 /* LV* are funky. We initialized them differently. */
10870 case ALTIVEC_BUILTIN_LVSL
:
10871 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
10872 exp
, target
, false);
10873 case ALTIVEC_BUILTIN_LVSR
:
10874 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
10875 exp
, target
, false);
10876 case ALTIVEC_BUILTIN_LVEBX
:
10877 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
10878 exp
, target
, false);
10879 case ALTIVEC_BUILTIN_LVEHX
:
10880 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
10881 exp
, target
, false);
10882 case ALTIVEC_BUILTIN_LVEWX
:
10883 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
10884 exp
, target
, false);
10885 case ALTIVEC_BUILTIN_LVXL
:
10886 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
10887 exp
, target
, false);
10888 case ALTIVEC_BUILTIN_LVX
:
10889 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
10890 exp
, target
, false);
10891 case ALTIVEC_BUILTIN_LVLX
:
10892 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
10893 exp
, target
, true);
10894 case ALTIVEC_BUILTIN_LVLXL
:
10895 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
10896 exp
, target
, true);
10897 case ALTIVEC_BUILTIN_LVRX
:
10898 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
10899 exp
, target
, true);
10900 case ALTIVEC_BUILTIN_LVRXL
:
10901 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
10902 exp
, target
, true);
10903 case VSX_BUILTIN_LXVD2X_V2DF
:
10904 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
10905 exp
, target
, false);
10906 case VSX_BUILTIN_LXVD2X_V2DI
:
10907 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
10908 exp
, target
, false);
10909 case VSX_BUILTIN_LXVW4X_V4SF
:
10910 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
10911 exp
, target
, false);
10912 case VSX_BUILTIN_LXVW4X_V4SI
:
10913 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
10914 exp
, target
, false);
10915 case VSX_BUILTIN_LXVW4X_V8HI
:
10916 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
10917 exp
, target
, false);
10918 case VSX_BUILTIN_LXVW4X_V16QI
:
10919 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
10920 exp
, target
, false);
10924 /* Fall through. */
10927 *expandedp
= false;
10931 /* Expand the builtin in EXP and store the result in TARGET. Store
10932 true in *EXPANDEDP if we found a builtin to expand. */
10934 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
10936 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10937 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10938 const struct builtin_description
*d
;
10945 case PAIRED_BUILTIN_STX
:
10946 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
10947 case PAIRED_BUILTIN_LX
:
10948 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
10951 /* Fall through. */
10954 /* Expand the paired predicates. */
10955 d
= bdesc_paired_preds
;
10956 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
10957 if (d
->code
== fcode
)
10958 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
10960 *expandedp
= false;
10964 /* Binops that need to be initialized manually, but can be expanded
10965 automagically by rs6000_expand_binop_builtin. */
10966 static const struct builtin_description bdesc_2arg_spe
[] =
10968 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
10969 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
10970 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
10971 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
10972 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
10973 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
10974 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
10975 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
10976 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
10977 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
10978 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
10979 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
10980 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
10981 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
10982 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
10983 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
10984 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
10985 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
10986 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
10987 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
10988 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
10989 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
10992 /* Expand the builtin in EXP and store the result in TARGET. Store
10993 true in *EXPANDEDP if we found a builtin to expand.
10995 This expands the SPE builtins that are not simple unary and binary
10998 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
11000 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11002 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11003 enum insn_code icode
;
11004 enum machine_mode tmode
, mode0
;
11006 const struct builtin_description
*d
;
11011 /* Syntax check for a 5-bit unsigned immediate. */
11014 case SPE_BUILTIN_EVSTDD
:
11015 case SPE_BUILTIN_EVSTDH
:
11016 case SPE_BUILTIN_EVSTDW
:
11017 case SPE_BUILTIN_EVSTWHE
:
11018 case SPE_BUILTIN_EVSTWHO
:
11019 case SPE_BUILTIN_EVSTWWE
:
11020 case SPE_BUILTIN_EVSTWWO
:
11021 arg1
= CALL_EXPR_ARG (exp
, 2);
11022 if (TREE_CODE (arg1
) != INTEGER_CST
11023 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11025 error ("argument 2 must be a 5-bit unsigned literal");
11033 /* The evsplat*i instructions are not quite generic. */
11036 case SPE_BUILTIN_EVSPLATFI
:
11037 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
11039 case SPE_BUILTIN_EVSPLATI
:
11040 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
11046 d
= bdesc_2arg_spe
;
11047 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
11048 if (d
->code
== fcode
)
11049 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11051 d
= bdesc_spe_predicates
;
11052 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
11053 if (d
->code
== fcode
)
11054 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
11056 d
= bdesc_spe_evsel
;
11057 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
11058 if (d
->code
== fcode
)
11059 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
11063 case SPE_BUILTIN_EVSTDDX
:
11064 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
11065 case SPE_BUILTIN_EVSTDHX
:
11066 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
11067 case SPE_BUILTIN_EVSTDWX
:
11068 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
11069 case SPE_BUILTIN_EVSTWHEX
:
11070 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
11071 case SPE_BUILTIN_EVSTWHOX
:
11072 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
11073 case SPE_BUILTIN_EVSTWWEX
:
11074 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
11075 case SPE_BUILTIN_EVSTWWOX
:
11076 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
11077 case SPE_BUILTIN_EVSTDD
:
11078 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
11079 case SPE_BUILTIN_EVSTDH
:
11080 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
11081 case SPE_BUILTIN_EVSTDW
:
11082 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
11083 case SPE_BUILTIN_EVSTWHE
:
11084 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
11085 case SPE_BUILTIN_EVSTWHO
:
11086 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
11087 case SPE_BUILTIN_EVSTWWE
:
11088 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
11089 case SPE_BUILTIN_EVSTWWO
:
11090 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
11091 case SPE_BUILTIN_MFSPEFSCR
:
11092 icode
= CODE_FOR_spe_mfspefscr
;
11093 tmode
= insn_data
[icode
].operand
[0].mode
;
11096 || GET_MODE (target
) != tmode
11097 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11098 target
= gen_reg_rtx (tmode
);
11100 pat
= GEN_FCN (icode
) (target
);
11105 case SPE_BUILTIN_MTSPEFSCR
:
11106 icode
= CODE_FOR_spe_mtspefscr
;
11107 arg0
= CALL_EXPR_ARG (exp
, 0);
11108 op0
= expand_normal (arg0
);
11109 mode0
= insn_data
[icode
].operand
[0].mode
;
11111 if (arg0
== error_mark_node
)
11114 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11115 op0
= copy_to_mode_reg (mode0
, op0
);
11117 pat
= GEN_FCN (icode
) (op0
);
11125 *expandedp
= false;
11130 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11132 rtx pat
, scratch
, tmp
;
11133 tree form
= CALL_EXPR_ARG (exp
, 0);
11134 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11135 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11136 rtx op0
= expand_normal (arg0
);
11137 rtx op1
= expand_normal (arg1
);
11138 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11139 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11141 enum rtx_code code
;
11143 if (TREE_CODE (form
) != INTEGER_CST
)
11145 error ("argument 1 of __builtin_paired_predicate must be a constant");
11149 form_int
= TREE_INT_CST_LOW (form
);
11151 gcc_assert (mode0
== mode1
);
11153 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11157 || GET_MODE (target
) != SImode
11158 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11159 target
= gen_reg_rtx (SImode
);
11160 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11161 op0
= copy_to_mode_reg (mode0
, op0
);
11162 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11163 op1
= copy_to_mode_reg (mode1
, op1
);
11165 scratch
= gen_reg_rtx (CCFPmode
);
11167 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11189 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11192 error ("argument 1 of __builtin_paired_predicate is out of range");
11196 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11197 emit_move_insn (target
, tmp
);
11202 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11204 rtx pat
, scratch
, tmp
;
11205 tree form
= CALL_EXPR_ARG (exp
, 0);
11206 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11207 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11208 rtx op0
= expand_normal (arg0
);
11209 rtx op1
= expand_normal (arg1
);
11210 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11211 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11213 enum rtx_code code
;
11215 if (TREE_CODE (form
) != INTEGER_CST
)
11217 error ("argument 1 of __builtin_spe_predicate must be a constant");
11221 form_int
= TREE_INT_CST_LOW (form
);
11223 gcc_assert (mode0
== mode1
);
11225 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11229 || GET_MODE (target
) != SImode
11230 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11231 target
= gen_reg_rtx (SImode
);
11233 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11234 op0
= copy_to_mode_reg (mode0
, op0
);
11235 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11236 op1
= copy_to_mode_reg (mode1
, op1
);
11238 scratch
= gen_reg_rtx (CCmode
);
11240 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11245 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11246 _lower_. We use one compare, but look in different bits of the
11247 CR for each variant.
11249 There are 2 elements in each SPE simd type (upper/lower). The CR
11250 bits are set as follows:
11252 BIT0 | BIT 1 | BIT 2 | BIT 3
11253 U | L | (U | L) | (U & L)
11255 So, for an "all" relationship, BIT 3 would be set.
11256 For an "any" relationship, BIT 2 would be set. Etc.
11258 Following traditional nomenclature, these bits map to:
11260 BIT0 | BIT 1 | BIT 2 | BIT 3
11263 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11268 /* All variant. OV bit. */
11270 /* We need to get to the OV bit, which is the ORDERED bit. We
11271 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11272 that's ugly and will make validate_condition_mode die.
11273 So let's just use another pattern. */
11274 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11276 /* Any variant. EQ bit. */
11280 /* Upper variant. LT bit. */
11284 /* Lower variant. GT bit. */
11289 error ("argument 1 of __builtin_spe_predicate is out of range");
11293 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11294 emit_move_insn (target
, tmp
);
11299 /* The evsel builtins look like this:
11301 e = __builtin_spe_evsel_OP (a, b, c, d);
11303 and work like this:
11305 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11306 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11310 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
11313 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11314 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11315 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11316 tree arg3
= CALL_EXPR_ARG (exp
, 3);
11317 rtx op0
= expand_normal (arg0
);
11318 rtx op1
= expand_normal (arg1
);
11319 rtx op2
= expand_normal (arg2
);
11320 rtx op3
= expand_normal (arg3
);
11321 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11322 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11324 gcc_assert (mode0
== mode1
);
11326 if (arg0
== error_mark_node
|| arg1
== error_mark_node
11327 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
11331 || GET_MODE (target
) != mode0
11332 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
11333 target
= gen_reg_rtx (mode0
);
11335 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11336 op0
= copy_to_mode_reg (mode0
, op0
);
11337 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11338 op1
= copy_to_mode_reg (mode0
, op1
);
11339 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11340 op2
= copy_to_mode_reg (mode0
, op2
);
11341 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
11342 op3
= copy_to_mode_reg (mode0
, op3
);
11344 /* Generate the compare. */
11345 scratch
= gen_reg_rtx (CCmode
);
11346 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11351 if (mode0
== V2SImode
)
11352 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
11354 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
11359 /* Raise an error message for a builtin function that is called without the
11360 appropriate target options being set. */
11363 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
11365 size_t uns_fncode
= (size_t)fncode
;
11366 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
11367 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
11369 gcc_assert (name
!= NULL
);
11370 if ((fnmask
& RS6000_BTM_CELL
) != 0)
11371 error ("Builtin function %s is only valid for the cell processor", name
);
11372 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
11373 error ("Builtin function %s requires the -mvsx option", name
);
11374 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
11375 error ("Builtin function %s requires the -maltivec option", name
);
11376 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
11377 error ("Builtin function %s requires the -mpaired option", name
);
11378 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
11379 error ("Builtin function %s requires the -mspe option", name
);
11381 error ("Builtin function %s is not supported with the current options",
11385 /* Expand an expression EXP that calls a built-in function,
11386 with result going to TARGET if that's convenient
11387 (and in mode MODE if that's convenient).
11388 SUBTARGET may be used as the target for computing one of EXP's operands.
11389 IGNORE is nonzero if the value is to be ignored. */
11392 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
11393 enum machine_mode mode ATTRIBUTE_UNUSED
,
11394 int ignore ATTRIBUTE_UNUSED
)
11396 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11397 enum rs6000_builtins fcode
11398 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
11399 size_t uns_fcode
= (size_t)fcode
;
11400 const struct builtin_description
*d
;
11404 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
11405 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
11407 if (TARGET_DEBUG_BUILTIN
)
11409 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
11410 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
11411 const char *name2
= ((icode
!= CODE_FOR_nothing
)
11412 ? get_insn_name ((int)icode
)
11416 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
11418 default: name3
= "unknown"; break;
11419 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
11420 case RS6000_BTC_UNARY
: name3
= "unary"; break;
11421 case RS6000_BTC_BINARY
: name3
= "binary"; break;
11422 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
11423 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
11424 case RS6000_BTC_ABS
: name3
= "abs"; break;
11425 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
11426 case RS6000_BTC_DST
: name3
= "dst"; break;
11431 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11432 (name1
) ? name1
: "---", fcode
,
11433 (name2
) ? name2
: "---", (int)icode
,
11435 func_valid_p
? "" : ", not valid");
11440 rs6000_invalid_builtin (fcode
);
11442 /* Given it is invalid, just generate a normal call. */
11443 return expand_call (exp
, target
, ignore
);
11448 case RS6000_BUILTIN_RECIP
:
11449 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
11451 case RS6000_BUILTIN_RECIPF
:
11452 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
11454 case RS6000_BUILTIN_RSQRTF
:
11455 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
11457 case RS6000_BUILTIN_RSQRT
:
11458 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
11460 case POWER7_BUILTIN_BPERMD
:
11461 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
11462 ? CODE_FOR_bpermd_di
11463 : CODE_FOR_bpermd_si
), exp
, target
);
11465 case RS6000_BUILTIN_GET_TB
:
11466 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
11469 case RS6000_BUILTIN_MFTB
:
11470 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
11471 ? CODE_FOR_rs6000_mftb_di
11472 : CODE_FOR_rs6000_mftb_si
),
11475 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
11476 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
11478 int icode
= (int) CODE_FOR_altivec_lvsr
;
11479 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11480 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
11484 gcc_assert (TARGET_ALTIVEC
);
11486 arg
= CALL_EXPR_ARG (exp
, 0);
11487 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
11488 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
11489 addr
= memory_address (mode
, op
);
11490 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
11494 /* For the load case need to negate the address. */
11495 op
= gen_reg_rtx (GET_MODE (addr
));
11496 emit_insn (gen_rtx_SET (VOIDmode
, op
,
11497 gen_rtx_NEG (GET_MODE (addr
), addr
)));
11499 op
= gen_rtx_MEM (mode
, op
);
11502 || GET_MODE (target
) != tmode
11503 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11504 target
= gen_reg_rtx (tmode
);
11506 /*pat = gen_altivec_lvsr (target, op);*/
11507 pat
= GEN_FCN (icode
) (target
, op
);
11515 case ALTIVEC_BUILTIN_VCFUX
:
11516 case ALTIVEC_BUILTIN_VCFSX
:
11517 case ALTIVEC_BUILTIN_VCTUXS
:
11518 case ALTIVEC_BUILTIN_VCTSXS
:
11519 /* FIXME: There's got to be a nicer way to handle this case than
11520 constructing a new CALL_EXPR. */
11521 if (call_expr_nargs (exp
) == 1)
11523 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
11524 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
11532 if (TARGET_ALTIVEC
)
11534 ret
= altivec_expand_builtin (exp
, target
, &success
);
11541 ret
= spe_expand_builtin (exp
, target
, &success
);
11546 if (TARGET_PAIRED_FLOAT
)
11548 ret
= paired_expand_builtin (exp
, target
, &success
);
11554 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
11556 /* Handle simple unary operations. */
11558 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
11559 if (d
->code
== fcode
)
11560 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
11562 /* Handle simple binary operations. */
11564 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11565 if (d
->code
== fcode
)
11566 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11568 /* Handle simple ternary operations. */
11570 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
11571 if (d
->code
== fcode
)
11572 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
11574 gcc_unreachable ();
11578 rs6000_init_builtins (void)
11582 enum machine_mode mode
;
11584 if (TARGET_DEBUG_BUILTIN
)
11585 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
11586 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
11587 (TARGET_SPE
) ? ", spe" : "",
11588 (TARGET_ALTIVEC
) ? ", altivec" : "",
11589 (TARGET_VSX
) ? ", vsx" : "");
11591 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
11592 V2SF_type_node
= build_vector_type (float_type_node
, 2);
11593 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
11594 V2DF_type_node
= build_vector_type (double_type_node
, 2);
11595 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
11596 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
11597 V4SF_type_node
= build_vector_type (float_type_node
, 4);
11598 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
11599 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
11601 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
11602 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
11603 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
11604 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
11606 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
11607 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
11608 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
11609 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
11611 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11612 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11613 'vector unsigned short'. */
11615 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
11616 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
11617 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
11618 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
11619 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
11621 long_integer_type_internal_node
= long_integer_type_node
;
11622 long_unsigned_type_internal_node
= long_unsigned_type_node
;
11623 long_long_integer_type_internal_node
= long_long_integer_type_node
;
11624 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
11625 intQI_type_internal_node
= intQI_type_node
;
11626 uintQI_type_internal_node
= unsigned_intQI_type_node
;
11627 intHI_type_internal_node
= intHI_type_node
;
11628 uintHI_type_internal_node
= unsigned_intHI_type_node
;
11629 intSI_type_internal_node
= intSI_type_node
;
11630 uintSI_type_internal_node
= unsigned_intSI_type_node
;
11631 intDI_type_internal_node
= intDI_type_node
;
11632 uintDI_type_internal_node
= unsigned_intDI_type_node
;
11633 float_type_internal_node
= float_type_node
;
11634 double_type_internal_node
= double_type_node
;
11635 void_type_internal_node
= void_type_node
;
11637 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11639 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
11640 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
11641 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
11642 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
11643 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
11644 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
11645 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
11646 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
11647 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
11648 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
11649 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
11650 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
11651 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
11652 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
11653 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
11654 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
11655 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
11656 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
11657 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
11658 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
11659 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
11661 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
11662 TYPE_NAME (bool_char_type_node
) = tdecl
;
11664 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
11665 TYPE_NAME (bool_short_type_node
) = tdecl
;
11667 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
11668 TYPE_NAME (bool_int_type_node
) = tdecl
;
11670 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
11671 TYPE_NAME (pixel_type_node
) = tdecl
;
11673 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
11674 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
11675 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
11676 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
11677 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
11679 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
11680 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
11682 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
11683 TYPE_NAME (V16QI_type_node
) = tdecl
;
11685 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
11686 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
11688 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
11689 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
11691 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
11692 TYPE_NAME (V8HI_type_node
) = tdecl
;
11694 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
11695 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
11697 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
11698 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
11700 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
11701 TYPE_NAME (V4SI_type_node
) = tdecl
;
11703 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
11704 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
11706 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
11707 TYPE_NAME (V4SF_type_node
) = tdecl
;
11709 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
11710 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
11712 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
11713 TYPE_NAME (V2DF_type_node
) = tdecl
;
11715 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
11716 TYPE_NAME (V2DI_type_node
) = tdecl
;
11718 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
11719 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
11721 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
11722 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
11724 /* Paired and SPE builtins are only available if you build a compiler with
11725 the appropriate options, so only create those builtins with the
11726 appropriate compiler option. Create Altivec and VSX builtins on machines
11727 with at least the general purpose extensions (970 and newer) to allow the
11728 use of the target attribute. */
11729 if (TARGET_PAIRED_FLOAT
)
11730 paired_init_builtins ();
11732 spe_init_builtins ();
11733 if (TARGET_EXTRA_BUILTINS
)
11734 altivec_init_builtins ();
11735 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
11736 rs6000_common_init_builtins ();
11738 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
11739 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
11740 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
11742 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
11743 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
11744 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
11746 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
11747 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
11748 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
11750 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
11751 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
11752 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
11754 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
11755 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
11756 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
11757 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
11759 ftype
= build_function_type_list (unsigned_intDI_type_node
,
11761 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
11764 ftype
= build_function_type_list (unsigned_intDI_type_node
,
11767 ftype
= build_function_type_list (unsigned_intSI_type_node
,
11769 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
11772 /* AIX libm provides clog as __clog. */
11773 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
11774 set_user_assembler_name (tdecl
, "__clog");
11777 #ifdef SUBTARGET_INIT_BUILTINS
11778 SUBTARGET_INIT_BUILTINS
;
11782 /* Returns the rs6000 builtin decl for CODE. */
11785 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11787 HOST_WIDE_INT fnmask
;
11789 if (code
>= RS6000_BUILTIN_COUNT
)
11790 return error_mark_node
;
11792 fnmask
= rs6000_builtin_info
[code
].mask
;
11793 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
11795 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
11796 return error_mark_node
;
11799 return rs6000_builtin_decls
[code
];
11803 spe_init_builtins (void)
11805 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
11806 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
11807 const struct builtin_description
*d
;
11810 tree v2si_ftype_4_v2si
11811 = build_function_type_list (opaque_V2SI_type_node
,
11812 opaque_V2SI_type_node
,
11813 opaque_V2SI_type_node
,
11814 opaque_V2SI_type_node
,
11815 opaque_V2SI_type_node
,
11818 tree v2sf_ftype_4_v2sf
11819 = build_function_type_list (opaque_V2SF_type_node
,
11820 opaque_V2SF_type_node
,
11821 opaque_V2SF_type_node
,
11822 opaque_V2SF_type_node
,
11823 opaque_V2SF_type_node
,
11826 tree int_ftype_int_v2si_v2si
11827 = build_function_type_list (integer_type_node
,
11829 opaque_V2SI_type_node
,
11830 opaque_V2SI_type_node
,
11833 tree int_ftype_int_v2sf_v2sf
11834 = build_function_type_list (integer_type_node
,
11836 opaque_V2SF_type_node
,
11837 opaque_V2SF_type_node
,
11840 tree void_ftype_v2si_puint_int
11841 = build_function_type_list (void_type_node
,
11842 opaque_V2SI_type_node
,
11847 tree void_ftype_v2si_puint_char
11848 = build_function_type_list (void_type_node
,
11849 opaque_V2SI_type_node
,
11854 tree void_ftype_v2si_pv2si_int
11855 = build_function_type_list (void_type_node
,
11856 opaque_V2SI_type_node
,
11857 opaque_p_V2SI_type_node
,
11861 tree void_ftype_v2si_pv2si_char
11862 = build_function_type_list (void_type_node
,
11863 opaque_V2SI_type_node
,
11864 opaque_p_V2SI_type_node
,
11868 tree void_ftype_int
11869 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
11871 tree int_ftype_void
11872 = build_function_type_list (integer_type_node
, NULL_TREE
);
11874 tree v2si_ftype_pv2si_int
11875 = build_function_type_list (opaque_V2SI_type_node
,
11876 opaque_p_V2SI_type_node
,
11880 tree v2si_ftype_puint_int
11881 = build_function_type_list (opaque_V2SI_type_node
,
11886 tree v2si_ftype_pushort_int
11887 = build_function_type_list (opaque_V2SI_type_node
,
11892 tree v2si_ftype_signed_char
11893 = build_function_type_list (opaque_V2SI_type_node
,
11894 signed_char_type_node
,
11897 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
11899 /* Initialize irregular SPE builtins. */
11901 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
11902 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
11903 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
11904 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
11905 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
11906 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
11907 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
11908 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
11909 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
11910 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
11911 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
11912 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
11913 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
11914 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
11915 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
11916 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
11917 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
11918 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
11921 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
11922 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
11923 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
11924 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
11925 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
11926 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
11927 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
11928 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
11929 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
11930 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
11931 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
11932 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
11933 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
11934 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
11935 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
11936 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
11937 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
11938 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
11939 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
11940 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
11941 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
11942 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
11945 d
= bdesc_spe_predicates
;
11946 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
11950 switch (insn_data
[d
->icode
].operand
[1].mode
)
11953 type
= int_ftype_int_v2si_v2si
;
11956 type
= int_ftype_int_v2sf_v2sf
;
11959 gcc_unreachable ();
11962 def_builtin (d
->name
, type
, d
->code
);
11965 /* Evsel predicates. */
11966 d
= bdesc_spe_evsel
;
11967 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
11971 switch (insn_data
[d
->icode
].operand
[1].mode
)
11974 type
= v2si_ftype_4_v2si
;
11977 type
= v2sf_ftype_4_v2sf
;
11980 gcc_unreachable ();
11983 def_builtin (d
->name
, type
, d
->code
);
11988 paired_init_builtins (void)
11990 const struct builtin_description
*d
;
11993 tree int_ftype_int_v2sf_v2sf
11994 = build_function_type_list (integer_type_node
,
11999 tree pcfloat_type_node
=
12000 build_pointer_type (build_qualified_type
12001 (float_type_node
, TYPE_QUAL_CONST
));
12003 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
12004 long_integer_type_node
,
12007 tree void_ftype_v2sf_long_pcfloat
=
12008 build_function_type_list (void_type_node
,
12010 long_integer_type_node
,
12015 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
12016 PAIRED_BUILTIN_LX
);
12019 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
12020 PAIRED_BUILTIN_STX
);
12023 d
= bdesc_paired_preds
;
12024 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
12028 if (TARGET_DEBUG_BUILTIN
)
12029 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
12030 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
12031 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
12033 switch (insn_data
[d
->icode
].operand
[1].mode
)
12036 type
= int_ftype_int_v2sf_v2sf
;
12039 gcc_unreachable ();
12042 def_builtin (d
->name
, type
, d
->code
);
12047 altivec_init_builtins (void)
12049 const struct builtin_description
*d
;
12054 tree pvoid_type_node
= build_pointer_type (void_type_node
);
12056 tree pcvoid_type_node
12057 = build_pointer_type (build_qualified_type (void_type_node
,
12060 tree int_ftype_opaque
12061 = build_function_type_list (integer_type_node
,
12062 opaque_V4SI_type_node
, NULL_TREE
);
12063 tree opaque_ftype_opaque
12064 = build_function_type_list (integer_type_node
, NULL_TREE
);
12065 tree opaque_ftype_opaque_int
12066 = build_function_type_list (opaque_V4SI_type_node
,
12067 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
12068 tree opaque_ftype_opaque_opaque_int
12069 = build_function_type_list (opaque_V4SI_type_node
,
12070 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
12071 integer_type_node
, NULL_TREE
);
12072 tree int_ftype_int_opaque_opaque
12073 = build_function_type_list (integer_type_node
,
12074 integer_type_node
, opaque_V4SI_type_node
,
12075 opaque_V4SI_type_node
, NULL_TREE
);
12076 tree int_ftype_int_v4si_v4si
12077 = build_function_type_list (integer_type_node
,
12078 integer_type_node
, V4SI_type_node
,
12079 V4SI_type_node
, NULL_TREE
);
12080 tree void_ftype_v4si
12081 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
12082 tree v8hi_ftype_void
12083 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
12084 tree void_ftype_void
12085 = build_function_type_list (void_type_node
, NULL_TREE
);
12086 tree void_ftype_int
12087 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
12089 tree opaque_ftype_long_pcvoid
12090 = build_function_type_list (opaque_V4SI_type_node
,
12091 long_integer_type_node
, pcvoid_type_node
,
12093 tree v16qi_ftype_long_pcvoid
12094 = build_function_type_list (V16QI_type_node
,
12095 long_integer_type_node
, pcvoid_type_node
,
12097 tree v8hi_ftype_long_pcvoid
12098 = build_function_type_list (V8HI_type_node
,
12099 long_integer_type_node
, pcvoid_type_node
,
12101 tree v4si_ftype_long_pcvoid
12102 = build_function_type_list (V4SI_type_node
,
12103 long_integer_type_node
, pcvoid_type_node
,
12105 tree v4sf_ftype_long_pcvoid
12106 = build_function_type_list (V4SF_type_node
,
12107 long_integer_type_node
, pcvoid_type_node
,
12109 tree v2df_ftype_long_pcvoid
12110 = build_function_type_list (V2DF_type_node
,
12111 long_integer_type_node
, pcvoid_type_node
,
12113 tree v2di_ftype_long_pcvoid
12114 = build_function_type_list (V2DI_type_node
,
12115 long_integer_type_node
, pcvoid_type_node
,
12118 tree void_ftype_opaque_long_pvoid
12119 = build_function_type_list (void_type_node
,
12120 opaque_V4SI_type_node
, long_integer_type_node
,
12121 pvoid_type_node
, NULL_TREE
);
12122 tree void_ftype_v4si_long_pvoid
12123 = build_function_type_list (void_type_node
,
12124 V4SI_type_node
, long_integer_type_node
,
12125 pvoid_type_node
, NULL_TREE
);
12126 tree void_ftype_v16qi_long_pvoid
12127 = build_function_type_list (void_type_node
,
12128 V16QI_type_node
, long_integer_type_node
,
12129 pvoid_type_node
, NULL_TREE
);
12130 tree void_ftype_v8hi_long_pvoid
12131 = build_function_type_list (void_type_node
,
12132 V8HI_type_node
, long_integer_type_node
,
12133 pvoid_type_node
, NULL_TREE
);
12134 tree void_ftype_v4sf_long_pvoid
12135 = build_function_type_list (void_type_node
,
12136 V4SF_type_node
, long_integer_type_node
,
12137 pvoid_type_node
, NULL_TREE
);
12138 tree void_ftype_v2df_long_pvoid
12139 = build_function_type_list (void_type_node
,
12140 V2DF_type_node
, long_integer_type_node
,
12141 pvoid_type_node
, NULL_TREE
);
12142 tree void_ftype_v2di_long_pvoid
12143 = build_function_type_list (void_type_node
,
12144 V2DI_type_node
, long_integer_type_node
,
12145 pvoid_type_node
, NULL_TREE
);
12146 tree int_ftype_int_v8hi_v8hi
12147 = build_function_type_list (integer_type_node
,
12148 integer_type_node
, V8HI_type_node
,
12149 V8HI_type_node
, NULL_TREE
);
12150 tree int_ftype_int_v16qi_v16qi
12151 = build_function_type_list (integer_type_node
,
12152 integer_type_node
, V16QI_type_node
,
12153 V16QI_type_node
, NULL_TREE
);
12154 tree int_ftype_int_v4sf_v4sf
12155 = build_function_type_list (integer_type_node
,
12156 integer_type_node
, V4SF_type_node
,
12157 V4SF_type_node
, NULL_TREE
);
12158 tree int_ftype_int_v2df_v2df
12159 = build_function_type_list (integer_type_node
,
12160 integer_type_node
, V2DF_type_node
,
12161 V2DF_type_node
, NULL_TREE
);
12162 tree v4si_ftype_v4si
12163 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12164 tree v8hi_ftype_v8hi
12165 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12166 tree v16qi_ftype_v16qi
12167 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12168 tree v4sf_ftype_v4sf
12169 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12170 tree v2df_ftype_v2df
12171 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12172 tree void_ftype_pcvoid_int_int
12173 = build_function_type_list (void_type_node
,
12174 pcvoid_type_node
, integer_type_node
,
12175 integer_type_node
, NULL_TREE
);
12177 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
12178 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
12179 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
12180 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
12181 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
12182 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
12183 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
12184 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
12185 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
12186 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
12187 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
12188 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
12189 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
12190 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
12191 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
12192 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
12193 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
12194 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
12195 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
12196 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
12197 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
12198 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
12199 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
12200 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
12201 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
12202 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
12203 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
12204 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
12205 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
12206 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
12208 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
12209 VSX_BUILTIN_LXVD2X_V2DF
);
12210 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
12211 VSX_BUILTIN_LXVD2X_V2DI
);
12212 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
12213 VSX_BUILTIN_LXVW4X_V4SF
);
12214 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
12215 VSX_BUILTIN_LXVW4X_V4SI
);
12216 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
12217 VSX_BUILTIN_LXVW4X_V8HI
);
12218 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
12219 VSX_BUILTIN_LXVW4X_V16QI
);
12220 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
12221 VSX_BUILTIN_STXVD2X_V2DF
);
12222 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
12223 VSX_BUILTIN_STXVD2X_V2DI
);
12224 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
12225 VSX_BUILTIN_STXVW4X_V4SF
);
12226 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
12227 VSX_BUILTIN_STXVW4X_V4SI
);
12228 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
12229 VSX_BUILTIN_STXVW4X_V8HI
);
12230 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
12231 VSX_BUILTIN_STXVW4X_V16QI
);
12232 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
12233 VSX_BUILTIN_VEC_LD
);
12234 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
12235 VSX_BUILTIN_VEC_ST
);
12237 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
12238 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
12239 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
12241 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
12242 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
12243 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
12244 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
12245 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
12246 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
12247 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
12248 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
12249 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
12250 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
12251 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
12252 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
12254 /* Cell builtins. */
12255 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
12256 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
12257 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
12258 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
12260 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
12261 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
12262 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
12263 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
12265 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
12266 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
12267 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
12268 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
12270 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
12271 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
12272 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
12273 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
12275 /* Add the DST variants. */
12277 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12278 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
12280 /* Initialize the predicates. */
12281 d
= bdesc_altivec_preds
;
12282 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12284 enum machine_mode mode1
;
12287 if (rs6000_overloaded_builtin_p (d
->code
))
12290 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12295 type
= int_ftype_int_opaque_opaque
;
12298 type
= int_ftype_int_v4si_v4si
;
12301 type
= int_ftype_int_v8hi_v8hi
;
12304 type
= int_ftype_int_v16qi_v16qi
;
12307 type
= int_ftype_int_v4sf_v4sf
;
12310 type
= int_ftype_int_v2df_v2df
;
12313 gcc_unreachable ();
12316 def_builtin (d
->name
, type
, d
->code
);
12319 /* Initialize the abs* operators. */
12321 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12323 enum machine_mode mode0
;
12326 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12331 type
= v4si_ftype_v4si
;
12334 type
= v8hi_ftype_v8hi
;
12337 type
= v16qi_ftype_v16qi
;
12340 type
= v4sf_ftype_v4sf
;
12343 type
= v2df_ftype_v2df
;
12346 gcc_unreachable ();
12349 def_builtin (d
->name
, type
, d
->code
);
12352 /* Initialize target builtin that implements
12353 targetm.vectorize.builtin_mask_for_load. */
12355 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
12356 v16qi_ftype_long_pcvoid
,
12357 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
12358 BUILT_IN_MD
, NULL
, NULL_TREE
);
12359 TREE_READONLY (decl
) = 1;
12360 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12361 altivec_builtin_mask_for_load
= decl
;
12363 /* Access to the vec_init patterns. */
12364 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
12365 integer_type_node
, integer_type_node
,
12366 integer_type_node
, NULL_TREE
);
12367 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
12369 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
12370 short_integer_type_node
,
12371 short_integer_type_node
,
12372 short_integer_type_node
,
12373 short_integer_type_node
,
12374 short_integer_type_node
,
12375 short_integer_type_node
,
12376 short_integer_type_node
, NULL_TREE
);
12377 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
12379 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
12380 char_type_node
, char_type_node
,
12381 char_type_node
, char_type_node
,
12382 char_type_node
, char_type_node
,
12383 char_type_node
, char_type_node
,
12384 char_type_node
, char_type_node
,
12385 char_type_node
, char_type_node
,
12386 char_type_node
, char_type_node
,
12387 char_type_node
, NULL_TREE
);
12388 def_builtin ("__builtin_vec_init_v16qi", ftype
,
12389 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
12391 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
12392 float_type_node
, float_type_node
,
12393 float_type_node
, NULL_TREE
);
12394 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
12396 /* VSX builtins. */
12397 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
12398 double_type_node
, NULL_TREE
);
12399 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
12401 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
12402 intDI_type_node
, NULL_TREE
);
12403 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
12405 /* Access to the vec_set patterns. */
12406 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
12408 integer_type_node
, NULL_TREE
);
12409 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
12411 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
12413 integer_type_node
, NULL_TREE
);
12414 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
12416 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
12418 integer_type_node
, NULL_TREE
);
12419 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
12421 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
12423 integer_type_node
, NULL_TREE
);
12424 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
12426 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
12428 integer_type_node
, NULL_TREE
);
12429 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
12431 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
12433 integer_type_node
, NULL_TREE
);
12434 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
12436 /* Access to the vec_extract patterns. */
12437 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
12438 integer_type_node
, NULL_TREE
);
12439 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
12441 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
12442 integer_type_node
, NULL_TREE
);
12443 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
12445 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
12446 integer_type_node
, NULL_TREE
);
12447 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
12449 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
12450 integer_type_node
, NULL_TREE
);
12451 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
12453 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
12454 integer_type_node
, NULL_TREE
);
12455 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
12457 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
12458 integer_type_node
, NULL_TREE
);
12459 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
12462 /* Hash function for builtin functions with up to 3 arguments and a return
12465 builtin_hash_function (const void *hash_entry
)
12469 const struct builtin_hash_struct
*bh
=
12470 (const struct builtin_hash_struct
*) hash_entry
;
12472 for (i
= 0; i
< 4; i
++)
12474 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
12475 ret
= (ret
* 2) + bh
->uns_p
[i
];
12481 /* Compare builtin hash entries H1 and H2 for equivalence. */
12483 builtin_hash_eq (const void *h1
, const void *h2
)
12485 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
12486 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
12488 return ((p1
->mode
[0] == p2
->mode
[0])
12489 && (p1
->mode
[1] == p2
->mode
[1])
12490 && (p1
->mode
[2] == p2
->mode
[2])
12491 && (p1
->mode
[3] == p2
->mode
[3])
12492 && (p1
->uns_p
[0] == p2
->uns_p
[0])
12493 && (p1
->uns_p
[1] == p2
->uns_p
[1])
12494 && (p1
->uns_p
[2] == p2
->uns_p
[2])
12495 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
12498 /* Map types for builtin functions with an explicit return type and up to 3
12499 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12500 of the argument. */
12502 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
12503 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
12504 enum rs6000_builtins builtin
, const char *name
)
12506 struct builtin_hash_struct h
;
12507 struct builtin_hash_struct
*h2
;
12511 tree ret_type
= NULL_TREE
;
12512 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
12514 /* Create builtin_hash_table. */
12515 if (builtin_hash_table
== NULL
)
12516 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
12517 builtin_hash_eq
, NULL
);
12519 h
.type
= NULL_TREE
;
12520 h
.mode
[0] = mode_ret
;
12521 h
.mode
[1] = mode_arg0
;
12522 h
.mode
[2] = mode_arg1
;
12523 h
.mode
[3] = mode_arg2
;
12529 /* If the builtin is a type that produces unsigned results or takes unsigned
12530 arguments, and it is returned as a decl for the vectorizer (such as
12531 widening multiplies, permute), make sure the arguments and return value
12532 are type correct. */
12535 /* unsigned 2 argument functions. */
12536 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
12537 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
12538 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
12539 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
12545 /* unsigned 3 argument functions. */
12546 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
12547 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
12548 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
12549 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
12550 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
12551 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
12552 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
12553 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
12554 case VSX_BUILTIN_VPERM_16QI_UNS
:
12555 case VSX_BUILTIN_VPERM_8HI_UNS
:
12556 case VSX_BUILTIN_VPERM_4SI_UNS
:
12557 case VSX_BUILTIN_VPERM_2DI_UNS
:
12558 case VSX_BUILTIN_XXSEL_16QI_UNS
:
12559 case VSX_BUILTIN_XXSEL_8HI_UNS
:
12560 case VSX_BUILTIN_XXSEL_4SI_UNS
:
12561 case VSX_BUILTIN_XXSEL_2DI_UNS
:
12568 /* signed permute functions with unsigned char mask. */
12569 case ALTIVEC_BUILTIN_VPERM_16QI
:
12570 case ALTIVEC_BUILTIN_VPERM_8HI
:
12571 case ALTIVEC_BUILTIN_VPERM_4SI
:
12572 case ALTIVEC_BUILTIN_VPERM_4SF
:
12573 case ALTIVEC_BUILTIN_VPERM_2DI
:
12574 case ALTIVEC_BUILTIN_VPERM_2DF
:
12575 case VSX_BUILTIN_VPERM_16QI
:
12576 case VSX_BUILTIN_VPERM_8HI
:
12577 case VSX_BUILTIN_VPERM_4SI
:
12578 case VSX_BUILTIN_VPERM_4SF
:
12579 case VSX_BUILTIN_VPERM_2DI
:
12580 case VSX_BUILTIN_VPERM_2DF
:
12584 /* unsigned args, signed return. */
12585 case VSX_BUILTIN_XVCVUXDDP_UNS
:
12586 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
12590 /* signed args, unsigned return. */
12591 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
12592 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
12600 /* Figure out how many args are present. */
12601 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
12605 fatal_error ("internal error: builtin function %s had no type", name
);
12607 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
12608 if (!ret_type
&& h
.uns_p
[0])
12609 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
12612 fatal_error ("internal error: builtin function %s had an unexpected "
12613 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
12615 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
12616 arg_type
[i
] = NULL_TREE
;
12618 for (i
= 0; i
< num_args
; i
++)
12620 int m
= (int) h
.mode
[i
+1];
12621 int uns_p
= h
.uns_p
[i
+1];
12623 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
12624 if (!arg_type
[i
] && uns_p
)
12625 arg_type
[i
] = builtin_mode_to_type
[m
][0];
12628 fatal_error ("internal error: builtin function %s, argument %d "
12629 "had unexpected argument type %s", name
, i
,
12630 GET_MODE_NAME (m
));
12633 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
12634 if (*found
== NULL
)
12636 h2
= ggc_alloc_builtin_hash_struct ();
12638 *found
= (void *)h2
;
12640 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
12641 arg_type
[2], NULL_TREE
);
12644 return ((struct builtin_hash_struct
*)(*found
))->type
;
12648 rs6000_common_init_builtins (void)
12650 const struct builtin_description
*d
;
12653 tree opaque_ftype_opaque
= NULL_TREE
;
12654 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
12655 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
12656 tree v2si_ftype_qi
= NULL_TREE
;
12657 tree v2si_ftype_v2si_qi
= NULL_TREE
;
12658 tree v2si_ftype_int_qi
= NULL_TREE
;
12659 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
12661 if (!TARGET_PAIRED_FLOAT
)
12663 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
12664 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
12667 /* Paired and SPE builtins are only available if you build a compiler with
12668 the appropriate options, so only create those builtins with the
12669 appropriate compiler option. Create Altivec and VSX builtins on machines
12670 with at least the general purpose extensions (970 and newer) to allow the
12671 use of the target attribute.. */
12673 if (TARGET_EXTRA_BUILTINS
)
12674 builtin_mask
|= RS6000_BTM_COMMON
;
12676 /* Add the ternary operators. */
12678 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
12681 HOST_WIDE_INT mask
= d
->mask
;
12683 if ((mask
& builtin_mask
) != mask
)
12685 if (TARGET_DEBUG_BUILTIN
)
12686 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
12690 if (rs6000_overloaded_builtin_p (d
->code
))
12692 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
12693 type
= opaque_ftype_opaque_opaque_opaque
12694 = build_function_type_list (opaque_V4SI_type_node
,
12695 opaque_V4SI_type_node
,
12696 opaque_V4SI_type_node
,
12697 opaque_V4SI_type_node
,
12702 enum insn_code icode
= d
->icode
;
12703 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12706 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
12707 insn_data
[icode
].operand
[1].mode
,
12708 insn_data
[icode
].operand
[2].mode
,
12709 insn_data
[icode
].operand
[3].mode
,
12713 def_builtin (d
->name
, type
, d
->code
);
12716 /* Add the binary operators. */
12718 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12720 enum machine_mode mode0
, mode1
, mode2
;
12722 HOST_WIDE_INT mask
= d
->mask
;
12724 if ((mask
& builtin_mask
) != mask
)
12726 if (TARGET_DEBUG_BUILTIN
)
12727 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
12731 if (rs6000_overloaded_builtin_p (d
->code
))
12733 if (! (type
= opaque_ftype_opaque_opaque
))
12734 type
= opaque_ftype_opaque_opaque
12735 = build_function_type_list (opaque_V4SI_type_node
,
12736 opaque_V4SI_type_node
,
12737 opaque_V4SI_type_node
,
12742 enum insn_code icode
= d
->icode
;
12743 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12746 mode0
= insn_data
[icode
].operand
[0].mode
;
12747 mode1
= insn_data
[icode
].operand
[1].mode
;
12748 mode2
= insn_data
[icode
].operand
[2].mode
;
12750 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
12752 if (! (type
= v2si_ftype_v2si_qi
))
12753 type
= v2si_ftype_v2si_qi
12754 = build_function_type_list (opaque_V2SI_type_node
,
12755 opaque_V2SI_type_node
,
12760 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
12761 && mode2
== QImode
)
12763 if (! (type
= v2si_ftype_int_qi
))
12764 type
= v2si_ftype_int_qi
12765 = build_function_type_list (opaque_V2SI_type_node
,
12772 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
12776 def_builtin (d
->name
, type
, d
->code
);
12779 /* Add the simple unary operators. */
12781 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12783 enum machine_mode mode0
, mode1
;
12785 HOST_WIDE_INT mask
= d
->mask
;
12787 if ((mask
& builtin_mask
) != mask
)
12789 if (TARGET_DEBUG_BUILTIN
)
12790 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
12794 if (rs6000_overloaded_builtin_p (d
->code
))
12796 if (! (type
= opaque_ftype_opaque
))
12797 type
= opaque_ftype_opaque
12798 = build_function_type_list (opaque_V4SI_type_node
,
12799 opaque_V4SI_type_node
,
12804 enum insn_code icode
= d
->icode
;
12805 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12808 mode0
= insn_data
[icode
].operand
[0].mode
;
12809 mode1
= insn_data
[icode
].operand
[1].mode
;
12811 if (mode0
== V2SImode
&& mode1
== QImode
)
12813 if (! (type
= v2si_ftype_qi
))
12814 type
= v2si_ftype_qi
12815 = build_function_type_list (opaque_V2SI_type_node
,
12821 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
12825 def_builtin (d
->name
, type
, d
->code
);
12830 rs6000_init_libfuncs (void)
12832 if (!TARGET_IEEEQUAD
)
12833 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12834 if (!TARGET_XL_COMPAT
)
12836 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
12837 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
12838 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
12839 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
12841 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
12843 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
12844 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
12845 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
12846 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
12847 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
12848 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
12849 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
12851 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
12852 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
12853 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
12854 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
12855 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
12856 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
12857 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
12858 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
12861 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
12862 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
12866 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
12867 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
12868 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
12869 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
12873 /* 32-bit SVR4 quad floating point routines. */
12875 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
12876 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
12877 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
12878 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
12879 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
12880 if (TARGET_PPC_GPOPT
)
12881 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
12883 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
12884 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
12885 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
12886 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
12887 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
12888 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
12890 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
12891 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
12892 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
12893 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
12894 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
12895 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
12896 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
12897 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
12902 /* Expand a block clear operation, and return 1 if successful. Return 0
12903 if we should let the compiler generate normal code.
12905 operands[0] is the destination
12906 operands[1] is the length
12907 operands[3] is the alignment */
12910 expand_block_clear (rtx operands
[])
12912 rtx orig_dest
= operands
[0];
12913 rtx bytes_rtx
= operands
[1];
12914 rtx align_rtx
= operands
[3];
12915 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
12916 HOST_WIDE_INT align
;
12917 HOST_WIDE_INT bytes
;
12922 /* If this is not a fixed size move, just call memcpy */
12926 /* This must be a fixed size alignment */
12927 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
12928 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
12930 /* Anything to clear? */
12931 bytes
= INTVAL (bytes_rtx
);
12935 /* Use the builtin memset after a point, to avoid huge code bloat.
12936 When optimize_size, avoid any significant code bloat; calling
12937 memset is about 4 instructions, so allow for one instruction to
12938 load zero and three to do clearing. */
12939 if (TARGET_ALTIVEC
&& align
>= 128)
12941 else if (TARGET_POWERPC64
&& align
>= 32)
12943 else if (TARGET_SPE
&& align
>= 64)
12948 if (optimize_size
&& bytes
> 3 * clear_step
)
12950 if (! optimize_size
&& bytes
> 8 * clear_step
)
12953 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
12955 enum machine_mode mode
= BLKmode
;
12958 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
12963 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
12968 else if (bytes
>= 8 && TARGET_POWERPC64
12969 /* 64-bit loads and stores require word-aligned
12971 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
12976 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
12977 { /* move 4 bytes */
12981 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
12982 { /* move 2 bytes */
12986 else /* move 1 byte at a time */
12992 dest
= adjust_address (orig_dest
, mode
, offset
);
12994 emit_move_insn (dest
, CONST0_RTX (mode
));
13001 /* Expand a block move operation, and return 1 if successful. Return 0
13002 if we should let the compiler generate normal code.
13004 operands[0] is the destination
13005 operands[1] is the source
13006 operands[2] is the length
13007 operands[3] is the alignment */
13009 #define MAX_MOVE_REG 4
13012 expand_block_move (rtx operands
[])
13014 rtx orig_dest
= operands
[0];
13015 rtx orig_src
= operands
[1];
13016 rtx bytes_rtx
= operands
[2];
13017 rtx align_rtx
= operands
[3];
13018 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
13023 rtx stores
[MAX_MOVE_REG
];
13026 /* If this is not a fixed size move, just call memcpy */
13030 /* This must be a fixed size alignment */
13031 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
13032 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
13034 /* Anything to move? */
13035 bytes
= INTVAL (bytes_rtx
);
13039 if (bytes
> rs6000_block_move_inline_limit
)
13042 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
13045 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
13046 rtx (*mov
) (rtx
, rtx
);
13048 enum machine_mode mode
= BLKmode
;
13051 /* Altivec first, since it will be faster than a string move
13052 when it applies, and usually not significantly larger. */
13053 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
13057 gen_func
.mov
= gen_movv4si
;
13059 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
13063 gen_func
.mov
= gen_movv2si
;
13065 else if (TARGET_STRING
13066 && bytes
> 24 /* move up to 32 bytes at a time */
13072 && ! fixed_regs
[10]
13073 && ! fixed_regs
[11]
13074 && ! fixed_regs
[12])
13076 move_bytes
= (bytes
> 32) ? 32 : bytes
;
13077 gen_func
.movmemsi
= gen_movmemsi_8reg
;
13079 else if (TARGET_STRING
13080 && bytes
> 16 /* move up to 24 bytes at a time */
13086 && ! fixed_regs
[10])
13088 move_bytes
= (bytes
> 24) ? 24 : bytes
;
13089 gen_func
.movmemsi
= gen_movmemsi_6reg
;
13091 else if (TARGET_STRING
13092 && bytes
> 8 /* move up to 16 bytes at a time */
13096 && ! fixed_regs
[8])
13098 move_bytes
= (bytes
> 16) ? 16 : bytes
;
13099 gen_func
.movmemsi
= gen_movmemsi_4reg
;
13101 else if (bytes
>= 8 && TARGET_POWERPC64
13102 /* 64-bit loads and stores require word-aligned
13104 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
13108 gen_func
.mov
= gen_movdi
;
13110 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
13111 { /* move up to 8 bytes at a time */
13112 move_bytes
= (bytes
> 8) ? 8 : bytes
;
13113 gen_func
.movmemsi
= gen_movmemsi_2reg
;
13115 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
13116 { /* move 4 bytes */
13119 gen_func
.mov
= gen_movsi
;
13121 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
13122 { /* move 2 bytes */
13125 gen_func
.mov
= gen_movhi
;
13127 else if (TARGET_STRING
&& bytes
> 1)
13128 { /* move up to 4 bytes at a time */
13129 move_bytes
= (bytes
> 4) ? 4 : bytes
;
13130 gen_func
.movmemsi
= gen_movmemsi_1reg
;
13132 else /* move 1 byte at a time */
13136 gen_func
.mov
= gen_movqi
;
13139 src
= adjust_address (orig_src
, mode
, offset
);
13140 dest
= adjust_address (orig_dest
, mode
, offset
);
13142 if (mode
!= BLKmode
)
13144 rtx tmp_reg
= gen_reg_rtx (mode
);
13146 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
13147 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
13150 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
13153 for (i
= 0; i
< num_reg
; i
++)
13154 emit_insn (stores
[i
]);
13158 if (mode
== BLKmode
)
13160 /* Move the address into scratch registers. The movmemsi
13161 patterns require zero offset. */
13162 if (!REG_P (XEXP (src
, 0)))
13164 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
13165 src
= replace_equiv_address (src
, src_reg
);
13167 set_mem_size (src
, move_bytes
);
13169 if (!REG_P (XEXP (dest
, 0)))
13171 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
13172 dest
= replace_equiv_address (dest
, dest_reg
);
13174 set_mem_size (dest
, move_bytes
);
13176 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
13177 GEN_INT (move_bytes
& 31),
13186 /* Return a string to perform a load_multiple operation.
13187 operands[0] is the vector.
13188 operands[1] is the source address.
13189 operands[2] is the first destination register. */
13192 rs6000_output_load_multiple (rtx operands
[3])
13194 /* We have to handle the case where the pseudo used to contain the address
13195 is assigned to one of the output registers. */
13197 int words
= XVECLEN (operands
[0], 0);
13200 if (XVECLEN (operands
[0], 0) == 1)
13201 return "lwz %2,0(%1)";
13203 for (i
= 0; i
< words
; i
++)
13204 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
13205 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
13209 xop
[0] = GEN_INT (4 * (words
-1));
13210 xop
[1] = operands
[1];
13211 xop
[2] = operands
[2];
13212 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
13217 xop
[0] = GEN_INT (4 * (words
-1));
13218 xop
[1] = operands
[1];
13219 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
13220 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
13225 for (j
= 0; j
< words
; j
++)
13228 xop
[0] = GEN_INT (j
* 4);
13229 xop
[1] = operands
[1];
13230 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
13231 output_asm_insn ("lwz %2,%0(%1)", xop
);
13233 xop
[0] = GEN_INT (i
* 4);
13234 xop
[1] = operands
[1];
13235 output_asm_insn ("lwz %1,%0(%1)", xop
);
13240 return "lswi %2,%1,%N0";
13244 /* A validation routine: say whether CODE, a condition code, and MODE
13245 match. The other alternatives either don't make sense or should
13246 never be generated. */
13249 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
13251 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
13252 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
13253 && GET_MODE_CLASS (mode
) == MODE_CC
);
13255 /* These don't make sense. */
13256 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
13257 || mode
!= CCUNSmode
);
13259 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
13260 || mode
== CCUNSmode
);
13262 gcc_assert (mode
== CCFPmode
13263 || (code
!= ORDERED
&& code
!= UNORDERED
13264 && code
!= UNEQ
&& code
!= LTGT
13265 && code
!= UNGT
&& code
!= UNLT
13266 && code
!= UNGE
&& code
!= UNLE
));
13268 /* These should never be generated except for
13269 flag_finite_math_only. */
13270 gcc_assert (mode
!= CCFPmode
13271 || flag_finite_math_only
13272 || (code
!= LE
&& code
!= GE
13273 && code
!= UNEQ
&& code
!= LTGT
13274 && code
!= UNGT
&& code
!= UNLT
));
13276 /* These are invalid; the information is not there. */
13277 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
13281 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13282 mask required to convert the result of a rotate insn into a shift
13283 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13286 includes_lshift_p (rtx shiftop
, rtx andop
)
13288 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13290 shift_mask
<<= INTVAL (shiftop
);
13292 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13295 /* Similar, but for right shift. */
13298 includes_rshift_p (rtx shiftop
, rtx andop
)
13300 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13302 shift_mask
>>= INTVAL (shiftop
);
13304 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13307 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13308 to perform a left shift. It must have exactly SHIFTOP least
13309 significant 0's, then one or more 1's, then zero or more 0's. */
13312 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
13314 if (GET_CODE (andop
) == CONST_INT
)
13316 HOST_WIDE_INT c
, lsb
, shift_mask
;
13318 c
= INTVAL (andop
);
13319 if (c
== 0 || c
== ~0)
13323 shift_mask
<<= INTVAL (shiftop
);
13325 /* Find the least significant one bit. */
13328 /* It must coincide with the LSB of the shift mask. */
13329 if (-lsb
!= shift_mask
)
13332 /* Invert to look for the next transition (if any). */
13335 /* Remove the low group of ones (originally low group of zeros). */
13338 /* Again find the lsb, and check we have all 1's above. */
13342 else if (GET_CODE (andop
) == CONST_DOUBLE
13343 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
13345 HOST_WIDE_INT low
, high
, lsb
;
13346 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
13348 low
= CONST_DOUBLE_LOW (andop
);
13349 if (HOST_BITS_PER_WIDE_INT
< 64)
13350 high
= CONST_DOUBLE_HIGH (andop
);
13352 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
13353 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
13356 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
13358 shift_mask_high
= ~0;
13359 if (INTVAL (shiftop
) > 32)
13360 shift_mask_high
<<= INTVAL (shiftop
) - 32;
13362 lsb
= high
& -high
;
13364 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
13370 lsb
= high
& -high
;
13371 return high
== -lsb
;
13374 shift_mask_low
= ~0;
13375 shift_mask_low
<<= INTVAL (shiftop
);
13379 if (-lsb
!= shift_mask_low
)
13382 if (HOST_BITS_PER_WIDE_INT
< 64)
13387 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
13389 lsb
= high
& -high
;
13390 return high
== -lsb
;
13394 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
13400 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13401 to perform a left shift. It must have SHIFTOP or more least
13402 significant 0's, with the remainder of the word 1's. */
13405 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
13407 if (GET_CODE (andop
) == CONST_INT
)
13409 HOST_WIDE_INT c
, lsb
, shift_mask
;
13412 shift_mask
<<= INTVAL (shiftop
);
13413 c
= INTVAL (andop
);
13415 /* Find the least significant one bit. */
13418 /* It must be covered by the shift mask.
13419 This test also rejects c == 0. */
13420 if ((lsb
& shift_mask
) == 0)
13423 /* Check we have all 1's above the transition, and reject all 1's. */
13424 return c
== -lsb
&& lsb
!= 1;
13426 else if (GET_CODE (andop
) == CONST_DOUBLE
13427 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
13429 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
13431 low
= CONST_DOUBLE_LOW (andop
);
13433 if (HOST_BITS_PER_WIDE_INT
< 64)
13435 HOST_WIDE_INT high
, shift_mask_high
;
13437 high
= CONST_DOUBLE_HIGH (andop
);
13441 shift_mask_high
= ~0;
13442 if (INTVAL (shiftop
) > 32)
13443 shift_mask_high
<<= INTVAL (shiftop
) - 32;
13445 lsb
= high
& -high
;
13447 if ((lsb
& shift_mask_high
) == 0)
13450 return high
== -lsb
;
13456 shift_mask_low
= ~0;
13457 shift_mask_low
<<= INTVAL (shiftop
);
13461 if ((lsb
& shift_mask_low
) == 0)
13464 return low
== -lsb
&& lsb
!= 1;
13470 /* Return 1 if operands will generate a valid arguments to rlwimi
13471 instruction for insert with right shift in 64-bit mode. The mask may
13472 not start on the first bit or stop on the last bit because wrap-around
13473 effects of instruction do not correspond to semantics of RTL insn. */
13476 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
13478 if (INTVAL (startop
) > 32
13479 && INTVAL (startop
) < 64
13480 && INTVAL (sizeop
) > 1
13481 && INTVAL (sizeop
) + INTVAL (startop
) < 64
13482 && INTVAL (shiftop
) > 0
13483 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
13484 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
13490 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13491 for lfq and stfq insns iff the registers are hard registers. */
13494 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
13496 /* We might have been passed a SUBREG. */
13497 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
13500 /* We might have been passed non floating point registers. */
13501 if (!FP_REGNO_P (REGNO (reg1
))
13502 || !FP_REGNO_P (REGNO (reg2
)))
13505 return (REGNO (reg1
) == REGNO (reg2
) - 1);
13508 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13509 addr1 and addr2 must be in consecutive memory locations
13510 (addr2 == addr1 + 8). */
13513 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
13516 unsigned int reg1
, reg2
;
13517 int offset1
, offset2
;
13519 /* The mems cannot be volatile. */
13520 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
13523 addr1
= XEXP (mem1
, 0);
13524 addr2
= XEXP (mem2
, 0);
13526 /* Extract an offset (if used) from the first addr. */
13527 if (GET_CODE (addr1
) == PLUS
)
13529 /* If not a REG, return zero. */
13530 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
13534 reg1
= REGNO (XEXP (addr1
, 0));
13535 /* The offset must be constant! */
13536 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
13538 offset1
= INTVAL (XEXP (addr1
, 1));
13541 else if (GET_CODE (addr1
) != REG
)
13545 reg1
= REGNO (addr1
);
13546 /* This was a simple (mem (reg)) expression. Offset is 0. */
13550 /* And now for the second addr. */
13551 if (GET_CODE (addr2
) == PLUS
)
13553 /* If not a REG, return zero. */
13554 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
13558 reg2
= REGNO (XEXP (addr2
, 0));
13559 /* The offset must be constant. */
13560 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
13562 offset2
= INTVAL (XEXP (addr2
, 1));
13565 else if (GET_CODE (addr2
) != REG
)
13569 reg2
= REGNO (addr2
);
13570 /* This was a simple (mem (reg)) expression. Offset is 0. */
13574 /* Both of these must have the same base register. */
13578 /* The offset for the second addr must be 8 more than the first addr. */
13579 if (offset2
!= offset1
+ 8)
13582 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13589 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
13591 static bool eliminated
= false;
13594 if (mode
!= SDmode
)
13595 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
13598 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
13599 gcc_assert (mem
!= NULL_RTX
);
13603 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
13604 cfun
->machine
->sdmode_stack_slot
= mem
;
13610 if (TARGET_DEBUG_ADDR
)
13612 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13613 GET_MODE_NAME (mode
));
13615 fprintf (stderr
, "\tNULL_RTX\n");
13624 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
13626 /* Don't walk into types. */
13627 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
13629 *walk_subtrees
= 0;
13633 switch (TREE_CODE (*tp
))
13642 case VIEW_CONVERT_EXPR
:
13643 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
13653 enum reload_reg_type
{
13655 VECTOR_REGISTER_TYPE
,
13656 OTHER_REGISTER_TYPE
13659 static enum reload_reg_type
13660 rs6000_reload_register_type (enum reg_class rclass
)
13666 return GPR_REGISTER_TYPE
;
13671 return VECTOR_REGISTER_TYPE
;
13674 return OTHER_REGISTER_TYPE
;
13678 /* Inform reload about cases where moving X with a mode MODE to a register in
13679 RCLASS requires an extra scratch or immediate register. Return the class
13680 needed for the immediate register.
13682 For VSX and Altivec, we may need a register to convert sp+offset into
13685 For misaligned 64-bit gpr loads and stores we need a register to
13686 convert an offset address to indirect. */
13689 rs6000_secondary_reload (bool in_p
,
13691 reg_class_t rclass_i
,
13692 enum machine_mode mode
,
13693 secondary_reload_info
*sri
)
13695 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13696 reg_class_t ret
= ALL_REGS
;
13697 enum insn_code icode
;
13698 bool default_p
= false;
13700 sri
->icode
= CODE_FOR_nothing
;
13702 /* Convert vector loads and stores into gprs to use an additional base
13704 icode
= rs6000_vector_reload
[mode
][in_p
!= false];
13705 if (icode
!= CODE_FOR_nothing
)
13708 sri
->icode
= CODE_FOR_nothing
;
13709 sri
->extra_cost
= 0;
13711 if (GET_CODE (x
) == MEM
)
13713 rtx addr
= XEXP (x
, 0);
13715 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13716 an extra register in that case, but it would need an extra
13717 register if the addressing is reg+reg or (reg+reg)&(-16). */
13718 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
13720 if (!legitimate_indirect_address_p (addr
, false)
13721 && !rs6000_legitimate_offset_address_p (TImode
, addr
,
13724 sri
->icode
= icode
;
13725 /* account for splitting the loads, and converting the
13726 address from reg+reg to reg. */
13727 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
13728 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
13731 /* Loads to and stores from vector registers can only do reg+reg
13732 addressing. Altivec registers can also do (reg+reg)&(-16). */
13733 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
13734 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
13736 if (!VECTOR_MEM_ALTIVEC_P (mode
)
13737 && GET_CODE (addr
) == AND
13738 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
13739 && INTVAL (XEXP (addr
, 1)) == -16
13740 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
13741 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
13743 sri
->icode
= icode
;
13744 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
13747 else if (!legitimate_indirect_address_p (addr
, false)
13748 && (rclass
== NO_REGS
13749 || !legitimate_indexed_address_p (addr
, false)))
13751 sri
->icode
= icode
;
13752 sri
->extra_cost
= 1;
13755 icode
= CODE_FOR_nothing
;
13757 /* Any other loads, including to pseudo registers which haven't been
13758 assigned to a register yet, default to require a scratch
13762 sri
->icode
= icode
;
13763 sri
->extra_cost
= 2;
13766 else if (REG_P (x
))
13768 int regno
= true_regnum (x
);
13770 icode
= CODE_FOR_nothing
;
13771 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
13775 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
13776 enum reload_reg_type rtype1
= rs6000_reload_register_type (rclass
);
13777 enum reload_reg_type rtype2
= rs6000_reload_register_type (xclass
);
13779 /* If memory is needed, use default_secondary_reload to create the
13781 if (rtype1
!= rtype2
|| rtype1
== OTHER_REGISTER_TYPE
)
13790 else if (TARGET_POWERPC64
13791 && rs6000_reload_register_type (rclass
) == GPR_REGISTER_TYPE
13793 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
13795 rtx off
= address_offset (XEXP (x
, 0));
13796 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
13798 if (off
!= NULL_RTX
13799 && (INTVAL (off
) & 3) != 0
13800 && (unsigned HOST_WIDE_INT
) INTVAL (off
) + 0x8000 < 0x10000 - extra
)
13803 sri
->icode
= CODE_FOR_reload_di_load
;
13805 sri
->icode
= CODE_FOR_reload_di_store
;
13806 sri
->extra_cost
= 2;
13812 else if (!TARGET_POWERPC64
13813 && rs6000_reload_register_type (rclass
) == GPR_REGISTER_TYPE
13815 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
13817 rtx off
= address_offset (XEXP (x
, 0));
13818 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
13820 /* We need a secondary reload only when our legitimate_address_p
13821 says the address is good (as otherwise the entire address
13822 will be reloaded). So for mode sizes of 8 and 16 this will
13823 be when the offset is in the ranges [0x7ffc,0x7fff] and
13824 [0x7ff4,0x7ff7] respectively. Note that the address we see
13825 here may have been manipulated by legitimize_reload_address. */
13826 if (off
!= NULL_RTX
13827 && ((unsigned HOST_WIDE_INT
) INTVAL (off
) - (0x8000 - extra
)
13831 sri
->icode
= CODE_FOR_reload_si_load
;
13833 sri
->icode
= CODE_FOR_reload_si_store
;
13834 sri
->extra_cost
= 2;
13844 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
13846 gcc_assert (ret
!= ALL_REGS
);
13848 if (TARGET_DEBUG_ADDR
)
13851 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13853 reg_class_names
[ret
],
13854 in_p
? "true" : "false",
13855 reg_class_names
[rclass
],
13856 GET_MODE_NAME (mode
));
13859 fprintf (stderr
, ", default secondary reload");
13861 if (sri
->icode
!= CODE_FOR_nothing
)
13862 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
13863 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
13865 fprintf (stderr
, "\n");
13873 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13874 to SP+reg addressing. */
13877 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
13879 int regno
= true_regnum (reg
);
13880 enum machine_mode mode
= GET_MODE (reg
);
13881 enum reg_class rclass
;
13883 rtx and_op2
= NULL_RTX
;
13886 rtx scratch_or_premodify
= scratch
;
13890 if (TARGET_DEBUG_ADDR
)
13892 fprintf (stderr
, "\nrs6000_secondary_reload_inner, type = %s\n",
13893 store_p
? "store" : "load");
13894 fprintf (stderr
, "reg:\n");
13896 fprintf (stderr
, "mem:\n");
13898 fprintf (stderr
, "scratch:\n");
13899 debug_rtx (scratch
);
13902 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
13903 gcc_assert (GET_CODE (mem
) == MEM
);
13904 rclass
= REGNO_REG_CLASS (regno
);
13905 addr
= XEXP (mem
, 0);
13909 /* GPRs can handle reg + small constant, all other addresses need to use
13910 the scratch register. */
13913 if (GET_CODE (addr
) == AND
)
13915 and_op2
= XEXP (addr
, 1);
13916 addr
= XEXP (addr
, 0);
13919 if (GET_CODE (addr
) == PRE_MODIFY
)
13921 scratch_or_premodify
= XEXP (addr
, 0);
13922 gcc_assert (REG_P (scratch_or_premodify
));
13923 gcc_assert (GET_CODE (XEXP (addr
, 1)) == PLUS
);
13924 addr
= XEXP (addr
, 1);
13927 if (GET_CODE (addr
) == PLUS
13928 && (and_op2
!= NULL_RTX
13929 || !rs6000_legitimate_offset_address_p (TImode
, addr
,
13932 addr_op1
= XEXP (addr
, 0);
13933 addr_op2
= XEXP (addr
, 1);
13934 gcc_assert (legitimate_indirect_address_p (addr_op1
, false));
13936 if (!REG_P (addr_op2
)
13937 && (GET_CODE (addr_op2
) != CONST_INT
13938 || !satisfies_constraint_I (addr_op2
)))
13940 if (TARGET_DEBUG_ADDR
)
13943 "\nMove plus addr to register %s, mode = %s: ",
13944 rs6000_reg_names
[REGNO (scratch
)],
13945 GET_MODE_NAME (mode
));
13946 debug_rtx (addr_op2
);
13948 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
13949 addr_op2
= scratch
;
13952 emit_insn (gen_rtx_SET (VOIDmode
,
13953 scratch_or_premodify
,
13954 gen_rtx_PLUS (Pmode
,
13958 addr
= scratch_or_premodify
;
13959 scratch_or_premodify
= scratch
;
13961 else if (!legitimate_indirect_address_p (addr
, false)
13962 && !rs6000_legitimate_offset_address_p (TImode
, addr
,
13965 if (TARGET_DEBUG_ADDR
)
13967 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
13968 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
13969 GET_MODE_NAME (mode
));
13972 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
13973 addr
= scratch_or_premodify
;
13974 scratch_or_premodify
= scratch
;
13978 /* Float/Altivec registers can only handle reg+reg addressing. Move
13979 other addresses into a scratch register. */
13984 /* With float regs, we need to handle the AND ourselves, since we can't
13985 use the Altivec instruction with an implicit AND -16. Allow scalar
13986 loads to float registers to use reg+offset even if VSX. */
13987 if (GET_CODE (addr
) == AND
13988 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
13989 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
13990 || INTVAL (XEXP (addr
, 1)) != -16
13991 || !VECTOR_MEM_ALTIVEC_P (mode
)))
13993 and_op2
= XEXP (addr
, 1);
13994 addr
= XEXP (addr
, 0);
13997 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13998 as the address later. */
13999 if (GET_CODE (addr
) == PRE_MODIFY
14000 && (!VECTOR_MEM_VSX_P (mode
)
14001 || and_op2
!= NULL_RTX
14002 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
14004 scratch_or_premodify
= XEXP (addr
, 0);
14005 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify
,
14007 gcc_assert (GET_CODE (XEXP (addr
, 1)) == PLUS
);
14008 addr
= XEXP (addr
, 1);
14011 if (legitimate_indirect_address_p (addr
, false) /* reg */
14012 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
14013 || GET_CODE (addr
) == PRE_MODIFY
/* VSX pre-modify */
14014 || (GET_CODE (addr
) == AND
/* Altivec memory */
14015 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
14016 && INTVAL (XEXP (addr
, 1)) == -16
14017 && VECTOR_MEM_ALTIVEC_P (mode
))
14018 || (rclass
== FLOAT_REGS
/* legacy float mem */
14019 && GET_MODE_SIZE (mode
) == 8
14020 && and_op2
== NULL_RTX
14021 && scratch_or_premodify
== scratch
14022 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
14025 else if (GET_CODE (addr
) == PLUS
)
14027 addr_op1
= XEXP (addr
, 0);
14028 addr_op2
= XEXP (addr
, 1);
14029 gcc_assert (REG_P (addr_op1
));
14031 if (TARGET_DEBUG_ADDR
)
14033 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
14034 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
14035 debug_rtx (addr_op2
);
14037 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
14038 emit_insn (gen_rtx_SET (VOIDmode
,
14039 scratch_or_premodify
,
14040 gen_rtx_PLUS (Pmode
,
14043 addr
= scratch_or_premodify
;
14044 scratch_or_premodify
= scratch
;
14047 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
14048 || GET_CODE (addr
) == CONST_INT
|| REG_P (addr
))
14050 if (TARGET_DEBUG_ADDR
)
14052 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
14053 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
14054 GET_MODE_NAME (mode
));
14058 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14059 addr
= scratch_or_premodify
;
14060 scratch_or_premodify
= scratch
;
14064 gcc_unreachable ();
14069 gcc_unreachable ();
14072 /* If the original address involved a pre-modify that we couldn't use the VSX
14073 memory instruction with update, and we haven't taken care of already,
14074 store the address in the pre-modify register and use that as the
14076 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
14078 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
14079 addr
= scratch_or_premodify
;
14082 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
14083 memory instruction, recreate the AND now, including the clobber which is
14084 generated by the general ANDSI3/ANDDI3 patterns for the
14085 andi. instruction. */
14086 if (and_op2
!= NULL_RTX
)
14088 if (! legitimate_indirect_address_p (addr
, false))
14090 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
14094 if (TARGET_DEBUG_ADDR
)
14096 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
14097 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
14098 debug_rtx (and_op2
);
14101 and_rtx
= gen_rtx_SET (VOIDmode
,
14103 gen_rtx_AND (Pmode
,
14107 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
14108 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
14109 gen_rtvec (2, and_rtx
, cc_clobber
)));
14113 /* Adjust the address if it changed. */
14114 if (addr
!= XEXP (mem
, 0))
14116 mem
= change_address (mem
, mode
, addr
);
14117 if (TARGET_DEBUG_ADDR
)
14118 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14121 /* Now create the move. */
14123 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14125 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14130 /* Convert reloads involving 64-bit gprs and misaligned offset
14131 addressing, or multiple 32-bit gprs and offsets that are too large,
14132 to use indirect addressing. */
14135 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
14137 int regno
= true_regnum (reg
);
14138 enum reg_class rclass
;
14140 rtx scratch_or_premodify
= scratch
;
14142 if (TARGET_DEBUG_ADDR
)
14144 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
14145 store_p
? "store" : "load");
14146 fprintf (stderr
, "reg:\n");
14148 fprintf (stderr
, "mem:\n");
14150 fprintf (stderr
, "scratch:\n");
14151 debug_rtx (scratch
);
14154 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
14155 gcc_assert (GET_CODE (mem
) == MEM
);
14156 rclass
= REGNO_REG_CLASS (regno
);
14157 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
14158 addr
= XEXP (mem
, 0);
14160 if (GET_CODE (addr
) == PRE_MODIFY
)
14162 scratch_or_premodify
= XEXP (addr
, 0);
14163 gcc_assert (REG_P (scratch_or_premodify
));
14164 addr
= XEXP (addr
, 1);
14166 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
14168 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14170 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
14172 /* Now create the move. */
14174 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14176 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14181 /* Allocate a 64-bit stack slot to be used for copying SDmode
14182 values through if this function has any SDmode references. */
14185 rs6000_alloc_sdmode_stack_slot (void)
14189 gimple_stmt_iterator gsi
;
14191 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
14194 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
14196 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
14199 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
14200 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
14206 /* Check for any SDmode parameters of the function. */
14207 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
14209 if (TREE_TYPE (t
) == error_mark_node
)
14212 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
14213 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
14215 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
14216 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
14224 rs6000_instantiate_decls (void)
14226 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
14227 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
14230 /* Given an rtx X being reloaded into a reg required to be
14231 in class CLASS, return the class of reg to actually use.
14232 In general this is just CLASS; but on some machines
14233 in some cases it is preferable to use a more restrictive class.
14235 On the RS/6000, we have to return NO_REGS when we want to reload a
14236 floating-point CONST_DOUBLE to force it to be copied to memory.
14238 We also don't want to reload integer values into floating-point
14239 registers if we can at all help it. In fact, this can
14240 cause reload to die, if it tries to generate a reload of CTR
14241 into a FP register and discovers it doesn't have the memory location
14244 ??? Would it be a good idea to have reload do the converse, that is
14245 try to reload floating modes into FP registers if possible?
14248 static enum reg_class
14249 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
14251 enum machine_mode mode
= GET_MODE (x
);
14253 if (VECTOR_UNIT_VSX_P (mode
)
14254 && x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
14257 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
14258 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
14259 && easy_vector_constant (x
, mode
))
14260 return ALTIVEC_REGS
;
14262 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
14265 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
14266 return GENERAL_REGS
;
14268 /* For VSX, prefer the traditional registers for 64-bit values because we can
14269 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14270 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14271 prefer Altivec loads.. */
14272 if (rclass
== VSX_REGS
)
14274 if (GET_MODE_SIZE (mode
) <= 8)
14277 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
14278 return ALTIVEC_REGS
;
14286 /* Debug version of rs6000_preferred_reload_class. */
14287 static enum reg_class
14288 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
14290 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
14293 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14295 reg_class_names
[ret
], reg_class_names
[rclass
],
14296 GET_MODE_NAME (GET_MODE (x
)));
14302 /* If we are copying between FP or AltiVec registers and anything else, we need
14303 a memory location. The exception is when we are targeting ppc64 and the
14304 move to/from fpr to gpr instructions are available. Also, under VSX, you
14305 can copy vector registers from the FP register set to the Altivec register
14306 set and vice versa. */
14309 rs6000_secondary_memory_needed (enum reg_class class1
,
14310 enum reg_class class2
,
14311 enum machine_mode mode
)
14313 if (class1
== class2
)
14316 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14317 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14318 between these classes. But we need memory for other things that can go in
14319 FLOAT_REGS like SFmode. */
14321 && (VECTOR_MEM_VSX_P (mode
) || VECTOR_UNIT_VSX_P (mode
))
14322 && (class1
== VSX_REGS
|| class1
== ALTIVEC_REGS
14323 || class1
== FLOAT_REGS
))
14324 return (class2
!= VSX_REGS
&& class2
!= ALTIVEC_REGS
14325 && class2
!= FLOAT_REGS
);
14327 if (class1
== VSX_REGS
|| class2
== VSX_REGS
)
14330 if (class1
== FLOAT_REGS
14331 && (!TARGET_MFPGPR
|| !TARGET_POWERPC64
14332 || ((mode
!= DFmode
)
14333 && (mode
!= DDmode
)
14334 && (mode
!= DImode
))))
14337 if (class2
== FLOAT_REGS
14338 && (!TARGET_MFPGPR
|| !TARGET_POWERPC64
14339 || ((mode
!= DFmode
)
14340 && (mode
!= DDmode
)
14341 && (mode
!= DImode
))))
14344 if (class1
== ALTIVEC_REGS
|| class2
== ALTIVEC_REGS
)
14350 /* Debug version of rs6000_secondary_memory_needed. */
14352 rs6000_debug_secondary_memory_needed (enum reg_class class1
,
14353 enum reg_class class2
,
14354 enum machine_mode mode
)
14356 bool ret
= rs6000_secondary_memory_needed (class1
, class2
, mode
);
14359 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14360 "class2 = %s, mode = %s\n",
14361 ret
? "true" : "false", reg_class_names
[class1
],
14362 reg_class_names
[class2
], GET_MODE_NAME (mode
));
14367 /* Return the register class of a scratch register needed to copy IN into
14368 or out of a register in RCLASS in MODE. If it can be done directly,
14369 NO_REGS is returned. */
14371 static enum reg_class
14372 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
14377 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
14379 && MACHOPIC_INDIRECT
14383 /* We cannot copy a symbolic operand directly into anything
14384 other than BASE_REGS for TARGET_ELF. So indicate that a
14385 register from BASE_REGS is needed as an intermediate
14388 On Darwin, pic addresses require a load from memory, which
14389 needs a base register. */
14390 if (rclass
!= BASE_REGS
14391 && (GET_CODE (in
) == SYMBOL_REF
14392 || GET_CODE (in
) == HIGH
14393 || GET_CODE (in
) == LABEL_REF
14394 || GET_CODE (in
) == CONST
))
14398 if (GET_CODE (in
) == REG
)
14400 regno
= REGNO (in
);
14401 if (regno
>= FIRST_PSEUDO_REGISTER
)
14403 regno
= true_regnum (in
);
14404 if (regno
>= FIRST_PSEUDO_REGISTER
)
14408 else if (GET_CODE (in
) == SUBREG
)
14410 regno
= true_regnum (in
);
14411 if (regno
>= FIRST_PSEUDO_REGISTER
)
14417 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14419 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
14420 || (regno
>= 0 && INT_REGNO_P (regno
)))
14423 /* Constants, memory, and FP registers can go into FP registers. */
14424 if ((regno
== -1 || FP_REGNO_P (regno
))
14425 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
14426 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
14428 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14431 && (regno
== -1 || VSX_REGNO_P (regno
))
14432 && VSX_REG_CLASS_P (rclass
))
14435 /* Memory, and AltiVec registers can go into AltiVec registers. */
14436 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
14437 && rclass
== ALTIVEC_REGS
)
14440 /* We can copy among the CR registers. */
14441 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
14442 && regno
>= 0 && CR_REGNO_P (regno
))
14445 /* Otherwise, we need GENERAL_REGS. */
14446 return GENERAL_REGS
;
14449 /* Debug version of rs6000_secondary_reload_class. */
14450 static enum reg_class
14451 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
14452 enum machine_mode mode
, rtx in
)
14454 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
14456 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14457 "mode = %s, input rtx:\n",
14458 reg_class_names
[ret
], reg_class_names
[rclass
],
14459 GET_MODE_NAME (mode
));
14465 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14468 rs6000_cannot_change_mode_class (enum machine_mode from
,
14469 enum machine_mode to
,
14470 enum reg_class rclass
)
14472 unsigned from_size
= GET_MODE_SIZE (from
);
14473 unsigned to_size
= GET_MODE_SIZE (to
);
14475 if (from_size
!= to_size
)
14477 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
14478 return ((from_size
< 8 || to_size
< 8 || TARGET_IEEEQUAD
)
14479 && reg_classes_intersect_p (xclass
, rclass
));
14482 if (TARGET_E500_DOUBLE
14483 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
14484 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
14485 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
14486 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
14487 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
14490 /* Since the VSX register set includes traditional floating point registers
14491 and altivec registers, just check for the size being different instead of
14492 trying to check whether the modes are vector modes. Otherwise it won't
14493 allow say DF and DI to change classes. */
14494 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
14495 return (from_size
!= 8 && from_size
!= 16);
14497 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
14498 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
14501 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
14502 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
14508 /* Debug version of rs6000_cannot_change_mode_class. */
14510 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
14511 enum machine_mode to
,
14512 enum reg_class rclass
)
14514 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
14517 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14518 "to = %s, rclass = %s\n",
14519 ret
? "true" : "false",
14520 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
14521 reg_class_names
[rclass
]);
14526 /* Given a comparison operation, return the bit number in CCR to test. We
14527 know this is a valid comparison.
14529 SCC_P is 1 if this is for an scc. That means that %D will have been
14530 used instead of %C, so the bits will be in different places.
14532 Return -1 if OP isn't a valid comparison for some reason. */
14535 ccr_bit (rtx op
, int scc_p
)
14537 enum rtx_code code
= GET_CODE (op
);
14538 enum machine_mode cc_mode
;
14543 if (!COMPARISON_P (op
))
14546 reg
= XEXP (op
, 0);
14548 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
14550 cc_mode
= GET_MODE (reg
);
14551 cc_regnum
= REGNO (reg
);
14552 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
14554 validate_condition_mode (code
, cc_mode
);
14556 /* When generating a sCOND operation, only positive conditions are
14559 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
14560 || code
== GTU
|| code
== LTU
);
14565 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
14567 return base_bit
+ 2;
14568 case GT
: case GTU
: case UNLE
:
14569 return base_bit
+ 1;
14570 case LT
: case LTU
: case UNGE
:
14572 case ORDERED
: case UNORDERED
:
14573 return base_bit
+ 3;
14576 /* If scc, we will have done a cror to put the bit in the
14577 unordered position. So test that bit. For integer, this is ! LT
14578 unless this is an scc insn. */
14579 return scc_p
? base_bit
+ 3 : base_bit
;
14582 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
14585 gcc_unreachable ();
14589 /* Return the GOT register. */
14592 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
14594 /* The second flow pass currently (June 1999) can't update
14595 regs_ever_live without disturbing other parts of the compiler, so
14596 update it here to make the prolog/epilogue code happy. */
14597 if (!can_create_pseudo_p ()
14598 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
14599 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
14601 crtl
->uses_pic_offset_table
= 1;
14603 return pic_offset_table_rtx
;
14606 static rs6000_stack_t stack_info
;
14608 /* Function to init struct machine_function.
14609 This will be called, via a pointer variable,
14610 from push_function_context. */
14612 static struct machine_function
*
14613 rs6000_init_machine_status (void)
14615 stack_info
.reload_completed
= 0;
14616 return ggc_alloc_cleared_machine_function ();
14619 /* These macros test for integers and extract the low-order bits. */
14621 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14622 && GET_MODE (X) == VOIDmode)
14624 #define INT_LOWPART(X) \
14625 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14628 extract_MB (rtx op
)
14631 unsigned long val
= INT_LOWPART (op
);
14633 /* If the high bit is zero, the value is the first 1 bit we find
14635 if ((val
& 0x80000000) == 0)
14637 gcc_assert (val
& 0xffffffff);
14640 while (((val
<<= 1) & 0x80000000) == 0)
14645 /* If the high bit is set and the low bit is not, or the mask is all
14646 1's, the value is zero. */
14647 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
14650 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14653 while (((val
>>= 1) & 1) != 0)
14660 extract_ME (rtx op
)
14663 unsigned long val
= INT_LOWPART (op
);
14665 /* If the low bit is zero, the value is the first 1 bit we find from
14667 if ((val
& 1) == 0)
14669 gcc_assert (val
& 0xffffffff);
14672 while (((val
>>= 1) & 1) == 0)
14678 /* If the low bit is set and the high bit is not, or the mask is all
14679 1's, the value is 31. */
14680 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
14683 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14686 while (((val
<<= 1) & 0x80000000) != 0)
14692 /* Locate some local-dynamic symbol still in use by this function
14693 so that we can print its name in some tls_ld pattern. */
14695 static const char *
14696 rs6000_get_some_local_dynamic_name (void)
14700 if (cfun
->machine
->some_ld_name
)
14701 return cfun
->machine
->some_ld_name
;
14703 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14705 && for_each_rtx (&PATTERN (insn
),
14706 rs6000_get_some_local_dynamic_name_1
, 0))
14707 return cfun
->machine
->some_ld_name
;
14709 gcc_unreachable ();
14712 /* Helper function for rs6000_get_some_local_dynamic_name. */
14715 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
14719 if (GET_CODE (x
) == SYMBOL_REF
)
14721 const char *str
= XSTR (x
, 0);
14722 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
14724 cfun
->machine
->some_ld_name
= str
;
14732 /* Write out a function code label. */
14735 rs6000_output_function_entry (FILE *file
, const char *fname
)
14737 if (fname
[0] != '.')
14739 switch (DEFAULT_ABI
)
14742 gcc_unreachable ();
14748 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
14757 RS6000_OUTPUT_BASENAME (file
, fname
);
14760 /* Print an operand. Recognize special options, documented below. */
14763 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14764 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14766 #define SMALL_DATA_RELOC "sda21"
14767 #define SMALL_DATA_REG 0
14771 print_operand (FILE *file
, rtx x
, int code
)
14774 unsigned HOST_WIDE_INT uval
;
14778 /* %a is output_address. */
14781 /* If constant, low-order 16 bits of constant, unsigned.
14782 Otherwise, write normally. */
14784 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
14786 print_operand (file
, x
, 0);
14790 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14791 for 64-bit mask direction. */
14792 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
14795 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14799 /* Like 'J' but get to the GT bit only. */
14800 gcc_assert (REG_P (x
));
14802 /* Bit 1 is GT bit. */
14803 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
14805 /* Add one for shift count in rlinm for scc. */
14806 fprintf (file
, "%d", i
+ 1);
14810 /* X is a CR register. Print the number of the EQ bit of the CR */
14811 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14812 output_operand_lossage ("invalid %%E value");
14814 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
14818 /* X is a CR register. Print the shift count needed to move it
14819 to the high-order four bits. */
14820 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14821 output_operand_lossage ("invalid %%f value");
14823 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
14827 /* Similar, but print the count for the rotate in the opposite
14829 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14830 output_operand_lossage ("invalid %%F value");
14832 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
14836 /* X is a constant integer. If it is negative, print "m",
14837 otherwise print "z". This is to make an aze or ame insn. */
14838 if (GET_CODE (x
) != CONST_INT
)
14839 output_operand_lossage ("invalid %%G value");
14840 else if (INTVAL (x
) >= 0)
14847 /* If constant, output low-order five bits. Otherwise, write
14850 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
14852 print_operand (file
, x
, 0);
14856 /* If constant, output low-order six bits. Otherwise, write
14859 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
14861 print_operand (file
, x
, 0);
14865 /* Print `i' if this is a constant, else nothing. */
14871 /* Write the bit number in CCR for jump. */
14872 i
= ccr_bit (x
, 0);
14874 output_operand_lossage ("invalid %%j code");
14876 fprintf (file
, "%d", i
);
14880 /* Similar, but add one for shift count in rlinm for scc and pass
14881 scc flag to `ccr_bit'. */
14882 i
= ccr_bit (x
, 1);
14884 output_operand_lossage ("invalid %%J code");
14886 /* If we want bit 31, write a shift count of zero, not 32. */
14887 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
14891 /* X must be a constant. Write the 1's complement of the
14894 output_operand_lossage ("invalid %%k value");
14896 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
14900 /* X must be a symbolic constant on ELF. Write an
14901 expression suitable for an 'addi' that adds in the low 16
14902 bits of the MEM. */
14903 if (GET_CODE (x
) == CONST
)
14905 if (GET_CODE (XEXP (x
, 0)) != PLUS
14906 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
14907 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
14908 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
14909 output_operand_lossage ("invalid %%K value");
14911 print_operand_address (file
, x
);
14912 fputs ("@l", file
);
14915 /* %l is output_asm_label. */
14918 /* Write second word of DImode or DFmode reference. Works on register
14919 or non-indexed memory only. */
14921 fputs (reg_names
[REGNO (x
) + 1], file
);
14922 else if (MEM_P (x
))
14924 /* Handle possible auto-increment. Since it is pre-increment and
14925 we have already done it, we can just use an offset of word. */
14926 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
14927 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
14928 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
14930 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
14931 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
14934 output_address (XEXP (adjust_address_nv (x
, SImode
,
14938 if (small_data_operand (x
, GET_MODE (x
)))
14939 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
14940 reg_names
[SMALL_DATA_REG
]);
14945 /* MB value for a mask operand. */
14946 if (! mask_operand (x
, SImode
))
14947 output_operand_lossage ("invalid %%m value");
14949 fprintf (file
, "%d", extract_MB (x
));
14953 /* ME value for a mask operand. */
14954 if (! mask_operand (x
, SImode
))
14955 output_operand_lossage ("invalid %%M value");
14957 fprintf (file
, "%d", extract_ME (x
));
14960 /* %n outputs the negative of its operand. */
14963 /* Write the number of elements in the vector times 4. */
14964 if (GET_CODE (x
) != PARALLEL
)
14965 output_operand_lossage ("invalid %%N value");
14967 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
14971 /* Similar, but subtract 1 first. */
14972 if (GET_CODE (x
) != PARALLEL
)
14973 output_operand_lossage ("invalid %%O value");
14975 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
14979 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14981 || INT_LOWPART (x
) < 0
14982 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
14983 output_operand_lossage ("invalid %%p value");
14985 fprintf (file
, "%d", i
);
14989 /* The operand must be an indirect memory reference. The result
14990 is the register name. */
14991 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
14992 || REGNO (XEXP (x
, 0)) >= 32)
14993 output_operand_lossage ("invalid %%P value");
14995 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
14999 /* This outputs the logical code corresponding to a boolean
15000 expression. The expression may have one or both operands
15001 negated (if one, only the first one). For condition register
15002 logical operations, it will also treat the negated
15003 CR codes as NOTs, but not handle NOTs of them. */
15005 const char *const *t
= 0;
15007 enum rtx_code code
= GET_CODE (x
);
15008 static const char * const tbl
[3][3] = {
15009 { "and", "andc", "nor" },
15010 { "or", "orc", "nand" },
15011 { "xor", "eqv", "xor" } };
15015 else if (code
== IOR
)
15017 else if (code
== XOR
)
15020 output_operand_lossage ("invalid %%q value");
15022 if (GET_CODE (XEXP (x
, 0)) != NOT
)
15026 if (GET_CODE (XEXP (x
, 1)) == NOT
)
15037 if (! TARGET_MFCRF
)
15043 /* X is a CR register. Print the mask for `mtcrf'. */
15044 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
15045 output_operand_lossage ("invalid %%R value");
15047 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
15051 /* Low 5 bits of 32 - value */
15053 output_operand_lossage ("invalid %%s value");
15055 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
15059 /* PowerPC64 mask position. All 0's is excluded.
15060 CONST_INT 32-bit mask is considered sign-extended so any
15061 transition must occur within the CONST_INT, not on the boundary. */
15062 if (! mask64_operand (x
, DImode
))
15063 output_operand_lossage ("invalid %%S value");
15065 uval
= INT_LOWPART (x
);
15067 if (uval
& 1) /* Clear Left */
15069 #if HOST_BITS_PER_WIDE_INT > 64
15070 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
15074 else /* Clear Right */
15077 #if HOST_BITS_PER_WIDE_INT > 64
15078 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
15084 gcc_assert (i
>= 0);
15085 fprintf (file
, "%d", i
);
15089 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15090 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
15092 /* Bit 3 is OV bit. */
15093 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
15095 /* If we want bit 31, write a shift count of zero, not 32. */
15096 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
15100 /* Print the symbolic name of a branch target register. */
15101 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
15102 && REGNO (x
) != CTR_REGNO
))
15103 output_operand_lossage ("invalid %%T value");
15104 else if (REGNO (x
) == LR_REGNO
)
15105 fputs ("lr", file
);
15107 fputs ("ctr", file
);
15111 /* High-order 16 bits of constant for use in unsigned operand. */
15113 output_operand_lossage ("invalid %%u value");
15115 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
15116 (INT_LOWPART (x
) >> 16) & 0xffff);
15120 /* High-order 16 bits of constant for use in signed operand. */
15122 output_operand_lossage ("invalid %%v value");
15124 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
15125 (INT_LOWPART (x
) >> 16) & 0xffff);
15129 /* Print `u' if this has an auto-increment or auto-decrement. */
15131 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
15132 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
15133 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
15138 /* Print the trap code for this operand. */
15139 switch (GET_CODE (x
))
15142 fputs ("eq", file
); /* 4 */
15145 fputs ("ne", file
); /* 24 */
15148 fputs ("lt", file
); /* 16 */
15151 fputs ("le", file
); /* 20 */
15154 fputs ("gt", file
); /* 8 */
15157 fputs ("ge", file
); /* 12 */
15160 fputs ("llt", file
); /* 2 */
15163 fputs ("lle", file
); /* 6 */
15166 fputs ("lgt", file
); /* 1 */
15169 fputs ("lge", file
); /* 5 */
15172 gcc_unreachable ();
15177 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15180 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
15181 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
15183 print_operand (file
, x
, 0);
15187 /* MB value for a PowerPC64 rldic operand. */
15188 i
= clz_hwi (GET_CODE (x
) == CONST_INT
15189 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
15191 #if HOST_BITS_PER_WIDE_INT == 32
15192 if (GET_CODE (x
) == CONST_INT
&& i
> 0)
15193 i
+= 32; /* zero-extend high-part was all 0's */
15194 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
15195 i
= clz_hwi (CONST_DOUBLE_LOW (x
)) + 32;
15198 fprintf (file
, "%d", i
);
15202 /* X is a FPR or Altivec register used in a VSX context. */
15203 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
15204 output_operand_lossage ("invalid %%x value");
15207 int reg
= REGNO (x
);
15208 int vsx_reg
= (FP_REGNO_P (reg
)
15210 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
15212 #ifdef TARGET_REGNAMES
15213 if (TARGET_REGNAMES
)
15214 fprintf (file
, "%%vs%d", vsx_reg
);
15217 fprintf (file
, "%d", vsx_reg
);
15223 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
15224 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
15225 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
15230 /* Like 'L', for third word of TImode */
15232 fputs (reg_names
[REGNO (x
) + 2], file
);
15233 else if (MEM_P (x
))
15235 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15236 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15237 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
15238 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15239 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
15241 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
15242 if (small_data_operand (x
, GET_MODE (x
)))
15243 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15244 reg_names
[SMALL_DATA_REG
]);
15249 /* X is a SYMBOL_REF. Write out the name preceded by a
15250 period and without any trailing data in brackets. Used for function
15251 names. If we are configured for System V (or the embedded ABI) on
15252 the PowerPC, do not emit the period, since those systems do not use
15253 TOCs and the like. */
15254 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
15256 /* Mark the decl as referenced so that cgraph will output the
15258 if (SYMBOL_REF_DECL (x
))
15259 mark_decl_referenced (SYMBOL_REF_DECL (x
));
15261 /* For macho, check to see if we need a stub. */
15264 const char *name
= XSTR (x
, 0);
15266 if (darwin_emit_branch_islands
15267 && MACHOPIC_INDIRECT
15268 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
15269 name
= machopic_indirection_name (x
, /*stub_p=*/true);
15271 assemble_name (file
, name
);
15273 else if (!DOT_SYMBOLS
)
15274 assemble_name (file
, XSTR (x
, 0));
15276 rs6000_output_function_entry (file
, XSTR (x
, 0));
15280 /* Like 'L', for last word of TImode. */
15282 fputs (reg_names
[REGNO (x
) + 3], file
);
15283 else if (MEM_P (x
))
15285 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15286 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15287 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
15288 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15289 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
15291 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
15292 if (small_data_operand (x
, GET_MODE (x
)))
15293 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15294 reg_names
[SMALL_DATA_REG
]);
15298 /* Print AltiVec or SPE memory operand. */
15303 gcc_assert (MEM_P (x
));
15307 /* Ugly hack because %y is overloaded. */
15308 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
15309 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
15310 || GET_MODE (x
) == TFmode
15311 || GET_MODE (x
) == TImode
))
15313 /* Handle [reg]. */
15316 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
15319 /* Handle [reg+UIMM]. */
15320 else if (GET_CODE (tmp
) == PLUS
&&
15321 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
15325 gcc_assert (REG_P (XEXP (tmp
, 0)));
15327 x
= INTVAL (XEXP (tmp
, 1));
15328 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
15332 /* Fall through. Must be [reg+reg]. */
15334 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
15335 && GET_CODE (tmp
) == AND
15336 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
15337 && INTVAL (XEXP (tmp
, 1)) == -16)
15338 tmp
= XEXP (tmp
, 0);
15339 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
15340 && GET_CODE (tmp
) == PRE_MODIFY
)
15341 tmp
= XEXP (tmp
, 1);
15343 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
15346 if (!GET_CODE (tmp
) == PLUS
15347 || !REG_P (XEXP (tmp
, 0))
15348 || !REG_P (XEXP (tmp
, 1)))
15350 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15354 if (REGNO (XEXP (tmp
, 0)) == 0)
15355 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
15356 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
15358 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
15359 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
15366 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
15367 else if (MEM_P (x
))
15369 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15370 know the width from the mode. */
15371 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
15372 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
15373 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
15374 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15375 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
15376 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
15377 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15378 output_address (XEXP (XEXP (x
, 0), 1));
15380 output_address (XEXP (x
, 0));
15384 if (toc_relative_expr_p (x
, false))
15385 /* This hack along with a corresponding hack in
15386 rs6000_output_addr_const_extra arranges to output addends
15387 where the assembler expects to find them. eg.
15388 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
15389 without this hack would be output as "x@toc+4". We
15391 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
15393 output_addr_const (file
, x
);
15398 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
15402 output_operand_lossage ("invalid %%xn code");
15406 /* Print the address of an operand. */
15409 print_operand_address (FILE *file
, rtx x
)
15412 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
15413 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
15414 || GET_CODE (x
) == LABEL_REF
)
15416 output_addr_const (file
, x
);
15417 if (small_data_operand (x
, GET_MODE (x
)))
15418 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15419 reg_names
[SMALL_DATA_REG
]);
15421 gcc_assert (!TARGET_TOC
);
15423 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
15424 && REG_P (XEXP (x
, 1)))
15426 if (REGNO (XEXP (x
, 0)) == 0)
15427 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
15428 reg_names
[ REGNO (XEXP (x
, 0)) ]);
15430 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
15431 reg_names
[ REGNO (XEXP (x
, 1)) ]);
15433 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
15434 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
15435 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
15436 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
15438 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
15439 && CONSTANT_P (XEXP (x
, 1)))
15441 fprintf (file
, "lo16(");
15442 output_addr_const (file
, XEXP (x
, 1));
15443 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15447 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
15448 && CONSTANT_P (XEXP (x
, 1)))
15450 output_addr_const (file
, XEXP (x
, 1));
15451 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15454 else if (toc_relative_expr_p (x
, false))
15456 /* This hack along with a corresponding hack in
15457 rs6000_output_addr_const_extra arranges to output addends
15458 where the assembler expects to find them. eg.
15460 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
15461 without this hack would be output as "x@toc+8@l(9)". We
15462 want "x+8@toc@l(9)". */
15463 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
15464 if (GET_CODE (x
) == LO_SUM
)
15465 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
15467 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
15470 gcc_unreachable ();
15473 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15476 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
15478 if (GET_CODE (x
) == UNSPEC
)
15479 switch (XINT (x
, 1))
15481 case UNSPEC_TOCREL
:
15482 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
15483 && REG_P (XVECEXP (x
, 0, 1))
15484 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
15485 output_addr_const (file
, XVECEXP (x
, 0, 0));
15486 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
15488 if (INTVAL (tocrel_offset
) >= 0)
15489 fprintf (file
, "+");
15490 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
15492 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
15495 assemble_name (file
, toc_label_name
);
15497 else if (TARGET_ELF
)
15498 fputs ("@toc", file
);
15502 case UNSPEC_MACHOPIC_OFFSET
:
15503 output_addr_const (file
, XVECEXP (x
, 0, 0));
15505 machopic_output_function_base_name (file
);
15512 /* Target hook for assembling integer objects. The PowerPC version has
15513 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15514 is defined. It also needs to handle DI-mode objects on 64-bit
15518 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
15520 #ifdef RELOCATABLE_NEEDS_FIXUP
15521 /* Special handling for SI values. */
15522 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
15524 static int recurse
= 0;
15526 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15527 the .fixup section. Since the TOC section is already relocated, we
15528 don't need to mark it here. We used to skip the text section, but it
15529 should never be valid for relocated addresses to be placed in the text
15531 if (TARGET_RELOCATABLE
15532 && in_section
!= toc_section
15534 && GET_CODE (x
) != CONST_INT
15535 && GET_CODE (x
) != CONST_DOUBLE
15541 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
15543 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
15544 fprintf (asm_out_file
, "\t.long\t(");
15545 output_addr_const (asm_out_file
, x
);
15546 fprintf (asm_out_file
, ")@fixup\n");
15547 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
15548 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
15549 fprintf (asm_out_file
, "\t.long\t");
15550 assemble_name (asm_out_file
, buf
);
15551 fprintf (asm_out_file
, "\n\t.previous\n");
15555 /* Remove initial .'s to turn a -mcall-aixdesc function
15556 address into the address of the descriptor, not the function
15558 else if (GET_CODE (x
) == SYMBOL_REF
15559 && XSTR (x
, 0)[0] == '.'
15560 && DEFAULT_ABI
== ABI_AIX
)
15562 const char *name
= XSTR (x
, 0);
15563 while (*name
== '.')
15566 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
15570 #endif /* RELOCATABLE_NEEDS_FIXUP */
15571 return default_assemble_integer (x
, size
, aligned_p
);
15574 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15575 /* Emit an assembler directive to set symbol visibility for DECL to
15576 VISIBILITY_TYPE. */
15579 rs6000_assemble_visibility (tree decl
, int vis
)
15584 /* Functions need to have their entry point symbol visibility set as
15585 well as their descriptor symbol visibility. */
15586 if (DEFAULT_ABI
== ABI_AIX
15588 && TREE_CODE (decl
) == FUNCTION_DECL
)
15590 static const char * const visibility_types
[] = {
15591 NULL
, "internal", "hidden", "protected"
15594 const char *name
, *type
;
15596 name
= ((* targetm
.strip_name_encoding
)
15597 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
15598 type
= visibility_types
[vis
];
15600 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
15601 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
15604 default_assemble_visibility (decl
, vis
);
15609 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
15611 /* Reversal of FP compares takes care -- an ordered compare
15612 becomes an unordered compare and vice versa. */
15613 if (mode
== CCFPmode
15614 && (!flag_finite_math_only
15615 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
15616 || code
== UNEQ
|| code
== LTGT
))
15617 return reverse_condition_maybe_unordered (code
);
15619 return reverse_condition (code
);
15622 /* Generate a compare for CODE. Return a brand-new rtx that
15623 represents the result of the compare. */
15626 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
15628 enum machine_mode comp_mode
;
15629 rtx compare_result
;
15630 enum rtx_code code
= GET_CODE (cmp
);
15631 rtx op0
= XEXP (cmp
, 0);
15632 rtx op1
= XEXP (cmp
, 1);
15634 if (FLOAT_MODE_P (mode
))
15635 comp_mode
= CCFPmode
;
15636 else if (code
== GTU
|| code
== LTU
15637 || code
== GEU
|| code
== LEU
)
15638 comp_mode
= CCUNSmode
;
15639 else if ((code
== EQ
|| code
== NE
)
15640 && unsigned_reg_p (op0
)
15641 && (unsigned_reg_p (op1
)
15642 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
15643 /* These are unsigned values, perhaps there will be a later
15644 ordering compare that can be shared with this one. */
15645 comp_mode
= CCUNSmode
;
15647 comp_mode
= CCmode
;
15649 /* If we have an unsigned compare, make sure we don't have a signed value as
15651 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
15652 && INTVAL (op1
) < 0)
15654 op0
= copy_rtx_if_shared (op0
);
15655 op1
= force_reg (GET_MODE (op0
), op1
);
15656 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
15659 /* First, the compare. */
15660 compare_result
= gen_reg_rtx (comp_mode
);
15662 /* E500 FP compare instructions on the GPRs. Yuck! */
15663 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
15664 && FLOAT_MODE_P (mode
))
15666 rtx cmp
, or_result
, compare_result2
;
15667 enum machine_mode op_mode
= GET_MODE (op0
);
15669 if (op_mode
== VOIDmode
)
15670 op_mode
= GET_MODE (op1
);
15672 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15673 This explains the following mess. */
15677 case EQ
: case UNEQ
: case NE
: case LTGT
:
15681 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15682 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
15683 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
15687 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15688 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
15689 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
15693 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15694 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
15695 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
15699 gcc_unreachable ();
15703 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
15707 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15708 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
15709 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
15713 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15714 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
15715 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
15719 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15720 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
15721 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
15725 gcc_unreachable ();
15729 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
15733 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15734 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
15735 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
15739 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15740 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
15741 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
15745 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15746 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
15747 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
15751 gcc_unreachable ();
15755 gcc_unreachable ();
15758 /* Synthesize LE and GE from LT/GT || EQ. */
15759 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
15765 case LE
: code
= LT
; break;
15766 case GE
: code
= GT
; break;
15767 case LEU
: code
= LT
; break;
15768 case GEU
: code
= GT
; break;
15769 default: gcc_unreachable ();
15772 compare_result2
= gen_reg_rtx (CCFPmode
);
15778 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15779 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
15780 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
15784 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15785 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
15786 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
15790 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15791 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
15792 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
15796 gcc_unreachable ();
15800 /* OR them together. */
15801 or_result
= gen_reg_rtx (CCFPmode
);
15802 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
15804 compare_result
= or_result
;
15809 if (code
== NE
|| code
== LTGT
)
15819 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15820 CLOBBERs to match cmptf_internal2 pattern. */
15821 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
15822 && GET_MODE (op0
) == TFmode
15823 && !TARGET_IEEEQUAD
15824 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
15825 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
15827 gen_rtx_SET (VOIDmode
,
15829 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
15830 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15831 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15832 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15833 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15834 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15835 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15836 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15837 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15838 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
15839 else if (GET_CODE (op1
) == UNSPEC
15840 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
15842 rtx op1b
= XVECEXP (op1
, 0, 0);
15843 comp_mode
= CCEQmode
;
15844 compare_result
= gen_reg_rtx (CCEQmode
);
15846 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
15848 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
15851 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
15852 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
15855 /* Some kinds of FP comparisons need an OR operation;
15856 under flag_finite_math_only we don't bother. */
15857 if (FLOAT_MODE_P (mode
)
15858 && !flag_finite_math_only
15859 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
15860 && (code
== LE
|| code
== GE
15861 || code
== UNEQ
|| code
== LTGT
15862 || code
== UNGT
|| code
== UNLT
))
15864 enum rtx_code or1
, or2
;
15865 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
15866 rtx or_result
= gen_reg_rtx (CCEQmode
);
15870 case LE
: or1
= LT
; or2
= EQ
; break;
15871 case GE
: or1
= GT
; or2
= EQ
; break;
15872 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
15873 case LTGT
: or1
= LT
; or2
= GT
; break;
15874 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
15875 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
15876 default: gcc_unreachable ();
15878 validate_condition_mode (or1
, comp_mode
);
15879 validate_condition_mode (or2
, comp_mode
);
15880 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
15881 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
15882 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
15883 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
15885 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
15887 compare_result
= or_result
;
15891 validate_condition_mode (code
, GET_MODE (compare_result
));
15893 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
15897 /* Emit the RTL for an sISEL pattern. */
15900 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
15902 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
15906 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
15909 enum machine_mode op_mode
;
15910 enum rtx_code cond_code
;
15911 rtx result
= operands
[0];
15913 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
15915 rs6000_emit_sISEL (mode
, operands
);
15919 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
15920 cond_code
= GET_CODE (condition_rtx
);
15922 if (FLOAT_MODE_P (mode
)
15923 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
15927 PUT_MODE (condition_rtx
, SImode
);
15928 t
= XEXP (condition_rtx
, 0);
15930 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
15932 if (cond_code
== NE
)
15933 emit_insn (gen_e500_flip_gt_bit (t
, t
));
15935 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
15939 if (cond_code
== NE
15940 || cond_code
== GE
|| cond_code
== LE
15941 || cond_code
== GEU
|| cond_code
== LEU
15942 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
15944 rtx not_result
= gen_reg_rtx (CCEQmode
);
15945 rtx not_op
, rev_cond_rtx
;
15946 enum machine_mode cc_mode
;
15948 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
15950 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
15951 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
15952 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
15953 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
15954 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
15957 op_mode
= GET_MODE (XEXP (operands
[1], 0));
15958 if (op_mode
== VOIDmode
)
15959 op_mode
= GET_MODE (XEXP (operands
[1], 1));
15961 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
15963 PUT_MODE (condition_rtx
, DImode
);
15964 convert_move (result
, condition_rtx
, 0);
15968 PUT_MODE (condition_rtx
, SImode
);
15969 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
15973 /* Emit a branch of kind CODE to location LOC. */
15976 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
15978 rtx condition_rtx
, loc_ref
;
15980 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
15981 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
15982 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
15983 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
15984 loc_ref
, pc_rtx
)));
15987 /* Return the string to output a conditional branch to LABEL, which is
15988 the operand template of the label, or NULL if the branch is really a
15989 conditional return.
15991 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15992 condition code register and its mode specifies what kind of
15993 comparison we made.
15995 REVERSED is nonzero if we should reverse the sense of the comparison.
15997 INSN is the insn. */
16000 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
16002 static char string
[64];
16003 enum rtx_code code
= GET_CODE (op
);
16004 rtx cc_reg
= XEXP (op
, 0);
16005 enum machine_mode mode
= GET_MODE (cc_reg
);
16006 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
16007 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
16008 int really_reversed
= reversed
^ need_longbranch
;
16014 validate_condition_mode (code
, mode
);
16016 /* Work out which way this really branches. We could use
16017 reverse_condition_maybe_unordered here always but this
16018 makes the resulting assembler clearer. */
16019 if (really_reversed
)
16021 /* Reversal of FP compares takes care -- an ordered compare
16022 becomes an unordered compare and vice versa. */
16023 if (mode
== CCFPmode
)
16024 code
= reverse_condition_maybe_unordered (code
);
16026 code
= reverse_condition (code
);
16029 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
16031 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
16036 /* Opposite of GT. */
16045 gcc_unreachable ();
16051 /* Not all of these are actually distinct opcodes, but
16052 we distinguish them for clarity of the resulting assembler. */
16053 case NE
: case LTGT
:
16054 ccode
= "ne"; break;
16055 case EQ
: case UNEQ
:
16056 ccode
= "eq"; break;
16058 ccode
= "ge"; break;
16059 case GT
: case GTU
: case UNGT
:
16060 ccode
= "gt"; break;
16062 ccode
= "le"; break;
16063 case LT
: case LTU
: case UNLT
:
16064 ccode
= "lt"; break;
16065 case UNORDERED
: ccode
= "un"; break;
16066 case ORDERED
: ccode
= "nu"; break;
16067 case UNGE
: ccode
= "nl"; break;
16068 case UNLE
: ccode
= "ng"; break;
16070 gcc_unreachable ();
16073 /* Maybe we have a guess as to how likely the branch is. */
16075 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
16076 if (note
!= NULL_RTX
)
16078 /* PROB is the difference from 50%. */
16079 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
16081 /* Only hint for highly probable/improbable branches on newer
16082 cpus as static prediction overrides processor dynamic
16083 prediction. For older cpus we may as well always hint, but
16084 assume not taken for branches that are very close to 50% as a
16085 mispredicted taken branch is more expensive than a
16086 mispredicted not-taken branch. */
16087 if (rs6000_always_hint
16088 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
16089 && br_prob_note_reliable_p (note
)))
16091 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
16092 && ((prob
> 0) ^ need_longbranch
))
16100 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
16102 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
16104 /* We need to escape any '%' characters in the reg_names string.
16105 Assume they'd only be the first character.... */
16106 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
16108 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
16112 /* If the branch distance was too far, we may have to use an
16113 unconditional branch to go the distance. */
16114 if (need_longbranch
)
16115 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
16117 s
+= sprintf (s
, ",%s", label
);
16123 /* Return the string to flip the GT bit on a CR. */
16125 output_e500_flip_gt_bit (rtx dst
, rtx src
)
16127 static char string
[64];
16130 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
16131 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
16134 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
16135 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
16137 sprintf (string
, "crnot %d,%d", a
, b
);
16141 /* Return insn for VSX or Altivec comparisons. */
16144 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
16147 enum machine_mode mode
= GET_MODE (op0
);
16155 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
16165 mask
= gen_reg_rtx (mode
);
16166 emit_insn (gen_rtx_SET (VOIDmode
,
16168 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
16175 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16176 DMODE is expected destination mode. This is a recursive function. */
16179 rs6000_emit_vector_compare (enum rtx_code rcode
,
16181 enum machine_mode dmode
)
16184 bool swap_operands
= false;
16185 bool try_again
= false;
16187 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
16188 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
16190 /* See if the comparison works as is. */
16191 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
16199 swap_operands
= true;
16204 swap_operands
= true;
16212 /* Invert condition and try again.
16213 e.g., A != B becomes ~(A==B). */
16215 enum rtx_code rev_code
;
16216 enum insn_code nor_code
;
16219 rev_code
= reverse_condition_maybe_unordered (rcode
);
16220 if (rev_code
== UNKNOWN
)
16223 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
16224 if (nor_code
== CODE_FOR_nothing
)
16227 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
16231 mask
= gen_reg_rtx (dmode
);
16232 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
16240 /* Try GT/GTU/LT/LTU OR EQ */
16243 enum insn_code ior_code
;
16244 enum rtx_code new_code
;
16265 gcc_unreachable ();
16268 ior_code
= optab_handler (ior_optab
, dmode
);
16269 if (ior_code
== CODE_FOR_nothing
)
16272 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
16276 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
16280 mask
= gen_reg_rtx (dmode
);
16281 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
16299 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
16304 /* You only get two chances. */
16308 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16309 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16310 operands for the relation operation COND. */
16313 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
16314 rtx cond
, rtx cc_op0
, rtx cc_op1
)
16316 enum machine_mode dest_mode
= GET_MODE (dest
);
16317 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
16318 enum rtx_code rcode
= GET_CODE (cond
);
16319 enum machine_mode cc_mode
= CCmode
;
16323 bool invert_move
= false;
16325 if (VECTOR_UNIT_NONE_P (dest_mode
))
16328 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
16329 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
16333 /* Swap operands if we can, and fall back to doing the operation as
16334 specified, and doing a NOR to invert the test. */
16340 /* Invert condition and try again.
16341 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16342 invert_move
= true;
16343 rcode
= reverse_condition_maybe_unordered (rcode
);
16344 if (rcode
== UNKNOWN
)
16348 /* Mark unsigned tests with CCUNSmode. */
16353 cc_mode
= CCUNSmode
;
16360 /* Get the vector mask for the given relational operations. */
16361 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
16369 op_true
= op_false
;
16373 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
16374 CONST0_RTX (dest_mode
));
16375 emit_insn (gen_rtx_SET (VOIDmode
,
16377 gen_rtx_IF_THEN_ELSE (dest_mode
,
16384 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16385 operands of the last comparison is nonzero/true, FALSE_COND if it
16386 is zero/false. Return 0 if the hardware has no such operation. */
16389 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
16391 enum rtx_code code
= GET_CODE (op
);
16392 rtx op0
= XEXP (op
, 0);
16393 rtx op1
= XEXP (op
, 1);
16394 REAL_VALUE_TYPE c1
;
16395 enum machine_mode compare_mode
= GET_MODE (op0
);
16396 enum machine_mode result_mode
= GET_MODE (dest
);
16398 bool is_against_zero
;
16400 /* These modes should always match. */
16401 if (GET_MODE (op1
) != compare_mode
16402 /* In the isel case however, we can use a compare immediate, so
16403 op1 may be a small constant. */
16404 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
16406 if (GET_MODE (true_cond
) != result_mode
)
16408 if (GET_MODE (false_cond
) != result_mode
)
16411 /* Don't allow using floating point comparisons for integer results for
16413 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
16416 /* First, work out if the hardware can do this at all, or
16417 if it's too slow.... */
16418 if (!FLOAT_MODE_P (compare_mode
))
16421 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
16424 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
16425 && SCALAR_FLOAT_MODE_P (compare_mode
))
16428 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
16430 /* A floating-point subtract might overflow, underflow, or produce
16431 an inexact result, thus changing the floating-point flags, so it
16432 can't be generated if we care about that. It's safe if one side
16433 of the construct is zero, since then no subtract will be
16435 if (SCALAR_FLOAT_MODE_P (compare_mode
)
16436 && flag_trapping_math
&& ! is_against_zero
)
16439 /* Eliminate half of the comparisons by switching operands, this
16440 makes the remaining code simpler. */
16441 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
16442 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
16444 code
= reverse_condition_maybe_unordered (code
);
16446 true_cond
= false_cond
;
16450 /* UNEQ and LTGT take four instructions for a comparison with zero,
16451 it'll probably be faster to use a branch here too. */
16452 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
16455 if (GET_CODE (op1
) == CONST_DOUBLE
)
16456 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
16458 /* We're going to try to implement comparisons by performing
16459 a subtract, then comparing against zero. Unfortunately,
16460 Inf - Inf is NaN which is not zero, and so if we don't
16461 know that the operand is finite and the comparison
16462 would treat EQ different to UNORDERED, we can't do it. */
16463 if (HONOR_INFINITIES (compare_mode
)
16464 && code
!= GT
&& code
!= UNGE
16465 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
16466 /* Constructs of the form (a OP b ? a : b) are safe. */
16467 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
16468 || (! rtx_equal_p (op0
, true_cond
)
16469 && ! rtx_equal_p (op1
, true_cond
))))
16472 /* At this point we know we can use fsel. */
16474 /* Reduce the comparison to a comparison against zero. */
16475 if (! is_against_zero
)
16477 temp
= gen_reg_rtx (compare_mode
);
16478 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16479 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
16481 op1
= CONST0_RTX (compare_mode
);
16484 /* If we don't care about NaNs we can reduce some of the comparisons
16485 down to faster ones. */
16486 if (! HONOR_NANS (compare_mode
))
16492 true_cond
= false_cond
;
16505 /* Now, reduce everything down to a GE. */
16512 temp
= gen_reg_rtx (compare_mode
);
16513 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16518 temp
= gen_reg_rtx (compare_mode
);
16519 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
16524 temp
= gen_reg_rtx (compare_mode
);
16525 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16526 gen_rtx_NEG (compare_mode
,
16527 gen_rtx_ABS (compare_mode
, op0
))));
16532 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16533 temp
= gen_reg_rtx (result_mode
);
16534 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16535 gen_rtx_IF_THEN_ELSE (result_mode
,
16536 gen_rtx_GE (VOIDmode
,
16538 true_cond
, false_cond
)));
16539 false_cond
= true_cond
;
16542 temp
= gen_reg_rtx (compare_mode
);
16543 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16548 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16549 temp
= gen_reg_rtx (result_mode
);
16550 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16551 gen_rtx_IF_THEN_ELSE (result_mode
,
16552 gen_rtx_GE (VOIDmode
,
16554 true_cond
, false_cond
)));
16555 true_cond
= false_cond
;
16558 temp
= gen_reg_rtx (compare_mode
);
16559 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16564 gcc_unreachable ();
16567 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16568 gen_rtx_IF_THEN_ELSE (result_mode
,
16569 gen_rtx_GE (VOIDmode
,
16571 true_cond
, false_cond
)));
16575 /* Same as above, but for ints (isel). */
16578 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
16580 rtx condition_rtx
, cr
;
16581 enum machine_mode mode
= GET_MODE (dest
);
16582 enum rtx_code cond_code
;
16583 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
16586 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
16589 /* We still have to do the compare, because isel doesn't do a
16590 compare, it just looks at the CRx bits set by a previous compare
16592 condition_rtx
= rs6000_generate_compare (op
, mode
);
16593 cond_code
= GET_CODE (condition_rtx
);
16594 cr
= XEXP (condition_rtx
, 0);
16595 signedp
= GET_MODE (cr
) == CCmode
;
16597 isel_func
= (mode
== SImode
16598 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
16599 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
16603 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
16604 /* isel handles these directly. */
16608 /* We need to swap the sense of the comparison. */
16611 true_cond
= false_cond
;
16613 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
16618 false_cond
= force_reg (mode
, false_cond
);
16619 if (true_cond
!= const0_rtx
)
16620 true_cond
= force_reg (mode
, true_cond
);
16622 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
16628 output_isel (rtx
*operands
)
16630 enum rtx_code code
;
16632 code
= GET_CODE (operands
[1]);
16634 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
16636 gcc_assert (GET_CODE (operands
[2]) == REG
16637 && GET_CODE (operands
[3]) == REG
);
16638 PUT_CODE (operands
[1], reverse_condition (code
));
16639 return "isel %0,%3,%2,%j1";
16642 return "isel %0,%2,%3,%j1";
16646 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
16648 enum machine_mode mode
= GET_MODE (op0
);
16652 /* VSX/altivec have direct min/max insns. */
16653 if ((code
== SMAX
|| code
== SMIN
)
16654 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16655 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
16657 emit_insn (gen_rtx_SET (VOIDmode
,
16659 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
16663 if (code
== SMAX
|| code
== SMIN
)
16668 if (code
== SMAX
|| code
== UMAX
)
16669 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
16670 op0
, op1
, mode
, 0);
16672 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
16673 op1
, op0
, mode
, 0);
16674 gcc_assert (target
);
16675 if (target
!= dest
)
16676 emit_move_insn (dest
, target
);
16679 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16680 COND is true. Mark the jump as unlikely to be taken. */
16683 emit_unlikely_jump (rtx cond
, rtx label
)
16685 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
16688 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
16689 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
16690 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
16693 /* A subroutine of the atomic operation splitters. Emit a load-locked
16694 instruction in MODE. */
16697 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
16699 rtx (*fn
) (rtx
, rtx
) = NULL
;
16704 fn
= gen_load_lockedsi
;
16707 fn
= gen_load_lockeddi
;
16710 gcc_unreachable ();
16712 emit_insn (fn (reg
, mem
));
16715 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16716 instruction in MODE. */
16719 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
16721 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
16726 fn
= gen_store_conditionalsi
;
16729 fn
= gen_store_conditionaldi
;
16732 gcc_unreachable ();
16735 /* Emit sync before stwcx. to address PPC405 Erratum. */
16736 if (PPC405_ERRATUM77
)
16737 emit_insn (gen_hwsync ());
16739 emit_insn (fn (res
, mem
, val
));
16742 /* Expand barriers before and after a load_locked/store_cond sequence. */
16745 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
16747 rtx addr
= XEXP (mem
, 0);
16748 int strict_p
= (reload_in_progress
|| reload_completed
);
16750 if (!legitimate_indirect_address_p (addr
, strict_p
)
16751 && !legitimate_indexed_address_p (addr
, strict_p
))
16753 addr
= force_reg (Pmode
, addr
);
16754 mem
= replace_equiv_address_nv (mem
, addr
);
16759 case MEMMODEL_RELAXED
:
16760 case MEMMODEL_CONSUME
:
16761 case MEMMODEL_ACQUIRE
:
16763 case MEMMODEL_RELEASE
:
16764 case MEMMODEL_ACQ_REL
:
16765 emit_insn (gen_lwsync ());
16767 case MEMMODEL_SEQ_CST
:
16768 emit_insn (gen_hwsync ());
16771 gcc_unreachable ();
16777 rs6000_post_atomic_barrier (enum memmodel model
)
16781 case MEMMODEL_RELAXED
:
16782 case MEMMODEL_CONSUME
:
16783 case MEMMODEL_RELEASE
:
16785 case MEMMODEL_ACQUIRE
:
16786 case MEMMODEL_ACQ_REL
:
16787 case MEMMODEL_SEQ_CST
:
16788 emit_insn (gen_isync ());
16791 gcc_unreachable ();
16795 /* A subroutine of the various atomic expanders. For sub-word operations,
16796 we must adjust things to operate on SImode. Given the original MEM,
16797 return a new aligned memory. Also build and return the quantities by
16798 which to shift and mask. */
16801 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
16803 rtx addr
, align
, shift
, mask
, mem
;
16804 HOST_WIDE_INT shift_mask
;
16805 enum machine_mode mode
= GET_MODE (orig_mem
);
16807 /* For smaller modes, we have to implement this via SImode. */
16808 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
16810 addr
= XEXP (orig_mem
, 0);
16811 addr
= force_reg (GET_MODE (addr
), addr
);
16813 /* Aligned memory containing subword. Generate a new memory. We
16814 do not want any of the existing MEM_ATTR data, as we're now
16815 accessing memory outside the original object. */
16816 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
16817 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16818 mem
= gen_rtx_MEM (SImode
, align
);
16819 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
16820 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
16821 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
16823 /* Shift amount for subword relative to aligned word. */
16824 shift
= gen_reg_rtx (SImode
);
16825 addr
= gen_lowpart (SImode
, addr
);
16826 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
16827 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
16828 shift
, 1, OPTAB_LIB_WIDEN
);
16831 /* Mask for insertion. */
16832 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
16833 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16839 /* A subroutine of the various atomic expanders. For sub-word operands,
16840 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16843 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
16847 x
= gen_reg_rtx (SImode
);
16848 emit_insn (gen_rtx_SET (VOIDmode
, x
,
16849 gen_rtx_AND (SImode
,
16850 gen_rtx_NOT (SImode
, mask
),
16853 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
16858 /* A subroutine of the various atomic expanders. For sub-word operands,
16859 extract WIDE to NARROW via SHIFT. */
16862 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
16864 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
16865 wide
, 1, OPTAB_LIB_WIDEN
);
16866 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
16869 /* Expand an atomic compare and swap operation. */
16872 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
16874 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
16875 rtx label1
, label2
, x
, mask
, shift
;
16876 enum machine_mode mode
;
16877 enum memmodel mod_s
, mod_f
;
16880 boolval
= operands
[0];
16881 retval
= operands
[1];
16883 oldval
= operands
[3];
16884 newval
= operands
[4];
16885 is_weak
= (INTVAL (operands
[5]) != 0);
16886 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
16887 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
16888 mode
= GET_MODE (mem
);
16890 mask
= shift
= NULL_RTX
;
16891 if (mode
== QImode
|| mode
== HImode
)
16893 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
16895 /* Shift and mask OLDVAL into position with the word. */
16896 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
16897 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
16898 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16900 /* Shift and mask NEWVAL into position within the word. */
16901 newval
= convert_modes (SImode
, mode
, newval
, 1);
16902 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
16903 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16905 /* Prepare to adjust the return value. */
16906 retval
= gen_reg_rtx (SImode
);
16909 else if (reg_overlap_mentioned_p (retval
, oldval
))
16910 oldval
= copy_to_reg (oldval
);
16912 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
16917 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16918 emit_label (XEXP (label1
, 0));
16920 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16922 emit_load_locked (mode
, retval
, mem
);
16927 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
16928 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16931 cond
= gen_reg_rtx (CCmode
);
16932 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
16933 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
16935 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16936 emit_unlikely_jump (x
, label2
);
16940 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
16942 emit_store_conditional (mode
, cond
, mem
, x
);
16946 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16947 emit_unlikely_jump (x
, label1
);
16950 if (mod_f
!= MEMMODEL_RELAXED
)
16951 emit_label (XEXP (label2
, 0));
16953 rs6000_post_atomic_barrier (mod_s
);
16955 if (mod_f
== MEMMODEL_RELAXED
)
16956 emit_label (XEXP (label2
, 0));
16959 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
16961 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16962 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
16963 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
16966 /* Expand an atomic exchange operation. */
16969 rs6000_expand_atomic_exchange (rtx operands
[])
16971 rtx retval
, mem
, val
, cond
;
16972 enum machine_mode mode
;
16973 enum memmodel model
;
16974 rtx label
, x
, mask
, shift
;
16976 retval
= operands
[0];
16979 model
= (enum memmodel
) INTVAL (operands
[3]);
16980 mode
= GET_MODE (mem
);
16982 mask
= shift
= NULL_RTX
;
16983 if (mode
== QImode
|| mode
== HImode
)
16985 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
16987 /* Shift and mask VAL into position with the word. */
16988 val
= convert_modes (SImode
, mode
, val
, 1);
16989 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
16990 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16992 /* Prepare to adjust the return value. */
16993 retval
= gen_reg_rtx (SImode
);
16997 mem
= rs6000_pre_atomic_barrier (mem
, model
);
16999 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
17000 emit_label (XEXP (label
, 0));
17002 emit_load_locked (mode
, retval
, mem
);
17006 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
17008 cond
= gen_reg_rtx (CCmode
);
17009 emit_store_conditional (mode
, cond
, mem
, x
);
17011 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
17012 emit_unlikely_jump (x
, label
);
17014 rs6000_post_atomic_barrier (model
);
17017 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
17020 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
17021 to perform. MEM is the memory on which to operate. VAL is the second
17022 operand of the binary operator. BEFORE and AFTER are optional locations to
17023 return the value of MEM either before of after the operation. MODEL_RTX
17024 is a CONST_INT containing the memory model to use. */
17027 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
17028 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
17030 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
17031 enum machine_mode mode
= GET_MODE (mem
);
17032 rtx label
, x
, cond
, mask
, shift
;
17033 rtx before
= orig_before
, after
= orig_after
;
17035 mask
= shift
= NULL_RTX
;
17036 if (mode
== QImode
|| mode
== HImode
)
17038 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
17040 /* Shift and mask VAL into position with the word. */
17041 val
= convert_modes (SImode
, mode
, val
, 1);
17042 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
17043 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17049 /* We've already zero-extended VAL. That is sufficient to
17050 make certain that it does not affect other bits. */
17055 /* If we make certain that all of the other bits in VAL are
17056 set, that will be sufficient to not affect other bits. */
17057 x
= gen_rtx_NOT (SImode
, mask
);
17058 x
= gen_rtx_IOR (SImode
, x
, val
);
17059 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
17066 /* These will all affect bits outside the field and need
17067 adjustment via MASK within the loop. */
17071 gcc_unreachable ();
17074 /* Prepare to adjust the return value. */
17075 before
= gen_reg_rtx (SImode
);
17077 after
= gen_reg_rtx (SImode
);
17081 mem
= rs6000_pre_atomic_barrier (mem
, model
);
17083 label
= gen_label_rtx ();
17084 emit_label (label
);
17085 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
17087 if (before
== NULL_RTX
)
17088 before
= gen_reg_rtx (mode
);
17090 emit_load_locked (mode
, before
, mem
);
17094 x
= expand_simple_binop (mode
, AND
, before
, val
,
17095 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17096 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
17100 after
= expand_simple_binop (mode
, code
, before
, val
,
17101 after
, 1, OPTAB_LIB_WIDEN
);
17107 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
17108 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17109 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
17112 cond
= gen_reg_rtx (CCmode
);
17113 emit_store_conditional (mode
, cond
, mem
, x
);
17115 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
17116 emit_unlikely_jump (x
, label
);
17118 rs6000_post_atomic_barrier (model
);
17123 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
17125 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
17127 else if (orig_after
&& after
!= orig_after
)
17128 emit_move_insn (orig_after
, after
);
17131 /* Emit instructions to move SRC to DST. Called by splitters for
17132 multi-register moves. It will emit at most one instruction for
17133 each register that is accessed; that is, it won't emit li/lis pairs
17134 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17138 rs6000_split_multireg_move (rtx dst
, rtx src
)
17140 /* The register number of the first register being moved. */
17142 /* The mode that is to be moved. */
17143 enum machine_mode mode
;
17144 /* The mode that the move is being done in, and its size. */
17145 enum machine_mode reg_mode
;
17147 /* The number of registers that will be moved. */
17150 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
17151 mode
= GET_MODE (dst
);
17152 nregs
= hard_regno_nregs
[reg
][mode
];
17153 if (FP_REGNO_P (reg
))
17154 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
17155 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
17156 else if (ALTIVEC_REGNO_P (reg
))
17157 reg_mode
= V16QImode
;
17158 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
17161 reg_mode
= word_mode
;
17162 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
17164 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
17166 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
17168 /* Move register range backwards, if we might have destructive
17171 for (i
= nregs
- 1; i
>= 0; i
--)
17172 emit_insn (gen_rtx_SET (VOIDmode
,
17173 simplify_gen_subreg (reg_mode
, dst
, mode
,
17174 i
* reg_mode_size
),
17175 simplify_gen_subreg (reg_mode
, src
, mode
,
17176 i
* reg_mode_size
)));
17182 bool used_update
= false;
17183 rtx restore_basereg
= NULL_RTX
;
17185 if (MEM_P (src
) && INT_REGNO_P (reg
))
17189 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
17190 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
17193 breg
= XEXP (XEXP (src
, 0), 0);
17194 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
17195 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
17196 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
17197 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
17198 src
= replace_equiv_address (src
, breg
);
17200 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
17202 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
17204 rtx basereg
= XEXP (XEXP (src
, 0), 0);
17207 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
17208 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
17209 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
17210 used_update
= true;
17213 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
17214 XEXP (XEXP (src
, 0), 1)));
17215 src
= replace_equiv_address (src
, basereg
);
17219 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
17220 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
17221 src
= replace_equiv_address (src
, basereg
);
17225 breg
= XEXP (src
, 0);
17226 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
17227 breg
= XEXP (breg
, 0);
17229 /* If the base register we are using to address memory is
17230 also a destination reg, then change that register last. */
17232 && REGNO (breg
) >= REGNO (dst
)
17233 && REGNO (breg
) < REGNO (dst
) + nregs
)
17234 j
= REGNO (breg
) - REGNO (dst
);
17236 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
17240 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
17241 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
17244 breg
= XEXP (XEXP (dst
, 0), 0);
17245 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
17246 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
17247 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
17249 /* We have to update the breg before doing the store.
17250 Use store with update, if available. */
17254 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
17255 emit_insn (TARGET_32BIT
17256 ? (TARGET_POWERPC64
17257 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
17258 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
17259 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
17260 used_update
= true;
17263 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
17264 dst
= replace_equiv_address (dst
, breg
);
17266 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
17267 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
17269 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
17271 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
17274 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
17275 emit_insn (gen_rtx_SET (VOIDmode
,
17276 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
17277 used_update
= true;
17280 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
17281 XEXP (XEXP (dst
, 0), 1)));
17282 dst
= replace_equiv_address (dst
, basereg
);
17286 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
17287 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
17288 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
17290 && REG_P (offsetreg
)
17291 && REGNO (basereg
) != REGNO (offsetreg
));
17292 if (REGNO (basereg
) == 0)
17294 rtx tmp
= offsetreg
;
17295 offsetreg
= basereg
;
17298 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
17299 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
17300 dst
= replace_equiv_address (dst
, basereg
);
17303 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
17304 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
17307 for (i
= 0; i
< nregs
; i
++)
17309 /* Calculate index to next subword. */
17314 /* If compiler already emitted move of first word by
17315 store with update, no need to do anything. */
17316 if (j
== 0 && used_update
)
17319 emit_insn (gen_rtx_SET (VOIDmode
,
17320 simplify_gen_subreg (reg_mode
, dst
, mode
,
17321 j
* reg_mode_size
),
17322 simplify_gen_subreg (reg_mode
, src
, mode
,
17323 j
* reg_mode_size
)));
17325 if (restore_basereg
!= NULL_RTX
)
17326 emit_insn (restore_basereg
);
17331 /* This page contains routines that are used to determine what the
17332 function prologue and epilogue code will do and write them out. */
17337 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
17340 /* Return the first fixed-point register that is required to be
17341 saved. 32 if none. */
17344 first_reg_to_save (void)
17348 /* Find lowest numbered live register. */
17349 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
17350 if (save_reg_p (first_reg
))
17353 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
17354 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
17355 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
17356 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
17357 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
17358 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
17362 && crtl
->uses_pic_offset_table
17363 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
17364 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
17370 /* Similar, for FP regs. */
17373 first_fp_reg_to_save (void)
17377 /* Find lowest numbered live register. */
17378 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
17379 if (save_reg_p (first_reg
))
17385 /* Similar, for AltiVec regs. */
17388 first_altivec_reg_to_save (void)
17392 /* Stack frame remains as is unless we are in AltiVec ABI. */
17393 if (! TARGET_ALTIVEC_ABI
)
17394 return LAST_ALTIVEC_REGNO
+ 1;
17396 /* On Darwin, the unwind routines are compiled without
17397 TARGET_ALTIVEC, and use save_world to save/restore the
17398 altivec registers when necessary. */
17399 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
17400 && ! TARGET_ALTIVEC
)
17401 return FIRST_ALTIVEC_REGNO
+ 20;
17403 /* Find lowest numbered live register. */
17404 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17405 if (save_reg_p (i
))
17411 /* Return a 32-bit mask of the AltiVec registers we need to set in
17412 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17413 the 32-bit word is 0. */
17415 static unsigned int
17416 compute_vrsave_mask (void)
17418 unsigned int i
, mask
= 0;
17420 /* On Darwin, the unwind routines are compiled without
17421 TARGET_ALTIVEC, and use save_world to save/restore the
17422 call-saved altivec registers when necessary. */
17423 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
17424 && ! TARGET_ALTIVEC
)
17427 /* First, find out if we use _any_ altivec registers. */
17428 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17429 if (df_regs_ever_live_p (i
))
17430 mask
|= ALTIVEC_REG_BIT (i
);
17435 /* Next, remove the argument registers from the set. These must
17436 be in the VRSAVE mask set by the caller, so we don't need to add
17437 them in again. More importantly, the mask we compute here is
17438 used to generate CLOBBERs in the set_vrsave insn, and we do not
17439 wish the argument registers to die. */
17440 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
17441 mask
&= ~ALTIVEC_REG_BIT (i
);
17443 /* Similarly, remove the return value from the set. */
17446 diddle_return_value (is_altivec_return_reg
, &yes
);
17448 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
17454 /* For a very restricted set of circumstances, we can cut down the
17455 size of prologues/epilogues by calling our own save/restore-the-world
17459 compute_save_world_info (rs6000_stack_t
*info_ptr
)
17461 info_ptr
->world_save_p
= 1;
17462 info_ptr
->world_save_p
17463 = (WORLD_SAVE_P (info_ptr
)
17464 && DEFAULT_ABI
== ABI_DARWIN
17465 && !cfun
->has_nonlocal_label
17466 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
17467 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
17468 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
17469 && info_ptr
->cr_save_p
);
17471 /* This will not work in conjunction with sibcalls. Make sure there
17472 are none. (This check is expensive, but seldom executed.) */
17473 if (WORLD_SAVE_P (info_ptr
))
17476 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
17477 if ( GET_CODE (insn
) == CALL_INSN
17478 && SIBLING_CALL_P (insn
))
17480 info_ptr
->world_save_p
= 0;
17485 if (WORLD_SAVE_P (info_ptr
))
17487 /* Even if we're not touching VRsave, make sure there's room on the
17488 stack for it, if it looks like we're calling SAVE_WORLD, which
17489 will attempt to save it. */
17490 info_ptr
->vrsave_size
= 4;
17492 /* If we are going to save the world, we need to save the link register too. */
17493 info_ptr
->lr_save_p
= 1;
17495 /* "Save" the VRsave register too if we're saving the world. */
17496 if (info_ptr
->vrsave_mask
== 0)
17497 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
17499 /* Because the Darwin register save/restore routines only handle
17500 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17502 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
17503 && (info_ptr
->first_altivec_reg_save
17504 >= FIRST_SAVED_ALTIVEC_REGNO
));
17511 is_altivec_return_reg (rtx reg
, void *xyes
)
17513 bool *yes
= (bool *) xyes
;
17514 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
17519 /* Look for user-defined global regs in the range FIRST to LAST-1.
17520 We should not restore these, and so cannot use lmw or out-of-line
17521 restore functions if there are any. We also can't save them
17522 (well, emit frame notes for them), because frame unwinding during
17523 exception handling will restore saved registers. */
17526 global_regs_p (unsigned first
, unsigned last
)
17528 while (first
< last
)
17529 if (global_regs
[first
++])
17534 /* Determine the strategy for savings/restoring registers. */
17537 SAVRES_MULTIPLE
= 0x1,
17538 SAVE_INLINE_FPRS
= 0x2,
17539 SAVE_INLINE_GPRS
= 0x4,
17540 REST_INLINE_FPRS
= 0x8,
17541 REST_INLINE_GPRS
= 0x10,
17542 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
17543 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
17544 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
17545 SAVE_INLINE_VRS
= 0x100,
17546 REST_INLINE_VRS
= 0x200
17550 rs6000_savres_strategy (rs6000_stack_t
*info
,
17551 bool using_static_chain_p
)
17556 if (TARGET_MULTIPLE
17557 && !TARGET_POWERPC64
17558 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
17559 && info
->first_gp_reg_save
< 31
17560 && !global_regs_p (info
->first_gp_reg_save
, 32))
17561 strategy
|= SAVRES_MULTIPLE
;
17563 if (crtl
->calls_eh_return
17564 || cfun
->machine
->ra_need_lr
)
17565 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
17566 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
17567 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
17569 if (info
->first_fp_reg_save
== 64
17570 /* The out-of-line FP routines use double-precision stores;
17571 we can't use those routines if we don't have such stores. */
17572 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
17573 || global_regs_p (info
->first_fp_reg_save
, 64))
17574 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17576 if (info
->first_gp_reg_save
== 32
17577 || (!(strategy
& SAVRES_MULTIPLE
)
17578 && global_regs_p (info
->first_gp_reg_save
, 32)))
17579 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17581 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
17582 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
17583 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17585 /* Define cutoff for using out-of-line functions to save registers. */
17586 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
17588 if (!optimize_size
)
17590 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17591 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17592 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17596 /* Prefer out-of-line restore if it will exit. */
17597 if (info
->first_fp_reg_save
> 61)
17598 strategy
|= SAVE_INLINE_FPRS
;
17599 if (info
->first_gp_reg_save
> 29)
17601 if (info
->first_fp_reg_save
== 64)
17602 strategy
|= SAVE_INLINE_GPRS
;
17604 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17606 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
17607 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17610 else if (DEFAULT_ABI
== ABI_DARWIN
)
17612 if (info
->first_fp_reg_save
> 60)
17613 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17614 if (info
->first_gp_reg_save
> 29)
17615 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17616 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17620 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
);
17621 if (info
->first_fp_reg_save
> 61)
17622 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17623 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17624 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17627 /* Don't bother to try to save things out-of-line if r11 is occupied
17628 by the static chain. It would require too much fiddling and the
17629 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17630 pointer on Darwin, and AIX uses r1 or r12. */
17631 if (using_static_chain_p
&& DEFAULT_ABI
!= ABI_AIX
)
17632 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
17634 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
17636 /* We can only use the out-of-line routines to restore if we've
17637 saved all the registers from first_fp_reg_save in the prologue.
17638 Otherwise, we risk loading garbage. */
17639 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
17643 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
17644 if (!save_reg_p (i
))
17646 strategy
|= REST_INLINE_FPRS
;
17651 /* If we are going to use store multiple, then don't even bother
17652 with the out-of-line routines, since the store-multiple
17653 instruction will always be smaller. */
17654 if ((strategy
& SAVRES_MULTIPLE
))
17655 strategy
|= SAVE_INLINE_GPRS
;
17657 /* info->lr_save_p isn't yet set if the only reason lr needs to be
17658 saved is an out-of-line save or restore. Set up the value for
17659 the next test (excluding out-of-line gpr restore). */
17660 lr_save_p
= (info
->lr_save_p
17661 || !(strategy
& SAVE_INLINE_GPRS
)
17662 || !(strategy
& SAVE_INLINE_FPRS
)
17663 || !(strategy
& SAVE_INLINE_VRS
)
17664 || !(strategy
& REST_INLINE_FPRS
)
17665 || !(strategy
& REST_INLINE_VRS
));
17667 /* The situation is more complicated with load multiple. We'd
17668 prefer to use the out-of-line routines for restores, since the
17669 "exit" out-of-line routines can handle the restore of LR and the
17670 frame teardown. However if doesn't make sense to use the
17671 out-of-line routine if that is the only reason we'd need to save
17672 LR, and we can't use the "exit" out-of-line gpr restore if we
17673 have saved some fprs; In those cases it is advantageous to use
17674 load multiple when available. */
17675 if ((strategy
& SAVRES_MULTIPLE
)
17677 || info
->first_fp_reg_save
!= 64))
17678 strategy
|= REST_INLINE_GPRS
;
17680 /* Saving CR interferes with the exit routines used on the SPE, so
17683 && info
->spe_64bit_regs_used
17684 && info
->cr_save_p
)
17685 strategy
|= REST_INLINE_GPRS
;
17687 /* We can only use load multiple or the out-of-line routines to
17688 restore if we've used store multiple or out-of-line routines
17689 in the prologue, i.e. if we've saved all the registers from
17690 first_gp_reg_save. Otherwise, we risk loading garbage. */
17691 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
17692 == SAVE_INLINE_GPRS
)
17696 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
17697 if (!save_reg_p (i
))
17699 strategy
|= REST_INLINE_GPRS
;
17704 if (TARGET_ELF
&& TARGET_64BIT
)
17706 if (!(strategy
& SAVE_INLINE_FPRS
))
17707 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
17708 else if (!(strategy
& SAVE_INLINE_GPRS
)
17709 && info
->first_fp_reg_save
== 64)
17710 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
17712 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
17713 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
17715 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
17716 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
17721 /* Calculate the stack information for the current function. This is
17722 complicated by having two separate calling sequences, the AIX calling
17723 sequence and the V.4 calling sequence.
17725 AIX (and Darwin/Mac OS X) stack frames look like:
17727 SP----> +---------------------------------------+
17728 | back chain to caller | 0 0
17729 +---------------------------------------+
17730 | saved CR | 4 8 (8-11)
17731 +---------------------------------------+
17733 +---------------------------------------+
17734 | reserved for compilers | 12 24
17735 +---------------------------------------+
17736 | reserved for binders | 16 32
17737 +---------------------------------------+
17738 | saved TOC pointer | 20 40
17739 +---------------------------------------+
17740 | Parameter save area (P) | 24 48
17741 +---------------------------------------+
17742 | Alloca space (A) | 24+P etc.
17743 +---------------------------------------+
17744 | Local variable space (L) | 24+P+A
17745 +---------------------------------------+
17746 | Float/int conversion temporary (X) | 24+P+A+L
17747 +---------------------------------------+
17748 | Save area for AltiVec registers (W) | 24+P+A+L+X
17749 +---------------------------------------+
17750 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17751 +---------------------------------------+
17752 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17753 +---------------------------------------+
17754 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17755 +---------------------------------------+
17756 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17757 +---------------------------------------+
17758 old SP->| back chain to caller's caller |
17759 +---------------------------------------+
17761 The required alignment for AIX configurations is two words (i.e., 8
17765 V.4 stack frames look like:
17767 SP----> +---------------------------------------+
17768 | back chain to caller | 0
17769 +---------------------------------------+
17770 | caller's saved LR | 4
17771 +---------------------------------------+
17772 | Parameter save area (P) | 8
17773 +---------------------------------------+
17774 | Alloca space (A) | 8+P
17775 +---------------------------------------+
17776 | Varargs save area (V) | 8+P+A
17777 +---------------------------------------+
17778 | Local variable space (L) | 8+P+A+V
17779 +---------------------------------------+
17780 | Float/int conversion temporary (X) | 8+P+A+V+L
17781 +---------------------------------------+
17782 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17783 +---------------------------------------+
17784 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17785 +---------------------------------------+
17786 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17787 +---------------------------------------+
17788 | SPE: area for 64-bit GP registers |
17789 +---------------------------------------+
17790 | SPE alignment padding |
17791 +---------------------------------------+
17792 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17793 +---------------------------------------+
17794 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17795 +---------------------------------------+
17796 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17797 +---------------------------------------+
17798 old SP->| back chain to caller's caller |
17799 +---------------------------------------+
17801 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17802 given. (But note below and in sysv4.h that we require only 8 and
17803 may round up the size of our stack frame anyways. The historical
17804 reason is early versions of powerpc-linux which didn't properly
17805 align the stack at program startup. A happy side-effect is that
17806 -mno-eabi libraries can be used with -meabi programs.)
17808 The EABI configuration defaults to the V.4 layout. However,
17809 the stack alignment requirements may differ. If -mno-eabi is not
17810 given, the required stack alignment is 8 bytes; if -mno-eabi is
17811 given, the required alignment is 16 bytes. (But see V.4 comment
17814 #ifndef ABI_STACK_BOUNDARY
17815 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17818 static rs6000_stack_t
*
17819 rs6000_stack_info (void)
17821 rs6000_stack_t
*info_ptr
= &stack_info
;
17822 int reg_size
= TARGET_32BIT
? 4 : 8;
17826 HOST_WIDE_INT non_fixed_size
;
17827 bool using_static_chain_p
;
17829 if (reload_completed
&& info_ptr
->reload_completed
)
17832 memset (info_ptr
, 0, sizeof (*info_ptr
));
17833 info_ptr
->reload_completed
= reload_completed
;
17837 /* Cache value so we don't rescan instruction chain over and over. */
17838 if (cfun
->machine
->insn_chain_scanned_p
== 0)
17839 cfun
->machine
->insn_chain_scanned_p
17840 = spe_func_has_64bit_regs_p () + 1;
17841 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
17844 /* Select which calling sequence. */
17845 info_ptr
->abi
= DEFAULT_ABI
;
17847 /* Calculate which registers need to be saved & save area size. */
17848 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
17849 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17850 even if it currently looks like we won't. Reload may need it to
17851 get at a constant; if so, it will have already created a constant
17852 pool entry for it. */
17853 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
17854 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
17855 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
17856 && crtl
->uses_const_pool
17857 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
17858 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
17860 first_gp
= info_ptr
->first_gp_reg_save
;
17862 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
17864 /* For the SPE, we have an additional upper 32-bits on each GPR.
17865 Ideally we should save the entire 64-bits only when the upper
17866 half is used in SIMD instructions. Since we only record
17867 registers live (not the size they are used in), this proves
17868 difficult because we'd have to traverse the instruction chain at
17869 the right time, taking reload into account. This is a real pain,
17870 so we opt to save the GPRs in 64-bits always if but one register
17871 gets used in 64-bits. Otherwise, all the registers in the frame
17872 get saved in 32-bits.
17874 So... since when we save all GPRs (except the SP) in 64-bits, the
17875 traditional GP save area will be empty. */
17876 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17877 info_ptr
->gp_size
= 0;
17879 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
17880 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
17882 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
17883 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
17884 - info_ptr
->first_altivec_reg_save
);
17886 /* Does this function call anything? */
17887 info_ptr
->calls_p
= (! crtl
->is_leaf
17888 || cfun
->machine
->ra_needs_full_frame
);
17890 /* Determine if we need to save the condition code registers. */
17891 if (df_regs_ever_live_p (CR2_REGNO
)
17892 || df_regs_ever_live_p (CR3_REGNO
)
17893 || df_regs_ever_live_p (CR4_REGNO
))
17895 info_ptr
->cr_save_p
= 1;
17896 if (DEFAULT_ABI
== ABI_V4
)
17897 info_ptr
->cr_size
= reg_size
;
17900 /* If the current function calls __builtin_eh_return, then we need
17901 to allocate stack space for registers that will hold data for
17902 the exception handler. */
17903 if (crtl
->calls_eh_return
)
17906 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
17909 /* SPE saves EH registers in 64-bits. */
17910 ehrd_size
= i
* (TARGET_SPE_ABI
17911 && info_ptr
->spe_64bit_regs_used
!= 0
17912 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
17917 /* Determine various sizes. */
17918 info_ptr
->reg_size
= reg_size
;
17919 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
17920 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
17921 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
17922 TARGET_ALTIVEC
? 16 : 8);
17923 if (FRAME_GROWS_DOWNWARD
)
17924 info_ptr
->vars_size
17925 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
17926 + info_ptr
->parm_size
,
17927 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
17928 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
17929 + info_ptr
->parm_size
);
17931 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17932 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
17934 info_ptr
->spe_gp_size
= 0;
17936 if (TARGET_ALTIVEC_ABI
)
17937 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
17939 info_ptr
->vrsave_mask
= 0;
17941 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
17942 info_ptr
->vrsave_size
= 4;
17944 info_ptr
->vrsave_size
= 0;
17946 compute_save_world_info (info_ptr
);
17948 /* Calculate the offsets. */
17949 switch (DEFAULT_ABI
)
17953 gcc_unreachable ();
17957 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
17958 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
17960 if (TARGET_ALTIVEC_ABI
)
17962 info_ptr
->vrsave_save_offset
17963 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
17965 /* Align stack so vector save area is on a quadword boundary.
17966 The padding goes above the vectors. */
17967 if (info_ptr
->altivec_size
!= 0)
17968 info_ptr
->altivec_padding_size
17969 = info_ptr
->vrsave_save_offset
& 0xF;
17971 info_ptr
->altivec_padding_size
= 0;
17973 info_ptr
->altivec_save_offset
17974 = info_ptr
->vrsave_save_offset
17975 - info_ptr
->altivec_padding_size
17976 - info_ptr
->altivec_size
;
17977 gcc_assert (info_ptr
->altivec_size
== 0
17978 || info_ptr
->altivec_save_offset
% 16 == 0);
17980 /* Adjust for AltiVec case. */
17981 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
17984 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
17985 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
17986 info_ptr
->lr_save_offset
= 2*reg_size
;
17990 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
17991 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
17992 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
17994 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17996 /* Align stack so SPE GPR save area is aligned on a
17997 double-word boundary. */
17998 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
17999 info_ptr
->spe_padding_size
18000 = 8 - (-info_ptr
->cr_save_offset
% 8);
18002 info_ptr
->spe_padding_size
= 0;
18004 info_ptr
->spe_gp_save_offset
18005 = info_ptr
->cr_save_offset
18006 - info_ptr
->spe_padding_size
18007 - info_ptr
->spe_gp_size
;
18009 /* Adjust for SPE case. */
18010 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
18012 else if (TARGET_ALTIVEC_ABI
)
18014 info_ptr
->vrsave_save_offset
18015 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
18017 /* Align stack so vector save area is on a quadword boundary. */
18018 if (info_ptr
->altivec_size
!= 0)
18019 info_ptr
->altivec_padding_size
18020 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
18022 info_ptr
->altivec_padding_size
= 0;
18024 info_ptr
->altivec_save_offset
18025 = info_ptr
->vrsave_save_offset
18026 - info_ptr
->altivec_padding_size
18027 - info_ptr
->altivec_size
;
18029 /* Adjust for AltiVec case. */
18030 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
18033 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
18034 info_ptr
->ehrd_offset
-= ehrd_size
;
18035 info_ptr
->lr_save_offset
= reg_size
;
18039 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
18040 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
18041 + info_ptr
->gp_size
18042 + info_ptr
->altivec_size
18043 + info_ptr
->altivec_padding_size
18044 + info_ptr
->spe_gp_size
18045 + info_ptr
->spe_padding_size
18047 + info_ptr
->cr_size
18048 + info_ptr
->vrsave_size
,
18051 non_fixed_size
= (info_ptr
->vars_size
18052 + info_ptr
->parm_size
18053 + info_ptr
->save_size
);
18055 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
18056 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
18058 /* Determine if we need to save the link register. */
18059 if (info_ptr
->calls_p
18060 || (DEFAULT_ABI
== ABI_AIX
18062 && !TARGET_PROFILE_KERNEL
)
18063 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
18064 #ifdef TARGET_RELOCATABLE
18065 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
18067 || rs6000_ra_ever_killed ())
18068 info_ptr
->lr_save_p
= 1;
18070 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
18071 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
18072 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
18073 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
18074 using_static_chain_p
);
18076 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
18077 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
18078 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
18079 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
18080 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
18081 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
18082 info_ptr
->lr_save_p
= 1;
18084 if (info_ptr
->lr_save_p
)
18085 df_set_regs_ever_live (LR_REGNO
, true);
18087 /* Determine if we need to allocate any stack frame:
18089 For AIX we need to push the stack if a frame pointer is needed
18090 (because the stack might be dynamically adjusted), if we are
18091 debugging, if we make calls, or if the sum of fp_save, gp_save,
18092 and local variables are more than the space needed to save all
18093 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
18094 + 18*8 = 288 (GPR13 reserved).
18096 For V.4 we don't have the stack cushion that AIX uses, but assume
18097 that the debugger can handle stackless frames. */
18099 if (info_ptr
->calls_p
)
18100 info_ptr
->push_p
= 1;
18102 else if (DEFAULT_ABI
== ABI_V4
)
18103 info_ptr
->push_p
= non_fixed_size
!= 0;
18105 else if (frame_pointer_needed
)
18106 info_ptr
->push_p
= 1;
18108 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
18109 info_ptr
->push_p
= 1;
18112 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
18114 /* Zero offsets if we're not saving those registers. */
18115 if (info_ptr
->fp_size
== 0)
18116 info_ptr
->fp_save_offset
= 0;
18118 if (info_ptr
->gp_size
== 0)
18119 info_ptr
->gp_save_offset
= 0;
18121 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
18122 info_ptr
->altivec_save_offset
= 0;
18124 /* Zero VRSAVE offset if not saved and restored. */
18125 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
18126 info_ptr
->vrsave_save_offset
= 0;
18128 if (! TARGET_SPE_ABI
18129 || info_ptr
->spe_64bit_regs_used
== 0
18130 || info_ptr
->spe_gp_size
== 0)
18131 info_ptr
->spe_gp_save_offset
= 0;
18133 if (! info_ptr
->lr_save_p
)
18134 info_ptr
->lr_save_offset
= 0;
18136 if (! info_ptr
->cr_save_p
)
18137 info_ptr
->cr_save_offset
= 0;
18142 /* Return true if the current function uses any GPRs in 64-bit SIMD
18146 spe_func_has_64bit_regs_p (void)
18150 /* Functions that save and restore all the call-saved registers will
18151 need to save/restore the registers in 64-bits. */
18152 if (crtl
->calls_eh_return
18153 || cfun
->calls_setjmp
18154 || crtl
->has_nonlocal_goto
)
18157 insns
= get_insns ();
18159 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
18165 /* FIXME: This should be implemented with attributes...
18167 (set_attr "spe64" "true")....then,
18168 if (get_spe64(insn)) return true;
18170 It's the only reliable way to do the stuff below. */
18172 i
= PATTERN (insn
);
18173 if (GET_CODE (i
) == SET
)
18175 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
18177 if (SPE_VECTOR_MODE (mode
))
18179 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
18189 debug_stack_info (rs6000_stack_t
*info
)
18191 const char *abi_string
;
18194 info
= rs6000_stack_info ();
18196 fprintf (stderr
, "\nStack information for function %s:\n",
18197 ((current_function_decl
&& DECL_NAME (current_function_decl
))
18198 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
18203 default: abi_string
= "Unknown"; break;
18204 case ABI_NONE
: abi_string
= "NONE"; break;
18205 case ABI_AIX
: abi_string
= "AIX"; break;
18206 case ABI_DARWIN
: abi_string
= "Darwin"; break;
18207 case ABI_V4
: abi_string
= "V.4"; break;
18210 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
18212 if (TARGET_ALTIVEC_ABI
)
18213 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
18215 if (TARGET_SPE_ABI
)
18216 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
18218 if (info
->first_gp_reg_save
!= 32)
18219 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
18221 if (info
->first_fp_reg_save
!= 64)
18222 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
18224 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
18225 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
18226 info
->first_altivec_reg_save
);
18228 if (info
->lr_save_p
)
18229 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
18231 if (info
->cr_save_p
)
18232 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
18234 if (info
->vrsave_mask
)
18235 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
18238 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
18241 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
18243 if (info
->gp_save_offset
)
18244 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
18246 if (info
->fp_save_offset
)
18247 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
18249 if (info
->altivec_save_offset
)
18250 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
18251 info
->altivec_save_offset
);
18253 if (info
->spe_gp_save_offset
)
18254 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
18255 info
->spe_gp_save_offset
);
18257 if (info
->vrsave_save_offset
)
18258 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
18259 info
->vrsave_save_offset
);
18261 if (info
->lr_save_offset
)
18262 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
18264 if (info
->cr_save_offset
)
18265 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
18267 if (info
->varargs_save_offset
)
18268 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
18270 if (info
->total_size
)
18271 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
18274 if (info
->vars_size
)
18275 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
18278 if (info
->parm_size
)
18279 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
18281 if (info
->fixed_size
)
18282 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
18285 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
18287 if (info
->spe_gp_size
)
18288 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
18291 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
18293 if (info
->altivec_size
)
18294 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
18296 if (info
->vrsave_size
)
18297 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
18299 if (info
->altivec_padding_size
)
18300 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
18301 info
->altivec_padding_size
);
18303 if (info
->spe_padding_size
)
18304 fprintf (stderr
, "\tspe_padding_size = %5d\n",
18305 info
->spe_padding_size
);
18308 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
18310 if (info
->save_size
)
18311 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
18313 if (info
->reg_size
!= 4)
18314 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
18316 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
18318 fprintf (stderr
, "\n");
18322 rs6000_return_addr (int count
, rtx frame
)
18324 /* Currently we don't optimize very well between prolog and body
18325 code and for PIC code the code can be actually quite bad, so
18326 don't try to be too clever here. */
18327 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
18329 cfun
->machine
->ra_needs_full_frame
= 1;
18336 plus_constant (Pmode
,
18338 (gen_rtx_MEM (Pmode
,
18339 memory_address (Pmode
, frame
))),
18340 RETURN_ADDRESS_OFFSET
)));
18343 cfun
->machine
->ra_need_lr
= 1;
18344 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
18347 /* Say whether a function is a candidate for sibcall handling or not. */
18350 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
18355 fntype
= TREE_TYPE (decl
);
18357 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
18359 /* We can't do it if the called function has more vector parameters
18360 than the current function; there's nowhere to put the VRsave code. */
18361 if (TARGET_ALTIVEC_ABI
18362 && TARGET_ALTIVEC_VRSAVE
18363 && !(decl
&& decl
== current_function_decl
))
18365 function_args_iterator args_iter
;
18369 /* Functions with vector parameters are required to have a
18370 prototype, so the argument type info must be available
18372 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
18373 if (TREE_CODE (type
) == VECTOR_TYPE
18374 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
18377 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
18378 if (TREE_CODE (type
) == VECTOR_TYPE
18379 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
18386 /* Under the AIX ABI we can't allow calls to non-local functions,
18387 because the callee may have a different TOC pointer to the
18388 caller and there's no way to ensure we restore the TOC when we
18389 return. With the secure-plt SYSV ABI we can't make non-local
18390 calls when -fpic/PIC because the plt call stubs use r30. */
18391 if (DEFAULT_ABI
== ABI_DARWIN
18392 || (DEFAULT_ABI
== ABI_AIX
18394 && !DECL_EXTERNAL (decl
)
18395 && (*targetm
.binds_local_p
) (decl
))
18396 || (DEFAULT_ABI
== ABI_V4
18397 && (!TARGET_SECURE_PLT
18400 && (*targetm
.binds_local_p
) (decl
)))))
18402 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
18404 if (!lookup_attribute ("longcall", attr_list
)
18405 || lookup_attribute ("shortcall", attr_list
))
18412 /* NULL if INSN insn is valid within a low-overhead loop.
18413 Otherwise return why doloop cannot be applied.
18414 PowerPC uses the COUNT register for branch on table instructions. */
18416 static const char *
18417 rs6000_invalid_within_doloop (const_rtx insn
)
18420 return "Function call in the loop.";
18423 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
18424 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
18425 return "Computed branch in the loop.";
18431 rs6000_ra_ever_killed (void)
18437 if (cfun
->is_thunk
)
18440 if (cfun
->machine
->lr_save_state
)
18441 return cfun
->machine
->lr_save_state
- 1;
18443 /* regs_ever_live has LR marked as used if any sibcalls are present,
18444 but this should not force saving and restoring in the
18445 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18446 clobbers LR, so that is inappropriate. */
18448 /* Also, the prologue can generate a store into LR that
18449 doesn't really count, like this:
18452 bcl to set PIC register
18456 When we're called from the epilogue, we need to avoid counting
18457 this as a store. */
18459 push_topmost_sequence ();
18460 top
= get_insns ();
18461 pop_topmost_sequence ();
18462 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
18464 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
18470 if (!SIBLING_CALL_P (insn
))
18473 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
18475 else if (set_of (reg
, insn
) != NULL_RTX
18476 && !prologue_epilogue_contains (insn
))
18483 /* Emit instructions needed to load the TOC register.
18484 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18485 a constant pool; or for SVR4 -fpic. */
18488 rs6000_emit_load_toc_table (int fromprolog
)
18491 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
18493 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
18496 rtx lab
, tmp1
, tmp2
, got
;
18498 lab
= gen_label_rtx ();
18499 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
18500 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18502 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
18504 got
= rs6000_got_sym ();
18505 tmp1
= tmp2
= dest
;
18508 tmp1
= gen_reg_rtx (Pmode
);
18509 tmp2
= gen_reg_rtx (Pmode
);
18511 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
18512 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
18513 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
18514 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
18516 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
18518 emit_insn (gen_load_toc_v4_pic_si ());
18519 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18521 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
18524 rtx temp0
= (fromprolog
18525 ? gen_rtx_REG (Pmode
, 0)
18526 : gen_reg_rtx (Pmode
));
18532 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
18533 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18535 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
18536 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18538 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
18539 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18540 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
18546 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
18547 lab
= gen_label_rtx ();
18548 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
18549 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18550 if (TARGET_LINK_STACK
)
18551 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
18552 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
18554 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
18556 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
18558 /* This is for AIX code running in non-PIC ELF32. */
18561 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
18562 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18564 emit_insn (gen_elf_high (dest
, realsym
));
18565 emit_insn (gen_elf_low (dest
, dest
, realsym
));
18569 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
18572 emit_insn (gen_load_toc_aix_si (dest
));
18574 emit_insn (gen_load_toc_aix_di (dest
));
18578 /* Emit instructions to restore the link register after determining where
18579 its value has been stored. */
18582 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
18584 rs6000_stack_t
*info
= rs6000_stack_info ();
18587 operands
[0] = source
;
18588 operands
[1] = scratch
;
18590 if (info
->lr_save_p
)
18592 rtx frame_rtx
= stack_pointer_rtx
;
18593 HOST_WIDE_INT sp_offset
= 0;
18596 if (frame_pointer_needed
18597 || cfun
->calls_alloca
18598 || info
->total_size
> 32767)
18600 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
18601 emit_move_insn (operands
[1], tmp
);
18602 frame_rtx
= operands
[1];
18604 else if (info
->push_p
)
18605 sp_offset
= info
->total_size
;
18607 tmp
= plus_constant (Pmode
, frame_rtx
,
18608 info
->lr_save_offset
+ sp_offset
);
18609 tmp
= gen_frame_mem (Pmode
, tmp
);
18610 emit_move_insn (tmp
, operands
[0]);
18613 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
18615 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18616 state of lr_save_p so any change from here on would be a bug. In
18617 particular, stop rs6000_ra_ever_killed from considering the SET
18618 of lr we may have added just above. */
18619 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
18622 static GTY(()) alias_set_type set
= -1;
18625 get_TOC_alias_set (void)
18628 set
= new_alias_set ();
18632 /* This returns nonzero if the current function uses the TOC. This is
18633 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18634 is generated by the ABI_V4 load_toc_* patterns. */
18641 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
18644 rtx pat
= PATTERN (insn
);
18647 if (GET_CODE (pat
) == PARALLEL
)
18648 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18650 rtx sub
= XVECEXP (pat
, 0, i
);
18651 if (GET_CODE (sub
) == USE
)
18653 sub
= XEXP (sub
, 0);
18654 if (GET_CODE (sub
) == UNSPEC
18655 && XINT (sub
, 1) == UNSPEC_TOC
)
18665 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
18667 rtx tocrel
, tocreg
, hi
;
18669 if (TARGET_DEBUG_ADDR
)
18671 if (GET_CODE (symbol
) == SYMBOL_REF
)
18672 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18676 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
18677 GET_RTX_NAME (GET_CODE (symbol
)));
18678 debug_rtx (symbol
);
18682 if (!can_create_pseudo_p ())
18683 df_set_regs_ever_live (TOC_REGISTER
, true);
18685 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
18686 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
18687 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
18690 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
18691 if (largetoc_reg
!= NULL
)
18693 emit_move_insn (largetoc_reg
, hi
);
18696 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
18699 /* Issue assembly directives that create a reference to the given DWARF
18700 FRAME_TABLE_LABEL from the current function section. */
18702 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
18704 fprintf (asm_out_file
, "\t.ref %s\n",
18705 (* targetm
.strip_name_encoding
) (frame_table_label
));
18708 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18709 and the change to the stack pointer. */
18712 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
18719 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
18720 if (hard_frame_needed
)
18721 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
18722 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
18723 || (hard_frame_needed
18724 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
18727 p
= rtvec_alloc (i
);
18730 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
18731 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
18734 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
18737 /* Emit the correct code for allocating stack space, as insns.
18738 If COPY_REG, make sure a copy of the old frame is left there.
18739 The generated code may use hard register 0 as a temporary. */
18742 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
18745 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
18746 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
18747 rtx todec
= gen_int_mode (-size
, Pmode
);
18750 if (INTVAL (todec
) != -size
)
18752 warning (0, "stack frame too large");
18753 emit_insn (gen_trap ());
18757 if (crtl
->limit_stack
)
18759 if (REG_P (stack_limit_rtx
)
18760 && REGNO (stack_limit_rtx
) > 1
18761 && REGNO (stack_limit_rtx
) <= 31)
18763 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
18764 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
18767 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
18769 && DEFAULT_ABI
== ABI_V4
)
18771 rtx toload
= gen_rtx_CONST (VOIDmode
,
18772 gen_rtx_PLUS (Pmode
,
18776 emit_insn (gen_elf_high (tmp_reg
, toload
));
18777 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
18778 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
18782 warning (0, "stack limit expression is not supported");
18788 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
18790 emit_move_insn (copy_reg
, stack_reg
);
18795 /* Need a note here so that try_split doesn't get confused. */
18796 if (get_last_insn () == NULL_RTX
)
18797 emit_note (NOTE_INSN_DELETED
);
18798 insn
= emit_move_insn (tmp_reg
, todec
);
18799 try_split (PATTERN (insn
), insn
, 0);
18803 insn
= emit_insn (TARGET_32BIT
18804 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
18806 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
18807 todec
, stack_reg
));
18808 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18809 it now and set the alias set/attributes. The above gen_*_update
18810 calls will generate a PARALLEL with the MEM set being the first
18812 par
= PATTERN (insn
);
18813 gcc_assert (GET_CODE (par
) == PARALLEL
);
18814 set
= XVECEXP (par
, 0, 0);
18815 gcc_assert (GET_CODE (set
) == SET
);
18816 mem
= SET_DEST (set
);
18817 gcc_assert (MEM_P (mem
));
18818 MEM_NOTRAP_P (mem
) = 1;
18819 set_mem_alias_set (mem
, get_frame_alias_set ());
18821 RTX_FRAME_RELATED_P (insn
) = 1;
18822 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
18823 gen_rtx_SET (VOIDmode
, stack_reg
,
18824 gen_rtx_PLUS (Pmode
, stack_reg
,
18825 GEN_INT (-size
))));
18828 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18830 #if PROBE_INTERVAL > 32768
18831 #error Cannot use indexed addressing mode for stack probing
18834 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18835 inclusive. These are offsets from the current stack pointer. */
18838 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
18840 /* See if we have a constant small number of probes to generate. If so,
18841 that's the easy case. */
18842 if (first
+ size
<= 32768)
18846 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18847 it exceeds SIZE. If only one probe is needed, this will not
18848 generate any code. Then probe at FIRST + SIZE. */
18849 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
18850 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
18853 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
18857 /* Otherwise, do the same as above, but in a loop. Note that we must be
18858 extra careful with variables wrapping around because we might be at
18859 the very top (or the very bottom) of the address space and we have
18860 to be able to handle this case properly; in particular, we use an
18861 equality test for the loop condition. */
18864 HOST_WIDE_INT rounded_size
;
18865 rtx r12
= gen_rtx_REG (Pmode
, 12);
18866 rtx r0
= gen_rtx_REG (Pmode
, 0);
18868 /* Sanity check for the addressing mode we're going to use. */
18869 gcc_assert (first
<= 32768);
18871 /* Step 1: round SIZE to the previous multiple of the interval. */
18873 rounded_size
= size
& -PROBE_INTERVAL
;
18876 /* Step 2: compute initial and final value of the loop counter. */
18878 /* TEST_ADDR = SP + FIRST. */
18879 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
18880 plus_constant (Pmode
, stack_pointer_rtx
,
18883 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18884 if (rounded_size
> 32768)
18886 emit_move_insn (r0
, GEN_INT (-rounded_size
));
18887 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
18888 gen_rtx_PLUS (Pmode
, r12
, r0
)));
18891 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
18892 plus_constant (Pmode
, r12
, -rounded_size
)));
18895 /* Step 3: the loop
18897 while (TEST_ADDR != LAST_ADDR)
18899 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18903 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18904 until it is equal to ROUNDED_SIZE. */
18907 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
18909 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
18912 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18913 that SIZE is equal to ROUNDED_SIZE. */
18915 if (size
!= rounded_size
)
18916 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
18920 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18921 absolute addresses. */
18924 output_probe_stack_range (rtx reg1
, rtx reg2
)
18926 static int labelno
= 0;
18927 char loop_lab
[32], end_lab
[32];
18930 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
18931 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
18933 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
18935 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18939 output_asm_insn ("cmpd 0,%0,%1", xops
);
18941 output_asm_insn ("cmpw 0,%0,%1", xops
);
18943 fputs ("\tbeq 0,", asm_out_file
);
18944 assemble_name_raw (asm_out_file
, end_lab
);
18945 fputc ('\n', asm_out_file
);
18947 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18948 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
18949 output_asm_insn ("addi %0,%0,%1", xops
);
18951 /* Probe at TEST_ADDR and branch. */
18952 xops
[1] = gen_rtx_REG (Pmode
, 0);
18953 output_asm_insn ("stw %1,0(%0)", xops
);
18954 fprintf (asm_out_file
, "\tb ");
18955 assemble_name_raw (asm_out_file
, loop_lab
);
18956 fputc ('\n', asm_out_file
);
18958 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
18963 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18964 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18965 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18966 deduce these equivalences by itself so it wasn't necessary to hold
18967 its hand so much. Don't be tempted to always supply d2_f_d_e with
18968 the actual cfa register, ie. r31 when we are using a hard frame
18969 pointer. That fails when saving regs off r1, and sched moves the
18970 r31 setup past the reg saves. */
18973 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
18974 rtx reg2
, rtx rreg
)
18978 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
18980 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
18983 gcc_checking_assert (val
== 0);
18984 real
= PATTERN (insn
);
18985 if (GET_CODE (real
) == PARALLEL
)
18986 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
18987 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
18989 rtx set
= XVECEXP (real
, 0, i
);
18991 RTX_FRAME_RELATED_P (set
) = 1;
18993 RTX_FRAME_RELATED_P (insn
) = 1;
18997 /* copy_rtx will not make unique copies of registers, so we need to
18998 ensure we don't have unwanted sharing here. */
19000 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
19003 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
19005 real
= copy_rtx (PATTERN (insn
));
19007 if (reg2
!= NULL_RTX
)
19008 real
= replace_rtx (real
, reg2
, rreg
);
19010 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
19011 gcc_checking_assert (val
== 0);
19013 real
= replace_rtx (real
, reg
,
19014 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
19015 STACK_POINTER_REGNUM
),
19018 /* We expect that 'real' is either a SET or a PARALLEL containing
19019 SETs (and possibly other stuff). In a PARALLEL, all the SETs
19020 are important so they all have to be marked RTX_FRAME_RELATED_P. */
19022 if (GET_CODE (real
) == SET
)
19026 temp
= simplify_rtx (SET_SRC (set
));
19028 SET_SRC (set
) = temp
;
19029 temp
= simplify_rtx (SET_DEST (set
));
19031 SET_DEST (set
) = temp
;
19032 if (GET_CODE (SET_DEST (set
)) == MEM
)
19034 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
19036 XEXP (SET_DEST (set
), 0) = temp
;
19043 gcc_assert (GET_CODE (real
) == PARALLEL
);
19044 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
19045 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
19047 rtx set
= XVECEXP (real
, 0, i
);
19049 temp
= simplify_rtx (SET_SRC (set
));
19051 SET_SRC (set
) = temp
;
19052 temp
= simplify_rtx (SET_DEST (set
));
19054 SET_DEST (set
) = temp
;
19055 if (GET_CODE (SET_DEST (set
)) == MEM
)
19057 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
19059 XEXP (SET_DEST (set
), 0) = temp
;
19061 RTX_FRAME_RELATED_P (set
) = 1;
19065 RTX_FRAME_RELATED_P (insn
) = 1;
19066 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
19071 /* Returns an insn that has a vrsave set operation with the
19072 appropriate CLOBBERs. */
19075 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
19078 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
19079 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
19082 = gen_rtx_SET (VOIDmode
,
19084 gen_rtx_UNSPEC_VOLATILE (SImode
,
19085 gen_rtvec (2, reg
, vrsave
),
19086 UNSPECV_SET_VRSAVE
));
19090 /* We need to clobber the registers in the mask so the scheduler
19091 does not move sets to VRSAVE before sets of AltiVec registers.
19093 However, if the function receives nonlocal gotos, reload will set
19094 all call saved registers live. We will end up with:
19096 (set (reg 999) (mem))
19097 (parallel [ (set (reg vrsave) (unspec blah))
19098 (clobber (reg 999))])
19100 The clobber will cause the store into reg 999 to be dead, and
19101 flow will attempt to delete an epilogue insn. In this case, we
19102 need an unspec use/set of the register. */
19104 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19105 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
19107 if (!epiloguep
|| call_used_regs
[i
])
19108 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
19109 gen_rtx_REG (V4SImode
, i
));
19112 rtx reg
= gen_rtx_REG (V4SImode
, i
);
19115 = gen_rtx_SET (VOIDmode
,
19117 gen_rtx_UNSPEC (V4SImode
,
19118 gen_rtvec (1, reg
), 27));
19122 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
19124 for (i
= 0; i
< nclobs
; ++i
)
19125 XVECEXP (insn
, 0, i
) = clobs
[i
];
19131 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
19135 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
19136 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
19137 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
19141 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
19143 return gen_frame_set (reg
, frame_reg
, offset
, false);
19147 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
19149 return gen_frame_set (reg
, frame_reg
, offset
, true);
19152 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
19153 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
19156 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
19157 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
19161 /* Some cases that need register indexed addressing. */
19162 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
19163 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
19164 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
19166 && SPE_VECTOR_MODE (mode
)
19167 && !SPE_CONST_OFFSET_OK (offset
))));
19169 reg
= gen_rtx_REG (mode
, regno
);
19170 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
19171 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
19172 NULL_RTX
, NULL_RTX
);
19175 /* Emit an offset memory reference suitable for a frame store, while
19176 converting to a valid addressing mode. */
19179 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
19181 rtx int_rtx
, offset_rtx
;
19183 int_rtx
= GEN_INT (offset
);
19185 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
19186 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
19188 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
19189 emit_move_insn (offset_rtx
, int_rtx
);
19192 offset_rtx
= int_rtx
;
19194 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
19197 #ifndef TARGET_FIX_AND_CONTINUE
19198 #define TARGET_FIX_AND_CONTINUE 0
19201 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
19202 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
19203 #define LAST_SAVRES_REGISTER 31
19204 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
19215 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
19217 /* Temporary holding space for an out-of-line register save/restore
19219 static char savres_routine_name
[30];
19221 /* Return the name for an out-of-line register save/restore routine.
19222 We are saving/restoring GPRs if GPR is true. */
19225 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
19227 const char *prefix
= "";
19228 const char *suffix
= "";
19230 /* Different targets are supposed to define
19231 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
19232 routine name could be defined with:
19234 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
19236 This is a nice idea in practice, but in reality, things are
19237 complicated in several ways:
19239 - ELF targets have save/restore routines for GPRs.
19241 - SPE targets use different prefixes for 32/64-bit registers, and
19242 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
19244 - PPC64 ELF targets have routines for save/restore of GPRs that
19245 differ in what they do with the link register, so having a set
19246 prefix doesn't work. (We only use one of the save routines at
19247 the moment, though.)
19249 - PPC32 elf targets have "exit" versions of the restore routines
19250 that restore the link register and can save some extra space.
19251 These require an extra suffix. (There are also "tail" versions
19252 of the restore routines and "GOT" versions of the save routines,
19253 but we don't generate those at present. Same problems apply,
19256 We deal with all this by synthesizing our own prefix/suffix and
19257 using that for the simple sprintf call shown above. */
19260 /* No floating point saves on the SPE. */
19261 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
19263 if ((sel
& SAVRES_SAVE
))
19264 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
19266 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
19268 if ((sel
& SAVRES_LR
))
19271 else if (DEFAULT_ABI
== ABI_V4
)
19276 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
19277 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
19278 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
19279 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
19280 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19281 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
19285 if ((sel
& SAVRES_LR
))
19288 else if (DEFAULT_ABI
== ABI_AIX
)
19290 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
19291 /* No out-of-line save/restore routines for GPRs on AIX. */
19292 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
19296 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
19297 prefix
= ((sel
& SAVRES_SAVE
)
19298 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
19299 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
19300 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
19302 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
19303 if ((sel
& SAVRES_LR
))
19304 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
19308 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
19309 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
19312 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19313 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
19318 if (DEFAULT_ABI
== ABI_DARWIN
)
19320 /* The Darwin approach is (slightly) different, in order to be
19321 compatible with code generated by the system toolchain. There is a
19322 single symbol for the start of save sequence, and the code here
19323 embeds an offset into that code on the basis of the first register
19325 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
19326 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
19327 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
19328 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
19329 (regno
- 13) * 4, prefix
, regno
);
19330 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
19331 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
19332 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
19333 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19334 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
19335 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
19340 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
19342 return savres_routine_name
;
19345 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19346 We are saving/restoring GPRs if GPR is true. */
19349 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
19351 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
19352 ? info
->first_gp_reg_save
19353 : (sel
& SAVRES_REG
) == SAVRES_FPR
19354 ? info
->first_fp_reg_save
- 32
19355 : (sel
& SAVRES_REG
) == SAVRES_VR
19356 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
19361 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
19362 versions of the gpr routines. */
19363 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
19364 && info
->spe_64bit_regs_used
)
19365 select
^= SAVRES_FPR
^ SAVRES_GPR
;
19367 /* Don't generate bogus routine names. */
19368 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
19369 && regno
<= LAST_SAVRES_REGISTER
19370 && select
>= 0 && select
<= 12);
19372 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
19378 name
= rs6000_savres_routine_name (info
, regno
, sel
);
19380 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
19381 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
19382 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
19388 /* Emit a sequence of insns, including a stack tie if needed, for
19389 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
19390 reset the stack pointer, but move the base of the frame into
19391 reg UPDT_REGNO for use by out-of-line register restore routines. */
19394 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
19395 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
19396 unsigned updt_regno
)
19400 /* This blockage is needed so that sched doesn't decide to move
19401 the sp change before the register restores. */
19402 if (DEFAULT_ABI
== ABI_V4
19404 && info
->spe_64bit_regs_used
!= 0
19405 && info
->first_gp_reg_save
!= 32))
19406 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
19408 /* If we are restoring registers out-of-line, we will be using the
19409 "exit" variants of the restore routines, which will reset the
19410 stack for us. But we do need to point updt_reg into the
19411 right place for those routines. */
19412 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
19414 if (frame_off
!= 0)
19415 return emit_insn (gen_add3_insn (updt_reg_rtx
,
19416 frame_reg_rtx
, GEN_INT (frame_off
)));
19417 else if (REGNO (frame_reg_rtx
) != updt_regno
)
19418 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
19423 /* Return the register number used as a pointer by out-of-line
19424 save/restore functions. */
19426 static inline unsigned
19427 ptr_regno_for_savres (int sel
)
19429 if (DEFAULT_ABI
== ABI_AIX
)
19430 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
19431 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
19434 /* Construct a parallel rtx describing the effect of a call to an
19435 out-of-line register save/restore routine, and emit the insn
19436 or jump_insn as appropriate. */
19439 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
19440 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
19441 enum machine_mode reg_mode
, int sel
)
19444 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
19445 int reg_size
= GET_MODE_SIZE (reg_mode
);
19451 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
19452 ? info
->first_gp_reg_save
19453 : (sel
& SAVRES_REG
) == SAVRES_FPR
19454 ? info
->first_fp_reg_save
19455 : (sel
& SAVRES_REG
) == SAVRES_VR
19456 ? info
->first_altivec_reg_save
19458 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
19460 : (sel
& SAVRES_REG
) == SAVRES_FPR
19462 : (sel
& SAVRES_REG
) == SAVRES_VR
19463 ? LAST_ALTIVEC_REGNO
+ 1
19465 n_regs
= end_reg
- start_reg
;
19466 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
19467 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
19470 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
19471 RTVEC_ELT (p
, offset
++) = ret_rtx
;
19473 RTVEC_ELT (p
, offset
++)
19474 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
19476 sym
= rs6000_savres_routine_sym (info
, sel
);
19477 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
19479 use_reg
= ptr_regno_for_savres (sel
);
19480 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19482 /* Vector regs are saved/restored using [reg+reg] addressing. */
19483 RTVEC_ELT (p
, offset
++)
19484 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
19485 RTVEC_ELT (p
, offset
++)
19486 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
19489 RTVEC_ELT (p
, offset
++)
19490 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
19492 for (i
= 0; i
< end_reg
- start_reg
; i
++)
19493 RTVEC_ELT (p
, i
+ offset
)
19494 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
19495 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
19496 (sel
& SAVRES_SAVE
) != 0);
19498 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
19499 RTVEC_ELT (p
, i
+ offset
)
19500 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
19502 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
19504 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
19506 insn
= emit_jump_insn (par
);
19507 JUMP_LABEL (insn
) = ret_rtx
;
19510 insn
= emit_insn (par
);
19514 /* Determine whether the gp REG is really used. */
19517 rs6000_reg_live_or_pic_offset_p (int reg
)
19519 /* If the function calls eh_return, claim used all the registers that would
19520 be checked for liveness otherwise. This is required for the PIC offset
19521 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19522 register allocation purposes in this case. */
19524 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
19525 && (!call_used_regs
[reg
]
19526 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
19527 && !TARGET_SINGLE_PIC_BASE
19528 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
19529 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
19530 && !TARGET_SINGLE_PIC_BASE
19531 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19532 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
19535 /* Emit function prologue as insns. */
19538 rs6000_emit_prologue (void)
19540 rs6000_stack_t
*info
= rs6000_stack_info ();
19541 enum machine_mode reg_mode
= Pmode
;
19542 int reg_size
= TARGET_32BIT
? 4 : 8;
19543 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
19544 rtx frame_reg_rtx
= sp_reg_rtx
;
19545 unsigned int cr_save_regno
;
19546 rtx cr_save_rtx
= NULL_RTX
;
19549 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
19550 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
19551 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
19552 /* Offset to top of frame for frame_reg and sp respectively. */
19553 HOST_WIDE_INT frame_off
= 0;
19554 HOST_WIDE_INT sp_off
= 0;
19556 #ifdef ENABLE_CHECKING
19557 /* Track and check usage of r0, r11, r12. */
19558 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
19559 #define START_USE(R) do \
19561 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19562 reg_inuse |= 1 << (R); \
19564 #define END_USE(R) do \
19566 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
19567 reg_inuse &= ~(1 << (R)); \
19569 #define NOT_INUSE(R) do \
19571 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19574 #define START_USE(R) do {} while (0)
19575 #define END_USE(R) do {} while (0)
19576 #define NOT_INUSE(R) do {} while (0)
19579 if (flag_stack_usage_info
)
19580 current_function_static_stack_size
= info
->total_size
;
19582 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& info
->total_size
)
19583 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, info
->total_size
);
19585 if (TARGET_FIX_AND_CONTINUE
)
19587 /* gdb on darwin arranges to forward a function from the old
19588 address by modifying the first 5 instructions of the function
19589 to branch to the overriding function. This is necessary to
19590 permit function pointers that point to the old function to
19591 actually forward to the new function. */
19592 emit_insn (gen_nop ());
19593 emit_insn (gen_nop ());
19594 emit_insn (gen_nop ());
19595 emit_insn (gen_nop ());
19596 emit_insn (gen_nop ());
19599 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
19601 reg_mode
= V2SImode
;
19605 /* Handle world saves specially here. */
19606 if (WORLD_SAVE_P (info
))
19613 /* save_world expects lr in r0. */
19614 reg0
= gen_rtx_REG (Pmode
, 0);
19615 if (info
->lr_save_p
)
19617 insn
= emit_move_insn (reg0
,
19618 gen_rtx_REG (Pmode
, LR_REGNO
));
19619 RTX_FRAME_RELATED_P (insn
) = 1;
19622 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19623 assumptions about the offsets of various bits of the stack
19625 gcc_assert (info
->gp_save_offset
== -220
19626 && info
->fp_save_offset
== -144
19627 && info
->lr_save_offset
== 8
19628 && info
->cr_save_offset
== 4
19631 && (!crtl
->calls_eh_return
19632 || info
->ehrd_offset
== -432)
19633 && info
->vrsave_save_offset
== -224
19634 && info
->altivec_save_offset
== -416);
19636 treg
= gen_rtx_REG (SImode
, 11);
19637 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
19639 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19640 in R11. It also clobbers R12, so beware! */
19642 /* Preserve CR2 for save_world prologues */
19644 sz
+= 32 - info
->first_gp_reg_save
;
19645 sz
+= 64 - info
->first_fp_reg_save
;
19646 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
19647 p
= rtvec_alloc (sz
);
19649 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
19650 gen_rtx_REG (SImode
,
19652 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
19653 gen_rtx_SYMBOL_REF (Pmode
,
19655 /* We do floats first so that the instruction pattern matches
19657 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
19659 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
19661 info
->first_fp_reg_save
+ i
),
19663 info
->fp_save_offset
+ frame_off
+ 8 * i
);
19664 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
19666 = gen_frame_store (gen_rtx_REG (V4SImode
,
19667 info
->first_altivec_reg_save
+ i
),
19669 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
19670 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19672 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
19674 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
19676 /* CR register traditionally saved as CR2. */
19678 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
19679 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
19680 /* Explain about use of R0. */
19681 if (info
->lr_save_p
)
19683 = gen_frame_store (reg0
,
19684 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
19685 /* Explain what happens to the stack pointer. */
19687 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
19688 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
19691 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
19692 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
19693 treg
, GEN_INT (-info
->total_size
));
19694 sp_off
= frame_off
= info
->total_size
;
19697 strategy
= info
->savres_strategy
;
19699 /* For V.4, update stack before we do any saving and set back pointer. */
19700 if (! WORLD_SAVE_P (info
)
19702 && (DEFAULT_ABI
== ABI_V4
19703 || crtl
->calls_eh_return
))
19705 bool need_r11
= (TARGET_SPE
19706 ? (!(strategy
& SAVE_INLINE_GPRS
)
19707 && info
->spe_64bit_regs_used
== 0)
19708 : (!(strategy
& SAVE_INLINE_FPRS
)
19709 || !(strategy
& SAVE_INLINE_GPRS
)
19710 || !(strategy
& SAVE_INLINE_VRS
)));
19711 int ptr_regno
= -1;
19712 rtx ptr_reg
= NULL_RTX
;
19715 if (info
->total_size
< 32767)
19716 frame_off
= info
->total_size
;
19719 else if (info
->cr_save_p
19721 || info
->first_fp_reg_save
< 64
19722 || info
->first_gp_reg_save
< 32
19723 || info
->altivec_size
!= 0
19724 || info
->vrsave_mask
!= 0
19725 || crtl
->calls_eh_return
)
19729 /* The prologue won't be saving any regs so there is no need
19730 to set up a frame register to access any frame save area.
19731 We also won't be using frame_off anywhere below, but set
19732 the correct value anyway to protect against future
19733 changes to this function. */
19734 frame_off
= info
->total_size
;
19736 if (ptr_regno
!= -1)
19738 /* Set up the frame offset to that needed by the first
19739 out-of-line save function. */
19740 START_USE (ptr_regno
);
19741 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
19742 frame_reg_rtx
= ptr_reg
;
19743 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
19744 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
19745 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
19746 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
19747 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
19748 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
19749 frame_off
= -ptr_off
;
19751 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
19752 sp_off
= info
->total_size
;
19753 if (frame_reg_rtx
!= sp_reg_rtx
)
19754 rs6000_emit_stack_tie (frame_reg_rtx
, false);
19757 /* If we use the link register, get it into r0. */
19758 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
19760 rtx addr
, reg
, mem
;
19762 reg
= gen_rtx_REG (Pmode
, 0);
19764 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
19765 RTX_FRAME_RELATED_P (insn
) = 1;
19767 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
19768 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
19770 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19771 GEN_INT (info
->lr_save_offset
+ frame_off
));
19772 mem
= gen_rtx_MEM (Pmode
, addr
);
19773 /* This should not be of rs6000_sr_alias_set, because of
19774 __builtin_return_address. */
19776 insn
= emit_move_insn (mem
, reg
);
19777 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
19778 NULL_RTX
, NULL_RTX
);
19783 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
19784 r12 will be needed by out-of-line gpr restore. */
19785 cr_save_regno
= (DEFAULT_ABI
== ABI_AIX
19786 && !(strategy
& (SAVE_INLINE_GPRS
19787 | SAVE_NOINLINE_GPRS_SAVES_LR
))
19789 if (!WORLD_SAVE_P (info
)
19791 && REGNO (frame_reg_rtx
) != cr_save_regno
19792 && !(using_static_chain_p
&& cr_save_regno
== 11))
19796 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
19797 START_USE (cr_save_regno
);
19798 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
19799 RTX_FRAME_RELATED_P (insn
) = 1;
19800 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19801 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19802 But that's OK. All we have to do is specify that _one_ condition
19803 code register is saved in this stack slot. The thrower's epilogue
19804 will then restore all the call-saved registers.
19805 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19806 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
19807 gen_rtx_REG (SImode
, CR2_REGNO
));
19808 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
19811 /* Do any required saving of fpr's. If only one or two to save, do
19812 it ourselves. Otherwise, call function. */
19813 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
19816 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
19817 if (save_reg_p (info
->first_fp_reg_save
+ i
))
19818 emit_frame_save (frame_reg_rtx
,
19819 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
19820 ? DFmode
: SFmode
),
19821 info
->first_fp_reg_save
+ i
,
19822 info
->fp_save_offset
+ frame_off
+ 8 * i
,
19823 sp_off
- frame_off
);
19825 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
19827 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
19828 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
19829 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
19830 rtx ptr_reg
= frame_reg_rtx
;
19832 if (REGNO (frame_reg_rtx
) == ptr_regno
)
19833 gcc_checking_assert (frame_off
== 0);
19836 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
19837 NOT_INUSE (ptr_regno
);
19838 emit_insn (gen_add3_insn (ptr_reg
,
19839 frame_reg_rtx
, GEN_INT (frame_off
)));
19841 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
19842 info
->fp_save_offset
,
19843 info
->lr_save_offset
,
19845 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
19846 NULL_RTX
, NULL_RTX
);
19851 /* Save GPRs. This is done as a PARALLEL if we are using
19852 the store-multiple instructions. */
19853 if (!WORLD_SAVE_P (info
)
19855 && info
->spe_64bit_regs_used
!= 0
19856 && info
->first_gp_reg_save
!= 32)
19859 rtx spe_save_area_ptr
;
19860 HOST_WIDE_INT save_off
;
19861 int ool_adjust
= 0;
19863 /* Determine whether we can address all of the registers that need
19864 to be saved with an offset from frame_reg_rtx that fits in
19865 the small const field for SPE memory instructions. */
19866 int spe_regs_addressable
19867 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
19868 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
19869 && (strategy
& SAVE_INLINE_GPRS
));
19871 if (spe_regs_addressable
)
19873 spe_save_area_ptr
= frame_reg_rtx
;
19874 save_off
= frame_off
;
19878 /* Make r11 point to the start of the SPE save area. We need
19879 to be careful here if r11 is holding the static chain. If
19880 it is, then temporarily save it in r0. */
19881 HOST_WIDE_INT offset
;
19883 if (!(strategy
& SAVE_INLINE_GPRS
))
19884 ool_adjust
= 8 * (info
->first_gp_reg_save
19885 - (FIRST_SAVRES_REGISTER
+ 1));
19886 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
19887 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
19888 save_off
= frame_off
- offset
;
19890 if (using_static_chain_p
)
19892 rtx r0
= gen_rtx_REG (Pmode
, 0);
19895 gcc_assert (info
->first_gp_reg_save
> 11);
19897 emit_move_insn (r0
, spe_save_area_ptr
);
19899 else if (REGNO (frame_reg_rtx
) != 11)
19902 emit_insn (gen_addsi3 (spe_save_area_ptr
,
19903 frame_reg_rtx
, GEN_INT (offset
)));
19904 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
19905 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
19908 if ((strategy
& SAVE_INLINE_GPRS
))
19910 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19911 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
19912 emit_frame_save (spe_save_area_ptr
, reg_mode
,
19913 info
->first_gp_reg_save
+ i
,
19914 (info
->spe_gp_save_offset
+ save_off
19916 sp_off
- save_off
);
19920 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
19921 info
->spe_gp_save_offset
+ save_off
,
19923 SAVRES_SAVE
| SAVRES_GPR
);
19925 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
19926 NULL_RTX
, NULL_RTX
);
19929 /* Move the static chain pointer back. */
19930 if (!spe_regs_addressable
)
19932 if (using_static_chain_p
)
19934 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
19937 else if (REGNO (frame_reg_rtx
) != 11)
19941 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
19943 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
19944 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
19945 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
19946 rtx ptr_reg
= frame_reg_rtx
;
19947 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
19948 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
19952 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
19954 /* Need to adjust r11 (r12) if we saved any FPRs. */
19955 if (end_save
+ frame_off
!= 0)
19957 rtx offset
= GEN_INT (end_save
+ frame_off
);
19960 frame_off
= -end_save
;
19962 NOT_INUSE (ptr_regno
);
19963 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
19965 else if (!ptr_set_up
)
19967 NOT_INUSE (ptr_regno
);
19968 emit_move_insn (ptr_reg
, frame_reg_rtx
);
19970 ptr_off
= -end_save
;
19971 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
19972 info
->gp_save_offset
+ ptr_off
,
19973 info
->lr_save_offset
+ ptr_off
,
19975 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
19976 NULL_RTX
, NULL_RTX
);
19980 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
19984 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
19985 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19987 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
19989 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
19990 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
19991 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
19992 NULL_RTX
, NULL_RTX
);
19994 else if (!WORLD_SAVE_P (info
))
19997 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19998 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
19999 emit_frame_save (frame_reg_rtx
, reg_mode
,
20000 info
->first_gp_reg_save
+ i
,
20001 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
20002 sp_off
- frame_off
);
20005 if (crtl
->calls_eh_return
)
20012 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
20013 if (regno
== INVALID_REGNUM
)
20017 p
= rtvec_alloc (i
);
20021 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
20022 if (regno
== INVALID_REGNUM
)
20026 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
20028 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
20029 RTVEC_ELT (p
, i
) = insn
;
20030 RTX_FRAME_RELATED_P (insn
) = 1;
20033 insn
= emit_insn (gen_blockage ());
20034 RTX_FRAME_RELATED_P (insn
) = 1;
20035 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
20038 /* In AIX ABI we need to make sure r2 is really saved. */
20039 if (TARGET_AIX
&& crtl
->calls_eh_return
)
20041 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
20042 rtx save_insn
, join_insn
, note
;
20043 long toc_restore_insn
;
20045 tmp_reg
= gen_rtx_REG (Pmode
, 11);
20046 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
20047 if (using_static_chain_p
)
20050 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
20054 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
20055 /* Peek at instruction to which this function returns. If it's
20056 restoring r2, then we know we've already saved r2. We can't
20057 unconditionally save r2 because the value we have will already
20058 be updated if we arrived at this function via a plt call or
20059 toc adjusting stub. */
20060 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
20061 toc_restore_insn
= TARGET_32BIT
? 0x80410014 : 0xE8410028;
20062 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
20063 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
20064 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
20065 validate_condition_mode (EQ
, CCUNSmode
);
20066 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
20067 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
20068 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
20069 toc_save_done
= gen_label_rtx ();
20070 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
20071 gen_rtx_EQ (VOIDmode
, compare_result
,
20073 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
20075 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
20076 JUMP_LABEL (jump
) = toc_save_done
;
20077 LABEL_NUSES (toc_save_done
) += 1;
20079 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
20080 TOC_REGNUM
, frame_off
+ 5 * reg_size
,
20081 sp_off
- frame_off
);
20083 emit_label (toc_save_done
);
20085 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
20086 have a CFG that has different saves along different paths.
20087 Move the note to a dummy blockage insn, which describes that
20088 R2 is unconditionally saved after the label. */
20089 /* ??? An alternate representation might be a special insn pattern
20090 containing both the branch and the store. That might let the
20091 code that minimizes the number of DW_CFA_advance opcodes better
20092 freedom in placing the annotations. */
20093 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
20095 remove_note (save_insn
, note
);
20097 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
20098 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
20099 RTX_FRAME_RELATED_P (save_insn
) = 0;
20101 join_insn
= emit_insn (gen_blockage ());
20102 REG_NOTES (join_insn
) = note
;
20103 RTX_FRAME_RELATED_P (join_insn
) = 1;
20105 if (using_static_chain_p
)
20107 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
20114 /* Save CR if we use any that must be preserved. */
20115 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
20117 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20118 GEN_INT (info
->cr_save_offset
+ frame_off
));
20119 rtx mem
= gen_frame_mem (SImode
, addr
);
20120 /* See the large comment above about why CR2_REGNO is used. */
20121 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
20123 /* If we didn't copy cr before, do so now using r0. */
20124 if (cr_save_rtx
== NULL_RTX
)
20129 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
20130 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
20131 RTX_FRAME_RELATED_P (insn
) = 1;
20132 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
20133 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
20135 insn
= emit_move_insn (mem
, cr_save_rtx
);
20136 END_USE (REGNO (cr_save_rtx
));
20138 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20139 NULL_RTX
, NULL_RTX
);
20142 /* Update stack and set back pointer unless this is V.4,
20143 for which it was done previously. */
20144 if (!WORLD_SAVE_P (info
) && info
->push_p
20145 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
20147 rtx ptr_reg
= NULL
;
20150 /* If saving altivec regs we need to be able to address all save
20151 locations using a 16-bit offset. */
20152 if ((strategy
& SAVE_INLINE_VRS
) == 0
20153 || (info
->altivec_size
!= 0
20154 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
20155 + info
->total_size
- frame_off
) > 32767)
20156 || (info
->vrsave_size
!= 0
20157 && (info
->vrsave_save_offset
20158 + info
->total_size
- frame_off
) > 32767))
20160 int sel
= SAVRES_SAVE
| SAVRES_VR
;
20161 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
20163 if (using_static_chain_p
20164 && ptr_regno
== STATIC_CHAIN_REGNUM
)
20166 if (REGNO (frame_reg_rtx
) != ptr_regno
)
20167 START_USE (ptr_regno
);
20168 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
20169 frame_reg_rtx
= ptr_reg
;
20170 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
20171 frame_off
= -ptr_off
;
20173 else if (REGNO (frame_reg_rtx
) == 1)
20174 frame_off
= info
->total_size
;
20175 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
20176 sp_off
= info
->total_size
;
20177 if (frame_reg_rtx
!= sp_reg_rtx
)
20178 rs6000_emit_stack_tie (frame_reg_rtx
, false);
20181 /* Set frame pointer, if needed. */
20182 if (frame_pointer_needed
)
20184 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
20186 RTX_FRAME_RELATED_P (insn
) = 1;
20189 /* Save AltiVec registers if needed. Save here because the red zone does
20190 not always include AltiVec registers. */
20191 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
20192 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
20194 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
20196 /* Oddly, the vector save/restore functions point r0 at the end
20197 of the save area, then use r11 or r12 to load offsets for
20198 [reg+reg] addressing. */
20199 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
20200 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
20201 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
20203 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
20205 if (end_save
+ frame_off
!= 0)
20207 rtx offset
= GEN_INT (end_save
+ frame_off
);
20209 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
20212 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20214 ptr_off
= -end_save
;
20215 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
20216 info
->altivec_save_offset
+ ptr_off
,
20217 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
20218 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
20219 NULL_RTX
, NULL_RTX
);
20220 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
20222 /* The oddity mentioned above clobbered our frame reg. */
20223 emit_move_insn (frame_reg_rtx
, ptr_reg
);
20224 frame_off
= ptr_off
;
20227 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
20228 && info
->altivec_size
!= 0)
20232 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20233 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20235 rtx areg
, savereg
, mem
;
20238 offset
= (info
->altivec_save_offset
+ frame_off
20239 + 16 * (i
- info
->first_altivec_reg_save
));
20241 savereg
= gen_rtx_REG (V4SImode
, i
);
20244 areg
= gen_rtx_REG (Pmode
, 0);
20245 emit_move_insn (areg
, GEN_INT (offset
));
20247 /* AltiVec addressing mode is [reg+reg]. */
20248 mem
= gen_frame_mem (V4SImode
,
20249 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
20251 insn
= emit_move_insn (mem
, savereg
);
20253 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20254 areg
, GEN_INT (offset
));
20258 /* VRSAVE is a bit vector representing which AltiVec registers
20259 are used. The OS uses this to determine which vector
20260 registers to save on a context switch. We need to save
20261 VRSAVE on the stack frame, add whatever AltiVec registers we
20262 used in this function, and do the corresponding magic in the
20265 if (!WORLD_SAVE_P (info
)
20267 && TARGET_ALTIVEC_VRSAVE
20268 && info
->vrsave_mask
!= 0)
20274 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
20275 be using r12 as frame_reg_rtx and r11 as the static chain
20276 pointer for nested functions. */
20278 if (DEFAULT_ABI
== ABI_AIX
&& !using_static_chain_p
)
20280 else if (REGNO (frame_reg_rtx
) == 12)
20283 if (using_static_chain_p
)
20287 NOT_INUSE (save_regno
);
20288 reg
= gen_rtx_REG (SImode
, save_regno
);
20289 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
20291 emit_insn (gen_get_vrsave_internal (reg
));
20293 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
20296 offset
= info
->vrsave_save_offset
+ frame_off
;
20297 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
20299 /* Include the registers in the mask. */
20300 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
20302 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
20305 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
20306 if (!TARGET_SINGLE_PIC_BASE
20307 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
20308 || (DEFAULT_ABI
== ABI_V4
20309 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
20310 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
20312 /* If emit_load_toc_table will use the link register, we need to save
20313 it. We use R12 for this purpose because emit_load_toc_table
20314 can use register 0. This allows us to use a plain 'blr' to return
20315 from the procedure more often. */
20316 int save_LR_around_toc_setup
= (TARGET_ELF
20317 && DEFAULT_ABI
!= ABI_AIX
20319 && ! info
->lr_save_p
20320 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
20321 if (save_LR_around_toc_setup
)
20323 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
20324 rtx tmp
= gen_rtx_REG (Pmode
, 12);
20326 insn
= emit_move_insn (tmp
, lr
);
20327 RTX_FRAME_RELATED_P (insn
) = 1;
20329 rs6000_emit_load_toc_table (TRUE
);
20331 insn
= emit_move_insn (lr
, tmp
);
20332 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
20333 RTX_FRAME_RELATED_P (insn
) = 1;
20336 rs6000_emit_load_toc_table (TRUE
);
20340 if (!TARGET_SINGLE_PIC_BASE
20341 && DEFAULT_ABI
== ABI_DARWIN
20342 && flag_pic
&& crtl
->uses_pic_offset_table
)
20344 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
20345 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
20347 /* Save and restore LR locally around this call (in R0). */
20348 if (!info
->lr_save_p
)
20349 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
20351 emit_insn (gen_load_macho_picbase (src
));
20353 emit_move_insn (gen_rtx_REG (Pmode
,
20354 RS6000_PIC_OFFSET_TABLE_REGNUM
),
20357 if (!info
->lr_save_p
)
20358 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
20362 /* If we need to, save the TOC register after doing the stack setup.
20363 Do not emit eh frame info for this save. The unwinder wants info,
20364 conceptually attached to instructions in this function, about
20365 register values in the caller of this function. This R2 may have
20366 already been changed from the value in the caller.
20367 We don't attempt to write accurate DWARF EH frame info for R2
20368 because code emitted by gcc for a (non-pointer) function call
20369 doesn't save and restore R2. Instead, R2 is managed out-of-line
20370 by a linker generated plt call stub when the function resides in
20371 a shared library. This behaviour is costly to describe in DWARF,
20372 both in terms of the size of DWARF info and the time taken in the
20373 unwinder to interpret it. R2 changes, apart from the
20374 calls_eh_return case earlier in this function, are handled by
20375 linux-unwind.h frob_update_context. */
20376 if (rs6000_save_toc_in_prologue_p ())
20378 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
20379 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, 5 * reg_size
));
20383 /* Write function prologue. */
20386 rs6000_output_function_prologue (FILE *file
,
20387 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
20389 rs6000_stack_t
*info
= rs6000_stack_info ();
20391 if (TARGET_DEBUG_STACK
)
20392 debug_stack_info (info
);
20394 /* Write .extern for any function we will call to save and restore
20396 if (info
->first_fp_reg_save
< 64
20401 int regno
= info
->first_fp_reg_save
- 32;
20403 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
20405 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
20406 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20407 name
= rs6000_savres_routine_name (info
, regno
, sel
);
20408 fprintf (file
, "\t.extern %s\n", name
);
20410 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
20412 bool lr
= (info
->savres_strategy
20413 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
20414 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20415 name
= rs6000_savres_routine_name (info
, regno
, sel
);
20416 fprintf (file
, "\t.extern %s\n", name
);
20420 rs6000_pic_labelno
++;
20423 /* Non-zero if vmx regs are restored before the frame pop, zero if
20424 we restore after the pop when possible. */
20425 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20427 /* Restoring cr is a two step process: loading a reg from the frame
20428 save, then moving the reg to cr. For ABI_V4 we must let the
20429 unwinder know that the stack location is no longer valid at or
20430 before the stack deallocation, but we can't emit a cfa_restore for
20431 cr at the stack deallocation like we do for other registers.
20432 The trouble is that it is possible for the move to cr to be
20433 scheduled after the stack deallocation. So say exactly where cr
20434 is located on each of the two insns. */
20437 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
20439 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
20440 rtx reg
= gen_rtx_REG (SImode
, regno
);
20441 rtx insn
= emit_move_insn (reg
, mem
);
20443 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
20445 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
20446 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
20448 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
20449 RTX_FRAME_RELATED_P (insn
) = 1;
20454 /* Reload CR from REG. */
20457 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
20462 if (using_mfcr_multiple
)
20464 for (i
= 0; i
< 8; i
++)
20465 if (save_reg_p (CR0_REGNO
+ i
))
20467 gcc_assert (count
);
20470 if (using_mfcr_multiple
&& count
> 1)
20475 p
= rtvec_alloc (count
);
20478 for (i
= 0; i
< 8; i
++)
20479 if (save_reg_p (CR0_REGNO
+ i
))
20481 rtvec r
= rtvec_alloc (2);
20482 RTVEC_ELT (r
, 0) = reg
;
20483 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
20484 RTVEC_ELT (p
, ndx
) =
20485 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
20486 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
20489 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20490 gcc_assert (ndx
== count
);
20493 for (i
= 0; i
< 8; i
++)
20494 if (save_reg_p (CR0_REGNO
+ i
))
20495 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
20498 if (!exit_func
&& (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
20500 rtx insn
= get_last_insn ();
20501 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
20503 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
20504 RTX_FRAME_RELATED_P (insn
) = 1;
20508 /* Like cr, the move to lr instruction can be scheduled after the
20509 stack deallocation, but unlike cr, its stack frame save is still
20510 valid. So we only need to emit the cfa_restore on the correct
20514 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
20516 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
20517 rtx reg
= gen_rtx_REG (Pmode
, regno
);
20519 emit_move_insn (reg
, mem
);
20523 restore_saved_lr (int regno
, bool exit_func
)
20525 rtx reg
= gen_rtx_REG (Pmode
, regno
);
20526 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
20527 rtx insn
= emit_move_insn (lr
, reg
);
20529 if (!exit_func
&& flag_shrink_wrap
)
20531 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
20532 RTX_FRAME_RELATED_P (insn
) = 1;
20537 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
20539 if (info
->cr_save_p
)
20540 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20541 gen_rtx_REG (SImode
, CR2_REGNO
),
20543 if (info
->lr_save_p
)
20544 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20545 gen_rtx_REG (Pmode
, LR_REGNO
),
20547 return cfa_restores
;
20550 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20551 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20552 below stack pointer not cloberred by signals. */
20555 offset_below_red_zone_p (HOST_WIDE_INT offset
)
20557 return offset
< (DEFAULT_ABI
== ABI_V4
20559 : TARGET_32BIT
? -220 : -288);
20562 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20565 emit_cfa_restores (rtx cfa_restores
)
20567 rtx insn
= get_last_insn ();
20568 rtx
*loc
= ®_NOTES (insn
);
20571 loc
= &XEXP (*loc
, 1);
20572 *loc
= cfa_restores
;
20573 RTX_FRAME_RELATED_P (insn
) = 1;
20576 /* Emit function epilogue as insns. */
20579 rs6000_emit_epilogue (int sibcall
)
20581 rs6000_stack_t
*info
;
20582 int restoring_GPRs_inline
;
20583 int restoring_FPRs_inline
;
20584 int using_load_multiple
;
20585 int using_mtcr_multiple
;
20586 int use_backchain_to_restore_sp
;
20589 HOST_WIDE_INT frame_off
= 0;
20590 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
20591 rtx frame_reg_rtx
= sp_reg_rtx
;
20592 rtx cfa_restores
= NULL_RTX
;
20594 rtx cr_save_reg
= NULL_RTX
;
20595 enum machine_mode reg_mode
= Pmode
;
20596 int reg_size
= TARGET_32BIT
? 4 : 8;
20599 unsigned ptr_regno
;
20601 info
= rs6000_stack_info ();
20603 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
20605 reg_mode
= V2SImode
;
20609 strategy
= info
->savres_strategy
;
20610 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
20611 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
20612 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
20613 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
20614 || rs6000_cpu
== PROCESSOR_PPC603
20615 || rs6000_cpu
== PROCESSOR_PPC750
20617 /* Restore via the backchain when we have a large frame, since this
20618 is more efficient than an addis, addi pair. The second condition
20619 here will not trigger at the moment; We don't actually need a
20620 frame pointer for alloca, but the generic parts of the compiler
20621 give us one anyway. */
20622 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
20623 || (cfun
->calls_alloca
20624 && !frame_pointer_needed
));
20625 restore_lr
= (info
->lr_save_p
20626 && (restoring_FPRs_inline
20627 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
20628 && (restoring_GPRs_inline
20629 || info
->first_fp_reg_save
< 64));
20631 if (WORLD_SAVE_P (info
))
20635 const char *alloc_rname
;
20638 /* eh_rest_world_r10 will return to the location saved in the LR
20639 stack slot (which is not likely to be our caller.)
20640 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20641 rest_world is similar, except any R10 parameter is ignored.
20642 The exception-handling stuff that was here in 2.95 is no
20643 longer necessary. */
20647 + 32 - info
->first_gp_reg_save
20648 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
20649 + 63 + 1 - info
->first_fp_reg_save
);
20651 strcpy (rname
, ((crtl
->calls_eh_return
) ?
20652 "*eh_rest_world_r10" : "*rest_world"));
20653 alloc_rname
= ggc_strdup (rname
);
20656 RTVEC_ELT (p
, j
++) = ret_rtx
;
20657 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
20658 gen_rtx_REG (Pmode
,
20661 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
20662 /* The instruction pattern requires a clobber here;
20663 it is shared with the restVEC helper. */
20665 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
20668 /* CR register traditionally saved as CR2. */
20669 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
20671 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
20672 if (flag_shrink_wrap
)
20674 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20675 gen_rtx_REG (Pmode
, LR_REGNO
),
20677 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20681 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20683 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
20685 = gen_frame_load (reg
,
20686 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
20687 if (flag_shrink_wrap
)
20688 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20690 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
20692 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
20694 = gen_frame_load (reg
,
20695 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
20696 if (flag_shrink_wrap
)
20697 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20699 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
20701 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
20702 ? DFmode
: SFmode
),
20703 info
->first_fp_reg_save
+ i
);
20705 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
20706 if (flag_shrink_wrap
)
20707 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20710 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
20712 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
20714 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
20716 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
20718 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
20719 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20721 if (flag_shrink_wrap
)
20723 REG_NOTES (insn
) = cfa_restores
;
20724 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20725 RTX_FRAME_RELATED_P (insn
) = 1;
20730 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
20732 frame_off
= info
->total_size
;
20734 /* Restore AltiVec registers if we must do so before adjusting the
20736 if (TARGET_ALTIVEC_ABI
20737 && info
->altivec_size
!= 0
20738 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20739 || (DEFAULT_ABI
!= ABI_V4
20740 && offset_below_red_zone_p (info
->altivec_save_offset
))))
20743 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
20745 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
20746 if (use_backchain_to_restore_sp
)
20748 int frame_regno
= 11;
20750 if ((strategy
& REST_INLINE_VRS
) == 0)
20752 /* Of r11 and r12, select the one not clobbered by an
20753 out-of-line restore function for the frame register. */
20754 frame_regno
= 11 + 12 - scratch_regno
;
20756 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
20757 emit_move_insn (frame_reg_rtx
,
20758 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20761 else if (frame_pointer_needed
)
20762 frame_reg_rtx
= hard_frame_pointer_rtx
;
20764 if ((strategy
& REST_INLINE_VRS
) == 0)
20766 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
20768 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
20769 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
20771 if (end_save
+ frame_off
!= 0)
20773 rtx offset
= GEN_INT (end_save
+ frame_off
);
20775 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
20778 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20780 ptr_off
= -end_save
;
20781 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
20782 info
->altivec_save_offset
+ ptr_off
,
20783 0, V4SImode
, SAVRES_VR
);
20787 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20788 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20790 rtx addr
, areg
, mem
, reg
;
20792 areg
= gen_rtx_REG (Pmode
, 0);
20794 (areg
, GEN_INT (info
->altivec_save_offset
20796 + 16 * (i
- info
->first_altivec_reg_save
)));
20798 /* AltiVec addressing mode is [reg+reg]. */
20799 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
20800 mem
= gen_frame_mem (V4SImode
, addr
);
20802 reg
= gen_rtx_REG (V4SImode
, i
);
20803 emit_move_insn (reg
, mem
);
20807 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20808 if (((strategy
& REST_INLINE_VRS
) == 0
20809 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
20810 && (flag_shrink_wrap
20811 || (offset_below_red_zone_p
20812 (info
->altivec_save_offset
20813 + 16 * (i
- info
->first_altivec_reg_save
)))))
20815 rtx reg
= gen_rtx_REG (V4SImode
, i
);
20816 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20820 /* Restore VRSAVE if we must do so before adjusting the stack. */
20822 && TARGET_ALTIVEC_VRSAVE
20823 && info
->vrsave_mask
!= 0
20824 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20825 || (DEFAULT_ABI
!= ABI_V4
20826 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
20830 if (frame_reg_rtx
== sp_reg_rtx
)
20832 if (use_backchain_to_restore_sp
)
20834 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20835 emit_move_insn (frame_reg_rtx
,
20836 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20839 else if (frame_pointer_needed
)
20840 frame_reg_rtx
= hard_frame_pointer_rtx
;
20843 reg
= gen_rtx_REG (SImode
, 12);
20844 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
20845 info
->vrsave_save_offset
+ frame_off
));
20847 emit_insn (generate_set_vrsave (reg
, info
, 1));
20851 /* If we have a large stack frame, restore the old stack pointer
20852 using the backchain. */
20853 if (use_backchain_to_restore_sp
)
20855 if (frame_reg_rtx
== sp_reg_rtx
)
20857 /* Under V.4, don't reset the stack pointer until after we're done
20858 loading the saved registers. */
20859 if (DEFAULT_ABI
== ABI_V4
)
20860 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20862 insn
= emit_move_insn (frame_reg_rtx
,
20863 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20866 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20867 && DEFAULT_ABI
== ABI_V4
)
20868 /* frame_reg_rtx has been set up by the altivec restore. */
20872 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
20873 frame_reg_rtx
= sp_reg_rtx
;
20876 /* If we have a frame pointer, we can restore the old stack pointer
20878 else if (frame_pointer_needed
)
20880 frame_reg_rtx
= sp_reg_rtx
;
20881 if (DEFAULT_ABI
== ABI_V4
)
20882 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20883 /* Prevent reordering memory accesses against stack pointer restore. */
20884 else if (cfun
->calls_alloca
20885 || offset_below_red_zone_p (-info
->total_size
))
20886 rs6000_emit_stack_tie (frame_reg_rtx
, true);
20888 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
20889 GEN_INT (info
->total_size
)));
20892 else if (info
->push_p
20893 && DEFAULT_ABI
!= ABI_V4
20894 && !crtl
->calls_eh_return
)
20896 /* Prevent reordering memory accesses against stack pointer restore. */
20897 if (cfun
->calls_alloca
20898 || offset_below_red_zone_p (-info
->total_size
))
20899 rs6000_emit_stack_tie (frame_reg_rtx
, false);
20900 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
20901 GEN_INT (info
->total_size
)));
20904 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
20908 REG_NOTES (insn
) = cfa_restores
;
20909 cfa_restores
= NULL_RTX
;
20911 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20912 RTX_FRAME_RELATED_P (insn
) = 1;
20915 /* Restore AltiVec registers if we have not done so already. */
20916 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20917 && TARGET_ALTIVEC_ABI
20918 && info
->altivec_size
!= 0
20919 && (DEFAULT_ABI
== ABI_V4
20920 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
20924 if ((strategy
& REST_INLINE_VRS
) == 0)
20926 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
20928 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
20929 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
20930 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
20932 if (end_save
+ frame_off
!= 0)
20934 rtx offset
= GEN_INT (end_save
+ frame_off
);
20936 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
20939 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20941 ptr_off
= -end_save
;
20942 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
20943 info
->altivec_save_offset
+ ptr_off
,
20944 0, V4SImode
, SAVRES_VR
);
20945 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
20947 /* Frame reg was clobbered by out-of-line save. Restore it
20948 from ptr_reg, and if we are calling out-of-line gpr or
20949 fpr restore set up the correct pointer and offset. */
20950 unsigned newptr_regno
= 1;
20951 if (!restoring_GPRs_inline
)
20953 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
20954 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
20955 newptr_regno
= ptr_regno_for_savres (sel
);
20956 end_save
= info
->gp_save_offset
+ info
->gp_size
;
20958 else if (!restoring_FPRs_inline
)
20960 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
20961 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20962 newptr_regno
= ptr_regno_for_savres (sel
);
20963 end_save
= info
->gp_save_offset
+ info
->gp_size
;
20966 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
20967 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
20969 if (end_save
+ ptr_off
!= 0)
20971 rtx offset
= GEN_INT (end_save
+ ptr_off
);
20973 frame_off
= -end_save
;
20974 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
20978 frame_off
= ptr_off
;
20979 emit_move_insn (frame_reg_rtx
, ptr_reg
);
20985 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20986 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20988 rtx addr
, areg
, mem
, reg
;
20990 areg
= gen_rtx_REG (Pmode
, 0);
20992 (areg
, GEN_INT (info
->altivec_save_offset
20994 + 16 * (i
- info
->first_altivec_reg_save
)));
20996 /* AltiVec addressing mode is [reg+reg]. */
20997 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
20998 mem
= gen_frame_mem (V4SImode
, addr
);
21000 reg
= gen_rtx_REG (V4SImode
, i
);
21001 emit_move_insn (reg
, mem
);
21005 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21006 if (((strategy
& REST_INLINE_VRS
) == 0
21007 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
21008 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
21010 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21011 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21015 /* Restore VRSAVE if we have not done so already. */
21016 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21018 && TARGET_ALTIVEC_VRSAVE
21019 && info
->vrsave_mask
!= 0
21020 && (DEFAULT_ABI
== ABI_V4
21021 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
21025 reg
= gen_rtx_REG (SImode
, 12);
21026 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21027 info
->vrsave_save_offset
+ frame_off
));
21029 emit_insn (generate_set_vrsave (reg
, info
, 1));
21032 /* If we exit by an out-of-line restore function on ABI_V4 then that
21033 function will deallocate the stack, so we don't need to worry
21034 about the unwinder restoring cr from an invalid stack frame
21036 exit_func
= (!restoring_FPRs_inline
21037 || (!restoring_GPRs_inline
21038 && info
->first_fp_reg_save
== 64));
21040 /* Get the old lr if we saved it. If we are restoring registers
21041 out-of-line, then the out-of-line routines can do this for us. */
21042 if (restore_lr
&& restoring_GPRs_inline
)
21043 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
21045 /* Get the old cr if we saved it. */
21046 if (info
->cr_save_p
)
21048 unsigned cr_save_regno
= 12;
21050 if (!restoring_GPRs_inline
)
21052 /* Ensure we don't use the register used by the out-of-line
21053 gpr register restore below. */
21054 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
21055 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
21056 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
21058 if (gpr_ptr_regno
== 12)
21059 cr_save_regno
= 11;
21060 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
21062 else if (REGNO (frame_reg_rtx
) == 12)
21063 cr_save_regno
= 11;
21065 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
21066 info
->cr_save_offset
+ frame_off
,
21070 /* Set LR here to try to overlap restores below. */
21071 if (restore_lr
&& restoring_GPRs_inline
)
21072 restore_saved_lr (0, exit_func
);
21074 /* Load exception handler data registers, if needed. */
21075 if (crtl
->calls_eh_return
)
21077 unsigned int i
, regno
;
21081 rtx reg
= gen_rtx_REG (reg_mode
, 2);
21082 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21083 frame_off
+ 5 * reg_size
));
21090 regno
= EH_RETURN_DATA_REGNO (i
);
21091 if (regno
== INVALID_REGNUM
)
21094 /* Note: possible use of r0 here to address SPE regs. */
21095 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
21096 info
->ehrd_offset
+ frame_off
21097 + reg_size
* (int) i
);
21099 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
21103 /* Restore GPRs. This is done as a PARALLEL if we are using
21104 the load-multiple instructions. */
21106 && info
->spe_64bit_regs_used
21107 && info
->first_gp_reg_save
!= 32)
21109 /* Determine whether we can address all of the registers that need
21110 to be saved with an offset from frame_reg_rtx that fits in
21111 the small const field for SPE memory instructions. */
21112 int spe_regs_addressable
21113 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
21114 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
21115 && restoring_GPRs_inline
);
21117 if (!spe_regs_addressable
)
21119 int ool_adjust
= 0;
21120 rtx old_frame_reg_rtx
= frame_reg_rtx
;
21121 /* Make r11 point to the start of the SPE save area. We worried about
21122 not clobbering it when we were saving registers in the prologue.
21123 There's no need to worry here because the static chain is passed
21124 anew to every function. */
21126 if (!restoring_GPRs_inline
)
21127 ool_adjust
= 8 * (info
->first_gp_reg_save
21128 - (FIRST_SAVRES_REGISTER
+ 1));
21129 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
21130 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
21131 GEN_INT (info
->spe_gp_save_offset
21134 /* Keep the invariant that frame_reg_rtx + frame_off points
21135 at the top of the stack frame. */
21136 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
21139 if (restoring_GPRs_inline
)
21141 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
21143 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21144 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21146 rtx offset
, addr
, mem
, reg
;
21148 /* We're doing all this to ensure that the immediate offset
21149 fits into the immediate field of 'evldd'. */
21150 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
21152 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
21153 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
21154 mem
= gen_rtx_MEM (V2SImode
, addr
);
21155 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
21157 emit_move_insn (reg
, mem
);
21161 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
21162 info
->spe_gp_save_offset
+ frame_off
,
21163 info
->lr_save_offset
+ frame_off
,
21165 SAVRES_GPR
| SAVRES_LR
);
21167 else if (!restoring_GPRs_inline
)
21169 /* We are jumping to an out-of-line function. */
21171 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
21172 bool can_use_exit
= end_save
== 0;
21173 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
21176 /* Emit stack reset code if we need it. */
21177 ptr_regno
= ptr_regno_for_savres (sel
);
21178 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21180 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
21181 else if (end_save
+ frame_off
!= 0)
21182 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
21183 GEN_INT (end_save
+ frame_off
)));
21184 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
21185 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21186 if (REGNO (frame_reg_rtx
) == ptr_regno
)
21187 frame_off
= -end_save
;
21189 if (can_use_exit
&& info
->cr_save_p
)
21190 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
21192 ptr_off
= -end_save
;
21193 rs6000_emit_savres_rtx (info
, ptr_reg
,
21194 info
->gp_save_offset
+ ptr_off
,
21195 info
->lr_save_offset
+ ptr_off
,
21198 else if (using_load_multiple
)
21201 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
21202 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21204 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21206 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21207 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21211 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21212 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21213 emit_insn (gen_frame_load
21214 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21216 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
21219 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
21221 /* If the frame pointer was used then we can't delay emitting
21222 a REG_CFA_DEF_CFA note. This must happen on the insn that
21223 restores the frame pointer, r31. We may have already emitted
21224 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
21225 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
21226 be harmless if emitted. */
21227 if (frame_pointer_needed
)
21229 insn
= get_last_insn ();
21230 add_reg_note (insn
, REG_CFA_DEF_CFA
,
21231 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
21232 RTX_FRAME_RELATED_P (insn
) = 1;
21235 /* Set up cfa_restores. We always need these when
21236 shrink-wrapping. If not shrink-wrapping then we only need
21237 the cfa_restore when the stack location is no longer valid.
21238 The cfa_restores must be emitted on or before the insn that
21239 invalidates the stack, and of course must not be emitted
21240 before the insn that actually does the restore. The latter
21241 is why it is a bad idea to emit the cfa_restores as a group
21242 on the last instruction here that actually does a restore:
21243 That insn may be reordered with respect to others doing
21245 if (flag_shrink_wrap
21246 && !restoring_GPRs_inline
21247 && info
->first_fp_reg_save
== 64)
21248 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
21250 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
21251 if (!restoring_GPRs_inline
21252 || using_load_multiple
21253 || rs6000_reg_live_or_pic_offset_p (i
))
21255 rtx reg
= gen_rtx_REG (reg_mode
, i
);
21257 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21261 if (!restoring_GPRs_inline
21262 && info
->first_fp_reg_save
== 64)
21264 /* We are jumping to an out-of-line function. */
21266 emit_cfa_restores (cfa_restores
);
21270 if (restore_lr
&& !restoring_GPRs_inline
)
21272 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
21273 restore_saved_lr (0, exit_func
);
21276 /* Restore fpr's if we need to do it without calling a function. */
21277 if (restoring_FPRs_inline
)
21278 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21279 if (save_reg_p (info
->first_fp_reg_save
+ i
))
21281 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21282 ? DFmode
: SFmode
),
21283 info
->first_fp_reg_save
+ i
);
21284 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21285 info
->fp_save_offset
+ frame_off
+ 8 * i
));
21286 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
21287 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21290 /* If we saved cr, restore it here. Just those that were used. */
21291 if (info
->cr_save_p
)
21292 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
21294 /* If this is V.4, unwind the stack pointer after all of the loads
21295 have been done, or set up r11 if we are restoring fp out of line. */
21297 if (!restoring_FPRs_inline
)
21299 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
21300 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21301 ptr_regno
= ptr_regno_for_savres (sel
);
21304 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
21305 if (REGNO (frame_reg_rtx
) == ptr_regno
)
21308 if (insn
&& restoring_FPRs_inline
)
21312 REG_NOTES (insn
) = cfa_restores
;
21313 cfa_restores
= NULL_RTX
;
21315 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
21316 RTX_FRAME_RELATED_P (insn
) = 1;
21319 if (crtl
->calls_eh_return
)
21321 rtx sa
= EH_RETURN_STACKADJ_RTX
;
21322 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
21328 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
21329 if (! restoring_FPRs_inline
)
21331 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
21332 RTVEC_ELT (p
, 0) = ret_rtx
;
21338 /* We can't hang the cfa_restores off a simple return,
21339 since the shrink-wrap code sometimes uses an existing
21340 return. This means there might be a path from
21341 pre-prologue code to this return, and dwarf2cfi code
21342 wants the eh_frame unwinder state to be the same on
21343 all paths to any point. So we need to emit the
21344 cfa_restores before the return. For -m64 we really
21345 don't need epilogue cfa_restores at all, except for
21346 this irritating dwarf2cfi with shrink-wrap
21347 requirement; The stack red-zone means eh_frame info
21348 from the prologue telling the unwinder to restore
21349 from the stack is perfectly good right to the end of
21351 emit_insn (gen_blockage ());
21352 emit_cfa_restores (cfa_restores
);
21353 cfa_restores
= NULL_RTX
;
21355 p
= rtvec_alloc (2);
21356 RTVEC_ELT (p
, 0) = simple_return_rtx
;
21359 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
21360 ? gen_rtx_USE (VOIDmode
,
21361 gen_rtx_REG (Pmode
, LR_REGNO
))
21362 : gen_rtx_CLOBBER (VOIDmode
,
21363 gen_rtx_REG (Pmode
, LR_REGNO
)));
21365 /* If we have to restore more than two FP registers, branch to the
21366 restore function. It will return to our caller. */
21367 if (! restoring_FPRs_inline
)
21372 if (flag_shrink_wrap
)
21373 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
21375 sym
= rs6000_savres_routine_sym (info
,
21376 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
21377 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
21378 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
21379 gen_rtx_REG (Pmode
,
21380 DEFAULT_ABI
== ABI_AIX
21382 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21384 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
21386 RTVEC_ELT (p
, i
+ 4)
21387 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
21388 if (flag_shrink_wrap
)
21389 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
21394 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21400 /* Ensure the cfa_restores are hung off an insn that won't
21401 be reordered above other restores. */
21402 emit_insn (gen_blockage ());
21404 emit_cfa_restores (cfa_restores
);
21408 /* Write function epilogue. */
21411 rs6000_output_function_epilogue (FILE *file
,
21412 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
21415 macho_branch_islands ();
21416 /* Mach-O doesn't support labels at the end of objects, so if
21417 it looks like we might want one, insert a NOP. */
21419 rtx insn
= get_last_insn ();
21420 rtx deleted_debug_label
= NULL_RTX
;
21423 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
21425 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
21426 notes only, instead set their CODE_LABEL_NUMBER to -1,
21427 otherwise there would be code generation differences
21428 in between -g and -g0. */
21429 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
21430 deleted_debug_label
= insn
;
21431 insn
= PREV_INSN (insn
);
21436 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
21437 fputs ("\tnop\n", file
);
21438 else if (deleted_debug_label
)
21439 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
21440 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
21441 CODE_LABEL_NUMBER (insn
) = -1;
21445 /* Output a traceback table here. See /usr/include/sys/debug.h for info
21448 We don't output a traceback table if -finhibit-size-directive was
21449 used. The documentation for -finhibit-size-directive reads
21450 ``don't output a @code{.size} assembler directive, or anything
21451 else that would cause trouble if the function is split in the
21452 middle, and the two halves are placed at locations far apart in
21453 memory.'' The traceback table has this property, since it
21454 includes the offset from the start of the function to the
21455 traceback table itself.
21457 System V.4 Powerpc's (and the embedded ABI derived from it) use a
21458 different traceback table. */
21459 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
21460 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
21462 const char *fname
= NULL
;
21463 const char *language_string
= lang_hooks
.name
;
21464 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
21466 int optional_tbtab
;
21467 rs6000_stack_t
*info
= rs6000_stack_info ();
21469 if (rs6000_traceback
== traceback_full
)
21470 optional_tbtab
= 1;
21471 else if (rs6000_traceback
== traceback_part
)
21472 optional_tbtab
= 0;
21474 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
21476 if (optional_tbtab
)
21478 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
21479 while (*fname
== '.') /* V.4 encodes . in the name */
21482 /* Need label immediately before tbtab, so we can compute
21483 its offset from the function start. */
21484 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
21485 ASM_OUTPUT_LABEL (file
, fname
);
21488 /* The .tbtab pseudo-op can only be used for the first eight
21489 expressions, since it can't handle the possibly variable
21490 length fields that follow. However, if you omit the optional
21491 fields, the assembler outputs zeros for all optional fields
21492 anyways, giving each variable length field is minimum length
21493 (as defined in sys/debug.h). Thus we can not use the .tbtab
21494 pseudo-op at all. */
21496 /* An all-zero word flags the start of the tbtab, for debuggers
21497 that have to find it by searching forward from the entry
21498 point or from the current pc. */
21499 fputs ("\t.long 0\n", file
);
21501 /* Tbtab format type. Use format type 0. */
21502 fputs ("\t.byte 0,", file
);
21504 /* Language type. Unfortunately, there does not seem to be any
21505 official way to discover the language being compiled, so we
21506 use language_string.
21507 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21508 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21509 a number, so for now use 9. LTO and Go aren't assigned numbers
21510 either, so for now use 0. */
21511 if (! strcmp (language_string
, "GNU C")
21512 || ! strcmp (language_string
, "GNU GIMPLE")
21513 || ! strcmp (language_string
, "GNU Go"))
21515 else if (! strcmp (language_string
, "GNU F77")
21516 || ! strcmp (language_string
, "GNU Fortran"))
21518 else if (! strcmp (language_string
, "GNU Pascal"))
21520 else if (! strcmp (language_string
, "GNU Ada"))
21522 else if (! strcmp (language_string
, "GNU C++")
21523 || ! strcmp (language_string
, "GNU Objective-C++"))
21525 else if (! strcmp (language_string
, "GNU Java"))
21527 else if (! strcmp (language_string
, "GNU Objective-C"))
21530 gcc_unreachable ();
21531 fprintf (file
, "%d,", i
);
21533 /* 8 single bit fields: global linkage (not set for C extern linkage,
21534 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21535 from start of procedure stored in tbtab, internal function, function
21536 has controlled storage, function has no toc, function uses fp,
21537 function logs/aborts fp operations. */
21538 /* Assume that fp operations are used if any fp reg must be saved. */
21539 fprintf (file
, "%d,",
21540 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
21542 /* 6 bitfields: function is interrupt handler, name present in
21543 proc table, function calls alloca, on condition directives
21544 (controls stack walks, 3 bits), saves condition reg, saves
21546 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21547 set up as a frame pointer, even when there is no alloca call. */
21548 fprintf (file
, "%d,",
21549 ((optional_tbtab
<< 6)
21550 | ((optional_tbtab
& frame_pointer_needed
) << 5)
21551 | (info
->cr_save_p
<< 1)
21552 | (info
->lr_save_p
)));
21554 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21556 fprintf (file
, "%d,",
21557 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
21559 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21560 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
21562 if (optional_tbtab
)
21564 /* Compute the parameter info from the function decl argument
21567 int next_parm_info_bit
= 31;
21569 for (decl
= DECL_ARGUMENTS (current_function_decl
);
21570 decl
; decl
= DECL_CHAIN (decl
))
21572 rtx parameter
= DECL_INCOMING_RTL (decl
);
21573 enum machine_mode mode
= GET_MODE (parameter
);
21575 if (GET_CODE (parameter
) == REG
)
21577 if (SCALAR_FLOAT_MODE_P (mode
))
21598 gcc_unreachable ();
21601 /* If only one bit will fit, don't or in this entry. */
21602 if (next_parm_info_bit
> 0)
21603 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
21604 next_parm_info_bit
-= 2;
21608 fixed_parms
+= ((GET_MODE_SIZE (mode
)
21609 + (UNITS_PER_WORD
- 1))
21611 next_parm_info_bit
-= 1;
21617 /* Number of fixed point parameters. */
21618 /* This is actually the number of words of fixed point parameters; thus
21619 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21620 fprintf (file
, "%d,", fixed_parms
);
21622 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21624 /* This is actually the number of fp registers that hold parameters;
21625 and thus the maximum value is 13. */
21626 /* Set parameters on stack bit if parameters are not in their original
21627 registers, regardless of whether they are on the stack? Xlc
21628 seems to set the bit when not optimizing. */
21629 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
21631 if (! optional_tbtab
)
21634 /* Optional fields follow. Some are variable length. */
21636 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21637 11 double float. */
21638 /* There is an entry for each parameter in a register, in the order that
21639 they occur in the parameter list. Any intervening arguments on the
21640 stack are ignored. If the list overflows a long (max possible length
21641 34 bits) then completely leave off all elements that don't fit. */
21642 /* Only emit this long if there was at least one parameter. */
21643 if (fixed_parms
|| float_parms
)
21644 fprintf (file
, "\t.long %d\n", parm_info
);
21646 /* Offset from start of code to tb table. */
21647 fputs ("\t.long ", file
);
21648 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
21649 RS6000_OUTPUT_BASENAME (file
, fname
);
21651 rs6000_output_function_entry (file
, fname
);
21654 /* Interrupt handler mask. */
21655 /* Omit this long, since we never set the interrupt handler bit
21658 /* Number of CTL (controlled storage) anchors. */
21659 /* Omit this long, since the has_ctl bit is never set above. */
21661 /* Displacement into stack of each CTL anchor. */
21662 /* Omit this list of longs, because there are no CTL anchors. */
21664 /* Length of function name. */
21667 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
21669 /* Function name. */
21670 assemble_string (fname
, strlen (fname
));
21672 /* Register for alloca automatic storage; this is always reg 31.
21673 Only emit this if the alloca bit was set above. */
21674 if (frame_pointer_needed
)
21675 fputs ("\t.byte 31\n", file
);
21677 fputs ("\t.align 2\n", file
);
21681 /* A C compound statement that outputs the assembler code for a thunk
21682 function, used to implement C++ virtual function calls with
21683 multiple inheritance. The thunk acts as a wrapper around a virtual
21684 function, adjusting the implicit object parameter before handing
21685 control off to the real function.
21687 First, emit code to add the integer DELTA to the location that
21688 contains the incoming first argument. Assume that this argument
21689 contains a pointer, and is the one used to pass the `this' pointer
21690 in C++. This is the incoming argument *before* the function
21691 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21692 values of all other incoming arguments.
21694 After the addition, emit code to jump to FUNCTION, which is a
21695 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21696 not touch the return address. Hence returning from FUNCTION will
21697 return to whoever called the current `thunk'.
21699 The effect must be as if FUNCTION had been called directly with the
21700 adjusted first argument. This macro is responsible for emitting
21701 all of the code for a thunk function; output_function_prologue()
21702 and output_function_epilogue() are not invoked.
21704 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21705 been extracted from it.) It might possibly be useful on some
21706 targets, but probably not.
21708 If you do not define this macro, the target-independent code in the
21709 C++ frontend will generate a less efficient heavyweight thunk that
21710 calls FUNCTION instead of jumping to it. The generic approach does
21711 not support varargs. */
21714 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
21715 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
21718 rtx this_rtx
, insn
, funexp
;
21720 reload_completed
= 1;
21721 epilogue_completed
= 1;
21723 /* Mark the end of the (empty) prologue. */
21724 emit_note (NOTE_INSN_PROLOGUE_END
);
21726 /* Find the "this" pointer. If the function returns a structure,
21727 the structure return pointer is in r3. */
21728 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
21729 this_rtx
= gen_rtx_REG (Pmode
, 4);
21731 this_rtx
= gen_rtx_REG (Pmode
, 3);
21733 /* Apply the constant offset, if required. */
21735 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
21737 /* Apply the offset from the vtable, if required. */
21740 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
21741 rtx tmp
= gen_rtx_REG (Pmode
, 12);
21743 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
21744 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
21746 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
21747 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
21751 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
21753 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
21755 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
21758 /* Generate a tail call to the target function. */
21759 if (!TREE_USED (function
))
21761 assemble_external (function
);
21762 TREE_USED (function
) = 1;
21764 funexp
= XEXP (DECL_RTL (function
), 0);
21765 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
21768 if (MACHOPIC_INDIRECT
)
21769 funexp
= machopic_indirect_call_target (funexp
);
21772 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21773 generate sibcall RTL explicitly. */
21774 insn
= emit_call_insn (
21775 gen_rtx_PARALLEL (VOIDmode
,
21777 gen_rtx_CALL (VOIDmode
,
21778 funexp
, const0_rtx
),
21779 gen_rtx_USE (VOIDmode
, const0_rtx
),
21780 gen_rtx_USE (VOIDmode
,
21781 gen_rtx_REG (SImode
,
21783 simple_return_rtx
)));
21784 SIBLING_CALL_P (insn
) = 1;
21787 /* Run just enough of rest_of_compilation to get the insns emitted.
21788 There's not really enough bulk here to make other passes such as
21789 instruction scheduling worth while. Note that use_thunk calls
21790 assemble_start_function and assemble_end_function. */
21791 insn
= get_insns ();
21792 shorten_branches (insn
);
21793 final_start_function (insn
, file
, 1);
21794 final (insn
, file
, 1);
21795 final_end_function ();
21797 reload_completed
= 0;
21798 epilogue_completed
= 0;
21801 /* A quick summary of the various types of 'constant-pool tables'
21804 Target Flags Name One table per
21805 AIX (none) AIX TOC object file
21806 AIX -mfull-toc AIX TOC object file
21807 AIX -mminimal-toc AIX minimal TOC translation unit
21808 SVR4/EABI (none) SVR4 SDATA object file
21809 SVR4/EABI -fpic SVR4 pic object file
21810 SVR4/EABI -fPIC SVR4 PIC translation unit
21811 SVR4/EABI -mrelocatable EABI TOC function
21812 SVR4/EABI -maix AIX TOC object file
21813 SVR4/EABI -maix -mminimal-toc
21814 AIX minimal TOC translation unit
21816 Name Reg. Set by entries contains:
21817 made by addrs? fp? sum?
21819 AIX TOC 2 crt0 as Y option option
21820 AIX minimal TOC 30 prolog gcc Y Y option
21821 SVR4 SDATA 13 crt0 gcc N Y N
21822 SVR4 pic 30 prolog ld Y not yet N
21823 SVR4 PIC 30 prolog gcc Y option option
21824 EABI TOC 30 prolog gcc Y option option
21828 /* Hash functions for the hash table. */
21831 rs6000_hash_constant (rtx k
)
21833 enum rtx_code code
= GET_CODE (k
);
21834 enum machine_mode mode
= GET_MODE (k
);
21835 unsigned result
= (code
<< 3) ^ mode
;
21836 const char *format
;
21839 format
= GET_RTX_FORMAT (code
);
21840 flen
= strlen (format
);
21846 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
21849 if (mode
!= VOIDmode
)
21850 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
21862 for (; fidx
< flen
; fidx
++)
21863 switch (format
[fidx
])
21868 const char *str
= XSTR (k
, fidx
);
21869 len
= strlen (str
);
21870 result
= result
* 613 + len
;
21871 for (i
= 0; i
< len
; i
++)
21872 result
= result
* 613 + (unsigned) str
[i
];
21877 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
21881 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
21884 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
21885 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
21889 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
21890 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
21897 gcc_unreachable ();
21904 toc_hash_function (const void *hash_entry
)
21906 const struct toc_hash_struct
*thc
=
21907 (const struct toc_hash_struct
*) hash_entry
;
21908 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
21911 /* Compare H1 and H2 for equivalence. */
21914 toc_hash_eq (const void *h1
, const void *h2
)
21916 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
21917 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
21919 if (((const struct toc_hash_struct
*) h1
)->key_mode
21920 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
21923 return rtx_equal_p (r1
, r2
);
21926 /* These are the names given by the C++ front-end to vtables, and
21927 vtable-like objects. Ideally, this logic should not be here;
21928 instead, there should be some programmatic way of inquiring as
21929 to whether or not an object is a vtable. */
21931 #define VTABLE_NAME_P(NAME) \
21932 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21933 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21934 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21935 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21936 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21938 #ifdef NO_DOLLAR_IN_LABEL
21939 /* Return a GGC-allocated character string translating dollar signs in
21940 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21943 rs6000_xcoff_strip_dollar (const char *name
)
21949 q
= (const char *) strchr (name
, '$');
21951 if (q
== 0 || q
== name
)
21954 len
= strlen (name
);
21955 strip
= XALLOCAVEC (char, len
+ 1);
21956 strcpy (strip
, name
);
21957 p
= strip
+ (q
- name
);
21961 p
= strchr (p
+ 1, '$');
21964 return ggc_alloc_string (strip
, len
);
21969 rs6000_output_symbol_ref (FILE *file
, rtx x
)
21971 /* Currently C++ toc references to vtables can be emitted before it
21972 is decided whether the vtable is public or private. If this is
21973 the case, then the linker will eventually complain that there is
21974 a reference to an unknown section. Thus, for vtables only,
21975 we emit the TOC reference to reference the symbol and not the
21977 const char *name
= XSTR (x
, 0);
21979 if (VTABLE_NAME_P (name
))
21981 RS6000_OUTPUT_BASENAME (file
, name
);
21984 assemble_name (file
, name
);
21987 /* Output a TOC entry. We derive the entry name from what is being
21991 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
21994 const char *name
= buf
;
21996 HOST_WIDE_INT offset
= 0;
21998 gcc_assert (!TARGET_NO_TOC
);
22000 /* When the linker won't eliminate them, don't output duplicate
22001 TOC entries (this happens on AIX if there is any kind of TOC,
22002 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
22004 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
22006 struct toc_hash_struct
*h
;
22009 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
22010 time because GGC is not initialized at that point. */
22011 if (toc_hash_table
== NULL
)
22012 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
22013 toc_hash_eq
, NULL
);
22015 h
= ggc_alloc_toc_hash_struct ();
22017 h
->key_mode
= mode
;
22018 h
->labelno
= labelno
;
22020 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
22021 if (*found
== NULL
)
22023 else /* This is indeed a duplicate.
22024 Set this label equal to that label. */
22026 fputs ("\t.set ", file
);
22027 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
22028 fprintf (file
, "%d,", labelno
);
22029 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
22030 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
22034 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
22035 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
22036 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
22038 fputs ("\t.set ", file
);
22039 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
22040 fprintf (file
, "%d,", labelno
);
22041 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
22042 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
22050 /* If we're going to put a double constant in the TOC, make sure it's
22051 aligned properly when strict alignment is on. */
22052 if (GET_CODE (x
) == CONST_DOUBLE
22053 && STRICT_ALIGNMENT
22054 && GET_MODE_BITSIZE (mode
) >= 64
22055 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
22056 ASM_OUTPUT_ALIGN (file
, 3);
22059 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
22061 /* Handle FP constants specially. Note that if we have a minimal
22062 TOC, things we put here aren't actually in the TOC, so we can allow
22064 if (GET_CODE (x
) == CONST_DOUBLE
&&
22065 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
22067 REAL_VALUE_TYPE rv
;
22070 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
22071 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
22072 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
22074 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
22078 if (TARGET_MINIMAL_TOC
)
22079 fputs (DOUBLE_INT_ASM_OP
, file
);
22081 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22082 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22083 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22084 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
22085 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22086 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22091 if (TARGET_MINIMAL_TOC
)
22092 fputs ("\t.long ", file
);
22094 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22095 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22096 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22097 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
22098 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22099 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22103 else if (GET_CODE (x
) == CONST_DOUBLE
&&
22104 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
22106 REAL_VALUE_TYPE rv
;
22109 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
22111 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
22112 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
22114 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
22118 if (TARGET_MINIMAL_TOC
)
22119 fputs (DOUBLE_INT_ASM_OP
, file
);
22121 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
22122 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22123 fprintf (file
, "0x%lx%08lx\n",
22124 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22129 if (TARGET_MINIMAL_TOC
)
22130 fputs ("\t.long ", file
);
22132 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
22133 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22134 fprintf (file
, "0x%lx,0x%lx\n",
22135 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22139 else if (GET_CODE (x
) == CONST_DOUBLE
&&
22140 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
22142 REAL_VALUE_TYPE rv
;
22145 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
22146 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
22147 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
22149 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
22153 if (TARGET_MINIMAL_TOC
)
22154 fputs (DOUBLE_INT_ASM_OP
, file
);
22156 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
22157 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
22162 if (TARGET_MINIMAL_TOC
)
22163 fputs ("\t.long ", file
);
22165 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
22166 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
22170 else if (GET_MODE (x
) == VOIDmode
22171 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
22173 unsigned HOST_WIDE_INT low
;
22174 HOST_WIDE_INT high
;
22176 if (GET_CODE (x
) == CONST_DOUBLE
)
22178 low
= CONST_DOUBLE_LOW (x
);
22179 high
= CONST_DOUBLE_HIGH (x
);
22182 #if HOST_BITS_PER_WIDE_INT == 32
22185 high
= (low
& 0x80000000) ? ~0 : 0;
22189 low
= INTVAL (x
) & 0xffffffff;
22190 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
22194 /* TOC entries are always Pmode-sized, but since this
22195 is a bigendian machine then if we're putting smaller
22196 integer constants in the TOC we have to pad them.
22197 (This is still a win over putting the constants in
22198 a separate constant pool, because then we'd have
22199 to have both a TOC entry _and_ the actual constant.)
22201 For a 32-bit target, CONST_INT values are loaded and shifted
22202 entirely within `low' and can be stored in one TOC entry. */
22204 /* It would be easy to make this work, but it doesn't now. */
22205 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
22207 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
22209 #if HOST_BITS_PER_WIDE_INT == 32
22210 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
22211 POINTER_SIZE
, &low
, &high
, 0);
22214 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
22215 high
= (HOST_WIDE_INT
) low
>> 32;
22222 if (TARGET_MINIMAL_TOC
)
22223 fputs (DOUBLE_INT_ASM_OP
, file
);
22225 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
22226 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22227 fprintf (file
, "0x%lx%08lx\n",
22228 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22233 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
22235 if (TARGET_MINIMAL_TOC
)
22236 fputs ("\t.long ", file
);
22238 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
22239 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22240 fprintf (file
, "0x%lx,0x%lx\n",
22241 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22245 if (TARGET_MINIMAL_TOC
)
22246 fputs ("\t.long ", file
);
22248 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
22249 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
22255 if (GET_CODE (x
) == CONST
)
22257 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
22258 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
22260 base
= XEXP (XEXP (x
, 0), 0);
22261 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
22264 switch (GET_CODE (base
))
22267 name
= XSTR (base
, 0);
22271 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
22272 CODE_LABEL_NUMBER (XEXP (base
, 0)));
22276 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
22280 gcc_unreachable ();
22283 if (TARGET_MINIMAL_TOC
)
22284 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
22287 fputs ("\t.tc ", file
);
22288 RS6000_OUTPUT_BASENAME (file
, name
);
22291 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
22293 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
22295 /* Mark large TOC symbols on AIX with [TE] so they are mapped
22296 after other TOC symbols, reducing overflow of small TOC access
22297 to [TC] symbols. */
22298 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
22299 ? "[TE]," : "[TC],", file
);
22302 /* Currently C++ toc references to vtables can be emitted before it
22303 is decided whether the vtable is public or private. If this is
22304 the case, then the linker will eventually complain that there is
22305 a TOC reference to an unknown section. Thus, for vtables only,
22306 we emit the TOC reference to reference the symbol and not the
22308 if (VTABLE_NAME_P (name
))
22310 RS6000_OUTPUT_BASENAME (file
, name
);
22312 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
22313 else if (offset
> 0)
22314 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
22317 output_addr_const (file
, x
);
22320 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
22321 && SYMBOL_REF_TLS_MODEL (base
) != 0)
22323 tree decl
= SYMBOL_REF_DECL (base
);
22324 if (bss_initializer_p (decl
))
22325 fputs ("[UL]", file
);
22327 fputs ("[TL]", file
);
22329 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
22330 fputs ("@le", file
);
22331 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
22332 fputs ("@ie", file
);
22333 /* Use global-dynamic for local-dynamic. */
22334 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
22335 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
22338 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
22339 fputs ("\t.tc .", file
);
22340 RS6000_OUTPUT_BASENAME (file
, name
);
22341 fputs ("[TC],", file
);
22342 output_addr_const (file
, x
);
22343 if (TREE_PUBLIC (SYMBOL_REF_DECL (base
)))
22344 fputs ("[TL]@m", file
);
22346 fputs ("[UL]@m", file
);
22354 /* Output an assembler pseudo-op to write an ASCII string of N characters
22355 starting at P to FILE.
22357 On the RS/6000, we have to do this using the .byte operation and
22358 write out special characters outside the quoted string.
22359 Also, the assembler is broken; very long strings are truncated,
22360 so we must artificially break them up early. */
22363 output_ascii (FILE *file
, const char *p
, int n
)
22366 int i
, count_string
;
22367 const char *for_string
= "\t.byte \"";
22368 const char *for_decimal
= "\t.byte ";
22369 const char *to_close
= NULL
;
22372 for (i
= 0; i
< n
; i
++)
22375 if (c
>= ' ' && c
< 0177)
22378 fputs (for_string
, file
);
22381 /* Write two quotes to get one. */
22389 for_decimal
= "\"\n\t.byte ";
22393 if (count_string
>= 512)
22395 fputs (to_close
, file
);
22397 for_string
= "\t.byte \"";
22398 for_decimal
= "\t.byte ";
22406 fputs (for_decimal
, file
);
22407 fprintf (file
, "%d", c
);
22409 for_string
= "\n\t.byte \"";
22410 for_decimal
= ", ";
22416 /* Now close the string if we have written one. Then end the line. */
22418 fputs (to_close
, file
);
22421 /* Generate a unique section name for FILENAME for a section type
22422 represented by SECTION_DESC. Output goes into BUF.
22424 SECTION_DESC can be any string, as long as it is different for each
22425 possible section type.
22427 We name the section in the same manner as xlc. The name begins with an
22428 underscore followed by the filename (after stripping any leading directory
22429 names) with the last period replaced by the string SECTION_DESC. If
22430 FILENAME does not contain a period, SECTION_DESC is appended to the end of
22434 rs6000_gen_section_name (char **buf
, const char *filename
,
22435 const char *section_desc
)
22437 const char *q
, *after_last_slash
, *last_period
= 0;
22441 after_last_slash
= filename
;
22442 for (q
= filename
; *q
; q
++)
22445 after_last_slash
= q
+ 1;
22446 else if (*q
== '.')
22450 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
22451 *buf
= (char *) xmalloc (len
);
22456 for (q
= after_last_slash
; *q
; q
++)
22458 if (q
== last_period
)
22460 strcpy (p
, section_desc
);
22461 p
+= strlen (section_desc
);
22465 else if (ISALNUM (*q
))
22469 if (last_period
== 0)
22470 strcpy (p
, section_desc
);
22475 /* Emit profile function. */
22478 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
22480 /* Non-standard profiling for kernels, which just saves LR then calls
22481 _mcount without worrying about arg saves. The idea is to change
22482 the function prologue as little as possible as it isn't easy to
22483 account for arg save/restore code added just for _mcount. */
22484 if (TARGET_PROFILE_KERNEL
)
22487 if (DEFAULT_ABI
== ABI_AIX
)
22489 #ifndef NO_PROFILE_COUNTERS
22490 # define NO_PROFILE_COUNTERS 0
22492 if (NO_PROFILE_COUNTERS
)
22493 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
22494 LCT_NORMAL
, VOIDmode
, 0);
22498 const char *label_name
;
22501 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
22502 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
22503 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
22505 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
22506 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
22509 else if (DEFAULT_ABI
== ABI_DARWIN
)
22511 const char *mcount_name
= RS6000_MCOUNT
;
22512 int caller_addr_regno
= LR_REGNO
;
22514 /* Be conservative and always set this, at least for now. */
22515 crtl
->uses_pic_offset_table
= 1;
22518 /* For PIC code, set up a stub and collect the caller's address
22519 from r0, which is where the prologue puts it. */
22520 if (MACHOPIC_INDIRECT
22521 && crtl
->uses_pic_offset_table
)
22522 caller_addr_regno
= 0;
22524 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
22525 LCT_NORMAL
, VOIDmode
, 1,
22526 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
22530 /* Write function profiler code. */
22533 output_function_profiler (FILE *file
, int labelno
)
22537 switch (DEFAULT_ABI
)
22540 gcc_unreachable ();
22545 warning (0, "no profiling of 64-bit code for this ABI");
22548 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
22549 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
22550 if (NO_PROFILE_COUNTERS
)
22552 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22553 reg_names
[0], reg_names
[1]);
22555 else if (TARGET_SECURE_PLT
&& flag_pic
)
22557 if (TARGET_LINK_STACK
)
22560 get_ppc476_thunk_name (name
);
22561 asm_fprintf (file
, "\tbl %s\n", name
);
22564 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
22565 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22566 reg_names
[0], reg_names
[1]);
22567 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
22568 asm_fprintf (file
, "\taddis %s,%s,",
22569 reg_names
[12], reg_names
[12]);
22570 assemble_name (file
, buf
);
22571 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
22572 assemble_name (file
, buf
);
22573 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
22575 else if (flag_pic
== 1)
22577 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
22578 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22579 reg_names
[0], reg_names
[1]);
22580 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
22581 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
22582 assemble_name (file
, buf
);
22583 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
22585 else if (flag_pic
> 1)
22587 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22588 reg_names
[0], reg_names
[1]);
22589 /* Now, we need to get the address of the label. */
22590 if (TARGET_LINK_STACK
)
22593 get_ppc476_thunk_name (name
);
22594 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
22595 assemble_name (file
, buf
);
22596 fputs ("-.\n1:", file
);
22597 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
22598 asm_fprintf (file
, "\taddi %s,%s,4\n",
22599 reg_names
[11], reg_names
[11]);
22603 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
22604 assemble_name (file
, buf
);
22605 fputs ("-.\n1:", file
);
22606 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
22608 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
22609 reg_names
[0], reg_names
[11]);
22610 asm_fprintf (file
, "\tadd %s,%s,%s\n",
22611 reg_names
[0], reg_names
[0], reg_names
[11]);
22615 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
22616 assemble_name (file
, buf
);
22617 fputs ("@ha\n", file
);
22618 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22619 reg_names
[0], reg_names
[1]);
22620 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
22621 assemble_name (file
, buf
);
22622 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
22625 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22626 fprintf (file
, "\tbl %s%s\n",
22627 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
22632 if (!TARGET_PROFILE_KERNEL
)
22634 /* Don't do anything, done in output_profile_hook (). */
22638 gcc_assert (!TARGET_32BIT
);
22640 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
22641 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
22643 if (cfun
->static_chain_decl
!= NULL
)
22645 asm_fprintf (file
, "\tstd %s,24(%s)\n",
22646 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
22647 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
22648 asm_fprintf (file
, "\tld %s,24(%s)\n",
22649 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
22652 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
22660 /* The following variable value is the last issued insn. */
22662 static rtx last_scheduled_insn
;
22664 /* The following variable helps to balance issuing of load and
22665 store instructions */
22667 static int load_store_pendulum
;
22669 /* Power4 load update and store update instructions are cracked into a
22670 load or store and an integer insn which are executed in the same cycle.
22671 Branches have their own dispatch slot which does not count against the
22672 GCC issue rate, but it changes the program flow so there are no other
22673 instructions to issue in this cycle. */
22676 rs6000_variable_issue_1 (rtx insn
, int more
)
22678 last_scheduled_insn
= insn
;
22679 if (GET_CODE (PATTERN (insn
)) == USE
22680 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22682 cached_can_issue_more
= more
;
22683 return cached_can_issue_more
;
22686 if (insn_terminates_group_p (insn
, current_group
))
22688 cached_can_issue_more
= 0;
22689 return cached_can_issue_more
;
22692 /* If no reservation, but reach here */
22693 if (recog_memoized (insn
) < 0)
22696 if (rs6000_sched_groups
)
22698 if (is_microcoded_insn (insn
))
22699 cached_can_issue_more
= 0;
22700 else if (is_cracked_insn (insn
))
22701 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
22703 cached_can_issue_more
= more
- 1;
22705 return cached_can_issue_more
;
22708 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
22711 cached_can_issue_more
= more
- 1;
22712 return cached_can_issue_more
;
22716 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
22718 int r
= rs6000_variable_issue_1 (insn
, more
);
22720 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
22724 /* Adjust the cost of a scheduling dependency. Return the new cost of
22725 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22728 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
22730 enum attr_type attr_type
;
22732 if (! recog_memoized (insn
))
22735 switch (REG_NOTE_KIND (link
))
22739 /* Data dependency; DEP_INSN writes a register that INSN reads
22740 some cycles later. */
22742 /* Separate a load from a narrower, dependent store. */
22743 if (rs6000_sched_groups
22744 && GET_CODE (PATTERN (insn
)) == SET
22745 && GET_CODE (PATTERN (dep_insn
)) == SET
22746 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
22747 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
22748 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
22749 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
22752 attr_type
= get_attr_type (insn
);
22757 /* Tell the first scheduling pass about the latency between
22758 a mtctr and bctr (and mtlr and br/blr). The first
22759 scheduling pass will not know about this latency since
22760 the mtctr instruction, which has the latency associated
22761 to it, will be generated by reload. */
22764 /* Leave some extra cycles between a compare and its
22765 dependent branch, to inhibit expensive mispredicts. */
22766 if ((rs6000_cpu_attr
== CPU_PPC603
22767 || rs6000_cpu_attr
== CPU_PPC604
22768 || rs6000_cpu_attr
== CPU_PPC604E
22769 || rs6000_cpu_attr
== CPU_PPC620
22770 || rs6000_cpu_attr
== CPU_PPC630
22771 || rs6000_cpu_attr
== CPU_PPC750
22772 || rs6000_cpu_attr
== CPU_PPC7400
22773 || rs6000_cpu_attr
== CPU_PPC7450
22774 || rs6000_cpu_attr
== CPU_PPCE5500
22775 || rs6000_cpu_attr
== CPU_PPCE6500
22776 || rs6000_cpu_attr
== CPU_POWER4
22777 || rs6000_cpu_attr
== CPU_POWER5
22778 || rs6000_cpu_attr
== CPU_POWER7
22779 || rs6000_cpu_attr
== CPU_CELL
)
22780 && recog_memoized (dep_insn
)
22781 && (INSN_CODE (dep_insn
) >= 0))
22783 switch (get_attr_type (dep_insn
))
22787 case TYPE_DELAYED_COMPARE
:
22788 case TYPE_IMUL_COMPARE
:
22789 case TYPE_LMUL_COMPARE
:
22790 case TYPE_FPCOMPARE
:
22791 case TYPE_CR_LOGICAL
:
22792 case TYPE_DELAYED_CR
:
22801 case TYPE_STORE_UX
:
22803 case TYPE_FPSTORE_U
:
22804 case TYPE_FPSTORE_UX
:
22805 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22806 && recog_memoized (dep_insn
)
22807 && (INSN_CODE (dep_insn
) >= 0))
22810 if (GET_CODE (PATTERN (insn
)) != SET
)
22811 /* If this happens, we have to extend this to schedule
22812 optimally. Return default for now. */
22815 /* Adjust the cost for the case where the value written
22816 by a fixed point operation is used as the address
22817 gen value on a store. */
22818 switch (get_attr_type (dep_insn
))
22825 if (! store_data_bypass_p (dep_insn
, insn
))
22829 case TYPE_LOAD_EXT
:
22830 case TYPE_LOAD_EXT_U
:
22831 case TYPE_LOAD_EXT_UX
:
22832 case TYPE_VAR_SHIFT_ROTATE
:
22833 case TYPE_VAR_DELAYED_COMPARE
:
22835 if (! store_data_bypass_p (dep_insn
, insn
))
22841 case TYPE_FAST_COMPARE
:
22844 case TYPE_INSERT_WORD
:
22845 case TYPE_INSERT_DWORD
:
22846 case TYPE_FPLOAD_U
:
22847 case TYPE_FPLOAD_UX
:
22849 case TYPE_STORE_UX
:
22850 case TYPE_FPSTORE_U
:
22851 case TYPE_FPSTORE_UX
:
22853 if (! store_data_bypass_p (dep_insn
, insn
))
22861 case TYPE_IMUL_COMPARE
:
22862 case TYPE_LMUL_COMPARE
:
22864 if (! store_data_bypass_p (dep_insn
, insn
))
22870 if (! store_data_bypass_p (dep_insn
, insn
))
22876 if (! store_data_bypass_p (dep_insn
, insn
))
22889 case TYPE_LOAD_EXT
:
22890 case TYPE_LOAD_EXT_U
:
22891 case TYPE_LOAD_EXT_UX
:
22892 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22893 && recog_memoized (dep_insn
)
22894 && (INSN_CODE (dep_insn
) >= 0))
22897 /* Adjust the cost for the case where the value written
22898 by a fixed point instruction is used within the address
22899 gen portion of a subsequent load(u)(x) */
22900 switch (get_attr_type (dep_insn
))
22907 if (set_to_load_agen (dep_insn
, insn
))
22911 case TYPE_LOAD_EXT
:
22912 case TYPE_LOAD_EXT_U
:
22913 case TYPE_LOAD_EXT_UX
:
22914 case TYPE_VAR_SHIFT_ROTATE
:
22915 case TYPE_VAR_DELAYED_COMPARE
:
22917 if (set_to_load_agen (dep_insn
, insn
))
22923 case TYPE_FAST_COMPARE
:
22926 case TYPE_INSERT_WORD
:
22927 case TYPE_INSERT_DWORD
:
22928 case TYPE_FPLOAD_U
:
22929 case TYPE_FPLOAD_UX
:
22931 case TYPE_STORE_UX
:
22932 case TYPE_FPSTORE_U
:
22933 case TYPE_FPSTORE_UX
:
22935 if (set_to_load_agen (dep_insn
, insn
))
22943 case TYPE_IMUL_COMPARE
:
22944 case TYPE_LMUL_COMPARE
:
22946 if (set_to_load_agen (dep_insn
, insn
))
22952 if (set_to_load_agen (dep_insn
, insn
))
22958 if (set_to_load_agen (dep_insn
, insn
))
22969 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22970 && recog_memoized (dep_insn
)
22971 && (INSN_CODE (dep_insn
) >= 0)
22972 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
22979 /* Fall out to return default cost. */
22983 case REG_DEP_OUTPUT
:
22984 /* Output dependency; DEP_INSN writes a register that INSN writes some
22986 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22987 && recog_memoized (dep_insn
)
22988 && (INSN_CODE (dep_insn
) >= 0))
22990 attr_type
= get_attr_type (insn
);
22995 if (get_attr_type (dep_insn
) == TYPE_FP
)
22999 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
23007 /* Anti dependency; DEP_INSN reads a register that INSN writes some
23012 gcc_unreachable ();
23018 /* Debug version of rs6000_adjust_cost. */
23021 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
23023 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
23029 switch (REG_NOTE_KIND (link
))
23031 default: dep
= "unknown depencency"; break;
23032 case REG_DEP_TRUE
: dep
= "data dependency"; break;
23033 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
23034 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
23038 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
23039 "%s, insn:\n", ret
, cost
, dep
);
23047 /* The function returns a true if INSN is microcoded.
23048 Return false otherwise. */
23051 is_microcoded_insn (rtx insn
)
23053 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23054 || GET_CODE (PATTERN (insn
)) == USE
23055 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23058 if (rs6000_cpu_attr
== CPU_CELL
)
23059 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
23061 if (rs6000_sched_groups
)
23063 enum attr_type type
= get_attr_type (insn
);
23064 if (type
== TYPE_LOAD_EXT_U
23065 || type
== TYPE_LOAD_EXT_UX
23066 || type
== TYPE_LOAD_UX
23067 || type
== TYPE_STORE_UX
23068 || type
== TYPE_MFCR
)
23075 /* The function returns true if INSN is cracked into 2 instructions
23076 by the processor (and therefore occupies 2 issue slots). */
23079 is_cracked_insn (rtx insn
)
23081 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23082 || GET_CODE (PATTERN (insn
)) == USE
23083 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23086 if (rs6000_sched_groups
)
23088 enum attr_type type
= get_attr_type (insn
);
23089 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
23090 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
23091 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
23092 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
23093 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
23094 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
23095 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
23096 || type
== TYPE_INSERT_WORD
)
23103 /* The function returns true if INSN can be issued only from
23104 the branch slot. */
23107 is_branch_slot_insn (rtx insn
)
23109 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23110 || GET_CODE (PATTERN (insn
)) == USE
23111 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23114 if (rs6000_sched_groups
)
23116 enum attr_type type
= get_attr_type (insn
);
23117 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
23125 /* The function returns true if out_inst sets a value that is
23126 used in the address generation computation of in_insn */
23128 set_to_load_agen (rtx out_insn
, rtx in_insn
)
23130 rtx out_set
, in_set
;
23132 /* For performance reasons, only handle the simple case where
23133 both loads are a single_set. */
23134 out_set
= single_set (out_insn
);
23137 in_set
= single_set (in_insn
);
23139 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
23145 /* Try to determine base/offset/size parts of the given MEM.
23146 Return true if successful, false if all the values couldn't
23149 This function only looks for REG or REG+CONST address forms.
23150 REG+REG address form will return false. */
23153 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
23154 HOST_WIDE_INT
*size
)
23157 if MEM_SIZE_KNOWN_P (mem
)
23158 *size
= MEM_SIZE (mem
);
23162 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
23163 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
23165 addr_rtx
= (XEXP (mem
, 0));
23167 if (GET_CODE (addr_rtx
) == REG
)
23172 else if (GET_CODE (addr_rtx
) == PLUS
23173 && CONST_INT_P (XEXP (addr_rtx
, 1)))
23175 *base
= XEXP (addr_rtx
, 0);
23176 *offset
= INTVAL (XEXP (addr_rtx
, 1));
23184 /* The function returns true if the target storage location of
23185 mem1 is adjacent to the target storage location of mem2 */
23186 /* Return 1 if memory locations are adjacent. */
23189 adjacent_mem_locations (rtx mem1
, rtx mem2
)
23192 HOST_WIDE_INT off1
, size1
, off2
, size2
;
23194 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
23195 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
23196 return ((REGNO (reg1
) == REGNO (reg2
))
23197 && ((off1
+ size1
== off2
)
23198 || (off2
+ size2
== off1
)));
23203 /* This function returns true if it can be determined that the two MEM
23204 locations overlap by at least 1 byte based on base reg/offset/size. */
23207 mem_locations_overlap (rtx mem1
, rtx mem2
)
23210 HOST_WIDE_INT off1
, size1
, off2
, size2
;
23212 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
23213 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
23214 return ((REGNO (reg1
) == REGNO (reg2
))
23215 && (((off1
<= off2
) && (off1
+ size1
> off2
))
23216 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
23221 /* A C statement (sans semicolon) to update the integer scheduling
23222 priority INSN_PRIORITY (INSN). Increase the priority to execute the
23223 INSN earlier, reduce the priority to execute INSN later. Do not
23224 define this macro if you do not need to adjust the scheduling
23225 priorities of insns. */
23228 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
23230 rtx load_mem
, str_mem
;
23231 /* On machines (like the 750) which have asymmetric integer units,
23232 where one integer unit can do multiply and divides and the other
23233 can't, reduce the priority of multiply/divide so it is scheduled
23234 before other integer operations. */
23237 if (! INSN_P (insn
))
23240 if (GET_CODE (PATTERN (insn
)) == USE
)
23243 switch (rs6000_cpu_attr
) {
23245 switch (get_attr_type (insn
))
23252 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
23253 priority
, priority
);
23254 if (priority
>= 0 && priority
< 0x01000000)
23261 if (insn_must_be_first_in_group (insn
)
23262 && reload_completed
23263 && current_sched_info
->sched_max_insns_priority
23264 && rs6000_sched_restricted_insns_priority
)
23267 /* Prioritize insns that can be dispatched only in the first
23269 if (rs6000_sched_restricted_insns_priority
== 1)
23270 /* Attach highest priority to insn. This means that in
23271 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
23272 precede 'priority' (critical path) considerations. */
23273 return current_sched_info
->sched_max_insns_priority
;
23274 else if (rs6000_sched_restricted_insns_priority
== 2)
23275 /* Increase priority of insn by a minimal amount. This means that in
23276 haifa-sched.c:ready_sort(), only 'priority' (critical path)
23277 considerations precede dispatch-slot restriction considerations. */
23278 return (priority
+ 1);
23281 if (rs6000_cpu
== PROCESSOR_POWER6
23282 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
23283 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
23284 /* Attach highest priority to insn if the scheduler has just issued two
23285 stores and this instruction is a load, or two loads and this instruction
23286 is a store. Power6 wants loads and stores scheduled alternately
23288 return current_sched_info
->sched_max_insns_priority
;
23293 /* Return true if the instruction is nonpipelined on the Cell. */
23295 is_nonpipeline_insn (rtx insn
)
23297 enum attr_type type
;
23298 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23299 || GET_CODE (PATTERN (insn
)) == USE
23300 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23303 type
= get_attr_type (insn
);
23304 if (type
== TYPE_IMUL
23305 || type
== TYPE_IMUL2
23306 || type
== TYPE_IMUL3
23307 || type
== TYPE_LMUL
23308 || type
== TYPE_IDIV
23309 || type
== TYPE_LDIV
23310 || type
== TYPE_SDIV
23311 || type
== TYPE_DDIV
23312 || type
== TYPE_SSQRT
23313 || type
== TYPE_DSQRT
23314 || type
== TYPE_MFCR
23315 || type
== TYPE_MFCRF
23316 || type
== TYPE_MFJMPR
)
23324 /* Return how many instructions the machine can issue per cycle. */
23327 rs6000_issue_rate (void)
23329 /* Unless scheduling for register pressure, use issue rate of 1 for
23330 first scheduling pass to decrease degradation. */
23331 if (!reload_completed
&& !flag_sched_pressure
)
23334 switch (rs6000_cpu_attr
) {
23336 case CPU_PPC601
: /* ? */
23346 case CPU_PPCE300C2
:
23347 case CPU_PPCE300C3
:
23348 case CPU_PPCE500MC
:
23349 case CPU_PPCE500MC64
:
23370 /* Return how many instructions to look ahead for better insn
23374 rs6000_use_sched_lookahead (void)
23376 switch (rs6000_cpu_attr
)
23383 return (reload_completed
? 8 : 0);
23390 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
23392 rs6000_use_sched_lookahead_guard (rtx insn
)
23394 if (rs6000_cpu_attr
!= CPU_CELL
)
23397 if (insn
== NULL_RTX
|| !INSN_P (insn
))
23400 if (!reload_completed
23401 || is_nonpipeline_insn (insn
)
23402 || is_microcoded_insn (insn
))
23408 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
23409 and return true. */
23412 find_mem_ref (rtx pat
, rtx
*mem_ref
)
23417 /* stack_tie does not produce any real memory traffic. */
23418 if (tie_operand (pat
, VOIDmode
))
23421 if (GET_CODE (pat
) == MEM
)
23427 /* Recursively process the pattern. */
23428 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
23430 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
23434 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
23437 else if (fmt
[i
] == 'E')
23438 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
23440 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
23448 /* Determine if PAT is a PATTERN of a load insn. */
23451 is_load_insn1 (rtx pat
, rtx
*load_mem
)
23453 if (!pat
|| pat
== NULL_RTX
)
23456 if (GET_CODE (pat
) == SET
)
23457 return find_mem_ref (SET_SRC (pat
), load_mem
);
23459 if (GET_CODE (pat
) == PARALLEL
)
23463 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
23464 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
23471 /* Determine if INSN loads from memory. */
23474 is_load_insn (rtx insn
, rtx
*load_mem
)
23476 if (!insn
|| !INSN_P (insn
))
23479 if (GET_CODE (insn
) == CALL_INSN
)
23482 return is_load_insn1 (PATTERN (insn
), load_mem
);
23485 /* Determine if PAT is a PATTERN of a store insn. */
23488 is_store_insn1 (rtx pat
, rtx
*str_mem
)
23490 if (!pat
|| pat
== NULL_RTX
)
23493 if (GET_CODE (pat
) == SET
)
23494 return find_mem_ref (SET_DEST (pat
), str_mem
);
23496 if (GET_CODE (pat
) == PARALLEL
)
23500 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
23501 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
23508 /* Determine if INSN stores to memory. */
23511 is_store_insn (rtx insn
, rtx
*str_mem
)
23513 if (!insn
|| !INSN_P (insn
))
23516 return is_store_insn1 (PATTERN (insn
), str_mem
);
23519 /* Returns whether the dependence between INSN and NEXT is considered
23520 costly by the given target. */
23523 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
23527 rtx load_mem
, str_mem
;
23529 /* If the flag is not enabled - no dependence is considered costly;
23530 allow all dependent insns in the same group.
23531 This is the most aggressive option. */
23532 if (rs6000_sched_costly_dep
== no_dep_costly
)
23535 /* If the flag is set to 1 - a dependence is always considered costly;
23536 do not allow dependent instructions in the same group.
23537 This is the most conservative option. */
23538 if (rs6000_sched_costly_dep
== all_deps_costly
)
23541 insn
= DEP_PRO (dep
);
23542 next
= DEP_CON (dep
);
23544 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
23545 && is_load_insn (next
, &load_mem
)
23546 && is_store_insn (insn
, &str_mem
))
23547 /* Prevent load after store in the same group. */
23550 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
23551 && is_load_insn (next
, &load_mem
)
23552 && is_store_insn (insn
, &str_mem
)
23553 && DEP_TYPE (dep
) == REG_DEP_TRUE
23554 && mem_locations_overlap(str_mem
, load_mem
))
23555 /* Prevent load after store in the same group if it is a true
23559 /* The flag is set to X; dependences with latency >= X are considered costly,
23560 and will not be scheduled in the same group. */
23561 if (rs6000_sched_costly_dep
<= max_dep_latency
23562 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
23568 /* Return the next insn after INSN that is found before TAIL is reached,
23569 skipping any "non-active" insns - insns that will not actually occupy
23570 an issue slot. Return NULL_RTX if such an insn is not found. */
23573 get_next_active_insn (rtx insn
, rtx tail
)
23575 if (insn
== NULL_RTX
|| insn
== tail
)
23580 insn
= NEXT_INSN (insn
);
23581 if (insn
== NULL_RTX
|| insn
== tail
)
23586 || (NONJUMP_INSN_P (insn
)
23587 && GET_CODE (PATTERN (insn
)) != USE
23588 && GET_CODE (PATTERN (insn
)) != CLOBBER
23589 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
23595 /* We are about to begin issuing insns for this clock cycle. */
23598 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
23599 rtx
*ready ATTRIBUTE_UNUSED
,
23600 int *pn_ready ATTRIBUTE_UNUSED
,
23601 int clock_var ATTRIBUTE_UNUSED
)
23603 int n_ready
= *pn_ready
;
23606 fprintf (dump
, "// rs6000_sched_reorder :\n");
23608 /* Reorder the ready list, if the second to last ready insn
23609 is a nonepipeline insn. */
23610 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
23612 if (is_nonpipeline_insn (ready
[n_ready
- 1])
23613 && (recog_memoized (ready
[n_ready
- 2]) > 0))
23614 /* Simply swap first two insns. */
23616 rtx tmp
= ready
[n_ready
- 1];
23617 ready
[n_ready
- 1] = ready
[n_ready
- 2];
23618 ready
[n_ready
- 2] = tmp
;
23622 if (rs6000_cpu
== PROCESSOR_POWER6
)
23623 load_store_pendulum
= 0;
23625 return rs6000_issue_rate ();
23628 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23631 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
23632 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
23635 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
23637 /* For Power6, we need to handle some special cases to try and keep the
23638 store queue from overflowing and triggering expensive flushes.
23640 This code monitors how load and store instructions are being issued
23641 and skews the ready list one way or the other to increase the likelihood
23642 that a desired instruction is issued at the proper time.
23644 A couple of things are done. First, we maintain a "load_store_pendulum"
23645 to track the current state of load/store issue.
23647 - If the pendulum is at zero, then no loads or stores have been
23648 issued in the current cycle so we do nothing.
23650 - If the pendulum is 1, then a single load has been issued in this
23651 cycle and we attempt to locate another load in the ready list to
23654 - If the pendulum is -2, then two stores have already been
23655 issued in this cycle, so we increase the priority of the first load
23656 in the ready list to increase it's likelihood of being chosen first
23659 - If the pendulum is -1, then a single store has been issued in this
23660 cycle and we attempt to locate another store in the ready list to
23661 issue with it, preferring a store to an adjacent memory location to
23662 facilitate store pairing in the store queue.
23664 - If the pendulum is 2, then two loads have already been
23665 issued in this cycle, so we increase the priority of the first store
23666 in the ready list to increase it's likelihood of being chosen first
23669 - If the pendulum < -2 or > 2, then do nothing.
23671 Note: This code covers the most common scenarios. There exist non
23672 load/store instructions which make use of the LSU and which
23673 would need to be accounted for to strictly model the behavior
23674 of the machine. Those instructions are currently unaccounted
23675 for to help minimize compile time overhead of this code.
23677 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
23681 rtx tmp
, load_mem
, str_mem
;
23683 if (is_store_insn (last_scheduled_insn
, &str_mem
))
23684 /* Issuing a store, swing the load_store_pendulum to the left */
23685 load_store_pendulum
--;
23686 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
23687 /* Issuing a load, swing the load_store_pendulum to the right */
23688 load_store_pendulum
++;
23690 return cached_can_issue_more
;
23692 /* If the pendulum is balanced, or there is only one instruction on
23693 the ready list, then all is well, so return. */
23694 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
23695 return cached_can_issue_more
;
23697 if (load_store_pendulum
== 1)
23699 /* A load has been issued in this cycle. Scan the ready list
23700 for another load to issue with it */
23705 if (is_load_insn (ready
[pos
], &load_mem
))
23707 /* Found a load. Move it to the head of the ready list,
23708 and adjust it's priority so that it is more likely to
23711 for (i
=pos
; i
<*pn_ready
-1; i
++)
23712 ready
[i
] = ready
[i
+ 1];
23713 ready
[*pn_ready
-1] = tmp
;
23715 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23716 INSN_PRIORITY (tmp
)++;
23722 else if (load_store_pendulum
== -2)
23724 /* Two stores have been issued in this cycle. Increase the
23725 priority of the first load in the ready list to favor it for
23726 issuing in the next cycle. */
23731 if (is_load_insn (ready
[pos
], &load_mem
)
23733 && INSN_PRIORITY_KNOWN (ready
[pos
]))
23735 INSN_PRIORITY (ready
[pos
])++;
23737 /* Adjust the pendulum to account for the fact that a load
23738 was found and increased in priority. This is to prevent
23739 increasing the priority of multiple loads */
23740 load_store_pendulum
--;
23747 else if (load_store_pendulum
== -1)
23749 /* A store has been issued in this cycle. Scan the ready list for
23750 another store to issue with it, preferring a store to an adjacent
23752 int first_store_pos
= -1;
23758 if (is_store_insn (ready
[pos
], &str_mem
))
23761 /* Maintain the index of the first store found on the
23763 if (first_store_pos
== -1)
23764 first_store_pos
= pos
;
23766 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
23767 && adjacent_mem_locations (str_mem
, str_mem2
))
23769 /* Found an adjacent store. Move it to the head of the
23770 ready list, and adjust it's priority so that it is
23771 more likely to stay there */
23773 for (i
=pos
; i
<*pn_ready
-1; i
++)
23774 ready
[i
] = ready
[i
+ 1];
23775 ready
[*pn_ready
-1] = tmp
;
23777 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23778 INSN_PRIORITY (tmp
)++;
23780 first_store_pos
= -1;
23788 if (first_store_pos
>= 0)
23790 /* An adjacent store wasn't found, but a non-adjacent store was,
23791 so move the non-adjacent store to the front of the ready
23792 list, and adjust its priority so that it is more likely to
23794 tmp
= ready
[first_store_pos
];
23795 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
23796 ready
[i
] = ready
[i
+ 1];
23797 ready
[*pn_ready
-1] = tmp
;
23798 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23799 INSN_PRIORITY (tmp
)++;
23802 else if (load_store_pendulum
== 2)
23804 /* Two loads have been issued in this cycle. Increase the priority
23805 of the first store in the ready list to favor it for issuing in
23811 if (is_store_insn (ready
[pos
], &str_mem
)
23813 && INSN_PRIORITY_KNOWN (ready
[pos
]))
23815 INSN_PRIORITY (ready
[pos
])++;
23817 /* Adjust the pendulum to account for the fact that a store
23818 was found and increased in priority. This is to prevent
23819 increasing the priority of multiple stores */
23820 load_store_pendulum
++;
23829 return cached_can_issue_more
;
23832 /* Return whether the presence of INSN causes a dispatch group termination
23833 of group WHICH_GROUP.
23835 If WHICH_GROUP == current_group, this function will return true if INSN
23836 causes the termination of the current group (i.e, the dispatch group to
23837 which INSN belongs). This means that INSN will be the last insn in the
23838 group it belongs to.
23840 If WHICH_GROUP == previous_group, this function will return true if INSN
23841 causes the termination of the previous group (i.e, the dispatch group that
23842 precedes the group to which INSN belongs). This means that INSN will be
23843 the first insn in the group it belongs to). */
23846 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
23853 first
= insn_must_be_first_in_group (insn
);
23854 last
= insn_must_be_last_in_group (insn
);
23859 if (which_group
== current_group
)
23861 else if (which_group
== previous_group
)
23869 insn_must_be_first_in_group (rtx insn
)
23871 enum attr_type type
;
23874 || GET_CODE (insn
) == NOTE
23875 || DEBUG_INSN_P (insn
)
23876 || GET_CODE (PATTERN (insn
)) == USE
23877 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23880 switch (rs6000_cpu
)
23882 case PROCESSOR_POWER5
:
23883 if (is_cracked_insn (insn
))
23885 case PROCESSOR_POWER4
:
23886 if (is_microcoded_insn (insn
))
23889 if (!rs6000_sched_groups
)
23892 type
= get_attr_type (insn
);
23899 case TYPE_DELAYED_CR
:
23900 case TYPE_CR_LOGICAL
:
23914 case PROCESSOR_POWER6
:
23915 type
= get_attr_type (insn
);
23919 case TYPE_INSERT_DWORD
:
23923 case TYPE_VAR_SHIFT_ROTATE
:
23930 case TYPE_INSERT_WORD
:
23931 case TYPE_DELAYED_COMPARE
:
23932 case TYPE_IMUL_COMPARE
:
23933 case TYPE_LMUL_COMPARE
:
23934 case TYPE_FPCOMPARE
:
23945 case TYPE_LOAD_EXT_UX
:
23947 case TYPE_STORE_UX
:
23948 case TYPE_FPLOAD_U
:
23949 case TYPE_FPLOAD_UX
:
23950 case TYPE_FPSTORE_U
:
23951 case TYPE_FPSTORE_UX
:
23957 case PROCESSOR_POWER7
:
23958 type
= get_attr_type (insn
);
23962 case TYPE_CR_LOGICAL
:
23969 case TYPE_DELAYED_COMPARE
:
23970 case TYPE_VAR_DELAYED_COMPARE
:
23976 case TYPE_LOAD_EXT
:
23977 case TYPE_LOAD_EXT_U
:
23978 case TYPE_LOAD_EXT_UX
:
23980 case TYPE_STORE_UX
:
23981 case TYPE_FPLOAD_U
:
23982 case TYPE_FPLOAD_UX
:
23983 case TYPE_FPSTORE_U
:
23984 case TYPE_FPSTORE_UX
:
24000 insn_must_be_last_in_group (rtx insn
)
24002 enum attr_type type
;
24005 || GET_CODE (insn
) == NOTE
24006 || DEBUG_INSN_P (insn
)
24007 || GET_CODE (PATTERN (insn
)) == USE
24008 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24011 switch (rs6000_cpu
) {
24012 case PROCESSOR_POWER4
:
24013 case PROCESSOR_POWER5
:
24014 if (is_microcoded_insn (insn
))
24017 if (is_branch_slot_insn (insn
))
24021 case PROCESSOR_POWER6
:
24022 type
= get_attr_type (insn
);
24029 case TYPE_VAR_SHIFT_ROTATE
:
24036 case TYPE_DELAYED_COMPARE
:
24037 case TYPE_IMUL_COMPARE
:
24038 case TYPE_LMUL_COMPARE
:
24039 case TYPE_FPCOMPARE
:
24053 case PROCESSOR_POWER7
:
24054 type
= get_attr_type (insn
);
24062 case TYPE_LOAD_EXT_U
:
24063 case TYPE_LOAD_EXT_UX
:
24064 case TYPE_STORE_UX
:
24077 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
24078 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
24081 is_costly_group (rtx
*group_insns
, rtx next_insn
)
24084 int issue_rate
= rs6000_issue_rate ();
24086 for (i
= 0; i
< issue_rate
; i
++)
24088 sd_iterator_def sd_it
;
24090 rtx insn
= group_insns
[i
];
24095 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
24097 rtx next
= DEP_CON (dep
);
24099 if (next
== next_insn
24100 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
24108 /* Utility of the function redefine_groups.
24109 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
24110 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
24111 to keep it "far" (in a separate group) from GROUP_INSNS, following
24112 one of the following schemes, depending on the value of the flag
24113 -minsert_sched_nops = X:
24114 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
24115 in order to force NEXT_INSN into a separate group.
24116 (2) X < sched_finish_regroup_exact: insert exactly X nops.
24117 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
24118 insertion (has a group just ended, how many vacant issue slots remain in the
24119 last group, and how many dispatch groups were encountered so far). */
24122 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
24123 rtx next_insn
, bool *group_end
, int can_issue_more
,
24128 int issue_rate
= rs6000_issue_rate ();
24129 bool end
= *group_end
;
24132 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
24133 return can_issue_more
;
24135 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
24136 return can_issue_more
;
24138 force
= is_costly_group (group_insns
, next_insn
);
24140 return can_issue_more
;
24142 if (sched_verbose
> 6)
24143 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
24144 *group_count
,can_issue_more
);
24146 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
24149 can_issue_more
= 0;
24151 /* Since only a branch can be issued in the last issue_slot, it is
24152 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
24153 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
24154 in this case the last nop will start a new group and the branch
24155 will be forced to the new group. */
24156 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
24159 /* Power6 and Power7 have special group ending nop. */
24160 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
)
24162 nop
= gen_group_ending_nop ();
24163 emit_insn_before (nop
, next_insn
);
24164 can_issue_more
= 0;
24167 while (can_issue_more
> 0)
24170 emit_insn_before (nop
, next_insn
);
24178 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
24180 int n_nops
= rs6000_sched_insert_nops
;
24182 /* Nops can't be issued from the branch slot, so the effective
24183 issue_rate for nops is 'issue_rate - 1'. */
24184 if (can_issue_more
== 0)
24185 can_issue_more
= issue_rate
;
24187 if (can_issue_more
== 0)
24189 can_issue_more
= issue_rate
- 1;
24192 for (i
= 0; i
< issue_rate
; i
++)
24194 group_insns
[i
] = 0;
24201 emit_insn_before (nop
, next_insn
);
24202 if (can_issue_more
== issue_rate
- 1) /* new group begins */
24205 if (can_issue_more
== 0)
24207 can_issue_more
= issue_rate
- 1;
24210 for (i
= 0; i
< issue_rate
; i
++)
24212 group_insns
[i
] = 0;
24218 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
24221 /* Is next_insn going to start a new group? */
24224 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
24225 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
24226 || (can_issue_more
< issue_rate
&&
24227 insn_terminates_group_p (next_insn
, previous_group
)));
24228 if (*group_end
&& end
)
24231 if (sched_verbose
> 6)
24232 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
24233 *group_count
, can_issue_more
);
24234 return can_issue_more
;
24237 return can_issue_more
;
24240 /* This function tries to synch the dispatch groups that the compiler "sees"
24241 with the dispatch groups that the processor dispatcher is expected to
24242 form in practice. It tries to achieve this synchronization by forcing the
24243 estimated processor grouping on the compiler (as opposed to the function
24244 'pad_goups' which tries to force the scheduler's grouping on the processor).
24246 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
24247 examines the (estimated) dispatch groups that will be formed by the processor
24248 dispatcher. It marks these group boundaries to reflect the estimated
24249 processor grouping, overriding the grouping that the scheduler had marked.
24250 Depending on the value of the flag '-minsert-sched-nops' this function can
24251 force certain insns into separate groups or force a certain distance between
24252 them by inserting nops, for example, if there exists a "costly dependence"
24255 The function estimates the group boundaries that the processor will form as
24256 follows: It keeps track of how many vacant issue slots are available after
24257 each insn. A subsequent insn will start a new group if one of the following
24259 - no more vacant issue slots remain in the current dispatch group.
24260 - only the last issue slot, which is the branch slot, is vacant, but the next
24261 insn is not a branch.
24262 - only the last 2 or less issue slots, including the branch slot, are vacant,
24263 which means that a cracked insn (which occupies two issue slots) can't be
24264 issued in this group.
24265 - less than 'issue_rate' slots are vacant, and the next insn always needs to
24266 start a new group. */
24269 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
24271 rtx insn
, next_insn
;
24273 int can_issue_more
;
24276 int group_count
= 0;
24280 issue_rate
= rs6000_issue_rate ();
24281 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
24282 for (i
= 0; i
< issue_rate
; i
++)
24284 group_insns
[i
] = 0;
24286 can_issue_more
= issue_rate
;
24288 insn
= get_next_active_insn (prev_head_insn
, tail
);
24291 while (insn
!= NULL_RTX
)
24293 slot
= (issue_rate
- can_issue_more
);
24294 group_insns
[slot
] = insn
;
24296 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
24297 if (insn_terminates_group_p (insn
, current_group
))
24298 can_issue_more
= 0;
24300 next_insn
= get_next_active_insn (insn
, tail
);
24301 if (next_insn
== NULL_RTX
)
24302 return group_count
+ 1;
24304 /* Is next_insn going to start a new group? */
24306 = (can_issue_more
== 0
24307 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
24308 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
24309 || (can_issue_more
< issue_rate
&&
24310 insn_terminates_group_p (next_insn
, previous_group
)));
24312 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
24313 next_insn
, &group_end
, can_issue_more
,
24319 can_issue_more
= 0;
24320 for (i
= 0; i
< issue_rate
; i
++)
24322 group_insns
[i
] = 0;
24326 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
24327 PUT_MODE (next_insn
, VOIDmode
);
24328 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
24329 PUT_MODE (next_insn
, TImode
);
24332 if (can_issue_more
== 0)
24333 can_issue_more
= issue_rate
;
24336 return group_count
;
24339 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
24340 dispatch group boundaries that the scheduler had marked. Pad with nops
24341 any dispatch groups which have vacant issue slots, in order to force the
24342 scheduler's grouping on the processor dispatcher. The function
24343 returns the number of dispatch groups found. */
24346 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
24348 rtx insn
, next_insn
;
24351 int can_issue_more
;
24353 int group_count
= 0;
24355 /* Initialize issue_rate. */
24356 issue_rate
= rs6000_issue_rate ();
24357 can_issue_more
= issue_rate
;
24359 insn
= get_next_active_insn (prev_head_insn
, tail
);
24360 next_insn
= get_next_active_insn (insn
, tail
);
24362 while (insn
!= NULL_RTX
)
24365 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
24367 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
24369 if (next_insn
== NULL_RTX
)
24374 /* If the scheduler had marked group termination at this location
24375 (between insn and next_insn), and neither insn nor next_insn will
24376 force group termination, pad the group with nops to force group
24379 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
24380 && !insn_terminates_group_p (insn
, current_group
)
24381 && !insn_terminates_group_p (next_insn
, previous_group
))
24383 if (!is_branch_slot_insn (next_insn
))
24386 while (can_issue_more
)
24389 emit_insn_before (nop
, next_insn
);
24394 can_issue_more
= issue_rate
;
24399 next_insn
= get_next_active_insn (insn
, tail
);
24402 return group_count
;
24405 /* We're beginning a new block. Initialize data structures as necessary. */
24408 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
24409 int sched_verbose ATTRIBUTE_UNUSED
,
24410 int max_ready ATTRIBUTE_UNUSED
)
24412 last_scheduled_insn
= NULL_RTX
;
24413 load_store_pendulum
= 0;
24416 /* The following function is called at the end of scheduling BB.
24417 After reload, it inserts nops at insn group bundling. */
24420 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
24425 fprintf (dump
, "=== Finishing schedule.\n");
24427 if (reload_completed
&& rs6000_sched_groups
)
24429 /* Do not run sched_finish hook when selective scheduling enabled. */
24430 if (sel_sched_p ())
24433 if (rs6000_sched_insert_nops
== sched_finish_none
)
24436 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
24437 n_groups
= pad_groups (dump
, sched_verbose
,
24438 current_sched_info
->prev_head
,
24439 current_sched_info
->next_tail
);
24441 n_groups
= redefine_groups (dump
, sched_verbose
,
24442 current_sched_info
->prev_head
,
24443 current_sched_info
->next_tail
);
24445 if (sched_verbose
>= 6)
24447 fprintf (dump
, "ngroups = %d\n", n_groups
);
24448 print_rtl (dump
, current_sched_info
->prev_head
);
24449 fprintf (dump
, "Done finish_sched\n");
24454 struct _rs6000_sched_context
24456 short cached_can_issue_more
;
24457 rtx last_scheduled_insn
;
24458 int load_store_pendulum
;
24461 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
24462 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
24464 /* Allocate store for new scheduling context. */
24466 rs6000_alloc_sched_context (void)
24468 return xmalloc (sizeof (rs6000_sched_context_def
));
24471 /* If CLEAN_P is true then initializes _SC with clean data,
24472 and from the global context otherwise. */
24474 rs6000_init_sched_context (void *_sc
, bool clean_p
)
24476 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
24480 sc
->cached_can_issue_more
= 0;
24481 sc
->last_scheduled_insn
= NULL_RTX
;
24482 sc
->load_store_pendulum
= 0;
24486 sc
->cached_can_issue_more
= cached_can_issue_more
;
24487 sc
->last_scheduled_insn
= last_scheduled_insn
;
24488 sc
->load_store_pendulum
= load_store_pendulum
;
24492 /* Sets the global scheduling context to the one pointed to by _SC. */
24494 rs6000_set_sched_context (void *_sc
)
24496 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
24498 gcc_assert (sc
!= NULL
);
24500 cached_can_issue_more
= sc
->cached_can_issue_more
;
24501 last_scheduled_insn
= sc
->last_scheduled_insn
;
24502 load_store_pendulum
= sc
->load_store_pendulum
;
24507 rs6000_free_sched_context (void *_sc
)
24509 gcc_assert (_sc
!= NULL
);
24515 /* Length in units of the trampoline for entering a nested function. */
24518 rs6000_trampoline_size (void)
24522 switch (DEFAULT_ABI
)
24525 gcc_unreachable ();
24528 ret
= (TARGET_32BIT
) ? 12 : 24;
24533 ret
= (TARGET_32BIT
) ? 40 : 48;
24540 /* Emit RTL insns to initialize the variable parts of a trampoline.
24541 FNADDR is an RTX for the address of the function's pure code.
24542 CXT is an RTX for the static chain value for the function. */
24545 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
24547 int regsize
= (TARGET_32BIT
) ? 4 : 8;
24548 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
24549 rtx ctx_reg
= force_reg (Pmode
, cxt
);
24550 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
24552 switch (DEFAULT_ABI
)
24555 gcc_unreachable ();
24557 /* Under AIX, just build the 3 word function descriptor */
24560 rtx fnmem
, fn_reg
, toc_reg
;
24562 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
24563 error ("You cannot take the address of a nested function if you use "
24564 "the -mno-pointers-to-nested-functions option.");
24566 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
24567 fn_reg
= gen_reg_rtx (Pmode
);
24568 toc_reg
= gen_reg_rtx (Pmode
);
24570 /* Macro to shorten the code expansions below. */
24571 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24573 m_tramp
= replace_equiv_address (m_tramp
, addr
);
24575 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
24576 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
24577 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
24578 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
24579 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
24585 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24588 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
24589 LCT_NORMAL
, VOIDmode
, 4,
24591 GEN_INT (rs6000_trampoline_size ()), SImode
,
24599 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24600 identifier as an argument, so the front end shouldn't look it up. */
24603 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
24605 return is_attribute_p ("altivec", attr_id
);
24608 /* Handle the "altivec" attribute. The attribute may have
24609 arguments as follows:
24611 __attribute__((altivec(vector__)))
24612 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24613 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24615 and may appear more than once (e.g., 'vector bool char') in a
24616 given declaration. */
24619 rs6000_handle_altivec_attribute (tree
*node
,
24620 tree name ATTRIBUTE_UNUSED
,
24622 int flags ATTRIBUTE_UNUSED
,
24623 bool *no_add_attrs
)
24625 tree type
= *node
, result
= NULL_TREE
;
24626 enum machine_mode mode
;
24629 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
24630 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
24631 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
24634 while (POINTER_TYPE_P (type
)
24635 || TREE_CODE (type
) == FUNCTION_TYPE
24636 || TREE_CODE (type
) == METHOD_TYPE
24637 || TREE_CODE (type
) == ARRAY_TYPE
)
24638 type
= TREE_TYPE (type
);
24640 mode
= TYPE_MODE (type
);
24642 /* Check for invalid AltiVec type qualifiers. */
24643 if (type
== long_double_type_node
)
24644 error ("use of %<long double%> in AltiVec types is invalid");
24645 else if (type
== boolean_type_node
)
24646 error ("use of boolean types in AltiVec types is invalid");
24647 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
24648 error ("use of %<complex%> in AltiVec types is invalid");
24649 else if (DECIMAL_FLOAT_MODE_P (mode
))
24650 error ("use of decimal floating point types in AltiVec types is invalid");
24651 else if (!TARGET_VSX
)
24653 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
24656 error ("use of %<long%> in AltiVec types is invalid for "
24657 "64-bit code without -mvsx");
24658 else if (rs6000_warn_altivec_long
)
24659 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24662 else if (type
== long_long_unsigned_type_node
24663 || type
== long_long_integer_type_node
)
24664 error ("use of %<long long%> in AltiVec types is invalid without "
24666 else if (type
== double_type_node
)
24667 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24670 switch (altivec_type
)
24673 unsigned_p
= TYPE_UNSIGNED (type
);
24677 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
24680 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
24683 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
24686 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
24688 case SFmode
: result
= V4SF_type_node
; break;
24689 case DFmode
: result
= V2DF_type_node
; break;
24690 /* If the user says 'vector int bool', we may be handed the 'bool'
24691 attribute _before_ the 'vector' attribute, and so select the
24692 proper type in the 'b' case below. */
24693 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
24694 case V2DImode
: case V2DFmode
:
24702 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
24703 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
24704 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
24705 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
24712 case V8HImode
: result
= pixel_V8HI_type_node
;
24718 /* Propagate qualifiers attached to the element type
24719 onto the vector type. */
24720 if (result
&& result
!= type
&& TYPE_QUALS (type
))
24721 result
= build_qualified_type (result
, TYPE_QUALS (type
));
24723 *no_add_attrs
= true; /* No need to hang on to the attribute. */
24726 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
24731 /* AltiVec defines four built-in scalar types that serve as vector
24732 elements; we must teach the compiler how to mangle them. */
24734 static const char *
24735 rs6000_mangle_type (const_tree type
)
24737 type
= TYPE_MAIN_VARIANT (type
);
24739 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
24740 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
24743 if (type
== bool_char_type_node
) return "U6__boolc";
24744 if (type
== bool_short_type_node
) return "U6__bools";
24745 if (type
== pixel_type_node
) return "u7__pixel";
24746 if (type
== bool_int_type_node
) return "U6__booli";
24747 if (type
== bool_long_type_node
) return "U6__booll";
24749 /* Mangle IBM extended float long double as `g' (__float128) on
24750 powerpc*-linux where long-double-64 previously was the default. */
24751 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
24753 && TARGET_LONG_DOUBLE_128
24754 && !TARGET_IEEEQUAD
)
24757 /* For all other types, use normal C++ mangling. */
24761 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24762 struct attribute_spec.handler. */
24765 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
24766 tree args ATTRIBUTE_UNUSED
,
24767 int flags ATTRIBUTE_UNUSED
,
24768 bool *no_add_attrs
)
24770 if (TREE_CODE (*node
) != FUNCTION_TYPE
24771 && TREE_CODE (*node
) != FIELD_DECL
24772 && TREE_CODE (*node
) != TYPE_DECL
)
24774 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
24776 *no_add_attrs
= true;
24782 /* Set longcall attributes on all functions declared when
24783 rs6000_default_long_calls is true. */
24785 rs6000_set_default_type_attributes (tree type
)
24787 if (rs6000_default_long_calls
24788 && (TREE_CODE (type
) == FUNCTION_TYPE
24789 || TREE_CODE (type
) == METHOD_TYPE
))
24790 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
24792 TYPE_ATTRIBUTES (type
));
24795 darwin_set_default_type_attributes (type
);
24799 /* Return a reference suitable for calling a function with the
24800 longcall attribute. */
24803 rs6000_longcall_ref (rtx call_ref
)
24805 const char *call_name
;
24808 if (GET_CODE (call_ref
) != SYMBOL_REF
)
24811 /* System V adds '.' to the internal name, so skip them. */
24812 call_name
= XSTR (call_ref
, 0);
24813 if (*call_name
== '.')
24815 while (*call_name
== '.')
24818 node
= get_identifier (call_name
);
24819 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
24822 return force_reg (Pmode
, call_ref
);
24825 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24826 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24829 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24830 struct attribute_spec.handler. */
24832 rs6000_handle_struct_attribute (tree
*node
, tree name
,
24833 tree args ATTRIBUTE_UNUSED
,
24834 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
24837 if (DECL_P (*node
))
24839 if (TREE_CODE (*node
) == TYPE_DECL
)
24840 type
= &TREE_TYPE (*node
);
24845 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
24846 || TREE_CODE (*type
) == UNION_TYPE
)))
24848 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
24849 *no_add_attrs
= true;
24852 else if ((is_attribute_p ("ms_struct", name
)
24853 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
24854 || ((is_attribute_p ("gcc_struct", name
)
24855 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
24857 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
24859 *no_add_attrs
= true;
24866 rs6000_ms_bitfield_layout_p (const_tree record_type
)
24868 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
24869 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
24870 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
24873 #ifdef USING_ELFOS_H
24875 /* A get_unnamed_section callback, used for switching to toc_section. */
24878 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
24880 if (DEFAULT_ABI
== ABI_AIX
24881 && TARGET_MINIMAL_TOC
24882 && !TARGET_RELOCATABLE
)
24884 if (!toc_initialized
)
24886 toc_initialized
= 1;
24887 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
24888 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
24889 fprintf (asm_out_file
, "\t.tc ");
24890 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
24891 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24892 fprintf (asm_out_file
, "\n");
24894 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24895 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24896 fprintf (asm_out_file
, " = .+32768\n");
24899 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24901 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
24902 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
24905 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24906 if (!toc_initialized
)
24908 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24909 fprintf (asm_out_file
, " = .+32768\n");
24910 toc_initialized
= 1;
24915 /* Implement TARGET_ASM_INIT_SECTIONS. */
24918 rs6000_elf_asm_init_sections (void)
24921 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
24924 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
24925 SDATA2_SECTION_ASM_OP
);
24928 /* Implement TARGET_SELECT_RTX_SECTION. */
24931 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
24932 unsigned HOST_WIDE_INT align
)
24934 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
24935 return toc_section
;
24937 return default_elf_select_rtx_section (mode
, x
, align
);
24940 /* For a SYMBOL_REF, set generic flags and then perform some
24941 target-specific processing.
24943 When the AIX ABI is requested on a non-AIX system, replace the
24944 function name with the real name (with a leading .) rather than the
24945 function descriptor name. This saves a lot of overriding code to
24946 read the prefixes. */
24948 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
24950 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
24952 default_encode_section_info (decl
, rtl
, first
);
24955 && TREE_CODE (decl
) == FUNCTION_DECL
24957 && DEFAULT_ABI
== ABI_AIX
)
24959 rtx sym_ref
= XEXP (rtl
, 0);
24960 size_t len
= strlen (XSTR (sym_ref
, 0));
24961 char *str
= XALLOCAVEC (char, len
+ 2);
24963 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
24964 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
24969 compare_section_name (const char *section
, const char *templ
)
24973 len
= strlen (templ
);
24974 return (strncmp (section
, templ
, len
) == 0
24975 && (section
[len
] == 0 || section
[len
] == '.'));
24979 rs6000_elf_in_small_data_p (const_tree decl
)
24981 if (rs6000_sdata
== SDATA_NONE
)
24984 /* We want to merge strings, so we never consider them small data. */
24985 if (TREE_CODE (decl
) == STRING_CST
)
24988 /* Functions are never in the small data area. */
24989 if (TREE_CODE (decl
) == FUNCTION_DECL
)
24992 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
24994 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
24995 if (compare_section_name (section
, ".sdata")
24996 || compare_section_name (section
, ".sdata2")
24997 || compare_section_name (section
, ".gnu.linkonce.s")
24998 || compare_section_name (section
, ".sbss")
24999 || compare_section_name (section
, ".sbss2")
25000 || compare_section_name (section
, ".gnu.linkonce.sb")
25001 || strcmp (section
, ".PPC.EMB.sdata0") == 0
25002 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
25007 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
25010 && size
<= g_switch_value
25011 /* If it's not public, and we're not going to reference it there,
25012 there's no need to put it in the small data section. */
25013 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
25020 #endif /* USING_ELFOS_H */
25022 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
25025 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
25027 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
25030 /* Do not place thread-local symbols refs in the object blocks. */
25033 rs6000_use_blocks_for_decl_p (const_tree decl
)
25035 return !DECL_THREAD_LOCAL_P (decl
);
25038 /* Return a REG that occurs in ADDR with coefficient 1.
25039 ADDR can be effectively incremented by incrementing REG.
25041 r0 is special and we must not select it as an address
25042 register by this routine since our caller will try to
25043 increment the returned register via an "la" instruction. */
25046 find_addr_reg (rtx addr
)
25048 while (GET_CODE (addr
) == PLUS
)
25050 if (GET_CODE (XEXP (addr
, 0)) == REG
25051 && REGNO (XEXP (addr
, 0)) != 0)
25052 addr
= XEXP (addr
, 0);
25053 else if (GET_CODE (XEXP (addr
, 1)) == REG
25054 && REGNO (XEXP (addr
, 1)) != 0)
25055 addr
= XEXP (addr
, 1);
25056 else if (CONSTANT_P (XEXP (addr
, 0)))
25057 addr
= XEXP (addr
, 1);
25058 else if (CONSTANT_P (XEXP (addr
, 1)))
25059 addr
= XEXP (addr
, 0);
25061 gcc_unreachable ();
25063 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
25068 rs6000_fatal_bad_address (rtx op
)
25070 fatal_insn ("bad address", op
);
25075 typedef struct branch_island_d
{
25076 tree function_name
;
25082 static vec
<branch_island
, va_gc
> *branch_islands
;
25084 /* Remember to generate a branch island for far calls to the given
25088 add_compiler_branch_island (tree label_name
, tree function_name
,
25091 branch_island bi
= {function_name
, label_name
, line_number
};
25092 vec_safe_push (branch_islands
, bi
);
25095 /* Generate far-jump branch islands for everything recorded in
25096 branch_islands. Invoked immediately after the last instruction of
25097 the epilogue has been emitted; the branch islands must be appended
25098 to, and contiguous with, the function body. Mach-O stubs are
25099 generated in machopic_output_stub(). */
25102 macho_branch_islands (void)
25106 while (!vec_safe_is_empty (branch_islands
))
25108 branch_island
*bi
= &branch_islands
->last ();
25109 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
25110 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
25111 char name_buf
[512];
25112 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
25113 if (name
[0] == '*' || name
[0] == '&')
25114 strcpy (name_buf
, name
+1);
25118 strcpy (name_buf
+1, name
);
25120 strcpy (tmp_buf
, "\n");
25121 strcat (tmp_buf
, label
);
25122 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25123 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
25124 dbxout_stabd (N_SLINE
, bi
->line_number
);
25125 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25128 if (TARGET_LINK_STACK
)
25131 get_ppc476_thunk_name (name
);
25132 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
25133 strcat (tmp_buf
, name
);
25134 strcat (tmp_buf
, "\n");
25135 strcat (tmp_buf
, label
);
25136 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
25140 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
25141 strcat (tmp_buf
, label
);
25142 strcat (tmp_buf
, "_pic\n");
25143 strcat (tmp_buf
, label
);
25144 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
25147 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
25148 strcat (tmp_buf
, name_buf
);
25149 strcat (tmp_buf
, " - ");
25150 strcat (tmp_buf
, label
);
25151 strcat (tmp_buf
, "_pic)\n");
25153 strcat (tmp_buf
, "\tmtlr r0\n");
25155 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
25156 strcat (tmp_buf
, name_buf
);
25157 strcat (tmp_buf
, " - ");
25158 strcat (tmp_buf
, label
);
25159 strcat (tmp_buf
, "_pic)\n");
25161 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
25165 strcat (tmp_buf
, ":\nlis r12,hi16(");
25166 strcat (tmp_buf
, name_buf
);
25167 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
25168 strcat (tmp_buf
, name_buf
);
25169 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
25171 output_asm_insn (tmp_buf
, 0);
25172 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25173 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
25174 dbxout_stabd (N_SLINE
, bi
->line_number
);
25175 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25176 branch_islands
->pop ();
25180 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
25181 already there or not. */
25184 no_previous_def (tree function_name
)
25189 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
25190 if (function_name
== bi
->function_name
)
25195 /* GET_PREV_LABEL gets the label name from the previous definition of
25199 get_prev_label (tree function_name
)
25204 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
25205 if (function_name
== bi
->function_name
)
25206 return bi
->label_name
;
25210 /* INSN is either a function call or a millicode call. It may have an
25211 unconditional jump in its delay slot.
25213 CALL_DEST is the routine we are calling. */
25216 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
25217 int cookie_operand_number
)
25219 static char buf
[256];
25220 if (darwin_emit_branch_islands
25221 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
25222 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
25225 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
25227 if (no_previous_def (funname
))
25229 rtx label_rtx
= gen_label_rtx ();
25230 char *label_buf
, temp_buf
[256];
25231 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
25232 CODE_LABEL_NUMBER (label_rtx
));
25233 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
25234 labelname
= get_identifier (label_buf
);
25235 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
25238 labelname
= get_prev_label (funname
);
25240 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
25241 instruction will reach 'foo', otherwise link as 'bl L42'".
25242 "L42" should be a 'branch island', that will do a far jump to
25243 'foo'. Branch islands are generated in
25244 macho_branch_islands(). */
25245 sprintf (buf
, "jbsr %%z%d,%.246s",
25246 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
25249 sprintf (buf
, "bl %%z%d", dest_operand_number
);
25253 /* Generate PIC and indirect symbol stubs. */
25256 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
25258 unsigned int length
;
25259 char *symbol_name
, *lazy_ptr_name
;
25260 char *local_label_0
;
25261 static int label
= 0;
25263 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25264 symb
= (*targetm
.strip_name_encoding
) (symb
);
25267 length
= strlen (symb
);
25268 symbol_name
= XALLOCAVEC (char, length
+ 32);
25269 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
25271 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
25272 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
25275 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
25277 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
25281 fprintf (file
, "\t.align 5\n");
25283 fprintf (file
, "%s:\n", stub
);
25284 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
25287 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
25288 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
25290 fprintf (file
, "\tmflr r0\n");
25291 if (TARGET_LINK_STACK
)
25294 get_ppc476_thunk_name (name
);
25295 fprintf (file
, "\tbl %s\n", name
);
25296 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
25300 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
25301 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
25303 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
25304 lazy_ptr_name
, local_label_0
);
25305 fprintf (file
, "\tmtlr r0\n");
25306 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
25307 (TARGET_64BIT
? "ldu" : "lwzu"),
25308 lazy_ptr_name
, local_label_0
);
25309 fprintf (file
, "\tmtctr r12\n");
25310 fprintf (file
, "\tbctr\n");
25314 fprintf (file
, "\t.align 4\n");
25316 fprintf (file
, "%s:\n", stub
);
25317 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
25319 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
25320 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
25321 (TARGET_64BIT
? "ldu" : "lwzu"),
25323 fprintf (file
, "\tmtctr r12\n");
25324 fprintf (file
, "\tbctr\n");
25327 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
25328 fprintf (file
, "%s:\n", lazy_ptr_name
);
25329 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
25330 fprintf (file
, "%sdyld_stub_binding_helper\n",
25331 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
25334 /* Legitimize PIC addresses. If the address is already
25335 position-independent, we return ORIG. Newly generated
25336 position-independent addresses go into a reg. This is REG if non
25337 zero, otherwise we allocate register(s) as necessary. */
25339 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
25342 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
25347 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
25348 reg
= gen_reg_rtx (Pmode
);
25350 if (GET_CODE (orig
) == CONST
)
25354 if (GET_CODE (XEXP (orig
, 0)) == PLUS
25355 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
25358 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
25360 /* Use a different reg for the intermediate value, as
25361 it will be marked UNCHANGING. */
25362 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
25363 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
25366 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
25369 if (GET_CODE (offset
) == CONST_INT
)
25371 if (SMALL_INT (offset
))
25372 return plus_constant (Pmode
, base
, INTVAL (offset
));
25373 else if (! reload_in_progress
&& ! reload_completed
)
25374 offset
= force_reg (Pmode
, offset
);
25377 rtx mem
= force_const_mem (Pmode
, orig
);
25378 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
25381 return gen_rtx_PLUS (Pmode
, base
, offset
);
25384 /* Fall back on generic machopic code. */
25385 return machopic_legitimize_pic_address (orig
, mode
, reg
);
25388 /* Output a .machine directive for the Darwin assembler, and call
25389 the generic start_file routine. */
25392 rs6000_darwin_file_start (void)
25394 static const struct
25398 HOST_WIDE_INT if_set
;
25400 { "ppc64", "ppc64", MASK_64BIT
},
25401 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
25402 { "power4", "ppc970", 0 },
25403 { "G5", "ppc970", 0 },
25404 { "7450", "ppc7450", 0 },
25405 { "7400", "ppc7400", MASK_ALTIVEC
},
25406 { "G4", "ppc7400", 0 },
25407 { "750", "ppc750", 0 },
25408 { "740", "ppc750", 0 },
25409 { "G3", "ppc750", 0 },
25410 { "604e", "ppc604e", 0 },
25411 { "604", "ppc604", 0 },
25412 { "603e", "ppc603", 0 },
25413 { "603", "ppc603", 0 },
25414 { "601", "ppc601", 0 },
25415 { NULL
, "ppc", 0 } };
25416 const char *cpu_id
= "";
25419 rs6000_file_start ();
25420 darwin_file_start ();
25422 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
25424 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
25425 cpu_id
= rs6000_default_cpu
;
25427 if (global_options_set
.x_rs6000_cpu_index
)
25428 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
25430 /* Look through the mapping array. Pick the first name that either
25431 matches the argument, has a bit set in IF_SET that is also set
25432 in the target flags, or has a NULL name. */
25435 while (mapping
[i
].arg
!= NULL
25436 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
25437 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
25440 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
25443 #endif /* TARGET_MACHO */
25447 rs6000_elf_reloc_rw_mask (void)
25451 else if (DEFAULT_ABI
== ABI_AIX
)
25457 /* Record an element in the table of global constructors. SYMBOL is
25458 a SYMBOL_REF of the function to be called; PRIORITY is a number
25459 between 0 and MAX_INIT_PRIORITY.
25461 This differs from default_named_section_asm_out_constructor in
25462 that we have special handling for -mrelocatable. */
25464 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
25466 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
25468 const char *section
= ".ctors";
25471 if (priority
!= DEFAULT_INIT_PRIORITY
)
25473 sprintf (buf
, ".ctors.%.5u",
25474 /* Invert the numbering so the linker puts us in the proper
25475 order; constructors are run from right to left, and the
25476 linker sorts in increasing order. */
25477 MAX_INIT_PRIORITY
- priority
);
25481 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
25482 assemble_align (POINTER_SIZE
);
25484 if (TARGET_RELOCATABLE
)
25486 fputs ("\t.long (", asm_out_file
);
25487 output_addr_const (asm_out_file
, symbol
);
25488 fputs (")@fixup\n", asm_out_file
);
25491 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
25494 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
25496 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
25498 const char *section
= ".dtors";
25501 if (priority
!= DEFAULT_INIT_PRIORITY
)
25503 sprintf (buf
, ".dtors.%.5u",
25504 /* Invert the numbering so the linker puts us in the proper
25505 order; constructors are run from right to left, and the
25506 linker sorts in increasing order. */
25507 MAX_INIT_PRIORITY
- priority
);
25511 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
25512 assemble_align (POINTER_SIZE
);
25514 if (TARGET_RELOCATABLE
)
25516 fputs ("\t.long (", asm_out_file
);
25517 output_addr_const (asm_out_file
, symbol
);
25518 fputs (")@fixup\n", asm_out_file
);
25521 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
25525 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
25529 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
25530 ASM_OUTPUT_LABEL (file
, name
);
25531 fputs (DOUBLE_INT_ASM_OP
, file
);
25532 rs6000_output_function_entry (file
, name
);
25533 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
25536 fputs ("\t.size\t", file
);
25537 assemble_name (file
, name
);
25538 fputs (",24\n\t.type\t.", file
);
25539 assemble_name (file
, name
);
25540 fputs (",@function\n", file
);
25541 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
25543 fputs ("\t.globl\t.", file
);
25544 assemble_name (file
, name
);
25549 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
25550 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
25551 rs6000_output_function_entry (file
, name
);
25552 fputs (":\n", file
);
25556 if (TARGET_RELOCATABLE
25557 && !TARGET_SECURE_PLT
25558 && (get_pool_size () != 0 || crtl
->profile
)
25563 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
25565 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
25566 fprintf (file
, "\t.long ");
25567 assemble_name (file
, buf
);
25569 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
25570 assemble_name (file
, buf
);
25574 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
25575 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
25577 if (DEFAULT_ABI
== ABI_AIX
)
25579 const char *desc_name
, *orig_name
;
25581 orig_name
= (*targetm
.strip_name_encoding
) (name
);
25582 desc_name
= orig_name
;
25583 while (*desc_name
== '.')
25586 if (TREE_PUBLIC (decl
))
25587 fprintf (file
, "\t.globl %s\n", desc_name
);
25589 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
25590 fprintf (file
, "%s:\n", desc_name
);
25591 fprintf (file
, "\t.long %s\n", orig_name
);
25592 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
25593 if (DEFAULT_ABI
== ABI_AIX
)
25594 fputs ("\t.long 0\n", file
);
25595 fprintf (file
, "\t.previous\n");
25597 ASM_OUTPUT_LABEL (file
, name
);
25600 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
25602 rs6000_elf_file_end (void)
25604 #ifdef HAVE_AS_GNU_ATTRIBUTE
25605 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
25607 if (rs6000_passes_float
)
25608 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
25609 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
25610 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
25612 if (rs6000_passes_vector
)
25613 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
25614 (TARGET_ALTIVEC_ABI
? 2
25615 : TARGET_SPE_ABI
? 3
25617 if (rs6000_returns_struct
)
25618 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
25619 aix_struct_return
? 2 : 1);
25622 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25624 file_end_indicate_exec_stack ();
25631 rs6000_xcoff_asm_output_anchor (rtx symbol
)
25635 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
25636 SYMBOL_REF_BLOCK_OFFSET (symbol
));
25637 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
25641 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
25643 fputs (GLOBAL_ASM_OP
, stream
);
25644 RS6000_OUTPUT_BASENAME (stream
, name
);
25645 putc ('\n', stream
);
25648 /* A get_unnamed_decl callback, used for read-only sections. PTR
25649 points to the section string variable. */
25652 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
25654 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
25655 *(const char *const *) directive
,
25656 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25659 /* Likewise for read-write sections. */
25662 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
25664 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
25665 *(const char *const *) directive
,
25666 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25670 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
25672 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
25673 *(const char *const *) directive
,
25674 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25677 /* A get_unnamed_section callback, used for switching to toc_section. */
25680 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
25682 if (TARGET_MINIMAL_TOC
)
25684 /* toc_section is always selected at least once from
25685 rs6000_xcoff_file_start, so this is guaranteed to
25686 always be defined once and only once in each file. */
25687 if (!toc_initialized
)
25689 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
25690 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
25691 toc_initialized
= 1;
25693 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
25694 (TARGET_32BIT
? "" : ",3"));
25697 fputs ("\t.toc\n", asm_out_file
);
25700 /* Implement TARGET_ASM_INIT_SECTIONS. */
25703 rs6000_xcoff_asm_init_sections (void)
25705 read_only_data_section
25706 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
25707 &xcoff_read_only_section_name
);
25709 private_data_section
25710 = get_unnamed_section (SECTION_WRITE
,
25711 rs6000_xcoff_output_readwrite_section_asm_op
,
25712 &xcoff_private_data_section_name
);
25715 = get_unnamed_section (SECTION_TLS
,
25716 rs6000_xcoff_output_tls_section_asm_op
,
25717 &xcoff_tls_data_section_name
);
25719 tls_private_data_section
25720 = get_unnamed_section (SECTION_TLS
,
25721 rs6000_xcoff_output_tls_section_asm_op
,
25722 &xcoff_private_data_section_name
);
25724 read_only_private_data_section
25725 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
25726 &xcoff_private_data_section_name
);
25729 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
25731 readonly_data_section
= read_only_data_section
;
25732 exception_section
= data_section
;
25736 rs6000_xcoff_reloc_rw_mask (void)
25742 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
25743 tree decl ATTRIBUTE_UNUSED
)
25746 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
25748 if (flags
& SECTION_CODE
)
25750 else if (flags
& SECTION_TLS
)
25752 else if (flags
& SECTION_WRITE
)
25757 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
25758 (flags
& SECTION_CODE
) ? "." : "",
25759 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
25763 rs6000_xcoff_select_section (tree decl
, int reloc
,
25764 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
25766 if (decl_readonly_section (decl
, reloc
))
25768 if (TREE_PUBLIC (decl
))
25769 return read_only_data_section
;
25771 return read_only_private_data_section
;
25776 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
25778 if (TREE_PUBLIC (decl
))
25779 return tls_data_section
;
25780 else if (bss_initializer_p (decl
))
25782 /* Convert to COMMON to emit in BSS. */
25783 DECL_COMMON (decl
) = 1;
25784 return tls_comm_section
;
25787 return tls_private_data_section
;
25791 if (TREE_PUBLIC (decl
))
25792 return data_section
;
25794 return private_data_section
;
25799 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
25803 /* Use select_section for private and uninitialized data. */
25804 if (!TREE_PUBLIC (decl
)
25805 || DECL_COMMON (decl
)
25806 || DECL_INITIAL (decl
) == NULL_TREE
25807 || DECL_INITIAL (decl
) == error_mark_node
25808 || (flag_zero_initialized_in_bss
25809 && initializer_zerop (DECL_INITIAL (decl
))))
25812 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
25813 name
= (*targetm
.strip_name_encoding
) (name
);
25814 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
25817 /* Select section for constant in constant pool.
25819 On RS/6000, all constants are in the private read-only data area.
25820 However, if this is being placed in the TOC it must be output as a
25824 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
25825 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
25827 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
25828 return toc_section
;
25830 return read_only_private_data_section
;
25833 /* Remove any trailing [DS] or the like from the symbol name. */
25835 static const char *
25836 rs6000_xcoff_strip_name_encoding (const char *name
)
25841 len
= strlen (name
);
25842 if (name
[len
- 1] == ']')
25843 return ggc_alloc_string (name
, len
- 4);
25848 /* Section attributes. AIX is always PIC. */
25850 static unsigned int
25851 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
25853 unsigned int align
;
25854 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
25856 /* Align to at least UNIT size. */
25857 if (flags
& SECTION_CODE
|| !decl
)
25858 align
= MIN_UNITS_PER_WORD
;
25860 /* Increase alignment of large objects if not already stricter. */
25861 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
25862 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
25863 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
25865 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
25868 /* Output at beginning of assembler file.
25870 Initialize the section names for the RS/6000 at this point.
25872 Specify filename, including full path, to assembler.
25874 We want to go into the TOC section so at least one .toc will be emitted.
25875 Also, in order to output proper .bs/.es pairs, we need at least one static
25876 [RW] section emitted.
25878 Finally, declare mcount when profiling to make the assembler happy. */
25881 rs6000_xcoff_file_start (void)
25883 rs6000_gen_section_name (&xcoff_bss_section_name
,
25884 main_input_filename
, ".bss_");
25885 rs6000_gen_section_name (&xcoff_private_data_section_name
,
25886 main_input_filename
, ".rw_");
25887 rs6000_gen_section_name (&xcoff_read_only_section_name
,
25888 main_input_filename
, ".ro_");
25889 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
25890 main_input_filename
, ".tls_");
25891 rs6000_gen_section_name (&xcoff_tbss_section_name
,
25892 main_input_filename
, ".tbss_[UL]");
25894 fputs ("\t.file\t", asm_out_file
);
25895 output_quoted_string (asm_out_file
, main_input_filename
);
25896 fputc ('\n', asm_out_file
);
25897 if (write_symbols
!= NO_DEBUG
)
25898 switch_to_section (private_data_section
);
25899 switch_to_section (text_section
);
25901 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
25902 rs6000_file_start ();
25905 /* Output at end of assembler file.
25906 On the RS/6000, referencing data should automatically pull in text. */
25909 rs6000_xcoff_file_end (void)
25911 switch_to_section (text_section
);
25912 fputs ("_section_.text:\n", asm_out_file
);
25913 switch_to_section (data_section
);
25914 fputs (TARGET_32BIT
25915 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25921 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
25926 default_encode_section_info (decl
, rtl
, first
);
25928 /* Careful not to prod global register variables. */
25931 symbol
= XEXP (rtl
, 0);
25932 if (GET_CODE (symbol
) != SYMBOL_REF
)
25935 flags
= SYMBOL_REF_FLAGS (symbol
);
25937 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
25938 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
25940 SYMBOL_REF_FLAGS (symbol
) = flags
;
25942 #endif /* HAVE_AS_TLS */
25943 #endif /* TARGET_XCOFF */
25945 /* Compute a (partial) cost for rtx X. Return true if the complete
25946 cost has been computed, and false if subexpressions should be
25947 scanned. In either case, *TOTAL contains the cost result. */
25950 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
25951 int *total
, bool speed
)
25953 enum machine_mode mode
= GET_MODE (x
);
25957 /* On the RS/6000, if it is valid in the insn, it is free. */
25959 if (((outer_code
== SET
25960 || outer_code
== PLUS
25961 || outer_code
== MINUS
)
25962 && (satisfies_constraint_I (x
)
25963 || satisfies_constraint_L (x
)))
25964 || (outer_code
== AND
25965 && (satisfies_constraint_K (x
)
25967 ? satisfies_constraint_L (x
)
25968 : satisfies_constraint_J (x
))
25969 || mask_operand (x
, mode
)
25971 && mask64_operand (x
, DImode
))))
25972 || ((outer_code
== IOR
|| outer_code
== XOR
)
25973 && (satisfies_constraint_K (x
)
25975 ? satisfies_constraint_L (x
)
25976 : satisfies_constraint_J (x
))))
25977 || outer_code
== ASHIFT
25978 || outer_code
== ASHIFTRT
25979 || outer_code
== LSHIFTRT
25980 || outer_code
== ROTATE
25981 || outer_code
== ROTATERT
25982 || outer_code
== ZERO_EXTRACT
25983 || (outer_code
== MULT
25984 && satisfies_constraint_I (x
))
25985 || ((outer_code
== DIV
|| outer_code
== UDIV
25986 || outer_code
== MOD
|| outer_code
== UMOD
)
25987 && exact_log2 (INTVAL (x
)) >= 0)
25988 || (outer_code
== COMPARE
25989 && (satisfies_constraint_I (x
)
25990 || satisfies_constraint_K (x
)))
25991 || ((outer_code
== EQ
|| outer_code
== NE
)
25992 && (satisfies_constraint_I (x
)
25993 || satisfies_constraint_K (x
)
25995 ? satisfies_constraint_L (x
)
25996 : satisfies_constraint_J (x
))))
25997 || (outer_code
== GTU
25998 && satisfies_constraint_I (x
))
25999 || (outer_code
== LTU
26000 && satisfies_constraint_P (x
)))
26005 else if ((outer_code
== PLUS
26006 && reg_or_add_cint_operand (x
, VOIDmode
))
26007 || (outer_code
== MINUS
26008 && reg_or_sub_cint_operand (x
, VOIDmode
))
26009 || ((outer_code
== SET
26010 || outer_code
== IOR
26011 || outer_code
== XOR
)
26013 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
26015 *total
= COSTS_N_INSNS (1);
26021 if (mode
== DImode
&& code
== CONST_DOUBLE
)
26023 if ((outer_code
== IOR
|| outer_code
== XOR
)
26024 && CONST_DOUBLE_HIGH (x
) == 0
26025 && (CONST_DOUBLE_LOW (x
)
26026 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
26031 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
26032 || ((outer_code
== SET
26033 || outer_code
== IOR
26034 || outer_code
== XOR
)
26035 && CONST_DOUBLE_HIGH (x
) == 0))
26037 *total
= COSTS_N_INSNS (1);
26047 /* When optimizing for size, MEM should be slightly more expensive
26048 than generating address, e.g., (plus (reg) (const)).
26049 L1 cache latency is about two instructions. */
26050 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
26059 if (FLOAT_MODE_P (mode
))
26060 *total
= rs6000_cost
->fp
;
26062 *total
= COSTS_N_INSNS (1);
26066 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
26067 && satisfies_constraint_I (XEXP (x
, 1)))
26069 if (INTVAL (XEXP (x
, 1)) >= -256
26070 && INTVAL (XEXP (x
, 1)) <= 255)
26071 *total
= rs6000_cost
->mulsi_const9
;
26073 *total
= rs6000_cost
->mulsi_const
;
26075 else if (mode
== SFmode
)
26076 *total
= rs6000_cost
->fp
;
26077 else if (FLOAT_MODE_P (mode
))
26078 *total
= rs6000_cost
->dmul
;
26079 else if (mode
== DImode
)
26080 *total
= rs6000_cost
->muldi
;
26082 *total
= rs6000_cost
->mulsi
;
26086 if (mode
== SFmode
)
26087 *total
= rs6000_cost
->fp
;
26089 *total
= rs6000_cost
->dmul
;
26094 if (FLOAT_MODE_P (mode
))
26096 *total
= mode
== DFmode
? rs6000_cost
->ddiv
26097 : rs6000_cost
->sdiv
;
26104 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
26105 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
26107 if (code
== DIV
|| code
== MOD
)
26109 *total
= COSTS_N_INSNS (2);
26112 *total
= COSTS_N_INSNS (1);
26116 if (GET_MODE (XEXP (x
, 1)) == DImode
)
26117 *total
= rs6000_cost
->divdi
;
26119 *total
= rs6000_cost
->divsi
;
26121 /* Add in shift and subtract for MOD. */
26122 if (code
== MOD
|| code
== UMOD
)
26123 *total
+= COSTS_N_INSNS (2);
26128 *total
= COSTS_N_INSNS (4);
26132 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
26136 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
26140 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
26152 *total
= COSTS_N_INSNS (1);
26160 /* Handle mul_highpart. */
26161 if (outer_code
== TRUNCATE
26162 && GET_CODE (XEXP (x
, 0)) == MULT
)
26164 if (mode
== DImode
)
26165 *total
= rs6000_cost
->muldi
;
26167 *total
= rs6000_cost
->mulsi
;
26170 else if (outer_code
== AND
)
26173 *total
= COSTS_N_INSNS (1);
26178 if (GET_CODE (XEXP (x
, 0)) == MEM
)
26181 *total
= COSTS_N_INSNS (1);
26187 if (!FLOAT_MODE_P (mode
))
26189 *total
= COSTS_N_INSNS (1);
26195 case UNSIGNED_FLOAT
:
26198 case FLOAT_TRUNCATE
:
26199 *total
= rs6000_cost
->fp
;
26203 if (mode
== DFmode
)
26206 *total
= rs6000_cost
->fp
;
26210 switch (XINT (x
, 1))
26213 *total
= rs6000_cost
->fp
;
26225 *total
= COSTS_N_INSNS (1);
26228 else if (FLOAT_MODE_P (mode
)
26229 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
26231 *total
= rs6000_cost
->fp
;
26239 /* Carry bit requires mode == Pmode.
26240 NEG or PLUS already counted so only add one. */
26242 && (outer_code
== NEG
|| outer_code
== PLUS
))
26244 *total
= COSTS_N_INSNS (1);
26247 if (outer_code
== SET
)
26249 if (XEXP (x
, 1) == const0_rtx
)
26251 if (TARGET_ISEL
&& !TARGET_MFCRF
)
26252 *total
= COSTS_N_INSNS (8);
26254 *total
= COSTS_N_INSNS (2);
26257 else if (mode
== Pmode
)
26259 *total
= COSTS_N_INSNS (3);
26268 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
26270 if (TARGET_ISEL
&& !TARGET_MFCRF
)
26271 *total
= COSTS_N_INSNS (8);
26273 *total
= COSTS_N_INSNS (2);
26277 if (outer_code
== COMPARE
)
26291 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
26294 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
26297 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
26300 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
26301 "opno = %d, total = %d, speed = %s, x:\n",
26302 ret
? "complete" : "scan inner",
26303 GET_RTX_NAME (code
),
26304 GET_RTX_NAME (outer_code
),
26307 speed
? "true" : "false");
26314 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
26317 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
26318 addr_space_t as
, bool speed
)
26320 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
26322 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
26323 ret
, speed
? "true" : "false");
26330 /* A C expression returning the cost of moving data from a register of class
26331 CLASS1 to one of CLASS2. */
26334 rs6000_register_move_cost (enum machine_mode mode
,
26335 reg_class_t from
, reg_class_t to
)
26339 if (TARGET_DEBUG_COST
)
26342 /* Moves from/to GENERAL_REGS. */
26343 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
26344 || reg_classes_intersect_p (from
, GENERAL_REGS
))
26346 reg_class_t rclass
= from
;
26348 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
26351 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
26352 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
26353 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
26355 /* It's more expensive to move CR_REGS than CR0_REGS because of the
26357 else if (rclass
== CR_REGS
)
26360 /* For those processors that have slow LR/CTR moves, make them more
26361 expensive than memory in order to bias spills to memory .*/
26362 else if ((rs6000_cpu
== PROCESSOR_POWER6
26363 || rs6000_cpu
== PROCESSOR_POWER7
)
26364 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
26365 ret
= 6 * hard_regno_nregs
[0][mode
];
26368 /* A move will cost one instruction per GPR moved. */
26369 ret
= 2 * hard_regno_nregs
[0][mode
];
26372 /* If we have VSX, we can easily move between FPR or Altivec registers. */
26373 else if (VECTOR_UNIT_VSX_P (mode
)
26374 && reg_classes_intersect_p (to
, VSX_REGS
)
26375 && reg_classes_intersect_p (from
, VSX_REGS
))
26376 ret
= 2 * hard_regno_nregs
[32][mode
];
26378 /* Moving between two similar registers is just one instruction. */
26379 else if (reg_classes_intersect_p (to
, from
))
26380 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
26382 /* Everything else has to go through GENERAL_REGS. */
26384 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
26385 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
26387 if (TARGET_DEBUG_COST
)
26389 if (dbg_cost_ctrl
== 1)
26391 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
26392 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
26393 reg_class_names
[to
]);
26400 /* A C expressions returning the cost of moving data of MODE from a register to
26404 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
26405 bool in ATTRIBUTE_UNUSED
)
26409 if (TARGET_DEBUG_COST
)
26412 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
26413 ret
= 4 * hard_regno_nregs
[0][mode
];
26414 else if (reg_classes_intersect_p (rclass
, FLOAT_REGS
))
26415 ret
= 4 * hard_regno_nregs
[32][mode
];
26416 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
26417 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
26419 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
26421 if (TARGET_DEBUG_COST
)
26423 if (dbg_cost_ctrl
== 1)
26425 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
26426 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
26433 /* Returns a code for a target-specific builtin that implements
26434 reciprocal of the function, or NULL_TREE if not available. */
26437 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
26438 bool sqrt ATTRIBUTE_UNUSED
)
26440 if (optimize_insn_for_size_p ())
26446 case VSX_BUILTIN_XVSQRTDP
:
26447 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
26450 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
26452 case VSX_BUILTIN_XVSQRTSP
:
26453 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
26456 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
26465 case BUILT_IN_SQRT
:
26466 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
26469 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
26471 case BUILT_IN_SQRTF
:
26472 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
26475 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
26482 /* Load up a constant. If the mode is a vector mode, splat the value across
26483 all of the vector elements. */
26486 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
26490 if (mode
== SFmode
|| mode
== DFmode
)
26492 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
26493 reg
= force_reg (mode
, d
);
26495 else if (mode
== V4SFmode
)
26497 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
26498 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
26499 reg
= gen_reg_rtx (mode
);
26500 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
26502 else if (mode
== V2DFmode
)
26504 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
26505 rtvec v
= gen_rtvec (2, d
, d
);
26506 reg
= gen_reg_rtx (mode
);
26507 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
26510 gcc_unreachable ();
26515 /* Generate an FMA instruction. */
26518 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
26520 enum machine_mode mode
= GET_MODE (target
);
26523 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
26524 gcc_assert (dst
!= NULL
);
26527 emit_move_insn (target
, dst
);
26530 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
26533 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
26535 enum machine_mode mode
= GET_MODE (target
);
26538 /* Altivec does not support fms directly;
26539 generate in terms of fma in that case. */
26540 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
26541 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
26544 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
26545 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
26547 gcc_assert (dst
!= NULL
);
26550 emit_move_insn (target
, dst
);
26553 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
26556 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
26558 enum machine_mode mode
= GET_MODE (dst
);
26561 /* This is a tad more complicated, since the fnma_optab is for
26562 a different expression: fma(-m1, m2, a), which is the same
26563 thing except in the case of signed zeros.
26565 Fortunately we know that if FMA is supported that FNMSUB is
26566 also supported in the ISA. Just expand it directly. */
26568 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
26570 r
= gen_rtx_NEG (mode
, a
);
26571 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
26572 r
= gen_rtx_NEG (mode
, r
);
26573 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
26576 /* Newton-Raphson approximation of floating point divide with just 2 passes
26577 (either single precision floating point, or newer machines with higher
26578 accuracy estimates). Support both scalar and vector divide. Assumes no
26579 trapping math and finite arguments. */
26582 rs6000_emit_swdiv_high_precision (rtx dst
, rtx n
, rtx d
)
26584 enum machine_mode mode
= GET_MODE (dst
);
26585 rtx x0
, e0
, e1
, y1
, u0
, v0
;
26586 enum insn_code code
= optab_handler (smul_optab
, mode
);
26587 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26588 rtx one
= rs6000_load_constant_and_splat (mode
, dconst1
);
26590 gcc_assert (code
!= CODE_FOR_nothing
);
26592 /* x0 = 1./d estimate */
26593 x0
= gen_reg_rtx (mode
);
26594 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26595 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
26598 e0
= gen_reg_rtx (mode
);
26599 rs6000_emit_nmsub (e0
, d
, x0
, one
); /* e0 = 1. - (d * x0) */
26601 e1
= gen_reg_rtx (mode
);
26602 rs6000_emit_madd (e1
, e0
, e0
, e0
); /* e1 = (e0 * e0) + e0 */
26604 y1
= gen_reg_rtx (mode
);
26605 rs6000_emit_madd (y1
, e1
, x0
, x0
); /* y1 = (e1 * x0) + x0 */
26607 u0
= gen_reg_rtx (mode
);
26608 emit_insn (gen_mul (u0
, n
, y1
)); /* u0 = n * y1 */
26610 v0
= gen_reg_rtx (mode
);
26611 rs6000_emit_nmsub (v0
, d
, u0
, n
); /* v0 = n - (d * u0) */
26613 rs6000_emit_madd (dst
, v0
, y1
, u0
); /* dst = (v0 * y1) + u0 */
26616 /* Newton-Raphson approximation of floating point divide that has a low
26617 precision estimate. Assumes no trapping math and finite arguments. */
26620 rs6000_emit_swdiv_low_precision (rtx dst
, rtx n
, rtx d
)
26622 enum machine_mode mode
= GET_MODE (dst
);
26623 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
26624 enum insn_code code
= optab_handler (smul_optab
, mode
);
26625 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26627 gcc_assert (code
!= CODE_FOR_nothing
);
26629 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
26631 /* x0 = 1./d estimate */
26632 x0
= gen_reg_rtx (mode
);
26633 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26634 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
26637 e0
= gen_reg_rtx (mode
);
26638 rs6000_emit_nmsub (e0
, d
, x0
, one
); /* e0 = 1. - d * x0 */
26640 y1
= gen_reg_rtx (mode
);
26641 rs6000_emit_madd (y1
, e0
, x0
, x0
); /* y1 = x0 + e0 * x0 */
26643 e1
= gen_reg_rtx (mode
);
26644 emit_insn (gen_mul (e1
, e0
, e0
)); /* e1 = e0 * e0 */
26646 y2
= gen_reg_rtx (mode
);
26647 rs6000_emit_madd (y2
, e1
, y1
, y1
); /* y2 = y1 + e1 * y1 */
26649 e2
= gen_reg_rtx (mode
);
26650 emit_insn (gen_mul (e2
, e1
, e1
)); /* e2 = e1 * e1 */
26652 y3
= gen_reg_rtx (mode
);
26653 rs6000_emit_madd (y3
, e2
, y2
, y2
); /* y3 = y2 + e2 * y2 */
26655 u0
= gen_reg_rtx (mode
);
26656 emit_insn (gen_mul (u0
, n
, y3
)); /* u0 = n * y3 */
26658 v0
= gen_reg_rtx (mode
);
26659 rs6000_emit_nmsub (v0
, d
, u0
, n
); /* v0 = n - d * u0 */
26661 rs6000_emit_madd (dst
, v0
, y3
, u0
); /* dst = u0 + v0 * y3 */
26664 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26665 add a reg_note saying that this was a division. Support both scalar and
26666 vector divide. Assumes no trapping math and finite arguments. */
26669 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
26671 enum machine_mode mode
= GET_MODE (dst
);
26673 if (RS6000_RECIP_HIGH_PRECISION_P (mode
))
26674 rs6000_emit_swdiv_high_precision (dst
, n
, d
);
26676 rs6000_emit_swdiv_low_precision (dst
, n
, d
);
26679 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
26682 /* Newton-Raphson approximation of single/double-precision floating point
26683 rsqrt. Assumes no trapping math and finite arguments. */
26686 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
26688 enum machine_mode mode
= GET_MODE (src
);
26689 rtx x0
= gen_reg_rtx (mode
);
26690 rtx y
= gen_reg_rtx (mode
);
26691 int passes
= (TARGET_RECIP_PRECISION
) ? 2 : 3;
26692 REAL_VALUE_TYPE dconst3_2
;
26695 enum insn_code code
= optab_handler (smul_optab
, mode
);
26696 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26698 gcc_assert (code
!= CODE_FOR_nothing
);
26700 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26701 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
26702 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
26704 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
26706 /* x0 = rsqrt estimate */
26707 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26708 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
26711 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26712 rs6000_emit_msub (y
, src
, halfthree
, src
);
26714 for (i
= 0; i
< passes
; i
++)
26716 rtx x1
= gen_reg_rtx (mode
);
26717 rtx u
= gen_reg_rtx (mode
);
26718 rtx v
= gen_reg_rtx (mode
);
26720 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26721 emit_insn (gen_mul (u
, x0
, x0
));
26722 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
26723 emit_insn (gen_mul (x1
, x0
, v
));
26727 emit_move_insn (dst
, x0
);
26731 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26732 (Power7) targets. DST is the target, and SRC is the argument operand. */
26735 rs6000_emit_popcount (rtx dst
, rtx src
)
26737 enum machine_mode mode
= GET_MODE (dst
);
26740 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26741 if (TARGET_POPCNTD
)
26743 if (mode
== SImode
)
26744 emit_insn (gen_popcntdsi2 (dst
, src
));
26746 emit_insn (gen_popcntddi2 (dst
, src
));
26750 tmp1
= gen_reg_rtx (mode
);
26752 if (mode
== SImode
)
26754 emit_insn (gen_popcntbsi2 (tmp1
, src
));
26755 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
26757 tmp2
= force_reg (SImode
, tmp2
);
26758 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
26762 emit_insn (gen_popcntbdi2 (tmp1
, src
));
26763 tmp2
= expand_mult (DImode
, tmp1
,
26764 GEN_INT ((HOST_WIDE_INT
)
26765 0x01010101 << 32 | 0x01010101),
26767 tmp2
= force_reg (DImode
, tmp2
);
26768 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
26773 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26774 target, and SRC is the argument operand. */
26777 rs6000_emit_parity (rtx dst
, rtx src
)
26779 enum machine_mode mode
= GET_MODE (dst
);
26782 tmp
= gen_reg_rtx (mode
);
26784 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26787 if (mode
== SImode
)
26789 emit_insn (gen_popcntbsi2 (tmp
, src
));
26790 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
26794 emit_insn (gen_popcntbdi2 (tmp
, src
));
26795 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
26800 if (mode
== SImode
)
26802 /* Is mult+shift >= shift+xor+shift+xor? */
26803 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
26805 rtx tmp1
, tmp2
, tmp3
, tmp4
;
26807 tmp1
= gen_reg_rtx (SImode
);
26808 emit_insn (gen_popcntbsi2 (tmp1
, src
));
26810 tmp2
= gen_reg_rtx (SImode
);
26811 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
26812 tmp3
= gen_reg_rtx (SImode
);
26813 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
26815 tmp4
= gen_reg_rtx (SImode
);
26816 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
26817 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
26820 rs6000_emit_popcount (tmp
, src
);
26821 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
26825 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26826 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
26828 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
26830 tmp1
= gen_reg_rtx (DImode
);
26831 emit_insn (gen_popcntbdi2 (tmp1
, src
));
26833 tmp2
= gen_reg_rtx (DImode
);
26834 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
26835 tmp3
= gen_reg_rtx (DImode
);
26836 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
26838 tmp4
= gen_reg_rtx (DImode
);
26839 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
26840 tmp5
= gen_reg_rtx (DImode
);
26841 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
26843 tmp6
= gen_reg_rtx (DImode
);
26844 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
26845 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
26848 rs6000_emit_popcount (tmp
, src
);
26849 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
26853 /* Expand an Altivec constant permutation. Return true if we match
26854 an efficient implementation; false to fall back to VPERM. */
26857 altivec_expand_vec_perm_const (rtx operands
[4])
26859 struct altivec_perm_insn
{
26860 enum insn_code impl
;
26861 unsigned char perm
[16];
26863 static const struct altivec_perm_insn patterns
[] = {
26864 { CODE_FOR_altivec_vpkuhum
,
26865 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26866 { CODE_FOR_altivec_vpkuwum
,
26867 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26868 { CODE_FOR_altivec_vmrghb
,
26869 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26870 { CODE_FOR_altivec_vmrghh
,
26871 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26872 { CODE_FOR_altivec_vmrghw
,
26873 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26874 { CODE_FOR_altivec_vmrglb
,
26875 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26876 { CODE_FOR_altivec_vmrglh
,
26877 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26878 { CODE_FOR_altivec_vmrglw
,
26879 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26882 unsigned int i
, j
, elt
, which
;
26883 unsigned char perm
[16];
26884 rtx target
, op0
, op1
, sel
, x
;
26887 target
= operands
[0];
26892 /* Unpack the constant selector. */
26893 for (i
= which
= 0; i
< 16; ++i
)
26895 rtx e
= XVECEXP (sel
, 0, i
);
26896 elt
= INTVAL (e
) & 31;
26897 which
|= (elt
< 16 ? 1 : 2);
26901 /* Simplify the constant selector based on operands. */
26905 gcc_unreachable ();
26909 if (!rtx_equal_p (op0
, op1
))
26914 for (i
= 0; i
< 16; ++i
)
26926 /* Look for splat patterns. */
26931 for (i
= 0; i
< 16; ++i
)
26932 if (perm
[i
] != elt
)
26936 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
26942 for (i
= 0; i
< 16; i
+= 2)
26943 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
26947 x
= gen_reg_rtx (V8HImode
);
26948 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
26949 GEN_INT (elt
/ 2)));
26950 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26957 for (i
= 0; i
< 16; i
+= 4)
26959 || perm
[i
+ 1] != elt
+ 1
26960 || perm
[i
+ 2] != elt
+ 2
26961 || perm
[i
+ 3] != elt
+ 3)
26965 x
= gen_reg_rtx (V4SImode
);
26966 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
26967 GEN_INT (elt
/ 4)));
26968 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26974 /* Look for merge and pack patterns. */
26975 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
26979 elt
= patterns
[j
].perm
[0];
26980 if (perm
[0] == elt
)
26982 else if (perm
[0] == elt
+ 16)
26986 for (i
= 1; i
< 16; ++i
)
26988 elt
= patterns
[j
].perm
[i
];
26990 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
26991 else if (one_vec
&& elt
>= 16)
26993 if (perm
[i
] != elt
)
26998 enum insn_code icode
= patterns
[j
].impl
;
26999 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
27000 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
27003 x
= op0
, op0
= op1
, op1
= x
;
27004 if (imode
!= V16QImode
)
27006 op0
= gen_lowpart (imode
, op0
);
27007 op1
= gen_lowpart (imode
, op1
);
27009 if (omode
== V16QImode
)
27012 x
= gen_reg_rtx (omode
);
27013 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
27014 if (omode
!= V16QImode
)
27015 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
27023 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
27024 Return true if we match an efficient implementation. */
27027 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
27028 unsigned char perm0
, unsigned char perm1
)
27032 /* If both selectors come from the same operand, fold to single op. */
27033 if ((perm0
& 2) == (perm1
& 2))
27040 /* If both operands are equal, fold to simpler permutation. */
27041 if (rtx_equal_p (op0
, op1
))
27044 perm1
= (perm1
& 1) + 2;
27046 /* If the first selector comes from the second operand, swap. */
27047 else if (perm0
& 2)
27053 x
= op0
, op0
= op1
, op1
= x
;
27055 /* If the second selector does not come from the second operand, fail. */
27056 else if ((perm1
& 2) == 0)
27060 if (target
!= NULL
)
27062 enum machine_mode vmode
, dmode
;
27065 vmode
= GET_MODE (target
);
27066 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
27067 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
27069 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
27070 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
27071 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
27072 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
27078 rs6000_expand_vec_perm_const (rtx operands
[4])
27080 rtx target
, op0
, op1
, sel
;
27081 unsigned char perm0
, perm1
;
27083 target
= operands
[0];
27088 /* Unpack the constant selector. */
27089 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
27090 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
27092 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
27095 /* Test whether a constant permutation is supported. */
27098 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
27099 const unsigned char *sel
)
27101 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
27102 if (TARGET_ALTIVEC
)
27105 /* Check for ps_merge* or evmerge* insns. */
27106 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
27107 || (TARGET_SPE
&& vmode
== V2SImode
))
27109 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
27110 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
27111 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
27117 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
27120 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
27121 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
27123 enum machine_mode imode
;
27127 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
27129 imode
= GET_MODE_INNER (vmode
);
27130 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
27131 imode
= mode_for_vector (imode
, nelt
);
27134 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
27135 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
27137 emit_move_insn (target
, x
);
27140 /* Expand an extract even operation. */
27143 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
27145 enum machine_mode vmode
= GET_MODE (target
);
27146 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
27149 for (i
= 0; i
< nelt
; i
++)
27150 perm
[i
] = GEN_INT (i
* 2);
27152 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
27155 /* Expand a vector interleave operation. */
27158 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
27160 enum machine_mode vmode
= GET_MODE (target
);
27161 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
27164 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
27165 for (i
= 0; i
< nelt
/ 2; i
++)
27167 perm
[i
* 2] = GEN_INT (i
+ high
);
27168 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
27171 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
27174 /* Return an RTX representing where to find the function value of a
27175 function returning MODE. */
27177 rs6000_complex_function_value (enum machine_mode mode
)
27179 unsigned int regno
;
27181 enum machine_mode inner
= GET_MODE_INNER (mode
);
27182 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
27184 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27185 regno
= FP_ARG_RETURN
;
27188 regno
= GP_ARG_RETURN
;
27190 /* 32-bit is OK since it'll go in r3/r4. */
27191 if (TARGET_32BIT
&& inner_bytes
>= 4)
27192 return gen_rtx_REG (mode
, regno
);
27195 if (inner_bytes
>= 8)
27196 return gen_rtx_REG (mode
, regno
);
27198 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
27200 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
27201 GEN_INT (inner_bytes
));
27202 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
27205 /* Target hook for TARGET_FUNCTION_VALUE.
27207 On the SPE, both FPs and vectors are returned in r3.
27209 On RS/6000 an integer value is in r3 and a floating-point value is in
27210 fp1, unless -msoft-float. */
27213 rs6000_function_value (const_tree valtype
,
27214 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
27215 bool outgoing ATTRIBUTE_UNUSED
)
27217 enum machine_mode mode
;
27218 unsigned int regno
;
27220 /* Special handling for structs in darwin64. */
27222 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
27224 CUMULATIVE_ARGS valcum
;
27228 valcum
.fregno
= FP_ARG_MIN_REG
;
27229 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
27230 /* Do a trial code generation as if this were going to be passed as
27231 an argument; if any part goes in memory, we return NULL. */
27232 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
27235 /* Otherwise fall through to standard ABI rules. */
27238 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
27240 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
27241 return gen_rtx_PARALLEL (DImode
,
27243 gen_rtx_EXPR_LIST (VOIDmode
,
27244 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
27246 gen_rtx_EXPR_LIST (VOIDmode
,
27247 gen_rtx_REG (SImode
,
27248 GP_ARG_RETURN
+ 1),
27251 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
27253 return gen_rtx_PARALLEL (DCmode
,
27255 gen_rtx_EXPR_LIST (VOIDmode
,
27256 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
27258 gen_rtx_EXPR_LIST (VOIDmode
,
27259 gen_rtx_REG (SImode
,
27260 GP_ARG_RETURN
+ 1),
27262 gen_rtx_EXPR_LIST (VOIDmode
,
27263 gen_rtx_REG (SImode
,
27264 GP_ARG_RETURN
+ 2),
27266 gen_rtx_EXPR_LIST (VOIDmode
,
27267 gen_rtx_REG (SImode
,
27268 GP_ARG_RETURN
+ 3),
27272 mode
= TYPE_MODE (valtype
);
27273 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
27274 || POINTER_TYPE_P (valtype
))
27275 mode
= TARGET_32BIT
? SImode
: DImode
;
27277 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27278 /* _Decimal128 must use an even/odd register pair. */
27279 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
27280 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
27281 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
27282 regno
= FP_ARG_RETURN
;
27283 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
27284 && targetm
.calls
.split_complex_arg
)
27285 return rs6000_complex_function_value (mode
);
27286 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27287 return register is used in both cases, and we won't see V2DImode/V2DFmode
27288 for pure altivec, combine the two cases. */
27289 else if (TREE_CODE (valtype
) == VECTOR_TYPE
27290 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
27291 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
27292 regno
= ALTIVEC_ARG_RETURN
;
27293 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
27294 && (mode
== DFmode
|| mode
== DCmode
27295 || mode
== TFmode
|| mode
== TCmode
))
27296 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
27298 regno
= GP_ARG_RETURN
;
27300 return gen_rtx_REG (mode
, regno
);
27303 /* Define how to find the value returned by a library function
27304 assuming the value has mode MODE. */
27306 rs6000_libcall_value (enum machine_mode mode
)
27308 unsigned int regno
;
27310 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
27312 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
27313 return gen_rtx_PARALLEL (DImode
,
27315 gen_rtx_EXPR_LIST (VOIDmode
,
27316 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
27318 gen_rtx_EXPR_LIST (VOIDmode
,
27319 gen_rtx_REG (SImode
,
27320 GP_ARG_RETURN
+ 1),
27324 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27325 /* _Decimal128 must use an even/odd register pair. */
27326 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
27327 else if (SCALAR_FLOAT_MODE_P (mode
)
27328 && TARGET_HARD_FLOAT
&& TARGET_FPRS
27329 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
27330 regno
= FP_ARG_RETURN
;
27331 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27332 return register is used in both cases, and we won't see V2DImode/V2DFmode
27333 for pure altivec, combine the two cases. */
27334 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
27335 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
27336 regno
= ALTIVEC_ARG_RETURN
;
27337 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
27338 return rs6000_complex_function_value (mode
);
27339 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
27340 && (mode
== DFmode
|| mode
== DCmode
27341 || mode
== TFmode
|| mode
== TCmode
))
27342 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
27344 regno
= GP_ARG_RETURN
;
27346 return gen_rtx_REG (mode
, regno
);
27350 /* Given FROM and TO register numbers, say whether this elimination is allowed.
27351 Frame pointer elimination is automatically handled.
27353 For the RS/6000, if frame pointer elimination is being done, we would like
27354 to convert ap into fp, not sp.
27356 We need r30 if -mminimal-toc was specified, and there are constant pool
27360 rs6000_can_eliminate (const int from
, const int to
)
27362 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
27363 ? ! frame_pointer_needed
27364 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
27365 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
27369 /* Define the offset between two registers, FROM to be eliminated and its
27370 replacement TO, at the start of a routine. */
27372 rs6000_initial_elimination_offset (int from
, int to
)
27374 rs6000_stack_t
*info
= rs6000_stack_info ();
27375 HOST_WIDE_INT offset
;
27377 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
27378 offset
= info
->push_p
? 0 : -info
->total_size
;
27379 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
27381 offset
= info
->push_p
? 0 : -info
->total_size
;
27382 if (FRAME_GROWS_DOWNWARD
)
27383 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
27385 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
27386 offset
= FRAME_GROWS_DOWNWARD
27387 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
27389 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
27390 offset
= info
->total_size
;
27391 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
27392 offset
= info
->push_p
? info
->total_size
: 0;
27393 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
27396 gcc_unreachable ();
27402 rs6000_dwarf_register_span (rtx reg
)
27406 unsigned regno
= REGNO (reg
);
27407 enum machine_mode mode
= GET_MODE (reg
);
27411 && (SPE_VECTOR_MODE (GET_MODE (reg
))
27412 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
27413 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
27418 regno
= REGNO (reg
);
27420 /* The duality of the SPE register size wreaks all kinds of havoc.
27421 This is a way of distinguishing r0 in 32-bits from r0 in
27423 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
27424 gcc_assert (words
<= 4);
27425 for (i
= 0; i
< words
; i
++, regno
++)
27427 if (BYTES_BIG_ENDIAN
)
27429 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
27430 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
27434 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
27435 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
27439 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
27442 /* Fill in sizes for SPE register high parts in table used by unwinder. */
27445 rs6000_init_dwarf_reg_sizes_extra (tree address
)
27450 enum machine_mode mode
= TYPE_MODE (char_type_node
);
27451 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
27452 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
27453 rtx value
= gen_int_mode (4, mode
);
27455 for (i
= 1201; i
< 1232; i
++)
27457 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
27458 HOST_WIDE_INT offset
27459 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
27461 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
27466 /* Map internal gcc register numbers to DWARF2 register numbers. */
27469 rs6000_dbx_register_number (unsigned int regno
)
27471 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
27473 if (regno
== LR_REGNO
)
27475 if (regno
== CTR_REGNO
)
27477 if (CR_REGNO_P (regno
))
27478 return regno
- CR0_REGNO
+ 86;
27479 if (regno
== CA_REGNO
)
27480 return 101; /* XER */
27481 if (ALTIVEC_REGNO_P (regno
))
27482 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
27483 if (regno
== VRSAVE_REGNO
)
27485 if (regno
== VSCR_REGNO
)
27487 if (regno
== SPE_ACC_REGNO
)
27489 if (regno
== SPEFSCR_REGNO
)
27491 /* SPE high reg number. We get these values of regno from
27492 rs6000_dwarf_register_span. */
27493 gcc_assert (regno
>= 1200 && regno
< 1232);
27497 /* target hook eh_return_filter_mode */
27498 static enum machine_mode
27499 rs6000_eh_return_filter_mode (void)
27501 return TARGET_32BIT
? SImode
: word_mode
;
27504 /* Target hook for scalar_mode_supported_p. */
27506 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
27508 if (DECIMAL_FLOAT_MODE_P (mode
))
27509 return default_decimal_float_supported_p ();
27511 return default_scalar_mode_supported_p (mode
);
27514 /* Target hook for vector_mode_supported_p. */
27516 rs6000_vector_mode_supported_p (enum machine_mode mode
)
27519 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
27522 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
27525 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
27532 /* Target hook for invalid_arg_for_unprototyped_fn. */
27533 static const char *
27534 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
27536 return (!rs6000_darwin64_abi
27538 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
27539 && (funcdecl
== NULL_TREE
27540 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
27541 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
27542 ? N_("AltiVec argument passed to unprototyped function")
27546 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
27547 setup by using __stack_chk_fail_local hidden function instead of
27548 calling __stack_chk_fail directly. Otherwise it is better to call
27549 __stack_chk_fail directly. */
27551 static tree ATTRIBUTE_UNUSED
27552 rs6000_stack_protect_fail (void)
27554 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
27555 ? default_hidden_stack_protect_fail ()
27556 : default_external_stack_protect_fail ();
27560 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
27561 int num_operands ATTRIBUTE_UNUSED
)
27563 if (rs6000_warn_cell_microcode
)
27566 int insn_code_number
= recog_memoized (insn
);
27567 location_t location
= INSN_LOCATION (insn
);
27569 /* Punt on insns we cannot recognize. */
27570 if (insn_code_number
< 0)
27573 temp
= get_insn_template (insn_code_number
, insn
);
27575 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
27576 warning_at (location
, OPT_mwarn_cell_microcode
,
27577 "emitting microcode insn %s\t[%s] #%d",
27578 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
27579 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
27580 warning_at (location
, OPT_mwarn_cell_microcode
,
27581 "emitting conditional microcode insn %s\t[%s] #%d",
27582 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
27586 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
27589 static unsigned HOST_WIDE_INT
27590 rs6000_asan_shadow_offset (void)
27592 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
27596 /* Mask options that we want to support inside of attribute((target)) and
27597 #pragma GCC target operations. Note, we do not include things like
27598 64/32-bit, endianess, hard/soft floating point, etc. that would have
27599 different calling sequences. */
27601 struct rs6000_opt_mask
{
27602 const char *name
; /* option name */
27603 HOST_WIDE_INT mask
; /* mask to set */
27604 bool invert
; /* invert sense of mask */
27605 bool valid_target
; /* option is a target option */
27608 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
27610 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
27611 { "cmpb", OPTION_MASK_CMPB
, false, true },
27612 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
27613 { "fprnd", OPTION_MASK_FPRND
, false, true },
27614 { "hard-dfp", OPTION_MASK_DFP
, false, true },
27615 { "isel", OPTION_MASK_ISEL
, false, true },
27616 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
27617 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
27618 { "mulhw", OPTION_MASK_MULHW
, false, true },
27619 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
27620 { "update", OPTION_MASK_NO_UPDATE
, true , true },
27621 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
27622 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
27623 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
27624 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
27625 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
27626 { "string", OPTION_MASK_STRING
, false, true },
27627 { "vsx", OPTION_MASK_VSX
, false, true },
27628 #ifdef OPTION_MASK_64BIT
27630 { "aix64", OPTION_MASK_64BIT
, false, false },
27631 { "aix32", OPTION_MASK_64BIT
, true, false },
27633 { "64", OPTION_MASK_64BIT
, false, false },
27634 { "32", OPTION_MASK_64BIT
, true, false },
27637 #ifdef OPTION_MASK_EABI
27638 { "eabi", OPTION_MASK_EABI
, false, false },
27640 #ifdef OPTION_MASK_LITTLE_ENDIAN
27641 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
27642 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
27644 #ifdef OPTION_MASK_RELOCATABLE
27645 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
27647 #ifdef OPTION_MASK_STRICT_ALIGN
27648 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
27650 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
27651 { "string", OPTION_MASK_STRING
, false, false },
27654 /* Builtin mask mapping for printing the flags. */
27655 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
27657 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
27658 { "vsx", RS6000_BTM_VSX
, false, false },
27659 { "spe", RS6000_BTM_SPE
, false, false },
27660 { "paired", RS6000_BTM_PAIRED
, false, false },
27661 { "fre", RS6000_BTM_FRE
, false, false },
27662 { "fres", RS6000_BTM_FRES
, false, false },
27663 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
27664 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
27665 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
27666 { "cell", RS6000_BTM_CELL
, false, false },
27669 /* Option variables that we want to support inside attribute((target)) and
27670 #pragma GCC target operations. */
27672 struct rs6000_opt_var
{
27673 const char *name
; /* option name */
27674 size_t global_offset
; /* offset of the option in global_options. */
27675 size_t target_offset
; /* offset of the option in target optiosn. */
27678 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
27681 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
27682 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
27683 { "avoid-indexed-addresses",
27684 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
27685 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
27687 offsetof (struct gcc_options
, x_rs6000_paired_float
),
27688 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
27690 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
27691 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
27694 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27695 parsing. Return true if there were no errors. */
27698 rs6000_inner_target_options (tree args
, bool attr_p
)
27702 if (args
== NULL_TREE
)
27705 else if (TREE_CODE (args
) == STRING_CST
)
27707 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
27710 while ((q
= strtok (p
, ",")) != NULL
)
27712 bool error_p
= false;
27713 bool not_valid_p
= false;
27714 const char *cpu_opt
= NULL
;
27717 if (strncmp (q
, "cpu=", 4) == 0)
27719 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
27720 if (cpu_index
>= 0)
27721 rs6000_cpu_index
= cpu_index
;
27728 else if (strncmp (q
, "tune=", 5) == 0)
27730 int tune_index
= rs6000_cpu_name_lookup (q
+5);
27731 if (tune_index
>= 0)
27732 rs6000_tune_index
= tune_index
;
27742 bool invert
= false;
27746 if (strncmp (r
, "no-", 3) == 0)
27752 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
27753 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
27755 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
27757 if (!rs6000_opt_masks
[i
].valid_target
)
27758 not_valid_p
= true;
27762 rs6000_isa_flags_explicit
|= mask
;
27764 /* VSX needs altivec, so -mvsx automagically sets
27766 if (mask
== OPTION_MASK_VSX
&& !invert
)
27767 mask
|= OPTION_MASK_ALTIVEC
;
27769 if (rs6000_opt_masks
[i
].invert
)
27773 rs6000_isa_flags
&= ~mask
;
27775 rs6000_isa_flags
|= mask
;
27780 if (error_p
&& !not_valid_p
)
27782 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
27783 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
27785 size_t j
= rs6000_opt_vars
[i
].global_offset
;
27786 *((int *) ((char *)&global_options
+ j
)) = !invert
;
27795 const char *eprefix
, *esuffix
;
27800 eprefix
= "__attribute__((__target__(";
27805 eprefix
= "#pragma GCC target ";
27810 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
27812 else if (not_valid_p
)
27813 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
27815 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
27820 else if (TREE_CODE (args
) == TREE_LIST
)
27824 tree value
= TREE_VALUE (args
);
27827 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
27831 args
= TREE_CHAIN (args
);
27833 while (args
!= NULL_TREE
);
27837 gcc_unreachable ();
27842 /* Print out the target options as a list for -mdebug=target. */
27845 rs6000_debug_target_options (tree args
, const char *prefix
)
27847 if (args
== NULL_TREE
)
27848 fprintf (stderr
, "%s<NULL>", prefix
);
27850 else if (TREE_CODE (args
) == STRING_CST
)
27852 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
27855 while ((q
= strtok (p
, ",")) != NULL
)
27858 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
27863 else if (TREE_CODE (args
) == TREE_LIST
)
27867 tree value
= TREE_VALUE (args
);
27870 rs6000_debug_target_options (value
, prefix
);
27873 args
= TREE_CHAIN (args
);
27875 while (args
!= NULL_TREE
);
27879 gcc_unreachable ();
27885 /* Hook to validate attribute((target("..."))). */
27888 rs6000_valid_attribute_p (tree fndecl
,
27889 tree
ARG_UNUSED (name
),
27893 struct cl_target_option cur_target
;
27895 tree old_optimize
= build_optimization_node ();
27896 tree new_target
, new_optimize
;
27897 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
27899 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
27901 if (TARGET_DEBUG_TARGET
)
27903 tree tname
= DECL_NAME (fndecl
);
27904 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
27906 fprintf (stderr
, "function: %.*s\n",
27907 (int) IDENTIFIER_LENGTH (tname
),
27908 IDENTIFIER_POINTER (tname
));
27910 fprintf (stderr
, "function: unknown\n");
27912 fprintf (stderr
, "args:");
27913 rs6000_debug_target_options (args
, " ");
27914 fprintf (stderr
, "\n");
27917 fprintf (stderr
, "flags: 0x%x\n", flags
);
27919 fprintf (stderr
, "--------------------\n");
27922 old_optimize
= build_optimization_node ();
27923 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
27925 /* If the function changed the optimization levels as well as setting target
27926 options, start with the optimizations specified. */
27927 if (func_optimize
&& func_optimize
!= old_optimize
)
27928 cl_optimization_restore (&global_options
,
27929 TREE_OPTIMIZATION (func_optimize
));
27931 /* The target attributes may also change some optimization flags, so update
27932 the optimization options if necessary. */
27933 cl_target_option_save (&cur_target
, &global_options
);
27934 rs6000_cpu_index
= rs6000_tune_index
= -1;
27935 ret
= rs6000_inner_target_options (args
, true);
27937 /* Set up any additional state. */
27940 ret
= rs6000_option_override_internal (false);
27941 new_target
= build_target_option_node ();
27946 new_optimize
= build_optimization_node ();
27953 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
27955 if (old_optimize
!= new_optimize
)
27956 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
27959 cl_target_option_restore (&global_options
, &cur_target
);
27961 if (old_optimize
!= new_optimize
)
27962 cl_optimization_restore (&global_options
,
27963 TREE_OPTIMIZATION (old_optimize
));
27969 /* Hook to validate the current #pragma GCC target and set the state, and
27970 update the macros based on what was changed. If ARGS is NULL, then
27971 POP_TARGET is used to reset the options. */
27974 rs6000_pragma_target_parse (tree args
, tree pop_target
)
27976 tree prev_tree
= build_target_option_node ();
27978 struct cl_target_option
*prev_opt
, *cur_opt
;
27979 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
27980 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
27982 if (TARGET_DEBUG_TARGET
)
27984 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
27985 fprintf (stderr
, "args:");
27986 rs6000_debug_target_options (args
, " ");
27987 fprintf (stderr
, "\n");
27991 fprintf (stderr
, "pop_target:\n");
27992 debug_tree (pop_target
);
27995 fprintf (stderr
, "pop_target: <NULL>\n");
27997 fprintf (stderr
, "--------------------\n");
28002 cur_tree
= ((pop_target
)
28004 : target_option_default_node
);
28005 cl_target_option_restore (&global_options
,
28006 TREE_TARGET_OPTION (cur_tree
));
28010 rs6000_cpu_index
= rs6000_tune_index
= -1;
28011 if (!rs6000_inner_target_options (args
, false)
28012 || !rs6000_option_override_internal (false)
28013 || (cur_tree
= build_target_option_node ()) == NULL_TREE
)
28015 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
28016 fprintf (stderr
, "invalid pragma\n");
28022 target_option_current_node
= cur_tree
;
28024 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
28025 change the macros that are defined. */
28026 if (rs6000_target_modify_macros_ptr
)
28028 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
28029 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
28030 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
28032 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
28033 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
28034 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
28036 diff_bumask
= (prev_bumask
^ cur_bumask
);
28037 diff_flags
= (prev_flags
^ cur_flags
);
28039 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
28041 /* Delete old macros. */
28042 rs6000_target_modify_macros_ptr (false,
28043 prev_flags
& diff_flags
,
28044 prev_bumask
& diff_bumask
);
28046 /* Define new macros. */
28047 rs6000_target_modify_macros_ptr (true,
28048 cur_flags
& diff_flags
,
28049 cur_bumask
& diff_bumask
);
28057 /* Remember the last target of rs6000_set_current_function. */
28058 static GTY(()) tree rs6000_previous_fndecl
;
28060 /* Establish appropriate back-end context for processing the function
28061 FNDECL. The argument might be NULL to indicate processing at top
28062 level, outside of any function scope. */
28064 rs6000_set_current_function (tree fndecl
)
28066 tree old_tree
= (rs6000_previous_fndecl
28067 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
28070 tree new_tree
= (fndecl
28071 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
28074 if (TARGET_DEBUG_TARGET
)
28076 bool print_final
= false;
28077 fprintf (stderr
, "\n==================== rs6000_set_current_function");
28080 fprintf (stderr
, ", fndecl %s (%p)",
28081 (DECL_NAME (fndecl
)
28082 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
28083 : "<unknown>"), (void *)fndecl
);
28085 if (rs6000_previous_fndecl
)
28086 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
28088 fprintf (stderr
, "\n");
28091 fprintf (stderr
, "\nnew fndecl target specific options:\n");
28092 debug_tree (new_tree
);
28093 print_final
= true;
28098 fprintf (stderr
, "\nold fndecl target specific options:\n");
28099 debug_tree (old_tree
);
28100 print_final
= true;
28104 fprintf (stderr
, "--------------------\n");
28107 /* Only change the context if the function changes. This hook is called
28108 several times in the course of compiling a function, and we don't want to
28109 slow things down too much or call target_reinit when it isn't safe. */
28110 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
28112 rs6000_previous_fndecl
= fndecl
;
28113 if (old_tree
== new_tree
)
28118 cl_target_option_restore (&global_options
,
28119 TREE_TARGET_OPTION (new_tree
));
28125 struct cl_target_option
*def
28126 = TREE_TARGET_OPTION (target_option_current_node
);
28128 cl_target_option_restore (&global_options
, def
);
28135 /* Save the current options */
28138 rs6000_function_specific_save (struct cl_target_option
*ptr
)
28140 ptr
->x_rs6000_isa_flags
= rs6000_isa_flags
;
28141 ptr
->x_rs6000_isa_flags_explicit
= rs6000_isa_flags_explicit
;
28144 /* Restore the current options */
28147 rs6000_function_specific_restore (struct cl_target_option
*ptr
)
28149 rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
28150 rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
28151 (void) rs6000_option_override_internal (false);
28154 /* Print the current options */
28157 rs6000_function_specific_print (FILE *file
, int indent
,
28158 struct cl_target_option
*ptr
)
28160 rs6000_print_isa_options (file
, indent
, "Isa options set",
28161 ptr
->x_rs6000_isa_flags
);
28163 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
28164 ptr
->x_rs6000_isa_flags_explicit
);
28167 /* Helper function to print the current isa or misc options on a line. */
28170 rs6000_print_options_internal (FILE *file
,
28172 const char *string
,
28173 HOST_WIDE_INT flags
,
28174 const char *prefix
,
28175 const struct rs6000_opt_mask
*opts
,
28176 size_t num_elements
)
28179 size_t start_column
= 0;
28181 size_t max_column
= 76;
28182 const char *comma
= "";
28183 const char *nl
= "\n";
28186 start_column
+= fprintf (file
, "%*s", indent
, "");
28190 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
28194 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
28196 /* Print the various mask options. */
28197 cur_column
= start_column
;
28198 for (i
= 0; i
< num_elements
; i
++)
28200 if ((flags
& opts
[i
].mask
) != 0)
28202 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
28203 size_t len
= (strlen (comma
)
28206 + strlen (rs6000_opt_masks
[i
].name
));
28209 if (cur_column
> max_column
)
28211 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
28212 cur_column
= start_column
+ len
;
28217 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
28218 rs6000_opt_masks
[i
].name
);
28219 flags
&= ~ opts
[i
].mask
;
28227 /* Helper function to print the current isa options on a line. */
28230 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
28231 HOST_WIDE_INT flags
)
28233 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
28234 &rs6000_opt_masks
[0],
28235 ARRAY_SIZE (rs6000_opt_masks
));
28239 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
28240 HOST_WIDE_INT flags
)
28242 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
28243 &rs6000_builtin_mask_names
[0],
28244 ARRAY_SIZE (rs6000_builtin_mask_names
));
28248 /* Hook to determine if one function can safely inline another. */
28251 rs6000_can_inline_p (tree caller
, tree callee
)
28254 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
28255 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
28257 /* If callee has no option attributes, then it is ok to inline. */
28261 /* If caller has no option attributes, but callee does then it is not ok to
28263 else if (!caller_tree
)
28268 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
28269 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
28271 /* Callee's options should a subset of the caller's, i.e. a vsx function
28272 can inline an altivec function but a non-vsx function can't inline a
28274 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
28275 == callee_opts
->x_rs6000_isa_flags
)
28279 if (TARGET_DEBUG_TARGET
)
28280 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
28281 (DECL_NAME (caller
)
28282 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
28284 (DECL_NAME (callee
)
28285 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
28287 (ret
? "can" : "cannot"));
28292 /* Allocate a stack temp and fixup the address so it meets the particular
28293 memory requirements (either offetable or REG+REG addressing). */
28296 rs6000_allocate_stack_temp (enum machine_mode mode
,
28297 bool offsettable_p
,
28300 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
28301 rtx addr
= XEXP (stack
, 0);
28302 int strict_p
= (reload_in_progress
|| reload_completed
);
28304 if (!legitimate_indirect_address_p (addr
, strict_p
))
28307 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
28308 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
28310 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
28311 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
28317 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
28318 to such a form to deal with memory reference instructions like STFIWX that
28319 only take reg+reg addressing. */
28322 rs6000_address_for_fpconvert (rtx x
)
28324 int strict_p
= (reload_in_progress
|| reload_completed
);
28327 gcc_assert (MEM_P (x
));
28328 addr
= XEXP (x
, 0);
28329 if (! legitimate_indirect_address_p (addr
, strict_p
)
28330 && ! legitimate_indexed_address_p (addr
, strict_p
))
28332 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
28334 rtx reg
= XEXP (addr
, 0);
28335 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
28336 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
28337 gcc_assert (REG_P (reg
));
28338 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
28341 else if (GET_CODE (addr
) == PRE_MODIFY
)
28343 rtx reg
= XEXP (addr
, 0);
28344 rtx expr
= XEXP (addr
, 1);
28345 gcc_assert (REG_P (reg
));
28346 gcc_assert (GET_CODE (expr
) == PLUS
);
28347 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
28351 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
28357 /* Given a memory reference, if it is not in the form for altivec memory
28358 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
28359 convert to the altivec format. */
28362 rs6000_address_for_altivec (rtx x
)
28364 gcc_assert (MEM_P (x
));
28365 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
28367 rtx addr
= XEXP (x
, 0);
28368 int strict_p
= (reload_in_progress
|| reload_completed
);
28370 if (!legitimate_indexed_address_p (addr
, strict_p
)
28371 && !legitimate_indirect_address_p (addr
, strict_p
))
28372 addr
= copy_to_mode_reg (Pmode
, addr
);
28374 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
28375 x
= change_address (x
, GET_MODE (x
), addr
);
28381 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
28383 On the RS/6000, all integer constants are acceptable, most won't be valid
28384 for particular insns, though. Only easy FP constants are acceptable. */
28387 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
28389 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
28392 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
28393 || GET_MODE (x
) == VOIDmode
28394 || (TARGET_POWERPC64
&& mode
== DImode
)
28395 || easy_fp_constant (x
, mode
)
28396 || easy_vector_constant (x
, mode
));
28400 /* A function pointer under AIX is a pointer to a data area whose first word
28401 contains the actual address of the function, whose second word contains a
28402 pointer to its TOC, and whose third word contains a value to place in the
28403 static chain register (r11). Note that if we load the static chain, our
28404 "trampoline" need not have any executable code. */
28407 rs6000_call_indirect_aix (rtx value
, rtx func_desc
, rtx flag
)
28413 rtx stack_toc_offset
;
28415 rtx func_toc_offset
;
28417 rtx func_sc_offset
;
28420 rtx (*call_func
) (rtx
, rtx
, rtx
, rtx
);
28421 rtx (*call_value_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
28423 stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
28424 toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
28426 /* Load up address of the actual function. */
28427 func_desc
= force_reg (Pmode
, func_desc
);
28428 func_addr
= gen_reg_rtx (Pmode
);
28429 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
28434 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_32BIT
);
28435 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_32BIT
);
28436 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_32BIT
);
28437 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28439 call_func
= gen_call_indirect_aix32bit
;
28440 call_value_func
= gen_call_value_indirect_aix32bit
;
28444 call_func
= gen_call_indirect_aix32bit_nor11
;
28445 call_value_func
= gen_call_value_indirect_aix32bit_nor11
;
28450 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_64BIT
);
28451 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_64BIT
);
28452 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_64BIT
);
28453 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28455 call_func
= gen_call_indirect_aix64bit
;
28456 call_value_func
= gen_call_value_indirect_aix64bit
;
28460 call_func
= gen_call_indirect_aix64bit_nor11
;
28461 call_value_func
= gen_call_value_indirect_aix64bit_nor11
;
28465 /* Reserved spot to store the TOC. */
28466 stack_toc_mem
= gen_frame_mem (Pmode
,
28467 gen_rtx_PLUS (Pmode
,
28469 stack_toc_offset
));
28472 gcc_assert (cfun
->machine
);
28474 /* Can we optimize saving the TOC in the prologue or do we need to do it at
28476 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
28477 cfun
->machine
->save_toc_in_prologue
= true;
28481 MEM_VOLATILE_P (stack_toc_mem
) = 1;
28482 emit_move_insn (stack_toc_mem
, toc_reg
);
28485 /* Calculate the address to load the TOC of the called function. We don't
28486 actually load this until the split after reload. */
28487 func_toc_mem
= gen_rtx_MEM (Pmode
,
28488 gen_rtx_PLUS (Pmode
,
28492 /* If we have a static chain, load it up. */
28493 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28495 func_sc_mem
= gen_rtx_MEM (Pmode
,
28496 gen_rtx_PLUS (Pmode
,
28500 sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
28501 emit_move_insn (sc_reg
, func_sc_mem
);
28504 /* Create the call. */
28506 insn
= call_value_func (value
, func_addr
, flag
, func_toc_mem
,
28509 insn
= call_func (func_addr
, flag
, func_toc_mem
, stack_toc_mem
);
28511 emit_call_insn (insn
);
28514 /* Return whether we need to always update the saved TOC pointer when we update
28515 the stack pointer. */
28518 rs6000_save_toc_in_prologue_p (void)
28520 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
28523 #ifdef HAVE_GAS_HIDDEN
28524 # define USE_HIDDEN_LINKONCE 1
28526 # define USE_HIDDEN_LINKONCE 0
28529 /* Fills in the label name that should be used for a 476 link stack thunk. */
28532 get_ppc476_thunk_name (char name
[32])
28534 gcc_assert (TARGET_LINK_STACK
);
28536 if (USE_HIDDEN_LINKONCE
)
28537 sprintf (name
, "__ppc476.get_thunk");
28539 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
28542 /* This function emits the simple thunk routine that is used to preserve
28543 the link stack on the 476 cpu. */
28545 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
28547 rs6000_code_end (void)
28552 if (!TARGET_LINK_STACK
)
28555 get_ppc476_thunk_name (name
);
28557 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
28558 build_function_type_list (void_type_node
, NULL_TREE
));
28559 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
28560 NULL_TREE
, void_type_node
);
28561 TREE_PUBLIC (decl
) = 1;
28562 TREE_STATIC (decl
) = 1;
28565 if (USE_HIDDEN_LINKONCE
)
28567 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
28568 targetm
.asm_out
.unique_section (decl
, 0);
28569 switch_to_section (get_named_section (decl
, NULL
, 0));
28570 DECL_WEAK (decl
) = 1;
28571 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
28572 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
28573 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
28574 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
28579 switch_to_section (text_section
);
28580 ASM_OUTPUT_LABEL (asm_out_file
, name
);
28583 DECL_INITIAL (decl
) = make_node (BLOCK
);
28584 current_function_decl
= decl
;
28585 init_function_start (decl
);
28586 first_function_block_is_cold
= false;
28587 /* Make sure unwind info is emitted for the thunk if needed. */
28588 final_start_function (emit_barrier (), asm_out_file
, 1);
28590 fputs ("\tblr\n", asm_out_file
);
28592 final_end_function ();
28593 init_insn_lengths ();
28594 free_after_compilation (cfun
);
28596 current_function_decl
= NULL
;
28599 /* Add r30 to hard reg set if the prologue sets it up and it is not
28600 pic_offset_table_rtx. */
28603 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
28605 if (!TARGET_SINGLE_PIC_BASE
28607 && TARGET_MINIMAL_TOC
28608 && get_pool_size () != 0)
28609 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
28612 struct gcc_target targetm
= TARGET_INITIALIZER
;
28614 #include "gt-rs6000.h"