| blob | 400cef3495a3faf08f7267765991bf278a1c5128 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 scalar_int_mode,
421 scalar_int_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1216 {
1219 }
1220 }
1221 }
1225 /* Now scan all the insns in forward order. */
1233 {
1236 /* Ignore instruction combination in basic blocks that are going to
1237 be removed as unreachable anyway. See PR82386. */
1245 label_tick++;
1255 {
1269 /* See if we know about function return values before this
1270 insn based upon SUBREG flags. */
1273 /* See if we can find hardregs and subreg of pseudos in
1274 narrower modes. This could help turning TRUNCATEs
1275 into SUBREGs. */
1278 /* Try this insn with each insn it links back to. */
1284 {
1287 }
1289 /* Try each sequence of three linked insns ending with this one. */
1293 {
1296 /* If the linked insn has been replaced by a note, then there
1297 is no point in pursuing this chain any further. */
1305 {
1308 }
1309 }
1311 /* Try to combine a jump insn that uses CC0
1312 with a preceding insn that sets CC0, and maybe with its
1313 logical predecessor as well.
1314 This is how we make decrement-and-branch insns.
1315 We need this special code because data flow connections
1316 via CC0 do not get entered in LOG_LINKS. */
1323 {
1334 }
1336 /* Do the same for an insn that explicitly references CC0. */
1343 {
1354 }
1356 /* Finally, see if any of the insns that this insn links to
1357 explicitly references CC0. If so, try this insn, that insn,
1358 and its predecessor if it sets CC0. */
1360 {
1372 }
1374 /* Try combining an insn with two different insns whose results it
1375 uses. */
1385 {
1388 }
1390 /* Try four-instruction combinations. */
1393 {
1397 /* If the linked insn has been replaced by a note, then there
1398 is no point in pursuing this chain any further. */
1403 {
1407 /* I0 -> I1 -> I2 -> I3. */
1413 {
1416 }
1417 /* I0, I1 -> I2, I2 -> I3. */
1424 {
1427 }
1428 }
1431 {
1435 /* I0 -> I2; I1, I2 -> I3. */
1441 {
1444 }
1445 /* I0 -> I1; I1, I2 -> I3. */
1451 {
1454 }
1455 }
1456 }
1458 /* Try this insn with each REG_EQUAL note it links back to. */
1460 {
1466 /* Avoid using a register that may already been marked
1467 dead by an earlier instruction. */
1475 {
1476 /* Temporarily replace the set's source with the
1477 contents of the REG_EQUAL note. The insn will
1478 be deleted or recognized by try_combine. */
1489 last_combined_insn);
1492 {
1495 }
1498 }
1499 }
1504 retry:
1505 ;
1506 }
1507 }
1514 /* Clean up. */
1520 {
1523 {
1526 }
1528 }
1538 /* Make recognizer allow volatile MEMs again. */
1542 }
1544 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1546 static void
1548 {
1554 }
1555 \f
1556 /* Set up any promoted values for incoming argument registers. */
1558 static void
1560 {
1561 tree arg;
1566 {
1571 /* Only continue if the incoming argument is in a register. */
1575 /* Determine, if possible, whether all call sites of the current
1576 function lie within the current compilation unit. (This does
1577 take into account the exporting of a function via taking its
1578 address, and so forth.) */
1581 /* The mode and signedness of the argument before any promotions happen
1582 (equal to the mode of the pseudo holding it at that stage). */
1586 /* The mode and signedness of the argument after any source language and
1587 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1591 /* The mode and signedness of the argument as it is actually passed,
1592 see assign_parm_setup_reg in function.c. */
1596 /* The mode of the register in which the argument is being passed. */
1599 /* Eliminate sign extensions in the callee when:
1600 (a) A mode promotion has occurred; */
1603 /* (b) The mode of the register is the same as the mode of
1604 the argument as it is passed; */
1607 /* (c) There's no language level extension; */
1609 ;
1610 /* (c.1) All callers are from the current compilation unit. If that's
1611 the case we don't have to rely on an ABI, we only have to know
1612 what we're generating right now, and we know that we will do the
1613 mode1 to mode2 promotion with the given sign. */
1616 /* (c.2) The combination of the two promotions is useful. This is
1617 true when the signs match, or if the first promotion is unsigned.
1618 In the later case, (sign_extend (zero_extend x)) is the same as
1619 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1625 /* Record that the value was promoted from mode1 to mode3,
1626 so that any sign extension at the head of the current
1627 function may be eliminated. */
1631 }
1632 }
1634 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1635 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1636 because some machines (maybe most) will actually do the sign-extension and
1637 this is the conservative approach.
1639 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1640 kludge. */
1642 static rtx
1644 {
1645 scalar_int_mode int_mode;
1654 }
1656 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1657 and SET. */
1659 static void
1661 rtx x)
1662 {
1672 {
1676 }
1678 /* Don't call nonzero_bits if it cannot change anything. */
1680 {
1685 }
1687 /* Don't call num_sign_bit_copies if it cannot change anything. */
1689 {
1692 {
1696 }
1699 }
1700 }
1702 /* Called via note_stores. If X is a pseudo that is narrower than
1703 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1705 If we are setting only a portion of X and we can't figure out what
1706 portion, assume all bits will be used since we don't know what will
1707 be happening.
1709 Similarly, set how many bits of X are known to be copies of the sign bit
1710 at all locations in the function. This is the smallest number implied
1711 by any set of X. */
1713 static void
1715 {
1717 scalar_int_mode mode;
1721 /* If this register is undefined at the start of the file, we can't
1722 say what its contents were. */
1723 && ! REGNO_REG_SET_P
1727 {
1731 {
1735 }
1737 /* If this register is being initialized using itself, and the
1738 register is uninitialized in this basic block, and there are
1739 no LOG_LINKS which set the register, then part of the
1740 register is uninitialized. In that case we can't assume
1741 anything about the number of nonzero bits.
1743 ??? We could do better if we checked this in
1744 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1745 could avoid making assumptions about the insn which initially
1746 sets the register, while still using the information in other
1747 insns. We would have to be careful to check every insn
1748 involved in the combination. */
1754 {
1761 {
1765 }
1766 }
1768 /* If this is a complex assignment, see if we can convert it into a
1769 simple assignment. */
1772 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1773 set what we know about X. */
1779 else
1780 {
1783 }
1784 }
1785 }
1786 \f
1787 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1788 optionally insns that were previously combined into I3 or that will be
1789 combined into the merger of INSN and I3. The order is PRED, PRED2,
1790 INSN, SUCC, SUCC2, I3.
1792 Return 0 if the combination is not allowed for any reason.
1794 If the combination is allowed, *PDEST will be set to the single
1795 destination of INSN and *PSRC to the single source, and this function
1796 will return 1. */
1798 static int
1802 {
1807 rtx link;
1812 {
1814 {
1819 }
1824 }
1828 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1829 or a PARALLEL consisting of such a SET and CLOBBERs.
1831 If INSN has CLOBBER parallel parts, ignore them for our processing.
1832 By definition, these happen during the execution of the insn. When it
1833 is merged with another insn, all bets are off. If they are, in fact,
1834 needed and aren't also supplied in I3, they may be added by
1835 recog_for_combine. Otherwise, it won't match.
1837 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1838 note.
1840 Get the source and destination of INSN. If more than one, can't
1841 combine. */
1847 {
1849 {
1853 {
1854 /* This is important to combine floating point insns
1855 for the SH4 port. */
1857 /* Combining an isolated USE doesn't make sense.
1858 We depend here on combinable_i3pat to reject them. */
1859 /* The code below this loop only verifies that the inputs of
1860 the SET in INSN do not change. We call reg_set_between_p
1861 to verify that the REG in the USE does not change between
1862 I3 and INSN.
1863 If the USE in INSN was for a pseudo register, the matching
1864 insn pattern will likely match any register; combining this
1865 with any other USE would only be safe if we knew that the
1866 used registers have identical values, or if there was
1867 something to tell them apart, e.g. different modes. For
1868 now, we forgo such complicated tests and simply disallow
1869 combining of USES of pseudo registers with any other USE. */
1872 {
1877 do
1878 {
1888 }
1890 }
1893 /* We can ignore CLOBBERs. */
1898 /* Ignore SETs whose result isn't used but not those that
1899 have side-effects. */
1905 /* If we have already found a SET, this is a second one and
1906 so we cannot combine with this insn. */
1914 /* Anything else means we can't combine. */
1916 }
1917 }
1920 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1921 so don't do anything with it. */
1924 }
1925 else
1931 /* The simplification in expand_field_assignment may call back to
1932 get_last_value, so set safe guard here. */
1938 /* Do not eliminate user-specified register if it is in an
1939 asm input because we may break the register asm usage defined
1940 in GCC manual if allow to do so.
1941 Be aware that this may cover more cases than we expect but this
1942 should be harmless. */
1947 /* Don't eliminate a store in the stack pointer. */
1949 /* Don't combine with an insn that sets a register to itself if it has
1950 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1952 /* Can't merge an ASM_OPERANDS. */
1954 /* Can't merge a function call. */
1956 /* Don't eliminate a function call argument. */
1962 /* Don't substitute into an incremented register. */
1966 /* Don't substitute into a non-local goto, this confuses CFG. */
1968 /* Make sure that DEST is not used after INSN but before SUCC, or
1969 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1970 || (!all_adjacent
1971 && ((succ2
1975 || (succ
1976 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1977 that case SUCC is not in the insn stream, so use SUCC2
1978 instead for this test. */
1980 succ2
1983 /* Make sure that the value that is to be substituted for the register
1984 does not use any registers whose values alter in between. However,
1985 If the insns are adjacent, a use can't cross a set even though we
1986 think it might (this can happen for a sequence of insns each setting
1987 the same destination; last_set of that register might point to
1988 a NOTE). If INSN has a REG_EQUIV note, the register is always
1989 equivalent to the memory so the substitution is valid even if there
1990 are intervening stores. Also, don't move a volatile asm or
1991 UNSPEC_VOLATILE across any other insns. */
1992 || (! all_adjacent
1998 /* Don't combine across a CALL_INSN, because that would possibly
1999 change whether the life span of some REGs crosses calls or not,
2000 and it is a pain to update that information.
2001 Exception: if source is a constant, moving it later can't hurt.
2002 Accept that as a special case. */
2006 /* DEST must either be a REG or CC0. */
2008 {
2009 /* If register alignment is being enforced for multi-word items in all
2010 cases except for parameters, it is possible to have a register copy
2011 insn referencing a hard register that is not allowed to contain the
2012 mode being copied and which would not be valid as an operand of most
2013 insns. Eliminate this problem by not combining with such an insn.
2015 Also, on some machines we don't want to extend the life of a hard
2016 register. */
2021 /* Don't extend the life of a hard register unless it is
2022 user variable (if we have few registers) or it can't
2023 fit into the desired register (meaning something special
2024 is going on).
2025 Also avoid substituting a return register into I3, because
2026 reload can't handle a conflict with constraints of other
2027 inputs. */
2032 }
2040 {
2043 /* If the clobber represents an earlyclobber operand, we must not
2044 substitute an expression containing the clobbered register.
2045 As we do not analyze the constraint strings here, we have to
2046 make the conservative assumption. However, if the register is
2047 a fixed hard reg, the clobber cannot represent any operand;
2048 we leave it up to the machine description to either accept or
2049 reject use-and-clobber patterns. */
2055 }
2057 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2058 or not), reject, unless nothing volatile comes between it and I3 */
2061 {
2062 /* Make sure neither succ nor succ2 contains a volatile reference. */
2067 /* We'll check insns between INSN and I3 below. */
2068 }
2070 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2071 to be an explicit register variable, and was chosen for a reason. */
2077 /* If INSN contains volatile references (specifically volatile MEMs),
2078 we cannot combine across any other volatile references.
2079 Even if INSN doesn't contain volatile references, any intervening
2080 volatile insn might affect machine state. */
2083 ? volatile_refs_p
2090 /* If INSN contains an autoincrement or autodecrement, make sure that
2091 register is not used between there and I3, and not already used in
2092 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2093 Also insist that I3 not be a jump; if it were one
2094 and the incremented register were spilled, we would lose. */
2112 /* Don't combine an insn that follows a CC0-setting insn.
2113 An insn that uses CC0 must not be separated from the one that sets it.
2114 We do, however, allow I2 to follow a CC0-setting insn if that insn
2115 is passed as I1; in that case it will be deleted also.
2116 We also allow combining in this case if all the insns are adjacent
2117 because that would leave the two CC0 insns adjacent as well.
2118 It would be more logical to test whether CC0 occurs inside I1 or I2,
2119 but that would be much slower, and this ought to be equivalent. */
2122 {
2127 }
2129 /* If we get here, we have passed all the tests and the combination is
2130 to be allowed. */
2136 }
2137 \f
2138 /* LOC is the location within I3 that contains its pattern or the component
2139 of a PARALLEL of the pattern. We validate that it is valid for combining.
2141 One problem is if I3 modifies its output, as opposed to replacing it
2142 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2143 doing so would produce an insn that is not equivalent to the original insns.
2145 Consider:
2147 (set (reg:DI 101) (reg:DI 100))
2148 (set (subreg:SI (reg:DI 101) 0) <foo>)
2150 This is NOT equivalent to:
2152 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2153 (set (reg:DI 101) (reg:DI 100))])
2155 Not only does this modify 100 (in which case it might still be valid
2156 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2158 We can also run into a problem if I2 sets a register that I1
2159 uses and I1 gets directly substituted into I3 (not via I2). In that
2160 case, we would be getting the wrong value of I2DEST into I3, so we
2161 must reject the combination. This case occurs when I2 and I1 both
2162 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2163 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2164 of a SET must prevent combination from occurring. The same situation
2165 can occur for I0, in which case I0_NOT_IN_SRC is set.
2167 Before doing the above check, we first try to expand a field assignment
2168 into a set of logical operations.
2170 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2171 we place a register that is both set and used within I3. If more than one
2172 such register is detected, we fail.
2174 Return 1 if the combination is valid, zero otherwise. */
2176 static int
2179 {
2183 {
2188 rtx subdest;
2195 /* Check for the case where I3 modifies its output, as discussed
2196 above. We don't want to prevent pseudos from being combined
2197 into the address of a MEM, so only prevent the combination if
2198 i1 or i2 set the same MEM. */
2208 /* This is the same test done in can_combine_p except we can't test
2209 all_adjacent; we don't have to, since this instruction will stay
2210 in place, thus we are not considering increasing the lifetime of
2211 INNER_DEST.
2213 Also, if this insn sets a function argument, combining it with
2214 something that might need a spill could clobber a previous
2215 function argument; the all_adjacent test in can_combine_p also
2216 checks this; here, we do a more specific test for this case. */
2226 /* If DEST is used in I3, it is being killed in this insn, so
2227 record that for later. We have to consider paradoxical
2228 subregs here, since they kill the whole register, but we
2229 ignore partial subregs, STRICT_LOW_PART, etc.
2230 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2231 STACK_POINTER_REGNUM, since these are always considered to be
2232 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2240 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2246 {
2251 }
2252 }
2255 {
2262 }
2265 }
2266 \f
2267 /* Return 1 if X is an arithmetic expression that contains a multiplication
2268 and division. We don't count multiplications by powers of two here. */
2270 static int
2272 {
2274 {
2290 }
2291 }
2292 \f
2293 /* Determine whether INSN can be used in a combination. Return nonzero if
2294 not. This is used in try_combine to detect early some cases where we
2295 can't perform combinations. */
2297 static int
2299 {
2300 rtx set;
2303 /* If this isn't really an insn, we can't do anything.
2304 This can occur when flow deletes an insn that it has merged into an
2305 auto-increment address. */
2309 /* Never combine loads and stores involving hard regs that are likely
2310 to be spilled. The register allocator can usually handle such
2311 reg-reg moves by tying. If we allow the combiner to make
2312 substitutions of likely-spilled regs, reload might die.
2313 As an exception, we allow combinations involving fixed regs; these are
2314 not available to the register allocator so there's no risk involved. */
2335 }
2337 struct likely_spilled_retval_info
2338 {
2341 };
2343 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2344 hard registers that are known to be written to / clobbered in full. */
2345 static void
2347 {
2364 else
2367 }
2369 /* Return nonzero iff part of the return value is live during INSN, and
2370 it is likely spilled. This can happen when more than one insn is needed
2371 to copy the return value, e.g. when we consider to combine into the
2372 second copy insn for a complex value. */
2374 static int
2376 {
2378 rtx reg;
2381 /* We assume here that no machine mode needs more than
2382 32 hard registers when the value overlaps with a register
2383 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2398 /* Disregard parts of the return value that are set later. */
2407 /* Check if any of the (probably) live return value registers is
2408 likely spilled. */
2409 nregs --;
2410 do
2411 {
2417 }
2419 /* Adjust INSN after we made a change to its destination.
2421 Changing the destination can invalidate notes that say something about
2422 the results of the insn and a LOG_LINK pointing to the insn. */
2424 static void
2426 {
2427 /* For notes, be conservative and simply remove them. */
2430 /* The new insn will have a destination that was previously the destination
2431 of an insn just above it. Call distribute_links to make a LOG_LINK from
2432 the next use of that destination. */
2448 }
2450 /* Return TRUE if combine can reuse reg X in mode MODE.
2451 ADDED_SETS is nonzero if the original set is still required. */
2452 static bool
2454 {
2461 /* Allow hard registers if the new mode is legal, and occupies no more
2462 registers than the old mode. */
2467 /* Or a pseudo that is only used once. */
2470 && !added_sets
2472 }
2475 /* Check whether X, the destination of a set, refers to part of
2476 the register specified by REG. */
2478 static bool
2480 {
2481 /* Check that reg is an integer mode register. */
2492 }
2494 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2495 Note that the INSN should be deleted *after* removing dead edges, so
2496 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2497 but not for a (set (pc) (label_ref FOO)). */
2499 static void
2501 {
2509 {
2514 /* Remove barriers from the footer if there are any. */
2517 {
2520 else
2524 }
2527 }
2528 }
2530 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2531 by an arbitrary number of CLOBBERs. */
2532 static bool
2534 {
2553 }
2555 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2556 CLOBBERs), can be split into individual SETs in that order, without
2557 changing semantics. */
2558 static bool
2560 {
2568 {
2577 }
2580 }
2582 /* Try to combine the insns I0, I1 and I2 into I3.
2583 Here I0, I1 and I2 appear earlier than I3.
2584 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2585 I3.
2587 If we are combining more than two insns and the resulting insn is not
2588 recognized, try splitting it into two insns. If that happens, I2 and I3
2589 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2590 Otherwise, I0, I1 and I2 are pseudo-deleted.
2592 Return 0 if the combination does not work. Then nothing is changed.
2593 If we did the combination, return the insn at which combine should
2594 resume scanning.
2596 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2597 new direct jump instruction.
2599 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2600 been I3 passed to an earlier try_combine within the same basic
2601 block. */
2606 {
2607 /* New patterns for I3 and I2, respectively. */
2611 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2612 dead. */
2614 /* Total number of SETs to put into I3. */
2616 /* Nonzero if I2's or I1's body now appears in I3. */
2618 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2620 /* Contains I3 if the destination of I3 is used in its source, which means
2621 that the old life of I3 is being killed. If that usage is placed into
2622 I2 and not in I3, a REG_DEAD note must be made. */
2624 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2626 /* Copy of SET_SRC of I1 and I0, if needed. */
2628 /* Set if I2DEST was reused as a scratch register. */
2630 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2632 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2637 /* Notes that must be added to REG_NOTES in I3 and I2. */
2639 /* Notes that we substituted I3 into I2 instead of the normal case. */
2641 /* Notes that I1, I2 or I3 is a MULT operation. */
2648 rtx temp_expr;
2651 rtx new_other_notes;
2655 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2656 never be). */
2660 /* Only try four-insn combinations when there's high likelihood of
2661 success. Look for simple insns, such as loads of constants or
2662 binary operations involving a constant. */
2664 {
2674 {
2677 rtx src;
2682 {
2685 }
2687 ngood++;
2690 nshift++;
2691 }
2693 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2694 are likely manipulating its value. Ideally we'll be able to combine
2695 all four insns into a bitfield insertion of some kind.
2697 Note the source in I0 might be inside a sign/zero extension and the
2698 memory modes in I0 and I3 might be different. So extract the address
2699 from the destination of I3 and search for it in the source of I0.
2701 In the event that there's a match but the source/dest do not actually
2702 refer to the same memory, the worst that happens is we try some
2703 combinations that we wouldn't have otherwise. */
2705 /* Ensure the source of SET0 is a MEM, possibly buried inside
2706 an extension. */
2712 /* Ensure the destination of SET3 is a MEM. */
2714 /* Would it be better to extract the base address for the MEM
2715 in SET3 and look for that? I don't have cases where it matters
2716 but I could envision such cases. */
2722 }
2724 /* Exit early if one of the insns involved can't be used for
2725 combinations. */
2736 combine_attempts++;
2739 /* Reset the hard register usage information. */
2743 {
2750 else
2753 }
2755 /* If multiple insns feed into one of I2 or I3, they can be in any
2756 order. To simplify the code below, reorder them in sequence. */
2766 /* First check for one important special case that the code below will
2767 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2768 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2769 we may be able to replace that destination with the destination of I3.
2770 This occurs in the common code where we compute both a quotient and
2771 remainder into a structure, in which case we want to do the computation
2772 directly into the structure to avoid register-register copies.
2774 Note that this case handles both multiple sets in I2 and also cases
2775 where I2 has a number of CLOBBERs inside the PARALLEL.
2777 We make very conservative checks below and only try to handle the
2778 most common cases of this. For example, we only handle the case
2779 where I2 and I3 are adjacent to avoid making difficult register
2780 usage tests. */
2788 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2789 below would need to check what is inside (and reg_overlap_mentioned_p
2790 doesn't support those codes anyway). Don't allow those destinations;
2791 the resulting insn isn't likely to be recognized anyway. */
2797 {
2800 /* Make sure that the destination of I3,
2801 which we are going to substitute into one output of I2,
2802 is not used within another output of I2. We must avoid making this:
2803 (parallel [(set (mem (reg 69)) ...)
2804 (set (reg 69) ...)])
2805 which is not well-defined as to order of actions.
2806 (Besides, reload can't handle output reloads for this.)
2808 The problem can also happen if the dest of I3 is a memory ref,
2809 if another dest in I2 is an indirect memory ref.
2811 Neither can this PARALLEL be an asm. We do not allow combining
2812 that usually (see can_combine_p), so do not here either. */
2815 {
2824 }
2830 {
2831 combine_merges++;
2841 /* Replace the dest in I2 with our dest and make the resulting
2842 insn the new pattern for I3. Then skip to where we validate
2843 the pattern. Everything was set up above. */
2848 }
2849 }
2851 /* If I2 is setting a pseudo to a constant and I3 is setting some
2852 sub-part of it to another constant, merge them by making a new
2853 constant. */
2861 {
2868 {
2873 {
2879 }
2880 }
2881 else
2882 {
2886 {
2889 }
2890 }
2893 {
2894 /* If this is the low part, we're done. */
2896 ;
2897 /* Handle the case where inner is twice the size of outer. */
2901 /* Otherwise give up for now. */
2902 else
2904 }
2907 {
2915 combine_merges++;
2922 /* Replace the source in I2 with the new constant and make the
2923 resulting insn the new pattern for I3. Then skip to where we
2924 validate the pattern. Everything was set up above. */
2930 /* The dest of I3 has been replaced with the dest of I2. */
2933 }
2934 }
2936 /* If we have no I1 and I2 looks like:
2937 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2938 (set Y OP)])
2939 make up a dummy I1 that is
2940 (set Y OP)
2941 and change I2 to be
2942 (set (reg:CC X) (compare:CC Y (const_int 0)))
2944 (We can ignore any trailing CLOBBERs.)
2946 This undoes a previous combination and allows us to match a branch-and-
2947 decrement insn. */
2959 {
2960 /* We make I1 with the same INSN_UID as I2. This gives it
2961 the same DF_INSN_LUID for value tracking. Our fake I1 will
2962 never appear in the insn stream so giving it the same INSN_UID
2963 as I2 will not cause a problem. */
2976 }
2978 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2979 make those two SETs separate I1 and I2 insns, and make an I0 that is
2980 the original I1. */
2986 {
2987 /* If there is no I1, there is no I0 either. */
2990 /* We make I1 with the same INSN_UID as I2. This gives it
2991 the same DF_INSN_LUID for value tracking. Our fake I1 will
2992 never appear in the insn stream so giving it the same INSN_UID
2993 as I2 will not cause a problem. */
3001 }
3003 /* Verify that I2 and I1 are valid for combining. */
3009 {
3012 }
3014 /* Record whether I2DEST is used in I2SRC and similarly for the other
3015 cases. Knowing this will help in register status updating below. */
3026 /* For the earlier insns, determine which of the subsequent ones they
3027 feed. */
3034 /* Ensure that I3's pattern can be the destination of combines. */
3040 {
3043 }
3045 /* See if any of the insns is a MULT operation. Unless one is, we will
3046 reject a combination that is, since it must be slower. Be conservative
3047 here. */
3055 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3056 We used to do this EXCEPT in one case: I3 has a post-inc in an
3057 output operand. However, that exception can give rise to insns like
3058 mov r3,(r3)+
3059 which is a famous insn on the PDP-11 where the value of r3 used as the
3060 source was model-dependent. Avoid this sort of thing. */
3062 #if 0
3068 /* It's not the exception. */
3069 #endif
3071 {
3072 rtx link;
3078 {
3081 }
3082 }
3084 /* See if the SETs in I1 or I2 need to be kept around in the merged
3085 instruction: whenever the value set there is still needed past I3.
3086 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3088 For the SET in I1, we have two cases: if I1 and I2 independently feed
3089 into I3, the set in I1 needs to be kept around unless I1DEST dies
3090 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3091 in I1 needs to be kept around unless I1DEST dies or is set in either
3092 I2 or I3. The same considerations apply to I0. */
3099 else
3107 else
3110 /* We are about to copy insns for the case where they need to be kept
3111 around. Check that they can be copied in the merged instruction. */
3117 {
3120 }
3122 /* If the set in I2 needs to be kept around, we must make a copy of
3123 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3124 PATTERN (I2), we are only substituting for the original I1DEST, not into
3125 an already-substituted copy. This also prevents making self-referential
3126 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3127 I2DEST. */
3130 {
3133 else
3135 }
3138 {
3141 else
3143 }
3146 {
3149 else
3151 }
3153 combine_merges++;
3155 /* Substitute in the latest insn for the regs set by the earlier ones. */
3161 /* Many machines that don't use CC0 have insns that can both perform an
3162 arithmetic operation and set the condition code. These operations will
3163 be represented as a PARALLEL with the first element of the vector
3164 being a COMPARE of an arithmetic operation with the constant zero.
3165 The second element of the vector will set some pseudo to the result
3166 of the same arithmetic operation. If we simplify the COMPARE, we won't
3167 match such a pattern and so will generate an extra insn. Here we test
3168 for this case, where both the comparison and the operation result are
3169 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3170 I2SRC. Later we will make the PARALLEL that contains I2. */
3176 {
3177 rtx newpat_dest;
3183 scalar_int_mode mode;
3192 {
3198 }
3200 /* Do the rest only if op1 is const0_rtx, which may be the
3201 result of simplification. */
3203 {
3204 /* If a single use of the CC is found, prepare to modify it
3205 when SELECT_CC_MODE returns a new CC-class mode, or when
3206 the above simplify_compare_const() returned a new comparison
3207 operator. undobuf.other_insn is assigned the CC use insn
3208 when modifying it. */
3210 {
3211 #ifdef SELECT_CC_MODE
3212 machine_mode new_mode
3217 {
3222 else
3223 {
3226 }
3227 }
3228 #endif
3229 /* Cases for modifying the CC-using comparison. */
3231 /* ??? Do we need to verify the zero rtx? */
3233 {
3234 /* Replace cc_use_loc with entire new RTX. */
3239 }
3241 {
3242 /* Just replace the CC reg with a new mode. */
3245 }
3246 }
3248 /* Now we modify the current newpat:
3249 First, SET_DEST(newpat) is updated if the CC mode has been
3250 altered. For targets without SELECT_CC_MODE, this should be
3251 optimized away. */
3254 /* This is always done to propagate i2src into newpat. */
3257 /* Create new version of i2pat if needed; the below PARALLEL
3258 creation needs this to work correctly. */
3262 }
3263 }
3266 {
3267 /* It is possible that the source of I2 or I1 may be performing
3268 an unneeded operation, such as a ZERO_EXTEND of something
3269 that is known to have the high part zero. Handle that case
3270 by letting subst look at the inner insns.
3272 Another way to do this would be to have a function that tries
3273 to simplify a single insn instead of merging two or more
3274 insns. We don't do this because of the potential of infinite
3275 loops and because of the potential extra memory required.
3276 However, doing it the way we are is a bit of a kludge and
3277 doesn't catch all cases.
3279 But only do this if -fexpensive-optimizations since it slows
3280 things down and doesn't usually win.
3282 This is not done in the COMPARE case above because the
3283 unmodified I2PAT is used in the PARALLEL and so a pattern
3284 with a modified I2SRC would not match. */
3287 {
3288 /* Pass pc_rtx so no substitutions are done, just
3289 simplifications. */
3291 {
3294 }
3298 }
3303 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3304 copy of I2SRC each time we substitute it, in order to avoid creating
3305 self-referential RTL when we will be substituting I1SRC for I1DEST
3306 later. Likewise if I0 feeds into I2, either directly or indirectly
3307 through I1, and I0DEST is in I0SRC. */
3314 /* Record whether I2's body now appears within I3's body. */
3316 }
3318 /* If we already got a failure, don't try to do more. Otherwise, try to
3319 substitute I1 if we have it. */
3322 {
3323 /* Check that an autoincrement side-effect on I1 has not been lost.
3324 This happens if I1DEST is mentioned in I2 and dies there, and
3325 has disappeared from the new pattern. */
3327 && i1_feeds_i2_n
3330 /* Before we can do this substitution, we must redo the test done
3331 above (see detailed comments there) that ensures I1DEST isn't
3332 mentioned in any SETs in NEWPAT that are field assignments. */
3335 {
3338 }
3343 /* If the following substitution will modify I1SRC, make a copy of it
3344 for the case where it is substituted for I1DEST in I2PAT later. */
3348 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3349 copy of I1SRC each time we substitute it, in order to avoid creating
3350 self-referential RTL when we will be substituting I0SRC for I0DEST
3351 later. */
3356 /* Record whether I1's body now appears within I3's body. */
3358 }
3360 /* Likewise for I0 if we have it. */
3363 {
3370 {
3373 }
3375 /* If the following substitution will modify I0SRC, make a copy of it
3376 for the case where it is substituted for I0DEST in I1PAT later. */
3379 /* And a copy for I0DEST in I2PAT substitution. */
3388 }
3390 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3391 to count all the ways that I2SRC and I1SRC can be used. */
3402 /* Fail if we tried to make a new register. */
3404 /* Fail if we couldn't do something and have a CLOBBER. */
3406 /* Fail if this new pattern is a MULT and we didn't have one before
3407 at the outer level. */
3410 {
3413 }
3415 /* If the actions of the earlier insns must be kept
3416 in addition to substituting them into the latest one,
3417 we must make a new PARALLEL for the latest insn
3418 to hold additional the SETs. */
3421 {
3423 combine_extras++;
3426 {
3432 }
3433 else
3434 {
3439 }
3445 {
3451 }
3453 {
3462 }
3463 }
3465 validate_replacement:
3467 /* Note which hard regs this insn has as inputs. */
3470 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3471 consider splitting this pattern, we might need these clobbers. */
3474 {
3480 }
3482 /* We have recognized nothing yet. */
3485 /* See if this is a PARALLEL of two SETs where one SET's destination is
3486 a register that is unused and this isn't marked as an instruction that
3487 might trap in an EH region. In that case, we just need the other SET.
3488 We prefer this over the PARALLEL.
3490 This can occur when simplifying a divmod insn. We *must* test for this
3491 case here because the code below that splits two independent SETs doesn't
3492 handle this case correctly when it updates the register status.
3494 It's pointless doing this if we originally had two sets, one from
3495 i3, and one from i2. Combining then splitting the parallel results
3496 in the original i2 again plus an invalid insn (which we delete).
3497 The net effect is only to move instructions around, which makes
3498 debug info less accurate.
3500 If the remaining SET came from I2 its destination should not be used
3501 between I2 and I3. See PR82024. */
3506 {
3517 {
3520 }
3529 {
3534 {
3540 }
3541 }
3545 }
3547 /* Is the result of combination a valid instruction? */
3551 /* If we were combining three insns and the result is a simple SET
3552 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3553 insns. There are two ways to do this. It can be split using a
3554 machine-specific method (like when you have an addition of a large
3555 constant) or by combine in the function find_split_point. */
3559 {
3563 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3564 use I2DEST as a scratch register will help. In the latter case,
3565 convert I2DEST to the mode of the source of NEWPAT if we can. */
3569 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3570 inputs of NEWPAT. */
3572 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3573 possible to try that as a scratch reg. This would require adding
3574 more code to make it work though. */
3577 {
3580 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3581 (temporarily, until we are committed to this instruction
3582 combination) does not work: for example, any call to nonzero_bits
3583 on the register (from a splitter in the MD file, for example)
3584 will get the old information, which is invalid.
3586 Since nowadays we can create registers during combine just fine,
3587 we should just create a new one here, not reuse i2dest. */
3589 /* First try to split using the original register as a
3590 scratch register. */
3594 i2dest)));
3597 /* If that didn't work, try changing the mode of I2DEST if
3598 we can. */
3603 {
3605 rtx ni2dest;
3609 else
3610 {
3613 }
3615 parallel = (gen_rtx_PARALLEL
3619 ni2dest))));
3624 {
3632 }
3633 }
3636 }
3638 /* If recog_for_combine has discarded clobbers, try to use them
3639 again for the split. */
3641 {
3644 }
3647 {
3652 }
3656 {
3666 /* If I2 or I3 has multiple SETs, we won't know how to track
3667 register status, so don't use these insns. If I2's destination
3668 is used between I2 and I3, we also can't use these insns. */
3678 /* It is possible that both insns now set the destination of I3.
3679 If so, we must show an extra use of it. */
3682 {
3701 }
3702 }
3704 /* If we can split it and use I2DEST, go ahead and see if that
3705 helps things be recognized. Verify that none of the registers
3706 are set between I2 and I3. */
3710 /* We need I2DEST in the proper mode. If it is a hard register
3711 or the only use of a pseudo, we can change its mode.
3712 Make sure we don't change a hard register to have a mode that
3713 isn't valid for it, or change the number of registers. */
3720 /* We can't overwrite I2DEST if its value is still used by
3721 NEWPAT. */
3723 {
3732 /* *SPLIT may be part of I2SRC, so make sure we have the
3733 original expression around for later debug processing.
3734 We should not need I2SRC any more in other cases. */
3737 else
3740 /* Get NEWDEST as a register in the proper mode. We have already
3741 validated that we can do this. */
3743 {
3746 else
3747 {
3750 }
3751 }
3753 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3754 an ASHIFT. This can occur if it was inside a PLUS and hence
3755 appeared to be a memory address. This is a kludge. */
3760 {
3763 /* Update split_code because we may not have a multiply
3764 anymore. */
3766 }
3768 /* Similarly for (plus (mult FOO (const_int pow2))). */
3774 {
3778 /* Update split_code because we may not have a multiply
3779 anymore. */
3781 }
3783 #ifdef INSN_SCHEDULING
3784 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3785 be written as a ZERO_EXTEND. */
3787 {
3788 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3789 what it really is. */
3794 else
3797 }
3798 #endif
3800 /* Attempt to split binary operators using arithmetic identities. */
3804 {
3811 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3813 {
3818 }
3819 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3826 {
3832 /* Split both "((X op Y) op X) op Y" and
3833 "((X op Y) op Y) op X" as "T op T" where T is
3834 "X op Y". */
3837 {
3842 }
3843 /* Split "((X op X) op Y) op Y)" as "T op T" where
3844 T is "X op Y". */
3846 {
3852 }
3853 }
3854 }
3857 {
3860 }
3864 /* recog_for_combine might have added CLOBBERs to newi2pat.
3865 Make sure NEWPAT does not depend on the clobbered regs. */
3869 {
3872 {
3875 }
3876 }
3878 /* If the split point was a MULT and we didn't have one before,
3879 don't use one now. */
3882 }
3883 }
3885 /* Check for a case where we loaded from memory in a narrow mode and
3886 then sign extended it, but we need both registers. In that case,
3887 we have a PARALLEL with both loads from the same memory location.
3888 We can split this into a load from memory followed by a register-register
3889 copy. This saves at least one insn, more if register allocation can
3890 eliminate the copy.
3892 We cannot do this if the destination of the first assignment is a
3893 condition code register or cc0. We eliminate this case by making sure
3894 the SET_DEST and SET_SRC have the same mode.
3896 We cannot do this if the destination of the second assignment is
3897 a register that we have already assumed is zero-extended. Similarly
3898 for a SUBREG of such a register. */
3933 {
3934 rtx ni2dest;
3948 }
3950 /* Similarly, check for a case where we have a PARALLEL of two independent
3951 SETs but we started with three insns. In this case, we can do the sets
3952 as two separate insns. This case occurs when some SET allows two
3953 other insns to combine, but the destination of that SET is still live.
3955 Also do this if we started with two insns and (at least) one of the
3956 resulting sets is a noop; this noop will be deleted later. */
3975 {
3979 /* Normally, it doesn't matter which of the two is done first,
3980 but the one that references cc0 can't be the second, and
3981 one which uses any regs/memory set in between i2 and i3 can't
3982 be first. The PARALLEL might also have been pre-existing in i3,
3983 so we need to make sure that we won't wrongly hoist a SET to i2
3984 that would conflict with a death note present in there. */
3992 /* If I3 is a jump, ensure that set0 is a jump so that
3993 we do not create invalid RTL. */
3995 )
3996 {
3999 }
4007 /* If I3 is a jump, ensure that set1 is a jump so that
4008 we do not create invalid RTL. */
4010 )
4011 {
4014 }
4015 else
4016 {
4019 }
4024 {
4025 /* recog_for_combine might have added CLOBBERs to newi2pat.
4026 Make sure NEWPAT does not depend on the clobbered regs. */
4028 {
4031 {
4034 {
4037 }
4038 }
4039 }
4042 }
4043 }
4045 /* If it still isn't recognized, fail and change things back the way they
4046 were. */
4048 /* Is the result a reasonable ASM_OPERANDS? */
4050 {
4053 }
4055 /* If we had to change another insn, make sure it is valid also. */
4057 {
4065 {
4068 }
4069 }
4071 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4072 they are adjacent to each other or not. */
4074 {
4078 {
4081 }
4082 }
4084 /* Only allow this combination if insn_rtx_costs reports that the
4085 replacement instructions are cheaper than the originals. */
4087 {
4090 }
4093 {
4098 {
4103 /* Temporarily revert mode back. */
4107 {
4108 /* If we used i2dest as a scratch register with a
4109 different mode, substitute it for the original
4110 i2src while its original mode is temporarily
4111 restored, and then clear i2scratch so that we don't
4112 do it again later. */
4114 this_basic_block);
4116 /* Put back the new mode. */
4118 }
4119 else
4120 {
4125 {
4128 }
4129 else
4130 {
4137 }
4139 /* We're dealing with a reg that changed mode but not
4140 meaning, so we want to turn it into a subreg for
4141 the new mode. However, because of REG sharing and
4142 because its mode had already changed, we have to do
4143 it in two steps. First, replace any debug uses of
4144 reg, with its original mode temporarily restored,
4145 with this copy we have created; then, replace the
4146 copy with the SUBREG of the original shared reg,
4147 once again changed to the new mode. */
4149 this_basic_block);
4153 this_basic_block);
4154 }
4155 }
4156 }
4158 /* If we will be able to accept this, we have made a
4159 change to the destination of I3. This requires us to
4160 do a few adjustments. */
4163 {
4166 }
4168 /* We now know that we can do this combination. Merge the insns and
4169 update the status of registers and LOG_LINKS. */
4172 {
4177 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4178 ensure that they are still valid. Then add any non-duplicate
4179 notes added by recog_for_combine. */
4181 {
4190 /* Simply drop equal note since it may be no longer valid
4191 for other_insn. It may be possible to record that CC
4192 register is changed and only discard those notes, but
4193 in practice it's unnecessary complication and doesn't
4194 give any meaningful improvement.
4196 See PR78559. */
4200 }
4204 NULL_RTX);
4205 }
4208 {
4211 rtx ni2dest;
4213 /* I3 now uses what used to be its destination and which is now
4214 I2's destination. This requires us to do a few adjustments. */
4218 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4219 so we still will.
4221 However, some later insn might be using I2's dest and have
4222 a LOG_LINK pointing at I3. We must remove this link.
4223 The simplest way to remove the link is to point it at I1,
4224 which we know will be a NOTE. */
4226 /* newi2pat is usually a SET here; however, recog_for_combine might
4227 have added some clobbers. */
4230 else
4237 {
4240 {
4246 }
4247 }
4248 }
4250 {
4255 /* Compute which registers we expect to eliminate. newi2pat may be setting
4256 either i3dest or i2dest, so we must check it. */
4259 || !i2dest_killed
4261 /* For i1, we need to compute both local elimination and global
4262 elimination information with respect to newi2pat because i1dest
4263 may be the same as i3dest, in which case newi2pat may be setting
4264 i1dest. Global information is used when distributing REG_DEAD
4265 note for i2 and i3, in which case it does matter if newi2pat sets
4266 i1dest or not.
4268 Local information is used when distributing REG_DEAD note for i1,
4269 in which case it doesn't matter if newi2pat sets i1dest or not.
4270 See PR62151, if we have four insns combination:
4271 i0: r0 <- i0src
4272 i1: r1 <- i1src (using r0)
4273 REG_DEAD (r0)
4274 i2: r0 <- i2src (using r1)
4275 i3: r3 <- i3src (using r0)
4276 ix: using r0
4277 From i1's point of view, r0 is eliminated, no matter if it is set
4278 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4279 should be discarded.
4281 Note local information only affects cases in forms like "I1->I2->I3",
4282 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4283 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4284 i0dest anyway. */
4286 || !i1dest_killed
4291 /* Same case as i1. */
4298 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4299 clear them. */
4307 /* Ensure that we do not have something that should not be shared but
4308 occurs multiple times in the new insns. Check this by first
4309 resetting all the `used' flags and then copying anything is shared. */
4333 {
4336 {
4338 {
4339 /* I2SRC must still be meaningful at this point. Some
4340 splitting operations can invalidate I2SRC, but those
4341 operations do not apply to calls. */
4345 }
4352 }
4353 }
4358 /* We had one special case above where I2 had more than one set and
4359 we replaced a destination of one of those sets with the destination
4360 of I3. In that case, we have to update LOG_LINKS of insns later
4361 in this basic block. Note that this (expensive) case is rare.
4363 Also, in this case, we must pretend that all REG_NOTEs for I2
4364 actually came from I3, so that REG_UNUSED notes from I2 will be
4365 properly handled. */
4368 {
4377 temp_insn
4387 {
4392 }
4393 else
4396 }
4404 {
4407 this_basic_block);
4410 }
4411 else
4412 {
4415 this_basic_block);
4417 }
4420 {
4425 this_basic_block);
4427 }
4430 {
4435 this_basic_block);
4437 }
4439 /* Get death notes for everything that is now used in either I3 or
4440 I2 and used to die in a previous insn. If we built two new
4441 patterns, move from I1 to I2 then I2 to I3 so that we get the
4442 proper movement on registers that I2 modifies. */
4448 else
4454 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4471 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4472 know these are REG_UNUSED and want them to go to the desired insn,
4473 so we always pass it as i3. */
4477 NULL_RTX);
4481 NULL_RTX);
4483 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4484 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4485 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4486 in that case, it might delete I2. Similarly for I2 and I1.
4487 Show an additional death due to the REG_DEAD note we make here. If
4488 we discard it in distribute_notes, we will decrement it again. */
4491 {
4496 else
4499 }
4502 {
4507 else
4510 }
4513 {
4518 else
4521 }
4524 {
4529 else
4532 }
4540 {
4545 /* The insn that used to set this register doesn't exist, and
4546 this life of the register may not exist either. See if one of
4547 I3's links points to an insn that sets I2DEST. If it does,
4548 that is now the last known value for I2DEST. If we don't update
4549 this and I2 set the register to a value that depended on its old
4550 contents, we will get confused. If this insn is used, thing
4551 will be set correctly in combine_instructions. */
4559 /* If the reg formerly set in I2 died only once and that was in I3,
4560 zero its use count so it won't make `reload' do any work. */
4563 && ! i2dest_in_i2src
4566 }
4569 {
4582 && ! i1dest_in_i1src
4585 }
4588 {
4601 && ! i0dest_in_i0src
4604 }
4606 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4607 been made to this insn. The order is important, because newi2pat
4608 can affect nonzero_bits of newpat. */
4612 }
4615 {
4617 {
4620 }
4622 }
4625 {
4627 {
4630 }
4632 }
4635 {
4637 {
4640 }
4642 }
4645 {
4647 {
4650 }
4652 }
4655 {
4657 {
4660 }
4662 }
4664 /* Set new_direct_jump_p if a new return or simple jump instruction
4665 has been created. Adjust the CFG accordingly. */
4667 {
4671 }
4676 {
4679 }
4683 {
4689 }
4694 {
4700 }
4702 /* A noop might also need cleaning up of CFG, if it comes from the
4703 simplification of a jump. */
4708 {
4711 }
4718 {
4721 }
4723 combine_successes++;
4730 else
4732 }
4733 \f
4734 /* Get a marker for undoing to the current state. */
4738 {
4740 }
4742 /* Undo the modifications up to the marker. */
4744 static void
4746 {
4750 {
4755 {
4770 }
4774 }
4777 }
4779 /* Undo all the modifications recorded in undobuf. */
4781 static void
4783 {
4785 }
4787 /* We've committed to accepting the changes we made. Move all
4788 of the undos to the free list. */
4790 static void
4792 {
4796 {
4800 }
4802 }
4803 \f
4804 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4805 where we have an arithmetic expression and return that point. LOC will
4806 be inside INSN.
4808 try_combine will call this function to see if an insn can be split into
4809 two insns. */
4813 {
4823 /* First special-case some codes. */
4825 {
4827 #ifdef INSN_SCHEDULING
4828 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4829 point. */
4832 #endif
4836 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4837 using LO_SUM and HIGH. */
4840 {
4848 }
4850 /* If we have a PLUS whose second operand is a constant and the
4851 address is not valid, perhaps will can split it up using
4852 the machine-specific way to split large constants. We use
4853 the first pseudo-reg (one of the virtual regs) as a placeholder;
4854 it will not remain in the result. */
4859 {
4862 subst_insn);
4864 /* This should have produced two insns, each of which sets our
4865 placeholder. If the source of the second is a valid address,
4866 we can make put both sources together and make a split point
4867 in the middle. */
4880 && memory_address_addr_space_p
4883 {
4887 /* Replace the placeholder in SRC2 with SRC1. If we can
4888 find where in SRC2 it was placed, that can become our
4889 split point and we can replace this address with SRC2.
4890 Just try two obvious places. */
4901 {
4904 }
4905 }
4907 /* If that didn't work, perhaps the first operand is complex and
4908 needs to be computed separately, so make a split point there.
4909 This will occur on machines that just support REG + CONST
4910 and have a constant moved through some previous computation. */
4916 }
4918 /* If we have a PLUS whose first operand is complex, try computing it
4919 separately by making a split there. */
4930 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4931 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4932 we need to put the operand into a register. So split at that
4933 point. */
4943 /* See if we can split SET_SRC as it stands. */
4948 /* See if we can split SET_DEST as it stands. */
4953 /* See if this is a bitfield assignment with everything constant. If
4954 so, this is an IOR of an AND, so split it into that. */
4966 {
4971 unsigned HOST_WIDE_INT mask
4973 rtx or_mask;
4982 else
4983 {
4989 or_mask));
4990 }
4997 }
4999 /* Otherwise, see if this is an operation that we can split into two.
5000 If so, try to split that. */
5004 {
5006 /* If we are AND'ing with a large constant that is only a single
5007 bit and the result is only being used in a context where we
5008 need to know if it is zero or nonzero, replace it with a bit
5009 extraction. This will avoid the large constant, which might
5010 have taken more than one insn to make. If the constant were
5011 not a valid argument to the AND but took only one insn to make,
5012 this is no worse, but if it took more than one insn, it will
5013 be better. */
5023 {
5028 {
5031 }
5032 }
5036 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5037 is known to be on, this can be converted into a NEG of a shift. */
5043 {
5055 }
5061 /* We can't optimize if either mode is a partial integer
5062 mode as we don't know how many bits are significant
5063 in those modes. */
5079 {
5087 }
5092 }
5097 {
5098 /* For unsigned, we have a choice of a shift followed by an
5099 AND or two shifts. Use two shifts for field sizes where the
5100 constant might be too large. We assume here that we can
5101 always at least get 8-bit constants in an AND insn, which is
5102 true for every current RISC. */
5105 {
5106 unsigned HOST_WIDE_INT mask
5110 gen_rtx_LSHIFTRT
5118 }
5119 else
5120 {
5122 gen_rtx_fmt_ee
5133 }
5134 }
5136 /* See if this is a simple operation with a constant as the second
5137 operand. It might be that this constant is out of range and hence
5138 could be used as a split point. */
5146 /* Finally, see if this is a simple operation with its first operand
5147 not in a register. The operation might require this operand in a
5148 register, so return it as a split point. We can always do this
5149 because if the first operand were another operation, we would have
5150 already found it as a split point. */
5159 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5160 it is better to write this as (not (ior A B)) so we can split it.
5161 Similarly for IOR. */
5163 {
5171 }
5173 /* Many RISC machines have a large set of logical insns. If the
5174 second operand is a NOT, put it first so we will try to split the
5175 other operand first. */
5177 {
5181 }
5186 /* Canonicalization can produce (minus A (mult B C)), where C is a
5187 constant. It may be better to try splitting (plus (mult B -C) A)
5188 instead if this isn't a multiply by a power of two. */
5192 {
5200 mode)),
5203 }
5205 /* Split at a multiply-accumulate instruction. However if this is
5206 the SET_SRC, we likely do not have such an instruction and it's
5207 worthless to try this split. */
5216 }
5218 /* Otherwise, select our actions depending on our rtx class. */
5220 {
5226 /* fall through */
5234 /* fall through */
5236 /* Some machines have (and (shift ...) ...) insns. If X is not
5237 an AND, but XEXP (X, 0) is, use it as our split point. */
5247 /* Otherwise, we don't have a split point. */
5249 }
5250 }
5251 \f
5252 /* Throughout X, replace FROM with TO, and return the result.
5253 The result is TO if X is FROM;
5254 otherwise the result is X, but its contents may have been modified.
5255 If they were modified, a record was made in undobuf so that
5256 undo_all will (among other things) return X to its original state.
5258 If the number of changes necessary is too much to record to undo,
5259 the excess changes are not made, so the result is invalid.
5260 The changes already made can still be undone.
5261 undobuf.num_undo is incremented for such changes, so by testing that
5262 the caller can tell whether the result is valid.
5264 `n_occurrences' is incremented each time FROM is replaced.
5266 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5268 IN_COND is nonzero if we are at the top level of a condition.
5270 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5271 by copying if `n_occurrences' is nonzero. */
5273 static rtx
5275 {
5280 rtx new_rtx;
5282 /* Two expressions are equal if they are identical copies of a shared
5283 RTX or if they are both registers with the same register number
5284 and mode. */
5286 #define COMBINE_RTX_EQUAL_P(X,Y) \
5287 ((X) == (Y) \
5288 || (REG_P (X) && REG_P (Y) \
5289 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5291 /* Do not substitute into clobbers of regs -- this will never result in
5292 valid RTL. */
5297 {
5298 n_occurrences++;
5300 }
5302 /* If X and FROM are the same register but different modes, they
5303 will not have been seen as equal above. However, the log links code
5304 will make a LOG_LINKS entry for that case. If we do nothing, we
5305 will try to rerecognize our original insn and, when it succeeds,
5306 we will delete the feeding insn, which is incorrect.
5308 So force this insn not to match in this (rare) case. */
5313 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5314 of which may contain things that can be combined. */
5318 /* It is possible to have a subexpression appear twice in the insn.
5319 Suppose that FROM is a register that appears within TO.
5320 Then, after that subexpression has been scanned once by `subst',
5321 the second time it is scanned, TO may be found. If we were
5322 to scan TO here, we would find FROM within it and create a
5323 self-referent rtl structure which is completely wrong. */
5327 /* Parallel asm_operands need special attention because all of the
5328 inputs are shared across the arms. Furthermore, unsharing the
5329 rtl results in recognition failures. Failure to handle this case
5330 specially can result in circular rtl.
5332 Solve this by doing a normal pass across the first entry of the
5333 parallel, and only processing the SET_DESTs of the subsequent
5334 entries. Ug. */
5339 {
5342 /* If this substitution failed, this whole thing fails. */
5350 {
5356 {
5359 /* If this substitution failed, this whole thing fails. */
5365 }
5366 }
5367 }
5368 else
5369 {
5373 /* We don't need to process a SET_DEST that is a register, CC0,
5374 or PC, so set up to skip this common case. All other cases
5375 where we want to suppress replacing something inside a
5376 SET_SRC are handled via the IN_DEST operand. */
5383 /* Trying to simplify the operands of a widening MULT is not likely
5384 to create RTL matching a machine insn. */
5396 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5397 constant. */
5402 {
5404 {
5407 {
5409 {
5412 n_occurrences++;
5413 }
5414 else
5415 {
5417 unique_copy);
5419 /* If this substitution failed, this whole thing
5420 fails. */
5424 }
5427 }
5428 }
5430 {
5431 /* If this is a register being set, ignore it. */
5438 ;
5441 {
5442 /* In general, don't install a subreg involving two
5443 modes not tieable. It can worsen register
5444 allocation, and can even make invalid reload
5445 insns, since the reg inside may need to be copied
5446 from in the outside mode, and that may be invalid
5447 if it is an fp reg copied in integer mode.
5449 We allow two exceptions to this: It is valid if
5450 it is inside another SUBREG and the mode of that
5451 SUBREG and the mode of the inside of TO is
5452 tieable and it is valid if X is a SET that copies
5453 FROM to CC0. */
5461 && (!HAVE_cc0
5476 n_occurrences++;
5477 }
5478 else
5479 /* If we are in a SET_DEST, suppress most cases unless we
5480 have gone inside a MEM, in which case we want to
5481 simplify the address. We assume here that things that
5482 are actually part of the destination have their inner
5483 parts in the first expression. This is true for SUBREG,
5484 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5485 things aside from REG and MEM that should appear in a
5486 SET_DEST. */
5488 (((in_dest
5494 unique_copy);
5496 /* If we found that we will have to reject this combination,
5497 indicate that by returning the CLOBBER ourselves, rather than
5498 an expression containing it. This will speed things up as
5499 well as prevent accidents where two CLOBBERs are considered
5500 to be equal, thus producing an incorrect simplification. */
5506 {
5514 }
5517 {
5521 }
5522 else
5524 }
5525 }
5526 }
5528 /* Check if we are loading something from the constant pool via float
5529 extension; in this case we would undo compress_float_constant
5530 optimization and degenerate constant load to an immediate value. */
5534 {
5538 }
5540 /* Try to simplify X. If the simplification changed the code, it is likely
5541 that further simplification will help, so loop, but limit the number
5542 of repetitions that will be performed. */
5545 {
5546 /* If X is sufficiently simple, don't bother trying to do anything
5547 with it. */
5556 /* We no longer know the original mode of operand 0 since we
5557 have changed the form of X) */
5559 }
5562 }
5563 \f
5564 /* If X is a commutative operation whose operands are not in the canonical
5565 order, use substitutions to swap them. */
5567 static void
5569 {
5572 {
5576 }
5577 }
5579 /* Simplify X, a piece of RTL. We just operate on the expression at the
5580 outer level; call `subst' to simplify recursively. Return the new
5581 expression.
5583 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5584 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5585 of a condition. */
5587 static rtx
5590 {
5593 scalar_int_mode int_mode;
5594 rtx temp;
5597 /* If this is a commutative operation, put a constant last and a complex
5598 expression first. We don't need to do this for comparisons here. */
5601 /* Try to fold this expression in case we have constants that weren't
5602 present before. */
5605 {
5613 {
5616 {
5620 }
5623 }
5636 }
5639 {
5644 }
5646 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5647 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5648 things. Check for cases where both arms are testing the same
5649 condition.
5651 Don't do anything if all operands are very simple. */
5664 {
5669 /* If everything is a comparison, what we have is highly unlikely
5670 to be simpler, so don't use it. */
5673 {
5680 /* Simplify the alternative arms; this may collapse the true and
5681 false arms to store-flag values. Be careful to use copy_rtx
5682 here since true_rtx or false_rtx might share RTL with x as a
5683 result of the if_then_else_cond call above. */
5687 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5688 is unlikely to be simpler. */
5691 {
5694 /* Restarting if we generate a store-flag expression will cause
5695 us to loop. Just drop through in this case. */
5697 /* If the result values are STORE_FLAG_VALUE and zero, we can
5698 just make the comparison operation. */
5709 /* Likewise, we can make the negate of a comparison operation
5710 if the result values are - STORE_FLAG_VALUE and zero. */
5718 mode);
5729 mode);
5730 else
5733 mode,
5734 VOIDmode,
5735 cond,
5736 cop1),
5741 }
5742 }
5743 }
5745 /* First see if we can apply the inverse distributive law. */
5748 {
5752 }
5754 /* If CODE is an associative operation not otherwise handled, see if we
5755 can associate some operands. This can win if they are constants or
5756 if they are logically related (i.e. (a & b) & a). */
5762 {
5764 {
5768 rtx inner;
5770 /* Make sure we pass the constant operand if any as the second
5771 one if this is a commutative operation. */
5779 /* For commutative operations, try the other pair if that one
5780 didn't simplify. */
5782 {
5787 }
5791 }
5792 }
5794 /* A little bit of algebraic simplification here. */
5796 {
5798 /* Ensure that our address has any ASHIFTs converted to MULT in case
5799 address-recognizing predicates are called later. */
5808 /* See if this can be moved to simplify_subreg. */
5811 /* Don't call gen_lowpart if the inner mode
5812 is VOIDmode and we cannot simplify it, as SUBREG without
5813 inner mode is invalid. */
5820 {
5821 rtx temp;
5827 /* If op is known to have all lower bits zero, the result is zero. */
5840 }
5842 /* Don't change the mode of the MEM if that would change the meaning
5843 of the address. */
5850 /* Note that we cannot do any narrowing for non-constants since
5851 we might have been counting on using the fact that some bits were
5852 zero. We now do this in the SET. */
5859 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5860 replaced by (lshiftrt X C). This will convert
5861 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5869 /* If X has only a single bit that might be nonzero, say, bit I, convert
5870 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5871 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5872 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5873 or a SUBREG of one since we'd be making the expression more
5874 complex if it was just a register. */
5881 {
5882 rtx temp1 = simplify_shift_const
5888 /* If all we did was surround TEMP with the two shifts, we
5889 haven't improved anything, so don't use it. Otherwise,
5890 we are better off with TEMP1. */
5895 }
5899 /* We can't handle truncation to a partial integer mode here
5900 because we don't know the real bitsize of the partial
5901 integer mode. */
5910 /* We can truncate a constant value and return it. */
5914 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5915 whose value is a comparison can be replaced with a subreg if
5916 STORE_FLAG_VALUE permits. */
5925 /* (const (const X)) can become (const X). Do it this way rather than
5926 returning the inner CONST since CONST can be shared with a
5927 REG_EQUAL note. */
5933 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5934 can add in an offset. find_split_point will split this address up
5935 again if it doesn't match. */
5942 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5943 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5944 bit-field and can be replaced by either a sign_extend or a
5945 sign_extract. The `and' may be a zero_extend and the two
5946 <c>, -<c> constants may be reversed. */
5962 return simplify_shift_const
5969 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5970 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5971 the bitsize of the mode - 1. This allows simplification of
5972 "a = (b & 8) == 0;" */
5979 return simplify_shift_const
5983 const1_rtx),
5987 /* If we are adding two things that have no bits in common, convert
5988 the addition into an IOR. This will often be further simplified,
5989 for example in cases like ((a & 1) + (a & 2)), which can
5990 become a & 3. */
5995 {
5996 /* Try to simplify the expression further. */
6000 /* If we could, great. If not, do not go ahead with the IOR
6001 replacement, since PLUS appears in many special purpose
6002 address arithmetic instructions. */
6010 }
6012 /* Canonicalize x + x into x << 1. */
6021 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6022 (and <foo> (const_int pow2-1)) */
6033 /* If we have (mult (plus A B) C), apply the distributive law and then
6034 the inverse distributive law to see if things simplify. This
6035 occurs mostly in addresses, often when unrolling loops. */
6038 {
6042 }
6044 /* Try simplify a*(b/c) as (a*b)/c. */
6047 {
6053 }
6057 /* If this is a divide by a power of two, treat it as a shift if
6058 its first operand is a shift. */
6078 /* If the first operand is a condition code, we can't do anything
6079 with it. */
6083 {
6091 /* Simplify our comparison, if possible. */
6094 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6095 if only the low-order bit is possibly nonzero in X (such as when
6096 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6097 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6098 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6099 (plus X 1).
6101 Remove any ZERO_EXTRACT we made when thinking this was a
6102 comparison. It may now be simpler to use, e.g., an AND. If a
6103 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6104 the call to make_compound_operation in the SET case.
6106 Don't apply these optimizations if the caller would
6107 prefer a comparison rather than a value.
6108 E.g., for the condition in an IF_THEN_ELSE most targets need
6109 an explicit comparison. */
6112 ;
6130 {
6134 int_mode);
6135 }
6143 {
6147 const1_rtx);
6148 }
6157 {
6160 }
6162 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6163 those above. */
6165 ;
6182 {
6186 int_mode);
6187 }
6196 {
6200 int_mode);
6201 }
6203 /* If X is 0/1, (eq X 0) is X-1. */
6210 {
6213 }
6215 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6216 one bit that might be nonzero, we can convert (ne x 0) to
6217 (ashift x c) where C puts the bit in the sign bit. Remove any
6218 AND with STORE_FLAG_VALUE when we are done, since we are only
6219 going to test the sign bit. */
6227 {
6233 else
6235 }
6237 /* If the code changed, return a whole new comparison.
6238 We also need to avoid using SUBST in cases where
6239 simplify_comparison has widened a comparison with a CONST_INT,
6240 since in that case the wider CONST_INT may fail the sanity
6241 checks in do_SUBST. */
6248 /* Otherwise, keep this operation, but maybe change its operands.
6249 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6252 }
6262 /* If we are processing SET_DEST, we are done. */
6280 /* If this is a shift by a constant amount, simplify it. */
6288 (HOST_WIDE_INT_1U
6296 }
6299 }
6300 \f
6301 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6303 static rtx
6305 {
6312 rtx temp;
6315 rtx reversed;
6318 /* Simplify storing of the truth value. */
6323 /* Also when the truth value has to be reversed. */
6329 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6330 in it is being compared against certain values. Get the true and false
6331 comparisons and see if that says anything about the value of each arm. */
6337 {
6338 HOST_WIDE_INT nzb;
6344 /* If FALSE_CODE is EQ, swap the codes and arms. */
6347 {
6350 }
6352 scalar_int_mode from_mode;
6354 {
6355 /* If we are comparing against zero and the expression being
6356 tested has only a single bit that might be nonzero, that is
6357 its value when it is not equal to zero. Similarly if it is
6358 known to be -1 or 0. */
6362 {
6365 }
6370 {
6373 }
6374 }
6376 /* Now simplify an arm if we know the value of the register in the
6377 branch and it is used in the arm. Be careful due to the potential
6378 of locally-shared RTL. */
6395 }
6397 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6398 reversed, do so to avoid needing two sets of patterns for
6399 subtract-and-branch insns. Similarly if we have a constant in the true
6400 arm, the false arm is the same as the first operand of the comparison, or
6401 the false arm is more complicated than the true arm. */
6414 {
6423 /* It is possible that the conditional has been simplified out. */
6426 }
6428 /* If the two arms are identical, we don't need the comparison. */
6433 /* Convert a == b ? b : a to "a". */
6445 /* Look for cases where we have (abs x) or (neg (abs X)). */
6448 && comparison_p
6455 {
6461 return
6464 mode);
6467 }
6469 /* Look for MIN or MAX. */
6472 && comparison_p
6477 {
6492 }
6494 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6495 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6496 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6497 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6498 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6499 neither 1 or -1, but it isn't worth checking for. */
6502 && comparison_p
6505 {
6521 /* If an identity-zero op is commutative, check whether there
6522 would be a match if we swapped the operands. */
6543 {
6547 }
6560 {
6564 }
6581 {
6585 }
6598 {
6602 }
6605 {
6611 const_true_rtx));
6619 }
6620 }
6622 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6623 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6624 negation of a single bit, we can convert this operation to a shift. We
6625 can actually do this more generally, but it doesn't seem worth it. */
6637 return
6641 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6642 non-zero bit in A is C1. */
6650 {
6656 }
6659 }
6660 \f
6661 /* Simplify X, a SET expression. Return the new expression. */
6663 static rtx
6665 {
6668 machine_mode mode
6672 scalar_int_mode int_mode;
6674 /* (set (pc) (return)) gets written as (return). */
6678 /* Now that we know for sure which bits of SRC we are using, see if we can
6679 simplify the expression for the object knowing that we only need the
6680 low-order bits. */
6683 {
6686 }
6688 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6689 the comparison result and try to simplify it unless we already have used
6690 undobuf.other_insn. */
6698 {
6707 {
6710 {
6713 }
6714 }
6715 else
6723 {
6727 }
6728 else
6729 {
6734 /* Attempt to simplify CC user. */
6736 {
6740 }
6742 /* Convert X into a no-op move. */
6746 }
6748 /* Simplify our comparison, if possible. */
6751 #ifdef SELECT_CC_MODE
6752 /* If this machine has CC modes other than CCmode, check to see if we
6753 need to use a different CC mode here. */
6762 else
6765 /* If the mode changed, we have to change SET_DEST, the mode in the
6766 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6767 a hard register, just build new versions with the proper mode. If it
6768 is a pseudo, we lose unless it is only time we set the pseudo, in
6769 which case we can safely change its mode. */
6771 {
6773 {
6775 rtx new_dest;
6779 else
6780 {
6783 }
6790 }
6791 }
6794 /* If the code changed, we have to build a new comparison in
6795 undobuf.other_insn. */
6797 {
6806 /* If the only change we made was to change an EQ into an NE or
6807 vice versa, OP0 has only one bit that might be nonzero, and OP1
6808 is zero, check if changing the user of the condition code will
6809 produce a valid insn. If it won't, we can keep the original code
6810 in that insn by surrounding our operation with an XOR. */
6817 {
6822 {
6829 }
6830 }
6831 }
6836 /* Don't generate a compare of a CC with 0, just use that CC. */
6838 {
6841 }
6842 /* Otherwise, if we didn't previously have the same COMPARE we
6843 want, create it from scratch. */
6846 {
6849 }
6850 }
6851 else
6852 {
6853 /* Get SET_SRC in a form where we have placed back any
6854 compound expressions. Then do the checks below. */
6857 }
6859 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6860 and X being a REG or (subreg (reg)), we may be able to convert this to
6861 (set (subreg:m2 x) (op)).
6863 We can always do this if M1 is narrower than M2 because that means that
6864 we only care about the low bits of the result.
6866 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6867 perform a narrower operation than requested since the high-order bits will
6868 be undefined. On machine where it is defined, this transformation is safe
6869 as long as M1 and M2 have the same number of words. */
6885 {
6888 dest));
6892 }
6894 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6895 in SRC. */
6899 {
6903 /* Here we make sure that we don't have a sign bit on. */
6906 {
6909 }
6910 }
6912 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6913 would require a paradoxical subreg. Replace the subreg with a
6914 zero_extend to avoid the reload that would otherwise be required. */
6920 {
6925 }
6927 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6928 are comparing an item known to be 0 or -1 against 0, use a logical
6929 operation instead. Check for one of the arms being an IOR of the other
6930 arm with some value. We compute three terms to be IOR'ed together. In
6931 practice, at most two will be nonzero. Then we do the IOR's. */
6939 && (!HAVE_conditional_move
6944 {
6969 int_mode),
6970 false_rtx);
6976 term3));
6979 }
6981 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6982 whole thing fail. */
6987 else
6988 /* Convert this into a field assignment operation, if possible. */
6990 }
6991 \f
6992 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6993 result. */
6995 static rtx
6997 {
7000 scalar_int_mode mode;
7003 {
7005 /* We can call simplify_and_const_int only if we don't lose
7006 any (sign) bits when converting INTVAL (op1) to
7007 "unsigned HOST_WIDE_INT". */
7012 {
7019 }
7021 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7022 apply the distributive law and then the inverse distributive
7023 law to see if things simplify. */
7025 {
7029 }
7031 {
7035 }
7039 /* If we have (ior (and A B) C), apply the distributive law and then
7040 the inverse distributive law to see if things simplify. */
7043 {
7047 }
7050 {
7054 }
7059 }
7062 }
7063 \f
7064 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7065 operations" because they can be replaced with two more basic operations.
7066 ZERO_EXTEND is also considered "compound" because it can be replaced with
7067 an AND operation, which is simpler, though only one operation.
7069 The function expand_compound_operation is called with an rtx expression
7070 and will convert it to the appropriate shifts and AND operations,
7071 simplifying at each stage.
7073 The function make_compound_operation is called to convert an expression
7074 consisting of shifts and ANDs into the equivalent compound expression.
7075 It is the inverse of this function, loosely speaking. */
7077 static rtx
7079 {
7083 rtx tem;
7084 scalar_int_mode inner_mode;
7087 {
7090 /* FALLTHRU */
7092 /* We can't necessarily use a const_int for a multiword mode;
7093 it depends on implicitly extending the value.
7094 Since we don't know the right way to extend it,
7095 we can't tell whether the implicit way is right.
7097 Even for a mode that is no wider than a const_int,
7098 we can't win, because we need to sign extend one of its bits through
7099 the rest of it, and we don't know which bit. */
7103 /* Reject modes that aren't scalar integers because turning vector
7104 or complex modes into shifts causes problems. */
7108 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7109 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7110 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7111 reloaded. If not for that, MEM's would very rarely be safe.
7113 Reject modes bigger than a word, because we might not be able
7114 to reference a two-register group starting with an arbitrary register
7115 (and currently gen_lowpart might crash for a SUBREG). */
7121 /* If the inner object has VOIDmode (the only way this can happen
7122 is if it is an ASM_OPERANDS), we can't do anything since we don't
7123 know how much masking to do. */
7132 /* fall through */
7135 /* If the operand is a CLOBBER, just return it. */
7143 /* Reject modes that aren't scalar integers because turning vector
7144 or complex modes into shifts causes problems. */
7151 /* This should stay within the object being extracted, fail otherwise. */
7162 }
7164 /* We've rejected non-scalar operations by now. */
7167 /* Convert sign extension to zero extension, if we know that the high
7168 bit is not set, as this is easier to optimize. It will be converted
7169 back to cheaper alternative in make_extraction. */
7175 {
7179 /* Make sure this is a profitable operation. */
7186 else
7188 }
7190 /* We can optimize some special cases of ZERO_EXTEND. */
7192 {
7193 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7194 know that the last value didn't have any inappropriate bits
7195 set. */
7203 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7212 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7213 is a comparison and STORE_FLAG_VALUE permits. This is like
7214 the first case, but it works even when MODE is larger
7215 than HOST_WIDE_INT. */
7223 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7232 }
7234 /* If we reach here, we want to return a pair of shifts. The inner
7235 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7236 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7237 logical depending on the value of UNSIGNEDP.
7239 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7240 converted into an AND of a shift.
7242 We must check for the case where the left shift would have a negative
7243 count. This can happen in a case like (x >> 31) & 255 on machines
7244 that can't shift by a constant. On those machines, we would first
7245 combine the shift with the AND to produce a variable-position
7246 extraction. Then the constant of 31 would be substituted in
7247 to produce such a position. */
7251 {
7259 }
7264 pos),
7266 else
7267 /* Any other cases we can't handle. */
7270 /* If we couldn't do this for some reason, return the original
7271 expression. */
7276 }
7277 \f
7278 /* X is a SET which contains an assignment of one object into
7279 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7280 or certain SUBREGS). If possible, convert it into a series of
7281 logical operations.
7283 We half-heartedly support variable positions, but do not at all
7284 support variable lengths. */
7286 static const_rtx
7288 {
7289 rtx inner;
7293 scalar_int_mode compute_mode;
7295 /* Loop until we find something we can't simplify. */
7297 {
7300 {
7304 }
7307 {
7312 /* A constant position should stay within the width of INNER. */
7318 {
7326 /* If position is ADJUST - X, new position is X. */
7328 else
7329 {
7334 pos);
7335 }
7336 }
7337 }
7339 /* A SUBREG between two modes that occupy the same numbers of words
7340 can be done by moving the SUBREG to the source. */
7342 /* We need SUBREGs to compute nonzero_bits properly. */
7343 && nonzero_sign_valid
7348 {
7350 gen_lowpart
7354 }
7355 else
7361 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7363 {
7364 /* Don't do anything for vector or complex integral types. */
7368 /* Try to find an integral mode to pun with. */
7374 }
7376 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7380 /* Don't try to compute in too wide unsupported modes. */
7384 /* Now compute the equivalent expression. Make a copy of INNER
7385 for the SET_DEST in case it is a MEM into which we will substitute;
7386 we don't want shared RTL in that case. */
7388 compute_mode);
7392 compute_mode,
7394 compute_mode),
7395 inner);
7400 mask),
7401 pos);
7406 }
7409 }
7410 \f
7411 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7412 it is an RTX that represents the (variable) starting position; otherwise,
7413 POS is the (constant) starting bit position. Both are counted from the LSB.
7415 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7417 IN_DEST is nonzero if this is a reference in the destination of a SET.
7418 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7419 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7420 be used.
7422 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7423 ZERO_EXTRACT should be built even for bits starting at bit 0.
7425 MODE is the desired mode of the result (if IN_DEST == 0).
7427 The result is an RTX for the extraction or NULL_RTX if the target
7428 can't handle it. */
7430 static rtx
7434 {
7435 /* This mode describes the size of the storage area
7436 to fetch the overall value from. Within that, we
7437 ignore the POS lowest bits, etc. */
7439 machine_mode inner_mode;
7440 scalar_int_mode wanted_inner_mode;
7446 HOST_WIDE_INT orig_pos;
7454 /* If trying or potentionally trying to extract
7455 bits outside of is_mode, don't look through
7456 non-paradoxical SUBREGs. See PR82192. */
7459 {
7460 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7461 consider just the QI as the memory to extract from.
7462 The subreg adds or removes high bits; its mode is
7463 irrelevant to the meaning of this extraction,
7464 since POS and LEN count from the lsb. */
7468 }
7473 {
7474 /* We're extracting the least significant bits of an rtx
7475 (ashift X (const_int C)), where LEN > C. Extract the
7476 least significant (LEN - C) bits of X, giving an rtx
7477 whose mode is MODE, then shift it left C times. */
7483 }
7485 /* If trying or potentionally trying to extract
7486 bits outside of is_mode, don't look through
7487 TRUNCATE. See PR82192. */
7494 /* See if this can be done without an extraction. We never can if the
7495 width of the field is not the same as that of some integer mode. For
7496 registers, we can only avoid the extraction if the position is at the
7497 low-order bit and this is either not in the destination or we have the
7498 appropriate STRICT_LOW_PART operation available.
7500 For MEM, we can avoid an extract if the field starts on an appropriate
7501 boundary and we can change the mode of the memory reference. */
7503 scalar_int_mode tmode;
7512 && (! in_dest
7516 && (pos
7519 /* We can't do this if we are widening INNER_MODE (it
7520 may not be aligned, for one thing). */
7526 {
7527 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7528 field. If the original and current mode are the same, we need not
7529 adjust the offset. Otherwise, we do if bytes big endian.
7531 If INNER is not a MEM, get a piece consisting of just the field
7532 of interest (in this case POS % BITS_PER_WORD must be 0). */
7535 {
7536 HOST_WIDE_INT offset;
7538 /* POS counts from lsb, but make OFFSET count in memory order. */
7541 else
7545 }
7547 {
7549 {
7550 /* We can't call gen_lowpart in a DEST since we
7551 always want a SUBREG (see below) and it would sometimes
7552 return a new hard register. */
7554 {
7555 unsigned int offset
7558 /* Avoid creating invalid subregs, for example when
7559 simplifying (x>>32)&255. */
7564 }
7565 else
7567 }
7568 else
7570 }
7571 else
7573 len >= HOST_BITS_PER_WIDE_INT
7574 ? HOST_WIDE_INT_M1U
7577 /* If this extraction is going into the destination of a SET,
7578 make a STRICT_LOW_PART unless we made a MEM. */
7593 /* If we know that no extraneous bits are set, and that the high
7594 bit is not set, convert the extraction to the cheaper of
7595 sign and zero extension, that are equivalent in these cases. */
7601 {
7605 /* Prefer ZERO_EXTENSION, since it gives more information to
7606 backends. */
7611 }
7613 /* Otherwise, sign- or zero-extend unless we already are in the
7614 proper mode. */
7618 }
7620 /* Unless this is a COMPARE or we have a funny memory reference,
7621 don't do anything with zero-extending field extracts starting at
7622 the low-order bit since they are simple AND operations. */
7627 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7628 if the position is not a constant and the length is not 1. In all
7629 other cases, we would only be going outside our object in cases when
7630 an original shift would have been undefined. */
7639 /* If INNER is not from memory, we want it to have the mode of a register
7640 extraction pattern's structure operand, or word_mode if there is no
7641 such pattern. The same applies to extraction_mode and pos_mode
7642 and their respective operands.
7644 For memory, assume that the desired extraction_mode and pos_mode
7645 are the same as for a register operation, since at present we don't
7646 have named patterns for aligned memory structures. */
7650 {
7654 }
7656 /* Never narrow an object, since that might not be safe. */
7664 else
7665 {
7666 /* Be careful not to go beyond the extracted object and maintain the
7667 natural alignment of the memory. */
7672 }
7677 {
7678 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7679 BITS_BIG_ENDIAN style. If position is constant, compute new
7680 position. Otherwise, build subtraction.
7681 Note that POS is relative to the mode of the original argument.
7682 If it's a MEM we need to recompute POS relative to that.
7683 However, if we're extracting from (or inserting into) a register,
7684 we want to recompute POS relative to wanted_inner_mode. */
7691 else
7692 pos_rtx
7695 pos_rtx);
7696 /* POS may be less than 0 now, but we check for that below.
7697 Note that it can only be less than 0 if !MEM_P (inner). */
7698 }
7700 /* If INNER has a wider mode, and this is a constant extraction, try to
7701 make it smaller and adjust the byte to point to the byte containing
7702 the value. */
7705 && ! pos_rtx
7710 {
7713 /* The computations below will be correct if the machine is big
7714 endian in both bits and bytes or little endian in bits and bytes.
7715 If it is mixed, we must adjust. */
7717 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7718 adjust OFFSET to compensate. */
7723 /* We can now move to the desired byte. */
7734 }
7736 /* If INNER is not memory, get it into the proper mode. If we are changing
7737 its mode, POS must be a constant and smaller than the size of the new
7738 mode. */
7740 {
7741 /* On the LHS, don't create paradoxical subregs implicitely truncating
7742 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7745 wanted_inner_mode))
7757 pos_rtx
7759 ? HOST_WIDE_INT_M1U
7763 }
7765 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7766 have to zero extend. Otherwise, we can just use a SUBREG.
7768 We dealt with constant rtxes earlier, so pos_rtx cannot
7769 have VOIDmode at this point. */
7773 {
7777 /* If we know that no extraneous bits are set, and that the high
7778 bit is not set, convert extraction to cheaper one - either
7779 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7780 cases. */
7788 {
7792 /* Prefer ZERO_EXTENSION, since it gives more information to
7793 backends. */
7797 }
7799 }
7801 /* Make POS_RTX unless we already have it and it is correct. If we don't
7802 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7803 be a CONST_INT. */
7810 /* Make the required operation. See if we can use existing rtx. */
7817 }
7818 \f
7819 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7820 can be commuted with any other operations in X. Return X without
7821 that shift if so. */
7823 static rtx
7825 {
7827 rtx tem;
7830 {
7832 /* This is the shift itself. If it is wide enough, we will return
7833 either the value being shifted if the shift count is equal to
7834 COUNT or a shift for the difference. */
7848 /* If we can safely shift this constant and we find the inner shift,
7849 make a new operation. */
7854 {
7858 }
7863 }
7866 }
7867 \f
7868 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7869 level of the expression and MODE is its mode. IN_CODE is as for
7870 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7871 that should be used when recursing on operands of *X_PTR.
7873 There are two possible actions:
7875 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7876 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7878 - Return a new rtx, which the caller returns directly. */
7880 static rtx
7884 {
7892 rtx tem;
7893 scalar_int_mode inner_mode;
7897 {
7900 }
7902 /* Process depending on the code of this operation. If NEW is set
7903 nonzero, it will be returned. */
7906 {
7908 /* Convert shifts by constants into multiplications if inside
7909 an address. */
7913 {
7919 {
7922 }
7925 }
7934 {
7938 }
7941 {
7945 mode));
7947 }
7948 else
7949 {
7952 }
7962 {
7966 }
7969 {
7973 mode));
7975 }
7976 else
7977 {
7981 }
7984 /* If the second operand is not a constant, we can't do anything
7985 with it. */
7989 /* If the constant is a power of two minus one and the first operand
7990 is a logical right shift, make an extraction. */
7993 {
7997 }
7999 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8006 {
8013 /* If we narrowed the mode when dropping the subreg, then we lose. */
8017 /* If that didn't give anything, see if the AND simplifies on
8018 its own. */
8020 {
8024 }
8025 }
8026 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8032 {
8033 /* Apply the distributive law, and then try to make extractions. */
8040 }
8042 /* If we are have (and (rotate X C) M) and C is larger than the number
8043 of bits in M, this is an extraction. */
8049 {
8055 }
8057 /* On machines without logical shifts, if the operand of the AND is
8058 a logical shift and our mask turns off all the propagated sign
8059 bits, we can replace the logical shift with an arithmetic shift. */
8067 {
8077 next_code),
8079 }
8081 /* If the constant is one less than a power of two, this might be
8082 representable by an extraction even if no shift is present.
8083 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8084 we are in a COMPARE. */
8088 next_code),
8091 /* If we are in a comparison and this is an AND with a power of two,
8092 convert this into the appropriate bit extract. */
8098 next_code),
8101 /* If the one operand is a paradoxical subreg of a register or memory and
8102 the constant (limited to the smaller mode) has only zero bits where
8103 the sub expression has known zero bits, this can be expressed as
8104 a zero_extend. */
8106 {
8107 rtx sub;
8113 {
8117 /* original AND constant with all the known zero bits set */
8120 {
8125 }
8126 }
8127 }
8132 /* If the sign bit is known to be zero, replace this with an
8133 arithmetic shift. */
8138 {
8141 next_code),
8144 }
8146 /* fall through */
8152 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8153 this is a SIGN_EXTRACT. */
8160 {
8167 }
8169 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8170 If so, try to merge the shifts into a SIGN_EXTEND. We could
8171 also do this for some cases of SIGN_EXTRACT, but it doesn't
8172 seem worth the effort; the case checked for occurs on Alpha. */
8183 next_code),
8190 /* Call ourselves recursively on the inner expression. If we are
8191 narrowing the object and it has a different RTL code from
8192 what it originally did, do this SUBREG as a force_to_mode. */
8193 {
8197 /* If the SUBREG is masking of a logical right shift,
8198 make an extraction. */
8205 {
8214 }
8216 /* If in_code is COMPARE, it isn't always safe to pass it through
8217 to the recursive make_compound_operation call. */
8221 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8222 is (const_int 0), rather than
8223 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8224 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8225 for non-equality comparisons against 0 is not equivalent
8226 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8236 simplified
8244 {
8245 rtx newer
8248 /* If we have something other than a SUBREG, we might have
8249 done an expansion, so rerun ourselves. */
8253 /* force_to_mode can expand compounds. If it just re-expanded
8254 the compound, use gen_lowpart to convert to the desired
8255 mode. */
8257 /* Likewise if it re-expanded the compound only partially.
8258 This happens for SUBREG of ZERO_EXTRACT if they extract
8259 the same number of bits. */
8268 }
8272 }
8277 }
8283 }
8285 /* Look at the expression rooted at X. Look for expressions
8286 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8287 Form these expressions.
8289 Return the new rtx, usually just X.
8291 Also, for machines like the VAX that don't have logical shift insns,
8292 try to convert logical to arithmetic shift operations in cases where
8293 they are equivalent. This undoes the canonicalizations to logical
8294 shifts done elsewhere.
8296 We try, as much as possible, to re-use rtl expressions to save memory.
8298 IN_CODE says what kind of expression we are processing. Normally, it is
8299 SET. In a memory address it is MEM. When processing the arguments of
8300 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8301 precisely it is an equality comparison against zero. */
8303 rtx
8305 {
8312 /* Select the code to be used in recursive calls. Once we are inside an
8313 address, we stay there. If we have a comparison, set to COMPARE,
8314 but once inside, go back to our default of SET. */
8321 scalar_int_mode mode;
8323 {
8329 }
8331 /* Now recursively process each operand of this operation. We need to
8332 handle ZERO_EXTEND specially so that we don't lose track of the
8333 inner mode. */
8335 {
8343 }
8348 {
8351 }
8354 {
8357 }
8361 }
8362 \f
8363 /* Given M see if it is a value that would select a field of bits
8364 within an item, but not the entire word. Return -1 if not.
8365 Otherwise, return the starting position of the field, where 0 is the
8366 low-order bit.
8368 *PLEN is set to the length of the field. */
8370 static int
8372 {
8373 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8378 /* Now shift off the low-order zero bits and see if we have a
8379 power of two minus 1. */
8387 }
8388 \f
8389 /* If X refers to a register that equals REG in value, replace these
8390 references with REG. */
8391 static rtx
8393 {
8401 {
8434 /* FALLTHRU */
8438 {
8442 else
8444 }
8446 /* fall through */
8453 {
8456 {
8458 {
8461 }
8463 }
8464 }
8466 {
8469 {
8472 {
8474 {
8477 }
8479 }
8480 }
8481 }
8484 }
8487 }
8489 /* Return X converted to MODE. If the value is already truncated to
8490 MODE we can just return a subreg even though in the general case we
8491 would need an explicit truncation. */
8493 static rtx
8495 {
8500 {
8501 /* Bit-cast X into an integer mode. */
8506 }
8509 }
8511 /* See if X can be simplified knowing that we will only refer to it in
8512 MODE and will only refer to those bits that are nonzero in MASK.
8513 If other bits are being computed or if masking operations are done
8514 that select a superset of the bits in MASK, they can sometimes be
8515 ignored.
8517 Return a possibly simplified expression, but always convert X to
8518 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8520 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8521 are all off in X. This is used when X will be complemented, by either
8522 NOT, NEG, or XOR. */
8524 static rtx
8527 {
8530 machine_mode op_mode;
8533 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8534 code below will do the wrong thing since the mode of such an
8535 expression is VOIDmode.
8537 Also do nothing if X is a CLOBBER; this can happen if X was
8538 the return value from a call to gen_lowpart. */
8542 /* We want to perform the operation in its present mode unless we know
8543 that the operation is valid in MODE, in which case we do the operation
8544 in MODE. */
8549 /* It is not valid to do a right-shift in a narrower mode
8550 than the one it came in with. */
8555 /* Truncate MASK to fit OP_MODE. */
8559 /* Determine what bits of X are guaranteed to be (non)zero. */
8562 /* If none of the bits in X are needed, return a zero. */
8566 /* If X is a CONST_INT, return a new one. Do this here since the
8567 test below will fail. */
8569 {
8572 else
8573 {
8576 }
8577 }
8579 /* If X is narrower than MODE and we want all the bits in X's mode, just
8580 get X in the proper mode. */
8585 /* We can ignore the effect of a SUBREG if it narrows the mode or
8586 if the constant masks to zero all the bits the mode doesn't have. */
8598 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8599 integer too. */
8605 }
8607 /* Subroutine of force_to_mode that handles cases in which both X and
8608 the result are scalar integers. MODE is the mode of the result,
8609 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8610 is preferred for simplified versions of X. The other arguments
8611 are as for force_to_mode. */
8613 static rtx
8617 {
8623 /* When we have an arithmetic operation, or a shift whose count we
8624 do not know, we need to assume that all bits up to the highest-order
8625 bit in MASK will be needed. This is how we form such a mask. */
8628 else
8633 {
8635 /* If X is a (clobber (const_int)), return it since we know we are
8636 generating something that won't match. */
8649 /* Similarly for a truncate. */
8653 /* If this is an AND with a constant, convert it into an AND
8654 whose constant is the AND of that constant with MASK. If it
8655 remains an AND of MASK, delete it since it is redundant. */
8658 {
8663 /* If X is still an AND, see if it is an AND with a mask that
8664 is just some low-order bits. If so, and it is MASK, we don't
8665 need it. */
8671 /* If it remains an AND, try making another AND with the bits
8672 in the mode mask that aren't in MASK turned on. If the
8673 constant in the AND is wide enough, this might make a
8674 cheaper constant. */
8679 {
8680 unsigned HOST_WIDE_INT cval
8682 rtx y;
8689 }
8692 }
8697 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8698 low-order bits (as in an alignment operation) and FOO is already
8699 aligned to that boundary, mask C1 to that boundary as well.
8700 This may eliminate that PLUS and, later, the AND. */
8702 {
8706 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8707 number, sign extend it. */
8720 }
8722 /* fall through */
8725 /* Substituting into the operands of a widening MULT is not likely to
8726 create RTL matching a machine insn. */
8736 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8737 most significant bit in MASK since carries from those bits will
8738 affect the bits we are interested in. */
8743 /* If X is (minus C Y) where C's least set bit is larger than any bit
8744 in the mask, then we may replace with (neg Y). */
8747 {
8750 }
8752 /* Similarly, if C contains every bit in the fuller_mask, then we may
8753 replace with (not Y). */
8756 {
8759 }
8766 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8767 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8768 operation which may be a bitfield extraction. Ensure that the
8769 constant we form is not wider than the mode of X. */
8781 {
8784 xmode);
8790 }
8792 binop:
8793 /* For most binary operations, just propagate into the operation and
8794 change the mode if we have an operation of that mode. */
8799 /* If we ended up truncating both operands, truncate the result of the
8800 operation instead. */
8803 {
8806 }
8812 {
8815 }
8819 /* For left shifts, do the same, but just for the first operand.
8820 However, we cannot do anything with shifts where we cannot
8821 guarantee that the counts are smaller than the size of the mode
8822 because such a count will have a different meaning in a
8823 wider mode. */
8833 /* If the shift count is a constant and we can do arithmetic in
8834 the mode of the shift, refine which bits we need. Otherwise, use the
8835 conservative form of the mask. */
8841 else
8849 {
8852 }
8856 /* Here we can only do something if the shift count is a constant,
8857 this shift constant is valid for the host, and we can do arithmetic
8858 in OP_MODE. */
8864 {
8868 /* Select the mask of the bits we need for the shift operand. */
8871 /* We can only change the mode of the shift if we can do arithmetic
8872 in the mode of the shift and INNER_MASK is no wider than the
8873 width of X's mode. */
8880 {
8883 }
8884 }
8886 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8887 shift and AND produces only copies of the sign bit (C2 is one less
8888 than a power of two), we can do this with just a shift. */
8892 /* The shift puts one of the sign bit copies in the least significant
8893 bit. */
8898 /* Number of bits left after the shift must be more than the mask
8899 needs. */
8902 /* Must be more sign bit copies than the mask needs. */
8912 /* If we are just looking for the sign bit, we don't need this shift at
8913 all, even if it has a variable count. */
8917 /* If this is a shift by a constant, get a mask that contains those bits
8918 that are not copies of the sign bit. We then have two cases: If
8919 MASK only includes those bits, this can be a logical shift, which may
8920 allow simplifications. If MASK is a single-bit field not within
8921 those bits, we are requesting a copy of the sign bit and hence can
8922 shift the sign bit to the appropriate location. */
8926 {
8930 /* If the considered data is wider than HOST_WIDE_INT, we can't
8931 represent a mask for all its bits in a single scalar.
8932 But we only care about the lower bits, so calculate these. */
8935 {
8938 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8939 is the number of bits a full-width mask would have set.
8940 We need only shift if these are fewer than nonzero can
8941 hold. If not, we must keep all bits set in nonzero. */
8946 + HOST_BITS_PER_WIDE_INT
8948 }
8949 else
8950 {
8953 }
8956 {
8961 }
8964 {
8965 x = simplify_shift_const
8971 }
8972 }
8974 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8975 even if the shift count isn't a constant. */
8979 shiftrt:
8981 /* If this is a zero- or sign-extension operation that just affects bits
8982 we don't care about, remove it. Be sure the call above returned
8983 something that is still a shift. */
8993 next_select);
8999 /* If the shift count is constant and we can do computations
9000 in the mode of X, compute where the bits we care about are.
9001 Otherwise, we can't do anything. Don't change the mode of
9002 the shift or propagate MODE into the shift, though. */
9005 {
9014 }
9018 /* If we just want the low-order bit, the NEG isn't needed since it
9019 won't change the low-order bit. */
9023 /* We need any bits less significant than the most significant bit in
9024 MASK since carries from those bits will affect the bits we are
9025 interested in. */
9030 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9031 same as the XOR case above. Ensure that the constant we form is not
9032 wider than the mode of X. */
9040 {
9047 }
9049 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9050 use the full mask inside the NOT. */
9053 unop:
9056 next_select));
9058 {
9061 }
9065 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9066 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9067 which is equal to STORE_FLAG_VALUE. */
9079 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9080 written in a narrower mode. We play it safe and do not do so. */
9096 }
9098 /* Ensure we return a value of the proper mode. */
9100 }
9101 \f
9102 /* Return nonzero if X is an expression that has one of two values depending on
9103 whether some other value is zero or nonzero. In that case, we return the
9104 value that is being tested, *PTRUE is set to the value if the rtx being
9105 returned has a nonzero value, and *PFALSE is set to the other alternative.
9107 If we return zero, we set *PTRUE and *PFALSE to X. */
9109 static rtx
9111 {
9116 scalar_int_mode int_mode;
9118 /* If we are comparing a value against zero, we are done. */
9121 {
9125 }
9127 /* If this is a unary operation whose operand has one of two values, apply
9128 our opcode to compute those values. */
9131 {
9136 }
9138 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9139 make can't possibly match and would suppress other optimizations. */
9141 ;
9143 /* If this is a binary operation, see if either side has only one of two
9144 values. If either one does or if both do and they are conditional on
9145 the same value, compute the new true and false values. */
9147 {
9155 {
9156 /* Try to enable a simplification by undoing work done by
9157 if_then_else_cond if it converted a REG into something more
9158 complex. */
9160 {
9163 }
9164 else
9165 {
9168 }
9169 }
9173 {
9174 /* If if_then_else_cond returned zero, then true/false are the
9175 same rtl. We must copy one of them to prevent invalid rtl
9176 sharing. */
9183 {
9188 }
9189 else
9190 {
9193 }
9196 }
9198 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9199 operands is zero when the other is nonzero, and vice-versa,
9200 and STORE_FLAG_VALUE is 1 or -1. */
9206 {
9223 {
9230 const_true_rtx);
9232 }
9233 }
9235 /* Similarly for MULT, AND and UMIN, except that for these the result
9236 is always zero. */
9240 {
9254 {
9257 }
9258 }
9259 }
9262 {
9263 /* If we have IF_THEN_ELSE already, extract the condition and
9264 canonicalize it if it is NE or EQ. */
9270 {
9273 }
9274 else
9276 }
9278 /* If X is a SUBREG, we can narrow both the true and false values
9279 if the inner expression, if there is a condition. */
9283 {
9289 {
9293 }
9294 }
9296 /* If X is a constant, this isn't special and will cause confusions
9297 if we treat it as such. Likewise if it is equivalent to a constant. */
9300 ;
9302 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9303 will be least confusing to the rest of the compiler. */
9305 {
9308 }
9310 /* If X is known to be either 0 or -1, those are the true and
9311 false values when testing X. */
9316 {
9319 }
9321 /* Likewise for 0 or a single bit. */
9324 {
9327 }
9329 /* Otherwise fail; show no condition with true and false values the same. */
9332 }
9333 \f
9334 /* Return the value of expression X given the fact that condition COND
9335 is known to be true when applied to REG as its first operand and VAL
9336 as its second. X is known to not be shared and so can be modified in
9337 place.
9339 We only handle the simplest cases, and specifically those cases that
9340 arise with IF_THEN_ELSE expressions. */
9342 static rtx
9344 {
9352 /* If either operand of the condition is a floating point value,
9353 then we have to avoid collapsing an EQ comparison. */
9363 /* If X is (abs REG) and we know something about REG's relationship
9364 with zero, we may be able to simplify this. */
9368 {
9377 }
9379 /* The only other cases we handle are MIN, MAX, and comparisons if the
9380 operands are the same as REG and VAL. */
9383 {
9385 {
9388 }
9391 {
9393 {
9401 else
9403 }
9406 {
9409 /* Do not reverse the condition when it is NE or EQ.
9410 This is because we cannot conclude anything about
9411 the value of 'SMAX (x, y)' when x is not equal to y,
9412 but we can when x equals y. */
9418 {
9429 }
9430 }
9431 }
9432 }
9434 {
9439 {
9440 /* We must simplify subreg here, before we lose track of the
9441 original inner_mode. */
9446 else
9448 }
9451 }
9452 /* We don't have to handle SIGN_EXTEND here, because even in the
9453 case of replacing something with a modeless CONST_INT, a
9454 CONST_INT is already (supposed to be) a valid sign extension for
9455 its narrower mode, which implies it's already properly
9456 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9457 story is different. */
9459 {
9464 {
9465 /* We must simplify the zero_extend here, before we lose
9466 track of the original inner_mode. */
9471 else
9473 }
9476 }
9480 {
9487 }
9490 }
9491 \f
9492 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9493 assignment as a field assignment. */
9495 static int
9497 {
9499 {
9504 /* For big endian, adjust the memory offset. */
9509 else
9511 }
9519 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9520 Note that all SUBREGs of MEM are paradoxical; otherwise they
9521 would have been rewritten. */
9534 /* We used to see if get_last_value of X and Y were the same but that's
9535 not correct. In one direction, we'll cause the assignment to have
9536 the wrong destination and in the case, we'll import a register into this
9537 insn that might have already have been dead. So fail if none of the
9538 above cases are true. */
9540 }
9541 \f
9542 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9543 Return that assignment if so.
9545 We only handle the most common cases. */
9547 static rtx
9549 {
9552 rtx assign;
9554 HOST_WIDE_INT c1;
9555 HOST_WIDE_INT pos;
9557 rtx other;
9559 /* All the rules in this function are specific to scalar integers. */
9560 scalar_int_mode mode;
9564 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9565 a clear of a one-bit field. We will have changed it to
9566 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9567 for a SUBREG. */
9573 {
9579 }
9588 {
9595 }
9597 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9598 one-bit field. */
9602 {
9608 }
9610 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9611 SRC is an AND with all bits of that field set, then we can discard
9612 the AND. */
9617 {
9624 else
9627 /* Complete overlap. We can remove the source AND. */
9631 /* Partial overlap. We can reduce the source AND. */
9633 {
9637 }
9638 }
9640 /* The other case we handle is assignments into a constant-position
9641 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9642 a mask that has all one bits except for a group of zero bits and
9643 OTHER is known to have zeros where C1 has ones, this is such an
9644 assignment. Compute the position and length from C1. Shift OTHER
9645 to the appropriate position, force it to the required mode, and
9646 make the extraction. Check for the AND in both operands. */
9648 /* One or more SUBREGs might obscure the constant-position field
9649 assignment. The first one we are likely to encounter is an outer
9650 narrowing SUBREG, which we can just strip for the purposes of
9651 identifying the constant-field assignment. */
9668 /* The second SUBREG that might get in the way is a paradoxical
9669 SUBREG around the first operand of the AND. We want to
9670 pretend the operand is as wide as the destination here. We
9671 do this by adjusting the MEM to wider mode for the sole
9672 purpose of the call to rtx_equal_for_field_assignment_p. Also
9673 note this trick only works for MEMs. */
9685 /* The second SUBREG that might get in the way is a paradoxical
9686 SUBREG around the first operand of the AND. We want to
9687 pretend the operand is as wide as the destination here. We
9688 do this by adjusting the MEM to wider mode for the sole
9689 purpose of the call to rtx_equal_for_field_assignment_p. Also
9690 note this trick only works for MEMs. */
9698 else
9712 /* The mode to use for the source is the mode of the assignment, or of
9713 what is inside a possible STRICT_LOW_PART. */
9717 /* Shift OTHER right POS places and make it the source, restricting it
9718 to the proper length and mode. */
9722 dest);
9724 len >= HOST_BITS_PER_WIDE_INT
9725 ? HOST_WIDE_INT_M1U
9729 /* If SRC is masked by an AND that does not make a difference in
9730 the value being stored, strip it. */
9741 }
9742 \f
9743 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9744 if so. */
9746 static rtx
9748 {
9752 rtx tem;
9754 /* Distributivity is not true for floating point as it can change the
9755 value. So we don't do it unless -funsafe-math-optimizations. */
9760 /* The outer operation can only be one of the following: */
9768 /* If either operand is a primitive we can't do anything, so get out
9769 fast. */
9779 /* See if the inner and outer operations distribute. */
9781 {
9786 /* These all distribute except over PLUS. */
9797 /* This is also a multiply, so it distributes over everything. */
9800 /* This used to handle SUBREG, but this turned out to be counter-
9801 productive, since (subreg (op ...)) usually is not handled by
9802 insn patterns, and this "optimization" therefore transformed
9803 recognizable patterns into unrecognizable ones. Therefore the
9804 SUBREG case was removed from here.
9806 It is possible that distributing SUBREG over arithmetic operations
9807 leads to an intermediate result than can then be optimized further,
9808 e.g. by moving the outer SUBREG to the other side of a SET as done
9809 in simplify_set. This seems to have been the original intent of
9810 handling SUBREGs here.
9812 However, with current GCC this does not appear to actually happen,
9813 at least on major platforms. If some case is found where removing
9814 the SUBREG case here prevents follow-on optimizations, distributing
9815 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9819 }
9821 /* Set LHS and RHS to the inner operands (A and B in the example
9822 above) and set OTHER to the common operand (C in the example).
9823 There is only one way to do this unless the inner operation is
9824 commutative. */
9836 else
9839 /* Form the new inner operation, seeing if it simplifies first. */
9842 /* There is one exception to the general way of distributing:
9843 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9845 {
9848 }
9850 /* We may be able to continuing distributing the result, so call
9851 ourselves recursively on the inner operation before forming the
9852 outer operation, which we return. */
9855 }
9857 /* See if X is of the form (* (+ A B) C), and if so convert to
9858 (+ (* A C) (* B C)) and try to simplify.
9860 Most of the time, this results in no change. However, if some of
9861 the operands are the same or inverses of each other, simplifications
9862 will result.
9864 For example, (and (ior A B) (not B)) can occur as the result of
9865 expanding a bit field assignment. When we apply the distributive
9866 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9867 which then simplifies to (and (A (not B))).
9869 Note that no checks happen on the validity of applying the inverse
9870 distributive law. This is pointless since we can do it in the
9871 few places where this routine is called.
9873 N is the index of the term that is decomposed (the arithmetic operation,
9874 i.e. (+ A B) in the first example above). !N is the index of the term that
9875 is distributed, i.e. of C in the first example above. */
9876 static rtx
9878 {
9879 machine_mode mode;
9883 /* Distributivity is not true for floating point as it can change the
9884 value. So we don't do it unless -funsafe-math-optimizations. */
9901 /* Special case (and (xor B C) (not A)), which is equivalent to
9902 (xor (ior A B) (ior A C)) */
9904 {
9907 }
9910 {
9911 /* Distribute the second term. */
9914 }
9915 else
9916 {
9917 /* Distribute the first term. */
9920 }
9930 }
9931 \f
9932 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9933 in MODE. Return an equivalent form, if different from (and VAROP
9934 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9936 static rtx
9939 {
9942 rtx orig_varop;
9950 /* Simplify VAROP knowing that we will be only looking at some of the
9951 bits in it.
9953 Note by passing in CONSTOP, we guarantee that the bits not set in
9954 CONSTOP are not significant and will never be examined. We must
9955 ensure that is the case by explicitly masking out those bits
9956 before returning. */
9959 /* If VAROP is a CLOBBER, we will fail so return it. */
9963 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9964 to VAROP and return the new constant. */
9968 /* See what bits may be nonzero in VAROP. Unlike the general case of
9969 a call to nonzero_bits, here we don't care about bits outside
9970 MODE. */
9974 /* Turn off all bits in the constant that are known to already be zero.
9975 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9976 which is tested below. */
9980 /* If we don't have any bits left, return zero. */
9984 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9985 a power of two, we can replace this with an ASHIFT. */
9990 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9991 or XOR, then try to apply the distributive law. This may eliminate
9992 operations if either branch can be simplified because of the AND.
9993 It may also make some cases more complex, but those cases probably
9994 won't match a pattern either with or without this. */
9997 {
9999 return
10000 gen_lowpart
10002 apply_distributive_law
10006 constop),
10009 constop))));
10010 }
10012 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10013 the AND and see if one of the operands simplifies to zero. If so, we
10014 may eliminate it. */
10018 {
10027 }
10029 /* Make a SUBREG if necessary. If we can't make it, fail. */
10034 /* If we are only masking insignificant bits, return VAROP. */
10041 /* Otherwise, return an AND. */
10043 }
10046 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10047 in MODE.
10049 Return an equivalent form, if different from X. Otherwise, return X. If
10050 X is zero, we are to always construct the equivalent form. */
10052 static rtx
10055 {
10066 }
10067 \f
10068 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10069 We don't care about bits outside of those defined in MODE.
10071 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10072 a shift, AND, or zero_extract, we can do better. */
10074 static rtx
10076 scalar_int_mode mode,
10078 {
10079 rtx tem;
10082 /* If X is a register whose nonzero bits value is current, use it.
10083 Otherwise, if X is a register whose value we can find, use that
10084 value. Otherwise, use the previously-computed global nonzero bits
10085 for this register. */
10099 && !REGNO_REG_SET_P
10102 {
10103 /* Note that, even if the precision of last_set_mode is lower than that
10104 of mode, record_value_for_reg invoked nonzero_bits on the register
10105 with nonzero_bits_mode (because last_set_mode is necessarily integral
10106 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10107 are all valid, hence in mode too since nonzero_bits_mode is defined
10108 to the largest HWI_COMPUTABLE_MODE_P mode. */
10111 }
10115 {
10120 }
10123 {
10127 /* We don't know anything about the upper bits. */
10131 }
10134 }
10136 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10137 end of X that are known to be equal to the sign bit. X will be used
10138 in mode MODE; the returned value will always be between 1 and the
10139 number of bits in MODE. */
10141 static rtx
10143 scalar_int_mode mode,
10145 {
10146 rtx tem;
10159 && !REGNO_REG_SET_P
10162 {
10165 }
10176 }
10177 \f
10178 /* Return the number of "extended" bits there are in X, when interpreted
10179 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10180 unsigned quantities, this is the number of high-order zero bits.
10181 For signed quantities, this is the number of copies of the sign bit
10182 minus 1. In both case, this function returns the number of "spare"
10183 bits. For example, if two quantities for which this function returns
10184 at least 1 are added, the addition is known not to overflow.
10186 This function will always return 0 unless called during combine, which
10187 implies that it must be called from a define_split. */
10189 unsigned int
10191 {
10195 scalar_int_mode int_mode;
10203 }
10205 /* This function is called from `simplify_shift_const' to merge two
10206 outer operations. Specifically, we have already found that we need
10207 to perform operation *POP0 with constant *PCONST0 at the outermost
10208 position. We would now like to also perform OP1 with constant CONST1
10209 (with *POP0 being done last).
10211 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10212 the resulting operation. *PCOMP_P is set to 1 if we would need to
10213 complement the innermost operand, otherwise it is unchanged.
10215 MODE is the mode in which the operation will be done. No bits outside
10216 the width of this mode matter. It is assumed that the width of this mode
10217 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10219 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10220 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10221 result is simply *PCONST0.
10223 If the resulting operation cannot be expressed as one operation, we
10224 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10226 static int
10227 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10228 {
10235 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10239 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10240 if OP0 is SET. */
10249 {
10251 {
10269 }
10270 }
10272 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10276 /* If the two constants aren't the same, we can't do anything. The
10277 remaining six cases can all be done. */
10281 else
10283 {
10286 /* (a & b) | b == b */
10289 /* (a ^ b) | b == a | b */
10290 {;}
10295 /* (a & b) ^ b == (~a) & b */
10298 /* (a | b) ^ b == a & ~b */
10304 /* (a | b) & b == b */
10307 /* (a ^ b) & b) == (~a) & b */
10312 }
10314 /* Check for NO-OP cases. */
10327 /* ??? Slightly redundant with the above mask, but not entirely.
10328 Moving this above means we'd have to sign-extend the mode mask
10329 for the final test. */
10334 }
10335 \f
10336 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10337 the shift in. The original shift operation CODE is performed on OP in
10338 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10339 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10340 result of the shift is subject to operation OUTER_CODE with operand
10341 OUTER_CONST. */
10343 static scalar_int_mode
10347 {
10350 /* In general we can't perform in wider mode for right shift and rotate. */
10352 {
10354 /* We can still widen if the bits brought in from the left are identical
10355 to the sign bit of ORIG_MODE. */
10363 /* Similarly here but with zero bits. */
10368 /* We can also widen if the bits brought in will be masked off. This
10369 operation is performed in ORIG_MODE. */
10371 {
10377 }
10378 /* fall through */
10388 }
10389 }
10391 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10392 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10393 if we cannot simplify it. Otherwise, return a simplified value.
10395 The shift is normally computed in the widest mode we find in VAROP, as
10396 long as it isn't a different number of words than RESULT_MODE. Exceptions
10397 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10399 static rtx
10402 {
10407 machine_mode shift_mode;
10409 unsigned int mode_words
10411 /* We form (outer_op (code varop count) (outer_const)). */
10417 /* Make sure and truncate the "natural" shift on the way in. We don't
10418 want to do this inside the loop as it makes it more difficult to
10419 combine shifts. */
10423 /* If we were given an invalid count, don't do anything except exactly
10424 what was requested. */
10431 /* Unless one of the branches of the `if' in this loop does a `continue',
10432 we will `break' the loop after the `if'. */
10435 {
10436 /* If we have an operand of (clobber (const_int 0)), fail. */
10440 /* Convert ROTATERT to ROTATE. */
10442 {
10446 }
10450 {
10451 /* We only change the modes of scalar shifts. */
10457 }
10459 scalar_int_mode shift_unit_mode
10462 /* Handle cases where the count is greater than the size of the mode
10463 minus 1. For ASHIFT, use the size minus one as the count (this can
10464 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10465 take the count modulo the size. For other shifts, the result is
10466 zero.
10468 Since these shifts are being produced by the compiler by combining
10469 multiple operations, each of which are defined, we know what the
10470 result is supposed to be. */
10473 {
10478 else
10479 {
10480 /* We can't simply return zero because there may be an
10481 outer op. */
10485 }
10486 }
10488 /* If we discovered we had to complement VAROP, leave. Making a NOT
10489 here would cause an infinite loop. */
10494 {
10495 /* An arithmetic right shift of a quantity known to be -1 or 0
10496 is a no-op. */
10500 {
10503 }
10505 /* If we are doing an arithmetic right shift and discarding all but
10506 the sign bit copies, this is equivalent to doing a shift by the
10507 bitsize minus one. Convert it into that shift because it will
10508 often allow other simplifications. */
10515 /* We simplify the tests below and elsewhere by converting
10516 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10517 `make_compound_operation' will convert it to an ASHIFTRT for
10518 those machines (such as VAX) that don't have an LSHIFTRT. */
10523 shift_unit_mode)))
10535 }
10538 {
10545 {
10548 }
10552 /* The following rules apply only to scalars. */
10557 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10558 minus the width of a smaller mode, we can do this with a
10559 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10566 {
10575 }
10579 /* The following rules apply only to scalars. */
10585 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10586 the same number of words as what we've seen so far. Then store
10587 the widest mode in MODE. */
10593 == mode_words
10595 {
10600 }
10604 /* Some machines use MULT instead of ASHIFT because MULT
10605 is cheaper. But it is still better on those machines to
10606 merge two shifts into one. */
10609 {
10610 varop
10616 }
10620 /* Similar, for when divides are cheaper. */
10623 {
10624 varop
10630 }
10634 /* If we are extracting just the sign bit of an arithmetic
10635 right shift, that shift is not needed. However, the sign
10636 bit of a wider mode may be different from what would be
10637 interpreted as the sign bit in a narrower mode, so, if
10638 the result is narrower, don't discard the shift. */
10643 {
10646 }
10648 /* fall through */
10653 /* The following rules apply only to scalars. */
10660 /* Here we have two nested shifts. The result is usually the
10661 AND of a new shift with a mask. We compute the result below. */
10667 {
10671 rtx mask_rtx;
10673 /* We have one common special case. We can't do any merging if
10674 the inner code is an ASHIFTRT of a smaller mode. However, if
10675 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10676 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10677 we can convert it to
10678 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10679 This simplifies certain SIGN_EXTEND operations. */
10683 {
10684 /* C3 has the low-order C1 bits zero. */
10696 }
10698 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10699 than C1 high-order bits equal to the sign bit, we can convert
10700 this to either an ASHIFT or an ASHIFTRT depending on the
10701 two counts.
10703 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10709 {
10713 {
10716 }
10719 }
10721 /* There are some cases we can't do. If CODE is ASHIFTRT,
10722 we can only do this if FIRST_CODE is also ASHIFTRT.
10724 We can't do the case when CODE is ROTATE and FIRST_CODE is
10725 ASHIFTRT.
10727 If the mode of this shift is not the mode of the outer shift,
10728 we can't do this if either shift is a right shift or ROTATE.
10730 Finally, we can't do any of these if the mode is too wide
10731 unless the codes are the same.
10733 Handle the case where the shift codes are the same
10734 first. */
10737 {
10746 }
10757 /* To compute the mask to apply after the shift, shift the
10758 nonzero bits of the inner shift the same way the
10759 outer shift will. */
10762 int_result_mode);
10764 mask_rtx
10768 /* Give up if we can't compute an outer operation to use. */
10776 /* If the shifts are in the same direction, we add the
10777 counts. Otherwise, we subtract them. */
10781 else
10784 /* If COUNT is positive, the new shift is usually CODE,
10785 except for the two exceptions below, in which case it is
10786 FIRST_CODE. If the count is negative, FIRST_CODE should
10787 always be used */
10797 }
10799 /* If we have (A << B << C) for any shift, we can convert this to
10800 (A << C << B). This wins if A is a constant. Only try this if
10801 B is not a constant. */
10806 {
10807 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10808 sure the result will be masked. See PR70222. */
10816 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10817 up outer sign extension (often left and right shift) is
10818 hardly more efficient than the original. See PR70429. */
10828 }
10832 /* The following rules apply only to scalars. */
10836 /* Make this fit the case below. */
10843 /* The following rules apply only to scalars. */
10849 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10850 with C the size of VAROP - 1 and the shift is logical if
10851 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10852 we have an (le X 0) operation. If we have an arithmetic shift
10853 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10854 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10862 {
10865 const0_rtx);
10871 }
10873 /* If we have (shift (logical)), move the logical to the outside
10874 to allow it to possibly combine with another logical and the
10875 shift to combine with another shift. This also canonicalizes to
10876 what a ZERO_EXTRACT looks like. Also, some machines have
10877 (and (shift)) insns. */
10880 /* We can't do this if we have (ashiftrt (xor)) and the
10881 constant has its sign bit set in shift_unit_mode with
10882 shift_unit_mode wider than result_mode. */
10886 shift_unit_mode))
10895 {
10898 }
10900 /* If we can't do that, try to simplify the shift in each arm of the
10901 logical expression, make a new logical expression, and apply
10902 the inverse distributive law. This also can't be done for
10903 (ashiftrt (xor)) where we've widened the shift and the constant
10904 changes the sign bit. */
10909 shift_unit_mode)))
10910 {
10922 }
10926 /* The following rules apply only to scalars. */
10931 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10932 says that the sign bit can be tested, FOO has mode MODE, C is
10933 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10934 that may be nonzero. */
10944 {
10948 }
10952 /* The following rules apply only to scalars. */
10957 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10958 than the number of bits in the mode is equivalent to A. */
10962 {
10966 }
10968 /* NEG commutes with ASHIFT since it is multiplication. Move the
10969 NEG outside to allow shifts to combine. */
10973 {
10976 }
10980 /* The following rules apply only to scalars. */
10985 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10986 is one less than the number of bits in the mode is
10987 equivalent to (xor A 1). */
10994 {
10998 }
11000 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11001 that might be nonzero in BAR are those being shifted out and those
11002 bits are known zero in FOO, we can replace the PLUS with FOO.
11003 Similarly in the other operand order. This code occurs when
11004 we are computing the size of a variable-size array. */
11011 {
11014 }
11022 {
11025 }
11027 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11038 {
11041 }
11043 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11044 signbit', and attempt to change the PLUS to an XOR and move it to
11045 the outer operation as is done above in the AND/IOR/XOR case
11046 leg for shift(logical). See details in logical handling above
11047 for reasoning in doing so. */
11059 {
11062 }
11067 /* The following rules apply only to scalars. */
11072 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11073 with C the size of VAROP - 1 and the shift is logical if
11074 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11075 we have a (gt X 0) operation. If the shift is arithmetic with
11076 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11077 we have a (neg (gt X 0)) operation. */
11086 {
11089 const0_rtx);
11095 }
11099 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11100 if the truncate does not affect the value. */
11107 {
11110 varop_inner
11113 GEN_INT
11118 }
11123 }
11126 }
11130 {
11131 /* We only change the modes of scalar shifts. */
11136 }
11138 /* We have now finished analyzing the shift. The result should be
11139 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11140 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11141 to the result of the shift. OUTER_CONST is the relevant constant,
11142 but we must turn off all bits turned off in the shift. */
11150 /* Make a SUBREG if necessary. If we can't make it, fail. */
11155 /* If we have an outer operation and we just made a shift, it is
11156 possible that we could have simplified the shift were it not
11157 for the outer operation. So try to do the simplification
11158 recursively. */
11162 else
11168 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11169 turn off all the bits that the shift would have turned off. */
11171 /* We only change the modes of scalar shifts. */
11175 /* Do the remainder of the processing in RESULT_MODE. */
11178 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11179 operation. */
11184 {
11194 {
11195 /* This means that we have determined that the result is
11196 equivalent to a constant. This should be rare. */
11199 }
11202 else
11205 }
11208 }
11210 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11211 The result of the shift is RESULT_MODE. If we cannot simplify it,
11212 return X or, if it is NULL, synthesize the expression with
11213 simplify_gen_binary. Otherwise, return a simplified value.
11215 The shift is normally computed in the widest mode we find in VAROP, as
11216 long as it isn't a different number of words than RESULT_MODE. Exceptions
11217 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11219 static rtx
11222 {
11232 }
11234 \f
11235 /* A subroutine of recog_for_combine. See there for arguments and
11236 return value. */
11238 static int
11240 {
11242 rtx pat_without_clobbers;
11250 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11251 we use to indicate that something didn't match. If we find such a
11252 thing, force rejection. */
11266 {
11269 else
11272 }
11274 /* If it isn't, there is the possibility that we previously had an insn
11275 that clobbered some register as a side effect, but the combined
11276 insn doesn't need to do that. So try once more without the clobbers
11277 unless this represents an ASM insn. */
11281 {
11286 {
11289 pos++;
11290 }
11300 {
11303 else
11306 }
11307 }
11314 /* Recognize all noop sets, these will be killed by followup pass. */
11318 /* If we had any clobbers to add, make a new pattern than contains
11319 them. Then check to make sure that all of them are dead. */
11321 {
11331 else
11338 {
11343 {
11347 }
11348 }
11350 }
11354 {
11362 /* Allow targets to reject combined insn. */
11364 {
11367 dump_file);
11369 /* Callers expect recog_for_combine to strip
11370 clobbers from the pattern on failure. */
11375 }
11380 }
11386 }
11388 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11389 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11390 Return whether anything was so changed. */
11392 static bool
11394 {
11400 {
11412 {
11421 else
11425 }
11431 {
11437 }
11442 {
11446 }
11447 else
11453 {
11456 }
11460 }
11467 scalar_int_mode mode;
11473 {
11487 else
11495 }
11498 }
11500 /* Like recog, but we receive the address of a pointer to a new pattern.
11501 We try to match the rtx that the pointer points to.
11502 If that fails, we may try to modify or replace the pattern,
11503 storing the replacement into the same pointer object.
11505 Modifications include deletion or addition of CLOBBERs. If the
11506 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11507 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11508 (and undo if that fails).
11510 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11511 the CLOBBERs are placed.
11513 The value is the final insn code from the pattern ultimately matched,
11514 or -1. */
11516 static int
11518 {
11530 {
11533 {
11537 }
11538 }
11541 {
11546 }
11549 }
11550 \f
11551 /* Like gen_lowpart_general but for use by combine. In combine it
11552 is not possible to create any new pseudoregs. However, it is
11553 safe to create invalid memory addresses, because combine will
11554 try to recognize them and all they will do is make the combine
11555 attempt fail.
11557 If for some reason this cannot do its job, an rtx
11558 (clobber (const_int 0)) is returned.
11559 An insn containing that will not be recognized. */
11561 static rtx
11563 {
11567 rtx result;
11572 /* We can only support MODE being wider than a word if X is a
11573 constant integer or has a mode the same size. */
11578 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11579 won't know what to do. So we will strip off the SUBREG here and
11580 process normally. */
11582 {
11585 /* For use in case we fall down into the address adjustments
11586 further below, we need to adjust the known mode and size of
11587 x; imode and isize, since we just adjusted x. */
11594 }
11602 {
11605 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11606 address. */
11611 /* If we want to refer to something bigger than the original memref,
11612 generate a paradoxical subreg instead. That will force a reload
11613 of the original memref X. */
11620 /* Adjust the address so that the address-after-the-data is
11621 unchanged. */
11626 }
11628 /* If X is a comparison operator, rewrite it in a new mode. This
11629 probably won't match, but may allow further simplifications. */
11633 /* If we couldn't simplify X any other way, just enclose it in a
11634 SUBREG. Normally, this SUBREG won't match, but some patterns may
11635 include an explicit SUBREG or we may simplify it further in combine. */
11636 else
11637 {
11638 rtx res;
11641 {
11646 }
11650 }
11652 fail:
11654 }
11655 \f
11656 /* Try to simplify a comparison between OP0 and a constant OP1,
11657 where CODE is the comparison code that will be tested, into a
11658 (CODE OP0 const0_rtx) form.
11660 The result is a possibly different comparison code to use.
11661 *POP1 may be updated. */
11663 static enum rtx_code
11666 {
11667 scalar_int_mode int_mode;
11670 /* Get the constant we are comparing against and turn off all bits
11671 not on in our mode. */
11675 /* If we are comparing against a constant power of two and the value
11676 being compared can only have that single bit nonzero (e.g., it was
11677 `and'ed with that bit), we can replace this with a comparison
11678 with zero. */
11687 {
11690 }
11692 /* Similarly, if we are comparing a value known to be either -1 or
11693 0 with -1, change it to the opposite comparison against zero. */
11699 {
11702 }
11704 /* Do some canonicalizations based on the comparison code. We prefer
11705 comparisons against zero and then prefer equality comparisons.
11706 If we can reduce the size of a constant, we will do that too. */
11708 {
11710 /* < C is equivalent to <= (C - 1) */
11712 {
11715 /* ... fall through to LE case below. */
11717 }
11718 else
11722 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11724 {
11727 }
11729 /* If we are doing a <= 0 comparison on a value known to have
11730 a zero sign bit, we can replace this with == 0. */
11741 /* >= C is equivalent to > (C - 1). */
11743 {
11746 /* ... fall through to GT below. */
11748 }
11749 else
11753 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11755 {
11758 }
11760 /* If we are doing a > 0 comparison on a value known to have
11761 a zero sign bit, we can replace this with != 0. */
11772 /* < C is equivalent to <= (C - 1). */
11774 {
11777 /* ... fall through ... */
11778 }
11779 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11784 {
11788 }
11789 else
11793 /* unsigned <= 0 is equivalent to == 0 */
11796 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11800 == ((HOST_WIDE_INT_1U
11802 {
11805 }
11809 /* >= C is equivalent to > (C - 1). */
11811 {
11814 /* ... fall through ... */
11815 }
11817 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11822 {
11826 }
11827 else
11831 /* unsigned > 0 is equivalent to != 0 */
11834 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11838 == (HOST_WIDE_INT_1U
11840 {
11843 }
11848 }
11852 }
11853 \f
11854 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11855 comparison code that will be tested.
11857 The result is a possibly different comparison code to use. *POP0 and
11858 *POP1 may be updated.
11860 It is possible that we might detect that a comparison is either always
11861 true or always false. However, we do not perform general constant
11862 folding in combine, so this knowledge isn't useful. Such tautologies
11863 should have been detected earlier. Hence we ignore all such cases. */
11865 static enum rtx_code
11867 {
11873 opt_scalar_int_mode tmode_iter;
11875 /* Try a few ways of applying the same transformation to both operands. */
11877 {
11878 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11879 so check specially. */
11898 {
11901 }
11903 /* If both operands are the same constant shift, see if we can ignore the
11904 shift. We can if the shift is a rotate or if the bits shifted out of
11905 this shift are known to be zero for both inputs and if the type of
11906 comparison is compatible with the shift. */
11919 {
11932 else
11934 }
11936 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11937 SUBREGs are of the same mode, and, in both cases, the AND would
11938 be redundant if the comparison was done in the narrower mode,
11939 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11940 and the operand's possibly nonzero bits are 0xffffff01; in that case
11941 if we only care about QImode, we don't need the AND). This case
11942 occurs if the output mode of an scc insn is not SImode and
11943 STORE_FLAG_VALUE == 1 (e.g., the 386).
11945 Similarly, check for a case where the AND's are ZERO_EXTEND
11946 operations from some narrower mode even though a SUBREG is not
11947 present. */
11952 {
11969 {
11973 /* The resulting comparison is always unsigned since we masked
11974 off the original sign bit. */
11978 }
11984 {
11990 }
11994 }
11996 /* If both operands are NOT, we can strip off the outer operation
11997 and adjust the comparison code for swapped operands; similarly for
11998 NEG, except that this must be an equality comparison. */
12004 else
12006 }
12008 /* If the first operand is a constant, swap the operands and adjust the
12009 comparison code appropriately, but don't do this if the second operand
12010 is already a constant integer. */
12012 {
12015 }
12017 /* We now enter a loop during which we will try to simplify the comparison.
12018 For the most part, we only are concerned with comparisons with zero,
12019 but some things may really be comparisons with zero but not start
12020 out looking that way. */
12023 {
12025 scalar_int_mode int_mode;
12029 HOST_WIDE_INT const_op;
12031 /* We only want to handle integral modes. This catches VOIDmode,
12032 CCmode, and the floating-point modes. An exception is that we
12033 can handle VOIDmode if OP0 is a COMPARE or a comparison
12034 operation. */
12041 /* Try to simplify the compare to constant, possibly changing the
12042 comparison op, and/or changing op1 to zero. */
12046 /* Compute some predicates to simplify code below. */
12053 /* If this is a sign bit comparison and we can do arithmetic in
12054 MODE, say that we will only be needing the sign bit of OP0. */
12059 HOST_WIDE_INT_1U
12064 {
12065 /* We can't do anything if OP0 is a condition code value, rather
12066 than an actual data value. */
12072 /* Get the two operands being compared. */
12075 else
12078 /* Check for the cases where we simply want the result of the
12079 earlier test or the opposite of that result. */
12083 {
12087 else
12091 {
12096 }
12097 }
12099 }
12105 /* Now try cases based on the opcode of OP0. If none of the cases
12106 does a "continue", we exit this loop immediately after the
12107 switch. */
12112 {
12114 /* If we are extracting a single bit from a variable position in
12115 a constant that has only a single bit set and are comparing it
12116 with zero, we can convert this into an equality comparison
12117 between the position and the location of the single bit. */
12118 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12119 have already reduced the shift count modulo the word size. */
12125 {
12133 /* Result is nonzero iff shift count is equal to I. */
12136 }
12138 /* fall through */
12143 {
12146 }
12150 /* If testing for equality, we can take the NOT of the constant. */
12153 {
12157 }
12159 /* If just looking at the sign bit, reverse the sense of the
12160 comparison. */
12162 {
12166 }
12170 /* If testing for equality, we can take the NEG of the constant. */
12173 {
12177 }
12179 /* The remaining cases only apply to comparisons with zero. */
12183 /* When X is ABS or is known positive,
12184 (neg X) is < 0 if and only if X != 0. */
12192 {
12196 }
12198 /* If we have NEG of something whose two high-order bits are the
12199 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12201 {
12205 }
12209 /* If we are testing equality and our count is a constant, we
12210 can perform the inverse operation on our RHS. */
12214 {
12218 }
12220 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12221 a particular bit. Convert it to an AND of a constant of that
12222 bit. This will be converted into a ZERO_EXTRACT. */
12226 {
12228 (HOST_WIDE_INT_1U
12233 }
12235 /* Fall through. */
12238 /* ABS is ignorable inside an equality comparison with zero. */
12240 {
12243 }
12247 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12248 (compare FOO CONST) if CONST fits in FOO's mode and we
12249 are either testing inequality or have an unsigned
12250 comparison with ZERO_EXTEND or a signed comparison with
12251 SIGN_EXTEND. But don't do it if we don't have a compare
12252 insn of the given mode, since we'd have to revert it
12253 later on, and then we wouldn't know whether to sign- or
12254 zero-extend. */
12256 && ! unsigned_comparison_p
12260 {
12263 }
12267 /* Check for the case where we are comparing A - C1 with C2, that is
12269 (subreg:MODE (plus (A) (-C1))) op (C2)
12271 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12272 comparison in the wider mode. One of the following two conditions
12273 must be true in order for this to be valid:
12275 1. The mode extension results in the same bit pattern being added
12276 on both sides and the comparison is equality or unsigned. As
12277 C2 has been truncated to fit in MODE, the pattern can only be
12278 all 0s or all 1s.
12280 2. The mode extension results in the sign bit being copied on
12281 each side.
12283 The difficulty here is that we have predicates for A but not for
12284 (A - C1) so we need to check that C1 is within proper bounds so
12285 as to perturbate A as little as possible. */
12294 {
12302 /* (A - C1) zero-extends if it is positive and sign-extends
12303 if it is negative, C2 both zero- and sign-extends. */
12307 /* (A - C1) sign-extends if it is positive and 1-extends
12308 if it is negative, C2 both sign- and 1-extends. */
12315 /* (A - C1) always sign-extends, like C2. */
12319 {
12322 }
12323 }
12325 /* If the inner mode is narrower and we are extracting the low part,
12326 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12328 ;
12337 {
12338 /* Remove outer subregs that don't do anything. */
12343 {
12347 }
12349 }
12350 else
12353 /* FALLTHROUGH */
12362 {
12365 }
12369 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12370 this for equality comparisons due to pathological cases involving
12371 overflows. */
12375 {
12379 }
12381 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12384 {
12388 }
12392 /* We used to optimize signed comparisons against zero, but that
12393 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12394 arrive here as equality comparisons, or (GEU, LTU) are
12395 optimized away. No need to special-case them. */
12397 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12398 (eq B (minus A C)), whichever simplifies. We can only do
12399 this for equality comparisons due to pathological cases involving
12400 overflows. */
12404 {
12408 }
12413 {
12417 }
12419 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12420 of bits in X minus 1, is one iff X > 0. */
12425 {
12429 }
12433 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12434 if C is zero or B is a constant. */
12438 {
12442 }
12447 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12448 iff X <= 0. */
12452 {
12456 }
12460 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12461 will be converted to a ZERO_EXTRACT later. */
12465 {
12470 }
12472 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12473 zero and X is a comparison and C1 and C2 describe only bits set
12474 in STORE_FLAG_VALUE, we can compare with X. */
12482 {
12489 {
12492 }
12493 }
12495 /* If we are doing an equality comparison of an AND of a bit equal
12496 to the sign bit, replace this with a LT or GE comparison of
12497 the underlying value. */
12504 {
12508 }
12510 /* If this AND operation is really a ZERO_EXTEND from a narrower
12511 mode, the constant fits within that mode, and this is either an
12512 equality or unsigned comparison, try to do this comparison in
12513 the narrower mode.
12515 Note that in:
12517 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12518 -> (ne:DI (reg:SI 4) (const_int 0))
12520 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12521 known to hold a value of the required mode the
12522 transformation is invalid. */
12530 {
12533 }
12535 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12536 fits in both M1 and M2 and the SUBREG is either paradoxical
12537 or represents the low part, permute the SUBREG and the AND
12538 and try again. */
12541 {
12543 /* Require an integral mode, to avoid creating something like
12544 (AND:SF ...). */
12547 /* It is unsafe to commute the AND into the SUBREG if the
12548 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12549 not defined. As originally written the upper bits
12550 have a defined value due to the AND operation.
12551 However, if we commute the AND inside the SUBREG then
12552 they no longer have defined values and the meaning of
12553 the code has been changed.
12554 Also C1 should not change value in the smaller mode,
12555 see PR67028 (a positive C1 can become negative in the
12556 smaller mode, so that the AND does no longer mask the
12557 upper bits). */
12558 && ((WORD_REGISTER_OPERATIONS
12570 {
12576 }
12577 }
12579 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12583 {
12588 }
12590 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12591 (eq (and (lshiftrt X) 1) 0).
12592 Also handle the case where (not X) is expressed using xor. */
12596 {
12606 == HOST_WIDE_INT_1U
12608 {
12609 op0
12614 }
12615 }
12619 /* If we have (compare (ashift FOO N) (const_int C)) and
12620 the high order N bits of FOO (N+1 if an inequality comparison)
12621 are known to be zero, we can do this by comparing FOO with C
12622 shifted right N bits so long as the low-order N bits of C are
12623 zero. */
12635 {
12636 /* We must perform a logical shift, not an arithmetic one,
12637 as we want the top N bits of C to be zero. */
12644 }
12646 /* If we are doing a sign bit comparison, it means we are testing
12647 a particular bit. Convert it to the appropriate AND. */
12650 {
12652 (HOST_WIDE_INT_1U
12657 }
12659 /* If this an equality comparison with zero and we are shifting
12660 the low bit to the sign bit, we can convert this to an AND of the
12661 low-order bit. */
12665 {
12668 }
12672 /* If this is an equality comparison with zero, we can do this
12673 as a logical shift, which might be much simpler. */
12676 {
12681 }
12683 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12684 do the comparison in a narrower mode. */
12694 {
12697 }
12699 /* Likewise if OP0 is a PLUS of a sign extension with a
12700 constant, which is usually represented with the PLUS
12701 between the shifts. */
12713 {
12721 new_const);
12723 }
12725 /* FALLTHROUGH */
12727 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12728 the low order N bits of FOO are known to be zero, we can do this
12729 by comparing FOO with C shifted left N bits so long as no
12730 overflow occurs. Even if the low order N bits of FOO aren't known
12731 to be zero, if the comparison is >= or < we can use the same
12732 optimization and for > or <= by setting all the low
12733 order N bits in the comparison constant. */
12744 {
12745 unsigned HOST_WIDE_INT low_bits
12747 & ((HOST_WIDE_INT_1U
12750 {
12751 /* If the shift was logical, then we must make the condition
12752 unsigned. */
12761 const_op
12766 }
12767 }
12769 /* If we are using this shift to extract just the sign bit, we
12770 can replace this with an LT or GE comparison. */
12775 {
12779 }
12784 }
12787 }
12789 /* Now make any compound operations involved in this comparison. Then,
12790 check for an outmost SUBREG on OP0 that is not doing anything or is
12791 paradoxical. The latter transformation must only be performed when
12792 it is known that the "extra" bits will be the same in op0 and op1 or
12793 that they don't matter. There are three cases to consider:
12795 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12796 care bits and we can assume they have any convenient value. So
12797 making the transformation is safe.
12799 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12800 In this case the upper bits of op0 are undefined. We should not make
12801 the simplification in that case as we do not know the contents of
12802 those bits.
12804 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12805 In that case we know those bits are zeros or ones. We must also be
12806 sure that they are the same as the upper bits of op1.
12808 We can never remove a SUBREG for a non-equality comparison because
12809 the sign bit is in a different place in the underlying object. */
12822 {
12824 {
12825 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12826 implemented. */
12828 {
12831 }
12832 }
12836 {
12841 }
12842 }
12844 /* We now do the opposite procedure: Some machines don't have compare
12845 insns in all modes. If OP0's mode is an integer mode smaller than a
12846 word and we can't do a compare in that mode, see if there is a larger
12847 mode for which we can do the compare. There are a number of cases in
12848 which we can use the wider mode. */
12854 {
12859 {
12862 /* If this is a test for negative, we can make an explicit
12863 test of the sign bit. Test this first so we can use
12864 a paradoxical subreg to extend OP0. */
12868 {
12869 unsigned HOST_WIDE_INT sign
12876 }
12878 /* If the only nonzero bits in OP0 and OP1 are those in the
12879 narrower mode and this is an equality or unsigned comparison,
12880 we can use the wider mode. Similarly for sign-extended
12881 values, in which case it is true for all comparisons. */
12898 {
12899 /* If OP0 is an AND and we don't have an AND in MODE either,
12900 make a new AND in the proper mode. */
12908 else
12909 {
12911 {
12916 }
12917 else
12918 {
12923 }
12925 }
12926 }
12927 }
12928 }
12930 /* We may have changed the comparison operands. Re-canonicalize. */
12932 {
12935 }
12937 /* If this machine only supports a subset of valid comparisons, see if we
12938 can convert an unsupported one into a supported one. */
12945 }
12946 \f
12947 /* Utility function for record_value_for_reg. Count number of
12948 rtxs in X. */
12949 static int
12951 {
12958 {
12978 }
12989 }
12990 \f
12991 /* Utility function for following routine. Called when X is part of a value
12992 being stored into last_set_value. Sets last_set_table_tick
12993 for each register mentioned. Similar to mention_regs in cse.c */
12995 static void
12997 {
13003 {
13009 {
13012 }
13015 }
13019 {
13020 /* Check for identical subexpressions. If x contains
13021 identical subexpression we only have to traverse one of
13022 them. */
13024 {
13025 /* Note that at this point x1 has already been
13026 processed. */
13030 /* If x0 and x1 are identical then there is no need to
13031 process x0. */
13035 /* If x0 is identical to a subexpression of x1 then while
13036 processing x1, x0 has already been processed. Thus we
13037 are done with x. */
13042 /* If x1 is identical to a subexpression of x0 then we
13043 still have to process the rest of x0. */
13046 {
13049 }
13050 }
13053 }
13057 }
13059 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13060 are saying that the register is clobbered and we no longer know its
13061 value. If INSN is zero, don't update reg_stat[].last_set; this is
13062 only permitted with VALUE also zero and is used to invalidate the
13063 register. */
13065 static void
13067 {
13073 /* If VALUE contains REG and we have a previous value for REG, substitute
13074 the previous value. */
13076 {
13077 rtx tem;
13079 /* Set things up so get_last_value is allowed to see anything set up to
13080 our insn. */
13084 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13085 it isn't going to be useful and will take a lot of time to process,
13086 so just use the CLOBBER. */
13089 {
13095 {
13096 /* If there are two or more occurrences of REG in VALUE,
13097 prevent the value from growing too much. */
13100 }
13103 }
13104 }
13106 /* For each register modified, show we don't know its value, that
13107 we don't know about its bitwise content, that its value has been
13108 updated, and that we don't know the location of the death of the
13109 register. */
13111 {
13123 }
13125 /* Mark registers that are being referenced in this value. */
13129 /* Now update the status of each register being set.
13130 If someone is using this register in this block, set this register
13131 to invalid since we will get confused between the two lives in this
13132 basic block. This makes using this register always invalid. In cse, we
13133 scan the table to invalidate all entries using this register, but this
13134 is too much work for us. */
13137 {
13143 else
13145 }
13147 /* The value being assigned might refer to X (like in "x++;"). In that
13148 case, we must replace it with (clobber (const_int 0)) to prevent
13149 infinite loops. */
13152 {
13156 }
13158 /* For the main register being modified, update the value, the mode, the
13159 nonzero bits, and the number of sign bit copies. */
13164 {
13172 rsp->last_set_sign_bit_copies
13174 }
13175 }
13177 /* Called via note_stores from record_dead_and_set_regs to handle one
13178 SET or CLOBBER in an insn. DATA is the instruction in which the
13179 set is occurring. */
13181 static void
13183 {
13190 {
13194 }
13197 {
13198 /* If we are setting the whole register, we know its value. Otherwise
13199 show that we don't know the value. We can handle SUBREG in
13200 some cases. */
13211 else
13213 }
13215 /* Ignore pushes, they clobber nothing. */
13218 }
13220 /* Update the records of when each REG was most recently set or killed
13221 for the things done by INSN. This is the last thing done in processing
13222 INSN in the combiner loop.
13224 We update reg_stat[], in particular fields last_set, last_set_value,
13225 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13226 last_death, and also the similar information mem_last_set (which insn
13227 most recently modified memory) and last_call_luid (which insn was the
13228 most recent subroutine call). */
13230 static void
13232 {
13233 rtx link;
13237 {
13240 {
13245 {
13250 }
13251 }
13254 }
13257 {
13258 hard_reg_set_iterator hrsi;
13260 {
13272 }
13276 /* We can't combine into a call pattern. Remember, though, that
13277 the return value register is set at this LUID. We could
13278 still replace a register with the return value from the
13279 wrong subroutine call! */
13281 }
13282 else
13284 }
13286 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13287 register present in the SUBREG, so for each such SUBREG go back and
13288 adjust nonzero and sign bit information of the registers that are
13289 known to have some zero/sign bits set.
13291 This is needed because when combine blows the SUBREGs away, the
13292 information on zero/sign bits is lost and further combines can be
13293 missed because of that. */
13295 static void
13297 {
13299 rtx set;
13307 {
13316 {
13319 }
13323 {
13326 }
13329 {
13332 }
13333 else
13335 }
13336 }
13338 /* Check if X, a register, is known to contain a value already
13339 truncated to MODE. In this case we can use a subreg to refer to
13340 the truncated value even though in the generic case we would need
13341 an explicit truncation. */
13343 static bool
13345 {
13357 }
13359 /* If X is a hard reg or a subreg record the mode that the register is
13360 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13361 able to turn a truncate into a subreg using this information. Return true
13362 if traversing X is complete. */
13364 static bool
13366 {
13367 machine_mode truncated_mode;
13371 {
13383 }
13384 /* ??? For hard-regs we now record everything. We might be able to
13385 optimize this using last_set_mode. */
13388 else
13395 {
13398 }
13401 }
13403 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13404 the modes they are used in. This can help truning TRUNCATEs into
13405 SUBREGs. */
13407 static void
13409 {
13414 }
13416 /* Scan X for promoted SUBREGs. For each one found,
13417 note what it implies to the registers used in it. */
13419 static void
13421 {
13426 else
13427 {
13433 {
13443 }
13444 }
13445 }
13446 \f
13447 /* Verify that all the registers and memory references mentioned in *LOC are
13448 still valid. *LOC was part of a value set in INSN when label_tick was
13449 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13450 the invalid references with (clobber (const_int 0)) and return 1. This
13451 replacement is useful because we often can get useful information about
13452 the form of a value (e.g., if it was produced by a shift that always
13453 produces -1 or 0) even though we don't know exactly what registers it
13454 was produced from. */
13456 static int
13458 {
13465 {
13471 {
13474 /* If this is a pseudo-register that was only set once and not
13475 live at the beginning of the function, it is always valid. */
13479 && (!REGNO_REG_SET_P
13481 regno)))
13483 {
13487 }
13488 }
13491 }
13492 /* If this is a memory reference, make sure that there were no stores after
13493 it that might have clobbered the value. We don't have alias info, so we
13494 assume any store invalidates it. Moreover, we only have local UIDs, so
13495 we also assume that there were stores in the intervening basic blocks. */
13498 {
13502 }
13505 {
13507 {
13508 /* Check for identical subexpressions. If x contains
13509 identical subexpression we only have to traverse one of
13510 them. */
13512 {
13513 /* Note that at this point x0 has already been checked
13514 and found valid. */
13518 /* If x0 and x1 are identical then x is also valid. */
13522 /* If x1 is identical to a subexpression of x0 then
13523 while checking x0, x1 has already been checked. Thus
13524 it is valid and so as x. */
13529 /* If x0 is identical to a subexpression of x1 then x is
13530 valid iff the rest of x1 is valid. */
13533 return
13537 }
13542 }
13548 }
13550 /* If we haven't found a reason for it to be invalid, it is valid. */
13552 }
13554 /* Get the last value assigned to X, if known. Some registers
13555 in the value may be replaced with (clobber (const_int 0)) if their value
13556 is known longer known reliably. */
13558 static rtx
13560 {
13562 rtx value;
13565 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13566 then convert it to the desired mode. If this is a paradoxical SUBREG,
13567 we cannot predict what values the "extra" bits might have. */
13581 /* If we don't have a value, or if it isn't for this basic block and
13582 it's either a hard register, set more than once, or it's a live
13583 at the beginning of the function, return 0.
13585 Because if it's not live at the beginning of the function then the reg
13586 is always set before being used (is never used without being set).
13587 And, if it's set only once, and it's always set before use, then all
13588 uses must have the same last value, even if it's not from this basic
13589 block. */
13596 || REGNO_REG_SET_P
13600 /* If the value was set in a later insn than the ones we are processing,
13601 we can't use it even if the register was only set once. */
13606 /* If fewer bits were set than what we are asked for now, we cannot use
13607 the value. */
13612 /* If the value has all its registers valid, return it. */
13616 /* Otherwise, make a copy and replace any invalid register with
13617 (clobber (const_int 0)). If that fails for some reason, return 0. */
13624 }
13625 \f
13626 /* Return nonzero if expression X refers to a REG or to memory
13627 that is set in an instruction more recent than FROM_LUID. */
13629 static int
13631 {
13637 {
13641 #ifdef PUSH_ROUNDING
13642 /* Don't allow uses of the stack pointer to be moved,
13643 because we don't know whether the move crosses a push insn. */
13646 #endif
13648 {
13654 }
13656 }
13664 {
13666 {
13671 }
13675 }
13677 }
13678 \f
13679 /* Define three variables used for communication between the following
13680 routines. */
13685 /* Function called via note_stores from reg_dead_at_p.
13687 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13688 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13690 static void
13692 {
13702 }
13704 /* Return nonzero if REG is known to be dead at INSN.
13706 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13707 referencing REG, it is dead. If we hit a SET referencing REG, it is
13708 live. Otherwise, see if it is live or dead at the start of the basic
13709 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13710 must be assumed to be always live. */
13712 static int
13714 {
13715 basic_block block;
13718 /* Set variables for reg_dead_at_p_1. */
13724 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13725 we allow the machine description to decide whether use-and-clobber
13726 patterns are OK. */
13728 {
13732 }
13734 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13735 beginning of basic block. */
13738 {
13740 {
13750 }
13756 }
13758 /* Look at live-in sets for the basic block that we were in. */
13764 }
13765 \f
13766 /* Note hard registers in X that are used. */
13768 static void
13770 {
13776 {
13780 CASE_CONST_ANY:
13785 /* CC0 must die in the insn after it is set, so we don't need to take
13786 special note of it here. */
13791 /* If we are clobbering a MEM, mark any hard registers inside the
13792 address as used. */
13799 /* A hard reg in a wide mode may really be multiple registers.
13800 If so, mark all of them just like the first. */
13802 {
13803 /* None of this applies to the stack, frame or arg pointers. */
13805 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13813 }
13817 {
13818 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13819 the address. */
13831 }
13836 }
13838 /* Recursively scan the operands of this expression. */
13840 {
13844 {
13848 {
13853 }
13854 }
13855 }
13856 }
13857 \f
13858 /* Remove register number REGNO from the dead registers list of INSN.
13860 Return the note used to record the death, if there was one. */
13862 rtx
13864 {
13871 }
13873 /* For each register (hardware or pseudo) used within expression X, if its
13874 death is in an instruction with luid between FROM_LUID (inclusive) and
13875 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13876 list headed by PNOTES.
13878 That said, don't move registers killed by maybe_kill_insn.
13880 This is done when X is being merged by combination into TO_INSN. These
13881 notes will then be distributed as needed. */
13883 static void
13886 {
13892 {
13896 /* Don't move the register if it gets killed in between from and to. */
13905 {
13908 /* It is possible for the call above to return 0. This can occur
13909 when last_death points to I2 or I1 that we combined with.
13910 In that case make a new note.
13912 We must also check for the case where X is a hard register
13913 and NOTE is a death note for a range of hard registers
13914 including X. In that case, we must put REG_DEAD notes for
13915 the remaining registers in place of NOTE. */
13919 {
13928 }
13930 /* If we didn't find any note, or if we found a REG_DEAD note that
13931 covers only part of the given reg, and we have a multi-reg hard
13932 register, then to be safe we must check for REG_DEAD notes
13933 for each register other than the first. They could have
13934 their own REG_DEAD notes lying around. */
13941 {
13948 else
13954 }
13957 {
13960 }
13961 else
13963 }
13966 }
13969 {
13974 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13975 that accesses one word of a multi-word item, some
13976 piece of everything register in the expression is used by
13977 this insn, so remove any old death. */
13978 /* ??? So why do we test for equality of the sizes? */
13987 {
13990 }
13992 /* If this is some other SUBREG, we know it replaces the entire
13993 value, so use that as the destination. */
13997 /* If this is a MEM, adjust deaths of anything used in the address.
13998 For a REG (the only other possibility), the entire value is
13999 being replaced so the old value is not used in this insn. */
14005 }
14014 {
14016 {
14021 }
14024 }
14025 }
14026 \f
14027 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14028 pattern of an insn. X must be a REG. */
14030 static int
14032 {
14036 {
14038 rtx target;
14045 else
14062 }
14070 }
14071 \f
14072 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14073 as appropriate. I3 and I2 are the insns resulting from the combination
14074 insns including FROM (I2 may be zero).
14076 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14077 not need REG_DEAD notes because they are being substituted for. This
14078 saves searching in the most common cases.
14080 Each note in the list is either ignored or placed on some insns, depending
14081 on the type of note. */
14083 static void
14086 {
14088 rtx tem_note;
14092 {
14097 {
14100 /* Doesn't matter much where we put this, as long as it's somewhere.
14101 It is preferable to keep these notes on branches, which is most
14102 likely to be i3. */
14109 else
14110 {
14113 }
14117 /* These notes must remain with the call or trapping instruction. */
14122 else
14123 {
14129 /* ??? Otherwise assume we've combined things such that we
14130 can now prove that the instructions can't trap. Drop the
14131 note in this case. */
14132 }
14136 /* ??? How to distribute between i3-i1. Assume i3 contains the
14137 entire adjustment. Assert i3 contains at least some adjust. */
14139 {
14141 /* fixup_args_size_notes looks at REG_NORETURN note,
14142 so ensure the note is placed there first. */
14144 {
14148 {
14154 }
14155 }
14157 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14158 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14161 && !ACCUMULATE_OUTGOING_ARGS
14163 }
14170 /* These notes must remain with the call. It should not be
14171 possible for both I2 and I3 to be a call. */
14174 else
14175 {
14178 }
14182 /* Any clobbers for i3 may still exist, and so we must process
14183 REG_UNUSED notes from that insn.
14185 Any clobbers from i2 or i1 can only exist if they were added by
14186 recog_for_combine. In that case, recog_for_combine created the
14187 necessary REG_UNUSED notes. Trying to keep any original
14188 REG_UNUSED notes from these insns can cause incorrect output
14189 if it is for the same register as the original i3 dest.
14190 In that case, we will notice that the register is set in i3,
14191 and then add a REG_UNUSED note for the destination of i3, which
14192 is wrong. However, it is possible to have REG_UNUSED notes from
14193 i2 or i1 for register which were both used and clobbered, so
14194 we keep notes from i2 or i1 if they will turn into REG_DEAD
14195 notes. */
14197 /* If this register is set or clobbered in I3, put the note there
14198 unless there is one already. */
14200 {
14208 }
14209 /* Otherwise, if this register is used by I3, then this register
14210 now dies here, so we must put a REG_DEAD note here unless there
14211 is one already. */
14217 {
14220 }
14226 /* These notes say something about results of an insn. We can
14227 only support them if they used to be on I3 in which case they
14228 remain on I3. Otherwise they are ignored.
14230 If the note refers to an expression that is not a constant, we
14231 must also ignore the note since we cannot tell whether the
14232 equivalence is still true. It might be possible to do
14233 slightly better than this (we only have a problem if I2DEST
14234 or I1DEST is present in the expression), but it doesn't
14235 seem worth the trouble. */
14243 /* These notes say something about how a register is used. They must
14244 be present on any use of the register in I2 or I3. */
14249 {
14252 else
14254 }
14259 /* This can show up in several ways -- either directly in the
14260 pattern, or hidden off in the constant pool with (or without?)
14261 a REG_EQUAL note. */
14262 /* ??? Ignore the without-reg_equal-note problem for now. */
14274 {
14277 else
14279 }
14281 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14282 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14283 there. */
14288 {
14295 }
14301 {
14309 }
14313 /* This note says something about the value of a register prior
14314 to the execution of an insn. It is too much trouble to see
14315 if the note is still correct in all situations. It is better
14316 to simply delete it. */
14320 /* If we replaced the right hand side of FROM_INSN with a
14321 REG_EQUAL note, the original use of the dying register
14322 will not have been combined into I3 and I2. In such cases,
14323 FROM_INSN is guaranteed to be the first of the combined
14324 instructions, so we simply need to search back before
14325 FROM_INSN for the previous use or set of this register,
14326 then alter the notes there appropriately.
14328 If the register is used as an input in I3, it dies there.
14329 Similarly for I2, if it is nonzero and adjacent to I3.
14331 If the register is not used as an input in either I3 or I2
14332 and it is not one of the registers we were supposed to eliminate,
14333 there are two possibilities. We might have a non-adjacent I2
14334 or we might have somehow eliminated an additional register
14335 from a computation. For example, we might have had A & B where
14336 we discover that B will always be zero. In this case we will
14337 eliminate the reference to A.
14339 In both cases, we must search to see if we can find a previous
14340 use of A and put the death note there. */
14346 else
14347 {
14358 && !(i2mod
14360 i2mod_old_rhs)))
14365 /* If the new I2 sets the same register that is marked dead
14366 in the note, we do not know where to put the note.
14367 Give up. */
14370 }
14373 {
14377 {
14379 {
14383 }
14385 /* If the register is being set at TEM_INSN, see if that is all
14386 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14387 into a REG_UNUSED note instead. Don't delete sets to
14388 global register vars. */
14392 {
14403 ;
14405 /* Verify that it was the set, and not a clobber that
14406 modified the register.
14408 CC0 targets must be careful to maintain setter/user
14409 pairs. If we cannot delete the setter due to side
14410 effects, mark the user with an UNUSED note instead
14411 of deleting it. */
14415 && (!HAVE_cc0
14419 {
14420 /* Move the notes and links of TEM_INSN elsewhere.
14421 This might delete other dead insns recursively.
14422 First set the pattern to something that won't use
14423 any register. */
14442 /* Delete the setter too. */
14444 {
14457 }
14458 }
14459 else
14460 {
14463 /* If there isn't already a REG_UNUSED note, put one
14464 here. Do not place a REG_DEAD note, even if
14465 the register is also used here; that would not
14466 match the algorithm used in lifetime analysis
14467 and can cause the consistency check in the
14468 scheduler to fail. */
14473 }
14474 }
14478 {
14481 /* If we are doing a 3->2 combination, and we have a
14482 register which formerly died in i3 and was not used
14483 by i2, which now no longer dies in i3 and is used in
14484 i2 but does not die in i2, and place is between i2
14485 and i3, then we may need to move a link from place to
14486 i2. */
14488 && from_insn
14491 {
14495 }
14497 }
14501 }
14503 }
14505 /* If the register is set or already dead at PLACE, we needn't do
14506 anything with this note if it is still a REG_DEAD note.
14507 We check here if it is set at all, not if is it totally replaced,
14508 which is what `dead_or_set_p' checks, so also check for it being
14509 set partially. */
14512 {
14518 {
14519 /* Unless the register previously died in PLACE, clear
14520 last_death. [I no longer understand why this is
14521 being done.] */
14525 }
14526 else
14529 /* If this is a death note for a hard reg that is occupying
14530 multiple registers, ensure that we are still using all
14531 parts of the object. If we find a piece of the object
14532 that is unused, we must arrange for an appropriate REG_DEAD
14533 note to be added for it. However, we can't just emit a USE
14534 and tag the note to it, since the register might actually
14535 be dead; so we recourse, and the recursive call then finds
14536 the previous insn that used this register. */
14539 {
14548 {
14551 }
14554 {
14555 /* Put only REG_DEAD notes for pieces that are
14556 not already dead or set. */
14560 {
14567 {
14569 NULL_RTX);
14573 NULL_RTX);
14574 }
14579 {
14581 {
14585 }
14589 {
14592 }
14593 }
14594 }
14597 }
14598 }
14599 }
14603 /* Any other notes should not be present at this point in the
14604 compilation. */
14606 }
14609 {
14612 }
14616 }
14617 }
14618 \f
14619 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14620 I3, I2, and I1 to new locations. This is also called to add a link
14621 pointing at I3 when I3's destination is changed. */
14623 static void
14625 {
14629 {
14636 /* If the insn that this link points to is a NOTE, ignore it. */
14645 {
14648 {
14664 }
14667 }
14668 else
14678 /* A LOG_LINK is defined as being placed on the first insn that uses
14679 a register and points to the insn that sets the register. Start
14680 searching at the next insn after the target of the link and stop
14681 when we reach a set of the register or the end of the basic block.
14683 Note that this correctly handles the link that used to point from
14684 I3 to I2. Also note that not much searching is typically done here
14685 since most links don't point very far away. */
14694 {
14698 }
14701 {
14704 }
14708 /* If we found a place to put the link, place it there unless there
14709 is already a link to the same insn as LINK at that point. */
14712 {
14720 {
14724 /* Set added_links_insn to the earliest insn we added a
14725 link to. */
14729 }
14730 }
14731 }
14732 }
14733 \f
14734 /* Check for any register or memory mentioned in EQUIV that is not
14735 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14736 of EXPR where some registers may have been replaced by constants. */
14738 static bool
14740 {
14743 {
14748 }
14750 }
14751 \f
14752 DEBUG_FUNCTION void
14754 {
14755 fprintf
14757 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14759 }
14761 void
14763 {
14764 fprintf
14766 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14768 }
14769 \f
14770 /* Try combining insns through substitution. */
14771 static unsigned int
14773 {
14783 rebuild_jump_labels_after_combine
14786 /* Combining insns may have turned an indirect jump into a
14787 direct jump. Rebuild the JUMP_LABEL fields of jumping
14788 instructions. */
14790 {
14797 }
14801 }
14806 {
14816 };
14819 {
14823 {}
14825 /* opt_pass methods: */
14828 {
14830 }
14836 rtl_opt_pass *
14838 {
14840 }