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2009-07-17 Richard Guenther <rguenther@suse.de>
[official-gcc.git] / gcc / config / sh / sh.h
blobd9a4c5f25cc6ec01bd6c7dd86ce03b260d1f471d
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #ifndef GCC_SH_H
24 #define GCC_SH_H
25
26 #include "config/vxworks-dummy.h"
27
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
30
31 #ifndef TARGET_FMOVD
32 #define TARGET_FMOVD 0
33 #define MASK_FMOVD 0
34 #endif
35
36 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
37 include it here, because bconfig.h is also included by gencodes.c . */
38 /* ??? No longer true. */
39 extern int code_for_indirect_jump_scratch;
40
41 #define TARGET_CPU_CPP_BUILTINS() \
42 do { \
43 builtin_define ("__sh__"); \
44 builtin_assert ("cpu=sh"); \
45 builtin_assert ("machine=sh"); \
46 switch ((int) sh_cpu) \
47 { \
48 case PROCESSOR_SH1: \
49 builtin_define ("__sh1__"); \
50 break; \
51 case PROCESSOR_SH2: \
52 builtin_define ("__sh2__"); \
53 break; \
54 case PROCESSOR_SH2E: \
55 builtin_define ("__SH2E__"); \
56 break; \
57 case PROCESSOR_SH2A: \
58 builtin_define ("__SH2A__"); \
59 builtin_define (TARGET_SH2A_DOUBLE \
60 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
61 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
62 : "__SH2A_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3: \
65 builtin_define ("__sh3__"); \
66 builtin_define ("__SH3__"); \
67 if (TARGET_HARD_SH4) \
68 builtin_define ("__SH4_NOFPU__"); \
69 break; \
70 case PROCESSOR_SH3E: \
71 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
72 break; \
73 case PROCESSOR_SH4: \
74 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
75 break; \
76 case PROCESSOR_SH4A: \
77 builtin_define ("__SH4A__"); \
78 builtin_define (TARGET_SH4 \
79 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
80 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
81 : "__SH4_NOFPU__"); \
82 break; \
83 case PROCESSOR_SH5: \
84 { \
85 builtin_define_with_value ("__SH5__", \
86 TARGET_SHMEDIA64 ? "64" : "32", 0); \
87 builtin_define_with_value ("__SHMEDIA__", \
88 TARGET_SHMEDIA ? "1" : "0", 0); \
89 if (! TARGET_FPU_DOUBLE) \
90 builtin_define ("__SH4_NOFPU__"); \
91 } \
92 } \
93 if (TARGET_FPU_ANY) \
94 builtin_define ("__SH_FPU_ANY__"); \
95 if (TARGET_FPU_DOUBLE) \
96 builtin_define ("__SH_FPU_DOUBLE__"); \
97 if (TARGET_HITACHI) \
98 builtin_define ("__HITACHI__"); \
99 if (TARGET_FMOVD) \
100 builtin_define ("__FMOVD_ENABLED__"); \
101 builtin_define (TARGET_LITTLE_ENDIAN \
102 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
103 } while (0)
104
105 /* We can not debug without a frame pointer. */
106 /* #define CAN_DEBUG_WITHOUT_FP */
107
108 #define CONDITIONAL_REGISTER_USAGE do \
109 { \
110 int regno; \
111 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
112 if (! VALID_REGISTER_P (regno)) \
113 fixed_regs[regno] = call_used_regs[regno] = 1; \
114 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
115 if (TARGET_SH5) \
116 { \
117 call_used_regs[FIRST_GENERAL_REG + 8] \
118 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
119 call_really_used_regs[FIRST_GENERAL_REG + 8] \
120 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
121 } \
122 if (TARGET_SHMEDIA) \
123 { \
124 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
125 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
126 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
127 } \
128 if (flag_pic) \
129 { \
130 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
131 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
132 } \
133 /* Renesas saves and restores mac registers on call. */ \
134 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
135 { \
136 call_really_used_regs[MACH_REG] = 0; \
137 call_really_used_regs[MACL_REG] = 0; \
138 } \
139 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
140 regno <= LAST_FP_REG; regno += 2) \
141 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
142 if (TARGET_SHMEDIA) \
143 { \
144 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
145 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
146 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
147 } \
148 else \
149 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
150 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
151 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
152 } while (0)
153 \f
154 /* Nonzero if this is an ELF target - compile time only */
155 #define TARGET_ELF 0
156
157 /* Nonzero if we should generate code using type 2E insns. */
158 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
159
160 /* Nonzero if we should generate code using type 2A insns. */
161 #define TARGET_SH2A TARGET_HARD_SH2A
162 /* Nonzero if we should generate code using type 2A SF insns. */
163 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
164 /* Nonzero if we should generate code using type 2A DF insns. */
165 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
166
167 /* Nonzero if we should generate code using type 3E insns. */
168 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
169
170 /* Nonzero if the cache line size is 32. */
171 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
172
173 /* Nonzero if we schedule for a superscalar implementation. */
174 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
175
176 /* Nonzero if the target has separate instruction and data caches. */
177 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
178
179 /* Nonzero if a double-precision FPU is available. */
180 #define TARGET_FPU_DOUBLE \
181 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
182
183 /* Nonzero if an FPU is available. */
184 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
185
186 /* Nonzero if we should generate code using type 4 insns. */
187 #undef TARGET_SH4
188 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
189
190 /* Nonzero if we're generating code for the common subset of
191 instructions present on both SH4a and SH4al-dsp. */
192 #define TARGET_SH4A_ARCH TARGET_SH4A
193
194 /* Nonzero if we're generating code for SH4a, unless the use of the
195 FPU is disabled (which makes it compatible with SH4al-dsp). */
196 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
197
198 /* Nonzero if we should generate code using the SHcompact instruction
199 set and 32-bit ABI. */
200 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
201
202 /* Nonzero if we should generate code using the SHmedia instruction
203 set and ABI. */
204 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
205
206 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
207 ABI. */
208 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
209
210 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
211 ABI. */
212 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
213
214 /* Nonzero if we should generate code using SHmedia FPU instructions. */
215 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
216
217 /* This is not used by the SH2E calling convention */
218 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
219 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
220 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
221
222 #ifndef TARGET_CPU_DEFAULT
223 #define TARGET_CPU_DEFAULT SELECT_SH1
224 #define SUPPORT_SH1 1
225 #define SUPPORT_SH2E 1
226 #define SUPPORT_SH4 1
227 #define SUPPORT_SH4_SINGLE 1
228 #define SUPPORT_SH2A 1
229 #define SUPPORT_SH2A_SINGLE 1
230 #endif
231
232 #define TARGET_DIVIDE_INV \
233 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
234 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
235 || sh_div_strategy == SH_DIV_INV_CALL \
236 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
237 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
238 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
239 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
240 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
241 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
242 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
243 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
244 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
245 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
246 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
247 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
248
249 #define SELECT_SH1 (MASK_SH1)
250 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
251 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
252 | MASK_FPU_SINGLE)
253 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
254 | MASK_HARD_SH2A_DOUBLE \
255 | MASK_SH2 | MASK_SH1)
256 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
257 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
258 | MASK_SH1 | MASK_FPU_SINGLE)
259 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
260 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
261 | MASK_SH2 | MASK_SH1)
262 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
263 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
264 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
265 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
266 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
267 | SELECT_SH3)
268 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
269 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
270 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
271 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
272 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
273 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
274 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
275 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
276 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
277 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
278 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
279
280 #if SUPPORT_SH1
281 #define SUPPORT_SH2 1
282 #endif
283 #if SUPPORT_SH2
284 #define SUPPORT_SH3 1
285 #define SUPPORT_SH2A_NOFPU 1
286 #endif
287 #if SUPPORT_SH3
288 #define SUPPORT_SH4_NOFPU 1
289 #endif
290 #if SUPPORT_SH4_NOFPU
291 #define SUPPORT_SH4A_NOFPU 1
292 #define SUPPORT_SH4AL 1
293 #endif
294
295 #if SUPPORT_SH2E
296 #define SUPPORT_SH3E 1
297 #define SUPPORT_SH2A_SINGLE_ONLY 1
298 #endif
299 #if SUPPORT_SH3E
300 #define SUPPORT_SH4_SINGLE_ONLY 1
301 #endif
302 #if SUPPORT_SH4_SINGLE_ONLY
303 #define SUPPORT_SH4A_SINGLE_ONLY 1
304 #endif
305
306 #if SUPPORT_SH4
307 #define SUPPORT_SH4A 1
308 #endif
309
310 #if SUPPORT_SH4_SINGLE
311 #define SUPPORT_SH4A_SINGLE 1
312 #endif
313
314 #if SUPPORT_SH5_COMPAT
315 #define SUPPORT_SH5_32MEDIA 1
316 #endif
317
318 #if SUPPORT_SH5_COMPACT_NOFPU
319 #define SUPPORT_SH5_32MEDIA_NOFPU 1
320 #endif
321
322 #define SUPPORT_ANY_SH5_32MEDIA \
323 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
324 #define SUPPORT_ANY_SH5_64MEDIA \
325 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
326 #define SUPPORT_ANY_SH5 \
327 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
328
329 /* Reset all target-selection flags. */
330 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
331 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
332 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
333
334 /* This defaults us to big-endian. */
335 #ifndef TARGET_ENDIAN_DEFAULT
336 #define TARGET_ENDIAN_DEFAULT 0
337 #endif
338
339 #ifndef TARGET_OPT_DEFAULT
340 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
341 #endif
342
343 #define TARGET_DEFAULT \
344 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
345
346 #ifndef SH_MULTILIB_CPU_DEFAULT
347 #define SH_MULTILIB_CPU_DEFAULT "m1"
348 #endif
349
350 #if TARGET_ENDIAN_DEFAULT
351 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
352 #else
353 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
354 #endif
355
356 #define CPP_SPEC " %(subtarget_cpp_spec) "
357
358 #ifndef SUBTARGET_CPP_SPEC
359 #define SUBTARGET_CPP_SPEC ""
360 #endif
361
362 #ifndef SUBTARGET_EXTRA_SPECS
363 #define SUBTARGET_EXTRA_SPECS
364 #endif
365
366 #define EXTRA_SPECS \
367 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
368 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
369 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
370 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
371 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
372 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
373 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
374 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
375 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
376 SUBTARGET_EXTRA_SPECS
377
378 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
379 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
380 #else
381 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
382 #endif
383
384 #define SH_ASM_SPEC \
385 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
386 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
387 %{m2a:--isa=sh2a} \
388 %{m2a-single:--isa=sh2a} \
389 %{m2a-single-only:--isa=sh2a} \
390 %{m2a-nofpu:--isa=sh2a-nofpu} \
391 %{m5-compact*:--isa=SHcompact} \
392 %{m5-32media*:--isa=SHmedia --abi=32} \
393 %{m5-64media*:--isa=SHmedia --abi=64} \
394 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
395
396 #define ASM_SPEC SH_ASM_SPEC
397
398 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
399 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
400 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
401 #else
402 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
403 #endif
404 #endif
405
406 #if STRICT_NOFPU == 1
407 /* Strict nofpu means that the compiler should tell the assembler
408 to reject FPU instructions. E.g. from ASM inserts. */
409 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
410 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
411 #else
412 /* If there were an -isa option for sh5-nofpu then it would also go here. */
413 #define SUBTARGET_ASM_ISA_SPEC \
414 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
415 #endif
416 #else /* ! STRICT_NOFPU */
417 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
418 #endif
419
420 #ifndef SUBTARGET_ASM_SPEC
421 #define SUBTARGET_ASM_SPEC ""
422 #endif
423
424 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
425 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
426 #else
427 #define LINK_EMUL_PREFIX "sh%{ml:l}"
428 #endif
429
430 #if TARGET_CPU_DEFAULT & MASK_SH5
431 #if TARGET_CPU_DEFAULT & MASK_SH_E
432 #define LINK_DEFAULT_CPU_EMUL "32"
433 #if TARGET_CPU_DEFAULT & MASK_SH1
434 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
435 #else
436 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
437 #endif /* MASK_SH1 */
438 #else /* !MASK_SH_E */
439 #define LINK_DEFAULT_CPU_EMUL "64"
440 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
441 #endif /* MASK_SH_E */
442 #define ASM_ISA_DEFAULT_SPEC \
443 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
444 #else /* !MASK_SH5 */
445 #define LINK_DEFAULT_CPU_EMUL ""
446 #define ASM_ISA_DEFAULT_SPEC ""
447 #endif /* MASK_SH5 */
448
449 #define SUBTARGET_LINK_EMUL_SUFFIX ""
450 #define SUBTARGET_LINK_SPEC ""
451
452 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
453 so that we can undo the damage without code replication. */
454 #define LINK_SPEC SH_LINK_SPEC
455
456 #define SH_LINK_SPEC "\
457 -m %(link_emul_prefix)\
458 %{m5-compact*|m5-32media*:32}\
459 %{m5-64media*:64}\
460 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
461 %(subtarget_link_emul_suffix) \
462 %{mrelax:-relax} %(subtarget_link_spec)"
463
464 #ifndef SH_DIV_STR_FOR_SIZE
465 #define SH_DIV_STR_FOR_SIZE "call"
466 #endif
467
468 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
469
470 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) sh_optimization_options (LEVEL, SIZE)
471
472 #define ASSEMBLER_DIALECT assembler_dialect
473
474 extern int assembler_dialect;
475
476 enum sh_divide_strategy_e {
477 /* SH5 strategies. */
478 SH_DIV_CALL,
479 SH_DIV_CALL2,
480 SH_DIV_FP, /* We could do this also for SH4. */
481 SH_DIV_INV,
482 SH_DIV_INV_MINLAT,
483 SH_DIV_INV20U,
484 SH_DIV_INV20L,
485 SH_DIV_INV_CALL,
486 SH_DIV_INV_CALL2,
487 SH_DIV_INV_FP,
488 /* SH1 .. SH4 strategies. Because of the small number of registers
489 available, the compiler uses knowledge of the actual set of registers
490 being clobbered by the different functions called. */
491 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
492 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
493 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
494 SH_DIV_INTRINSIC
495 };
496
497 extern enum sh_divide_strategy_e sh_div_strategy;
498
499 #ifndef SH_DIV_STRATEGY_DEFAULT
500 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
501 #endif
502
503 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
504
505 extern const char *sh_fixed_range_str;
506
507 #define OVERRIDE_OPTIONS sh_override_options ()
508
509 \f
510 /* Target machine storage layout. */
511
512 /* Define this if most significant bit is lowest numbered
513 in instructions that operate on numbered bit-fields. */
514
515 #define BITS_BIG_ENDIAN 0
516
517 /* Define this if most significant byte of a word is the lowest numbered. */
518 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
519
520 /* Define this if most significant word of a multiword number is the lowest
521 numbered. */
522 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
523
524 /* Define this to set the endianness to use in libgcc2.c, which can
525 not depend on target_flags. */
526 #if defined(__LITTLE_ENDIAN__)
527 #define LIBGCC2_WORDS_BIG_ENDIAN 0
528 #else
529 #define LIBGCC2_WORDS_BIG_ENDIAN 1
530 #endif
531
532 #define MAX_BITS_PER_WORD 64
533
534 /* Width in bits of an `int'. We want just 32-bits, even if words are
535 longer. */
536 #define INT_TYPE_SIZE 32
537
538 /* Width in bits of a `long'. */
539 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
540
541 /* Width in bits of a `long long'. */
542 #define LONG_LONG_TYPE_SIZE 64
543
544 /* Width in bits of a `long double'. */
545 #define LONG_DOUBLE_TYPE_SIZE 64
546
547 /* Width of a word, in units (bytes). */
548 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
549 #define MIN_UNITS_PER_WORD 4
550
551 /* Scaling factor for Dwarf data offsets for CFI information.
552 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
553 SHmedia; however, since we do partial register saves for the registers
554 visible to SHcompact, and for target registers for SHMEDIA32, we have
555 to allow saves that are only 4-byte aligned. */
556 #define DWARF_CIE_DATA_ALIGNMENT -4
557
558 /* Width in bits of a pointer.
559 See also the macro `Pmode' defined below. */
560 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
561
562 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
563 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
564
565 /* Boundary (in *bits*) on which stack pointer should be aligned. */
566 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
567
568 /* The log (base 2) of the cache line size, in bytes. Processors prior to
569 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
570 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
571 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
572
573 /* ABI given & required minimum allocation boundary (in *bits*) for the
574 code of a function. */
575 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
576
577 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
578 the vbit must go into the delta field of
579 pointers-to-member-functions. */
580 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
581 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
582
583 /* Alignment of field after `int : 0' in a structure. */
584 #define EMPTY_FIELD_BOUNDARY 32
585
586 /* No data type wants to be aligned rounder than this. */
587 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
588
589 /* The best alignment to use in cases where we have a choice. */
590 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
591
592 /* Make strings word-aligned so strcpy from constants will be faster. */
593 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
594 ((TREE_CODE (EXP) == STRING_CST \
595 && (ALIGN) < FASTEST_ALIGNMENT) \
596 ? FASTEST_ALIGNMENT : (ALIGN))
597
598 /* get_mode_alignment assumes complex values are always held in multiple
599 registers, but that is not the case on the SH; CQImode and CHImode are
600 held in a single integer register. SH5 also holds CSImode and SCmode
601 values in integer registers. This is relevant for argument passing on
602 SHcompact as we use a stack temp in order to pass CSImode by reference. */
603 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
604 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
605 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
606 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
607 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
608
609 /* Make arrays of chars word-aligned for the same reasons. */
610 #define DATA_ALIGNMENT(TYPE, ALIGN) \
611 (TREE_CODE (TYPE) == ARRAY_TYPE \
612 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
613 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
614
615 /* Number of bits which any structure or union's size must be a
616 multiple of. Each structure or union's size is rounded up to a
617 multiple of this. */
618 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
619
620 /* Set this nonzero if move instructions will actually fail to work
621 when given unaligned data. */
622 #define STRICT_ALIGNMENT 1
623
624 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
625 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
626 barrier_align (LABEL_AFTER_BARRIER)
627
628 #define LOOP_ALIGN(A_LABEL) \
629 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
630 ? 0 : sh_loop_align (A_LABEL))
631
632 #define LABEL_ALIGN(A_LABEL) \
633 ( \
634 (PREV_INSN (A_LABEL) \
635 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
636 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
637 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
638 /* explicit alignment insn in constant tables. */ \
639 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
640 : 0)
641
642 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
643 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
644
645 /* The base two logarithm of the known minimum alignment of an insn length. */
646 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
647 (NONJUMP_INSN_P (A_INSN) \
648 ? 1 << TARGET_SHMEDIA \
649 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
650 ? 1 << TARGET_SHMEDIA \
651 : CACHE_LOG)
652 \f
653 /* Standard register usage. */
654
655 /* Register allocation for the Renesas calling convention:
656
657 r0 arg return
658 r1..r3 scratch
659 r4..r7 args in
660 r8..r13 call saved
661 r14 frame pointer/call saved
662 r15 stack pointer
663 ap arg pointer (doesn't really exist, always eliminated)
664 pr subroutine return address
665 t t bit
666 mach multiply/accumulate result, high part
667 macl multiply/accumulate result, low part.
668 fpul fp/int communication register
669 rap return address pointer register
670 fr0 fp arg return
671 fr1..fr3 scratch floating point registers
672 fr4..fr11 fp args in
673 fr12..fr15 call saved floating point registers */
674
675 #define MAX_REGISTER_NAME_LENGTH 5
676 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
677
678 #define SH_REGISTER_NAMES_INITIALIZER \
679 { \
680 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
681 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
682 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
683 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
684 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
685 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
686 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
687 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
688 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
689 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
690 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
691 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
692 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
693 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
694 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
695 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
696 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
697 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
698 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
699 "rap", "sfp" \
700 }
701
702 #define REGNAMES_ARR_INDEX_1(index) \
703 (sh_register_names[index])
704 #define REGNAMES_ARR_INDEX_2(index) \
705 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
706 #define REGNAMES_ARR_INDEX_4(index) \
707 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
708 #define REGNAMES_ARR_INDEX_8(index) \
709 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
710 #define REGNAMES_ARR_INDEX_16(index) \
711 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
712 #define REGNAMES_ARR_INDEX_32(index) \
713 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
714 #define REGNAMES_ARR_INDEX_64(index) \
715 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
716
717 #define REGISTER_NAMES \
718 { \
719 REGNAMES_ARR_INDEX_64 (0), \
720 REGNAMES_ARR_INDEX_64 (64), \
721 REGNAMES_ARR_INDEX_8 (128), \
722 REGNAMES_ARR_INDEX_8 (136), \
723 REGNAMES_ARR_INDEX_8 (144), \
724 REGNAMES_ARR_INDEX_2 (152) \
725 }
726
727 #define ADDREGNAMES_SIZE 32
728 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
729 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
730 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
731
732 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
733 { \
734 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
735 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
736 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
737 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
738 }
739
740 #define ADDREGNAMES_REGNO(index) \
741 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
742 : (-1))
743
744 #define ADDREGNAMES_ARR_INDEX_1(index) \
745 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
746 #define ADDREGNAMES_ARR_INDEX_2(index) \
747 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
748 #define ADDREGNAMES_ARR_INDEX_4(index) \
749 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
750 #define ADDREGNAMES_ARR_INDEX_8(index) \
751 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
752 #define ADDREGNAMES_ARR_INDEX_16(index) \
753 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
754 #define ADDREGNAMES_ARR_INDEX_32(index) \
755 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
756
757 #define ADDITIONAL_REGISTER_NAMES \
758 { \
759 ADDREGNAMES_ARR_INDEX_32 (0) \
760 }
761
762 /* Number of actual hardware registers.
763 The hardware registers are assigned numbers for the compiler
764 from 0 to just below FIRST_PSEUDO_REGISTER.
765 All registers that the compiler knows about must be given numbers,
766 even those that are not normally considered general registers. */
767
768 /* There are many other relevant definitions in sh.md's md_constants. */
769
770 #define FIRST_GENERAL_REG R0_REG
771 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
772 #define FIRST_FP_REG DR0_REG
773 #define LAST_FP_REG (FIRST_FP_REG + \
774 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
775 #define FIRST_XD_REG XD0_REG
776 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
777 #define FIRST_TARGET_REG TR0_REG
778 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
779
780 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
781
782 #define FIRST_BANKED_REG R0_REG
783 #define LAST_BANKED_REG R7_REG
784
785 #define BANKED_REGISTER_P(REGNO) \
786 IN_RANGE ((REGNO), \
787 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
788 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
789
790 #define GENERAL_REGISTER_P(REGNO) \
791 IN_RANGE ((REGNO), \
792 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
793 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
794
795 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
796 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
797 || ((REGNO) == FRAME_POINTER_REGNUM))
798
799 #define FP_REGISTER_P(REGNO) \
800 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
801
802 #define XD_REGISTER_P(REGNO) \
803 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
804
805 #define FP_OR_XD_REGISTER_P(REGNO) \
806 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
807
808 #define FP_ANY_REGISTER_P(REGNO) \
809 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
810
811 #define SPECIAL_REGISTER_P(REGNO) \
812 ((REGNO) == GBR_REG || (REGNO) == T_REG \
813 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
814
815 #define TARGET_REGISTER_P(REGNO) \
816 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
817
818 #define SHMEDIA_REGISTER_P(REGNO) \
819 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
820 || TARGET_REGISTER_P (REGNO))
821
822 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
823 that should be fixed. */
824 #define VALID_REGISTER_P(REGNO) \
825 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
826 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
827 || (REGNO) == FRAME_POINTER_REGNUM \
828 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
829 || (TARGET_SH2E && (REGNO) == FPUL_REG))
830
831 /* The mode that should be generally used to store a register by
832 itself in the stack, or to load it back. */
833 #define REGISTER_NATURAL_MODE(REGNO) \
834 (FP_REGISTER_P (REGNO) ? SFmode \
835 : XD_REGISTER_P (REGNO) ? DFmode \
836 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
837 ? DImode \
838 : SImode)
839
840 #define FIRST_PSEUDO_REGISTER 154
841
842 /* Don't count soft frame pointer. */
843 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
844
845 /* 1 for registers that have pervasive standard uses
846 and are not available for the register allocator.
847
848 Mach register is fixed 'cause it's only 10 bits wide for SH1.
849 It is 32 bits wide for SH2. */
850
851 #define FIXED_REGISTERS \
852 { \
853 /* Regular registers. */ \
854 0, 0, 0, 0, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 1, \
856 /* r16 is reserved, r18 is the former pr. */ \
857 1, 0, 0, 0, 0, 0, 0, 0, \
858 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
859 /* r26 is a global variable data pointer; r27 is for constants. */ \
860 1, 1, 1, 1, 0, 0, 0, 0, \
861 0, 0, 0, 0, 0, 0, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, \
864 0, 0, 0, 0, 0, 0, 0, 1, \
865 /* FP registers. */ \
866 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, \
868 0, 0, 0, 0, 0, 0, 0, 0, \
869 0, 0, 0, 0, 0, 0, 0, 0, \
870 0, 0, 0, 0, 0, 0, 0, 0, \
871 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, \
873 0, 0, 0, 0, 0, 0, 0, 0, \
874 /* Branch target registers. */ \
875 0, 0, 0, 0, 0, 0, 0, 0, \
876 /* XD registers. */ \
877 0, 0, 0, 0, 0, 0, 0, 0, \
878 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
879 1, 1, 1, 1, 1, 1, 0, 1, \
880 /*"rap", "sfp" */ \
881 1, 1, \
882 }
883
884 /* 1 for registers not available across function calls.
885 These must include the FIXED_REGISTERS and also any
886 registers that can be used without being saved.
887 The latter must include the registers where values are returned
888 and the register where structure-value addresses are passed.
889 Aside from that, you can include as many other registers as you like. */
890
891 #define CALL_USED_REGISTERS \
892 { \
893 /* Regular registers. */ \
894 1, 1, 1, 1, 1, 1, 1, 1, \
895 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
896 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
897 across SH5 function calls. */ \
898 0, 0, 0, 0, 0, 0, 0, 1, \
899 1, 1, 1, 1, 1, 1, 1, 1, \
900 1, 1, 1, 1, 0, 0, 0, 0, \
901 0, 0, 0, 0, 1, 1, 1, 1, \
902 1, 1, 1, 1, 0, 0, 0, 0, \
903 0, 0, 0, 0, 0, 0, 0, 0, \
904 0, 0, 0, 0, 1, 1, 1, 1, \
905 /* FP registers. */ \
906 1, 1, 1, 1, 1, 1, 1, 1, \
907 1, 1, 1, 1, 0, 0, 0, 0, \
908 1, 1, 1, 1, 1, 1, 1, 1, \
909 1, 1, 1, 1, 1, 1, 1, 1, \
910 1, 1, 1, 1, 0, 0, 0, 0, \
911 0, 0, 0, 0, 0, 0, 0, 0, \
912 0, 0, 0, 0, 0, 0, 0, 0, \
913 0, 0, 0, 0, 0, 0, 0, 0, \
914 /* Branch target registers. */ \
915 1, 1, 1, 1, 1, 0, 0, 0, \
916 /* XD registers. */ \
917 1, 1, 1, 1, 1, 1, 0, 0, \
918 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
919 1, 1, 1, 1, 1, 1, 1, 1, \
920 /*"rap", "sfp" */ \
921 1, 1, \
922 }
923
924 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
925 fixed, like PIC_OFFSET_TABLE_REGNUM. */
926 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
927
928 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
929 across SHcompact function calls. We can't tell whether a called
930 function is SHmedia or SHcompact, so we assume it may be when
931 compiling SHmedia code with the 32-bit ABI, since that's the only
932 ABI that can be linked with SHcompact code. */
933 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
934 (TARGET_SHMEDIA32 \
935 && GET_MODE_SIZE (MODE) > 4 \
936 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
937 && (REGNO) <= FIRST_GENERAL_REG + 15) \
938 || TARGET_REGISTER_P (REGNO) \
939 || (REGNO) == PR_MEDIA_REG))
940
941 /* Return number of consecutive hard regs needed starting at reg REGNO
942 to hold something of mode MODE.
943 This is ordinarily the length in words of a value of mode MODE
944 but can be less for certain modes in special long registers.
945
946 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
947
948 #define HARD_REGNO_NREGS(REGNO, MODE) \
949 (XD_REGISTER_P (REGNO) \
950 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
951 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
952 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
953 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
954
955 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
956
957 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
958 sh_hard_regno_mode_ok ((REGNO), (MODE))
959
960 /* Value is 1 if it is a good idea to tie two pseudo registers
961 when one has mode MODE1 and one has mode MODE2.
962 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
963 for any hard reg, then this must be 0 for correct output.
964 That's the case for xd registers: we don't hold SFmode values in
965 them, so we can't tie an SFmode pseudos with one in another
966 floating-point mode. */
967
968 #define MODES_TIEABLE_P(MODE1, MODE2) \
969 ((MODE1) == (MODE2) \
970 || (TARGET_SHMEDIA \
971 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
972 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
973 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
974 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
975 && (GET_MODE_SIZE (MODE2) <= 4)) \
976 : ((MODE1) != SFmode && (MODE2) != SFmode))))
977
978 /* A C expression that is nonzero if hard register NEW_REG can be
979 considered for use as a rename register for OLD_REG register */
980
981 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
982 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
983
984 /* Specify the registers used for certain standard purposes.
985 The values of these macros are register numbers. */
986
987 /* Define this if the program counter is overloaded on a register. */
988 /* #define PC_REGNUM 15*/
989
990 /* Register to use for pushing function arguments. */
991 #define STACK_POINTER_REGNUM SP_REG
992
993 /* Base register for access to local variables of the function. */
994 #define HARD_FRAME_POINTER_REGNUM FP_REG
995
996 /* Base register for access to local variables of the function. */
997 #define FRAME_POINTER_REGNUM 153
998
999 /* Fake register that holds the address on the stack of the
1000 current function's return address. */
1001 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1002
1003 /* Register to hold the addressing base for position independent
1004 code access to data items. */
1005 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1006
1007 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1008
1009 /* Definitions for register eliminations.
1010
1011 We have three registers that can be eliminated on the SH. First, the
1012 frame pointer register can often be eliminated in favor of the stack
1013 pointer register. Secondly, the argument pointer register can always be
1014 eliminated; it is replaced with either the stack or frame pointer.
1015 Third, there is the return address pointer, which can also be replaced
1016 with either the stack or the frame pointer. */
1017
1018 /* This is an array of structures. Each structure initializes one pair
1019 of eliminable registers. The "from" register number is given first,
1020 followed by "to". Eliminations of the same "from" register are listed
1021 in order of preference. */
1022
1023 /* If you add any registers here that are not actually hard registers,
1024 and that have any alternative of elimination that doesn't always
1025 apply, you need to amend calc_live_regs to exclude it, because
1026 reload spills all eliminable registers where it sees an
1027 can_eliminate == 0 entry, thus making them 'live' .
1028 If you add any hard registers that can be eliminated in different
1029 ways, you have to patch reload to spill them only when all alternatives
1030 of elimination fail. */
1031
1032 #define ELIMINABLE_REGS \
1033 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1034 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1035 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1036 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1037 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1038 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1039 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1040
1041 /* Define the offset between two registers, one to be eliminated, and the other
1042 its replacement, at the start of a routine. */
1043
1044 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1045 OFFSET = initial_elimination_offset ((FROM), (TO))
1046
1047 /* Base register for access to arguments of the function. */
1048 #define ARG_POINTER_REGNUM AP_REG
1049
1050 /* Register in which the static-chain is passed to a function. */
1051 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1052
1053 /* Don't default to pcc-struct-return, because we have already specified
1054 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1055 target hook. */
1056
1057 #define DEFAULT_PCC_STRUCT_RETURN 0
1058
1059 #define SHMEDIA_REGS_STACK_ADJUST() \
1060 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1061 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1062 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1063 : 0)
1064
1065 \f
1066 /* Define the classes of registers for register constraints in the
1067 machine description. Also define ranges of constants.
1068
1069 One of the classes must always be named ALL_REGS and include all hard regs.
1070 If there is more than one class, another class must be named NO_REGS
1071 and contain no registers.
1072
1073 The name GENERAL_REGS must be the name of a class (or an alias for
1074 another name such as ALL_REGS). This is the class of registers
1075 that is allowed by "g" or "r" in a register constraint.
1076 Also, registers outside this class are allocated only when
1077 instructions express preferences for them.
1078
1079 The classes must be numbered in nondecreasing order; that is,
1080 a larger-numbered class must never be contained completely
1081 in a smaller-numbered class.
1082
1083 For any two classes, it is very desirable that there be another
1084 class that represents their union. */
1085
1086 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1087 be used as the destination of some of the arithmetic ops. There are
1088 also some special purpose registers; the T bit register, the
1089 Procedure Return Register and the Multiply Accumulate Registers. */
1090 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1091 reg_class_subunion. We don't want to have an actual union class
1092 of these, because it would only be used when both classes are calculated
1093 to give the same cost, but there is only one FPUL register.
1094 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1095 applying to the actual instruction alternative considered. E.g., the
1096 y/r alternative of movsi_ie is considered to have no more cost that
1097 the r/r alternative, which is patently untrue. */
1098
1099 enum reg_class
1100 {
1101 NO_REGS,
1102 R0_REGS,
1103 PR_REGS,
1104 T_REGS,
1105 MAC_REGS,
1106 FPUL_REGS,
1107 SIBCALL_REGS,
1108 GENERAL_REGS,
1109 FP0_REGS,
1110 FP_REGS,
1111 DF_HI_REGS,
1112 DF_REGS,
1113 FPSCR_REGS,
1114 GENERAL_FP_REGS,
1115 GENERAL_DF_REGS,
1116 TARGET_REGS,
1117 ALL_REGS,
1118 LIM_REG_CLASSES
1119 };
1120
1121 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1122
1123 /* Give names of register classes as strings for dump file. */
1124 #define REG_CLASS_NAMES \
1125 { \
1126 "NO_REGS", \
1127 "R0_REGS", \
1128 "PR_REGS", \
1129 "T_REGS", \
1130 "MAC_REGS", \
1131 "FPUL_REGS", \
1132 "SIBCALL_REGS", \
1133 "GENERAL_REGS", \
1134 "FP0_REGS", \
1135 "FP_REGS", \
1136 "DF_HI_REGS", \
1137 "DF_REGS", \
1138 "FPSCR_REGS", \
1139 "GENERAL_FP_REGS", \
1140 "GENERAL_DF_REGS", \
1141 "TARGET_REGS", \
1142 "ALL_REGS", \
1143 }
1144
1145 /* Define which registers fit in which classes.
1146 This is an initializer for a vector of HARD_REG_SET
1147 of length N_REG_CLASSES. */
1148
1149 #define REG_CLASS_CONTENTS \
1150 { \
1151 /* NO_REGS: */ \
1152 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1153 /* R0_REGS: */ \
1154 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1155 /* PR_REGS: */ \
1156 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1157 /* T_REGS: */ \
1158 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1159 /* MAC_REGS: */ \
1160 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1161 /* FPUL_REGS: */ \
1162 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1163 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1164 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1165 /* GENERAL_REGS: */ \
1166 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1167 /* FP0_REGS: */ \
1168 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1169 /* FP_REGS: */ \
1170 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1171 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1172 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1173 /* DF_REGS: */ \
1174 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1175 /* FPSCR_REGS: */ \
1176 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1177 /* GENERAL_FP_REGS: */ \
1178 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1179 /* GENERAL_DF_REGS: */ \
1180 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1181 /* TARGET_REGS: */ \
1182 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1183 /* ALL_REGS: */ \
1184 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1185 }
1186
1187 /* The same information, inverted:
1188 Return the class number of the smallest class containing
1189 reg number REGNO. This could be a conditional expression
1190 or could index an array. */
1191
1192 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1193 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1194
1195 /* The following macro defines cover classes for Integrated Register
1196 Allocator. Cover classes is a set of non-intersected register
1197 classes covering all hard registers used for register allocation
1198 purpose. Any move between two registers of a cover class should be
1199 cheaper than load or store of the registers. The macro value is
1200 array of register classes with LIM_REG_CLASSES used as the end
1201 marker. */
1202
1203 #define IRA_COVER_CLASSES \
1204 { \
1205 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1206 FPUL_REGS, LIM_REG_CLASSES \
1207 }
1208
1209 /* When defined, the compiler allows registers explicitly used in the
1210 rtl to be used as spill registers but prevents the compiler from
1211 extending the lifetime of these registers. */
1212
1213 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1214
1215 /* The order in which register should be allocated. */
1216 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1217 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1218 spilled or used otherwise, we better have the FP_REGS allocated first. */
1219 #define REG_ALLOC_ORDER \
1220 {/* Caller-saved FPRs */ \
1221 65, 66, 67, 68, 69, 70, 71, 64, \
1222 72, 73, 74, 75, 80, 81, 82, 83, \
1223 84, 85, 86, 87, 88, 89, 90, 91, \
1224 92, 93, 94, 95, 96, 97, 98, 99, \
1225 /* Callee-saved FPRs */ \
1226 76, 77, 78, 79,100,101,102,103, \
1227 104,105,106,107,108,109,110,111, \
1228 112,113,114,115,116,117,118,119, \
1229 120,121,122,123,124,125,126,127, \
1230 136,137,138,139,140,141,142,143, \
1231 /* FPSCR */ 151, \
1232 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1233 1, 2, 3, 7, 6, 5, 4, 0, \
1234 8, 9, 17, 19, 20, 21, 22, 23, \
1235 36, 37, 38, 39, 40, 41, 42, 43, \
1236 60, 61, 62, \
1237 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1238 10, 11, 12, 13, 14, 18, \
1239 /* SH5 callee-saved GPRs */ \
1240 28, 29, 30, 31, 32, 33, 34, 35, \
1241 44, 45, 46, 47, 48, 49, 50, 51, \
1242 52, 53, 54, 55, 56, 57, 58, 59, \
1243 /* FPUL */ 150, \
1244 /* SH5 branch target registers */ \
1245 128,129,130,131,132,133,134,135, \
1246 /* Fixed registers */ \
1247 15, 16, 24, 25, 26, 27, 63,144, \
1248 145,146,147,148,149,152,153 }
1249
1250 /* The class value for index registers, and the one for base regs. */
1251 #define INDEX_REG_CLASS \
1252 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1253 #define BASE_REG_CLASS GENERAL_REGS
1254 \f
1255 /* Defines for sh.md and constraints.md. */
1256
1257 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1258 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1259 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1260 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1261 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1262 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1263 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1264 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1265
1266 #define CONST_OK_FOR_J16(VALUE) \
1267 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1268 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1269
1270 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1271 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1272
1273 /* Given an rtx X being reloaded into a reg required to be
1274 in class CLASS, return the class of reg to actually use.
1275 In general this is just CLASS; but on some machines
1276 in some cases it is preferable to use a more restrictive class. */
1277
1278 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1279 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1280 && (GET_CODE (X) == CONST_DOUBLE \
1281 || GET_CODE (X) == SYMBOL_REF \
1282 || PIC_ADDR_P (X)) \
1283 ? GENERAL_REGS \
1284 : (CLASS)) \
1285
1286 #if 0
1287 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1288 ((((REGCLASS_HAS_FP_REG (CLASS) \
1289 && (REG_P (X) \
1290 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1291 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1292 && TARGET_FMOVD)))) \
1293 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1294 && REG_P (X) \
1295 && FP_REGISTER_P (REGNO (X)))) \
1296 && ! TARGET_SHMEDIA \
1297 && ((MODE) == SFmode || (MODE) == SImode)) \
1298 ? FPUL_REGS \
1299 : (((CLASS) == FPUL_REGS \
1300 || (REGCLASS_HAS_FP_REG (CLASS) \
1301 && ! TARGET_SHMEDIA && MODE == SImode)) \
1302 && (MEM_P (X) \
1303 || (REG_P (X) \
1304 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1305 || REGNO (X) == T_REG \
1306 || system_reg_operand (X, VOIDmode))))) \
1307 ? GENERAL_REGS \
1308 : (((CLASS) == TARGET_REGS \
1309 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1310 && !satisfies_constraint_Csy (X) \
1311 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1312 ? GENERAL_REGS \
1313 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1314 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1315 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1316 ? GENERAL_REGS \
1317 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1318 && TARGET_REGISTER_P (REGNO (X))) \
1319 ? GENERAL_REGS : (ELSE))
1320
1321 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1322 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1323
1324 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1325 ((REGCLASS_HAS_FP_REG (CLASS) \
1326 && ! TARGET_SHMEDIA \
1327 && immediate_operand ((X), (MODE)) \
1328 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1329 && (MODE) == SFmode && fldi_ok ())) \
1330 ? R0_REGS \
1331 : ((CLASS) == FPUL_REGS \
1332 && ((REG_P (X) \
1333 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1334 || REGNO (X) == T_REG)) \
1335 || GET_CODE (X) == PLUS)) \
1336 ? GENERAL_REGS \
1337 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1338 ? (satisfies_constraint_I08 (X) \
1339 ? GENERAL_REGS \
1340 : R0_REGS) \
1341 : ((CLASS) == FPSCR_REGS \
1342 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1343 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1344 ? GENERAL_REGS \
1345 : (REGCLASS_HAS_FP_REG (CLASS) \
1346 && TARGET_SHMEDIA \
1347 && immediate_operand ((X), (MODE)) \
1348 && (X) != CONST0_RTX (GET_MODE (X)) \
1349 && GET_MODE (X) != V4SFmode) \
1350 ? GENERAL_REGS \
1351 : (((MODE) == QImode || (MODE) == HImode) \
1352 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1353 ? GENERAL_REGS \
1354 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1355 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1356 ? TARGET_REGS \
1357 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1358 #endif
1359
1360 /* Return the maximum number of consecutive registers
1361 needed to represent mode MODE in a register of class CLASS.
1362
1363 If TARGET_SHMEDIA, we need two FP registers per word.
1364 Otherwise we will need at most one register per word. */
1365 #define CLASS_MAX_NREGS(CLASS, MODE) \
1366 (TARGET_SHMEDIA \
1367 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1368 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1369 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1370
1371 /* If defined, gives a class of registers that cannot be used as the
1372 operand of a SUBREG that changes the mode of the object illegally. */
1373 /* ??? We need to renumber the internal numbers for the frnn registers
1374 when in little endian in order to allow mode size changes. */
1375
1376 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1377 sh_cannot_change_mode_class (FROM, TO, CLASS)
1378 \f
1379 /* Stack layout; function entry, exit and calling. */
1380
1381 /* Define the number of registers that can hold parameters.
1382 These macros are used only in other macro definitions below. */
1383
1384 #define NPARM_REGS(MODE) \
1385 (TARGET_FPU_ANY && (MODE) == SFmode \
1386 ? (TARGET_SH5 ? 12 : 8) \
1387 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1388 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1389 ? (TARGET_SH5 ? 12 : 8) \
1390 : (TARGET_SH5 ? 8 : 4))
1391
1392 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1393 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1394
1395 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1396 #define FIRST_FP_RET_REG FIRST_FP_REG
1397
1398 /* Define this if pushing a word on the stack
1399 makes the stack pointer a smaller address. */
1400 #define STACK_GROWS_DOWNWARD
1401
1402 /* Define this macro to nonzero if the addresses of local variable slots
1403 are at negative offsets from the frame pointer. */
1404 #define FRAME_GROWS_DOWNWARD 1
1405
1406 /* Offset from the frame pointer to the first local variable slot to
1407 be allocated. */
1408 #define STARTING_FRAME_OFFSET 0
1409
1410 /* If we generate an insn to push BYTES bytes,
1411 this says how many the stack pointer really advances by. */
1412 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1413 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1414 do correct alignment. */
1415 #if 0
1416 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1417 #endif
1418
1419 /* Offset of first parameter from the argument pointer register value. */
1420 #define FIRST_PARM_OFFSET(FNDECL) 0
1421
1422 /* Value is the number of byte of arguments automatically
1423 popped when returning from a subroutine call.
1424 FUNDECL is the declaration node of the function (as a tree),
1425 FUNTYPE is the data type of the function (as a tree),
1426 or for a library call it is an identifier node for the subroutine name.
1427 SIZE is the number of bytes of arguments passed on the stack.
1428
1429 On the SH, the caller does not pop any of its arguments that were passed
1430 on the stack. */
1431 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1432
1433 /* Value is the number of bytes of arguments automatically popped when
1434 calling a subroutine.
1435 CUM is the accumulated argument list.
1436
1437 On SHcompact, the call trampoline pops arguments off the stack. */
1438 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1439
1440 /* Some subroutine macros specific to this machine. */
1441
1442 #define BASE_RETURN_VALUE_REG(MODE) \
1443 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1444 ? FIRST_FP_RET_REG \
1445 : TARGET_FPU_ANY && (MODE) == SCmode \
1446 ? FIRST_FP_RET_REG \
1447 : (TARGET_FPU_DOUBLE \
1448 && ((MODE) == DFmode || (MODE) == SFmode \
1449 || (MODE) == DCmode || (MODE) == SCmode )) \
1450 ? FIRST_FP_RET_REG \
1451 : FIRST_RET_REG)
1452
1453 #define BASE_ARG_REG(MODE) \
1454 ((TARGET_SH2E && ((MODE) == SFmode)) \
1455 ? FIRST_FP_PARM_REG \
1456 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1457 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1458 ? FIRST_FP_PARM_REG \
1459 : FIRST_PARM_REG)
1460
1461 /* Define how to find the value returned by a function.
1462 VALTYPE is the data type of the value (as a tree).
1463 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1464 otherwise, FUNC is 0.
1465 For the SH, this is like LIBCALL_VALUE, except that we must change the
1466 mode like PROMOTE_MODE does.
1467 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1468 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1469
1470 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1471 gen_rtx_REG ( \
1472 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1473 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1474 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1475 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1476 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1477 || TREE_CODE (VALTYPE) == REAL_TYPE \
1478 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1479 && sh_promote_prototypes (FUNC) \
1480 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1481 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1482
1483 /* Define how to find the value returned by a library function
1484 assuming the value has mode MODE. */
1485 #define LIBCALL_VALUE(MODE) \
1486 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1487
1488 /* 1 if N is a possible register number for a function value. */
1489 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1490 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1491 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1492
1493 /* 1 if N is a possible register number for function argument passing. */
1494 /* ??? There are some callers that pass REGNO as int, and others that pass
1495 it as unsigned. We get warnings unless we do casts everywhere. */
1496 #define FUNCTION_ARG_REGNO_P(REGNO) \
1497 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1498 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1499 || (TARGET_FPU_ANY \
1500 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1501 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1502 + NPARM_REGS (SFmode))))
1503 \f
1504 /* Define a data type for recording info about an argument list
1505 during the scan of that argument list. This data type should
1506 hold all necessary information about the function itself
1507 and about the args processed so far, enough to enable macros
1508 such as FUNCTION_ARG to determine where the next arg should go.
1509
1510 On SH, this is a single integer, which is a number of words
1511 of arguments scanned so far (including the invisible argument,
1512 if any, which holds the structure-value-address).
1513 Thus NARGREGS or more means all following args should go on the stack. */
1514
1515 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1516 struct sh_args {
1517 int arg_count[2];
1518 int force_mem;
1519 /* Nonzero if a prototype is available for the function. */
1520 int prototype_p;
1521 /* The number of an odd floating-point register, that should be used
1522 for the next argument of type float. */
1523 int free_single_fp_reg;
1524 /* Whether we're processing an outgoing function call. */
1525 int outgoing;
1526 /* The number of general-purpose registers that should have been
1527 used to pass partial arguments, that are passed totally on the
1528 stack. On SHcompact, a call trampoline will pop them off the
1529 stack before calling the actual function, and, if the called
1530 function is implemented in SHcompact mode, the incoming arguments
1531 decoder will push such arguments back onto the stack. For
1532 incoming arguments, STACK_REGS also takes into account other
1533 arguments passed by reference, that the decoder will also push
1534 onto the stack. */
1535 int stack_regs;
1536 /* The number of general-purpose registers that should have been
1537 used to pass arguments, if the arguments didn't have to be passed
1538 by reference. */
1539 int byref_regs;
1540 /* Set as by shcompact_byref if the current argument is to be passed
1541 by reference. */
1542 int byref;
1543
1544 /* call_cookie is a bitmask used by call expanders, as well as
1545 function prologue and epilogues, to allow SHcompact to comply
1546 with the SH5 32-bit ABI, that requires 64-bit registers to be
1547 used even though only the lower 32-bit half is visible in
1548 SHcompact mode. The strategy is to call SHmedia trampolines.
1549
1550 The alternatives for each of the argument-passing registers are
1551 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1552 contents from the address in it; (d) add 8 to it, storing the
1553 result in the next register, then (c); (e) copy it from some
1554 floating-point register,
1555
1556 Regarding copies from floating-point registers, r2 may only be
1557 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1558 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1559 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1560 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1561 dr10.
1562
1563 The bit mask is structured as follows:
1564
1565 - 1 bit to tell whether to set up a return trampoline.
1566
1567 - 3 bits to count the number consecutive registers to pop off the
1568 stack.
1569
1570 - 4 bits for each of r9, r8, r7 and r6.
1571
1572 - 3 bits for each of r5, r4, r3 and r2.
1573
1574 - 3 bits set to 0 (the most significant ones)
1575
1576 3 2 1 0
1577 1098 7654 3210 9876 5432 1098 7654 3210
1578 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1579 2223 3344 4555 6666 7777 8888 9999 SSS-
1580
1581 - If F is set, the register must be copied from an FP register,
1582 whose number is encoded in the remaining bits.
1583
1584 - Else, if L is set, the register must be loaded from the address
1585 contained in it. If the P bit is *not* set, the address of the
1586 following dword should be computed first, and stored in the
1587 following register.
1588
1589 - Else, if P is set, the register alone should be popped off the
1590 stack.
1591
1592 - After all this processing, the number of registers represented
1593 in SSS will be popped off the stack. This is an optimization
1594 for pushing/popping consecutive registers, typically used for
1595 varargs and large arguments partially passed in registers.
1596
1597 - If T is set, a return trampoline will be set up for 64-bit
1598 return values to be split into 2 32-bit registers. */
1599 long call_cookie;
1600
1601 /* This is set to nonzero when the call in question must use the Renesas ABI,
1602 even without the -mrenesas option. */
1603 int renesas_abi;
1604 };
1605
1606 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1607 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1608 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1609 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1610 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1611 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1612 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1613 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1614 #define CALL_COOKIE_INT_REG(REG, VAL) \
1615 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1616 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1617 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1618
1619 #define CUMULATIVE_ARGS struct sh_args
1620
1621 #define GET_SH_ARG_CLASS(MODE) \
1622 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1623 ? SH_ARG_FLOAT \
1624 /* There's no mention of complex float types in the SH5 ABI, so we
1625 should presumably handle them as aggregate types. */ \
1626 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1627 ? SH_ARG_INT \
1628 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1629 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1630 ? SH_ARG_FLOAT : SH_ARG_INT)
1631
1632 #define ROUND_ADVANCE(SIZE) \
1633 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1634
1635 /* Round a register number up to a proper boundary for an arg of mode
1636 MODE.
1637
1638 The SH doesn't care about double alignment, so we only
1639 round doubles to even regs when asked to explicitly. */
1640
1641 #define ROUND_REG(CUM, MODE) \
1642 (((TARGET_ALIGN_DOUBLE \
1643 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1644 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1645 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1646 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1647 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1648 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1649
1650 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1651 for a call to a function whose data type is FNTYPE.
1652 For a library call, FNTYPE is 0.
1653
1654 On SH, the offset always starts at 0: the first parm reg is always
1655 the same reg for a given argument class.
1656
1657 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1658
1659 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1660 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1661
1662 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1663 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1664
1665 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1666 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1667 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1668 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1669
1670 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1671 This macro is only used in this file. */
1672
1673 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1674 (((TYPE) == 0 \
1675 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1676 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1677 || ! (AGGREGATE_TYPE_P (TYPE) \
1678 || (!TARGET_FPU_ANY \
1679 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1680 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1681 && ! (CUM).force_mem \
1682 && (TARGET_SH2E \
1683 ? ((MODE) == BLKmode \
1684 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1685 + int_size_in_bytes (TYPE)) \
1686 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1687 : ((ROUND_REG((CUM), (MODE)) \
1688 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1689 <= NPARM_REGS (MODE))) \
1690 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1691
1692 /* By accident we got stuck with passing SCmode on SH4 little endian
1693 in two registers that are nominally successive - which is different from
1694 two single SFmode values, where we take endianness translation into
1695 account. That does not work at all if an odd number of registers is
1696 already in use, so that got fixed, but library functions are still more
1697 likely to use complex numbers without mixing them with SFmode arguments
1698 (which in C would have to be structures), so for the sake of ABI
1699 compatibility the way SCmode values are passed when an even number of
1700 FP registers is in use remains different from a pair of SFmode values for
1701 now.
1702 I.e.:
1703 foo (double); a: fr5,fr4
1704 foo (float a, float b); a: fr5 b: fr4
1705 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1706 this should be the other way round...
1707 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1708 #define FUNCTION_ARG_SCmode_WART 1
1709
1710 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1711 register in SHcompact mode, it must be padded in the most
1712 significant end. This means that passing it by reference wouldn't
1713 pad properly on a big-endian machine. In this particular case, we
1714 pass this argument on the stack, in a way that the call trampoline
1715 will load its value into the appropriate register. */
1716 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1717 ((MODE) == BLKmode \
1718 && TARGET_SHCOMPACT \
1719 && ! TARGET_LITTLE_ENDIAN \
1720 && int_size_in_bytes (TYPE) > 4 \
1721 && int_size_in_bytes (TYPE) < 8)
1722
1723 /* Minimum alignment for an argument to be passed by callee-copy
1724 reference. We need such arguments to be aligned to 8 byte
1725 boundaries, because they'll be loaded using quad loads. */
1726 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1727
1728 /* The SH5 ABI requires floating-point arguments to be passed to
1729 functions without a prototype in both an FP register and a regular
1730 register or the stack. When passing the argument in both FP and
1731 general-purpose registers, list the FP register first. */
1732 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1733 (gen_rtx_PARALLEL \
1734 ((MODE), \
1735 gen_rtvec (2, \
1736 gen_rtx_EXPR_LIST \
1737 (VOIDmode, \
1738 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1739 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1740 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1741 : NULL_RTX), \
1742 const0_rtx), \
1743 gen_rtx_EXPR_LIST \
1744 (VOIDmode, \
1745 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1746 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1747 + (CUM).arg_count[(int) SH_ARG_INT]) \
1748 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1749 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1750 const0_rtx))))
1751
1752 /* The SH5 ABI requires regular registers or stack slots to be
1753 reserved for floating-point arguments. Registers are taken care of
1754 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1755 Unfortunately, there's no way to just reserve a stack slot, so
1756 we'll end up needlessly storing a copy of the argument in the
1757 stack. For incoming arguments, however, the PARALLEL will be
1758 optimized to the register-only form, and the value in the stack
1759 slot won't be used at all. */
1760 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1761 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1762 ? gen_rtx_REG ((MODE), (REG)) \
1763 : gen_rtx_PARALLEL ((MODE), \
1764 gen_rtvec (2, \
1765 gen_rtx_EXPR_LIST \
1766 (VOIDmode, NULL_RTX, \
1767 const0_rtx), \
1768 gen_rtx_EXPR_LIST \
1769 (VOIDmode, gen_rtx_REG ((MODE), \
1770 (REG)), \
1771 const0_rtx))))
1772
1773 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1774 (TARGET_SH5 \
1775 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1776 || (MODE) == DCmode) \
1777 && ((CUM).arg_count[(int) SH_ARG_INT] \
1778 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1779 : GET_MODE_SIZE (MODE)) \
1780 + 7) / 8) > NPARM_REGS (SImode))
1781
1782 /* Perform any needed actions needed for a function that is receiving a
1783 variable number of arguments. */
1784
1785 /* Call the function profiler with a given profile label.
1786 We use two .aligns, so as to make sure that both the .long is aligned
1787 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1788 from the trapa instruction. */
1789
1790 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1791 { \
1792 if (TARGET_SHMEDIA) \
1793 { \
1794 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1795 fprintf((STREAM), "\ttrapa\tr0\n"); \
1796 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1797 } \
1798 else \
1799 { \
1800 fprintf((STREAM), "\t.align\t2\n"); \
1801 fprintf((STREAM), "\ttrapa\t#33\n"); \
1802 fprintf((STREAM), "\t.align\t2\n"); \
1803 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1804 } \
1805 }
1806
1807 /* Define this macro if the code for function profiling should come
1808 before the function prologue. Normally, the profiling code comes
1809 after. */
1810
1811 #define PROFILE_BEFORE_PROLOGUE
1812
1813 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1814 the stack pointer does not matter. The value is tested only in
1815 functions that have frame pointers.
1816 No definition is equivalent to always zero. */
1817
1818 #define EXIT_IGNORE_STACK 1
1819
1820 /*
1821 On the SH, the trampoline looks like
1822 2 0002 D202 mov.l l2,r2
1823 1 0000 D301 mov.l l1,r3
1824 3 0004 422B jmp @r2
1825 4 0006 0009 nop
1826 5 0008 00000000 l1: .long area
1827 6 000c 00000000 l2: .long function */
1828
1829 /* Length in units of the trampoline for entering a nested function. */
1830 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1831
1832 /* Alignment required for a trampoline in bits . */
1833 #define TRAMPOLINE_ALIGNMENT \
1834 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
1835 : TARGET_SHMEDIA ? 256 : 64)
1836
1837 /* Emit RTL insns to initialize the variable parts of a trampoline.
1838 FNADDR is an RTX for the address of the function's pure code.
1839 CXT is an RTX for the static chain value for the function. */
1840
1841 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1842 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1843
1844 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
1845
1846 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
1847 { \
1848 if (TARGET_SHMEDIA) \
1849 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
1850 gen_reg_rtx (Pmode), 0, \
1851 OPTAB_LIB_WIDEN); \
1852 } while (0)
1853
1854 /* A C expression whose value is RTL representing the value of the return
1855 address for the frame COUNT steps up from the current frame.
1856 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1857 can ignore COUNT. */
1858
1859 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1860 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1861
1862 /* A C expression whose value is RTL representing the location of the
1863 incoming return address at the beginning of any function, before the
1864 prologue. This RTL is either a REG, indicating that the return
1865 value is saved in REG, or a MEM representing a location in
1866 the stack. */
1867 #define INCOMING_RETURN_ADDR_RTX \
1868 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1869 \f
1870 /* Addressing modes, and classification of registers for them. */
1871 #define HAVE_POST_INCREMENT TARGET_SH1
1872 #define HAVE_PRE_DECREMENT TARGET_SH1
1873
1874 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1875 ? 0 : TARGET_SH1)
1876 #define USE_LOAD_PRE_DECREMENT(mode) 0
1877 #define USE_STORE_POST_INCREMENT(mode) 0
1878 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1879 ? 0 : TARGET_SH1)
1880
1881 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1882 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1883 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1884
1885 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1886 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1887 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1888
1889 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1890
1891 /* Macros to check register numbers against specific register classes. */
1892
1893 /* These assume that REGNO is a hard or pseudo reg number.
1894 They give nonzero only if REGNO is a hard reg of the suitable class
1895 or a pseudo reg currently allocated to a suitable hard reg.
1896 Since they use reg_renumber, they are safe only once reg_renumber
1897 has been allocated, which happens in local-alloc.c. */
1898
1899 #define REGNO_OK_FOR_BASE_P(REGNO) \
1900 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1901 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1902 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1903 (TARGET_SHMEDIA \
1904 ? (GENERAL_REGISTER_P (REGNO) \
1905 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1906 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1907
1908 /* Maximum number of registers that can appear in a valid memory
1909 address. */
1910
1911 #define MAX_REGS_PER_ADDRESS 2
1912
1913 /* Recognize any constant value that is a valid address. */
1914
1915 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1916
1917 /* Nonzero if the constant value X is a legitimate general operand. */
1918 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
1919
1920 #define LEGITIMATE_CONSTANT_P(X) \
1921 (TARGET_SHMEDIA \
1922 ? ((GET_MODE (X) != DFmode \
1923 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
1924 || (X) == CONST0_RTX (GET_MODE (X)) \
1925 || ! TARGET_SHMEDIA_FPU \
1926 || TARGET_SHMEDIA64) \
1927 : (GET_CODE (X) != CONST_DOUBLE \
1928 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1929 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
1930
1931 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1932 and check its validity for a certain class.
1933 The suitable hard regs are always accepted and all pseudo regs
1934 are also accepted if STRICT is not set. */
1935
1936 /* Nonzero if X is a reg that can be used as a base reg. */
1937 #define REG_OK_FOR_BASE_P(X, STRICT) \
1938 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1939 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1940
1941 /* Nonzero if X is a reg that can be used as an index. */
1942 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1943 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1944 : REGNO (X) == R0_REG) \
1945 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1946
1947 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1948 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1949 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1950 : REGNO (X) == R0_REG && OFFSET == 0) \
1951 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1952
1953 /* Macros for extra constraints. */
1954
1955 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1956 ((GET_CODE ((OP)) == LABEL_REF) \
1957 || (GET_CODE ((OP)) == CONST \
1958 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1959 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1960 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1961
1962 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1963 (CONSTANT_P (OP) \
1964 && !CONST_INT_P (OP) \
1965 && GET_CODE (OP) != CONST_DOUBLE \
1966 && (!flag_pic \
1967 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1968 && !PIC_ADDR_P (OP) \
1969 && GET_CODE (OP) != LABEL_REF)))
1970
1971 /* Check whether OP is a datalabel unspec. */
1972 #define DATALABEL_REF_NO_CONST_P(OP) \
1973 (GET_CODE (OP) == UNSPEC \
1974 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1975 && XVECLEN ((OP), 0) == 1 \
1976 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1977
1978 #define GOT_ENTRY_P(OP) \
1979 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1980 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1981
1982 #define GOTPLT_ENTRY_P(OP) \
1983 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1984 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1985
1986 #define UNSPEC_GOTOFF_P(OP) \
1987 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1988
1989 #define GOTOFF_P(OP) \
1990 (GET_CODE (OP) == CONST \
1991 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1992 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1993 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1994 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1995
1996 #define PIC_ADDR_P(OP) \
1997 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1998 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1999
2000 #define PCREL_SYMOFF_P(OP) \
2001 (GET_CODE (OP) == CONST \
2002 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2003 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
2004
2005 #define NON_PIC_REFERENCE_P(OP) \
2006 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2007 || (GET_CODE (OP) == CONST \
2008 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2009 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2010 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2011 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2012 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2013 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2014 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2015 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
2016
2017 #define PIC_REFERENCE_P(OP) \
2018 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2019 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2020
2021 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2022 (flag_pic \
2023 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2024 || PCREL_SYMOFF_P (OP)) \
2025 : NON_PIC_REFERENCE_P (OP))
2026 \f
2027 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
2028 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
2029 || (GET_CODE (X) == SUBREG \
2030 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2031 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2032 && REG_P (SUBREG_REG (X)) \
2033 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
2034
2035 /* Since this must be r0, which is a single register class, we must check
2036 SUBREGs more carefully, to be sure that we don't accept one that extends
2037 outside the class. */
2038 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
2039 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
2040 || (GET_CODE (X) == SUBREG \
2041 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2042 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2043 && REG_P (SUBREG_REG (X)) \
2044 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
2045
2046 #ifdef REG_OK_STRICT
2047 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
2048 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
2049 #else
2050 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
2051 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
2052 #endif
2053
2054 #define ALLOW_INDEXED_ADDRESS \
2055 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2056
2057 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
2058 do { \
2059 if (sh_legitimate_index_p ((MODE), (OP))) \
2060 goto WIN; \
2061 } while (0)
2062 \f
2063 /* A C compound statement that attempts to replace X, which is an address
2064 that needs reloading, with a valid memory address for an operand of
2065 mode MODE. WIN is a C statement label elsewhere in the code.
2066
2067 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2068 of the address. That will allow inheritance of the address reloads. */
2069
2070 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2071 { \
2072 if (GET_CODE (X) == PLUS \
2073 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2074 && CONST_INT_P (XEXP (X, 1)) \
2075 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2076 && ! TARGET_SHMEDIA \
2077 && ! (TARGET_SH4 && (MODE) == DFmode) \
2078 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2079 && (ALLOW_INDEXED_ADDRESS \
2080 || XEXP ((X), 0) == stack_pointer_rtx \
2081 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2082 { \
2083 rtx index_rtx = XEXP (X, 1); \
2084 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2085 rtx sum; \
2086 \
2087 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2088 { \
2089 push_reload (X, NULL_RTX, &X, NULL, \
2090 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2091 (TYPE)); \
2092 goto WIN; \
2093 } \
2094 if (TARGET_SH2E && MODE == SFmode) \
2095 { \
2096 X = copy_rtx (X); \
2097 push_reload (X, NULL_RTX, &X, NULL, \
2098 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2099 (TYPE)); \
2100 goto WIN; \
2101 } \
2102 /* Instead of offset_base 128..131 use 124..127, so that \
2103 simple add suffices. */ \
2104 if (offset > 127) \
2105 { \
2106 offset_base = ((offset + 4) & ~60) - 4; \
2107 } \
2108 else \
2109 offset_base = offset & ~60; \
2110 /* Sometimes the normal form does not suit DImode. We \
2111 could avoid that by using smaller ranges, but that \
2112 would give less optimized code when SImode is \
2113 prevalent. */ \
2114 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2115 { \
2116 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2117 GEN_INT (offset_base)); \
2118 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2119 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2120 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2121 (TYPE)); \
2122 goto WIN; \
2123 } \
2124 } \
2125 /* We must re-recognize what we created before. */ \
2126 else if (GET_CODE (X) == PLUS \
2127 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2128 && GET_CODE (XEXP (X, 0)) == PLUS \
2129 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
2130 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2131 && CONST_INT_P (XEXP (X, 1)) \
2132 && ! TARGET_SHMEDIA \
2133 && ! (TARGET_SH2E && MODE == SFmode)) \
2134 { \
2135 /* Because this address is so complex, we know it must have \
2136 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2137 it is already unshared, and needs no further unsharing. */ \
2138 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2139 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2140 goto WIN; \
2141 } \
2142 }
2143 \f
2144 /* Specify the machine mode that this machine uses
2145 for the index in the tablejump instruction. */
2146 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2147
2148 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2149 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2150 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2151 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2152 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2153 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2154 : SImode)
2155
2156 /* Define as C expression which evaluates to nonzero if the tablejump
2157 instruction expects the table to contain offsets from the address of the
2158 table.
2159 Do not define this if the table should contain absolute addresses. */
2160 #define CASE_VECTOR_PC_RELATIVE 1
2161
2162 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2163 #define FLOAT_TYPE_SIZE 32
2164
2165 /* Since the SH2e has only `float' support, it is desirable to make all
2166 floating point types equivalent to `float'. */
2167 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2168
2169 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2170 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2171 #else
2172 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2173 #endif
2174
2175 /* 'char' is signed by default. */
2176 #define DEFAULT_SIGNED_CHAR 1
2177
2178 /* The type of size_t unsigned int. */
2179 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2180
2181 #undef PTRDIFF_TYPE
2182 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2183
2184 #define WCHAR_TYPE "short unsigned int"
2185 #define WCHAR_TYPE_SIZE 16
2186
2187 #define SH_ELF_WCHAR_TYPE "long int"
2188
2189 /* Max number of bytes we can move from memory to memory
2190 in one reasonably fast instruction. */
2191 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2192
2193 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2194 MOVE_MAX is not a compile-time constant. */
2195 #define MAX_MOVE_MAX 8
2196
2197 /* Max number of bytes we want move_by_pieces to be able to copy
2198 efficiently. */
2199 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2200
2201 /* Define if operations between registers always perform the operation
2202 on the full register even if a narrower mode is specified. */
2203 #define WORD_REGISTER_OPERATIONS
2204
2205 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2206 will either zero-extend or sign-extend. The value of this macro should
2207 be the code that says which one of the two operations is implicitly
2208 done, UNKNOWN if none. */
2209 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2210 /* FP registers can load SImode values, but don't implicitly sign-extend
2211 them to DImode. */
2212 #define LOAD_EXTEND_OP(MODE) \
2213 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2214 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2215
2216 /* Define if loading short immediate values into registers sign extends. */
2217 #define SHORT_IMMEDIATES_SIGN_EXTEND
2218
2219 /* Nonzero if access to memory by bytes is no faster than for words. */
2220 #define SLOW_BYTE_ACCESS 1
2221
2222 /* Immediate shift counts are truncated by the output routines (or was it
2223 the assembler?). Shift counts in a register are truncated by SH. Note
2224 that the native compiler puts too large (> 32) immediate shift counts
2225 into a register and shifts by the register, letting the SH decide what
2226 to do instead of doing that itself. */
2227 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2228 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2229 expects - the sign bit is significant - so it appears that we need to
2230 leave this zero for correct SH3 code. */
2231 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2232
2233 /* All integers have the same format so truncation is easy. */
2234 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2235 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2236 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2237
2238 /* Define this if addresses of constant functions
2239 shouldn't be put through pseudo regs where they can be cse'd.
2240 Desirable on machines where ordinary constants are expensive
2241 but a CALL with constant address is cheap. */
2242 /*#define NO_FUNCTION_CSE 1*/
2243
2244 /* The machine modes of pointers and functions. */
2245 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2246 #define FUNCTION_MODE Pmode
2247
2248 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2249 are actually function calls with some special constraints on arguments
2250 and register usage.
2251
2252 These macros tell reorg that the references to arguments and
2253 register clobbers for insns of type sfunc do not appear to happen
2254 until after the millicode call. This allows reorg to put insns
2255 which set the argument registers into the delay slot of the millicode
2256 call -- thus they act more like traditional CALL_INSNs.
2257
2258 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2259 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2260 in particular. */
2261
2262 #define INSN_SETS_ARE_DELAYED(X) \
2263 ((NONJUMP_INSN_P (X) \
2264 && GET_CODE (PATTERN (X)) != SEQUENCE \
2265 && GET_CODE (PATTERN (X)) != USE \
2266 && GET_CODE (PATTERN (X)) != CLOBBER \
2267 && get_attr_is_sfunc (X)))
2268
2269 #define INSN_REFERENCES_ARE_DELAYED(X) \
2270 ((NONJUMP_INSN_P (X) \
2271 && GET_CODE (PATTERN (X)) != SEQUENCE \
2272 && GET_CODE (PATTERN (X)) != USE \
2273 && GET_CODE (PATTERN (X)) != CLOBBER \
2274 && get_attr_is_sfunc (X)))
2275
2276 \f
2277 /* Position Independent Code. */
2278
2279 /* We can't directly access anything that contains a symbol,
2280 nor can we indirect via the constant pool. */
2281 #define LEGITIMATE_PIC_OPERAND_P(X) \
2282 ((! nonpic_symbol_mentioned_p (X) \
2283 && (GET_CODE (X) != SYMBOL_REF \
2284 || ! CONSTANT_POOL_ADDRESS_P (X) \
2285 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2286 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2287
2288 #define SYMBOLIC_CONST_P(X) \
2289 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2290 && nonpic_symbol_mentioned_p (X))
2291 \f
2292 /* Compute extra cost of moving data between one register class
2293 and another. */
2294
2295 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2296 uses this information. Hence, the general register <-> floating point
2297 register information here is not used for SFmode. */
2298
2299 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2300 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2301 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2302
2303 #define REGCLASS_HAS_FP_REG(CLASS) \
2304 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2305 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2306
2307 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2308 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2309
2310 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2311 would be so that people with slow memory systems could generate
2312 different code that does fewer memory accesses. */
2313
2314 /* A C expression for the cost of a branch instruction. A value of 1
2315 is the default; other values are interpreted relative to that.
2316 The SH1 does not have delay slots, hence we get a pipeline stall
2317 at every branch. The SH4 is superscalar, so the single delay slot
2318 is not sufficient to keep both pipelines filled. */
2319 #define BRANCH_COST(speed_p, predictable_p) \
2320 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2321 \f
2322 /* Assembler output control. */
2323
2324 /* A C string constant describing how to begin a comment in the target
2325 assembler language. The compiler assumes that the comment will end at
2326 the end of the line. */
2327 #define ASM_COMMENT_START "!"
2328
2329 #define ASM_APP_ON ""
2330 #define ASM_APP_OFF ""
2331 #define FILE_ASM_OP "\t.file\n"
2332 #define SET_ASM_OP "\t.set\t"
2333
2334 /* How to change between sections. */
2335
2336 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2337 #define DATA_SECTION_ASM_OP "\t.data"
2338
2339 #if defined CRT_BEGIN || defined CRT_END
2340 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2341 # undef TEXT_SECTION_ASM_OP
2342 # if __SHMEDIA__ == 1 && __SH5__ == 32
2343 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2344 # else
2345 # define TEXT_SECTION_ASM_OP "\t.text"
2346 # endif
2347 #endif
2348
2349
2350 /* If defined, a C expression whose value is a string containing the
2351 assembler operation to identify the following data as
2352 uninitialized global data. If not defined, and neither
2353 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2354 uninitialized global data will be output in the data section if
2355 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2356 used. */
2357 #ifndef BSS_SECTION_ASM_OP
2358 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2359 #endif
2360
2361 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2362 separate, explicit argument. If you define this macro, it is used
2363 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2364 handling the required alignment of the variable. The alignment is
2365 specified as the number of bits.
2366
2367 Try to use function `asm_output_aligned_bss' defined in file
2368 `varasm.c' when defining this macro. */
2369 #ifndef ASM_OUTPUT_ALIGNED_BSS
2370 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2371 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2372 #endif
2373
2374 /* Define this so that jump tables go in same section as the current function,
2375 which could be text or it could be a user defined section. */
2376 #define JUMP_TABLES_IN_TEXT_SECTION 1
2377
2378 #undef DO_GLOBAL_CTORS_BODY
2379 #define DO_GLOBAL_CTORS_BODY \
2380 { \
2381 typedef void (*pfunc) (void); \
2382 extern pfunc __ctors[]; \
2383 extern pfunc __ctors_end[]; \
2384 pfunc *p; \
2385 for (p = __ctors_end; p > __ctors; ) \
2386 { \
2387 (*--p)(); \
2388 } \
2389 }
2390
2391 #undef DO_GLOBAL_DTORS_BODY
2392 #define DO_GLOBAL_DTORS_BODY \
2393 { \
2394 typedef void (*pfunc) (void); \
2395 extern pfunc __dtors[]; \
2396 extern pfunc __dtors_end[]; \
2397 pfunc *p; \
2398 for (p = __dtors; p < __dtors_end; p++) \
2399 { \
2400 (*p)(); \
2401 } \
2402 }
2403
2404 #define ASM_OUTPUT_REG_PUSH(file, v) \
2405 { \
2406 if (TARGET_SHMEDIA) \
2407 { \
2408 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2409 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2410 } \
2411 else \
2412 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2413 }
2414
2415 #define ASM_OUTPUT_REG_POP(file, v) \
2416 { \
2417 if (TARGET_SHMEDIA) \
2418 { \
2419 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2420 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2421 } \
2422 else \
2423 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2424 }
2425
2426 /* DBX register number for a given compiler register number. */
2427 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2428 to match gdb. */
2429 /* svr4.h undefines this macro, yet we really want to use the same numbers
2430 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2431 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2432 register exists, so we should return -1 for invalid register numbers. */
2433 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2434
2435 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2436 used to use the encodings 245..260, but that doesn't make sense:
2437 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2438 the FP registers stay the same when switching between compact and media
2439 mode. Hence, we also need to use the same dwarf frame columns.
2440 Likewise, we need to support unwind information for SHmedia registers
2441 even in compact code. */
2442 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2443 (IN_RANGE ((REGNO), \
2444 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2445 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2446 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2447 : ((int) (REGNO) >= FIRST_FP_REG \
2448 && ((int) (REGNO) \
2449 <= (FIRST_FP_REG + \
2450 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2451 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2452 + (TARGET_SH5 ? 77 : 25)) \
2453 : XD_REGISTER_P (REGNO) \
2454 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2455 : TARGET_REGISTER_P (REGNO) \
2456 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2457 : (REGNO) == PR_REG \
2458 ? (TARGET_SH5 ? 18 : 17) \
2459 : (REGNO) == PR_MEDIA_REG \
2460 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2461 : (REGNO) == GBR_REG \
2462 ? (TARGET_SH5 ? 238 : 18) \
2463 : (REGNO) == MACH_REG \
2464 ? (TARGET_SH5 ? 239 : 20) \
2465 : (REGNO) == MACL_REG \
2466 ? (TARGET_SH5 ? 240 : 21) \
2467 : (REGNO) == T_REG \
2468 ? (TARGET_SH5 ? 242 : 22) \
2469 : (REGNO) == FPUL_REG \
2470 ? (TARGET_SH5 ? 244 : 23) \
2471 : (REGNO) == FPSCR_REG \
2472 ? (TARGET_SH5 ? 243 : 24) \
2473 : (unsigned) -1)
2474
2475 /* This is how to output a reference to a symbol_ref. On SH5,
2476 references to non-code symbols must be preceded by `datalabel'. */
2477 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2478 do \
2479 { \
2480 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2481 fputs ("datalabel ", (FILE)); \
2482 assemble_name ((FILE), XSTR ((SYM), 0)); \
2483 } \
2484 while (0)
2485
2486 /* This is how to output an assembler line
2487 that says to advance the location counter
2488 to a multiple of 2**LOG bytes. */
2489
2490 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2491 if ((LOG) != 0) \
2492 fprintf ((FILE), "\t.align %d\n", (LOG))
2493
2494 /* Globalizing directive for a label. */
2495 #define GLOBAL_ASM_OP "\t.global\t"
2496
2497 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2498
2499 /* Output a relative address table. */
2500
2501 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2502 switch (GET_MODE (BODY)) \
2503 { \
2504 case SImode: \
2505 if (TARGET_SH5) \
2506 { \
2507 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2508 (VALUE), (REL)); \
2509 break; \
2510 } \
2511 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2512 break; \
2513 case HImode: \
2514 if (TARGET_SH5) \
2515 { \
2516 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2517 (VALUE), (REL)); \
2518 break; \
2519 } \
2520 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2521 break; \
2522 case QImode: \
2523 if (TARGET_SH5) \
2524 { \
2525 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2526 (VALUE), (REL)); \
2527 break; \
2528 } \
2529 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2530 break; \
2531 default: \
2532 break; \
2533 }
2534
2535 /* Output an absolute table element. */
2536
2537 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2538 if (! optimize || TARGET_BIGTABLE) \
2539 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2540 else \
2541 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2542
2543 \f
2544 /* A C statement to be executed just prior to the output of
2545 assembler code for INSN, to modify the extracted operands so
2546 they will be output differently.
2547
2548 Here the argument OPVEC is the vector containing the operands
2549 extracted from INSN, and NOPERANDS is the number of elements of
2550 the vector which contain meaningful data for this insn.
2551 The contents of this vector are what will be used to convert the insn
2552 template into assembler code, so you can change the assembler output
2553 by changing the contents of the vector. */
2554
2555 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2556 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2557
2558 /* Print operand X (an rtx) in assembler syntax to file FILE.
2559 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2560 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2561
2562 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2563
2564 /* Print a memory address as an operand to reference that memory location. */
2565
2566 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2567
2568 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2569 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
2570 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
2571
2572 /* Recognize machine-specific patterns that may appear within
2573 constants. Used for PIC-specific UNSPECs. */
2574 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2575 do \
2576 if (GET_CODE (X) == UNSPEC) \
2577 { \
2578 switch (XINT ((X), 1)) \
2579 { \
2580 case UNSPEC_DATALABEL: \
2581 fputs ("datalabel ", (STREAM)); \
2582 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2583 break; \
2584 case UNSPEC_PIC: \
2585 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2586 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2587 break; \
2588 case UNSPEC_GOT: \
2589 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2590 fputs ("@GOT", (STREAM)); \
2591 break; \
2592 case UNSPEC_GOTOFF: \
2593 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2594 fputs ("@GOTOFF", (STREAM)); \
2595 break; \
2596 case UNSPEC_PLT: \
2597 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2598 fputs ("@PLT", (STREAM)); \
2599 break; \
2600 case UNSPEC_GOTPLT: \
2601 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2602 fputs ("@GOTPLT", (STREAM)); \
2603 break; \
2604 case UNSPEC_DTPOFF: \
2605 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2606 fputs ("@DTPOFF", (STREAM)); \
2607 break; \
2608 case UNSPEC_GOTTPOFF: \
2609 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2610 fputs ("@GOTTPOFF", (STREAM)); \
2611 break; \
2612 case UNSPEC_TPOFF: \
2613 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2614 fputs ("@TPOFF", (STREAM)); \
2615 break; \
2616 case UNSPEC_CALLER: \
2617 { \
2618 char name[32]; \
2619 /* LPCS stands for Label for PIC Call Site. */ \
2620 ASM_GENERATE_INTERNAL_LABEL \
2621 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2622 assemble_name ((STREAM), name); \
2623 } \
2624 break; \
2625 case UNSPEC_EXTRACT_S16: \
2626 case UNSPEC_EXTRACT_U16: \
2627 { \
2628 rtx val, shift; \
2629 \
2630 val = XVECEXP (X, 0, 0); \
2631 shift = XVECEXP (X, 0, 1); \
2632 fputc ('(', STREAM); \
2633 if (shift != const0_rtx) \
2634 fputc ('(', STREAM); \
2635 if (GET_CODE (val) == CONST \
2636 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
2637 { \
2638 fputc ('(', STREAM); \
2639 output_addr_const (STREAM, val); \
2640 fputc (')', STREAM); \
2641 } \
2642 else \
2643 output_addr_const (STREAM, val); \
2644 if (shift != const0_rtx) \
2645 { \
2646 fputs (" >> ", STREAM); \
2647 output_addr_const (STREAM, shift); \
2648 fputc (')', STREAM); \
2649 } \
2650 fputs (" & 65535)", STREAM); \
2651 } \
2652 break; \
2653 case UNSPEC_SYMOFF: \
2654 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2655 fputc ('-', STREAM); \
2656 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
2657 { \
2658 fputc ('(', STREAM); \
2659 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2660 fputc (')', STREAM); \
2661 } \
2662 else \
2663 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2664 break; \
2665 case UNSPEC_PCREL_SYMOFF: \
2666 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2667 fputs ("-(", STREAM); \
2668 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2669 fputs ("-.)", STREAM); \
2670 break; \
2671 default: \
2672 goto FAIL; \
2673 } \
2674 break; \
2675 } \
2676 else \
2677 goto FAIL; \
2678 while (0)
2679
2680 \f
2681 extern struct rtx_def *sh_compare_op0;
2682 extern struct rtx_def *sh_compare_op1;
2683
2684 /* Which processor to schedule for. The elements of the enumeration must
2685 match exactly the cpu attribute in the sh.md file. */
2686
2687 enum processor_type {
2688 PROCESSOR_SH1,
2689 PROCESSOR_SH2,
2690 PROCESSOR_SH2E,
2691 PROCESSOR_SH2A,
2692 PROCESSOR_SH3,
2693 PROCESSOR_SH3E,
2694 PROCESSOR_SH4,
2695 PROCESSOR_SH4A,
2696 PROCESSOR_SH5
2697 };
2698
2699 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2700 extern enum processor_type sh_cpu;
2701
2702 extern int optimize; /* needed for gen_casesi. */
2703
2704 enum mdep_reorg_phase_e
2705 {
2706 SH_BEFORE_MDEP_REORG,
2707 SH_INSERT_USES_LABELS,
2708 SH_SHORTEN_BRANCHES0,
2709 SH_FIXUP_PCLOAD,
2710 SH_SHORTEN_BRANCHES1,
2711 SH_AFTER_MDEP_REORG
2712 };
2713
2714 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2715
2716 /* Handle Renesas compiler's pragmas. */
2717 #define REGISTER_TARGET_PRAGMAS() do { \
2718 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2719 c_register_pragma (0, "trapa", sh_pr_trapa); \
2720 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2721 } while (0)
2722
2723 extern tree sh_deferred_function_attributes;
2724 extern tree *sh_deferred_function_attributes_tail;
2725
2726 /* Set when processing a function with interrupt attribute. */
2727
2728 extern int current_function_interrupt;
2729
2730 \f
2731 /* Instructions with unfilled delay slots take up an
2732 extra two bytes for the nop in the delay slot.
2733 sh-dsp parallel processing insns are four bytes long. */
2734
2735 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2736 (LENGTH) += sh_insn_length_adjustment (X);
2737 \f
2738 /* Define this macro if it is advisable to hold scalars in registers
2739 in a wider mode than that declared by the program. In such cases,
2740 the value is constrained to be within the bounds of the declared
2741 type, but kept valid in the wider mode. The signedness of the
2742 extension may differ from that of the type.
2743
2744 Leaving the unsignedp unchanged gives better code than always setting it
2745 to 0. This is despite the fact that we have only signed char and short
2746 load instructions. */
2747 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2748 if (GET_MODE_CLASS (MODE) == MODE_INT \
2749 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2750 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2751 (MODE) = (TARGET_SH1 ? SImode \
2752 : TARGET_SHMEDIA32 ? SImode : DImode);
2753
2754 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2755
2756 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2757
2758 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2759 and popping arguments. However, we do have push/pop instructions, and
2760 rather limited offsets (4 bits) in load/store instructions, so it isn't
2761 clear if this would give better code. If implemented, should check for
2762 compatibility problems. */
2763
2764 #define SH_DYNAMIC_SHIFT_COST \
2765 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2766
2767
2768 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2769
2770 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2771
2772 #define ACTUAL_NORMAL_MODE(ENTITY) \
2773 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2774
2775 #define NORMAL_MODE(ENTITY) \
2776 (sh_cfun_interrupt_handler_p () \
2777 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2778 : ACTUAL_NORMAL_MODE (ENTITY))
2779
2780 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2781
2782 #define MODE_EXIT(ENTITY) \
2783 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2784
2785 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2786 && (REGNO) == FPSCR_REG)
2787
2788 #define MODE_NEEDED(ENTITY, INSN) \
2789 (recog_memoized (INSN) >= 0 \
2790 ? get_attr_fp_mode (INSN) \
2791 : FP_MODE_NONE)
2792
2793 #define MODE_AFTER(MODE, INSN) \
2794 (TARGET_HITACHI \
2795 && recog_memoized (INSN) >= 0 \
2796 && get_attr_fp_set (INSN) != FP_SET_NONE \
2797 ? (int) get_attr_fp_set (INSN) \
2798 : (MODE))
2799
2800 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2801 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2802
2803 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2804 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2805
2806 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2807 sh_can_redirect_branch ((INSN), (SEQ))
2808
2809 #define DWARF_FRAME_RETURN_COLUMN \
2810 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2811
2812 #define EH_RETURN_DATA_REGNO(N) \
2813 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2814
2815 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2816 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2817
2818 /* We have to distinguish between code and data, so that we apply
2819 datalabel where and only where appropriate. Use sdataN for data. */
2820 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2821 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2822 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2823 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2824
2825 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2826 indirect are handled automatically. */
2827 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2828 do { \
2829 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2830 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2831 { \
2832 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2833 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2834 if (0) goto DONE; \
2835 } \
2836 } while (0)
2837
2838 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2839 /* SH constant pool breaks the devices in crtstuff.c to control section
2840 in where code resides. We have to write it as asm code. */
2841 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2842 asm (SECTION_OP "\n\
2843 mov.l 1f,r1\n\
2844 mova 2f,r0\n\
2845 braf r1\n\
2846 lds r0,pr\n\
2847 0: .p2align 2\n\
2848 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2849 2:\n" TEXT_SECTION_ASM_OP);
2850 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2851
2852 /* FIXME: middle-end support for highpart optimizations is missing. */
2853 #define high_life_started reload_in_progress
2854
2855 #endif /* ! GCC_SH_H */
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