1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Copy sign instructions
109 (UNSPEC_COPYSIGN 800)
111 ; Test Data Class (TDC)
112 (UNSPEC_TDC_INSN 900)
116 ;; UNSPEC_VOLATILE usage
124 (UNSPECV_TPF_PROLOGUE 20)
125 (UNSPECV_TPF_EPILOGUE 21)
129 (UNSPECV_POOL_SECTION 201)
130 (UNSPECV_POOL_ALIGN 202)
131 (UNSPECV_POOL_ENTRY 203)
132 (UNSPECV_MAIN_POOL 300)
145 ; Registers with special meaning
149 ; Sibling call register.
151 ; Literal pool base register.
153 ; Return address register.
155 ; Condition code register.
157 ; Thread local storage pointer register.
161 ; Hardware register names
165 ; General purpose registers
167 ; Floating point registers.
173 ;; PFPO GPR0 argument format
178 ; PFPO operation type
179 (PFPO_CONVERT 0x1000000)
181 (PFPO_OP_TYPE_SF 0x5)
182 (PFPO_OP_TYPE_DF 0x6)
183 (PFPO_OP_TYPE_TF 0x7)
184 (PFPO_OP_TYPE_SD 0x8)
185 (PFPO_OP_TYPE_DD 0x9)
186 (PFPO_OP_TYPE_TD 0xa)
187 ; Bitposition of operand types
188 (PFPO_OP0_TYPE_SHIFT 16)
189 (PFPO_OP1_TYPE_SHIFT 8)
193 ;; Instruction operand type as used in the Principles of Operation.
194 ;; Used to determine defaults for length and other attribute values.
196 (define_attr "op_type"
197 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
200 ;; Instruction type attribute used for scheduling.
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
203 cs,vs,store,sem,idiv,
204 imulhi,imulsi,imuldi,
205 branch,jsr,fsimptf,fsimpdf,fsimpsf,
206 floadtf,floaddf,floadsf,fstoredf,fstoresf,
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
210 itoftf, itofdf, itofsf, itofdd, itoftd,
211 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
212 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
214 (cond [(eq_attr "op_type" "NN") (const_string "other")
215 (eq_attr "op_type" "SS") (const_string "cs")]
216 (const_string "integer")))
218 ;; Another attribute used for scheduling purposes:
219 ;; agen: Instruction uses the address generation unit
220 ;; reg: Instruction does not use the agen unit
222 (define_attr "atype" "agen,reg"
223 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
225 (const_string "agen")))
227 ;; Properties concerning Z10 execution grouping and value forwarding.
228 ;; z10_super: instruction is superscalar.
229 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
230 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
231 ;; target register. It can forward this value to a second instruction that reads
232 ;; the same register if that second instruction is issued in the same group.
233 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
234 ;; instruction in the S pipe writes to the register, then the T instruction
235 ;; can immediately read the new value.
236 ;; z10_fr: union of Z10_fwd and z10_rec.
237 ;; z10_c: second operand of instruction is a register and read with complemented bits.
239 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
242 (define_attr "z10prop" "none,
243 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
244 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
246 z10_fr, z10_fr_A3, z10_fr_E1,
248 (const_string "none"))
253 (define_attr "length" ""
254 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
255 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
259 ;; Processor type. This attribute must exactly match the processor_type
260 ;; enumeration in s390.h. The current machine description does not
261 ;; distinguish between g5 and g6, but there are differences between the two
262 ;; CPUs could in theory be modeled.
264 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
265 (const (symbol_ref "s390_tune_attr")))
267 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
268 (const_string "standard"))
270 (define_attr "enabled" ""
271 (cond [(eq_attr "cpu_facility" "standard")
274 (and (eq_attr "cpu_facility" "ieee")
275 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
278 (and (eq_attr "cpu_facility" "zarch")
279 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
282 (and (eq_attr "cpu_facility" "longdisp")
283 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
286 (and (eq_attr "cpu_facility" "extimm")
287 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
290 (and (eq_attr "cpu_facility" "dfp")
291 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
294 (and (eq_attr "cpu_facility" "z10")
295 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
299 ;; Pipeline description for z900. For lack of anything better,
300 ;; this description is also used for the g5 and g6.
303 ;; Pipeline description for z990, z9-109 and z9-ec.
306 ;; Pipeline description for z10
310 (include "predicates.md")
312 ;; Constraint definitions
313 (include "constraints.md")
320 ;; These mode iterators allow floating point patterns to be generated from the
322 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
323 (SD "TARGET_HARD_DFP")])
324 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
325 (define_mode_iterator FPALL [TF DF SF TD DD SD])
326 (define_mode_iterator BFP [TF DF SF])
327 (define_mode_iterator DFP [TD DD])
328 (define_mode_iterator DFP_ALL [TD DD SD])
329 (define_mode_iterator DSF [DF SF])
330 (define_mode_iterator SD_SF [SF SD])
331 (define_mode_iterator DD_DF [DF DD])
332 (define_mode_iterator TD_TF [TF TD])
334 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
335 ;; from the same template.
336 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
338 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
339 ;; from the same template.
340 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
341 (define_mode_iterator DSI [DI SI])
343 ;; These mode iterators allow :P to be used for patterns that operate on
344 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
345 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
346 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
348 ;; This mode iterator allows the QI and HI patterns to be defined from
349 ;; the same template.
350 (define_mode_iterator HQI [HI QI])
352 ;; This mode iterator allows the integer patterns to be defined from the
354 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
355 (define_mode_iterator INTALL [TI DI SI HI QI])
357 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
358 ;; the same template.
359 (define_code_iterator SHIFT [ashift lshiftrt])
361 ;; This iterator and attribute allow to combine most atomic operations.
362 (define_code_iterator ATOMIC [and ior xor plus minus mult])
363 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
364 (plus "add") (minus "sub") (mult "nand")])
366 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
367 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
368 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
370 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
371 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
373 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
375 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
376 ;; Likewise for "<RXe>".
377 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
378 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
380 ;; The decimal floating point variants of add, sub, div and mul support 3
381 ;; fp register operands. The following attributes allow to merge the bfp and
382 ;; dfp variants in a single insn definition.
384 ;; This attribute is used to set op_type accordingly.
385 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
386 (DD "RRR") (SD "RRR")])
388 ;; This attribute is used in the operand constraint list in order to have the
389 ;; first and the second operand match for bfp modes.
390 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
392 ;; This attribute is used in the operand list of the instruction to have an
393 ;; additional operand for the dfp instructions.
394 (define_mode_attr op1 [(TF "") (DF "") (SF "")
395 (TD "%1,") (DD "%1,") (SD "%1,")])
398 ;; This attribute is used in the operand constraint list
399 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
400 ;; TFmode values are represented by a fp register pair. Since the
401 ;; sign bit instructions only handle single source and target fp registers
402 ;; these instructions can only be used for TFmode values if the source and
403 ;; target operand uses the same fp register.
404 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
406 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
407 ;; This is used to disable the memory alternative in TFmode patterns.
408 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
410 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
411 ;; within instruction mnemonics.
412 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
414 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
415 ;; modes and to an empty string for bfp modes.
416 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
418 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
419 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
420 ;; version only operates on one register.
421 (define_mode_attr d0 [(DI "d") (SI "0")])
423 ;; In combination with d0 this allows to combine instructions of which the 31bit
424 ;; version only operates on one register. The DImode version needs an additional
425 ;; register for the assembler output.
426 (define_mode_attr 1 [(DI "%1,") (SI "")])
428 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
429 ;; 'ashift' and "srdl" in 'lshiftrt'.
430 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
432 ;; In SHIFT templates, this attribute holds the correct standard name for the
433 ;; pattern itself and the corresponding function calls.
434 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
436 ;; This attribute handles differences in the instruction 'type' and will result
437 ;; in "RRE" for DImode and "RR" for SImode.
438 (define_mode_attr E [(DI "E") (SI "")])
440 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
441 ;; to result in "RXY" for DImode and "RX" for SImode.
442 (define_mode_attr Y [(DI "Y") (SI "")])
444 ;; This attribute handles differences in the instruction 'type' and will result
445 ;; in "RSE" for TImode and "RS" for DImode.
446 (define_mode_attr TE [(TI "E") (DI "")])
448 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
449 ;; and "lcr" in SImode.
450 (define_mode_attr g [(DI "g") (SI "")])
452 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
453 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
454 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
455 ;; variant for long displacements.
456 (define_mode_attr y [(DI "g") (SI "y")])
458 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
459 ;; and "cds" in DImode.
460 (define_mode_attr tg [(TI "g") (DI "")])
462 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
463 ;; and "cfdbr" in SImode.
464 (define_mode_attr gf [(DI "g") (SI "f")])
466 ;; ICM mask required to load MODE value into the lowest subreg
467 ;; of a SImode register.
468 (define_mode_attr icm_lo [(HI "3") (QI "1")])
470 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
471 ;; HImode and "llgc" in QImode.
472 (define_mode_attr hc [(HI "h") (QI "c")])
474 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
476 (define_mode_attr DBL [(DI "TI") (SI "DI")])
478 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
479 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
480 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
482 ;; Maximum unsigned integer that fits in MODE.
483 (define_mode_attr max_uint [(HI "65535") (QI "255")])
486 ;;- Compare instructions.
489 ; Test-under-Mask instructions
491 (define_insn "*tmqi_mem"
492 [(set (reg CC_REGNUM)
493 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
494 (match_operand:QI 1 "immediate_operand" "n,n"))
495 (match_operand:QI 2 "immediate_operand" "n,n")))]
496 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
500 [(set_attr "op_type" "SI,SIY")
501 (set_attr "z10prop" "z10_super,z10_super")])
503 (define_insn "*tmdi_reg"
504 [(set (reg CC_REGNUM)
505 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
506 (match_operand:DI 1 "immediate_operand"
507 "N0HD0,N1HD0,N2HD0,N3HD0"))
508 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
510 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
511 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
517 [(set_attr "op_type" "RI")
518 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
520 (define_insn "*tmsi_reg"
521 [(set (reg CC_REGNUM)
522 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
523 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
524 (match_operand:SI 2 "immediate_operand" "n,n")))]
525 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
526 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
530 [(set_attr "op_type" "RI")
531 (set_attr "z10prop" "z10_super,z10_super")])
533 (define_insn "*tm<mode>_full"
534 [(set (reg CC_REGNUM)
535 (compare (match_operand:HQI 0 "register_operand" "d")
536 (match_operand:HQI 1 "immediate_operand" "n")))]
537 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
539 [(set_attr "op_type" "RI")
540 (set_attr "z10prop" "z10_super")])
544 ; Load-and-Test instructions
547 ; tst(di|si) instruction pattern(s).
549 (define_insn "*tstdi_sign"
550 [(set (reg CC_REGNUM)
554 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
555 (const_int 32)) (const_int 32))
556 (match_operand:DI 1 "const0_operand" "")))
557 (set (match_operand:DI 2 "register_operand" "=d,d")
558 (sign_extend:DI (match_dup 0)))]
559 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
562 [(set_attr "op_type" "RRE,RXY")
563 (set_attr "cpu_facility" "*,z10")
564 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
567 (define_insn "*tst<mode>_extimm"
568 [(set (reg CC_REGNUM)
569 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
570 (match_operand:GPR 1 "const0_operand" "")))
571 (set (match_operand:GPR 2 "register_operand" "=d,d")
573 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
577 [(set_attr "op_type" "RR<E>,RXY")
578 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
581 (define_insn "*tst<mode>_cconly_extimm"
582 [(set (reg CC_REGNUM)
583 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
584 (match_operand:GPR 1 "const0_operand" "")))
585 (clobber (match_scratch:GPR 2 "=X,d"))]
586 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
590 [(set_attr "op_type" "RR<E>,RXY")
591 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
593 (define_insn "*tstdi"
594 [(set (reg CC_REGNUM)
595 (compare (match_operand:DI 0 "register_operand" "d")
596 (match_operand:DI 1 "const0_operand" "")))
597 (set (match_operand:DI 2 "register_operand" "=d")
599 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
601 [(set_attr "op_type" "RRE")
602 (set_attr "z10prop" "z10_fr_E1")])
604 (define_insn "*tstsi"
605 [(set (reg CC_REGNUM)
606 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
607 (match_operand:SI 1 "const0_operand" "")))
608 (set (match_operand:SI 2 "register_operand" "=d,d,d")
610 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
615 [(set_attr "op_type" "RR,RS,RSY")
616 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
618 (define_insn "*tstsi_cconly"
619 [(set (reg CC_REGNUM)
620 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
621 (match_operand:SI 1 "const0_operand" "")))
622 (clobber (match_scratch:SI 2 "=X,d,d"))]
623 "s390_match_ccmode(insn, CCSmode)"
628 [(set_attr "op_type" "RR,RS,RSY")
629 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
631 (define_insn "*tstdi_cconly_31"
632 [(set (reg CC_REGNUM)
633 (compare (match_operand:DI 0 "register_operand" "d")
634 (match_operand:DI 1 "const0_operand" "")))]
635 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
637 [(set_attr "op_type" "RS")
638 (set_attr "atype" "reg")])
641 (define_insn "*tst<mode>_cconly2"
642 [(set (reg CC_REGNUM)
643 (compare (match_operand:GPR 0 "register_operand" "d")
644 (match_operand:GPR 1 "const0_operand" "")))]
645 "s390_match_ccmode(insn, CCSmode)"
647 [(set_attr "op_type" "RR<E>")
648 (set_attr "z10prop" "z10_fr_E1")])
650 ; tst(hi|qi) instruction pattern(s).
652 (define_insn "*tst<mode>CCT"
653 [(set (reg CC_REGNUM)
654 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
655 (match_operand:HQI 1 "const0_operand" "")))
656 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
658 "s390_match_ccmode(insn, CCTmode)"
661 icmy\t%2,<icm_lo>,%S0
663 [(set_attr "op_type" "RS,RSY,RI")
664 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
666 (define_insn "*tsthiCCT_cconly"
667 [(set (reg CC_REGNUM)
668 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
669 (match_operand:HI 1 "const0_operand" "")))
670 (clobber (match_scratch:HI 2 "=d,d,X"))]
671 "s390_match_ccmode(insn, CCTmode)"
676 [(set_attr "op_type" "RS,RSY,RI")
677 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
679 (define_insn "*tstqiCCT_cconly"
680 [(set (reg CC_REGNUM)
681 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
682 (match_operand:QI 1 "const0_operand" "")))]
683 "s390_match_ccmode(insn, CCTmode)"
688 [(set_attr "op_type" "SI,SIY,RI")
689 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
691 (define_insn "*tst<mode>"
692 [(set (reg CC_REGNUM)
693 (compare (match_operand:HQI 0 "s_operand" "Q,S")
694 (match_operand:HQI 1 "const0_operand" "")))
695 (set (match_operand:HQI 2 "register_operand" "=d,d")
697 "s390_match_ccmode(insn, CCSmode)"
700 icmy\t%2,<icm_lo>,%S0"
701 [(set_attr "op_type" "RS,RSY")
702 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
704 (define_insn "*tst<mode>_cconly"
705 [(set (reg CC_REGNUM)
706 (compare (match_operand:HQI 0 "s_operand" "Q,S")
707 (match_operand:HQI 1 "const0_operand" "")))
708 (clobber (match_scratch:HQI 2 "=d,d"))]
709 "s390_match_ccmode(insn, CCSmode)"
712 icmy\t%2,<icm_lo>,%S0"
713 [(set_attr "op_type" "RS,RSY")
714 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
717 ; Compare (equality) instructions
719 (define_insn "*cmpdi_cct"
720 [(set (reg CC_REGNUM)
721 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
722 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
723 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
730 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
731 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
733 (define_insn "*cmpsi_cct"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
736 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
737 "s390_match_ccmode (insn, CCTmode)"
745 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
746 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
748 ; Compare (signed) instructions
750 (define_insn "*cmpdi_ccs_sign"
751 [(set (reg CC_REGNUM)
752 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
754 (match_operand:DI 0 "register_operand" "d, d,d")))]
755 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
760 [(set_attr "op_type" "RRE,RXY,RIL")
761 (set_attr "z10prop" "z10_c,*,*")
762 (set_attr "type" "*,*,larl")])
766 (define_insn "*cmpsi_ccs_sign"
767 [(set (reg CC_REGNUM)
768 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
769 (match_operand:SI 0 "register_operand" "d,d,d")))]
770 "s390_match_ccmode(insn, CCSRmode)"
775 [(set_attr "op_type" "RX,RXY,RIL")
776 (set_attr "cpu_facility" "*,*,z10")
777 (set_attr "type" "*,*,larl")])
779 (define_insn "*cmphi_ccs_z10"
780 [(set (reg CC_REGNUM)
781 (compare (match_operand:HI 0 "s_operand" "Q")
782 (match_operand:HI 1 "immediate_operand" "K")))]
783 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
785 [(set_attr "op_type" "SIL")])
787 (define_insn "*cmpdi_ccs_signhi_rl"
788 [(set (reg CC_REGNUM)
789 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
790 (match_operand:GPR 0 "register_operand" "d,d")))]
791 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
795 [(set_attr "op_type" "RXY,RIL")
796 (set_attr "type" "*,larl")])
798 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
799 (define_insn "*cmp<mode>_ccs"
800 [(set (reg CC_REGNUM)
801 (compare (match_operand:GPR 0 "nonimmediate_operand"
803 (match_operand:GPR 1 "general_operand"
805 "s390_match_ccmode(insn, CCSmode)"
814 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
815 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
816 (set_attr "type" "*,*,*,*,*,*,larl")
817 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
820 ; Compare (unsigned) instructions
822 (define_insn "*cmpsi_ccu_zerohi_rlsi"
823 [(set (reg CC_REGNUM)
824 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
825 "larl_operand" "X")))
826 (match_operand:SI 0 "register_operand" "d")))]
827 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
829 [(set_attr "op_type" "RIL")
830 (set_attr "type" "larl")
831 (set_attr "z10prop" "z10_super")])
834 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
835 [(set (reg CC_REGNUM)
836 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
837 "larl_operand" "X")))
838 (match_operand:GPR 0 "register_operand" "d")))]
839 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
841 [(set_attr "op_type" "RIL")
842 (set_attr "type" "larl")
843 (set_attr "z10prop" "z10_super")])
845 (define_insn "*cmpdi_ccu_zero"
846 [(set (reg CC_REGNUM)
847 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
849 (match_operand:DI 0 "register_operand" "d, d,d")))]
850 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
855 [(set_attr "op_type" "RRE,RXY,RIL")
856 (set_attr "cpu_facility" "*,*,z10")
857 (set_attr "type" "*,*,larl")
858 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
860 (define_insn "*cmpdi_ccu"
861 [(set (reg CC_REGNUM)
862 (compare (match_operand:DI 0 "nonimmediate_operand"
864 (match_operand:DI 1 "general_operand"
865 "d,Op,b,D,RT,BQ,Q")))]
866 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
875 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
876 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
877 (set_attr "type" "*,*,larl,*,*,*,*")
878 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
880 (define_insn "*cmpsi_ccu"
881 [(set (reg CC_REGNUM)
882 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
883 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
884 "s390_match_ccmode (insn, CCUmode)"
894 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
895 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
896 (set_attr "type" "*,*,larl,*,*,*,*,*")
897 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
899 (define_insn "*cmphi_ccu"
900 [(set (reg CC_REGNUM)
901 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
902 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
903 "s390_match_ccmode (insn, CCUmode)
904 && !register_operand (operands[1], HImode)"
911 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
912 (set_attr "cpu_facility" "*,*,z10,*,*")
913 (set_attr "z10prop" "*,*,z10_super,*,*")])
915 (define_insn "*cmpqi_ccu"
916 [(set (reg CC_REGNUM)
917 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
918 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
919 "s390_match_ccmode (insn, CCUmode)
920 && !register_operand (operands[1], QImode)"
928 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
929 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
932 ; Block compare (CLC) instruction patterns.
935 [(set (reg CC_REGNUM)
936 (compare (match_operand:BLK 0 "memory_operand" "Q")
937 (match_operand:BLK 1 "memory_operand" "Q")))
938 (use (match_operand 2 "const_int_operand" "n"))]
939 "s390_match_ccmode (insn, CCUmode)
940 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
941 "clc\t%O0(%2,%R0),%S1"
942 [(set_attr "op_type" "SS")])
945 [(set (reg CC_REGNUM)
946 (compare (match_operand 0 "memory_operand" "")
947 (match_operand 1 "memory_operand" "")))]
949 && s390_match_ccmode (insn, CCUmode)
950 && GET_MODE (operands[0]) == GET_MODE (operands[1])
951 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
953 [(set (match_dup 0) (match_dup 1))
954 (use (match_dup 2))])]
956 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
957 operands[0] = adjust_address (operands[0], BLKmode, 0);
958 operands[1] = adjust_address (operands[1], BLKmode, 0);
960 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
961 operands[0], operands[1]);
962 operands[0] = SET_DEST (PATTERN (curr_insn));
966 ; (TF|DF|SF|TD|DD|SD) instructions
968 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
969 (define_insn "*cmp<mode>_ccs_0"
970 [(set (reg CC_REGNUM)
971 (compare (match_operand:FP 0 "register_operand" "f")
972 (match_operand:FP 1 "const0_operand" "")))]
973 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
974 "lt<xde><bt>r\t%0,%0"
975 [(set_attr "op_type" "RRE")
976 (set_attr "type" "fsimp<mode>")])
978 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
979 (define_insn "*cmp<mode>_ccs"
980 [(set (reg CC_REGNUM)
981 (compare (match_operand:FP 0 "register_operand" "f,f")
982 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
983 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
987 [(set_attr "op_type" "RRE,RXE")
988 (set_attr "type" "fsimp<mode>")])
991 ; Compare and Branch instructions
993 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
994 ; The following instructions do a complementary access of their second
995 ; operand (z01 only): crj_c, cgrjc, cr, cgr
996 (define_insn "*cmp_and_br_signed_<mode>"
998 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
999 [(match_operand:GPR 1 "register_operand" "d,d")
1000 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1001 (label_ref (match_operand 3 "" ""))
1003 (clobber (reg:CC CC_REGNUM))]
1006 if (get_attr_length (insn) == 6)
1007 return which_alternative ?
1008 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1010 return which_alternative ?
1011 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1013 [(set_attr "op_type" "RIE")
1014 (set_attr "type" "branch")
1015 (set_attr "z10prop" "z10_super_c,z10_super")
1016 (set (attr "length")
1017 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1018 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1019 ; 10 byte for cgr/jg
1021 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1022 ; The following instructions do a complementary access of their second
1023 ; operand (z10 only): clrj, clgrj, clr, clgr
1024 (define_insn "*cmp_and_br_unsigned_<mode>"
1026 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1027 [(match_operand:GPR 1 "register_operand" "d,d")
1028 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1029 (label_ref (match_operand 3 "" ""))
1031 (clobber (reg:CC CC_REGNUM))]
1034 if (get_attr_length (insn) == 6)
1035 return which_alternative ?
1036 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1038 return which_alternative ?
1039 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1041 [(set_attr "op_type" "RIE")
1042 (set_attr "type" "branch")
1043 (set_attr "z10prop" "z10_super_c,z10_super")
1044 (set (attr "length")
1045 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1046 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1047 ; 10 byte for clgr/jg
1050 ;;- Move instructions.
1054 ; movti instruction pattern(s).
1057 (define_insn "movti"
1058 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1059 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1066 [(set_attr "op_type" "RSY,RSY,*,*")
1067 (set_attr "type" "lm,stm,*,*")])
1070 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1071 (match_operand:TI 1 "general_operand" ""))]
1072 "TARGET_64BIT && reload_completed
1073 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1074 [(set (match_dup 2) (match_dup 4))
1075 (set (match_dup 3) (match_dup 5))]
1077 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1078 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1079 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1080 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1084 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1085 (match_operand:TI 1 "general_operand" ""))]
1086 "TARGET_64BIT && reload_completed
1087 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1088 [(set (match_dup 2) (match_dup 4))
1089 (set (match_dup 3) (match_dup 5))]
1091 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1092 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1093 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1094 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1098 [(set (match_operand:TI 0 "register_operand" "")
1099 (match_operand:TI 1 "memory_operand" ""))]
1100 "TARGET_64BIT && reload_completed
1101 && !s_operand (operands[1], VOIDmode)"
1102 [(set (match_dup 0) (match_dup 1))]
1104 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1105 s390_load_address (addr, XEXP (operands[1], 0));
1106 operands[1] = replace_equiv_address (operands[1], addr);
1111 ; Patterns used for secondary reloads
1114 ; z10 provides move instructions accepting larl memory operands.
1115 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1116 ; These patterns are also used for unaligned SI and DI accesses.
1118 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1119 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1120 (match_operand:INTALL 1 "register_operand" "=d")
1121 (match_operand:P 2 "register_operand" "=&a")])]
1124 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1128 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1129 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1130 (match_operand:INTALL 1 "memory_operand" "")
1131 (match_operand:P 2 "register_operand" "=a")])]
1134 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1138 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1139 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1140 (match_operand:FPALL 1 "register_operand" "=d")
1141 (match_operand:P 2 "register_operand" "=&a")])]
1144 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1148 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1149 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1150 (match_operand:FPALL 1 "memory_operand" "")
1151 (match_operand:P 2 "register_operand" "=a")])]
1154 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1158 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1159 [(parallel [(match_operand:P 0 "register_operand" "=d")
1160 (match_operand:P 1 "larl_operand" "")
1161 (match_operand:P 2 "register_operand" "=a")])]
1164 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1168 ; Handles loading a PLUS (load address) expression
1170 (define_expand "reload<mode>_plus"
1171 [(parallel [(match_operand:P 0 "register_operand" "=a")
1172 (match_operand:P 1 "s390_plus_operand" "")
1173 (match_operand:P 2 "register_operand" "=&a")])]
1176 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1180 ; Handles assessing a non-offsetable memory address
1182 (define_expand "reload<mode>_nonoffmem_in"
1183 [(parallel [(match_operand 0 "register_operand" "")
1184 (match_operand 1 "" "")
1185 (match_operand:P 2 "register_operand" "=&a")])]
1188 gcc_assert (MEM_P (operands[1]));
1189 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1190 operands[1] = replace_equiv_address (operands[1], operands[2]);
1191 emit_move_insn (operands[0], operands[1]);
1195 (define_expand "reload<mode>_nonoffmem_out"
1196 [(parallel [(match_operand 0 "" "")
1197 (match_operand 1 "register_operand" "")
1198 (match_operand:P 2 "register_operand" "=&a")])]
1201 gcc_assert (MEM_P (operands[0]));
1202 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1203 operands[0] = replace_equiv_address (operands[0], operands[2]);
1204 emit_move_insn (operands[0], operands[1]);
1208 (define_expand "reload<mode>_PIC_addr"
1209 [(parallel [(match_operand 0 "register_operand" "=d")
1210 (match_operand 1 "larl_operand" "")
1211 (match_operand:P 2 "register_operand" "=a")])]
1214 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1215 emit_move_insn (operands[0], new_rtx);
1219 ; movdi instruction pattern(s).
1222 (define_expand "movdi"
1223 [(set (match_operand:DI 0 "general_operand" "")
1224 (match_operand:DI 1 "general_operand" ""))]
1227 /* Handle symbolic constants. */
1229 && (SYMBOLIC_CONST (operands[1])
1230 || (GET_CODE (operands[1]) == PLUS
1231 && XEXP (operands[1], 0) == pic_offset_table_rtx
1232 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1233 emit_symbolic_move (operands);
1236 (define_insn "*movdi_larl"
1237 [(set (match_operand:DI 0 "register_operand" "=d")
1238 (match_operand:DI 1 "larl_operand" "X"))]
1240 && !FP_REG_P (operands[0])"
1242 [(set_attr "op_type" "RIL")
1243 (set_attr "type" "larl")
1244 (set_attr "z10prop" "z10_super_A1")])
1246 (define_insn "*movdi_64"
1247 [(set (match_operand:DI 0 "nonimmediate_operand"
1248 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1249 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1250 (match_operand:DI 1 "general_operand"
1251 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1252 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1281 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1282 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1283 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1284 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1286 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1287 z10,*,*,*,*,*,longdisp,*,longdisp,
1289 (set_attr "z10prop" "z10_fwd_A1,
1318 [(set (match_operand:DI 0 "register_operand" "")
1319 (match_operand:DI 1 "register_operand" ""))]
1320 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1321 [(set (match_dup 2) (match_dup 3))
1322 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1323 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1324 "operands[2] = gen_lowpart (SImode, operands[0]);
1325 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1328 [(set (match_operand:DI 0 "register_operand" "")
1329 (match_operand:DI 1 "register_operand" ""))]
1330 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1331 && dead_or_set_p (insn, operands[1])"
1332 [(set (match_dup 3) (match_dup 2))
1333 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1334 (set (match_dup 4) (match_dup 2))]
1335 "operands[2] = gen_lowpart (SImode, operands[1]);
1336 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1339 [(set (match_operand:DI 0 "register_operand" "")
1340 (match_operand:DI 1 "register_operand" ""))]
1341 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1342 && !dead_or_set_p (insn, operands[1])"
1343 [(set (match_dup 3) (match_dup 2))
1344 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1345 (set (match_dup 4) (match_dup 2))
1346 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1347 "operands[2] = gen_lowpart (SImode, operands[1]);
1348 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1350 (define_insn "*movdi_31"
1351 [(set (match_operand:DI 0 "nonimmediate_operand"
1352 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1353 (match_operand:DI 1 "general_operand"
1354 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1369 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1370 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1371 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1373 ; For a load from a symbol ref we can use one of the target registers
1374 ; together with larl to load the address.
1376 [(set (match_operand:DI 0 "register_operand" "")
1377 (match_operand:DI 1 "memory_operand" ""))]
1378 "!TARGET_64BIT && reload_completed && TARGET_Z10
1379 && larl_operand (XEXP (operands[1], 0), SImode)"
1380 [(set (match_dup 2) (match_dup 3))
1381 (set (match_dup 0) (match_dup 1))]
1383 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1384 operands[3] = XEXP (operands[1], 0);
1385 operands[1] = replace_equiv_address (operands[1], operands[2]);
1389 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1390 (match_operand:DI 1 "general_operand" ""))]
1391 "!TARGET_64BIT && reload_completed
1392 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1393 [(set (match_dup 2) (match_dup 4))
1394 (set (match_dup 3) (match_dup 5))]
1396 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1397 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1398 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1399 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1403 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1404 (match_operand:DI 1 "general_operand" ""))]
1405 "!TARGET_64BIT && reload_completed
1406 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1407 [(set (match_dup 2) (match_dup 4))
1408 (set (match_dup 3) (match_dup 5))]
1410 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1411 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1412 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1413 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1417 [(set (match_operand:DI 0 "register_operand" "")
1418 (match_operand:DI 1 "memory_operand" ""))]
1419 "!TARGET_64BIT && reload_completed
1420 && !FP_REG_P (operands[0])
1421 && !s_operand (operands[1], VOIDmode)"
1422 [(set (match_dup 0) (match_dup 1))]
1424 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1425 s390_load_address (addr, XEXP (operands[1], 0));
1426 operands[1] = replace_equiv_address (operands[1], addr);
1430 [(set (match_operand:DI 0 "register_operand" "")
1431 (mem:DI (match_operand 1 "address_operand" "")))]
1433 && !FP_REG_P (operands[0])
1434 && GET_CODE (operands[1]) == SYMBOL_REF
1435 && CONSTANT_POOL_ADDRESS_P (operands[1])
1436 && get_pool_mode (operands[1]) == DImode
1437 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1438 [(set (match_dup 0) (match_dup 2))]
1439 "operands[2] = get_pool_constant (operands[1]);")
1441 (define_insn "*la_64"
1442 [(set (match_operand:DI 0 "register_operand" "=d,d")
1443 (match_operand:QI 1 "address_operand" "U,W"))]
1448 [(set_attr "op_type" "RX,RXY")
1449 (set_attr "type" "la")
1450 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1454 [(set (match_operand:DI 0 "register_operand" "")
1455 (match_operand:QI 1 "address_operand" ""))
1456 (clobber (reg:CC CC_REGNUM))])]
1458 && preferred_la_operand_p (operands[1], const0_rtx)"
1459 [(set (match_dup 0) (match_dup 1))]
1463 [(set (match_operand:DI 0 "register_operand" "")
1464 (match_operand:DI 1 "register_operand" ""))
1467 (plus:DI (match_dup 0)
1468 (match_operand:DI 2 "nonmemory_operand" "")))
1469 (clobber (reg:CC CC_REGNUM))])]
1471 && !reg_overlap_mentioned_p (operands[0], operands[2])
1472 && preferred_la_operand_p (operands[1], operands[2])"
1473 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1477 ; movsi instruction pattern(s).
1480 (define_expand "movsi"
1481 [(set (match_operand:SI 0 "general_operand" "")
1482 (match_operand:SI 1 "general_operand" ""))]
1485 /* Handle symbolic constants. */
1487 && (SYMBOLIC_CONST (operands[1])
1488 || (GET_CODE (operands[1]) == PLUS
1489 && XEXP (operands[1], 0) == pic_offset_table_rtx
1490 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1491 emit_symbolic_move (operands);
1494 (define_insn "*movsi_larl"
1495 [(set (match_operand:SI 0 "register_operand" "=d")
1496 (match_operand:SI 1 "larl_operand" "X"))]
1497 "!TARGET_64BIT && TARGET_CPU_ZARCH
1498 && !FP_REG_P (operands[0])"
1500 [(set_attr "op_type" "RIL")
1501 (set_attr "type" "larl")
1502 (set_attr "z10prop" "z10_fwd_A1")])
1504 (define_insn "*movsi_zarch"
1505 [(set (match_operand:SI 0 "nonimmediate_operand"
1506 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1507 (match_operand:SI 1 "general_operand"
1508 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1533 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1534 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1535 (set_attr "type" "*,
1557 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1558 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1559 (set_attr "z10prop" "z10_fwd_A1,
1582 (define_insn "*movsi_esa"
1583 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1584 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1598 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1599 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1600 (set_attr "z10prop" "z10_fwd_A1,
1614 [(set (match_operand:SI 0 "register_operand" "")
1615 (mem:SI (match_operand 1 "address_operand" "")))]
1616 "!FP_REG_P (operands[0])
1617 && GET_CODE (operands[1]) == SYMBOL_REF
1618 && CONSTANT_POOL_ADDRESS_P (operands[1])
1619 && get_pool_mode (operands[1]) == SImode
1620 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1621 [(set (match_dup 0) (match_dup 2))]
1622 "operands[2] = get_pool_constant (operands[1]);")
1624 (define_insn "*la_31"
1625 [(set (match_operand:SI 0 "register_operand" "=d,d")
1626 (match_operand:QI 1 "address_operand" "U,W"))]
1627 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1631 [(set_attr "op_type" "RX,RXY")
1632 (set_attr "type" "la")
1633 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1637 [(set (match_operand:SI 0 "register_operand" "")
1638 (match_operand:QI 1 "address_operand" ""))
1639 (clobber (reg:CC CC_REGNUM))])]
1641 && preferred_la_operand_p (operands[1], const0_rtx)"
1642 [(set (match_dup 0) (match_dup 1))]
1646 [(set (match_operand:SI 0 "register_operand" "")
1647 (match_operand:SI 1 "register_operand" ""))
1650 (plus:SI (match_dup 0)
1651 (match_operand:SI 2 "nonmemory_operand" "")))
1652 (clobber (reg:CC CC_REGNUM))])]
1654 && !reg_overlap_mentioned_p (operands[0], operands[2])
1655 && preferred_la_operand_p (operands[1], operands[2])"
1656 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1659 (define_insn "*la_31_and"
1660 [(set (match_operand:SI 0 "register_operand" "=d,d")
1661 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1662 (const_int 2147483647)))]
1667 [(set_attr "op_type" "RX,RXY")
1668 (set_attr "type" "la")
1669 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1671 (define_insn_and_split "*la_31_and_cc"
1672 [(set (match_operand:SI 0 "register_operand" "=d")
1673 (and:SI (match_operand:QI 1 "address_operand" "p")
1674 (const_int 2147483647)))
1675 (clobber (reg:CC CC_REGNUM))]
1678 "&& reload_completed"
1680 (and:SI (match_dup 1) (const_int 2147483647)))]
1682 [(set_attr "op_type" "RX")
1683 (set_attr "type" "la")])
1685 (define_insn "force_la_31"
1686 [(set (match_operand:SI 0 "register_operand" "=d,d")
1687 (match_operand:QI 1 "address_operand" "U,W"))
1688 (use (const_int 0))]
1693 [(set_attr "op_type" "RX")
1694 (set_attr "type" "la")
1695 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1698 ; movhi instruction pattern(s).
1701 (define_expand "movhi"
1702 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1703 (match_operand:HI 1 "general_operand" ""))]
1706 /* Make it explicit that loading a register from memory
1707 always sign-extends (at least) to SImode. */
1708 if (optimize && can_create_pseudo_p ()
1709 && register_operand (operands[0], VOIDmode)
1710 && GET_CODE (operands[1]) == MEM)
1712 rtx tmp = gen_reg_rtx (SImode);
1713 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1714 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1715 operands[1] = gen_lowpart (HImode, tmp);
1719 (define_insn "*movhi"
1720 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1721 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1733 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1734 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1735 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1736 (set_attr "z10prop" "z10_fr_E1,
1747 [(set (match_operand:HI 0 "register_operand" "")
1748 (mem:HI (match_operand 1 "address_operand" "")))]
1749 "GET_CODE (operands[1]) == SYMBOL_REF
1750 && CONSTANT_POOL_ADDRESS_P (operands[1])
1751 && get_pool_mode (operands[1]) == HImode
1752 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1753 [(set (match_dup 0) (match_dup 2))]
1754 "operands[2] = get_pool_constant (operands[1]);")
1757 ; movqi instruction pattern(s).
1760 (define_expand "movqi"
1761 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1762 (match_operand:QI 1 "general_operand" ""))]
1765 /* On z/Architecture, zero-extending from memory to register
1766 is just as fast as a QImode load. */
1767 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1768 && register_operand (operands[0], VOIDmode)
1769 && GET_CODE (operands[1]) == MEM)
1771 rtx tmp = gen_reg_rtx (word_mode);
1772 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1773 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1774 operands[1] = gen_lowpart (QImode, tmp);
1778 (define_insn "*movqi"
1779 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
1780 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
1791 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
1792 (set_attr "type" "lr,*,*,*,store,store,store,store")
1793 (set_attr "z10prop" "z10_fr_E1,
1803 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1804 (mem:QI (match_operand 1 "address_operand" "")))]
1805 "GET_CODE (operands[1]) == SYMBOL_REF
1806 && CONSTANT_POOL_ADDRESS_P (operands[1])
1807 && get_pool_mode (operands[1]) == QImode
1808 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1809 [(set (match_dup 0) (match_dup 2))]
1810 "operands[2] = get_pool_constant (operands[1]);")
1813 ; movstrictqi instruction pattern(s).
1816 (define_insn "*movstrictqi"
1817 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1818 (match_operand:QI 1 "memory_operand" "R,T"))]
1823 [(set_attr "op_type" "RX,RXY")
1824 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1827 ; movstricthi instruction pattern(s).
1830 (define_insn "*movstricthi"
1831 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1832 (match_operand:HI 1 "memory_operand" "Q,S"))
1833 (clobber (reg:CC CC_REGNUM))]
1838 [(set_attr "op_type" "RS,RSY")
1839 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1842 ; movstrictsi instruction pattern(s).
1845 (define_insn "movstrictsi"
1846 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1847 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1854 [(set_attr "op_type" "RR,RX,RXY,RRE")
1855 (set_attr "type" "lr,load,load,*")
1856 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1859 ; mov(tf|td) instruction pattern(s).
1862 (define_expand "mov<mode>"
1863 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1864 (match_operand:TD_TF 1 "general_operand" ""))]
1868 (define_insn "*mov<mode>_64"
1869 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1870 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1881 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1882 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")])
1884 (define_insn "*mov<mode>_31"
1885 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1886 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1893 [(set_attr "op_type" "RRE,RRE,*,*")
1894 (set_attr "type" "fsimptf,fsimptf,*,*")])
1896 ; TFmode in GPRs splitters
1899 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1900 (match_operand:TD_TF 1 "general_operand" ""))]
1901 "TARGET_64BIT && reload_completed
1902 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1903 [(set (match_dup 2) (match_dup 4))
1904 (set (match_dup 3) (match_dup 5))]
1906 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1907 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1908 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1909 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1913 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1914 (match_operand:TD_TF 1 "general_operand" ""))]
1915 "TARGET_64BIT && reload_completed
1916 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1917 [(set (match_dup 2) (match_dup 4))
1918 (set (match_dup 3) (match_dup 5))]
1920 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1921 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1922 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1923 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1927 [(set (match_operand:TD_TF 0 "register_operand" "")
1928 (match_operand:TD_TF 1 "memory_operand" ""))]
1929 "TARGET_64BIT && reload_completed
1930 && !FP_REG_P (operands[0])
1931 && !s_operand (operands[1], VOIDmode)"
1932 [(set (match_dup 0) (match_dup 1))]
1934 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1935 s390_load_address (addr, XEXP (operands[1], 0));
1936 operands[1] = replace_equiv_address (operands[1], addr);
1939 ; TFmode in BFPs splitters
1942 [(set (match_operand:TD_TF 0 "register_operand" "")
1943 (match_operand:TD_TF 1 "memory_operand" ""))]
1944 "reload_completed && offsettable_memref_p (operands[1])
1945 && FP_REG_P (operands[0])"
1946 [(set (match_dup 2) (match_dup 4))
1947 (set (match_dup 3) (match_dup 5))]
1949 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1951 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1953 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
1954 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
1958 [(set (match_operand:TD_TF 0 "memory_operand" "")
1959 (match_operand:TD_TF 1 "register_operand" ""))]
1960 "reload_completed && offsettable_memref_p (operands[0])
1961 && FP_REG_P (operands[1])"
1962 [(set (match_dup 2) (match_dup 4))
1963 (set (match_dup 3) (match_dup 5))]
1965 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
1966 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
1967 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1969 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1974 ; mov(df|dd) instruction pattern(s).
1977 (define_expand "mov<mode>"
1978 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1979 (match_operand:DD_DF 1 "general_operand" ""))]
1983 (define_insn "*mov<mode>_64dfp"
1984 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
1985 "=f,f,f,d,f,f,R,T,d, d,RT")
1986 (match_operand:DD_DF 1 "general_operand"
1987 " G,f,d,f,R,T,f,f,d,RT, d"))]
1988 "TARGET_64BIT && TARGET_DFP"
2001 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2002 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2003 fstoredf,fstoredf,lr,load,store")
2004 (set_attr "z10prop" "*,
2017 (define_insn "*mov<mode>_64"
2018 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2019 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2031 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2032 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2033 fstore<mode>,fstore<mode>,lr,load,store")
2034 (set_attr "z10prop" "*,
2044 (define_insn "*mov<mode>_31"
2045 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2046 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2047 (match_operand:DD_DF 1 "general_operand"
2048 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2063 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2064 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2065 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2068 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2069 (match_operand:DD_DF 1 "general_operand" ""))]
2070 "!TARGET_64BIT && reload_completed
2071 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2072 [(set (match_dup 2) (match_dup 4))
2073 (set (match_dup 3) (match_dup 5))]
2075 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2076 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2077 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2078 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2082 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2083 (match_operand:DD_DF 1 "general_operand" ""))]
2084 "!TARGET_64BIT && reload_completed
2085 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2086 [(set (match_dup 2) (match_dup 4))
2087 (set (match_dup 3) (match_dup 5))]
2089 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2090 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2091 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2092 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2096 [(set (match_operand:DD_DF 0 "register_operand" "")
2097 (match_operand:DD_DF 1 "memory_operand" ""))]
2098 "!TARGET_64BIT && reload_completed
2099 && !FP_REG_P (operands[0])
2100 && !s_operand (operands[1], VOIDmode)"
2101 [(set (match_dup 0) (match_dup 1))]
2103 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2104 s390_load_address (addr, XEXP (operands[1], 0));
2105 operands[1] = replace_equiv_address (operands[1], addr);
2109 ; mov(sf|sd) instruction pattern(s).
2112 (define_insn "mov<mode>"
2113 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2114 "=f,f,f,f,R,T,d,d,d,R,T")
2115 (match_operand:SD_SF 1 "general_operand"
2116 " G,f,R,T,f,f,d,R,T,d,d"))]
2130 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2131 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2132 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2133 (set_attr "z10prop" "*,
2146 ; movcc instruction pattern
2149 (define_insn "movcc"
2150 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2151 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2161 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2162 (set_attr "type" "lr,*,*,store,store,load,load")
2163 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2166 ; Block move (MVC) patterns.
2170 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2171 (match_operand:BLK 1 "memory_operand" "Q"))
2172 (use (match_operand 2 "const_int_operand" "n"))]
2173 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2174 "mvc\t%O0(%2,%R0),%S1"
2175 [(set_attr "op_type" "SS")])
2179 [(set (match_operand:BLK 0 "memory_operand" "")
2180 (match_operand:BLK 1 "memory_operand" ""))
2181 (use (match_operand 2 "const_int_operand" ""))])
2183 [(set (match_operand:BLK 3 "memory_operand" "")
2184 (match_operand:BLK 4 "memory_operand" ""))
2185 (use (match_operand 5 "const_int_operand" ""))])]
2186 "s390_offset_p (operands[0], operands[3], operands[2])
2187 && s390_offset_p (operands[1], operands[4], operands[2])
2188 && !s390_overlap_p (operands[0], operands[1],
2189 INTVAL (operands[2]) + INTVAL (operands[5]))
2190 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2192 [(set (match_dup 6) (match_dup 7))
2193 (use (match_dup 8))])]
2194 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2195 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2196 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2200 ; load_multiple pattern(s).
2202 ; ??? Due to reload problems with replacing registers inside match_parallel
2203 ; we currently support load_multiple/store_multiple only after reload.
2206 (define_expand "load_multiple"
2207 [(match_par_dup 3 [(set (match_operand 0 "" "")
2208 (match_operand 1 "" ""))
2209 (use (match_operand 2 "" ""))])]
2212 enum machine_mode mode;
2218 /* Support only loading a constant number of fixed-point registers from
2219 memory and only bother with this if more than two */
2220 if (GET_CODE (operands[2]) != CONST_INT
2221 || INTVAL (operands[2]) < 2
2222 || INTVAL (operands[2]) > 16
2223 || GET_CODE (operands[1]) != MEM
2224 || GET_CODE (operands[0]) != REG
2225 || REGNO (operands[0]) >= 16)
2228 count = INTVAL (operands[2]);
2229 regno = REGNO (operands[0]);
2230 mode = GET_MODE (operands[0]);
2231 if (mode != SImode && mode != word_mode)
2234 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2235 if (!can_create_pseudo_p ())
2237 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2239 from = XEXP (operands[1], 0);
2242 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2243 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2244 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2246 from = XEXP (XEXP (operands[1], 0), 0);
2247 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2254 from = force_reg (Pmode, XEXP (operands[1], 0));
2258 for (i = 0; i < count; i++)
2259 XVECEXP (operands[3], 0, i)
2260 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2261 change_address (operands[1], mode,
2262 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2265 (define_insn "*load_multiple_di"
2266 [(match_parallel 0 "load_multiple_operation"
2267 [(set (match_operand:DI 1 "register_operand" "=r")
2268 (match_operand:DI 2 "s_operand" "QS"))])]
2269 "reload_completed && word_mode == DImode"
2271 int words = XVECLEN (operands[0], 0);
2272 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2273 return "lmg\t%1,%0,%S2";
2275 [(set_attr "op_type" "RSY")
2276 (set_attr "type" "lm")])
2278 (define_insn "*load_multiple_si"
2279 [(match_parallel 0 "load_multiple_operation"
2280 [(set (match_operand:SI 1 "register_operand" "=r,r")
2281 (match_operand:SI 2 "s_operand" "Q,S"))])]
2284 int words = XVECLEN (operands[0], 0);
2285 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2286 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2288 [(set_attr "op_type" "RS,RSY")
2289 (set_attr "type" "lm")])
2292 ; store multiple pattern(s).
2295 (define_expand "store_multiple"
2296 [(match_par_dup 3 [(set (match_operand 0 "" "")
2297 (match_operand 1 "" ""))
2298 (use (match_operand 2 "" ""))])]
2301 enum machine_mode mode;
2307 /* Support only storing a constant number of fixed-point registers to
2308 memory and only bother with this if more than two. */
2309 if (GET_CODE (operands[2]) != CONST_INT
2310 || INTVAL (operands[2]) < 2
2311 || INTVAL (operands[2]) > 16
2312 || GET_CODE (operands[0]) != MEM
2313 || GET_CODE (operands[1]) != REG
2314 || REGNO (operands[1]) >= 16)
2317 count = INTVAL (operands[2]);
2318 regno = REGNO (operands[1]);
2319 mode = GET_MODE (operands[1]);
2320 if (mode != SImode && mode != word_mode)
2323 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2325 if (!can_create_pseudo_p ())
2327 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2329 to = XEXP (operands[0], 0);
2332 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2333 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2334 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2336 to = XEXP (XEXP (operands[0], 0), 0);
2337 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2344 to = force_reg (Pmode, XEXP (operands[0], 0));
2348 for (i = 0; i < count; i++)
2349 XVECEXP (operands[3], 0, i)
2350 = gen_rtx_SET (VOIDmode,
2351 change_address (operands[0], mode,
2352 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2353 gen_rtx_REG (mode, regno + i));
2356 (define_insn "*store_multiple_di"
2357 [(match_parallel 0 "store_multiple_operation"
2358 [(set (match_operand:DI 1 "s_operand" "=QS")
2359 (match_operand:DI 2 "register_operand" "r"))])]
2360 "reload_completed && word_mode == DImode"
2362 int words = XVECLEN (operands[0], 0);
2363 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2364 return "stmg\t%2,%0,%S1";
2366 [(set_attr "op_type" "RSY")
2367 (set_attr "type" "stm")])
2370 (define_insn "*store_multiple_si"
2371 [(match_parallel 0 "store_multiple_operation"
2372 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2373 (match_operand:SI 2 "register_operand" "r,r"))])]
2376 int words = XVECLEN (operands[0], 0);
2377 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2378 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2380 [(set_attr "op_type" "RS,RSY")
2381 (set_attr "type" "stm")])
2384 ;; String instructions.
2387 (define_insn "*execute_rl"
2388 [(match_parallel 0 ""
2389 [(unspec [(match_operand 1 "register_operand" "a")
2390 (match_operand 2 "" "")
2391 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2392 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2393 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2395 [(set_attr "op_type" "RIL")
2396 (set_attr "type" "cs")])
2398 (define_insn "*execute"
2399 [(match_parallel 0 ""
2400 [(unspec [(match_operand 1 "register_operand" "a")
2401 (match_operand:BLK 2 "memory_operand" "R")
2402 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2403 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2404 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2406 [(set_attr "op_type" "RX")
2407 (set_attr "type" "cs")])
2411 ; strlenM instruction pattern(s).
2414 (define_expand "strlen<mode>"
2415 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2418 (unspec:P [(const_int 0)
2419 (match_operand:BLK 1 "memory_operand" "")
2421 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2422 (clobber (scratch:P))
2423 (clobber (reg:CC CC_REGNUM))])
2425 [(set (match_operand:P 0 "register_operand" "")
2426 (minus:P (match_dup 4) (match_dup 5)))
2427 (clobber (reg:CC CC_REGNUM))])]
2430 operands[4] = gen_reg_rtx (Pmode);
2431 operands[5] = gen_reg_rtx (Pmode);
2432 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2433 operands[1] = replace_equiv_address (operands[1], operands[5]);
2436 (define_insn "*strlen<mode>"
2437 [(set (match_operand:P 0 "register_operand" "=a")
2438 (unspec:P [(match_operand:P 2 "general_operand" "0")
2439 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2441 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2442 (clobber (match_scratch:P 1 "=a"))
2443 (clobber (reg:CC CC_REGNUM))]
2445 "srst\t%0,%1\;jo\t.-4"
2446 [(set_attr "length" "8")
2447 (set_attr "type" "vs")])
2450 ; cmpstrM instruction pattern(s).
2453 (define_expand "cmpstrsi"
2454 [(set (reg:SI 0) (const_int 0))
2456 [(clobber (match_operand 3 "" ""))
2457 (clobber (match_dup 4))
2458 (set (reg:CCU CC_REGNUM)
2459 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2460 (match_operand:BLK 2 "memory_operand" "")))
2463 [(set (match_operand:SI 0 "register_operand" "=d")
2464 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2465 (clobber (reg:CC CC_REGNUM))])]
2468 /* As the result of CMPINT is inverted compared to what we need,
2469 we have to swap the operands. */
2470 rtx op1 = operands[2];
2471 rtx op2 = operands[1];
2472 rtx addr1 = gen_reg_rtx (Pmode);
2473 rtx addr2 = gen_reg_rtx (Pmode);
2475 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2476 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2477 operands[1] = replace_equiv_address_nv (op1, addr1);
2478 operands[2] = replace_equiv_address_nv (op2, addr2);
2479 operands[3] = addr1;
2480 operands[4] = addr2;
2483 (define_insn "*cmpstr<mode>"
2484 [(clobber (match_operand:P 0 "register_operand" "=d"))
2485 (clobber (match_operand:P 1 "register_operand" "=d"))
2486 (set (reg:CCU CC_REGNUM)
2487 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2488 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2491 "clst\t%0,%1\;jo\t.-4"
2492 [(set_attr "length" "8")
2493 (set_attr "type" "vs")])
2496 ; movstr instruction pattern.
2499 (define_expand "movstr"
2500 [(set (reg:SI 0) (const_int 0))
2502 [(clobber (match_dup 3))
2503 (set (match_operand:BLK 1 "memory_operand" "")
2504 (match_operand:BLK 2 "memory_operand" ""))
2505 (set (match_operand 0 "register_operand" "")
2506 (unspec [(match_dup 1)
2508 (reg:SI 0)] UNSPEC_MVST))
2509 (clobber (reg:CC CC_REGNUM))])]
2512 rtx addr1 = gen_reg_rtx (Pmode);
2513 rtx addr2 = gen_reg_rtx (Pmode);
2515 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2516 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2517 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2518 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2519 operands[3] = addr2;
2522 (define_insn "*movstr"
2523 [(clobber (match_operand:P 2 "register_operand" "=d"))
2524 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2525 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2526 (set (match_operand:P 0 "register_operand" "=d")
2527 (unspec [(mem:BLK (match_dup 1))
2528 (mem:BLK (match_dup 3))
2529 (reg:SI 0)] UNSPEC_MVST))
2530 (clobber (reg:CC CC_REGNUM))]
2532 "mvst\t%1,%2\;jo\t.-4"
2533 [(set_attr "length" "8")
2534 (set_attr "type" "vs")])
2538 ; movmemM instruction pattern(s).
2541 (define_expand "movmem<mode>"
2542 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2543 (match_operand:BLK 1 "memory_operand" "")) ; source
2544 (use (match_operand:GPR 2 "general_operand" "")) ; count
2545 (match_operand 3 "" "")]
2547 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2549 ; Move a block that is up to 256 bytes in length.
2550 ; The block length is taken as (operands[2] % 256) + 1.
2552 (define_expand "movmem_short"
2554 [(set (match_operand:BLK 0 "memory_operand" "")
2555 (match_operand:BLK 1 "memory_operand" ""))
2556 (use (match_operand 2 "nonmemory_operand" ""))
2557 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2558 (clobber (match_dup 3))])]
2560 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2562 (define_insn "*movmem_short"
2563 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2564 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2565 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2566 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2567 (clobber (match_scratch 4 "=X,X,X,&a"))]
2568 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2569 && GET_MODE (operands[4]) == Pmode"
2571 [(set_attr "type" "cs")
2572 (set_attr "cpu_facility" "*,*,z10,*")])
2575 [(set (match_operand:BLK 0 "memory_operand" "")
2576 (match_operand:BLK 1 "memory_operand" ""))
2577 (use (match_operand 2 "const_int_operand" ""))
2578 (use (match_operand 3 "immediate_operand" ""))
2579 (clobber (scratch))]
2582 [(set (match_dup 0) (match_dup 1))
2583 (use (match_dup 2))])]
2584 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2587 [(set (match_operand:BLK 0 "memory_operand" "")
2588 (match_operand:BLK 1 "memory_operand" ""))
2589 (use (match_operand 2 "register_operand" ""))
2590 (use (match_operand 3 "memory_operand" ""))
2591 (clobber (scratch))]
2594 [(unspec [(match_dup 2) (match_dup 3)
2595 (const_int 0)] UNSPEC_EXECUTE)
2596 (set (match_dup 0) (match_dup 1))
2597 (use (const_int 1))])]
2601 [(set (match_operand:BLK 0 "memory_operand" "")
2602 (match_operand:BLK 1 "memory_operand" ""))
2603 (use (match_operand 2 "register_operand" ""))
2604 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2605 (clobber (scratch))]
2606 "TARGET_Z10 && reload_completed"
2608 [(unspec [(match_dup 2) (const_int 0)
2609 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2610 (set (match_dup 0) (match_dup 1))
2611 (use (const_int 1))])]
2612 "operands[3] = gen_label_rtx ();")
2615 [(set (match_operand:BLK 0 "memory_operand" "")
2616 (match_operand:BLK 1 "memory_operand" ""))
2617 (use (match_operand 2 "register_operand" ""))
2618 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2619 (clobber (match_operand 3 "register_operand" ""))]
2620 "reload_completed && TARGET_CPU_ZARCH"
2621 [(set (match_dup 3) (label_ref (match_dup 4)))
2623 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2624 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2625 (set (match_dup 0) (match_dup 1))
2626 (use (const_int 1))])]
2627 "operands[4] = gen_label_rtx ();")
2629 ; Move a block of arbitrary length.
2631 (define_expand "movmem_long"
2633 [(clobber (match_dup 2))
2634 (clobber (match_dup 3))
2635 (set (match_operand:BLK 0 "memory_operand" "")
2636 (match_operand:BLK 1 "memory_operand" ""))
2637 (use (match_operand 2 "general_operand" ""))
2639 (clobber (reg:CC CC_REGNUM))])]
2642 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2643 rtx reg0 = gen_reg_rtx (dword_mode);
2644 rtx reg1 = gen_reg_rtx (dword_mode);
2645 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2646 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2647 rtx len0 = gen_lowpart (Pmode, reg0);
2648 rtx len1 = gen_lowpart (Pmode, reg1);
2650 emit_clobber (reg0);
2651 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2652 emit_move_insn (len0, operands[2]);
2654 emit_clobber (reg1);
2655 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2656 emit_move_insn (len1, operands[2]);
2658 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2659 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2664 (define_insn "*movmem_long"
2665 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2666 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2667 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2668 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2671 (clobber (reg:CC CC_REGNUM))]
2673 "mvcle\t%0,%1,0\;jo\t.-4"
2674 [(set_attr "length" "8")
2675 (set_attr "type" "vs")])
2682 (define_expand "signbit<mode>2"
2683 [(set (reg:CCZ CC_REGNUM)
2684 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2687 (set (match_operand:SI 0 "register_operand" "=d")
2688 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2691 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2694 (define_expand "isinf<mode>2"
2695 [(set (reg:CCZ CC_REGNUM)
2696 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2699 (set (match_operand:SI 0 "register_operand" "=d")
2700 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2703 operands[2] = GEN_INT (S390_TDC_INFINITY);
2706 ; This insn is used to generate all variants of the Test Data Class
2707 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2708 ; is the register to be tested and the second one is the bit mask
2709 ; specifying the required test(s).
2711 (define_insn "*TDC_insn_<mode>"
2712 [(set (reg:CCZ CC_REGNUM)
2713 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2714 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2716 "t<_d>c<xde><bt>\t%0,%1"
2717 [(set_attr "op_type" "RXE")
2718 (set_attr "type" "fsimp<mode>")])
2720 (define_insn_and_split "*ccz_to_int"
2721 [(set (match_operand:SI 0 "register_operand" "=d")
2722 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2723 UNSPEC_CCZ_TO_INT))]
2727 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2731 ; setmemM instruction pattern(s).
2734 (define_expand "setmem<mode>"
2735 [(set (match_operand:BLK 0 "memory_operand" "")
2736 (match_operand:QI 2 "general_operand" ""))
2737 (use (match_operand:GPR 1 "general_operand" ""))
2738 (match_operand 3 "" "")]
2740 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2742 ; Clear a block that is up to 256 bytes in length.
2743 ; The block length is taken as (operands[1] % 256) + 1.
2745 (define_expand "clrmem_short"
2747 [(set (match_operand:BLK 0 "memory_operand" "")
2749 (use (match_operand 1 "nonmemory_operand" ""))
2750 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2751 (clobber (match_dup 2))
2752 (clobber (reg:CC CC_REGNUM))])]
2754 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2756 (define_insn "*clrmem_short"
2757 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2759 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2760 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2761 (clobber (match_scratch 3 "=X,X,X,&a"))
2762 (clobber (reg:CC CC_REGNUM))]
2763 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2764 && GET_MODE (operands[3]) == Pmode"
2766 [(set_attr "type" "cs")
2767 (set_attr "cpu_facility" "*,*,z10,*")])
2770 [(set (match_operand:BLK 0 "memory_operand" "")
2772 (use (match_operand 1 "const_int_operand" ""))
2773 (use (match_operand 2 "immediate_operand" ""))
2775 (clobber (reg:CC CC_REGNUM))]
2778 [(set (match_dup 0) (const_int 0))
2780 (clobber (reg:CC CC_REGNUM))])]
2781 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2784 [(set (match_operand:BLK 0 "memory_operand" "")
2786 (use (match_operand 1 "register_operand" ""))
2787 (use (match_operand 2 "memory_operand" ""))
2789 (clobber (reg:CC CC_REGNUM))]
2792 [(unspec [(match_dup 1) (match_dup 2)
2793 (const_int 0)] UNSPEC_EXECUTE)
2794 (set (match_dup 0) (const_int 0))
2796 (clobber (reg:CC CC_REGNUM))])]
2800 [(set (match_operand:BLK 0 "memory_operand" "")
2802 (use (match_operand 1 "register_operand" ""))
2803 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2805 (clobber (reg:CC CC_REGNUM))]
2806 "TARGET_Z10 && reload_completed"
2808 [(unspec [(match_dup 1) (const_int 0)
2809 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2810 (set (match_dup 0) (const_int 0))
2812 (clobber (reg:CC CC_REGNUM))])]
2813 "operands[3] = gen_label_rtx ();")
2816 [(set (match_operand:BLK 0 "memory_operand" "")
2818 (use (match_operand 1 "register_operand" ""))
2819 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2820 (clobber (match_operand 2 "register_operand" ""))
2821 (clobber (reg:CC CC_REGNUM))]
2822 "reload_completed && TARGET_CPU_ZARCH"
2823 [(set (match_dup 2) (label_ref (match_dup 3)))
2825 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2826 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2827 (set (match_dup 0) (const_int 0))
2829 (clobber (reg:CC CC_REGNUM))])]
2830 "operands[3] = gen_label_rtx ();")
2832 ; Initialize a block of arbitrary length with (operands[2] % 256).
2834 (define_expand "setmem_long"
2836 [(clobber (match_dup 1))
2837 (set (match_operand:BLK 0 "memory_operand" "")
2838 (match_operand 2 "shift_count_or_setmem_operand" ""))
2839 (use (match_operand 1 "general_operand" ""))
2841 (clobber (reg:CC CC_REGNUM))])]
2844 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2845 rtx reg0 = gen_reg_rtx (dword_mode);
2846 rtx reg1 = gen_reg_rtx (dword_mode);
2847 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2848 rtx len0 = gen_lowpart (Pmode, reg0);
2850 emit_clobber (reg0);
2851 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2852 emit_move_insn (len0, operands[1]);
2854 emit_move_insn (reg1, const0_rtx);
2856 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2861 (define_insn "*setmem_long"
2862 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2863 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2864 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2866 (use (match_operand:<DBL> 1 "register_operand" "d"))
2867 (clobber (reg:CC CC_REGNUM))]
2869 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2870 [(set_attr "length" "8")
2871 (set_attr "type" "vs")])
2873 (define_insn "*setmem_long_and"
2874 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2875 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2876 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2877 (match_operand 4 "const_int_operand" "n")))
2879 (use (match_operand:<DBL> 1 "register_operand" "d"))
2880 (clobber (reg:CC CC_REGNUM))]
2881 "(INTVAL (operands[4]) & 255) == 255"
2882 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2883 [(set_attr "length" "8")
2884 (set_attr "type" "vs")])
2886 ; cmpmemM instruction pattern(s).
2889 (define_expand "cmpmemsi"
2890 [(set (match_operand:SI 0 "register_operand" "")
2891 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2892 (match_operand:BLK 2 "memory_operand" "") ) )
2893 (use (match_operand:SI 3 "general_operand" ""))
2894 (use (match_operand:SI 4 "" ""))]
2896 "s390_expand_cmpmem (operands[0], operands[1],
2897 operands[2], operands[3]); DONE;")
2899 ; Compare a block that is up to 256 bytes in length.
2900 ; The block length is taken as (operands[2] % 256) + 1.
2902 (define_expand "cmpmem_short"
2904 [(set (reg:CCU CC_REGNUM)
2905 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2906 (match_operand:BLK 1 "memory_operand" "")))
2907 (use (match_operand 2 "nonmemory_operand" ""))
2908 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2909 (clobber (match_dup 3))])]
2911 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2913 (define_insn "*cmpmem_short"
2914 [(set (reg:CCU CC_REGNUM)
2915 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2916 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2917 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2918 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2919 (clobber (match_scratch 4 "=X,X,X,&a"))]
2920 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2921 && GET_MODE (operands[4]) == Pmode"
2923 [(set_attr "type" "cs")
2924 (set_attr "cpu_facility" "*,*,z10,*")])
2927 [(set (reg:CCU CC_REGNUM)
2928 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2929 (match_operand:BLK 1 "memory_operand" "")))
2930 (use (match_operand 2 "const_int_operand" ""))
2931 (use (match_operand 3 "immediate_operand" ""))
2932 (clobber (scratch))]
2935 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2936 (use (match_dup 2))])]
2937 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2940 [(set (reg:CCU CC_REGNUM)
2941 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2942 (match_operand:BLK 1 "memory_operand" "")))
2943 (use (match_operand 2 "register_operand" ""))
2944 (use (match_operand 3 "memory_operand" ""))
2945 (clobber (scratch))]
2948 [(unspec [(match_dup 2) (match_dup 3)
2949 (const_int 0)] UNSPEC_EXECUTE)
2950 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2951 (use (const_int 1))])]
2955 [(set (reg:CCU CC_REGNUM)
2956 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2957 (match_operand:BLK 1 "memory_operand" "")))
2958 (use (match_operand 2 "register_operand" ""))
2959 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2960 (clobber (scratch))]
2961 "TARGET_Z10 && reload_completed"
2963 [(unspec [(match_dup 2) (const_int 0)
2964 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2965 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2966 (use (const_int 1))])]
2967 "operands[4] = gen_label_rtx ();")
2970 [(set (reg:CCU CC_REGNUM)
2971 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2972 (match_operand:BLK 1 "memory_operand" "")))
2973 (use (match_operand 2 "register_operand" ""))
2974 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2975 (clobber (match_operand 3 "register_operand" ""))]
2976 "reload_completed && TARGET_CPU_ZARCH"
2977 [(set (match_dup 3) (label_ref (match_dup 4)))
2979 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2980 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2981 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2982 (use (const_int 1))])]
2983 "operands[4] = gen_label_rtx ();")
2985 ; Compare a block of arbitrary length.
2987 (define_expand "cmpmem_long"
2989 [(clobber (match_dup 2))
2990 (clobber (match_dup 3))
2991 (set (reg:CCU CC_REGNUM)
2992 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2993 (match_operand:BLK 1 "memory_operand" "")))
2994 (use (match_operand 2 "general_operand" ""))
2995 (use (match_dup 3))])]
2998 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2999 rtx reg0 = gen_reg_rtx (dword_mode);
3000 rtx reg1 = gen_reg_rtx (dword_mode);
3001 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
3002 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
3003 rtx len0 = gen_lowpart (Pmode, reg0);
3004 rtx len1 = gen_lowpart (Pmode, reg1);
3006 emit_clobber (reg0);
3007 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3008 emit_move_insn (len0, operands[2]);
3010 emit_clobber (reg1);
3011 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3012 emit_move_insn (len1, operands[2]);
3014 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3015 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3020 (define_insn "*cmpmem_long"
3021 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3022 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3023 (set (reg:CCU CC_REGNUM)
3024 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3025 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3027 (use (match_dup 3))]
3029 "clcle\t%0,%1,0\;jo\t.-4"
3030 [(set_attr "length" "8")
3031 (set_attr "type" "vs")])
3033 ; Convert CCUmode condition code to integer.
3034 ; Result is zero if EQ, positive if LTU, negative if GTU.
3036 (define_insn_and_split "cmpint"
3037 [(set (match_operand:SI 0 "register_operand" "=d")
3038 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3040 (clobber (reg:CC CC_REGNUM))]
3044 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3046 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3047 (clobber (reg:CC CC_REGNUM))])])
3049 (define_insn_and_split "*cmpint_cc"
3050 [(set (reg CC_REGNUM)
3051 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3054 (set (match_operand:SI 0 "register_operand" "=d")
3055 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3056 "s390_match_ccmode (insn, CCSmode)"
3058 "&& reload_completed"
3059 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3061 [(set (match_dup 2) (match_dup 3))
3062 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3064 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3065 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3066 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3069 (define_insn_and_split "*cmpint_sign"
3070 [(set (match_operand:DI 0 "register_operand" "=d")
3071 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3072 UNSPEC_CCU_TO_INT)))
3073 (clobber (reg:CC CC_REGNUM))]
3076 "&& reload_completed"
3077 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3079 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3080 (clobber (reg:CC CC_REGNUM))])])
3082 (define_insn_and_split "*cmpint_sign_cc"
3083 [(set (reg CC_REGNUM)
3084 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3085 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3086 UNSPEC_CCU_TO_INT) 0)
3087 (const_int 32)) (const_int 32))
3089 (set (match_operand:DI 0 "register_operand" "=d")
3090 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3091 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
3093 "&& reload_completed"
3094 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3096 [(set (match_dup 2) (match_dup 3))
3097 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3099 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3100 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3101 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3106 ;;- Conversion instructions.
3109 (define_insn "*sethighpartsi"
3110 [(set (match_operand:SI 0 "register_operand" "=d,d")
3111 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3112 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3113 (clobber (reg:CC CC_REGNUM))]
3118 [(set_attr "op_type" "RS,RSY")
3119 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3121 (define_insn "*sethighpartdi_64"
3122 [(set (match_operand:DI 0 "register_operand" "=d")
3123 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3124 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3125 (clobber (reg:CC CC_REGNUM))]
3128 [(set_attr "op_type" "RSY")
3129 (set_attr "z10prop" "z10_super")])
3131 (define_insn "*sethighpartdi_31"
3132 [(set (match_operand:DI 0 "register_operand" "=d,d")
3133 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3134 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3135 (clobber (reg:CC CC_REGNUM))]
3140 [(set_attr "op_type" "RS,RSY")
3141 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3144 (define_insn_and_split "*extzv<mode>"
3145 [(set (match_operand:GPR 0 "register_operand" "=d")
3146 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3147 (match_operand 2 "const_int_operand" "n")
3149 (clobber (reg:CC CC_REGNUM))]
3150 "INTVAL (operands[2]) > 0
3151 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3153 "&& reload_completed"
3155 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3156 (clobber (reg:CC CC_REGNUM))])
3157 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3159 int bitsize = INTVAL (operands[2]);
3160 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3161 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3163 operands[1] = adjust_address (operands[1], BLKmode, 0);
3164 set_mem_size (operands[1], GEN_INT (size));
3165 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3166 operands[3] = GEN_INT (mask);
3169 (define_insn_and_split "*extv<mode>"
3170 [(set (match_operand:GPR 0 "register_operand" "=d")
3171 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3172 (match_operand 2 "const_int_operand" "n")
3174 (clobber (reg:CC CC_REGNUM))]
3175 "INTVAL (operands[2]) > 0
3176 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3178 "&& reload_completed"
3180 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3181 (clobber (reg:CC CC_REGNUM))])
3183 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3184 (clobber (reg:CC CC_REGNUM))])]
3186 int bitsize = INTVAL (operands[2]);
3187 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3188 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3190 operands[1] = adjust_address (operands[1], BLKmode, 0);
3191 set_mem_size (operands[1], GEN_INT (size));
3192 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3193 operands[3] = GEN_INT (mask);
3197 ; insv instruction patterns
3200 (define_expand "insv"
3201 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3202 (match_operand 1 "const_int_operand" "")
3203 (match_operand 2 "const_int_operand" ""))
3204 (match_operand 3 "general_operand" ""))]
3207 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3212 (define_insn "*insv<mode>_z10"
3213 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3214 (match_operand 1 "const_int_operand" "I")
3215 (match_operand 2 "const_int_operand" "I"))
3216 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3217 (clobber (reg:CC CC_REGNUM))]
3219 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3220 GET_MODE_BITSIZE (<MODE>mode)"
3222 int start = INTVAL (operands[2]);
3223 int size = INTVAL (operands[1]);
3224 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3226 operands[2] = GEN_INT (offset + start); /* start bit position */
3227 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3228 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3229 start - size); /* left shift count */
3231 return "risbg\t%0,%3,%b2,%b1,%b4";
3233 [(set_attr "op_type" "RIE")
3234 (set_attr "z10prop" "z10_super_E1")])
3236 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3237 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3238 (define_insn "*insv<mode>_z10_noshift"
3239 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3240 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3241 (match_operand 2 "const_int_operand" "n"))
3242 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3243 (match_operand 4 "const_int_operand" "n"))))
3244 (clobber (reg:CC CC_REGNUM))]
3246 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3247 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3248 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3254 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3255 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3257 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3258 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3259 operands[7] = const0_rtx; /* left shift count */
3261 return "risbg\t%0,%1,%b5,%b6,%b7";
3263 [(set_attr "op_type" "RIE")
3264 (set_attr "z10prop" "z10_super_E1")])
3266 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3267 (define_insn "*insv<mode>_or_z10_noshift"
3268 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3269 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3270 (match_operand 2 "const_int_operand" "n"))
3271 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3272 (clobber (reg:CC CC_REGNUM))]
3274 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3275 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3280 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3281 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3283 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3284 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3285 operands[6] = const0_rtx; /* left shift count */
3287 return "rosbg\t%0,%1,%b4,%b5,%b6";
3289 [(set_attr "op_type" "RIE")])
3291 (define_insn "*insv<mode>_mem_reg"
3292 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
3293 (match_operand 1 "const_int_operand" "n,n")
3295 (match_operand:P 2 "register_operand" "d,d"))]
3296 "INTVAL (operands[1]) > 0
3297 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3298 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3300 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3302 operands[1] = GEN_INT ((1ul << size) - 1);
3303 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3304 : "stcmy\t%2,%1,%S0";
3306 [(set_attr "op_type" "RS,RSY")
3307 (set_attr "z10prop" "z10_super,z10_super")])
3309 (define_insn "*insvdi_mem_reghigh"
3310 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3311 (match_operand 1 "const_int_operand" "n")
3313 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3316 && INTVAL (operands[1]) > 0
3317 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3318 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3320 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3322 operands[1] = GEN_INT ((1ul << size) - 1);
3323 return "stcmh\t%2,%1,%S0";
3325 [(set_attr "op_type" "RSY")
3326 (set_attr "z10prop" "z10_super")])
3328 (define_insn "*insv<mode>_reg_imm"
3329 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3331 (match_operand 1 "const_int_operand" "n"))
3332 (match_operand:P 2 "const_int_operand" "n"))]
3334 && INTVAL (operands[1]) >= 0
3335 && INTVAL (operands[1]) < BITS_PER_WORD
3336 && INTVAL (operands[1]) % 16 == 0"
3338 switch (BITS_PER_WORD - INTVAL (operands[1]))
3340 case 64: return "iihh\t%0,%x2"; break;
3341 case 48: return "iihl\t%0,%x2"; break;
3342 case 32: return "iilh\t%0,%x2"; break;
3343 case 16: return "iill\t%0,%x2"; break;
3344 default: gcc_unreachable();
3347 [(set_attr "op_type" "RI")
3348 (set_attr "z10prop" "z10_super_E1")])
3350 ; Update the left-most 32 bit of a DI.
3351 (define_insn "*insv_h_di_reg_extimm"
3352 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3355 (match_operand:DI 1 "const_int_operand" "n"))]
3358 [(set_attr "op_type" "RIL")
3359 (set_attr "z10prop" "z10_fwd_E1")])
3361 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3362 (define_insn "*insv_l<mode>_reg_extimm"
3363 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3365 (match_operand 1 "const_int_operand" "n"))
3366 (match_operand:P 2 "const_int_operand" "n"))]
3368 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3370 [(set_attr "op_type" "RIL")
3371 (set_attr "z10prop" "z10_fwd_A1")])
3374 ; extendsidi2 instruction pattern(s).
3377 (define_expand "extendsidi2"
3378 [(set (match_operand:DI 0 "register_operand" "")
3379 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3384 emit_clobber (operands[0]);
3385 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3386 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3387 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3392 (define_insn "*extendsidi2"
3393 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3394 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3400 [(set_attr "op_type" "RRE,RXY,RIL")
3401 (set_attr "type" "*,*,larl")
3402 (set_attr "cpu_facility" "*,*,z10")
3403 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3406 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3409 (define_expand "extend<HQI:mode><DSI:mode>2"
3410 [(set (match_operand:DSI 0 "register_operand" "")
3411 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3414 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
3416 rtx tmp = gen_reg_rtx (SImode);
3417 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3418 emit_insn (gen_extendsidi2 (operands[0], tmp));
3421 else if (!TARGET_EXTIMM)
3423 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3424 GET_MODE_BITSIZE (<HQI:MODE>mode));
3426 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3427 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3428 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3434 ; extendhidi2 instruction pattern(s).
3437 (define_insn "*extendhidi2_extimm"
3438 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3439 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3440 "TARGET_64BIT && TARGET_EXTIMM"
3445 [(set_attr "op_type" "RRE,RXY,RIL")
3446 (set_attr "type" "*,*,larl")
3447 (set_attr "cpu_facility" "extimm,extimm,z10")
3448 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3450 (define_insn "*extendhidi2"
3451 [(set (match_operand:DI 0 "register_operand" "=d")
3452 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3455 [(set_attr "op_type" "RXY")
3456 (set_attr "z10prop" "z10_super_E1")])
3459 ; extendhisi2 instruction pattern(s).
3462 (define_insn "*extendhisi2_extimm"
3463 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3464 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3471 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3472 (set_attr "type" "*,*,*,larl")
3473 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3474 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3476 (define_insn "*extendhisi2"
3477 [(set (match_operand:SI 0 "register_operand" "=d,d")
3478 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3483 [(set_attr "op_type" "RX,RXY")
3484 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3487 ; extendqi(si|di)2 instruction pattern(s).
3490 ; lbr, lgbr, lb, lgb
3491 (define_insn "*extendqi<mode>2_extimm"
3492 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3493 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3498 [(set_attr "op_type" "RRE,RXY")
3499 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3502 (define_insn "*extendqi<mode>2"
3503 [(set (match_operand:GPR 0 "register_operand" "=d")
3504 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3505 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3507 [(set_attr "op_type" "RXY")
3508 (set_attr "z10prop" "z10_super_E1")])
3510 (define_insn_and_split "*extendqi<mode>2_short_displ"
3511 [(set (match_operand:GPR 0 "register_operand" "=d")
3512 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3513 (clobber (reg:CC CC_REGNUM))]
3514 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3516 "&& reload_completed"
3518 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3519 (clobber (reg:CC CC_REGNUM))])
3521 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3522 (clobber (reg:CC CC_REGNUM))])]
3524 operands[1] = adjust_address (operands[1], BLKmode, 0);
3525 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3526 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3527 - GET_MODE_BITSIZE (QImode));
3531 ; zero_extendsidi2 instruction pattern(s).
3534 (define_expand "zero_extendsidi2"
3535 [(set (match_operand:DI 0 "register_operand" "")
3536 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3541 emit_clobber (operands[0]);
3542 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3543 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3548 (define_insn "*zero_extendsidi2"
3549 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3550 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3556 [(set_attr "op_type" "RRE,RXY,RIL")
3557 (set_attr "type" "*,*,larl")
3558 (set_attr "cpu_facility" "*,*,z10")
3559 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3562 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3565 (define_insn "*llgt_sidi"
3566 [(set (match_operand:DI 0 "register_operand" "=d")
3567 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3568 (const_int 2147483647)))]
3571 [(set_attr "op_type" "RXE")
3572 (set_attr "z10prop" "z10_super_E1")])
3574 (define_insn_and_split "*llgt_sidi_split"
3575 [(set (match_operand:DI 0 "register_operand" "=d")
3576 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3577 (const_int 2147483647)))
3578 (clobber (reg:CC CC_REGNUM))]
3581 "&& reload_completed"
3583 (and:DI (subreg:DI (match_dup 1) 0)
3584 (const_int 2147483647)))]
3587 (define_insn "*llgt_sisi"
3588 [(set (match_operand:SI 0 "register_operand" "=d,d")
3589 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3590 (const_int 2147483647)))]
3595 [(set_attr "op_type" "RRE,RXE")
3596 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3598 (define_insn "*llgt_didi"
3599 [(set (match_operand:DI 0 "register_operand" "=d,d")
3600 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3601 (const_int 2147483647)))]
3606 [(set_attr "op_type" "RRE,RXE")
3607 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3610 [(set (match_operand:GPR 0 "register_operand" "")
3611 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3612 (const_int 2147483647)))
3613 (clobber (reg:CC CC_REGNUM))]
3614 "TARGET_ZARCH && reload_completed"
3616 (and:GPR (match_dup 1)
3617 (const_int 2147483647)))]
3621 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3624 (define_expand "zero_extend<mode>di2"
3625 [(set (match_operand:DI 0 "register_operand" "")
3626 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3631 rtx tmp = gen_reg_rtx (SImode);
3632 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3633 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3636 else if (!TARGET_EXTIMM)
3638 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3639 GET_MODE_BITSIZE(<MODE>mode));
3640 operands[1] = gen_lowpart (DImode, operands[1]);
3641 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3642 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3647 (define_expand "zero_extend<mode>si2"
3648 [(set (match_operand:SI 0 "register_operand" "")
3649 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3654 operands[1] = gen_lowpart (SImode, operands[1]);
3655 emit_insn (gen_andsi3 (operands[0], operands[1],
3656 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3662 (define_insn "*zero_extendhi<mode>2_z10"
3663 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3664 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3670 [(set_attr "op_type" "RXY,RRE,RIL")
3671 (set_attr "type" "*,*,larl")
3672 (set_attr "cpu_facility" "*,*,z10")
3673 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3675 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3676 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3677 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3678 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3683 [(set_attr "op_type" "RRE,RXY")
3684 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3687 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3688 [(set (match_operand:GPR 0 "register_operand" "=d")
3689 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3690 "TARGET_ZARCH && !TARGET_EXTIMM"
3692 [(set_attr "op_type" "RXY")
3693 (set_attr "z10prop" "z10_fwd_A3")])
3695 (define_insn_and_split "*zero_extendhisi2_31"
3696 [(set (match_operand:SI 0 "register_operand" "=&d")
3697 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3698 (clobber (reg:CC CC_REGNUM))]
3701 "&& reload_completed"
3702 [(set (match_dup 0) (const_int 0))
3704 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3705 (clobber (reg:CC CC_REGNUM))])]
3706 "operands[2] = gen_lowpart (HImode, operands[0]);")
3708 (define_insn_and_split "*zero_extendqisi2_31"
3709 [(set (match_operand:SI 0 "register_operand" "=&d")
3710 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3713 "&& reload_completed"
3714 [(set (match_dup 0) (const_int 0))
3715 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3716 "operands[2] = gen_lowpart (QImode, operands[0]);")
3719 ; zero_extendqihi2 instruction pattern(s).
3722 (define_expand "zero_extendqihi2"
3723 [(set (match_operand:HI 0 "register_operand" "")
3724 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3725 "TARGET_ZARCH && !TARGET_EXTIMM"
3727 operands[1] = gen_lowpart (HImode, operands[1]);
3728 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3732 (define_insn "*zero_extendqihi2_64"
3733 [(set (match_operand:HI 0 "register_operand" "=d")
3734 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3735 "TARGET_ZARCH && !TARGET_EXTIMM"
3737 [(set_attr "op_type" "RXY")
3738 (set_attr "z10prop" "z10_fwd_A3")])
3740 (define_insn_and_split "*zero_extendqihi2_31"
3741 [(set (match_operand:HI 0 "register_operand" "=&d")
3742 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3745 "&& reload_completed"
3746 [(set (match_dup 0) (const_int 0))
3747 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3748 "operands[2] = gen_lowpart (QImode, operands[0]);")
3751 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3754 (define_expand "fixuns_truncdddi2"
3756 [(set (match_operand:DI 0 "register_operand" "")
3757 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3758 (clobber (match_scratch:TD 2 "=f"))])]
3762 rtx label1 = gen_label_rtx ();
3763 rtx label2 = gen_label_rtx ();
3764 rtx temp = gen_reg_rtx (TDmode);
3765 REAL_VALUE_TYPE cmp, sub;
3767 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3768 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3770 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3771 solution is doing the check and the subtraction in TD mode and using a
3772 TD -> DI convert afterwards. */
3773 emit_insn (gen_extendddtd2 (temp, operands[1]));
3774 temp = force_reg (TDmode, temp);
3775 emit_cmp_and_jump_insns (temp,
3776 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3777 LT, NULL_RTX, VOIDmode, 0, label1);
3778 emit_insn (gen_subtd3 (temp, temp,
3779 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3780 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3783 emit_label (label1);
3784 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3785 emit_label (label2);
3789 (define_expand "fixuns_trunctddi2"
3790 [(set (match_operand:DI 0 "register_operand" "")
3791 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3794 rtx label1 = gen_label_rtx ();
3795 rtx label2 = gen_label_rtx ();
3796 rtx temp = gen_reg_rtx (TDmode);
3797 REAL_VALUE_TYPE cmp, sub;
3799 operands[1] = force_reg (TDmode, operands[1]);
3800 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3801 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3803 emit_cmp_and_jump_insns (operands[1],
3804 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3805 LT, NULL_RTX, VOIDmode, 0, label1);
3806 emit_insn (gen_subtd3 (temp, operands[1],
3807 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3808 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3811 emit_label (label1);
3812 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3813 emit_label (label2);
3818 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3819 ; instruction pattern(s).
3822 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3823 [(set (match_operand:GPR 0 "register_operand" "")
3824 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3827 rtx label1 = gen_label_rtx ();
3828 rtx label2 = gen_label_rtx ();
3829 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3830 REAL_VALUE_TYPE cmp, sub;
3832 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3833 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3834 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3836 emit_cmp_and_jump_insns (operands[1],
3837 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3838 LT, NULL_RTX, VOIDmode, 0, label1);
3839 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3840 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3841 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3845 emit_label (label1);
3846 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3847 operands[1], GEN_INT (5)));
3848 emit_label (label2);
3852 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3853 [(set (match_operand:GPR 0 "register_operand" "")
3854 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3857 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3862 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3863 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3864 [(set (match_operand:GPR 0 "register_operand" "=d")
3865 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3866 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3867 (clobber (reg:CC CC_REGNUM))]
3869 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3870 [(set_attr "op_type" "RRE")
3871 (set_attr "type" "ftoi")])
3875 ; fix_trunc(td|dd)di2 instruction pattern(s).
3878 (define_expand "fix_trunc<mode>di2"
3879 [(set (match_operand:DI 0 "register_operand" "")
3880 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3881 "TARGET_64BIT && TARGET_HARD_DFP"
3883 operands[1] = force_reg (<MODE>mode, operands[1]);
3884 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3890 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3891 [(set (match_operand:DI 0 "register_operand" "=d")
3892 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3893 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3894 (clobber (reg:CC CC_REGNUM))]
3895 "TARGET_64BIT && TARGET_HARD_DFP"
3896 "cg<DFP:xde>tr\t%0,%h2,%1"
3897 [(set_attr "op_type" "RRF")
3898 (set_attr "type" "ftoidfp")])
3902 ; fix_trunctf(si|di)2 instruction pattern(s).
3905 (define_expand "fix_trunctf<mode>2"
3906 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3907 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3908 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3909 (clobber (reg:CC CC_REGNUM))])]
3915 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3918 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3919 (define_insn "floatdi<mode>2"
3920 [(set (match_operand:FP 0 "register_operand" "=f")
3921 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3922 "TARGET_64BIT && TARGET_HARD_FLOAT"
3923 "c<xde>g<bt>r\t%0,%1"
3924 [(set_attr "op_type" "RRE")
3925 (set_attr "type" "itof<mode>" )])
3927 ; cxfbr, cdfbr, cefbr
3928 (define_insn "floatsi<mode>2"
3929 [(set (match_operand:BFP 0 "register_operand" "=f")
3930 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3933 [(set_attr "op_type" "RRE")
3934 (set_attr "type" "itof<mode>" )])
3938 ; truncdfsf2 instruction pattern(s).
3941 (define_insn "truncdfsf2"
3942 [(set (match_operand:SF 0 "register_operand" "=f")
3943 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3946 [(set_attr "op_type" "RRE")
3947 (set_attr "type" "ftruncdf")])
3950 ; trunctf(df|sf)2 instruction pattern(s).
3954 (define_insn "trunctf<mode>2"
3955 [(set (match_operand:DSF 0 "register_operand" "=f")
3956 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
3957 (clobber (match_scratch:TF 2 "=f"))]
3959 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
3960 [(set_attr "length" "6")
3961 (set_attr "type" "ftrunctf")])
3964 ; trunctddd2 and truncddsd2 instruction pattern(s).
3967 (define_insn "trunctddd2"
3968 [(set (match_operand:DD 0 "register_operand" "=f")
3969 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
3970 (clobber (match_scratch:TD 2 "=f"))]
3972 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
3973 [(set_attr "length" "6")
3974 (set_attr "type" "ftruncdd")])
3976 (define_insn "truncddsd2"
3977 [(set (match_operand:SD 0 "register_operand" "=f")
3978 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
3981 [(set_attr "op_type" "RRF")
3982 (set_attr "type" "ftruncsd")])
3985 ; extend(sf|df)(df|tf)2 instruction pattern(s).
3988 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
3989 (define_insn "extend<DSF:mode><BFP:mode>2"
3990 [(set (match_operand:BFP 0 "register_operand" "=f,f")
3991 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
3993 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
3995 l<BFP:xde><DSF:xde>br\t%0,%1
3996 l<BFP:xde><DSF:xde>b\t%0,%1"
3997 [(set_attr "op_type" "RRE,RXE")
3998 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4001 ; extendddtd2 and extendsddd2 instruction pattern(s).
4004 (define_insn "extendddtd2"
4005 [(set (match_operand:TD 0 "register_operand" "=f")
4006 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4009 [(set_attr "op_type" "RRF")
4010 (set_attr "type" "fsimptf")])
4012 (define_insn "extendsddd2"
4013 [(set (match_operand:DD 0 "register_operand" "=f")
4014 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4017 [(set_attr "op_type" "RRF")
4018 (set_attr "type" "fsimptf")])
4020 ; Binary <-> Decimal floating point trunc patterns
4023 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4024 [(set (reg:DFP_ALL FPR0_REGNUM)
4025 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4026 (use (reg:SI GPR0_REGNUM))
4027 (clobber (reg:CC CC_REGNUM))]
4031 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4032 [(set (reg:BFP FPR0_REGNUM)
4033 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4034 (use (reg:SI GPR0_REGNUM))
4035 (clobber (reg:CC CC_REGNUM))]
4039 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4040 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4041 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4043 [(set (reg:DFP_ALL FPR0_REGNUM)
4044 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4045 (use (reg:SI GPR0_REGNUM))
4046 (clobber (reg:CC CC_REGNUM))])
4047 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4048 (reg:DFP_ALL FPR0_REGNUM))]
4050 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4052 HOST_WIDE_INT flags;
4054 flags = (PFPO_CONVERT |
4055 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4056 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4058 operands[2] = GEN_INT (flags);
4061 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4062 [(set (reg:DFP_ALL FPR2_REGNUM)
4063 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4064 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4066 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4067 (use (reg:SI GPR0_REGNUM))
4068 (clobber (reg:CC CC_REGNUM))])
4069 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4071 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4073 HOST_WIDE_INT flags;
4075 flags = (PFPO_CONVERT |
4076 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4077 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4079 operands[2] = GEN_INT (flags);
4083 ; Binary <-> Decimal floating point extend patterns
4086 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4087 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4088 (use (reg:SI GPR0_REGNUM))
4089 (clobber (reg:CC CC_REGNUM))]
4093 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4094 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4095 (use (reg:SI GPR0_REGNUM))
4096 (clobber (reg:CC CC_REGNUM))]
4100 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4101 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4102 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4104 [(set (reg:DFP_ALL FPR0_REGNUM)
4105 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4106 (use (reg:SI GPR0_REGNUM))
4107 (clobber (reg:CC CC_REGNUM))])
4108 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4109 (reg:DFP_ALL FPR0_REGNUM))]
4111 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4113 HOST_WIDE_INT flags;
4115 flags = (PFPO_CONVERT |
4116 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4117 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4119 operands[2] = GEN_INT (flags);
4122 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4123 [(set (reg:DFP_ALL FPR2_REGNUM)
4124 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4125 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4127 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4128 (use (reg:SI GPR0_REGNUM))
4129 (clobber (reg:CC CC_REGNUM))])
4130 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4132 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4134 HOST_WIDE_INT flags;
4136 flags = (PFPO_CONVERT |
4137 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4138 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4140 operands[2] = GEN_INT (flags);
4145 ;; ARITHMETIC OPERATIONS
4147 ; arithmetic operations set the ConditionCode,
4148 ; because of unpredictable Bits in Register for Halfword and Byte
4149 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4152 ;;- Add instructions.
4156 ; addti3 instruction pattern(s).
4159 (define_insn_and_split "addti3"
4160 [(set (match_operand:TI 0 "register_operand" "=&d")
4161 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4162 (match_operand:TI 2 "general_operand" "do") ) )
4163 (clobber (reg:CC CC_REGNUM))]
4166 "&& reload_completed"
4168 [(set (reg:CCL1 CC_REGNUM)
4169 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4171 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4173 [(set (match_dup 3) (plus:DI
4174 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4175 (match_dup 4)) (match_dup 5)))
4176 (clobber (reg:CC CC_REGNUM))])]
4177 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4178 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4179 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4180 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4181 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4182 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4185 ; adddi3 instruction pattern(s).
4188 (define_expand "adddi3"
4190 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4191 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4192 (match_operand:DI 2 "general_operand" "")))
4193 (clobber (reg:CC CC_REGNUM))])]
4197 (define_insn "*adddi3_sign"
4198 [(set (match_operand:DI 0 "register_operand" "=d,d")
4199 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4200 (match_operand:DI 1 "register_operand" "0,0")))
4201 (clobber (reg:CC CC_REGNUM))]
4206 [(set_attr "op_type" "RRE,RXY")])
4208 (define_insn "*adddi3_zero_cc"
4209 [(set (reg CC_REGNUM)
4210 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4211 (match_operand:DI 1 "register_operand" "0,0"))
4213 (set (match_operand:DI 0 "register_operand" "=d,d")
4214 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4215 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4219 [(set_attr "op_type" "RRE,RXY")
4220 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4222 (define_insn "*adddi3_zero_cconly"
4223 [(set (reg CC_REGNUM)
4224 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4225 (match_operand:DI 1 "register_operand" "0,0"))
4227 (clobber (match_scratch:DI 0 "=d,d"))]
4228 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4232 [(set_attr "op_type" "RRE,RXY")
4233 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4235 (define_insn "*adddi3_zero"
4236 [(set (match_operand:DI 0 "register_operand" "=d,d")
4237 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4238 (match_operand:DI 1 "register_operand" "0,0")))
4239 (clobber (reg:CC CC_REGNUM))]
4244 [(set_attr "op_type" "RRE,RXY")
4245 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4247 (define_insn_and_split "*adddi3_31z"
4248 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4249 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4250 (match_operand:DI 2 "general_operand" "do") ) )
4251 (clobber (reg:CC CC_REGNUM))]
4252 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4254 "&& reload_completed"
4256 [(set (reg:CCL1 CC_REGNUM)
4257 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4259 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4261 [(set (match_dup 3) (plus:SI
4262 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4263 (match_dup 4)) (match_dup 5)))
4264 (clobber (reg:CC CC_REGNUM))])]
4265 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4266 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4267 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4268 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4269 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4270 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4272 (define_insn_and_split "*adddi3_31"
4273 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4274 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4275 (match_operand:DI 2 "general_operand" "do") ) )
4276 (clobber (reg:CC CC_REGNUM))]
4279 "&& reload_completed"
4281 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4282 (clobber (reg:CC CC_REGNUM))])
4284 [(set (reg:CCL1 CC_REGNUM)
4285 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4287 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4289 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4291 (label_ref (match_dup 9))))
4293 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4294 (clobber (reg:CC CC_REGNUM))])
4296 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4297 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4298 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4299 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4300 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4301 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4302 operands[9] = gen_label_rtx ();")
4305 ; addsi3 instruction pattern(s).
4308 (define_expand "addsi3"
4310 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4311 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4312 (match_operand:SI 2 "general_operand" "")))
4313 (clobber (reg:CC CC_REGNUM))])]
4317 (define_insn "*addsi3_sign"
4318 [(set (match_operand:SI 0 "register_operand" "=d,d")
4319 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4320 (match_operand:SI 1 "register_operand" "0,0")))
4321 (clobber (reg:CC CC_REGNUM))]
4326 [(set_attr "op_type" "RX,RXY")])
4329 ; add(di|si)3 instruction pattern(s).
4332 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4333 (define_insn "*add<mode>3"
4334 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4335 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4336 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4337 (clobber (reg:CC CC_REGNUM))]
4347 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4348 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4349 (set_attr "z10prop" "z10_super_E1,
4357 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4358 (define_insn "*add<mode>3_carry1_cc"
4359 [(set (reg CC_REGNUM)
4360 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4361 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4363 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4364 (plus:GPR (match_dup 1) (match_dup 2)))]
4365 "s390_match_ccmode (insn, CCL1mode)"
4373 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4374 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4375 (set_attr "z10prop" "z10_super_E1,
4382 ; alr, al, aly, algr, alg
4383 (define_insn "*add<mode>3_carry1_cconly"
4384 [(set (reg CC_REGNUM)
4385 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4386 (match_operand:GPR 2 "general_operand" "d,R,T"))
4388 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4389 "s390_match_ccmode (insn, CCL1mode)"
4394 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4395 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4397 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4398 (define_insn "*add<mode>3_carry2_cc"
4399 [(set (reg CC_REGNUM)
4400 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4401 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4403 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4404 (plus:GPR (match_dup 1) (match_dup 2)))]
4405 "s390_match_ccmode (insn, CCL1mode)"
4413 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4414 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4415 (set_attr "z10prop" "z10_super_E1,
4422 ; alr, al, aly, algr, alg
4423 (define_insn "*add<mode>3_carry2_cconly"
4424 [(set (reg CC_REGNUM)
4425 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4426 (match_operand:GPR 2 "general_operand" "d,R,T"))
4428 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4429 "s390_match_ccmode (insn, CCL1mode)"
4434 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4435 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4437 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4438 (define_insn "*add<mode>3_cc"
4439 [(set (reg CC_REGNUM)
4440 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4441 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4443 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4444 (plus:GPR (match_dup 1) (match_dup 2)))]
4445 "s390_match_ccmode (insn, CCLmode)"
4453 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4454 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4455 (set_attr "z10prop" "z10_super_E1,
4462 ; alr, al, aly, algr, alg
4463 (define_insn "*add<mode>3_cconly"
4464 [(set (reg CC_REGNUM)
4465 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4466 (match_operand:GPR 2 "general_operand" "d,R,T"))
4468 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4469 "s390_match_ccmode (insn, CCLmode)"
4474 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4475 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4477 ; alr, al, aly, algr, alg
4478 (define_insn "*add<mode>3_cconly2"
4479 [(set (reg CC_REGNUM)
4480 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4481 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4482 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4483 "s390_match_ccmode(insn, CCLmode)"
4488 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4489 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4491 ; ahi, afi, aghi, agfi, asi, agsi
4492 (define_insn "*add<mode>3_imm_cc"
4493 [(set (reg CC_REGNUM)
4494 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4495 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4497 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4498 (plus:GPR (match_dup 1) (match_dup 2)))]
4499 "s390_match_ccmode (insn, CCAmode)
4500 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4501 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4502 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4503 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4508 [(set_attr "op_type" "RI,RIL,SIY")
4509 (set_attr "cpu_facility" "*,extimm,z10")
4510 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4513 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4516 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4517 (define_insn "add<mode>3"
4518 [(set (match_operand:FP 0 "register_operand" "=f, f")
4519 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4520 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4521 (clobber (reg:CC CC_REGNUM))]
4524 a<xde><bt>r\t%0,<op1>%2
4526 [(set_attr "op_type" "<RRer>,RXE")
4527 (set_attr "type" "fsimp<mode>")])
4529 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4530 (define_insn "*add<mode>3_cc"
4531 [(set (reg CC_REGNUM)
4532 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4533 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4534 (match_operand:FP 3 "const0_operand" "")))
4535 (set (match_operand:FP 0 "register_operand" "=f,f")
4536 (plus:FP (match_dup 1) (match_dup 2)))]
4537 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4539 a<xde><bt>r\t%0,<op1>%2
4541 [(set_attr "op_type" "<RRer>,RXE")
4542 (set_attr "type" "fsimp<mode>")])
4544 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4545 (define_insn "*add<mode>3_cconly"
4546 [(set (reg CC_REGNUM)
4547 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4548 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4549 (match_operand:FP 3 "const0_operand" "")))
4550 (clobber (match_scratch:FP 0 "=f,f"))]
4551 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4553 a<xde><bt>r\t%0,<op1>%2
4555 [(set_attr "op_type" "<RRer>,RXE")
4556 (set_attr "type" "fsimp<mode>")])
4560 ;;- Subtract instructions.
4564 ; subti3 instruction pattern(s).
4567 (define_insn_and_split "subti3"
4568 [(set (match_operand:TI 0 "register_operand" "=&d")
4569 (minus:TI (match_operand:TI 1 "register_operand" "0")
4570 (match_operand:TI 2 "general_operand" "do") ) )
4571 (clobber (reg:CC CC_REGNUM))]
4574 "&& reload_completed"
4576 [(set (reg:CCL2 CC_REGNUM)
4577 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4579 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4581 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4582 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4583 (clobber (reg:CC CC_REGNUM))])]
4584 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4585 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4586 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4587 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4588 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4589 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4592 ; subdi3 instruction pattern(s).
4595 (define_expand "subdi3"
4597 [(set (match_operand:DI 0 "register_operand" "")
4598 (minus:DI (match_operand:DI 1 "register_operand" "")
4599 (match_operand:DI 2 "general_operand" "")))
4600 (clobber (reg:CC CC_REGNUM))])]
4604 (define_insn "*subdi3_sign"
4605 [(set (match_operand:DI 0 "register_operand" "=d,d")
4606 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4607 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4608 (clobber (reg:CC CC_REGNUM))]
4613 [(set_attr "op_type" "RRE,RXY")
4614 (set_attr "z10prop" "z10_c,*")])
4616 (define_insn "*subdi3_zero_cc"
4617 [(set (reg CC_REGNUM)
4618 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4619 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4621 (set (match_operand:DI 0 "register_operand" "=d,d")
4622 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4623 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4627 [(set_attr "op_type" "RRE,RXY")
4628 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4630 (define_insn "*subdi3_zero_cconly"
4631 [(set (reg CC_REGNUM)
4632 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4633 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4635 (clobber (match_scratch:DI 0 "=d,d"))]
4636 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4640 [(set_attr "op_type" "RRE,RXY")
4641 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4643 (define_insn "*subdi3_zero"
4644 [(set (match_operand:DI 0 "register_operand" "=d,d")
4645 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4646 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4647 (clobber (reg:CC CC_REGNUM))]
4652 [(set_attr "op_type" "RRE,RXY")
4653 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4655 (define_insn_and_split "*subdi3_31z"
4656 [(set (match_operand:DI 0 "register_operand" "=&d")
4657 (minus:DI (match_operand:DI 1 "register_operand" "0")
4658 (match_operand:DI 2 "general_operand" "do") ) )
4659 (clobber (reg:CC CC_REGNUM))]
4660 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4662 "&& reload_completed"
4664 [(set (reg:CCL2 CC_REGNUM)
4665 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4667 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4669 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4670 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4671 (clobber (reg:CC CC_REGNUM))])]
4672 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4673 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4674 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4675 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4676 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4677 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4679 (define_insn_and_split "*subdi3_31"
4680 [(set (match_operand:DI 0 "register_operand" "=&d")
4681 (minus:DI (match_operand:DI 1 "register_operand" "0")
4682 (match_operand:DI 2 "general_operand" "do") ) )
4683 (clobber (reg:CC CC_REGNUM))]
4686 "&& reload_completed"
4688 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4689 (clobber (reg:CC CC_REGNUM))])
4691 [(set (reg:CCL2 CC_REGNUM)
4692 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4694 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4696 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4698 (label_ref (match_dup 9))))
4700 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4701 (clobber (reg:CC CC_REGNUM))])
4703 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4704 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4705 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4706 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4707 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4708 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4709 operands[9] = gen_label_rtx ();")
4712 ; subsi3 instruction pattern(s).
4715 (define_expand "subsi3"
4717 [(set (match_operand:SI 0 "register_operand" "")
4718 (minus:SI (match_operand:SI 1 "register_operand" "")
4719 (match_operand:SI 2 "general_operand" "")))
4720 (clobber (reg:CC CC_REGNUM))])]
4724 (define_insn "*subsi3_sign"
4725 [(set (match_operand:SI 0 "register_operand" "=d,d")
4726 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4727 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4728 (clobber (reg:CC CC_REGNUM))]
4733 [(set_attr "op_type" "RX,RXY")])
4736 ; sub(di|si)3 instruction pattern(s).
4739 ; sr, s, sy, sgr, sg
4740 (define_insn "*sub<mode>3"
4741 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4742 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4743 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4744 (clobber (reg:CC CC_REGNUM))]
4750 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4751 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4753 ; slr, sl, sly, slgr, slg
4754 (define_insn "*sub<mode>3_borrow_cc"
4755 [(set (reg CC_REGNUM)
4756 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4757 (match_operand:GPR 2 "general_operand" "d,R,T"))
4759 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4760 (minus:GPR (match_dup 1) (match_dup 2)))]
4761 "s390_match_ccmode (insn, CCL2mode)"
4766 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4767 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4769 ; slr, sl, sly, slgr, slg
4770 (define_insn "*sub<mode>3_borrow_cconly"
4771 [(set (reg CC_REGNUM)
4772 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4773 (match_operand:GPR 2 "general_operand" "d,R,T"))
4775 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4776 "s390_match_ccmode (insn, CCL2mode)"
4781 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4782 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4784 ; slr, sl, sly, slgr, slg
4785 (define_insn "*sub<mode>3_cc"
4786 [(set (reg CC_REGNUM)
4787 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4788 (match_operand:GPR 2 "general_operand" "d,R,T"))
4790 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4791 (minus:GPR (match_dup 1) (match_dup 2)))]
4792 "s390_match_ccmode (insn, CCLmode)"
4797 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4798 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4800 ; slr, sl, sly, slgr, slg
4801 (define_insn "*sub<mode>3_cc2"
4802 [(set (reg CC_REGNUM)
4803 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4804 (match_operand:GPR 2 "general_operand" "d,R,T")))
4805 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4806 (minus:GPR (match_dup 1) (match_dup 2)))]
4807 "s390_match_ccmode (insn, CCL3mode)"
4812 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4813 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4815 ; slr, sl, sly, slgr, slg
4816 (define_insn "*sub<mode>3_cconly"
4817 [(set (reg CC_REGNUM)
4818 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4819 (match_operand:GPR 2 "general_operand" "d,R,T"))
4821 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4822 "s390_match_ccmode (insn, CCLmode)"
4827 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4828 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4831 ; slr, sl, sly, slgr, slg
4832 (define_insn "*sub<mode>3_cconly2"
4833 [(set (reg CC_REGNUM)
4834 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4835 (match_operand:GPR 2 "general_operand" "d,R,T")))
4836 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4837 "s390_match_ccmode (insn, CCL3mode)"
4842 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4843 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4847 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4850 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4851 (define_insn "sub<mode>3"
4852 [(set (match_operand:FP 0 "register_operand" "=f, f")
4853 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4854 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4855 (clobber (reg:CC CC_REGNUM))]
4858 s<xde><bt>r\t%0,<op1>%2
4860 [(set_attr "op_type" "<RRer>,RXE")
4861 (set_attr "type" "fsimp<mode>")])
4863 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4864 (define_insn "*sub<mode>3_cc"
4865 [(set (reg CC_REGNUM)
4866 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4867 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4868 (match_operand:FP 3 "const0_operand" "")))
4869 (set (match_operand:FP 0 "register_operand" "=f,f")
4870 (minus:FP (match_dup 1) (match_dup 2)))]
4871 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4873 s<xde><bt>r\t%0,<op1>%2
4875 [(set_attr "op_type" "<RRer>,RXE")
4876 (set_attr "type" "fsimp<mode>")])
4878 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4879 (define_insn "*sub<mode>3_cconly"
4880 [(set (reg CC_REGNUM)
4881 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4882 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4883 (match_operand:FP 3 "const0_operand" "")))
4884 (clobber (match_scratch:FP 0 "=f,f"))]
4885 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4887 s<xde><bt>r\t%0,<op1>%2
4889 [(set_attr "op_type" "<RRer>,RXE")
4890 (set_attr "type" "fsimp<mode>")])
4894 ;;- Conditional add/subtract instructions.
4898 ; add(di|si)cc instruction pattern(s).
4901 ; the following 4 patterns are used when the result of an add with
4902 ; carry is checked for an overflow condition
4904 ; op1 + op2 + c < op1
4906 ; alcr, alc, alcgr, alcg
4907 (define_insn "*add<mode>3_alc_carry1_cc"
4908 [(set (reg CC_REGNUM)
4910 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4911 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4912 (match_operand:GPR 2 "general_operand" "d,RT"))
4914 (set (match_operand:GPR 0 "register_operand" "=d,d")
4915 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4916 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4920 [(set_attr "op_type" "RRE,RXY")])
4922 ; alcr, alc, alcgr, alcg
4923 (define_insn "*add<mode>3_alc_carry1_cconly"
4924 [(set (reg CC_REGNUM)
4926 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4927 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4928 (match_operand:GPR 2 "general_operand" "d,RT"))
4930 (clobber (match_scratch:GPR 0 "=d,d"))]
4931 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4935 [(set_attr "op_type" "RRE,RXY")])
4937 ; op1 + op2 + c < op2
4939 ; alcr, alc, alcgr, alcg
4940 (define_insn "*add<mode>3_alc_carry2_cc"
4941 [(set (reg CC_REGNUM)
4943 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4944 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4945 (match_operand:GPR 2 "general_operand" "d,RT"))
4947 (set (match_operand:GPR 0 "register_operand" "=d,d")
4948 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4949 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4953 [(set_attr "op_type" "RRE,RXY")])
4955 ; alcr, alc, alcgr, alcg
4956 (define_insn "*add<mode>3_alc_carry2_cconly"
4957 [(set (reg CC_REGNUM)
4959 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4960 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4961 (match_operand:GPR 2 "general_operand" "d,RT"))
4963 (clobber (match_scratch:GPR 0 "=d,d"))]
4964 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4968 [(set_attr "op_type" "RRE,RXY")])
4970 ; alcr, alc, alcgr, alcg
4971 (define_insn "*add<mode>3_alc_cc"
4972 [(set (reg CC_REGNUM)
4974 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4975 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4976 (match_operand:GPR 2 "general_operand" "d,RT"))
4978 (set (match_operand:GPR 0 "register_operand" "=d,d")
4979 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4980 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4984 [(set_attr "op_type" "RRE,RXY")])
4986 ; alcr, alc, alcgr, alcg
4987 (define_insn "*add<mode>3_alc"
4988 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4989 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4990 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4991 (match_operand:GPR 2 "general_operand" "d,RT")))
4992 (clobber (reg:CC CC_REGNUM))]
4997 [(set_attr "op_type" "RRE,RXY")])
4999 ; slbr, slb, slbgr, slbg
5000 (define_insn "*sub<mode>3_slb_cc"
5001 [(set (reg CC_REGNUM)
5003 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5004 (match_operand:GPR 2 "general_operand" "d,RT"))
5005 (match_operand:GPR 3 "s390_slb_comparison" ""))
5007 (set (match_operand:GPR 0 "register_operand" "=d,d")
5008 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5009 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5013 [(set_attr "op_type" "RRE,RXY")
5014 (set_attr "z10prop" "z10_c,*")])
5016 ; slbr, slb, slbgr, slbg
5017 (define_insn "*sub<mode>3_slb"
5018 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5019 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5020 (match_operand:GPR 2 "general_operand" "d,RT"))
5021 (match_operand:GPR 3 "s390_slb_comparison" "")))
5022 (clobber (reg:CC CC_REGNUM))]
5027 [(set_attr "op_type" "RRE,RXY")
5028 (set_attr "z10prop" "z10_c,*")])
5030 (define_expand "add<mode>cc"
5031 [(match_operand:GPR 0 "register_operand" "")
5032 (match_operand 1 "comparison_operator" "")
5033 (match_operand:GPR 2 "register_operand" "")
5034 (match_operand:GPR 3 "const_int_operand" "")]
5036 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5037 XEXP (operands[1], 0), XEXP (operands[1], 1),
5038 operands[0], operands[2],
5039 operands[3])) FAIL; DONE;")
5042 ; scond instruction pattern(s).
5045 (define_insn_and_split "*scond<mode>"
5046 [(set (match_operand:GPR 0 "register_operand" "=&d")
5047 (match_operand:GPR 1 "s390_alc_comparison" ""))
5048 (clobber (reg:CC CC_REGNUM))]
5051 "&& reload_completed"
5052 [(set (match_dup 0) (const_int 0))
5054 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5056 (clobber (reg:CC CC_REGNUM))])]
5059 (define_insn_and_split "*scond<mode>_neg"
5060 [(set (match_operand:GPR 0 "register_operand" "=&d")
5061 (match_operand:GPR 1 "s390_slb_comparison" ""))
5062 (clobber (reg:CC CC_REGNUM))]
5065 "&& reload_completed"
5066 [(set (match_dup 0) (const_int 0))
5068 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5070 (clobber (reg:CC CC_REGNUM))])
5072 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5073 (clobber (reg:CC CC_REGNUM))])]
5077 (define_expand "cstore<mode>4"
5078 [(set (match_operand:SI 0 "register_operand" "")
5079 (match_operator:SI 1 "s390_scond_operator"
5080 [(match_operand:GPR 2 "register_operand" "")
5081 (match_operand:GPR 3 "general_operand" "")]))]
5083 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5084 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5086 (define_expand "cstorecc4"
5088 [(set (match_operand:SI 0 "register_operand" "")
5089 (match_operator:SI 1 "s390_eqne_operator"
5090 [(match_operand:CCZ1 2 "register_operand")
5091 (match_operand 3 "const0_operand")]))
5092 (clobber (reg:CC CC_REGNUM))])]
5094 "emit_insn (gen_sne (operands[0], operands[2]));
5095 if (GET_CODE (operands[1]) == EQ)
5096 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5099 (define_insn_and_split "sne"
5100 [(set (match_operand:SI 0 "register_operand" "=d")
5101 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5103 (clobber (reg:CC CC_REGNUM))]
5108 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5109 (clobber (reg:CC CC_REGNUM))])])
5113 ;;- Multiply instructions.
5117 ; muldi3 instruction pattern(s).
5120 (define_insn "*muldi3_sign"
5121 [(set (match_operand:DI 0 "register_operand" "=d,d")
5122 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5123 (match_operand:DI 1 "register_operand" "0,0")))]
5128 [(set_attr "op_type" "RRE,RXY")
5129 (set_attr "type" "imuldi")])
5131 (define_insn "muldi3"
5132 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5133 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5134 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5141 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5142 (set_attr "type" "imuldi")
5143 (set_attr "cpu_facility" "*,*,*,z10")])
5146 ; mulsi3 instruction pattern(s).
5149 (define_insn "*mulsi3_sign"
5150 [(set (match_operand:SI 0 "register_operand" "=d,d")
5151 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5152 (match_operand:SI 1 "register_operand" "0,0")))]
5157 [(set_attr "op_type" "RX,RXY")
5158 (set_attr "type" "imulhi")
5159 (set_attr "cpu_facility" "*,z10")])
5161 (define_insn "mulsi3"
5162 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5163 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5164 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5172 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5173 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5174 (set_attr "cpu_facility" "*,*,*,*,z10")])
5177 ; mulsidi3 instruction pattern(s).
5180 (define_insn "mulsidi3"
5181 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5182 (mult:DI (sign_extend:DI
5183 (match_operand:SI 1 "register_operand" "%0,0,0"))
5185 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5191 [(set_attr "op_type" "RR,RX,RXY")
5192 (set_attr "type" "imulsi")
5193 (set_attr "cpu_facility" "*,*,z10")])
5196 ; umulsidi3 instruction pattern(s).
5199 (define_insn "umulsidi3"
5200 [(set (match_operand:DI 0 "register_operand" "=d,d")
5201 (mult:DI (zero_extend:DI
5202 (match_operand:SI 1 "register_operand" "%0,0"))
5204 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5205 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5209 [(set_attr "op_type" "RRE,RXY")
5210 (set_attr "type" "imulsi")])
5213 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5216 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5217 (define_insn "mul<mode>3"
5218 [(set (match_operand:FP 0 "register_operand" "=f,f")
5219 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5220 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5223 m<xdee><bt>r\t%0,<op1>%2
5225 [(set_attr "op_type" "<RRer>,RXE")
5226 (set_attr "type" "fmul<mode>")])
5228 ; madbr, maebr, maxb, madb, maeb
5229 (define_insn "*fmadd<mode>"
5230 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5231 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
5232 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5233 (match_operand:DSF 3 "register_operand" "0,0")))]
5234 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5238 [(set_attr "op_type" "RRE,RXE")
5239 (set_attr "type" "fmul<mode>")])
5241 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5242 (define_insn "*fmsub<mode>"
5243 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5244 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
5245 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5246 (match_operand:DSF 3 "register_operand" "0,0")))]
5247 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5251 [(set_attr "op_type" "RRE,RXE")
5252 (set_attr "type" "fmul<mode>")])
5255 ;;- Divide and modulo instructions.
5259 ; divmoddi4 instruction pattern(s).
5262 (define_expand "divmoddi4"
5263 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5264 (div:DI (match_operand:DI 1 "register_operand" "")
5265 (match_operand:DI 2 "general_operand" "")))
5266 (set (match_operand:DI 3 "general_operand" "")
5267 (mod:DI (match_dup 1) (match_dup 2)))])
5268 (clobber (match_dup 4))]
5271 rtx insn, div_equal, mod_equal;
5273 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5274 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5276 operands[4] = gen_reg_rtx(TImode);
5277 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5279 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5280 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5282 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5283 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5288 (define_insn "divmodtidi3"
5289 [(set (match_operand:TI 0 "register_operand" "=d,d")
5293 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5294 (match_operand:DI 2 "general_operand" "d,RT")))
5296 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5301 [(set_attr "op_type" "RRE,RXY")
5302 (set_attr "type" "idiv")])
5304 (define_insn "divmodtisi3"
5305 [(set (match_operand:TI 0 "register_operand" "=d,d")
5309 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5311 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5314 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5319 [(set_attr "op_type" "RRE,RXY")
5320 (set_attr "type" "idiv")])
5323 ; udivmoddi4 instruction pattern(s).
5326 (define_expand "udivmoddi4"
5327 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5328 (udiv:DI (match_operand:DI 1 "general_operand" "")
5329 (match_operand:DI 2 "nonimmediate_operand" "")))
5330 (set (match_operand:DI 3 "general_operand" "")
5331 (umod:DI (match_dup 1) (match_dup 2)))])
5332 (clobber (match_dup 4))]
5335 rtx insn, div_equal, mod_equal, equal;
5337 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5338 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5339 equal = gen_rtx_IOR (TImode,
5340 gen_rtx_ASHIFT (TImode,
5341 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5343 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5345 operands[4] = gen_reg_rtx(TImode);
5346 emit_clobber (operands[4]);
5347 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5348 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5350 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5351 set_unique_reg_note (insn, REG_EQUAL, equal);
5353 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5354 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5356 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5357 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5362 (define_insn "udivmodtidi3"
5363 [(set (match_operand:TI 0 "register_operand" "=d,d")
5368 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5370 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5374 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5379 [(set_attr "op_type" "RRE,RXY")
5380 (set_attr "type" "idiv")])
5383 ; divmodsi4 instruction pattern(s).
5386 (define_expand "divmodsi4"
5387 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5388 (div:SI (match_operand:SI 1 "general_operand" "")
5389 (match_operand:SI 2 "nonimmediate_operand" "")))
5390 (set (match_operand:SI 3 "general_operand" "")
5391 (mod:SI (match_dup 1) (match_dup 2)))])
5392 (clobber (match_dup 4))]
5395 rtx insn, div_equal, mod_equal, equal;
5397 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5398 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5399 equal = gen_rtx_IOR (DImode,
5400 gen_rtx_ASHIFT (DImode,
5401 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5403 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5405 operands[4] = gen_reg_rtx(DImode);
5406 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5408 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5409 set_unique_reg_note (insn, REG_EQUAL, equal);
5411 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5412 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5414 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5415 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5420 (define_insn "divmoddisi3"
5421 [(set (match_operand:DI 0 "register_operand" "=d,d")
5426 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5428 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5432 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5437 [(set_attr "op_type" "RR,RX")
5438 (set_attr "type" "idiv")])
5441 ; udivsi3 and umodsi3 instruction pattern(s).
5444 (define_expand "udivmodsi4"
5445 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5446 (udiv:SI (match_operand:SI 1 "general_operand" "")
5447 (match_operand:SI 2 "nonimmediate_operand" "")))
5448 (set (match_operand:SI 3 "general_operand" "")
5449 (umod:SI (match_dup 1) (match_dup 2)))])
5450 (clobber (match_dup 4))]
5451 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5453 rtx insn, div_equal, mod_equal, equal;
5455 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5456 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5457 equal = gen_rtx_IOR (DImode,
5458 gen_rtx_ASHIFT (DImode,
5459 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5461 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5463 operands[4] = gen_reg_rtx(DImode);
5464 emit_clobber (operands[4]);
5465 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5466 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5468 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5469 set_unique_reg_note (insn, REG_EQUAL, equal);
5471 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5472 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5474 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5475 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5480 (define_insn "udivmoddisi3"
5481 [(set (match_operand:DI 0 "register_operand" "=d,d")
5486 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5488 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5492 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5493 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5497 [(set_attr "op_type" "RRE,RXY")
5498 (set_attr "type" "idiv")])
5500 (define_expand "udivsi3"
5501 [(set (match_operand:SI 0 "register_operand" "=d")
5502 (udiv:SI (match_operand:SI 1 "general_operand" "")
5503 (match_operand:SI 2 "general_operand" "")))
5504 (clobber (match_dup 3))]
5505 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5507 rtx insn, udiv_equal, umod_equal, equal;
5509 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5510 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5511 equal = gen_rtx_IOR (DImode,
5512 gen_rtx_ASHIFT (DImode,
5513 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5515 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5517 operands[3] = gen_reg_rtx (DImode);
5519 if (CONSTANT_P (operands[2]))
5521 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5523 rtx label1 = gen_label_rtx ();
5525 operands[1] = make_safe_from (operands[1], operands[0]);
5526 emit_move_insn (operands[0], const0_rtx);
5527 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5529 emit_move_insn (operands[0], const1_rtx);
5530 emit_label (label1);
5534 operands[2] = force_reg (SImode, operands[2]);
5535 operands[2] = make_safe_from (operands[2], operands[0]);
5537 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5538 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5540 set_unique_reg_note (insn, REG_EQUAL, equal);
5542 insn = emit_move_insn (operands[0],
5543 gen_lowpart (SImode, operands[3]));
5544 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5549 rtx label1 = gen_label_rtx ();
5550 rtx label2 = gen_label_rtx ();
5551 rtx label3 = gen_label_rtx ();
5553 operands[1] = force_reg (SImode, operands[1]);
5554 operands[1] = make_safe_from (operands[1], operands[0]);
5555 operands[2] = force_reg (SImode, operands[2]);
5556 operands[2] = make_safe_from (operands[2], operands[0]);
5558 emit_move_insn (operands[0], const0_rtx);
5559 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5561 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5563 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5565 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5566 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5568 set_unique_reg_note (insn, REG_EQUAL, equal);
5570 insn = emit_move_insn (operands[0],
5571 gen_lowpart (SImode, operands[3]));
5572 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5575 emit_label (label1);
5576 emit_move_insn (operands[0], operands[1]);
5578 emit_label (label2);
5579 emit_move_insn (operands[0], const1_rtx);
5580 emit_label (label3);
5582 emit_move_insn (operands[0], operands[0]);
5586 (define_expand "umodsi3"
5587 [(set (match_operand:SI 0 "register_operand" "=d")
5588 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5589 (match_operand:SI 2 "nonimmediate_operand" "")))
5590 (clobber (match_dup 3))]
5591 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5593 rtx insn, udiv_equal, umod_equal, equal;
5595 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5596 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5597 equal = gen_rtx_IOR (DImode,
5598 gen_rtx_ASHIFT (DImode,
5599 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5601 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5603 operands[3] = gen_reg_rtx (DImode);
5605 if (CONSTANT_P (operands[2]))
5607 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5609 rtx label1 = gen_label_rtx ();
5611 operands[1] = make_safe_from (operands[1], operands[0]);
5612 emit_move_insn (operands[0], operands[1]);
5613 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5615 emit_insn (gen_abssi2 (operands[0], operands[2]));
5616 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5617 emit_label (label1);
5621 operands[2] = force_reg (SImode, operands[2]);
5622 operands[2] = make_safe_from (operands[2], operands[0]);
5624 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5625 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5627 set_unique_reg_note (insn, REG_EQUAL, equal);
5629 insn = emit_move_insn (operands[0],
5630 gen_highpart (SImode, operands[3]));
5631 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5636 rtx label1 = gen_label_rtx ();
5637 rtx label2 = gen_label_rtx ();
5638 rtx label3 = gen_label_rtx ();
5640 operands[1] = force_reg (SImode, operands[1]);
5641 operands[1] = make_safe_from (operands[1], operands[0]);
5642 operands[2] = force_reg (SImode, operands[2]);
5643 operands[2] = make_safe_from (operands[2], operands[0]);
5645 emit_move_insn(operands[0], operands[1]);
5646 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5648 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5650 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5652 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5653 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5655 set_unique_reg_note (insn, REG_EQUAL, equal);
5657 insn = emit_move_insn (operands[0],
5658 gen_highpart (SImode, operands[3]));
5659 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5662 emit_label (label1);
5663 emit_move_insn (operands[0], const0_rtx);
5665 emit_label (label2);
5666 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5667 emit_label (label3);
5673 ; div(df|sf)3 instruction pattern(s).
5676 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5677 (define_insn "div<mode>3"
5678 [(set (match_operand:FP 0 "register_operand" "=f,f")
5679 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5680 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5683 d<xde><bt>r\t%0,<op1>%2
5685 [(set_attr "op_type" "<RRer>,RXE")
5686 (set_attr "type" "fdiv<mode>")])
5690 ;;- And instructions.
5693 (define_expand "and<mode>3"
5694 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5695 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5696 (match_operand:INT 2 "general_operand" "")))
5697 (clobber (reg:CC CC_REGNUM))]
5699 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5702 ; anddi3 instruction pattern(s).
5705 (define_insn "*anddi3_cc"
5706 [(set (reg CC_REGNUM)
5707 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5708 (match_operand:DI 2 "general_operand" "d,RT"))
5710 (set (match_operand:DI 0 "register_operand" "=d,d")
5711 (and:DI (match_dup 1) (match_dup 2)))]
5712 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5716 [(set_attr "op_type" "RRE,RXY")
5717 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5719 (define_insn "*anddi3_cconly"
5720 [(set (reg CC_REGNUM)
5721 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5722 (match_operand:DI 2 "general_operand" "d,RT"))
5724 (clobber (match_scratch:DI 0 "=d,d"))]
5725 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5726 /* Do not steal TM patterns. */
5727 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5731 [(set_attr "op_type" "RRE,RXY")
5732 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5734 (define_insn "*anddi3"
5735 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5736 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5737 "%d,o,0,0,0,0,0,0,0,0,0,0")
5738 (match_operand:DI 2 "general_operand"
5739 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5740 (clobber (reg:CC CC_REGNUM))]
5741 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5755 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5756 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5757 (set_attr "z10prop" "*,
5771 [(set (match_operand:DI 0 "s_operand" "")
5772 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5773 (clobber (reg:CC CC_REGNUM))]
5776 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5777 (clobber (reg:CC CC_REGNUM))])]
5778 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5782 ; andsi3 instruction pattern(s).
5785 (define_insn "*andsi3_cc"
5786 [(set (reg CC_REGNUM)
5787 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5788 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5790 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5791 (and:SI (match_dup 1) (match_dup 2)))]
5792 "s390_match_ccmode(insn, CCTmode)"
5798 [(set_attr "op_type" "RIL,RR,RX,RXY")
5799 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5801 (define_insn "*andsi3_cconly"
5802 [(set (reg CC_REGNUM)
5803 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5804 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5806 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5807 "s390_match_ccmode(insn, CCTmode)
5808 /* Do not steal TM patterns. */
5809 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5815 [(set_attr "op_type" "RIL,RR,RX,RXY")
5816 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5818 (define_insn "*andsi3_zarch"
5819 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5820 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5821 "%d,o,0,0,0,0,0,0,0,0")
5822 (match_operand:SI 2 "general_operand"
5823 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5824 (clobber (reg:CC CC_REGNUM))]
5825 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5837 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5838 (set_attr "z10prop" "*,
5849 (define_insn "*andsi3_esa"
5850 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5851 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5852 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5853 (clobber (reg:CC CC_REGNUM))]
5854 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5860 [(set_attr "op_type" "RR,RX,SI,SS")
5861 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5865 [(set (match_operand:SI 0 "s_operand" "")
5866 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5867 (clobber (reg:CC CC_REGNUM))]
5870 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5871 (clobber (reg:CC CC_REGNUM))])]
5872 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5875 ; andhi3 instruction pattern(s).
5878 (define_insn "*andhi3_zarch"
5879 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5880 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5881 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5882 (clobber (reg:CC CC_REGNUM))]
5883 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5889 [(set_attr "op_type" "RR,RI,SI,SS")
5890 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5893 (define_insn "*andhi3_esa"
5894 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5895 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5896 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5897 (clobber (reg:CC CC_REGNUM))]
5898 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5903 [(set_attr "op_type" "RR,SI,SS")
5904 (set_attr "z10prop" "z10_super_E1,*,*")
5908 [(set (match_operand:HI 0 "s_operand" "")
5909 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5910 (clobber (reg:CC CC_REGNUM))]
5913 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5914 (clobber (reg:CC CC_REGNUM))])]
5915 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5918 ; andqi3 instruction pattern(s).
5921 (define_insn "*andqi3_zarch"
5922 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5923 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5924 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5925 (clobber (reg:CC CC_REGNUM))]
5926 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5933 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
5934 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
5936 (define_insn "*andqi3_esa"
5937 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5938 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5939 (match_operand:QI 2 "general_operand" "d,n,Q")))
5940 (clobber (reg:CC CC_REGNUM))]
5941 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5946 [(set_attr "op_type" "RR,SI,SS")
5947 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
5950 ; Block and (NC) patterns.
5954 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5955 (and:BLK (match_dup 0)
5956 (match_operand:BLK 1 "memory_operand" "Q")))
5957 (use (match_operand 2 "const_int_operand" "n"))
5958 (clobber (reg:CC CC_REGNUM))]
5959 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5960 "nc\t%O0(%2,%R0),%S1"
5961 [(set_attr "op_type" "SS")])
5964 [(set (match_operand 0 "memory_operand" "")
5966 (match_operand 1 "memory_operand" "")))
5967 (clobber (reg:CC CC_REGNUM))]
5969 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5970 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5972 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5974 (clobber (reg:CC CC_REGNUM))])]
5976 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5977 operands[0] = adjust_address (operands[0], BLKmode, 0);
5978 operands[1] = adjust_address (operands[1], BLKmode, 0);
5983 [(set (match_operand:BLK 0 "memory_operand" "")
5984 (and:BLK (match_dup 0)
5985 (match_operand:BLK 1 "memory_operand" "")))
5986 (use (match_operand 2 "const_int_operand" ""))
5987 (clobber (reg:CC CC_REGNUM))])
5989 [(set (match_operand:BLK 3 "memory_operand" "")
5990 (and:BLK (match_dup 3)
5991 (match_operand:BLK 4 "memory_operand" "")))
5992 (use (match_operand 5 "const_int_operand" ""))
5993 (clobber (reg:CC CC_REGNUM))])]
5994 "s390_offset_p (operands[0], operands[3], operands[2])
5995 && s390_offset_p (operands[1], operands[4], operands[2])
5996 && !s390_overlap_p (operands[0], operands[1],
5997 INTVAL (operands[2]) + INTVAL (operands[5]))
5998 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6000 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6002 (clobber (reg:CC CC_REGNUM))])]
6003 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6004 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6005 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6009 ;;- Bit set (inclusive or) instructions.
6012 (define_expand "ior<mode>3"
6013 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6014 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6015 (match_operand:INT 2 "general_operand" "")))
6016 (clobber (reg:CC CC_REGNUM))]
6018 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6021 ; iordi3 instruction pattern(s).
6024 (define_insn "*iordi3_cc"
6025 [(set (reg CC_REGNUM)
6026 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6027 (match_operand:DI 2 "general_operand" "d,RT"))
6029 (set (match_operand:DI 0 "register_operand" "=d,d")
6030 (ior:DI (match_dup 1) (match_dup 2)))]
6031 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6035 [(set_attr "op_type" "RRE,RXY")
6036 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6038 (define_insn "*iordi3_cconly"
6039 [(set (reg CC_REGNUM)
6040 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6041 (match_operand:DI 2 "general_operand" "d,RT"))
6043 (clobber (match_scratch:DI 0 "=d,d"))]
6044 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6048 [(set_attr "op_type" "RRE,RXY")
6049 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6051 (define_insn "*iordi3"
6052 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6053 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6054 (match_operand:DI 2 "general_operand"
6055 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6056 (clobber (reg:CC CC_REGNUM))]
6057 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6069 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6070 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6071 (set_attr "z10prop" "z10_super_E1,
6083 [(set (match_operand:DI 0 "s_operand" "")
6084 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6085 (clobber (reg:CC CC_REGNUM))]
6088 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6089 (clobber (reg:CC CC_REGNUM))])]
6090 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6093 ; iorsi3 instruction pattern(s).
6096 (define_insn "*iorsi3_cc"
6097 [(set (reg CC_REGNUM)
6098 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6099 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6101 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6102 (ior:SI (match_dup 1) (match_dup 2)))]
6103 "s390_match_ccmode(insn, CCTmode)"
6109 [(set_attr "op_type" "RIL,RR,RX,RXY")
6110 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6112 (define_insn "*iorsi3_cconly"
6113 [(set (reg CC_REGNUM)
6114 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6115 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6117 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6118 "s390_match_ccmode(insn, CCTmode)"
6124 [(set_attr "op_type" "RIL,RR,RX,RXY")
6125 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6127 (define_insn "*iorsi3_zarch"
6128 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6129 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6130 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6131 (clobber (reg:CC CC_REGNUM))]
6132 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6142 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6143 (set_attr "z10prop" "z10_super_E1,
6152 (define_insn "*iorsi3_esa"
6153 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6154 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6155 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6156 (clobber (reg:CC CC_REGNUM))]
6157 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6163 [(set_attr "op_type" "RR,RX,SI,SS")
6164 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6167 [(set (match_operand:SI 0 "s_operand" "")
6168 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6169 (clobber (reg:CC CC_REGNUM))]
6172 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6173 (clobber (reg:CC CC_REGNUM))])]
6174 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6177 ; iorhi3 instruction pattern(s).
6180 (define_insn "*iorhi3_zarch"
6181 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6182 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6183 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6184 (clobber (reg:CC CC_REGNUM))]
6185 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6191 [(set_attr "op_type" "RR,RI,SI,SS")
6192 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6194 (define_insn "*iorhi3_esa"
6195 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6196 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6197 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6198 (clobber (reg:CC CC_REGNUM))]
6199 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6204 [(set_attr "op_type" "RR,SI,SS")
6205 (set_attr "z10prop" "z10_super_E1,*,*")])
6208 [(set (match_operand:HI 0 "s_operand" "")
6209 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6210 (clobber (reg:CC CC_REGNUM))]
6213 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6214 (clobber (reg:CC CC_REGNUM))])]
6215 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6218 ; iorqi3 instruction pattern(s).
6221 (define_insn "*iorqi3_zarch"
6222 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6223 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6224 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6225 (clobber (reg:CC CC_REGNUM))]
6226 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6233 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6234 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6236 (define_insn "*iorqi3_esa"
6237 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6238 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6239 (match_operand:QI 2 "general_operand" "d,n,Q")))
6240 (clobber (reg:CC CC_REGNUM))]
6241 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6246 [(set_attr "op_type" "RR,SI,SS")
6247 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6250 ; Block inclusive or (OC) patterns.
6254 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6255 (ior:BLK (match_dup 0)
6256 (match_operand:BLK 1 "memory_operand" "Q")))
6257 (use (match_operand 2 "const_int_operand" "n"))
6258 (clobber (reg:CC CC_REGNUM))]
6259 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6260 "oc\t%O0(%2,%R0),%S1"
6261 [(set_attr "op_type" "SS")])
6264 [(set (match_operand 0 "memory_operand" "")
6266 (match_operand 1 "memory_operand" "")))
6267 (clobber (reg:CC CC_REGNUM))]
6269 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6270 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6272 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6274 (clobber (reg:CC CC_REGNUM))])]
6276 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6277 operands[0] = adjust_address (operands[0], BLKmode, 0);
6278 operands[1] = adjust_address (operands[1], BLKmode, 0);
6283 [(set (match_operand:BLK 0 "memory_operand" "")
6284 (ior:BLK (match_dup 0)
6285 (match_operand:BLK 1 "memory_operand" "")))
6286 (use (match_operand 2 "const_int_operand" ""))
6287 (clobber (reg:CC CC_REGNUM))])
6289 [(set (match_operand:BLK 3 "memory_operand" "")
6290 (ior:BLK (match_dup 3)
6291 (match_operand:BLK 4 "memory_operand" "")))
6292 (use (match_operand 5 "const_int_operand" ""))
6293 (clobber (reg:CC CC_REGNUM))])]
6294 "s390_offset_p (operands[0], operands[3], operands[2])
6295 && s390_offset_p (operands[1], operands[4], operands[2])
6296 && !s390_overlap_p (operands[0], operands[1],
6297 INTVAL (operands[2]) + INTVAL (operands[5]))
6298 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6300 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6302 (clobber (reg:CC CC_REGNUM))])]
6303 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6304 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6305 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6309 ;;- Xor instructions.
6312 (define_expand "xor<mode>3"
6313 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6314 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6315 (match_operand:INT 2 "general_operand" "")))
6316 (clobber (reg:CC CC_REGNUM))]
6318 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6321 ; xordi3 instruction pattern(s).
6324 (define_insn "*xordi3_cc"
6325 [(set (reg CC_REGNUM)
6326 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6327 (match_operand:DI 2 "general_operand" "d,RT"))
6329 (set (match_operand:DI 0 "register_operand" "=d,d")
6330 (xor:DI (match_dup 1) (match_dup 2)))]
6331 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6335 [(set_attr "op_type" "RRE,RXY")
6336 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6338 (define_insn "*xordi3_cconly"
6339 [(set (reg CC_REGNUM)
6340 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6341 (match_operand:DI 2 "general_operand" "d,RT"))
6343 (clobber (match_scratch:DI 0 "=d,d"))]
6344 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6348 [(set_attr "op_type" "RRE,RXY")
6349 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6351 (define_insn "*xordi3"
6352 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6353 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6354 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6355 (clobber (reg:CC CC_REGNUM))]
6356 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6364 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6365 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6366 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6369 [(set (match_operand:DI 0 "s_operand" "")
6370 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6371 (clobber (reg:CC CC_REGNUM))]
6374 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6375 (clobber (reg:CC CC_REGNUM))])]
6376 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6379 ; xorsi3 instruction pattern(s).
6382 (define_insn "*xorsi3_cc"
6383 [(set (reg CC_REGNUM)
6384 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6385 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6387 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6388 (xor:SI (match_dup 1) (match_dup 2)))]
6389 "s390_match_ccmode(insn, CCTmode)"
6395 [(set_attr "op_type" "RIL,RR,RX,RXY")
6396 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6398 (define_insn "*xorsi3_cconly"
6399 [(set (reg CC_REGNUM)
6400 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6401 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6403 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6404 "s390_match_ccmode(insn, CCTmode)"
6410 [(set_attr "op_type" "RIL,RR,RX,RXY")
6411 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6413 (define_insn "*xorsi3"
6414 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6415 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6416 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6417 (clobber (reg:CC CC_REGNUM))]
6418 "s390_logical_operator_ok_p (operands)"
6426 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6427 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6430 [(set (match_operand:SI 0 "s_operand" "")
6431 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6432 (clobber (reg:CC CC_REGNUM))]
6435 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6436 (clobber (reg:CC CC_REGNUM))])]
6437 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6440 ; xorhi3 instruction pattern(s).
6443 (define_insn "*xorhi3"
6444 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6445 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6446 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6447 (clobber (reg:CC CC_REGNUM))]
6448 "s390_logical_operator_ok_p (operands)"
6454 [(set_attr "op_type" "RIL,RR,SI,SS")
6455 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6458 [(set (match_operand:HI 0 "s_operand" "")
6459 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6460 (clobber (reg:CC CC_REGNUM))]
6463 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6464 (clobber (reg:CC CC_REGNUM))])]
6465 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6468 ; xorqi3 instruction pattern(s).
6471 (define_insn "*xorqi3"
6472 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6473 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6474 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6475 (clobber (reg:CC CC_REGNUM))]
6476 "s390_logical_operator_ok_p (operands)"
6483 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6484 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6488 ; Block exclusive or (XC) patterns.
6492 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6493 (xor:BLK (match_dup 0)
6494 (match_operand:BLK 1 "memory_operand" "Q")))
6495 (use (match_operand 2 "const_int_operand" "n"))
6496 (clobber (reg:CC CC_REGNUM))]
6497 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6498 "xc\t%O0(%2,%R0),%S1"
6499 [(set_attr "op_type" "SS")])
6502 [(set (match_operand 0 "memory_operand" "")
6504 (match_operand 1 "memory_operand" "")))
6505 (clobber (reg:CC CC_REGNUM))]
6507 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6508 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6510 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6512 (clobber (reg:CC CC_REGNUM))])]
6514 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6515 operands[0] = adjust_address (operands[0], BLKmode, 0);
6516 operands[1] = adjust_address (operands[1], BLKmode, 0);
6521 [(set (match_operand:BLK 0 "memory_operand" "")
6522 (xor:BLK (match_dup 0)
6523 (match_operand:BLK 1 "memory_operand" "")))
6524 (use (match_operand 2 "const_int_operand" ""))
6525 (clobber (reg:CC CC_REGNUM))])
6527 [(set (match_operand:BLK 3 "memory_operand" "")
6528 (xor:BLK (match_dup 3)
6529 (match_operand:BLK 4 "memory_operand" "")))
6530 (use (match_operand 5 "const_int_operand" ""))
6531 (clobber (reg:CC CC_REGNUM))])]
6532 "s390_offset_p (operands[0], operands[3], operands[2])
6533 && s390_offset_p (operands[1], operands[4], operands[2])
6534 && !s390_overlap_p (operands[0], operands[1],
6535 INTVAL (operands[2]) + INTVAL (operands[5]))
6536 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6538 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6540 (clobber (reg:CC CC_REGNUM))])]
6541 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6542 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6543 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6546 ; Block xor (XC) patterns with src == dest.
6549 (define_insn "*xc_zero"
6550 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6552 (use (match_operand 1 "const_int_operand" "n"))
6553 (clobber (reg:CC CC_REGNUM))]
6554 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6555 "xc\t%O0(%1,%R0),%S0"
6556 [(set_attr "op_type" "SS")])
6560 [(set (match_operand:BLK 0 "memory_operand" "")
6562 (use (match_operand 1 "const_int_operand" ""))
6563 (clobber (reg:CC CC_REGNUM))])
6565 [(set (match_operand:BLK 2 "memory_operand" "")
6567 (use (match_operand 3 "const_int_operand" ""))
6568 (clobber (reg:CC CC_REGNUM))])]
6569 "s390_offset_p (operands[0], operands[2], operands[1])
6570 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6572 [(set (match_dup 4) (const_int 0))
6574 (clobber (reg:CC CC_REGNUM))])]
6575 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6576 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6580 ;;- Negate instructions.
6584 ; neg(di|si)2 instruction pattern(s).
6587 (define_expand "neg<mode>2"
6589 [(set (match_operand:DSI 0 "register_operand" "=d")
6590 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6591 (clobber (reg:CC CC_REGNUM))])]
6595 (define_insn "*negdi2_sign_cc"
6596 [(set (reg CC_REGNUM)
6597 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6598 (match_operand:SI 1 "register_operand" "d") 0)
6599 (const_int 32)) (const_int 32)))
6601 (set (match_operand:DI 0 "register_operand" "=d")
6602 (neg:DI (sign_extend:DI (match_dup 1))))]
6603 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6605 [(set_attr "op_type" "RRE")
6606 (set_attr "z10prop" "z10_c")])
6608 (define_insn "*negdi2_sign"
6609 [(set (match_operand:DI 0 "register_operand" "=d")
6610 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6611 (clobber (reg:CC CC_REGNUM))]
6614 [(set_attr "op_type" "RRE")
6615 (set_attr "z10prop" "z10_c")])
6618 (define_insn "*neg<mode>2_cc"
6619 [(set (reg CC_REGNUM)
6620 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6622 (set (match_operand:GPR 0 "register_operand" "=d")
6623 (neg:GPR (match_dup 1)))]
6624 "s390_match_ccmode (insn, CCAmode)"
6626 [(set_attr "op_type" "RR<E>")
6627 (set_attr "z10prop" "z10_super_c_E1")])
6630 (define_insn "*neg<mode>2_cconly"
6631 [(set (reg CC_REGNUM)
6632 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6634 (clobber (match_scratch:GPR 0 "=d"))]
6635 "s390_match_ccmode (insn, CCAmode)"
6637 [(set_attr "op_type" "RR<E>")
6638 (set_attr "z10prop" "z10_super_c_E1")])
6641 (define_insn "*neg<mode>2"
6642 [(set (match_operand:GPR 0 "register_operand" "=d")
6643 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6644 (clobber (reg:CC CC_REGNUM))]
6647 [(set_attr "op_type" "RR<E>")
6648 (set_attr "z10prop" "z10_super_c_E1")])
6650 (define_insn_and_split "*negdi2_31"
6651 [(set (match_operand:DI 0 "register_operand" "=d")
6652 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6653 (clobber (reg:CC CC_REGNUM))]
6656 "&& reload_completed"
6658 [(set (match_dup 2) (neg:SI (match_dup 3)))
6659 (clobber (reg:CC CC_REGNUM))])
6661 [(set (reg:CCAP CC_REGNUM)
6662 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6663 (set (match_dup 4) (neg:SI (match_dup 5)))])
6665 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6667 (label_ref (match_dup 6))))
6669 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6670 (clobber (reg:CC CC_REGNUM))])
6672 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6673 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6674 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6675 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6676 operands[6] = gen_label_rtx ();")
6679 ; neg(df|sf)2 instruction pattern(s).
6682 (define_expand "neg<mode>2"
6684 [(set (match_operand:BFP 0 "register_operand" "=f")
6685 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6686 (clobber (reg:CC CC_REGNUM))])]
6690 ; lcxbr, lcdbr, lcebr
6691 (define_insn "*neg<mode>2_cc"
6692 [(set (reg CC_REGNUM)
6693 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6694 (match_operand:BFP 2 "const0_operand" "")))
6695 (set (match_operand:BFP 0 "register_operand" "=f")
6696 (neg:BFP (match_dup 1)))]
6697 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6699 [(set_attr "op_type" "RRE")
6700 (set_attr "type" "fsimp<mode>")])
6702 ; lcxbr, lcdbr, lcebr
6703 (define_insn "*neg<mode>2_cconly"
6704 [(set (reg CC_REGNUM)
6705 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6706 (match_operand:BFP 2 "const0_operand" "")))
6707 (clobber (match_scratch:BFP 0 "=f"))]
6708 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6710 [(set_attr "op_type" "RRE")
6711 (set_attr "type" "fsimp<mode>")])
6714 (define_insn "*neg<mode>2_nocc"
6715 [(set (match_operand:FP 0 "register_operand" "=f")
6716 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6719 [(set_attr "op_type" "RRE")
6720 (set_attr "type" "fsimp<mode>")])
6722 ; lcxbr, lcdbr, lcebr
6723 (define_insn "*neg<mode>2"
6724 [(set (match_operand:BFP 0 "register_operand" "=f")
6725 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6726 (clobber (reg:CC CC_REGNUM))]
6729 [(set_attr "op_type" "RRE")
6730 (set_attr "type" "fsimp<mode>")])
6734 ;;- Absolute value instructions.
6738 ; abs(di|si)2 instruction pattern(s).
6741 (define_insn "*absdi2_sign_cc"
6742 [(set (reg CC_REGNUM)
6743 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6744 (match_operand:SI 1 "register_operand" "d") 0)
6745 (const_int 32)) (const_int 32)))
6747 (set (match_operand:DI 0 "register_operand" "=d")
6748 (abs:DI (sign_extend:DI (match_dup 1))))]
6749 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6751 [(set_attr "op_type" "RRE")
6752 (set_attr "z10prop" "z10_c")])
6754 (define_insn "*absdi2_sign"
6755 [(set (match_operand:DI 0 "register_operand" "=d")
6756 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6757 (clobber (reg:CC CC_REGNUM))]
6760 [(set_attr "op_type" "RRE")
6761 (set_attr "z10prop" "z10_c")])
6764 (define_insn "*abs<mode>2_cc"
6765 [(set (reg CC_REGNUM)
6766 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6768 (set (match_operand:GPR 0 "register_operand" "=d")
6769 (abs:GPR (match_dup 1)))]
6770 "s390_match_ccmode (insn, CCAmode)"
6772 [(set_attr "op_type" "RR<E>")
6773 (set_attr "z10prop" "z10_c")])
6776 (define_insn "*abs<mode>2_cconly"
6777 [(set (reg CC_REGNUM)
6778 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6780 (clobber (match_scratch:GPR 0 "=d"))]
6781 "s390_match_ccmode (insn, CCAmode)"
6783 [(set_attr "op_type" "RR<E>")
6784 (set_attr "z10prop" "z10_c")])
6787 (define_insn "abs<mode>2"
6788 [(set (match_operand:GPR 0 "register_operand" "=d")
6789 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6790 (clobber (reg:CC CC_REGNUM))]
6793 [(set_attr "op_type" "RR<E>")
6794 (set_attr "z10prop" "z10_c")])
6797 ; abs(df|sf)2 instruction pattern(s).
6800 (define_expand "abs<mode>2"
6802 [(set (match_operand:BFP 0 "register_operand" "=f")
6803 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6804 (clobber (reg:CC CC_REGNUM))])]
6808 ; lpxbr, lpdbr, lpebr
6809 (define_insn "*abs<mode>2_cc"
6810 [(set (reg CC_REGNUM)
6811 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6812 (match_operand:BFP 2 "const0_operand" "")))
6813 (set (match_operand:BFP 0 "register_operand" "=f")
6814 (abs:BFP (match_dup 1)))]
6815 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6817 [(set_attr "op_type" "RRE")
6818 (set_attr "type" "fsimp<mode>")])
6820 ; lpxbr, lpdbr, lpebr
6821 (define_insn "*abs<mode>2_cconly"
6822 [(set (reg CC_REGNUM)
6823 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6824 (match_operand:BFP 2 "const0_operand" "")))
6825 (clobber (match_scratch:BFP 0 "=f"))]
6826 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6828 [(set_attr "op_type" "RRE")
6829 (set_attr "type" "fsimp<mode>")])
6832 (define_insn "*abs<mode>2_nocc"
6833 [(set (match_operand:FP 0 "register_operand" "=f")
6834 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6837 [(set_attr "op_type" "RRE")
6838 (set_attr "type" "fsimp<mode>")])
6840 ; lpxbr, lpdbr, lpebr
6841 (define_insn "*abs<mode>2"
6842 [(set (match_operand:BFP 0 "register_operand" "=f")
6843 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6844 (clobber (reg:CC CC_REGNUM))]
6847 [(set_attr "op_type" "RRE")
6848 (set_attr "type" "fsimp<mode>")])
6852 ;;- Negated absolute value instructions
6859 (define_insn "*negabsdi2_sign_cc"
6860 [(set (reg CC_REGNUM)
6861 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6862 (match_operand:SI 1 "register_operand" "d") 0)
6863 (const_int 32)) (const_int 32))))
6865 (set (match_operand:DI 0 "register_operand" "=d")
6866 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6867 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6869 [(set_attr "op_type" "RRE")
6870 (set_attr "z10prop" "z10_c")])
6872 (define_insn "*negabsdi2_sign"
6873 [(set (match_operand:DI 0 "register_operand" "=d")
6874 (neg:DI (abs:DI (sign_extend:DI
6875 (match_operand:SI 1 "register_operand" "d")))))
6876 (clobber (reg:CC CC_REGNUM))]
6879 [(set_attr "op_type" "RRE")
6880 (set_attr "z10prop" "z10_c")])
6883 (define_insn "*negabs<mode>2_cc"
6884 [(set (reg CC_REGNUM)
6885 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6887 (set (match_operand:GPR 0 "register_operand" "=d")
6888 (neg:GPR (abs:GPR (match_dup 1))))]
6889 "s390_match_ccmode (insn, CCAmode)"
6891 [(set_attr "op_type" "RR<E>")
6892 (set_attr "z10prop" "z10_c")])
6895 (define_insn "*negabs<mode>2_cconly"
6896 [(set (reg CC_REGNUM)
6897 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6899 (clobber (match_scratch:GPR 0 "=d"))]
6900 "s390_match_ccmode (insn, CCAmode)"
6902 [(set_attr "op_type" "RR<E>")
6903 (set_attr "z10prop" "z10_c")])
6906 (define_insn "*negabs<mode>2"
6907 [(set (match_operand:GPR 0 "register_operand" "=d")
6908 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6909 (clobber (reg:CC CC_REGNUM))]
6912 [(set_attr "op_type" "RR<E>")
6913 (set_attr "z10prop" "z10_c")])
6919 ; lnxbr, lndbr, lnebr
6920 (define_insn "*negabs<mode>2_cc"
6921 [(set (reg CC_REGNUM)
6922 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6923 (match_operand:BFP 2 "const0_operand" "")))
6924 (set (match_operand:BFP 0 "register_operand" "=f")
6925 (neg:BFP (abs:BFP (match_dup 1))))]
6926 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6928 [(set_attr "op_type" "RRE")
6929 (set_attr "type" "fsimp<mode>")])
6931 ; lnxbr, lndbr, lnebr
6932 (define_insn "*negabs<mode>2_cconly"
6933 [(set (reg CC_REGNUM)
6934 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6935 (match_operand:BFP 2 "const0_operand" "")))
6936 (clobber (match_scratch:BFP 0 "=f"))]
6937 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6939 [(set_attr "op_type" "RRE")
6940 (set_attr "type" "fsimp<mode>")])
6943 (define_insn "*negabs<mode>2_nocc"
6944 [(set (match_operand:FP 0 "register_operand" "=f")
6945 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6948 [(set_attr "op_type" "RRE")
6949 (set_attr "type" "fsimp<mode>")])
6951 ; lnxbr, lndbr, lnebr
6952 (define_insn "*negabs<mode>2"
6953 [(set (match_operand:BFP 0 "register_operand" "=f")
6954 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6955 (clobber (reg:CC CC_REGNUM))]
6958 [(set_attr "op_type" "RRE")
6959 (set_attr "type" "fsimp<mode>")])
6962 ;;- Copy sign instructions
6966 (define_insn "copysign<mode>3"
6967 [(set (match_operand:FP 0 "register_operand" "=f")
6968 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
6969 (match_operand:FP 2 "register_operand" "f")]
6973 [(set_attr "op_type" "RRF")
6974 (set_attr "type" "fsimp<mode>")])
6977 ;;- Square root instructions.
6981 ; sqrt(df|sf)2 instruction pattern(s).
6984 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
6985 (define_insn "sqrt<mode>2"
6986 [(set (match_operand:BFP 0 "register_operand" "=f,f")
6987 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
6992 [(set_attr "op_type" "RRE,RXE")
6993 (set_attr "type" "fsqrt<mode>")])
6997 ;;- One complement instructions.
7001 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7004 (define_expand "one_cmpl<mode>2"
7006 [(set (match_operand:INT 0 "register_operand" "")
7007 (xor:INT (match_operand:INT 1 "register_operand" "")
7009 (clobber (reg:CC CC_REGNUM))])]
7015 ;; Find leftmost bit instructions.
7018 (define_expand "clzdi2"
7019 [(set (match_operand:DI 0 "register_operand" "=d")
7020 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7021 "TARGET_EXTIMM && TARGET_64BIT"
7023 rtx insn, clz_equal;
7024 rtx wide_reg = gen_reg_rtx (TImode);
7025 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7027 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7029 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7031 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7032 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7037 (define_insn "clztidi2"
7038 [(set (match_operand:TI 0 "register_operand" "=d")
7042 (xor:DI (match_operand:DI 1 "register_operand" "d")
7043 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7044 (subreg:SI (clz:DI (match_dup 1)) 4))))
7047 (zero_extend:TI (clz:DI (match_dup 1)))))
7048 (clobber (reg:CC CC_REGNUM))]
7049 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7050 == (unsigned HOST_WIDE_INT) 1 << 63
7051 && TARGET_EXTIMM && TARGET_64BIT"
7053 [(set_attr "op_type" "RRE")])
7057 ;;- Rotate instructions.
7061 ; rotl(di|si)3 instruction pattern(s).
7065 (define_insn "rotl<mode>3"
7066 [(set (match_operand:GPR 0 "register_operand" "=d")
7067 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7068 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7071 [(set_attr "op_type" "RSE")
7072 (set_attr "atype" "reg")
7073 (set_attr "z10prop" "z10_super_E1")])
7076 (define_insn "*rotl<mode>3_and"
7077 [(set (match_operand:GPR 0 "register_operand" "=d")
7078 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7079 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7080 (match_operand:SI 3 "const_int_operand" "n"))))]
7081 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7083 [(set_attr "op_type" "RSE")
7084 (set_attr "atype" "reg")
7085 (set_attr "z10prop" "z10_super_E1")])
7089 ;;- Shift instructions.
7093 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7096 (define_expand "<shift><mode>3"
7097 [(set (match_operand:DSI 0 "register_operand" "")
7098 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7099 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7104 (define_insn "*<shift>di3_31"
7105 [(set (match_operand:DI 0 "register_operand" "=d")
7106 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7107 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7110 [(set_attr "op_type" "RS")
7111 (set_attr "atype" "reg")])
7113 ; sll, srl, sllg, srlg
7114 (define_insn "*<shift><mode>3"
7115 [(set (match_operand:GPR 0 "register_operand" "=d")
7116 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7117 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7119 "s<lr>l<g>\t%0,<1>%Y2"
7120 [(set_attr "op_type" "RS<E>")
7121 (set_attr "atype" "reg")
7122 (set_attr "z10prop" "z10_super_E1")])
7125 (define_insn "*<shift>di3_31_and"
7126 [(set (match_operand:DI 0 "register_operand" "=d")
7127 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7128 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7129 (match_operand:SI 3 "const_int_operand" "n"))))]
7130 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7132 [(set_attr "op_type" "RS")
7133 (set_attr "atype" "reg")])
7135 ; sll, srl, sllg, srlg
7136 (define_insn "*<shift><mode>3_and"
7137 [(set (match_operand:GPR 0 "register_operand" "=d")
7138 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7139 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7140 (match_operand:SI 3 "const_int_operand" "n"))))]
7141 "(INTVAL (operands[3]) & 63) == 63"
7142 "s<lr>l<g>\t%0,<1>%Y2"
7143 [(set_attr "op_type" "RS<E>")
7144 (set_attr "atype" "reg")
7145 (set_attr "z10prop" "z10_super_E1")])
7148 ; ashr(di|si)3 instruction pattern(s).
7151 (define_expand "ashr<mode>3"
7153 [(set (match_operand:DSI 0 "register_operand" "")
7154 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7155 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7156 (clobber (reg:CC CC_REGNUM))])]
7160 (define_insn "*ashrdi3_cc_31"
7161 [(set (reg CC_REGNUM)
7162 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7163 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7165 (set (match_operand:DI 0 "register_operand" "=d")
7166 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7167 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7169 [(set_attr "op_type" "RS")
7170 (set_attr "atype" "reg")])
7172 (define_insn "*ashrdi3_cconly_31"
7173 [(set (reg CC_REGNUM)
7174 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7175 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7177 (clobber (match_scratch:DI 0 "=d"))]
7178 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7180 [(set_attr "op_type" "RS")
7181 (set_attr "atype" "reg")])
7183 (define_insn "*ashrdi3_31"
7184 [(set (match_operand:DI 0 "register_operand" "=d")
7185 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7186 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7187 (clobber (reg:CC CC_REGNUM))]
7190 [(set_attr "op_type" "RS")
7191 (set_attr "atype" "reg")])
7194 (define_insn "*ashr<mode>3_cc"
7195 [(set (reg CC_REGNUM)
7196 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7197 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7199 (set (match_operand:GPR 0 "register_operand" "=d")
7200 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7201 "s390_match_ccmode(insn, CCSmode)"
7203 [(set_attr "op_type" "RS<E>")
7204 (set_attr "atype" "reg")
7205 (set_attr "z10prop" "z10_super_E1")])
7208 (define_insn "*ashr<mode>3_cconly"
7209 [(set (reg CC_REGNUM)
7210 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7211 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7213 (clobber (match_scratch:GPR 0 "=d"))]
7214 "s390_match_ccmode(insn, CCSmode)"
7216 [(set_attr "op_type" "RS<E>")
7217 (set_attr "atype" "reg")
7218 (set_attr "z10prop" "z10_super_E1")])
7221 (define_insn "*ashr<mode>3"
7222 [(set (match_operand:GPR 0 "register_operand" "=d")
7223 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7224 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7225 (clobber (reg:CC CC_REGNUM))]
7228 [(set_attr "op_type" "RS<E>")
7229 (set_attr "atype" "reg")
7230 (set_attr "z10prop" "z10_super_E1")])
7233 ; shift pattern with implicit ANDs
7235 (define_insn "*ashrdi3_cc_31_and"
7236 [(set (reg CC_REGNUM)
7237 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7238 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7239 (match_operand:SI 3 "const_int_operand" "n")))
7241 (set (match_operand:DI 0 "register_operand" "=d")
7242 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7243 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7244 && (INTVAL (operands[3]) & 63) == 63"
7246 [(set_attr "op_type" "RS")
7247 (set_attr "atype" "reg")])
7249 (define_insn "*ashrdi3_cconly_31_and"
7250 [(set (reg CC_REGNUM)
7251 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7252 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7253 (match_operand:SI 3 "const_int_operand" "n")))
7255 (clobber (match_scratch:DI 0 "=d"))]
7256 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7257 && (INTVAL (operands[3]) & 63) == 63"
7259 [(set_attr "op_type" "RS")
7260 (set_attr "atype" "reg")])
7262 (define_insn "*ashrdi3_31_and"
7263 [(set (match_operand:DI 0 "register_operand" "=d")
7264 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7265 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7266 (match_operand:SI 3 "const_int_operand" "n"))))
7267 (clobber (reg:CC CC_REGNUM))]
7268 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7270 [(set_attr "op_type" "RS")
7271 (set_attr "atype" "reg")])
7274 (define_insn "*ashr<mode>3_cc_and"
7275 [(set (reg CC_REGNUM)
7276 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7277 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7278 (match_operand:SI 3 "const_int_operand" "n")))
7280 (set (match_operand:GPR 0 "register_operand" "=d")
7281 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7282 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7284 [(set_attr "op_type" "RS<E>")
7285 (set_attr "atype" "reg")
7286 (set_attr "z10prop" "z10_super_E1")])
7289 (define_insn "*ashr<mode>3_cconly_and"
7290 [(set (reg CC_REGNUM)
7291 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7292 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7293 (match_operand:SI 3 "const_int_operand" "n")))
7295 (clobber (match_scratch:GPR 0 "=d"))]
7296 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7298 [(set_attr "op_type" "RS<E>")
7299 (set_attr "atype" "reg")
7300 (set_attr "z10prop" "z10_super_E1")])
7303 (define_insn "*ashr<mode>3_and"
7304 [(set (match_operand:GPR 0 "register_operand" "=d")
7305 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7306 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7307 (match_operand:SI 3 "const_int_operand" "n"))))
7308 (clobber (reg:CC CC_REGNUM))]
7309 "(INTVAL (operands[3]) & 63) == 63"
7311 [(set_attr "op_type" "RS<E>")
7312 (set_attr "atype" "reg")
7313 (set_attr "z10prop" "z10_super_E1")])
7317 ;; Branch instruction patterns.
7320 (define_expand "cbranch<mode>4"
7322 (if_then_else (match_operator 0 "comparison_operator"
7323 [(match_operand:GPR 1 "register_operand" "")
7324 (match_operand:GPR 2 "general_operand" "")])
7325 (label_ref (match_operand 3 "" ""))
7328 "s390_emit_jump (operands[3],
7329 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7332 (define_expand "cbranch<mode>4"
7334 (if_then_else (match_operator 0 "comparison_operator"
7335 [(match_operand:FP 1 "register_operand" "")
7336 (match_operand:FP 2 "general_operand" "")])
7337 (label_ref (match_operand 3 "" ""))
7340 "s390_emit_jump (operands[3],
7341 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7344 (define_expand "cbranchcc4"
7346 (if_then_else (match_operator 0 "s390_eqne_operator"
7347 [(match_operand 1 "cc_reg_operand" "")
7348 (match_operand 2 "const0_operand" "")])
7349 (label_ref (match_operand 3 "" ""))
7352 "s390_emit_jump (operands[3],
7353 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7359 ;;- Conditional jump instructions.
7362 (define_insn "*cjump_64"
7365 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7366 (label_ref (match_operand 0 "" ""))
7370 if (get_attr_length (insn) == 4)
7373 return "jg%C1\t%l0";
7375 [(set_attr "op_type" "RI")
7376 (set_attr "type" "branch")
7377 (set (attr "length")
7378 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7379 (const_int 4) (const_int 6)))])
7381 (define_insn "*cjump_31"
7384 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7385 (label_ref (match_operand 0 "" ""))
7389 gcc_assert (get_attr_length (insn) == 4);
7392 [(set_attr "op_type" "RI")
7393 (set_attr "type" "branch")
7394 (set (attr "length")
7395 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7396 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7397 (const_int 4) (const_int 6))
7398 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7399 (const_int 4) (const_int 8))))])
7401 (define_insn "*cjump_long"
7404 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7405 (match_operand 0 "address_operand" "U")
7409 if (get_attr_op_type (insn) == OP_TYPE_RR)
7414 [(set (attr "op_type")
7415 (if_then_else (match_operand 0 "register_operand" "")
7416 (const_string "RR") (const_string "RX")))
7417 (set_attr "type" "branch")
7418 (set_attr "atype" "agen")])
7422 ;;- Negated conditional jump instructions.
7425 (define_insn "*icjump_64"
7428 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7430 (label_ref (match_operand 0 "" ""))))]
7433 if (get_attr_length (insn) == 4)
7436 return "jg%D1\t%l0";
7438 [(set_attr "op_type" "RI")
7439 (set_attr "type" "branch")
7440 (set (attr "length")
7441 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7442 (const_int 4) (const_int 6)))])
7444 (define_insn "*icjump_31"
7447 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7449 (label_ref (match_operand 0 "" ""))))]
7452 gcc_assert (get_attr_length (insn) == 4);
7455 [(set_attr "op_type" "RI")
7456 (set_attr "type" "branch")
7457 (set (attr "length")
7458 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7459 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7460 (const_int 4) (const_int 6))
7461 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7462 (const_int 4) (const_int 8))))])
7464 (define_insn "*icjump_long"
7467 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7469 (match_operand 0 "address_operand" "U")))]
7472 if (get_attr_op_type (insn) == OP_TYPE_RR)
7477 [(set (attr "op_type")
7478 (if_then_else (match_operand 0 "register_operand" "")
7479 (const_string "RR") (const_string "RX")))
7480 (set_attr "type" "branch")
7481 (set_attr "atype" "agen")])
7484 ;;- Trap instructions.
7488 [(trap_if (const_int 1) (const_int 0))]
7491 [(set_attr "op_type" "RI")
7492 (set_attr "type" "branch")])
7494 (define_expand "ctrap<mode>4"
7495 [(trap_if (match_operator 0 "comparison_operator"
7496 [(match_operand:GPR 1 "register_operand" "")
7497 (match_operand:GPR 2 "general_operand" "")])
7498 (match_operand 3 "const0_operand" ""))]
7501 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7502 operands[1], operands[2]);
7503 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7507 (define_expand "ctrap<mode>4"
7508 [(trap_if (match_operator 0 "comparison_operator"
7509 [(match_operand:FP 1 "register_operand" "")
7510 (match_operand:FP 2 "general_operand" "")])
7511 (match_operand 3 "const0_operand" ""))]
7514 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7515 operands[1], operands[2]);
7516 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7520 (define_insn "condtrap"
7521 [(trap_if (match_operator 0 "s390_comparison"
7522 [(match_operand 1 "cc_reg_operand" "c")
7527 [(set_attr "op_type" "RI")
7528 (set_attr "type" "branch")])
7530 ; crt, cgrt, cit, cgit
7531 (define_insn "*cmp_and_trap_signed_int<mode>"
7532 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7533 [(match_operand:GPR 1 "register_operand" "d,d")
7534 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7540 [(set_attr "op_type" "RRF,RIE")
7541 (set_attr "type" "branch")
7542 (set_attr "z10prop" "z10_super_c,z10_super")])
7544 ; clrt, clgrt, clfit, clgit
7545 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7546 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7547 [(match_operand:GPR 1 "register_operand" "d,d")
7548 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7553 cl<gf>it%C0\t%1,%x2"
7554 [(set_attr "op_type" "RRF,RIE")
7555 (set_attr "type" "branch")
7556 (set_attr "z10prop" "z10_super_c,z10_super")])
7559 ;;- Loop instructions.
7561 ;; This is all complicated by the fact that since this is a jump insn
7562 ;; we must handle our own output reloads.
7564 (define_expand "doloop_end"
7565 [(use (match_operand 0 "" "")) ; loop pseudo
7566 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7567 (use (match_operand 2 "" "")) ; max iterations
7568 (use (match_operand 3 "" "")) ; loop level
7569 (use (match_operand 4 "" ""))] ; label
7572 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7573 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7574 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7575 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7576 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7577 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7584 (define_insn_and_split "doloop_si64"
7587 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7589 (label_ref (match_operand 0 "" ""))
7591 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7592 (plus:SI (match_dup 1) (const_int -1)))
7593 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7594 (clobber (reg:CC CC_REGNUM))]
7597 if (which_alternative != 0)
7599 else if (get_attr_length (insn) == 4)
7600 return "brct\t%1,%l0";
7602 return "ahi\t%1,-1\;jgne\t%l0";
7604 "&& reload_completed
7605 && (! REG_P (operands[2])
7606 || ! rtx_equal_p (operands[1], operands[2]))"
7607 [(set (match_dup 3) (match_dup 1))
7608 (parallel [(set (reg:CCAN CC_REGNUM)
7609 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7611 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7612 (set (match_dup 2) (match_dup 3))
7613 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7614 (label_ref (match_dup 0))
7617 [(set_attr "op_type" "RI")
7618 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7619 ; hurt us in the (rare) case of ahi.
7620 (set_attr "z10prop" "z10_super_E1")
7621 (set_attr "type" "branch")
7622 (set (attr "length")
7623 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7624 (const_int 4) (const_int 10)))])
7626 (define_insn_and_split "doloop_si31"
7629 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7631 (label_ref (match_operand 0 "" ""))
7633 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7634 (plus:SI (match_dup 1) (const_int -1)))
7635 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7636 (clobber (reg:CC CC_REGNUM))]
7639 if (which_alternative != 0)
7641 else if (get_attr_length (insn) == 4)
7642 return "brct\t%1,%l0";
7646 "&& reload_completed
7647 && (! REG_P (operands[2])
7648 || ! rtx_equal_p (operands[1], operands[2]))"
7649 [(set (match_dup 3) (match_dup 1))
7650 (parallel [(set (reg:CCAN CC_REGNUM)
7651 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7653 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7654 (set (match_dup 2) (match_dup 3))
7655 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7656 (label_ref (match_dup 0))
7659 [(set_attr "op_type" "RI")
7660 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7661 ; hurt us in the (rare) case of ahi.
7662 (set_attr "z10prop" "z10_super_E1")
7663 (set_attr "type" "branch")
7664 (set (attr "length")
7665 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7666 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7667 (const_int 4) (const_int 6))
7668 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7669 (const_int 4) (const_int 8))))])
7671 (define_insn "*doloop_si_long"
7674 (ne (match_operand:SI 1 "register_operand" "d")
7676 (match_operand 0 "address_operand" "U")
7678 (set (match_operand:SI 2 "register_operand" "=1")
7679 (plus:SI (match_dup 1) (const_int -1)))
7680 (clobber (match_scratch:SI 3 "=X"))
7681 (clobber (reg:CC CC_REGNUM))]
7684 if (get_attr_op_type (insn) == OP_TYPE_RR)
7685 return "bctr\t%1,%0";
7687 return "bct\t%1,%a0";
7689 [(set (attr "op_type")
7690 (if_then_else (match_operand 0 "register_operand" "")
7691 (const_string "RR") (const_string "RX")))
7692 (set_attr "type" "branch")
7693 (set_attr "atype" "agen")
7694 (set_attr "z10prop" "z10_c")])
7696 (define_insn_and_split "doloop_di"
7699 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7701 (label_ref (match_operand 0 "" ""))
7703 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7704 (plus:DI (match_dup 1) (const_int -1)))
7705 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7706 (clobber (reg:CC CC_REGNUM))]
7709 if (which_alternative != 0)
7711 else if (get_attr_length (insn) == 4)
7712 return "brctg\t%1,%l0";
7714 return "aghi\t%1,-1\;jgne\t%l0";
7716 "&& reload_completed
7717 && (! REG_P (operands[2])
7718 || ! rtx_equal_p (operands[1], operands[2]))"
7719 [(set (match_dup 3) (match_dup 1))
7720 (parallel [(set (reg:CCAN CC_REGNUM)
7721 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7723 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7724 (set (match_dup 2) (match_dup 3))
7725 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7726 (label_ref (match_dup 0))
7729 [(set_attr "op_type" "RI")
7730 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7731 ; hurt us in the (rare) case of ahi.
7732 (set_attr "z10prop" "z10_super_E1")
7733 (set_attr "type" "branch")
7734 (set (attr "length")
7735 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7736 (const_int 4) (const_int 10)))])
7739 ;;- Unconditional jump instructions.
7743 ; jump instruction pattern(s).
7746 (define_expand "jump"
7747 [(match_operand 0 "" "")]
7749 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7751 (define_insn "*jump64"
7752 [(set (pc) (label_ref (match_operand 0 "" "")))]
7755 if (get_attr_length (insn) == 4)
7760 [(set_attr "op_type" "RI")
7761 (set_attr "type" "branch")
7762 (set (attr "length")
7763 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7764 (const_int 4) (const_int 6)))])
7766 (define_insn "*jump31"
7767 [(set (pc) (label_ref (match_operand 0 "" "")))]
7770 gcc_assert (get_attr_length (insn) == 4);
7773 [(set_attr "op_type" "RI")
7774 (set_attr "type" "branch")
7775 (set (attr "length")
7776 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7777 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7778 (const_int 4) (const_int 6))
7779 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7780 (const_int 4) (const_int 8))))])
7783 ; indirect-jump instruction pattern(s).
7786 (define_insn "indirect_jump"
7787 [(set (pc) (match_operand 0 "address_operand" "U"))]
7790 if (get_attr_op_type (insn) == OP_TYPE_RR)
7795 [(set (attr "op_type")
7796 (if_then_else (match_operand 0 "register_operand" "")
7797 (const_string "RR") (const_string "RX")))
7798 (set_attr "type" "branch")
7799 (set_attr "atype" "agen")])
7802 ; casesi instruction pattern(s).
7805 (define_insn "casesi_jump"
7806 [(set (pc) (match_operand 0 "address_operand" "U"))
7807 (use (label_ref (match_operand 1 "" "")))]
7810 if (get_attr_op_type (insn) == OP_TYPE_RR)
7815 [(set (attr "op_type")
7816 (if_then_else (match_operand 0 "register_operand" "")
7817 (const_string "RR") (const_string "RX")))
7818 (set_attr "type" "branch")
7819 (set_attr "atype" "agen")])
7821 (define_expand "casesi"
7822 [(match_operand:SI 0 "general_operand" "")
7823 (match_operand:SI 1 "general_operand" "")
7824 (match_operand:SI 2 "general_operand" "")
7825 (label_ref (match_operand 3 "" ""))
7826 (label_ref (match_operand 4 "" ""))]
7829 rtx index = gen_reg_rtx (SImode);
7830 rtx base = gen_reg_rtx (Pmode);
7831 rtx target = gen_reg_rtx (Pmode);
7833 emit_move_insn (index, operands[0]);
7834 emit_insn (gen_subsi3 (index, index, operands[1]));
7835 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7838 if (Pmode != SImode)
7839 index = convert_to_mode (Pmode, index, 1);
7840 if (GET_CODE (index) != REG)
7841 index = copy_to_mode_reg (Pmode, index);
7844 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7846 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7848 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7850 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7851 emit_move_insn (target, index);
7854 target = gen_rtx_PLUS (Pmode, base, target);
7855 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7862 ;;- Jump to subroutine.
7867 ; untyped call instruction pattern(s).
7870 ;; Call subroutine returning any type.
7871 (define_expand "untyped_call"
7872 [(parallel [(call (match_operand 0 "" "")
7874 (match_operand 1 "" "")
7875 (match_operand 2 "" "")])]
7880 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7882 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7884 rtx set = XVECEXP (operands[2], 0, i);
7885 emit_move_insn (SET_DEST (set), SET_SRC (set));
7888 /* The optimizer does not know that the call sets the function value
7889 registers we stored in the result block. We avoid problems by
7890 claiming that all hard registers are used and clobbered at this
7892 emit_insn (gen_blockage ());
7897 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7898 ;; all of memory. This blocks insns from being moved across this point.
7900 (define_insn "blockage"
7901 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7904 [(set_attr "type" "none")
7905 (set_attr "length" "0")])
7911 (define_expand "sibcall"
7912 [(call (match_operand 0 "" "")
7913 (match_operand 1 "" ""))]
7916 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7920 (define_insn "*sibcall_br"
7921 [(call (mem:QI (reg SIBCALL_REGNUM))
7922 (match_operand 0 "const_int_operand" "n"))]
7923 "SIBLING_CALL_P (insn)
7924 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7926 [(set_attr "op_type" "RR")
7927 (set_attr "type" "branch")
7928 (set_attr "atype" "agen")])
7930 (define_insn "*sibcall_brc"
7931 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7932 (match_operand 1 "const_int_operand" "n"))]
7933 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7935 [(set_attr "op_type" "RI")
7936 (set_attr "type" "branch")])
7938 (define_insn "*sibcall_brcl"
7939 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7940 (match_operand 1 "const_int_operand" "n"))]
7941 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7943 [(set_attr "op_type" "RIL")
7944 (set_attr "type" "branch")])
7947 ; sibcall_value patterns
7950 (define_expand "sibcall_value"
7951 [(set (match_operand 0 "" "")
7952 (call (match_operand 1 "" "")
7953 (match_operand 2 "" "")))]
7956 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7960 (define_insn "*sibcall_value_br"
7961 [(set (match_operand 0 "" "")
7962 (call (mem:QI (reg SIBCALL_REGNUM))
7963 (match_operand 1 "const_int_operand" "n")))]
7964 "SIBLING_CALL_P (insn)
7965 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7967 [(set_attr "op_type" "RR")
7968 (set_attr "type" "branch")
7969 (set_attr "atype" "agen")])
7971 (define_insn "*sibcall_value_brc"
7972 [(set (match_operand 0 "" "")
7973 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7974 (match_operand 2 "const_int_operand" "n")))]
7975 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7977 [(set_attr "op_type" "RI")
7978 (set_attr "type" "branch")])
7980 (define_insn "*sibcall_value_brcl"
7981 [(set (match_operand 0 "" "")
7982 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7983 (match_operand 2 "const_int_operand" "n")))]
7984 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7986 [(set_attr "op_type" "RIL")
7987 (set_attr "type" "branch")])
7991 ; call instruction pattern(s).
7994 (define_expand "call"
7995 [(call (match_operand 0 "" "")
7996 (match_operand 1 "" ""))
7997 (use (match_operand 2 "" ""))]
8000 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8001 gen_rtx_REG (Pmode, RETURN_REGNUM));
8005 (define_insn "*bras"
8006 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8007 (match_operand 1 "const_int_operand" "n"))
8008 (clobber (match_operand 2 "register_operand" "=r"))]
8009 "!SIBLING_CALL_P (insn)
8010 && TARGET_SMALL_EXEC
8011 && GET_MODE (operands[2]) == Pmode"
8013 [(set_attr "op_type" "RI")
8014 (set_attr "type" "jsr")])
8016 (define_insn "*brasl"
8017 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8018 (match_operand 1 "const_int_operand" "n"))
8019 (clobber (match_operand 2 "register_operand" "=r"))]
8020 "!SIBLING_CALL_P (insn)
8022 && GET_MODE (operands[2]) == Pmode"
8024 [(set_attr "op_type" "RIL")
8025 (set_attr "type" "jsr")])
8027 (define_insn "*basr"
8028 [(call (mem:QI (match_operand 0 "address_operand" "U"))
8029 (match_operand 1 "const_int_operand" "n"))
8030 (clobber (match_operand 2 "register_operand" "=r"))]
8031 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8033 if (get_attr_op_type (insn) == OP_TYPE_RR)
8034 return "basr\t%2,%0";
8036 return "bas\t%2,%a0";
8038 [(set (attr "op_type")
8039 (if_then_else (match_operand 0 "register_operand" "")
8040 (const_string "RR") (const_string "RX")))
8041 (set_attr "type" "jsr")
8042 (set_attr "atype" "agen")])
8045 ; call_value instruction pattern(s).
8048 (define_expand "call_value"
8049 [(set (match_operand 0 "" "")
8050 (call (match_operand 1 "" "")
8051 (match_operand 2 "" "")))
8052 (use (match_operand 3 "" ""))]
8055 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8056 gen_rtx_REG (Pmode, RETURN_REGNUM));
8060 (define_insn "*bras_r"
8061 [(set (match_operand 0 "" "")
8062 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8063 (match_operand:SI 2 "const_int_operand" "n")))
8064 (clobber (match_operand 3 "register_operand" "=r"))]
8065 "!SIBLING_CALL_P (insn)
8066 && TARGET_SMALL_EXEC
8067 && GET_MODE (operands[3]) == Pmode"
8069 [(set_attr "op_type" "RI")
8070 (set_attr "type" "jsr")])
8072 (define_insn "*brasl_r"
8073 [(set (match_operand 0 "" "")
8074 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8075 (match_operand 2 "const_int_operand" "n")))
8076 (clobber (match_operand 3 "register_operand" "=r"))]
8077 "!SIBLING_CALL_P (insn)
8079 && GET_MODE (operands[3]) == Pmode"
8081 [(set_attr "op_type" "RIL")
8082 (set_attr "type" "jsr")])
8084 (define_insn "*basr_r"
8085 [(set (match_operand 0 "" "")
8086 (call (mem:QI (match_operand 1 "address_operand" "U"))
8087 (match_operand 2 "const_int_operand" "n")))
8088 (clobber (match_operand 3 "register_operand" "=r"))]
8089 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8091 if (get_attr_op_type (insn) == OP_TYPE_RR)
8092 return "basr\t%3,%1";
8094 return "bas\t%3,%a1";
8096 [(set (attr "op_type")
8097 (if_then_else (match_operand 1 "register_operand" "")
8098 (const_string "RR") (const_string "RX")))
8099 (set_attr "type" "jsr")
8100 (set_attr "atype" "agen")])
8103 ;;- Thread-local storage support.
8106 (define_expand "get_tp_64"
8107 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8111 (define_expand "get_tp_31"
8112 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8116 (define_expand "set_tp_64"
8117 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8118 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8122 (define_expand "set_tp_31"
8123 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8124 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8128 (define_insn "*set_tp"
8129 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8132 [(set_attr "type" "none")
8133 (set_attr "length" "0")])
8135 (define_insn "*tls_load_64"
8136 [(set (match_operand:DI 0 "register_operand" "=d")
8137 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8138 (match_operand:DI 2 "" "")]
8142 [(set_attr "op_type" "RXE")
8143 (set_attr "z10prop" "z10_fwd_A3")])
8145 (define_insn "*tls_load_31"
8146 [(set (match_operand:SI 0 "register_operand" "=d,d")
8147 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8148 (match_operand:SI 2 "" "")]
8154 [(set_attr "op_type" "RX,RXY")
8155 (set_attr "type" "load")
8156 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8158 (define_insn "*bras_tls"
8159 [(set (match_operand 0 "" "")
8160 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8161 (match_operand 2 "const_int_operand" "n")))
8162 (clobber (match_operand 3 "register_operand" "=r"))
8163 (use (match_operand 4 "" ""))]
8164 "!SIBLING_CALL_P (insn)
8165 && TARGET_SMALL_EXEC
8166 && GET_MODE (operands[3]) == Pmode"
8168 [(set_attr "op_type" "RI")
8169 (set_attr "type" "jsr")])
8171 (define_insn "*brasl_tls"
8172 [(set (match_operand 0 "" "")
8173 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8174 (match_operand 2 "const_int_operand" "n")))
8175 (clobber (match_operand 3 "register_operand" "=r"))
8176 (use (match_operand 4 "" ""))]
8177 "!SIBLING_CALL_P (insn)
8179 && GET_MODE (operands[3]) == Pmode"
8181 [(set_attr "op_type" "RIL")
8182 (set_attr "type" "jsr")])
8184 (define_insn "*basr_tls"
8185 [(set (match_operand 0 "" "")
8186 (call (mem:QI (match_operand 1 "address_operand" "U"))
8187 (match_operand 2 "const_int_operand" "n")))
8188 (clobber (match_operand 3 "register_operand" "=r"))
8189 (use (match_operand 4 "" ""))]
8190 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8192 if (get_attr_op_type (insn) == OP_TYPE_RR)
8193 return "basr\t%3,%1%J4";
8195 return "bas\t%3,%a1%J4";
8197 [(set (attr "op_type")
8198 (if_then_else (match_operand 1 "register_operand" "")
8199 (const_string "RR") (const_string "RX")))
8200 (set_attr "type" "jsr")
8201 (set_attr "atype" "agen")])
8204 ;;- Atomic operations
8208 ; memory barrier pattern.
8211 (define_expand "memory_barrier"
8213 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8216 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8217 MEM_VOLATILE_P (operands[0]) = 1;
8220 (define_insn "*memory_barrier"
8221 [(set (match_operand:BLK 0 "" "")
8222 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8225 [(set_attr "op_type" "RR")])
8227 ; Although bcr is superscalar on Z10, this variant will never become part of
8228 ; an execution group.
8231 ; compare and swap patterns.
8234 (define_expand "sync_compare_and_swap<mode>"
8236 [(set (match_operand:TDSI 0 "register_operand" "")
8237 (match_operand:TDSI 1 "memory_operand" ""))
8239 (unspec_volatile:TDSI
8241 (match_operand:TDSI 2 "register_operand" "")
8242 (match_operand:TDSI 3 "register_operand" "")]
8244 (set (reg:CCZ1 CC_REGNUM)
8245 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8248 (define_expand "sync_compare_and_swap<mode>"
8250 [(set (match_operand:HQI 0 "register_operand" "")
8251 (match_operand:HQI 1 "memory_operand" ""))
8253 (unspec_volatile:HQI
8255 (match_operand:HQI 2 "general_operand" "")
8256 (match_operand:HQI 3 "general_operand" "")]
8258 (clobber (reg:CC CC_REGNUM))])]
8260 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8261 operands[2], operands[3]); DONE;")
8264 (define_insn "*sync_compare_and_swap<mode>"
8265 [(set (match_operand:DP 0 "register_operand" "=r")
8266 (match_operand:DP 1 "memory_operand" "+Q"))
8270 (match_operand:DP 2 "register_operand" "0")
8271 (match_operand:DP 3 "register_operand" "r")]
8273 (set (reg:CCZ1 CC_REGNUM)
8274 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8276 "cds<tg>\t%0,%3,%S1"
8277 [(set_attr "op_type" "RS<TE>")
8278 (set_attr "type" "sem")])
8281 (define_insn "*sync_compare_and_swap<mode>"
8282 [(set (match_operand:GPR 0 "register_operand" "=r")
8283 (match_operand:GPR 1 "memory_operand" "+Q"))
8285 (unspec_volatile:GPR
8287 (match_operand:GPR 2 "register_operand" "0")
8288 (match_operand:GPR 3 "register_operand" "r")]
8290 (set (reg:CCZ1 CC_REGNUM)
8291 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8294 [(set_attr "op_type" "RS<E>")
8295 (set_attr "type" "sem")])
8299 ; Other atomic instruction patterns.
8302 (define_expand "sync_lock_test_and_set<mode>"
8303 [(match_operand:HQI 0 "register_operand")
8304 (match_operand:HQI 1 "memory_operand")
8305 (match_operand:HQI 2 "general_operand")]
8307 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8308 operands[2], false); DONE;")
8310 (define_expand "sync_<atomic><mode>"
8311 [(set (match_operand:HQI 0 "memory_operand")
8312 (ATOMIC:HQI (match_dup 0)
8313 (match_operand:HQI 1 "general_operand")))]
8315 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8316 operands[1], false); DONE;")
8318 (define_expand "sync_old_<atomic><mode>"
8319 [(set (match_operand:HQI 0 "register_operand")
8320 (match_operand:HQI 1 "memory_operand"))
8322 (ATOMIC:HQI (match_dup 1)
8323 (match_operand:HQI 2 "general_operand")))]
8325 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8326 operands[2], false); DONE;")
8328 (define_expand "sync_new_<atomic><mode>"
8329 [(set (match_operand:HQI 0 "register_operand")
8330 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8331 (match_operand:HQI 2 "general_operand")))
8332 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8334 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8335 operands[2], true); DONE;")
8338 ;;- Miscellaneous instructions.
8342 ; allocate stack instruction pattern(s).
8345 (define_expand "allocate_stack"
8346 [(match_operand 0 "general_operand" "")
8347 (match_operand 1 "general_operand" "")]
8350 rtx temp = gen_reg_rtx (Pmode);
8352 emit_move_insn (temp, s390_back_chain_rtx ());
8353 anti_adjust_stack (operands[1]);
8354 emit_move_insn (s390_back_chain_rtx (), temp);
8356 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8362 ; setjmp instruction pattern.
8365 (define_expand "builtin_setjmp_receiver"
8366 [(match_operand 0 "" "")]
8369 emit_insn (s390_load_got ());
8370 emit_use (pic_offset_table_rtx);
8374 ;; These patterns say how to save and restore the stack pointer. We need not
8375 ;; save the stack pointer at function level since we are careful to
8376 ;; preserve the backchain. At block level, we have to restore the backchain
8377 ;; when we restore the stack pointer.
8379 ;; For nonlocal gotos, we must save both the stack pointer and its
8380 ;; backchain and restore both. Note that in the nonlocal case, the
8381 ;; save area is a memory location.
8383 (define_expand "save_stack_function"
8384 [(match_operand 0 "general_operand" "")
8385 (match_operand 1 "general_operand" "")]
8389 (define_expand "restore_stack_function"
8390 [(match_operand 0 "general_operand" "")
8391 (match_operand 1 "general_operand" "")]
8395 (define_expand "restore_stack_block"
8396 [(match_operand 0 "register_operand" "")
8397 (match_operand 1 "register_operand" "")]
8400 rtx temp = gen_reg_rtx (Pmode);
8402 emit_move_insn (temp, s390_back_chain_rtx ());
8403 emit_move_insn (operands[0], operands[1]);
8404 emit_move_insn (s390_back_chain_rtx (), temp);
8409 (define_expand "save_stack_nonlocal"
8410 [(match_operand 0 "memory_operand" "")
8411 (match_operand 1 "register_operand" "")]
8414 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8415 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8417 /* Copy the backchain to the first word, sp to the second and the
8418 literal pool base to the third. */
8420 if (TARGET_BACKCHAIN)
8422 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
8423 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
8426 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
8427 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
8432 (define_expand "restore_stack_nonlocal"
8433 [(match_operand 0 "register_operand" "")
8434 (match_operand 1 "memory_operand" "")]
8437 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8438 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8439 rtx temp = NULL_RTX;
8441 /* Restore the backchain from the first word, sp from the second and the
8442 literal pool base from the third. */
8444 if (TARGET_BACKCHAIN)
8445 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
8447 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
8448 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
8451 emit_move_insn (s390_back_chain_rtx (), temp);
8457 (define_expand "exception_receiver"
8461 s390_set_has_landing_pad_p (true);
8466 ; nop instruction pattern(s).
8473 [(set_attr "op_type" "RR")
8474 (set_attr "z10prop" "z10_fr_E1")])
8480 [(set_attr "op_type" "RR")])
8484 ; Special literal pool access instruction pattern(s).
8487 (define_insn "*pool_entry"
8488 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8489 UNSPECV_POOL_ENTRY)]
8492 enum machine_mode mode = GET_MODE (PATTERN (insn));
8493 unsigned int align = GET_MODE_BITSIZE (mode);
8494 s390_output_pool_entry (operands[0], mode, align);
8497 [(set (attr "length")
8498 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8500 (define_insn "pool_align"
8501 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8502 UNSPECV_POOL_ALIGN)]
8505 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8507 (define_insn "pool_section_start"
8508 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8511 [(set_attr "length" "0")])
8513 (define_insn "pool_section_end"
8514 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8517 [(set_attr "length" "0")])
8519 (define_insn "main_base_31_small"
8520 [(set (match_operand 0 "register_operand" "=a")
8521 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8522 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8524 [(set_attr "op_type" "RR")
8525 (set_attr "type" "la")])
8527 (define_insn "main_base_31_large"
8528 [(set (match_operand 0 "register_operand" "=a")
8529 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8530 (set (pc) (label_ref (match_operand 2 "" "")))]
8531 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8533 [(set_attr "op_type" "RI")])
8535 (define_insn "main_base_64"
8536 [(set (match_operand 0 "register_operand" "=a")
8537 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8538 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8540 [(set_attr "op_type" "RIL")
8541 (set_attr "type" "larl")
8542 (set_attr "z10prop" "z10_fwd_A1")])
8544 (define_insn "main_pool"
8545 [(set (match_operand 0 "register_operand" "=a")
8546 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8547 "GET_MODE (operands[0]) == Pmode"
8552 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8553 (const_string "larl") (const_string "la")))])
8555 (define_insn "reload_base_31"
8556 [(set (match_operand 0 "register_operand" "=a")
8557 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8558 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8559 "basr\t%0,0\;la\t%0,%1-.(%0)"
8560 [(set_attr "length" "6")
8561 (set_attr "type" "la")])
8563 (define_insn "reload_base_64"
8564 [(set (match_operand 0 "register_operand" "=a")
8565 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8566 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8568 [(set_attr "op_type" "RIL")
8569 (set_attr "type" "larl")
8570 (set_attr "z10prop" "z10_fwd_A1")])
8573 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8578 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8581 ;; Insns related to generating the function prologue and epilogue.
8585 (define_expand "prologue"
8586 [(use (const_int 0))]
8588 "s390_emit_prologue (); DONE;")
8590 (define_expand "epilogue"
8591 [(use (const_int 1))]
8593 "s390_emit_epilogue (false); DONE;")
8595 (define_expand "sibcall_epilogue"
8596 [(use (const_int 0))]
8598 "s390_emit_epilogue (true); DONE;")
8600 (define_insn "*return"
8602 (use (match_operand 0 "register_operand" "a"))]
8603 "GET_MODE (operands[0]) == Pmode"
8605 [(set_attr "op_type" "RR")
8606 (set_attr "type" "jsr")
8607 (set_attr "atype" "agen")])
8610 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8611 ;; pointer. This is used for compatibility.
8613 (define_expand "ptr_extend"
8614 [(set (match_operand:DI 0 "register_operand" "=r")
8615 (match_operand:SI 1 "register_operand" "r"))]
8618 emit_insn (gen_anddi3 (operands[0],
8619 gen_lowpart (DImode, operands[1]),
8620 GEN_INT (0x7fffffff)));
8624 ;; Instruction definition to expand eh_return macro to support
8625 ;; swapping in special linkage return addresses.
8627 (define_expand "eh_return"
8628 [(use (match_operand 0 "register_operand" ""))]
8631 s390_emit_tpf_eh_return (operands[0]);
8636 ; Stack Protector Patterns
8639 (define_expand "stack_protect_set"
8640 [(set (match_operand 0 "memory_operand" "")
8641 (match_operand 1 "memory_operand" ""))]
8644 #ifdef TARGET_THREAD_SSP_OFFSET
8646 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8647 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8650 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8652 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8657 (define_insn "stack_protect_set<mode>"
8658 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8659 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8661 "mvc\t%O0(%G0,%R0),%S1"
8662 [(set_attr "op_type" "SS")])
8664 (define_expand "stack_protect_test"
8665 [(set (reg:CC CC_REGNUM)
8666 (compare (match_operand 0 "memory_operand" "")
8667 (match_operand 1 "memory_operand" "")))
8668 (match_operand 2 "" "")]
8672 #ifdef TARGET_THREAD_SSP_OFFSET
8674 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8675 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8678 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8680 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8682 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
8683 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
8684 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
8688 (define_insn "stack_protect_test<mode>"
8689 [(set (reg:CCZ CC_REGNUM)
8690 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8691 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8693 "clc\t%O0(%G0,%R0),%S1"
8694 [(set_attr "op_type" "SS")])
8696 ; This is used in s390_emit_prologue in order to prevent insns
8697 ; adjusting the stack pointer to be moved over insns writing stack
8698 ; slots using a copy of the stack pointer in a different register.
8699 (define_insn "stack_tie"
8700 [(set (match_operand:BLK 0 "memory_operand" "+m")
8701 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8704 [(set_attr "length" "0")])
8708 ; Data prefetch patterns
8711 (define_insn "prefetch"
8712 [(prefetch (match_operand 0 "address_operand" "UW,X")
8713 (match_operand:SI 1 "const_int_operand" "n,n")
8714 (match_operand:SI 2 "const_int_operand" "n,n"))]
8717 if (larl_operand (operands[0], Pmode))
8718 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8720 if (s390_mem_constraint ("W", operands[0])
8721 || s390_mem_constraint ("U", operands[0]))
8722 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8724 /* This point might be reached if op0 is a larl operand with an
8725 uneven addend. In this case we simply omit issuing a prefetch
8730 [(set_attr "type" "load,larl")
8731 (set_attr "op_type" "RXY,RIL")
8732 (set_attr "z10prop" "z10_super")])
8736 ; Byte swap instructions
8739 (define_insn "bswap<mode>2"
8740 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8741 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
8746 [(set_attr "type" "*,load")
8747 (set_attr "op_type" "RRE,RXY")
8748 (set_attr "z10prop" "z10_super")])