| blob | 64de3dc5337d8b4654d5055ad0436ef0d49b50e7 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 (UNSPEC_TOCREL 49)
103 (UNSPEC_MACHOPIC_OFFSET 50)
104 ])
106 ;;
107 ;; UNSPEC_VOLATILE usage
108 ;;
110 (define_constants
111 [(UNSPECV_BLOCK 0)
112 (UNSPECV_LL 1) ; load-locked
113 (UNSPECV_SC 2) ; store-conditional
114 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ])
116 \f
117 ;; Define an insn type attribute. This is used in function unit delay
118 ;; computations.
119 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
120 (const_string "integer"))
122 ;; Define floating point instruction sub-types for use with Xfpu.md
123 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
125 ;; Length (in bytes).
126 ; '(pc)' in the following doesn't include the instruction itself; it is
127 ; calculated as if the instruction had zero size.
128 (define_attr "length" ""
129 (if_then_else (eq_attr "type" "branch")
130 (if_then_else (and (ge (minus (match_dup 0) (pc))
131 (const_int -32768))
132 (lt (minus (match_dup 0) (pc))
133 (const_int 32764)))
134 (const_int 4)
135 (const_int 8))
136 (const_int 4)))
138 ;; Processor type -- this attribute must exactly match the processor_type
139 ;; enumeration in rs6000.h.
141 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell"
142 (const (symbol_ref "rs6000_cpu_attr")))
145 ;; If this instruction is microcoded on the CELL processor
146 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
147 (define_attr "cell_micro" "not,conditional,always"
148 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
149 (const_string "always")
150 (const_string "not")))
152 (automata_option "ndfa")
154 (include "rios1.md")
155 (include "rios2.md")
156 (include "rs64.md")
157 (include "mpc.md")
158 (include "40x.md")
159 (include "440.md")
160 (include "603.md")
161 (include "6xx.md")
162 (include "7xx.md")
163 (include "7450.md")
164 (include "8540.md")
165 (include "e300c2c3.md")
166 (include "e500mc.md")
167 (include "power4.md")
168 (include "power5.md")
169 (include "power6.md")
170 (include "cell.md")
171 (include "xfpu.md")
173 (include "predicates.md")
174 (include "constraints.md")
176 (include "darwin.md")
178 \f
179 ;; Mode iterators
181 ; This mode iterator allows :GPR to be used to indicate the allowable size
182 ; of whole values in GPRs.
183 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
185 ; Any supported integer mode.
186 (define_mode_iterator INT [QI HI SI DI TI])
188 ; Any supported integer mode that fits in one register.
189 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
191 ; extend modes for DImode
192 (define_mode_iterator QHSI [QI HI SI])
194 ; SImode or DImode, even if DImode doesn't fit in GPRs.
195 (define_mode_iterator SDI [SI DI])
197 ; The size of a pointer. Also, the size of the value that a record-condition
198 ; (one with a '.') will compare.
199 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
201 ; Any hardware-supported floating-point mode
202 (define_mode_iterator FP [
203 (SF "TARGET_HARD_FLOAT
204 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
205 (DF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
207 (TF "!TARGET_IEEEQUAD
208 && TARGET_HARD_FLOAT
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
210 && TARGET_LONG_DOUBLE_128")
211 (DD "TARGET_DFP")
212 (TD "TARGET_DFP")])
214 ; Various instructions that come in SI and DI forms.
215 ; A generic w/d attribute, for things like cmpw/cmpd.
216 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
218 ; DImode bits
219 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
221 ;; ISEL/ISEL64 target selection
222 (define_mode_attr sel [(SI "") (DI "64")])
224 ;; Suffix for reload patterns
225 (define_mode_attr ptrsize [(SI "32bit")
226 (DI "64bit")])
228 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
229 (DI "TARGET_64BIT")])
231 (define_mode_attr mptrsize [(SI "si")
232 (DI "di")])
234 \f
235 ;; Start with fixed-point load and store insns. Here we put only the more
236 ;; complex forms. Basic data transfer is done later.
238 (define_expand "zero_extend<mode>di2"
239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
240 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
241 "TARGET_POWERPC64"
242 "")
244 (define_insn "*zero_extend<mode>di2_internal1"
245 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
246 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
247 "TARGET_POWERPC64"
248 "@
249 l<wd>z%U1%X1 %0,%1
250 rldicl %0,%1,0,<dbits>"
251 [(set_attr "type" "load,*")])
253 (define_insn "*zero_extend<mode>di2_internal2"
254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
255 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
256 (const_int 0)))
257 (clobber (match_scratch:DI 2 "=r,r"))]
258 "TARGET_64BIT"
259 "@
260 rldicl. %2,%1,0,<dbits>
261 #"
262 [(set_attr "type" "compare")
263 (set_attr "length" "4,8")])
265 (define_split
266 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
268 (const_int 0)))
269 (clobber (match_scratch:DI 2 ""))]
270 "TARGET_POWERPC64 && reload_completed"
271 [(set (match_dup 2)
272 (zero_extend:DI (match_dup 1)))
273 (set (match_dup 0)
274 (compare:CC (match_dup 2)
275 (const_int 0)))]
276 "")
278 (define_insn "*zero_extend<mode>di2_internal3"
279 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
281 (const_int 0)))
282 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
283 (zero_extend:DI (match_dup 1)))]
284 "TARGET_64BIT"
285 "@
286 rldicl. %0,%1,0,<dbits>
287 #"
288 [(set_attr "type" "compare")
289 (set_attr "length" "4,8")])
291 (define_split
292 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
293 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
294 (const_int 0)))
295 (set (match_operand:DI 0 "gpc_reg_operand" "")
296 (zero_extend:DI (match_dup 1)))]
297 "TARGET_POWERPC64 && reload_completed"
298 [(set (match_dup 0)
299 (zero_extend:DI (match_dup 1)))
300 (set (match_dup 2)
301 (compare:CC (match_dup 0)
302 (const_int 0)))]
303 "")
305 (define_insn "extendqidi2"
306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
307 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
308 "TARGET_POWERPC64"
309 "extsb %0,%1"
310 [(set_attr "type" "exts")])
312 (define_insn ""
313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
314 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
315 (const_int 0)))
316 (clobber (match_scratch:DI 2 "=r,r"))]
317 "TARGET_64BIT"
318 "@
319 extsb. %2,%1
320 #"
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
324 (define_split
325 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
327 (const_int 0)))
328 (clobber (match_scratch:DI 2 ""))]
329 "TARGET_POWERPC64 && reload_completed"
330 [(set (match_dup 2)
331 (sign_extend:DI (match_dup 1)))
332 (set (match_dup 0)
333 (compare:CC (match_dup 2)
334 (const_int 0)))]
335 "")
337 (define_insn ""
338 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
340 (const_int 0)))
341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_64BIT"
344 "@
345 extsb. %0,%1
346 #"
347 [(set_attr "type" "compare")
348 (set_attr "length" "4,8")])
350 (define_split
351 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
352 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
353 (const_int 0)))
354 (set (match_operand:DI 0 "gpc_reg_operand" "")
355 (sign_extend:DI (match_dup 1)))]
356 "TARGET_POWERPC64 && reload_completed"
357 [(set (match_dup 0)
358 (sign_extend:DI (match_dup 1)))
359 (set (match_dup 2)
360 (compare:CC (match_dup 0)
361 (const_int 0)))]
362 "")
364 (define_expand "extendhidi2"
365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
366 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
367 "TARGET_POWERPC64"
368 "")
370 (define_insn ""
371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
372 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
373 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
374 "@
375 lha%U1%X1 %0,%1
376 extsh %0,%1"
377 [(set_attr "type" "load_ext,exts")])
379 (define_insn ""
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
381 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
382 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
383 "extsh %0,%1"
384 [(set_attr "type" "exts")])
386 (define_insn ""
387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
388 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
389 (const_int 0)))
390 (clobber (match_scratch:DI 2 "=r,r"))]
391 "TARGET_64BIT"
392 "@
393 extsh. %2,%1
394 #"
395 [(set_attr "type" "compare")
396 (set_attr "length" "4,8")])
398 (define_split
399 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
401 (const_int 0)))
402 (clobber (match_scratch:DI 2 ""))]
403 "TARGET_POWERPC64 && reload_completed"
404 [(set (match_dup 2)
405 (sign_extend:DI (match_dup 1)))
406 (set (match_dup 0)
407 (compare:CC (match_dup 2)
408 (const_int 0)))]
409 "")
411 (define_insn ""
412 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
413 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
414 (const_int 0)))
415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
416 (sign_extend:DI (match_dup 1)))]
417 "TARGET_64BIT"
418 "@
419 extsh. %0,%1
420 #"
421 [(set_attr "type" "compare")
422 (set_attr "length" "4,8")])
424 (define_split
425 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
426 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
427 (const_int 0)))
428 (set (match_operand:DI 0 "gpc_reg_operand" "")
429 (sign_extend:DI (match_dup 1)))]
430 "TARGET_POWERPC64 && reload_completed"
431 [(set (match_dup 0)
432 (sign_extend:DI (match_dup 1)))
433 (set (match_dup 2)
434 (compare:CC (match_dup 0)
435 (const_int 0)))]
436 "")
438 (define_expand "extendsidi2"
439 [(set (match_operand:DI 0 "gpc_reg_operand" "")
440 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
441 "TARGET_POWERPC64"
442 "")
444 (define_insn ""
445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
446 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
447 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
448 "@
449 lwa%U1%X1 %0,%1
450 extsw %0,%1"
451 [(set_attr "type" "load_ext,exts")])
453 (define_insn ""
454 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
455 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
456 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
457 "extsw %0,%1"
458 [(set_attr "type" "exts")])
460 (define_insn ""
461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
463 (const_int 0)))
464 (clobber (match_scratch:DI 2 "=r,r"))]
465 "TARGET_64BIT"
466 "@
467 extsw. %2,%1
468 #"
469 [(set_attr "type" "compare")
470 (set_attr "length" "4,8")])
472 (define_split
473 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
475 (const_int 0)))
476 (clobber (match_scratch:DI 2 ""))]
477 "TARGET_POWERPC64 && reload_completed"
478 [(set (match_dup 2)
479 (sign_extend:DI (match_dup 1)))
480 (set (match_dup 0)
481 (compare:CC (match_dup 2)
482 (const_int 0)))]
483 "")
485 (define_insn ""
486 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
488 (const_int 0)))
489 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
490 (sign_extend:DI (match_dup 1)))]
491 "TARGET_64BIT"
492 "@
493 extsw. %0,%1
494 #"
495 [(set_attr "type" "compare")
496 (set_attr "length" "4,8")])
498 (define_split
499 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
500 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
501 (const_int 0)))
502 (set (match_operand:DI 0 "gpc_reg_operand" "")
503 (sign_extend:DI (match_dup 1)))]
504 "TARGET_POWERPC64 && reload_completed"
505 [(set (match_dup 0)
506 (sign_extend:DI (match_dup 1)))
507 (set (match_dup 2)
508 (compare:CC (match_dup 0)
509 (const_int 0)))]
510 "")
512 (define_expand "zero_extendqisi2"
513 [(set (match_operand:SI 0 "gpc_reg_operand" "")
514 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
515 ""
516 "")
518 (define_insn ""
519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
520 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
521 ""
522 "@
523 lbz%U1%X1 %0,%1
524 {rlinm|rlwinm} %0,%1,0,0xff"
525 [(set_attr "type" "load,*")])
527 (define_insn ""
528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
530 (const_int 0)))
531 (clobber (match_scratch:SI 2 "=r,r"))]
532 ""
533 "@
534 {andil.|andi.} %2,%1,0xff
535 #"
536 [(set_attr "type" "fast_compare,compare")
537 (set_attr "length" "4,8")])
539 (define_split
540 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
542 (const_int 0)))
543 (clobber (match_scratch:SI 2 ""))]
544 "reload_completed"
545 [(set (match_dup 2)
546 (zero_extend:SI (match_dup 1)))
547 (set (match_dup 0)
548 (compare:CC (match_dup 2)
549 (const_int 0)))]
550 "")
552 (define_insn ""
553 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
555 (const_int 0)))
556 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
557 (zero_extend:SI (match_dup 1)))]
558 ""
559 "@
560 {andil.|andi.} %0,%1,0xff
561 #"
562 [(set_attr "type" "fast_compare,compare")
563 (set_attr "length" "4,8")])
565 (define_split
566 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
567 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
568 (const_int 0)))
569 (set (match_operand:SI 0 "gpc_reg_operand" "")
570 (zero_extend:SI (match_dup 1)))]
571 "reload_completed"
572 [(set (match_dup 0)
573 (zero_extend:SI (match_dup 1)))
574 (set (match_dup 2)
575 (compare:CC (match_dup 0)
576 (const_int 0)))]
577 "")
579 (define_expand "extendqisi2"
580 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
581 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
582 ""
583 "
584 {
585 if (TARGET_POWERPC)
586 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
587 else if (TARGET_POWER)
588 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
589 else
590 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
591 DONE;
592 }")
594 (define_insn "extendqisi2_ppc"
595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
596 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
597 "TARGET_POWERPC"
598 "extsb %0,%1"
599 [(set_attr "type" "exts")])
601 (define_insn ""
602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
603 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
604 (const_int 0)))
605 (clobber (match_scratch:SI 2 "=r,r"))]
606 "TARGET_POWERPC"
607 "@
608 extsb. %2,%1
609 #"
610 [(set_attr "type" "compare")
611 (set_attr "length" "4,8")])
613 (define_split
614 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
616 (const_int 0)))
617 (clobber (match_scratch:SI 2 ""))]
618 "TARGET_POWERPC && reload_completed"
619 [(set (match_dup 2)
620 (sign_extend:SI (match_dup 1)))
621 (set (match_dup 0)
622 (compare:CC (match_dup 2)
623 (const_int 0)))]
624 "")
626 (define_insn ""
627 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
629 (const_int 0)))
630 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC"
633 "@
634 extsb. %0,%1
635 #"
636 [(set_attr "type" "compare")
637 (set_attr "length" "4,8")])
639 (define_split
640 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
641 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
642 (const_int 0)))
643 (set (match_operand:SI 0 "gpc_reg_operand" "")
644 (sign_extend:SI (match_dup 1)))]
645 "TARGET_POWERPC && reload_completed"
646 [(set (match_dup 0)
647 (sign_extend:SI (match_dup 1)))
648 (set (match_dup 2)
649 (compare:CC (match_dup 0)
650 (const_int 0)))]
651 "")
653 (define_expand "extendqisi2_power"
654 [(parallel [(set (match_dup 2)
655 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
656 (const_int 24)))
657 (clobber (scratch:SI))])
658 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))
661 (clobber (scratch:SI))])]
662 "TARGET_POWER"
663 "
664 { operands[1] = gen_lowpart (SImode, operands[1]);
665 operands[2] = gen_reg_rtx (SImode); }")
667 (define_expand "extendqisi2_no_power"
668 [(set (match_dup 2)
669 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
670 (const_int 24)))
671 (set (match_operand:SI 0 "gpc_reg_operand" "")
672 (ashiftrt:SI (match_dup 2)
673 (const_int 24)))]
674 "! TARGET_POWER && ! TARGET_POWERPC"
675 "
676 { operands[1] = gen_lowpart (SImode, operands[1]);
677 operands[2] = gen_reg_rtx (SImode); }")
679 (define_expand "zero_extendqihi2"
680 [(set (match_operand:HI 0 "gpc_reg_operand" "")
681 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
682 ""
683 "")
685 (define_insn ""
686 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
687 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
688 ""
689 "@
690 lbz%U1%X1 %0,%1
691 {rlinm|rlwinm} %0,%1,0,0xff"
692 [(set_attr "type" "load,*")])
694 (define_insn ""
695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
696 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
697 (const_int 0)))
698 (clobber (match_scratch:HI 2 "=r,r"))]
699 ""
700 "@
701 {andil.|andi.} %2,%1,0xff
702 #"
703 [(set_attr "type" "fast_compare,compare")
704 (set_attr "length" "4,8")])
706 (define_split
707 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
709 (const_int 0)))
710 (clobber (match_scratch:HI 2 ""))]
711 "reload_completed"
712 [(set (match_dup 2)
713 (zero_extend:HI (match_dup 1)))
714 (set (match_dup 0)
715 (compare:CC (match_dup 2)
716 (const_int 0)))]
717 "")
719 (define_insn ""
720 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
724 (zero_extend:HI (match_dup 1)))]
725 ""
726 "@
727 {andil.|andi.} %0,%1,0xff
728 #"
729 [(set_attr "type" "fast_compare,compare")
730 (set_attr "length" "4,8")])
732 (define_split
733 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
734 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
735 (const_int 0)))
736 (set (match_operand:HI 0 "gpc_reg_operand" "")
737 (zero_extend:HI (match_dup 1)))]
738 "reload_completed"
739 [(set (match_dup 0)
740 (zero_extend:HI (match_dup 1)))
741 (set (match_dup 2)
742 (compare:CC (match_dup 0)
743 (const_int 0)))]
744 "")
746 (define_expand "extendqihi2"
747 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
748 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
749 ""
750 "
751 {
752 if (TARGET_POWERPC)
753 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
754 else if (TARGET_POWER)
755 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
756 else
757 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
758 DONE;
759 }")
761 (define_insn "extendqihi2_ppc"
762 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
763 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
764 "TARGET_POWERPC"
765 "extsb %0,%1"
766 [(set_attr "type" "exts")])
768 (define_insn ""
769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
771 (const_int 0)))
772 (clobber (match_scratch:HI 2 "=r,r"))]
773 "TARGET_POWERPC"
774 "@
775 extsb. %2,%1
776 #"
777 [(set_attr "type" "compare")
778 (set_attr "length" "4,8")])
780 (define_split
781 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
783 (const_int 0)))
784 (clobber (match_scratch:HI 2 ""))]
785 "TARGET_POWERPC && reload_completed"
786 [(set (match_dup 2)
787 (sign_extend:HI (match_dup 1)))
788 (set (match_dup 0)
789 (compare:CC (match_dup 2)
790 (const_int 0)))]
791 "")
793 (define_insn ""
794 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
796 (const_int 0)))
797 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
798 (sign_extend:HI (match_dup 1)))]
799 "TARGET_POWERPC"
800 "@
801 extsb. %0,%1
802 #"
803 [(set_attr "type" "compare")
804 (set_attr "length" "4,8")])
806 (define_split
807 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
808 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
809 (const_int 0)))
810 (set (match_operand:HI 0 "gpc_reg_operand" "")
811 (sign_extend:HI (match_dup 1)))]
812 "TARGET_POWERPC && reload_completed"
813 [(set (match_dup 0)
814 (sign_extend:HI (match_dup 1)))
815 (set (match_dup 2)
816 (compare:CC (match_dup 0)
817 (const_int 0)))]
818 "")
820 (define_expand "extendqihi2_power"
821 [(parallel [(set (match_dup 2)
822 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
823 (const_int 24)))
824 (clobber (scratch:SI))])
825 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
826 (ashiftrt:SI (match_dup 2)
827 (const_int 24)))
828 (clobber (scratch:SI))])]
829 "TARGET_POWER"
830 "
831 { operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
835 (define_expand "extendqihi2_no_power"
836 [(set (match_dup 2)
837 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
838 (const_int 24)))
839 (set (match_operand:HI 0 "gpc_reg_operand" "")
840 (ashiftrt:SI (match_dup 2)
841 (const_int 24)))]
842 "! TARGET_POWER && ! TARGET_POWERPC"
843 "
844 { operands[0] = gen_lowpart (SImode, operands[0]);
845 operands[1] = gen_lowpart (SImode, operands[1]);
846 operands[2] = gen_reg_rtx (SImode); }")
848 (define_expand "zero_extendhisi2"
849 [(set (match_operand:SI 0 "gpc_reg_operand" "")
850 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
851 ""
852 "")
854 (define_insn ""
855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
856 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
857 ""
858 "@
859 lhz%U1%X1 %0,%1
860 {rlinm|rlwinm} %0,%1,0,0xffff"
861 [(set_attr "type" "load,*")])
863 (define_insn ""
864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
866 (const_int 0)))
867 (clobber (match_scratch:SI 2 "=r,r"))]
868 ""
869 "@
870 {andil.|andi.} %2,%1,0xffff
871 #"
872 [(set_attr "type" "fast_compare,compare")
873 (set_attr "length" "4,8")])
875 (define_split
876 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
878 (const_int 0)))
879 (clobber (match_scratch:SI 2 ""))]
880 "reload_completed"
881 [(set (match_dup 2)
882 (zero_extend:SI (match_dup 1)))
883 (set (match_dup 0)
884 (compare:CC (match_dup 2)
885 (const_int 0)))]
886 "")
888 (define_insn ""
889 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
893 (zero_extend:SI (match_dup 1)))]
894 ""
895 "@
896 {andil.|andi.} %0,%1,0xffff
897 #"
898 [(set_attr "type" "fast_compare,compare")
899 (set_attr "length" "4,8")])
901 (define_split
902 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
903 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
904 (const_int 0)))
905 (set (match_operand:SI 0 "gpc_reg_operand" "")
906 (zero_extend:SI (match_dup 1)))]
907 "reload_completed"
908 [(set (match_dup 0)
909 (zero_extend:SI (match_dup 1)))
910 (set (match_dup 2)
911 (compare:CC (match_dup 0)
912 (const_int 0)))]
913 "")
915 (define_expand "extendhisi2"
916 [(set (match_operand:SI 0 "gpc_reg_operand" "")
917 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
918 ""
919 "")
921 (define_insn ""
922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
923 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
924 "rs6000_gen_cell_microcode"
925 "@
926 lha%U1%X1 %0,%1
927 {exts|extsh} %0,%1"
928 [(set_attr "type" "load_ext,exts")])
930 (define_insn ""
931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
932 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
933 "!rs6000_gen_cell_microcode"
934 "{exts|extsh} %0,%1"
935 [(set_attr "type" "exts")])
937 (define_insn ""
938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
939 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
940 (const_int 0)))
941 (clobber (match_scratch:SI 2 "=r,r"))]
942 ""
943 "@
944 {exts.|extsh.} %2,%1
945 #"
946 [(set_attr "type" "compare")
947 (set_attr "length" "4,8")])
949 (define_split
950 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
952 (const_int 0)))
953 (clobber (match_scratch:SI 2 ""))]
954 "reload_completed"
955 [(set (match_dup 2)
956 (sign_extend:SI (match_dup 1)))
957 (set (match_dup 0)
958 (compare:CC (match_dup 2)
959 (const_int 0)))]
960 "")
962 (define_insn ""
963 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
967 (sign_extend:SI (match_dup 1)))]
968 ""
969 "@
970 {exts.|extsh.} %0,%1
971 #"
972 [(set_attr "type" "compare")
973 (set_attr "length" "4,8")])
974 \f
975 ;; IBM 405, 440 and 464 half-word multiplication operations.
977 (define_insn "*macchwc"
978 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
979 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
980 (match_operand:SI 2 "gpc_reg_operand" "r")
981 (const_int 16))
982 (sign_extend:SI
983 (match_operand:HI 1 "gpc_reg_operand" "r")))
984 (match_operand:SI 4 "gpc_reg_operand" "0"))
985 (const_int 0)))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_dup 2)
989 (const_int 16))
990 (sign_extend:SI
991 (match_dup 1)))
992 (match_dup 4)))]
993 "TARGET_MULHW"
994 "macchw. %0, %1, %2"
995 [(set_attr "type" "imul3")])
997 (define_insn "*macchw"
998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
999 (plus:SI (mult:SI (ashiftrt:SI
1000 (match_operand:SI 2 "gpc_reg_operand" "r")
1001 (const_int 16))
1002 (sign_extend:SI
1003 (match_operand:HI 1 "gpc_reg_operand" "r")))
1004 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1005 "TARGET_MULHW"
1006 "macchw %0, %1, %2"
1007 [(set_attr "type" "imul3")])
1009 (define_insn "*macchwuc"
1010 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1011 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1012 (match_operand:SI 2 "gpc_reg_operand" "r")
1013 (const_int 16))
1014 (zero_extend:SI
1015 (match_operand:HI 1 "gpc_reg_operand" "r")))
1016 (match_operand:SI 4 "gpc_reg_operand" "0"))
1017 (const_int 0)))
1018 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1019 (plus:SI (mult:SI (lshiftrt:SI
1020 (match_dup 2)
1021 (const_int 16))
1022 (zero_extend:SI
1023 (match_dup 1)))
1024 (match_dup 4)))]
1025 "TARGET_MULHW"
1026 "macchwu. %0, %1, %2"
1027 [(set_attr "type" "imul3")])
1029 (define_insn "*macchwu"
1030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (lshiftrt:SI
1032 (match_operand:SI 2 "gpc_reg_operand" "r")
1033 (const_int 16))
1034 (zero_extend:SI
1035 (match_operand:HI 1 "gpc_reg_operand" "r")))
1036 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1037 "TARGET_MULHW"
1038 "macchwu %0, %1, %2"
1039 [(set_attr "type" "imul3")])
1041 (define_insn "*machhwc"
1042 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1043 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1044 (match_operand:SI 1 "gpc_reg_operand" "%r")
1045 (const_int 16))
1046 (ashiftrt:SI
1047 (match_operand:SI 2 "gpc_reg_operand" "r")
1048 (const_int 16)))
1049 (match_operand:SI 4 "gpc_reg_operand" "0"))
1050 (const_int 0)))
1051 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (ashiftrt:SI
1053 (match_dup 1)
1054 (const_int 16))
1055 (ashiftrt:SI
1056 (match_dup 2)
1057 (const_int 16)))
1058 (match_dup 4)))]
1059 "TARGET_MULHW"
1060 "machhw. %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1063 (define_insn "*machhw"
1064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1065 (plus:SI (mult:SI (ashiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1067 (const_int 16))
1068 (ashiftrt:SI
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1070 (const_int 16)))
1071 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1072 "TARGET_MULHW"
1073 "machhw %0, %1, %2"
1074 [(set_attr "type" "imul3")])
1076 (define_insn "*machhwuc"
1077 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1078 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1079 (match_operand:SI 1 "gpc_reg_operand" "%r")
1080 (const_int 16))
1081 (lshiftrt:SI
1082 (match_operand:SI 2 "gpc_reg_operand" "r")
1083 (const_int 16)))
1084 (match_operand:SI 4 "gpc_reg_operand" "0"))
1085 (const_int 0)))
1086 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1087 (plus:SI (mult:SI (lshiftrt:SI
1088 (match_dup 1)
1089 (const_int 16))
1090 (lshiftrt:SI
1091 (match_dup 2)
1092 (const_int 16)))
1093 (match_dup 4)))]
1094 "TARGET_MULHW"
1095 "machhwu. %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1098 (define_insn "*machhwu"
1099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1100 (plus:SI (mult:SI (lshiftrt:SI
1101 (match_operand:SI 1 "gpc_reg_operand" "%r")
1102 (const_int 16))
1103 (lshiftrt:SI
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1105 (const_int 16)))
1106 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1107 "TARGET_MULHW"
1108 "machhwu %0, %1, %2"
1109 [(set_attr "type" "imul3")])
1111 (define_insn "*maclhwc"
1112 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1113 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1114 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1115 (sign_extend:SI
1116 (match_operand:HI 2 "gpc_reg_operand" "r")))
1117 (match_operand:SI 4 "gpc_reg_operand" "0"))
1118 (const_int 0)))
1119 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1120 (plus:SI (mult:SI (sign_extend:SI
1121 (match_dup 1))
1122 (sign_extend:SI
1123 (match_dup 2)))
1124 (match_dup 4)))]
1125 "TARGET_MULHW"
1126 "maclhw. %0, %1, %2"
1127 [(set_attr "type" "imul3")])
1129 (define_insn "*maclhw"
1130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (plus:SI (mult:SI (sign_extend:SI
1132 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1133 (sign_extend:SI
1134 (match_operand:HI 2 "gpc_reg_operand" "r")))
1135 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1136 "TARGET_MULHW"
1137 "maclhw %0, %1, %2"
1138 [(set_attr "type" "imul3")])
1140 (define_insn "*maclhwuc"
1141 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1142 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1143 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1144 (zero_extend:SI
1145 (match_operand:HI 2 "gpc_reg_operand" "r")))
1146 (match_operand:SI 4 "gpc_reg_operand" "0"))
1147 (const_int 0)))
1148 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1149 (plus:SI (mult:SI (zero_extend:SI
1150 (match_dup 1))
1151 (zero_extend:SI
1152 (match_dup 2)))
1153 (match_dup 4)))]
1154 "TARGET_MULHW"
1155 "maclhwu. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1158 (define_insn "*maclhwu"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (plus:SI (mult:SI (zero_extend:SI
1161 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1162 (zero_extend:SI
1163 (match_operand:HI 2 "gpc_reg_operand" "r")))
1164 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1165 "TARGET_MULHW"
1166 "maclhwu %0, %1, %2"
1167 [(set_attr "type" "imul3")])
1169 (define_insn "*nmacchwc"
1170 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1171 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1172 (mult:SI (ashiftrt:SI
1173 (match_operand:SI 2 "gpc_reg_operand" "r")
1174 (const_int 16))
1175 (sign_extend:SI
1176 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1177 (const_int 0)))
1178 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1179 (minus:SI (match_dup 4)
1180 (mult:SI (ashiftrt:SI
1181 (match_dup 2)
1182 (const_int 16))
1183 (sign_extend:SI
1184 (match_dup 1)))))]
1185 "TARGET_MULHW"
1186 "nmacchw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1189 (define_insn "*nmacchw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (ashiftrt:SI
1193 (match_operand:SI 2 "gpc_reg_operand" "r")
1194 (const_int 16))
1195 (sign_extend:SI
1196 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1197 "TARGET_MULHW"
1198 "nmacchw %0, %1, %2"
1199 [(set_attr "type" "imul3")])
1201 (define_insn "*nmachhwc"
1202 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1203 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1204 (mult:SI (ashiftrt:SI
1205 (match_operand:SI 1 "gpc_reg_operand" "%r")
1206 (const_int 16))
1207 (ashiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1209 (const_int 16))))
1210 (const_int 0)))
1211 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (minus:SI (match_dup 4)
1213 (mult:SI (ashiftrt:SI
1214 (match_dup 1)
1215 (const_int 16))
1216 (ashiftrt:SI
1217 (match_dup 2)
1218 (const_int 16)))))]
1219 "TARGET_MULHW"
1220 "nmachhw. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*nmachhw"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1226 (mult:SI (ashiftrt:SI
1227 (match_operand:SI 1 "gpc_reg_operand" "%r")
1228 (const_int 16))
1229 (ashiftrt:SI
1230 (match_operand:SI 2 "gpc_reg_operand" "r")
1231 (const_int 16)))))]
1232 "TARGET_MULHW"
1233 "nmachhw %0, %1, %2"
1234 [(set_attr "type" "imul3")])
1236 (define_insn "*nmaclhwc"
1237 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1238 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1239 (mult:SI (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1241 (sign_extend:SI
1242 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1243 (const_int 0)))
1244 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1245 (minus:SI (match_dup 4)
1246 (mult:SI (sign_extend:SI
1247 (match_dup 1))
1248 (sign_extend:SI
1249 (match_dup 2)))))]
1250 "TARGET_MULHW"
1251 "nmaclhw. %0, %1, %2"
1252 [(set_attr "type" "imul3")])
1254 (define_insn "*nmaclhw"
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1257 (mult:SI (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1259 (sign_extend:SI
1260 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1261 "TARGET_MULHW"
1262 "nmaclhw %0, %1, %2"
1263 [(set_attr "type" "imul3")])
1265 (define_insn "*mulchwc"
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 (compare:CC (mult:SI (ashiftrt:SI
1268 (match_operand:SI 2 "gpc_reg_operand" "r")
1269 (const_int 16))
1270 (sign_extend:SI
1271 (match_operand:HI 1 "gpc_reg_operand" "r")))
1272 (const_int 0)))
1273 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1274 (mult:SI (ashiftrt:SI
1275 (match_dup 2)
1276 (const_int 16))
1277 (sign_extend:SI
1278 (match_dup 1))))]
1279 "TARGET_MULHW"
1280 "mulchw. %0, %1, %2"
1281 [(set_attr "type" "imul3")])
1283 (define_insn "*mulchw"
1284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1285 (mult:SI (ashiftrt:SI
1286 (match_operand:SI 2 "gpc_reg_operand" "r")
1287 (const_int 16))
1288 (sign_extend:SI
1289 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1290 "TARGET_MULHW"
1291 "mulchw %0, %1, %2"
1292 [(set_attr "type" "imul3")])
1294 (define_insn "*mulchwuc"
1295 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1296 (compare:CC (mult:SI (lshiftrt:SI
1297 (match_operand:SI 2 "gpc_reg_operand" "r")
1298 (const_int 16))
1299 (zero_extend:SI
1300 (match_operand:HI 1 "gpc_reg_operand" "r")))
1301 (const_int 0)))
1302 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1303 (mult:SI (lshiftrt:SI
1304 (match_dup 2)
1305 (const_int 16))
1306 (zero_extend:SI
1307 (match_dup 1))))]
1308 "TARGET_MULHW"
1309 "mulchwu. %0, %1, %2"
1310 [(set_attr "type" "imul3")])
1312 (define_insn "*mulchwu"
1313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1314 (mult:SI (lshiftrt:SI
1315 (match_operand:SI 2 "gpc_reg_operand" "r")
1316 (const_int 16))
1317 (zero_extend:SI
1318 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1319 "TARGET_MULHW"
1320 "mulchwu %0, %1, %2"
1321 [(set_attr "type" "imul3")])
1323 (define_insn "*mulhhwc"
1324 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1325 (compare:CC (mult:SI (ashiftrt:SI
1326 (match_operand:SI 1 "gpc_reg_operand" "%r")
1327 (const_int 16))
1328 (ashiftrt:SI
1329 (match_operand:SI 2 "gpc_reg_operand" "r")
1330 (const_int 16)))
1331 (const_int 0)))
1332 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1333 (mult:SI (ashiftrt:SI
1334 (match_dup 1)
1335 (const_int 16))
1336 (ashiftrt:SI
1337 (match_dup 2)
1338 (const_int 16))))]
1339 "TARGET_MULHW"
1340 "mulhhw. %0, %1, %2"
1341 [(set_attr "type" "imul3")])
1343 (define_insn "*mulhhw"
1344 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1345 (mult:SI (ashiftrt:SI
1346 (match_operand:SI 1 "gpc_reg_operand" "%r")
1347 (const_int 16))
1348 (ashiftrt:SI
1349 (match_operand:SI 2 "gpc_reg_operand" "r")
1350 (const_int 16))))]
1351 "TARGET_MULHW"
1352 "mulhhw %0, %1, %2"
1353 [(set_attr "type" "imul3")])
1355 (define_insn "*mulhhwuc"
1356 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1357 (compare:CC (mult:SI (lshiftrt:SI
1358 (match_operand:SI 1 "gpc_reg_operand" "%r")
1359 (const_int 16))
1360 (lshiftrt:SI
1361 (match_operand:SI 2 "gpc_reg_operand" "r")
1362 (const_int 16)))
1363 (const_int 0)))
1364 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (mult:SI (lshiftrt:SI
1366 (match_dup 1)
1367 (const_int 16))
1368 (lshiftrt:SI
1369 (match_dup 2)
1370 (const_int 16))))]
1371 "TARGET_MULHW"
1372 "mulhhwu. %0, %1, %2"
1373 [(set_attr "type" "imul3")])
1375 (define_insn "*mulhhwu"
1376 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1377 (mult:SI (lshiftrt:SI
1378 (match_operand:SI 1 "gpc_reg_operand" "%r")
1379 (const_int 16))
1380 (lshiftrt:SI
1381 (match_operand:SI 2 "gpc_reg_operand" "r")
1382 (const_int 16))))]
1383 "TARGET_MULHW"
1384 "mulhhwu %0, %1, %2"
1385 [(set_attr "type" "imul3")])
1387 (define_insn "*mullhwc"
1388 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1389 (compare:CC (mult:SI (sign_extend:SI
1390 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1391 (sign_extend:SI
1392 (match_operand:HI 2 "gpc_reg_operand" "r")))
1393 (const_int 0)))
1394 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1395 (mult:SI (sign_extend:SI
1396 (match_dup 1))
1397 (sign_extend:SI
1398 (match_dup 2))))]
1399 "TARGET_MULHW"
1400 "mullhw. %0, %1, %2"
1401 [(set_attr "type" "imul3")])
1403 (define_insn "*mullhw"
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (mult:SI (sign_extend:SI
1406 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1407 (sign_extend:SI
1408 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1409 "TARGET_MULHW"
1410 "mullhw %0, %1, %2"
1411 [(set_attr "type" "imul3")])
1413 (define_insn "*mullhwuc"
1414 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1415 (compare:CC (mult:SI (zero_extend:SI
1416 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1417 (zero_extend:SI
1418 (match_operand:HI 2 "gpc_reg_operand" "r")))
1419 (const_int 0)))
1420 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1421 (mult:SI (zero_extend:SI
1422 (match_dup 1))
1423 (zero_extend:SI
1424 (match_dup 2))))]
1425 "TARGET_MULHW"
1426 "mullhwu. %0, %1, %2"
1427 [(set_attr "type" "imul3")])
1429 (define_insn "*mullhwu"
1430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1431 (mult:SI (zero_extend:SI
1432 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1433 (zero_extend:SI
1434 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1435 "TARGET_MULHW"
1436 "mullhwu %0, %1, %2"
1437 [(set_attr "type" "imul3")])
1438 \f
1439 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1440 (define_insn "dlmzb"
1441 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1442 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1443 (match_operand:SI 2 "gpc_reg_operand" "r")]
1444 UNSPEC_DLMZB_CR))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1446 (unspec:SI [(match_dup 1)
1447 (match_dup 2)]
1448 UNSPEC_DLMZB))]
1449 "TARGET_DLMZB"
1450 "dlmzb. %0, %1, %2")
1452 (define_expand "strlensi"
1453 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1454 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1455 (match_operand:QI 2 "const_int_operand" "")
1456 (match_operand 3 "const_int_operand" "")]
1457 UNSPEC_DLMZB_STRLEN))
1458 (clobber (match_scratch:CC 4 "=x"))]
1459 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1460 {
1461 rtx result = operands[0];
1462 rtx src = operands[1];
1463 rtx search_char = operands[2];
1464 rtx align = operands[3];
1465 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1466 rtx loop_label, end_label, mem, cr0, cond;
1467 if (search_char != const0_rtx
1468 || GET_CODE (align) != CONST_INT
1469 || INTVAL (align) < 8)
1470 FAIL;
1471 word1 = gen_reg_rtx (SImode);
1472 word2 = gen_reg_rtx (SImode);
1473 scratch_dlmzb = gen_reg_rtx (SImode);
1474 scratch_string = gen_reg_rtx (Pmode);
1475 loop_label = gen_label_rtx ();
1476 end_label = gen_label_rtx ();
1477 addr = force_reg (Pmode, XEXP (src, 0));
1478 emit_move_insn (scratch_string, addr);
1479 emit_label (loop_label);
1480 mem = change_address (src, SImode, scratch_string);
1481 emit_move_insn (word1, mem);
1482 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1483 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1484 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1485 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1486 emit_jump_insn (gen_rtx_SET (VOIDmode,
1487 pc_rtx,
1488 gen_rtx_IF_THEN_ELSE (VOIDmode,
1489 cond,
1490 gen_rtx_LABEL_REF
1491 (VOIDmode,
1492 end_label),
1493 pc_rtx)));
1494 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1495 emit_jump_insn (gen_rtx_SET (VOIDmode,
1496 pc_rtx,
1497 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1498 emit_barrier ();
1499 emit_label (end_label);
1500 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1501 emit_insn (gen_subsi3 (result, scratch_string, addr));
1502 emit_insn (gen_subsi3 (result, result, const1_rtx));
1503 DONE;
1504 })
1505 \f
1506 (define_split
1507 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1508 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1509 (const_int 0)))
1510 (set (match_operand:SI 0 "gpc_reg_operand" "")
1511 (sign_extend:SI (match_dup 1)))]
1512 "reload_completed"
1513 [(set (match_dup 0)
1514 (sign_extend:SI (match_dup 1)))
1515 (set (match_dup 2)
1516 (compare:CC (match_dup 0)
1517 (const_int 0)))]
1518 "")
1520 ;; Fixed-point arithmetic insns.
1522 (define_expand "add<mode>3"
1523 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1524 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1525 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1526 ""
1527 {
1528 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1529 {
1530 if (non_short_cint_operand (operands[2], DImode))
1531 FAIL;
1532 }
1533 else if (GET_CODE (operands[2]) == CONST_INT
1534 && ! add_operand (operands[2], <MODE>mode))
1535 {
1536 rtx tmp = ((!can_create_pseudo_p ()
1537 || rtx_equal_p (operands[0], operands[1]))
1538 ? operands[0] : gen_reg_rtx (<MODE>mode));
1540 HOST_WIDE_INT val = INTVAL (operands[2]);
1541 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1542 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1544 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1545 FAIL;
1547 /* The ordering here is important for the prolog expander.
1548 When space is allocated from the stack, adding 'low' first may
1549 produce a temporary deallocation (which would be bad). */
1550 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1551 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1552 DONE;
1553 }
1554 })
1556 ;; Discourage ai/addic because of carry but provide it in an alternative
1557 ;; allowing register zero as source.
1558 (define_insn "*add<mode>3_internal1"
1559 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1560 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1561 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1562 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1563 "@
1564 {cax|add} %0,%1,%2
1565 {cal %0,%2(%1)|addi %0,%1,%2}
1566 {ai|addic} %0,%1,%2
1567 {cau|addis} %0,%1,%v2"
1568 [(set_attr "length" "4,4,4,4")])
1570 (define_insn "addsi3_high"
1571 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1572 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1573 (high:SI (match_operand 2 "" ""))))]
1574 "TARGET_MACHO && !TARGET_64BIT"
1575 "{cau|addis} %0,%1,ha16(%2)"
1576 [(set_attr "length" "4")])
1578 (define_insn "*add<mode>3_internal2"
1579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1580 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1581 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1582 (const_int 0)))
1583 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1584 ""
1585 "@
1586 {cax.|add.} %3,%1,%2
1587 {ai.|addic.} %3,%1,%2
1588 #
1589 #"
1590 [(set_attr "type" "fast_compare,compare,compare,compare")
1591 (set_attr "length" "4,4,8,8")])
1593 (define_split
1594 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1595 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1596 (match_operand:GPR 2 "reg_or_short_operand" ""))
1597 (const_int 0)))
1598 (clobber (match_scratch:GPR 3 ""))]
1599 "reload_completed"
1600 [(set (match_dup 3)
1601 (plus:GPR (match_dup 1)
1602 (match_dup 2)))
1603 (set (match_dup 0)
1604 (compare:CC (match_dup 3)
1605 (const_int 0)))]
1606 "")
1608 (define_insn "*add<mode>3_internal3"
1609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1610 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1611 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1612 (const_int 0)))
1613 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1614 (plus:P (match_dup 1)
1615 (match_dup 2)))]
1616 ""
1617 "@
1618 {cax.|add.} %0,%1,%2
1619 {ai.|addic.} %0,%1,%2
1620 #
1621 #"
1622 [(set_attr "type" "fast_compare,compare,compare,compare")
1623 (set_attr "length" "4,4,8,8")])
1625 (define_split
1626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1627 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1628 (match_operand:P 2 "reg_or_short_operand" ""))
1629 (const_int 0)))
1630 (set (match_operand:P 0 "gpc_reg_operand" "")
1631 (plus:P (match_dup 1) (match_dup 2)))]
1632 "reload_completed"
1633 [(set (match_dup 0)
1634 (plus:P (match_dup 1)
1635 (match_dup 2)))
1636 (set (match_dup 3)
1637 (compare:CC (match_dup 0)
1638 (const_int 0)))]
1639 "")
1641 ;; Split an add that we can't do in one insn into two insns, each of which
1642 ;; does one 16-bit part. This is used by combine. Note that the low-order
1643 ;; add should be last in case the result gets used in an address.
1645 (define_split
1646 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1647 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1648 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1649 ""
1650 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1651 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1652 {
1653 HOST_WIDE_INT val = INTVAL (operands[2]);
1654 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1655 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1657 operands[4] = GEN_INT (low);
1658 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1659 operands[3] = GEN_INT (rest);
1660 else if (can_create_pseudo_p ())
1661 {
1662 operands[3] = gen_reg_rtx (DImode);
1663 emit_move_insn (operands[3], operands[2]);
1664 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1665 DONE;
1666 }
1667 else
1668 FAIL;
1669 })
1671 (define_insn "one_cmpl<mode>2"
1672 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1673 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1674 ""
1675 "nor %0,%1,%1")
1677 (define_insn ""
1678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1679 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1680 (const_int 0)))
1681 (clobber (match_scratch:P 2 "=r,r"))]
1682 ""
1683 "@
1684 nor. %2,%1,%1
1685 #"
1686 [(set_attr "type" "fast_compare,compare")
1687 (set_attr "length" "4,8")])
1689 (define_split
1690 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1692 (const_int 0)))
1693 (clobber (match_scratch:P 2 ""))]
1694 "reload_completed"
1695 [(set (match_dup 2)
1696 (not:P (match_dup 1)))
1697 (set (match_dup 0)
1698 (compare:CC (match_dup 2)
1699 (const_int 0)))]
1700 "")
1702 (define_insn ""
1703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1705 (const_int 0)))
1706 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1707 (not:P (match_dup 1)))]
1708 ""
1709 "@
1710 nor. %0,%1,%1
1711 #"
1712 [(set_attr "type" "fast_compare,compare")
1713 (set_attr "length" "4,8")])
1715 (define_split
1716 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1717 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1718 (const_int 0)))
1719 (set (match_operand:P 0 "gpc_reg_operand" "")
1720 (not:P (match_dup 1)))]
1721 "reload_completed"
1722 [(set (match_dup 0)
1723 (not:P (match_dup 1)))
1724 (set (match_dup 2)
1725 (compare:CC (match_dup 0)
1726 (const_int 0)))]
1727 "")
1729 (define_insn ""
1730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1731 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1732 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1733 "! TARGET_POWERPC"
1734 "{sf%I1|subf%I1c} %0,%2,%1")
1736 (define_insn ""
1737 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1738 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1739 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1740 "TARGET_POWERPC"
1741 "@
1742 subf %0,%2,%1
1743 subfic %0,%2,%1")
1745 (define_insn ""
1746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1747 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1748 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1749 (const_int 0)))
1750 (clobber (match_scratch:SI 3 "=r,r"))]
1751 "! TARGET_POWERPC"
1752 "@
1753 {sf.|subfc.} %3,%2,%1
1754 #"
1755 [(set_attr "type" "compare")
1756 (set_attr "length" "4,8")])
1758 (define_insn ""
1759 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1760 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1761 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1762 (const_int 0)))
1763 (clobber (match_scratch:P 3 "=r,r"))]
1764 "TARGET_POWERPC"
1765 "@
1766 subf. %3,%2,%1
1767 #"
1768 [(set_attr "type" "fast_compare")
1769 (set_attr "length" "4,8")])
1771 (define_split
1772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1773 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1774 (match_operand:P 2 "gpc_reg_operand" ""))
1775 (const_int 0)))
1776 (clobber (match_scratch:P 3 ""))]
1777 "reload_completed"
1778 [(set (match_dup 3)
1779 (minus:P (match_dup 1)
1780 (match_dup 2)))
1781 (set (match_dup 0)
1782 (compare:CC (match_dup 3)
1783 (const_int 0)))]
1784 "")
1786 (define_insn ""
1787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1788 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1790 (const_int 0)))
1791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1792 (minus:SI (match_dup 1) (match_dup 2)))]
1793 "! TARGET_POWERPC"
1794 "@
1795 {sf.|subfc.} %0,%2,%1
1796 #"
1797 [(set_attr "type" "compare")
1798 (set_attr "length" "4,8")])
1800 (define_insn ""
1801 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1802 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1803 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1804 (const_int 0)))
1805 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1806 (minus:P (match_dup 1)
1807 (match_dup 2)))]
1808 "TARGET_POWERPC"
1809 "@
1810 subf. %0,%2,%1
1811 #"
1812 [(set_attr "type" "fast_compare")
1813 (set_attr "length" "4,8")])
1815 (define_split
1816 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1817 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1818 (match_operand:P 2 "gpc_reg_operand" ""))
1819 (const_int 0)))
1820 (set (match_operand:P 0 "gpc_reg_operand" "")
1821 (minus:P (match_dup 1)
1822 (match_dup 2)))]
1823 "reload_completed"
1824 [(set (match_dup 0)
1825 (minus:P (match_dup 1)
1826 (match_dup 2)))
1827 (set (match_dup 3)
1828 (compare:CC (match_dup 0)
1829 (const_int 0)))]
1830 "")
1832 (define_expand "sub<mode>3"
1833 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1834 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1835 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1836 ""
1837 "
1838 {
1839 if (GET_CODE (operands[2]) == CONST_INT)
1840 {
1841 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1842 negate_rtx (<MODE>mode, operands[2])));
1843 DONE;
1844 }
1845 }")
1847 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1848 ;; instruction and some auxiliary computations. Then we just have a single
1849 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1850 ;; combine.
1852 (define_expand "sminsi3"
1853 [(set (match_dup 3)
1854 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (match_operand:SI 2 "reg_or_short_operand" ""))
1856 (const_int 0)
1857 (minus:SI (match_dup 2) (match_dup 1))))
1858 (set (match_operand:SI 0 "gpc_reg_operand" "")
1859 (minus:SI (match_dup 2) (match_dup 3)))]
1860 "TARGET_POWER || TARGET_ISEL"
1861 "
1862 {
1863 if (TARGET_ISEL)
1864 {
1865 operands[2] = force_reg (SImode, operands[2]);
1866 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1867 DONE;
1868 }
1870 operands[3] = gen_reg_rtx (SImode);
1871 }")
1873 (define_split
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1875 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "reg_or_short_operand" "")))
1877 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1878 "TARGET_POWER"
1879 [(set (match_dup 3)
1880 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1881 (const_int 0)
1882 (minus:SI (match_dup 2) (match_dup 1))))
1883 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1884 "")
1886 (define_expand "smaxsi3"
1887 [(set (match_dup 3)
1888 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1889 (match_operand:SI 2 "reg_or_short_operand" ""))
1890 (const_int 0)
1891 (minus:SI (match_dup 2) (match_dup 1))))
1892 (set (match_operand:SI 0 "gpc_reg_operand" "")
1893 (plus:SI (match_dup 3) (match_dup 1)))]
1894 "TARGET_POWER || TARGET_ISEL"
1895 "
1896 {
1897 if (TARGET_ISEL)
1898 {
1899 operands[2] = force_reg (SImode, operands[2]);
1900 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1901 DONE;
1902 }
1903 operands[3] = gen_reg_rtx (SImode);
1904 }")
1906 (define_split
1907 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1908 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1909 (match_operand:SI 2 "reg_or_short_operand" "")))
1910 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1911 "TARGET_POWER"
1912 [(set (match_dup 3)
1913 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1914 (const_int 0)
1915 (minus:SI (match_dup 2) (match_dup 1))))
1916 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1917 "")
1919 (define_expand "uminsi3"
1920 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1921 (match_dup 5)))
1922 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1923 (match_dup 5)))
1924 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1925 (const_int 0)
1926 (minus:SI (match_dup 4) (match_dup 3))))
1927 (set (match_operand:SI 0 "gpc_reg_operand" "")
1928 (minus:SI (match_dup 2) (match_dup 3)))]
1929 "TARGET_POWER || TARGET_ISEL"
1930 "
1931 {
1932 if (TARGET_ISEL)
1933 {
1934 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1935 DONE;
1936 }
1937 operands[3] = gen_reg_rtx (SImode);
1938 operands[4] = gen_reg_rtx (SImode);
1939 operands[5] = GEN_INT (-2147483647 - 1);
1940 }")
1942 (define_expand "umaxsi3"
1943 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1944 (match_dup 5)))
1945 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1946 (match_dup 5)))
1947 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1948 (const_int 0)
1949 (minus:SI (match_dup 4) (match_dup 3))))
1950 (set (match_operand:SI 0 "gpc_reg_operand" "")
1951 (plus:SI (match_dup 3) (match_dup 1)))]
1952 "TARGET_POWER || TARGET_ISEL"
1953 "
1954 {
1955 if (TARGET_ISEL)
1956 {
1957 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1958 DONE;
1959 }
1960 operands[3] = gen_reg_rtx (SImode);
1961 operands[4] = gen_reg_rtx (SImode);
1962 operands[5] = GEN_INT (-2147483647 - 1);
1963 }")
1965 (define_insn ""
1966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1967 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1968 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1969 (const_int 0)
1970 (minus:SI (match_dup 2) (match_dup 1))))]
1971 "TARGET_POWER"
1972 "doz%I2 %0,%1,%2")
1974 (define_insn ""
1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1976 (compare:CC
1977 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1979 (const_int 0)
1980 (minus:SI (match_dup 2) (match_dup 1)))
1981 (const_int 0)))
1982 (clobber (match_scratch:SI 3 "=r,r"))]
1983 "TARGET_POWER"
1984 "@
1985 doz%I2. %3,%1,%2
1986 #"
1987 [(set_attr "type" "delayed_compare")
1988 (set_attr "length" "4,8")])
1990 (define_split
1991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1992 (compare:CC
1993 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1994 (match_operand:SI 2 "reg_or_short_operand" ""))
1995 (const_int 0)
1996 (minus:SI (match_dup 2) (match_dup 1)))
1997 (const_int 0)))
1998 (clobber (match_scratch:SI 3 ""))]
1999 "TARGET_POWER && reload_completed"
2000 [(set (match_dup 3)
2001 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2002 (const_int 0)
2003 (minus:SI (match_dup 2) (match_dup 1))))
2004 (set (match_dup 0)
2005 (compare:CC (match_dup 3)
2006 (const_int 0)))]
2007 "")
2009 (define_insn ""
2010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2011 (compare:CC
2012 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2013 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2014 (const_int 0)
2015 (minus:SI (match_dup 2) (match_dup 1)))
2016 (const_int 0)))
2017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2018 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2019 (const_int 0)
2020 (minus:SI (match_dup 2) (match_dup 1))))]
2021 "TARGET_POWER"
2022 "@
2023 doz%I2. %0,%1,%2
2024 #"
2025 [(set_attr "type" "delayed_compare")
2026 (set_attr "length" "4,8")])
2028 (define_split
2029 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2030 (compare:CC
2031 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2032 (match_operand:SI 2 "reg_or_short_operand" ""))
2033 (const_int 0)
2034 (minus:SI (match_dup 2) (match_dup 1)))
2035 (const_int 0)))
2036 (set (match_operand:SI 0 "gpc_reg_operand" "")
2037 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2038 (const_int 0)
2039 (minus:SI (match_dup 2) (match_dup 1))))]
2040 "TARGET_POWER && reload_completed"
2041 [(set (match_dup 0)
2042 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2043 (const_int 0)
2044 (minus:SI (match_dup 2) (match_dup 1))))
2045 (set (match_dup 3)
2046 (compare:CC (match_dup 0)
2047 (const_int 0)))]
2048 "")
2050 ;; We don't need abs with condition code because such comparisons should
2051 ;; never be done.
2052 (define_expand "abssi2"
2053 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2054 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2055 ""
2056 "
2057 {
2058 if (TARGET_ISEL)
2059 {
2060 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2061 DONE;
2062 }
2063 else if (! TARGET_POWER)
2064 {
2065 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2066 DONE;
2067 }
2068 }")
2070 (define_insn "*abssi2_power"
2071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2072 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2073 "TARGET_POWER"
2074 "abs %0,%1")
2076 (define_insn_and_split "abssi2_isel"
2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2078 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2079 (clobber (match_scratch:SI 2 "=&b"))
2080 (clobber (match_scratch:CC 3 "=y"))]
2081 "TARGET_ISEL"
2082 "#"
2083 "&& reload_completed"
2084 [(set (match_dup 2) (neg:SI (match_dup 1)))
2085 (set (match_dup 3)
2086 (compare:CC (match_dup 1)
2087 (const_int 0)))
2088 (set (match_dup 0)
2089 (if_then_else:SI (ge (match_dup 3)
2090 (const_int 0))
2091 (match_dup 1)
2092 (match_dup 2)))]
2093 "")
2095 (define_insn_and_split "abssi2_nopower"
2096 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2097 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2098 (clobber (match_scratch:SI 2 "=&r,&r"))]
2099 "! TARGET_POWER && ! TARGET_ISEL"
2100 "#"
2101 "&& reload_completed"
2102 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2103 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2104 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2105 "")
2107 (define_insn "*nabs_power"
2108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2109 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2110 "TARGET_POWER"
2111 "nabs %0,%1")
2113 (define_insn_and_split "*nabs_nopower"
2114 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2115 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2116 (clobber (match_scratch:SI 2 "=&r,&r"))]
2117 "! TARGET_POWER"
2118 "#"
2119 "&& reload_completed"
2120 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2121 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2122 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2123 "")
2125 (define_expand "neg<mode>2"
2126 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2127 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2128 ""
2129 "")
2131 (define_insn "*neg<mode>2_internal"
2132 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2133 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2134 ""
2135 "neg %0,%1")
2137 (define_insn ""
2138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2139 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2140 (const_int 0)))
2141 (clobber (match_scratch:P 2 "=r,r"))]
2142 ""
2143 "@
2144 neg. %2,%1
2145 #"
2146 [(set_attr "type" "fast_compare")
2147 (set_attr "length" "4,8")])
2149 (define_split
2150 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2151 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2152 (const_int 0)))
2153 (clobber (match_scratch:P 2 ""))]
2154 "reload_completed"
2155 [(set (match_dup 2)
2156 (neg:P (match_dup 1)))
2157 (set (match_dup 0)
2158 (compare:CC (match_dup 2)
2159 (const_int 0)))]
2160 "")
2162 (define_insn ""
2163 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2165 (const_int 0)))
2166 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2167 (neg:P (match_dup 1)))]
2168 ""
2169 "@
2170 neg. %0,%1
2171 #"
2172 [(set_attr "type" "fast_compare")
2173 (set_attr "length" "4,8")])
2175 (define_split
2176 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2177 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2178 (const_int 0)))
2179 (set (match_operand:P 0 "gpc_reg_operand" "")
2180 (neg:P (match_dup 1)))]
2181 "reload_completed"
2182 [(set (match_dup 0)
2183 (neg:P (match_dup 1)))
2184 (set (match_dup 2)
2185 (compare:CC (match_dup 0)
2186 (const_int 0)))]
2187 "")
2189 (define_insn "clz<mode>2"
2190 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2191 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2192 ""
2193 "{cntlz|cntlz<wd>} %0,%1"
2194 [(set_attr "type" "cntlz")])
2196 (define_expand "ctz<mode>2"
2197 [(set (match_dup 2)
2198 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2199 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2200 (match_dup 2)))
2201 (clobber (scratch:CC))])
2202 (set (match_dup 4) (clz:GPR (match_dup 3)))
2203 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2204 (minus:GPR (match_dup 5) (match_dup 4)))]
2205 ""
2206 {
2207 operands[2] = gen_reg_rtx (<MODE>mode);
2208 operands[3] = gen_reg_rtx (<MODE>mode);
2209 operands[4] = gen_reg_rtx (<MODE>mode);
2210 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2211 })
2213 (define_expand "ffs<mode>2"
2214 [(set (match_dup 2)
2215 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2216 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2217 (match_dup 2)))
2218 (clobber (scratch:CC))])
2219 (set (match_dup 4) (clz:GPR (match_dup 3)))
2220 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2221 (minus:GPR (match_dup 5) (match_dup 4)))]
2222 ""
2223 {
2224 operands[2] = gen_reg_rtx (<MODE>mode);
2225 operands[3] = gen_reg_rtx (<MODE>mode);
2226 operands[4] = gen_reg_rtx (<MODE>mode);
2227 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2228 })
2230 (define_insn "popcntb<mode>2"
2231 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2232 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2233 UNSPEC_POPCNTB))]
2234 "TARGET_POPCNTB"
2235 "popcntb %0,%1")
2237 (define_insn "popcntwsi2"
2238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2239 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2240 "TARGET_POPCNTD"
2241 "popcntw %0,%1")
2243 (define_insn "popcntddi2"
2244 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2245 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2246 "TARGET_POPCNTD && TARGET_POWERPC64"
2247 "popcntd %0,%1")
2249 (define_expand "popcount<mode>2"
2250 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2251 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2252 "TARGET_POPCNTB || TARGET_POPCNTD"
2253 {
2254 rs6000_emit_popcount (operands[0], operands[1]);
2255 DONE;
2256 })
2258 (define_expand "parity<mode>2"
2259 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2260 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2261 "TARGET_POPCNTB"
2262 {
2263 rs6000_emit_parity (operands[0], operands[1]);
2264 DONE;
2265 })
2267 ;; Since the hardware zeros the upper part of the register, save generating the
2268 ;; AND immediate if we are converting to unsigned
2269 (define_insn "*bswaphi2_extenddi"
2270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2271 (zero_extend:DI
2272 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2273 "TARGET_POWERPC64"
2274 "lhbrx %0,%y1"
2275 [(set_attr "length" "4")
2276 (set_attr "type" "load")])
2278 (define_insn "*bswaphi2_extendsi"
2279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2280 (zero_extend:SI
2281 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2282 "TARGET_POWERPC"
2283 "lhbrx %0,%y1"
2284 [(set_attr "length" "4")
2285 (set_attr "type" "load")])
2287 (define_expand "bswaphi2"
2288 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2289 (bswap:HI
2290 (match_operand:HI 1 "reg_or_mem_operand" "")))
2291 (clobber (match_scratch:SI 2 ""))])]
2292 ""
2293 {
2294 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2295 operands[1] = force_reg (HImode, operands[1]);
2296 })
2298 (define_insn "bswaphi2_internal"
2299 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2300 (bswap:HI
2301 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2302 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2303 "TARGET_POWERPC"
2304 "@
2305 lhbrx %0,%y1
2306 sthbrx %1,%y0
2307 #"
2308 [(set_attr "length" "4,4,12")
2309 (set_attr "type" "load,store,*")])
2311 (define_split
2312 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2313 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2314 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2315 "TARGET_POWERPC && reload_completed"
2316 [(set (match_dup 3)
2317 (zero_extract:SI (match_dup 4)
2318 (const_int 8)
2319 (const_int 16)))
2320 (set (match_dup 2)
2321 (and:SI (ashift:SI (match_dup 4)
2322 (const_int 8))
2323 (const_int 65280))) ;; 0xff00
2324 (set (match_dup 3)
2325 (ior:SI (match_dup 3)
2326 (match_dup 2)))]
2327 "
2328 {
2329 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2330 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2331 }")
2333 (define_insn "*bswapsi2_extenddi"
2334 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2335 (zero_extend:DI
2336 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2337 "TARGET_POWERPC64"
2338 "lwbrx %0,%y1"
2339 [(set_attr "length" "4")
2340 (set_attr "type" "load")])
2342 (define_expand "bswapsi2"
2343 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2344 (bswap:SI
2345 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2346 ""
2347 {
2348 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2349 operands[1] = force_reg (SImode, operands[1]);
2350 })
2352 (define_insn "*bswapsi2_internal"
2353 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2354 (bswap:SI
2355 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2356 ""
2357 "@
2358 {lbrx|lwbrx} %0,%y1
2359 {stbrx|stwbrx} %1,%y0
2360 #"
2361 [(set_attr "length" "4,4,12")
2362 (set_attr "type" "load,store,*")])
2364 (define_split
2365 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2366 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2367 "reload_completed"
2368 [(set (match_dup 0)
2369 (rotate:SI (match_dup 1) (const_int 8)))
2370 (set (zero_extract:SI (match_dup 0)
2371 (const_int 8)
2372 (const_int 0))
2373 (match_dup 1))
2374 (set (zero_extract:SI (match_dup 0)
2375 (const_int 8)
2376 (const_int 16))
2377 (rotate:SI (match_dup 1)
2378 (const_int 16)))]
2379 "")
2381 (define_expand "bswapdi2"
2382 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2383 (bswap:DI
2384 (match_operand:DI 1 "reg_or_mem_operand" "")))
2385 (clobber (match_scratch:DI 2 ""))
2386 (clobber (match_scratch:DI 3 ""))
2387 (clobber (match_scratch:DI 4 ""))])]
2388 ""
2389 {
2390 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2391 operands[1] = force_reg (DImode, operands[1]);
2393 if (TARGET_32BIT)
2394 {
2395 /* 32-bit needs fewer scratch registers. */
2396 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2397 DONE;
2398 }
2399 })
2401 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2402 (define_insn "*bswapdi2_ldbrx"
2403 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2404 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2405 (clobber (match_scratch:DI 2 "=X,X,&r"))
2406 (clobber (match_scratch:DI 3 "=X,X,&r"))
2407 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2408 "TARGET_POWERPC64 && TARGET_LDBRX
2409 && (REG_P (operands[0]) || REG_P (operands[1]))"
2410 "@
2411 ldbrx %0,%y1
2412 stdbrx %1,%y0
2413 #"
2414 [(set_attr "length" "4,4,36")
2415 (set_attr "type" "load,store,*")])
2417 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2418 (define_insn "*bswapdi2_64bit"
2419 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2420 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2421 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2422 (clobber (match_scratch:DI 3 "=&b,&r,&r"))
2423 (clobber (match_scratch:DI 4 "=&b,X,&r"))]
2424 "TARGET_POWERPC64 && !TARGET_LDBRX
2425 && (REG_P (operands[0]) || REG_P (operands[1]))"
2426 "#"
2427 [(set_attr "length" "16,12,36")])
2429 (define_split
2430 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2431 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2432 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2433 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2434 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2435 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2436 [(const_int 0)]
2437 "
2438 {
2439 rtx dest = operands[0];
2440 rtx src = operands[1];
2441 rtx op2 = operands[2];
2442 rtx op3 = operands[3];
2443 rtx op4 = operands[4];
2444 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2445 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2446 rtx addr1;
2447 rtx addr2;
2448 rtx word_high;
2449 rtx word_low;
2451 addr1 = XEXP (src, 0);
2452 if (GET_CODE (addr1) == PLUS)
2453 {
2454 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2455 addr1 = XEXP (addr1, 1);
2456 }
2457 else
2458 emit_move_insn (op2, GEN_INT (4));
2460 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2462 if (BYTES_BIG_ENDIAN)
2463 {
2464 word_high = change_address (src, SImode, addr1);
2465 word_low = change_address (src, SImode, addr2);
2466 }
2467 else
2468 {
2469 word_high = change_address (src, SImode, addr2);
2470 word_low = change_address (src, SImode, addr1);
2471 }
2473 emit_insn (gen_bswapsi2 (op3_32, word_low));
2474 emit_insn (gen_bswapsi2 (op4_32, word_high));
2475 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2476 emit_insn (gen_iordi3 (dest, dest, op4));
2477 }")
2479 (define_split
2480 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2481 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2482 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2483 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2484 (clobber (match_operand:DI 4 "" ""))]
2485 "TARGET_POWERPC64 && reload_completed && !TARGET_LDBRX"
2486 [(const_int 0)]
2487 "
2488 {
2489 rtx dest = operands[0];
2490 rtx src = operands[1];
2491 rtx op2 = operands[2];
2492 rtx op3 = operands[3];
2493 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2494 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2495 rtx addr1;
2496 rtx addr2;
2497 rtx word_high;
2498 rtx word_low;
2500 addr1 = XEXP (dest, 0);
2501 if (GET_CODE (addr1) == PLUS)
2502 {
2503 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2504 addr1 = XEXP (addr1, 1);
2505 }
2506 else
2507 emit_move_insn (op2, GEN_INT (4));
2509 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2511 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2512 if (BYTES_BIG_ENDIAN)
2513 {
2514 word_high = change_address (dest, SImode, addr1);
2515 word_low = change_address (dest, SImode, addr2);
2516 emit_insn (gen_bswapsi2 (word_high, src_si));
2517 emit_insn (gen_bswapsi2 (word_low, op3_si));
2518 }
2519 else
2520 {
2521 word_high = change_address (dest, SImode, addr2);
2522 word_low = change_address (dest, SImode, addr1);
2523 emit_insn (gen_bswapsi2 (word_low, src_si));
2524 emit_insn (gen_bswapsi2 (word_high, op3_si));
2525 }
2526 }")
2528 (define_split
2529 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2530 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2531 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2532 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2533 (clobber (match_operand:DI 4 "" ""))]
2534 "TARGET_POWERPC64 && reload_completed"
2535 [(const_int 0)]
2536 "
2537 {
2538 rtx dest = operands[0];
2539 rtx src = operands[1];
2540 rtx op2 = operands[2];
2541 rtx op3 = operands[3];
2542 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2543 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2544 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2545 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2547 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2548 emit_insn (gen_bswapsi2 (dest_si, src_si));
2549 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2550 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2551 emit_insn (gen_iordi3 (dest, dest, op3));
2552 }")
2554 (define_insn "bswapdi2_32bit"
2555 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2556 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2557 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2558 "TARGET_32BIT && (REG_P (operands[0]) || REG_P (operands[1]))"
2559 "#"
2560 [(set_attr "length" "16,12,36")])
2562 (define_split
2563 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2564 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2565 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2566 "TARGET_32BIT && reload_completed"
2567 [(const_int 0)]
2568 "
2569 {
2570 rtx dest = operands[0];
2571 rtx src = operands[1];
2572 rtx op2 = operands[2];
2573 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2574 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2575 rtx addr1;
2576 rtx addr2;
2577 rtx word_high;
2578 rtx word_low;
2580 addr1 = XEXP (src, 0);
2581 if (GET_CODE (addr1) == PLUS)
2582 {
2583 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2584 addr1 = XEXP (addr1, 1);
2585 }
2586 else
2587 emit_move_insn (op2, GEN_INT (4));
2589 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2591 if (BYTES_BIG_ENDIAN)
2592 {
2593 word_high = change_address (src, SImode, addr1);
2594 word_low = change_address (src, SImode, addr2);
2595 }
2596 else
2597 {
2598 word_high = change_address (src, SImode, addr2);
2599 word_low = change_address (src, SImode, addr1);
2600 }
2602 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2603 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2604 }")
2606 (define_split
2607 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2608 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2609 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2610 "TARGET_32BIT && reload_completed"
2611 [(const_int 0)]
2612 "
2613 {
2614 rtx dest = operands[0];
2615 rtx src = operands[1];
2616 rtx op2 = operands[2];
2617 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2618 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2619 rtx addr1;
2620 rtx addr2;
2621 rtx word_high;
2622 rtx word_low;
2624 addr1 = XEXP (dest, 0);
2625 if (GET_CODE (addr1) == PLUS)
2626 {
2627 emit_insn (gen_addsi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2628 addr1 = XEXP (addr1, 1);
2629 }
2630 else
2631 emit_move_insn (op2, GEN_INT (4));
2633 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2635 if (BYTES_BIG_ENDIAN)
2636 {
2637 word_high = change_address (dest, SImode, addr1);
2638 word_low = change_address (dest, SImode, addr2);
2639 }
2640 else
2641 {
2642 word_high = change_address (dest, SImode, addr2);
2643 word_low = change_address (dest, SImode, addr1);
2644 }
2646 emit_insn (gen_bswapsi2 (word_high, src_low));
2647 emit_insn (gen_bswapsi2 (word_low, src_high));
2648 }")
2650 (define_split
2651 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2652 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2653 (clobber (match_operand:SI 2 "" ""))]
2654 "TARGET_32BIT && reload_completed"
2655 [(const_int 0)]
2656 "
2657 {
2658 rtx dest = operands[0];
2659 rtx src = operands[1];
2660 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2661 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2662 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2663 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2665 emit_insn (gen_bswapsi2 (dest_high, src_low));
2666 emit_insn (gen_bswapsi2 (dest_low, src_high));
2667 }")
2669 (define_expand "mulsi3"
2670 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2671 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2672 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2673 ""
2674 "
2675 {
2676 if (TARGET_POWER)
2677 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2678 else
2679 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2680 DONE;
2681 }")
2683 (define_insn "mulsi3_mq"
2684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2685 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2686 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2687 (clobber (match_scratch:SI 3 "=q,q"))]
2688 "TARGET_POWER"
2689 "@
2690 {muls|mullw} %0,%1,%2
2691 {muli|mulli} %0,%1,%2"
2692 [(set (attr "type")
2693 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2694 (const_string "imul3")
2695 (match_operand:SI 2 "short_cint_operand" "")
2696 (const_string "imul2")]
2697 (const_string "imul")))])
2699 (define_insn "mulsi3_no_mq"
2700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2701 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2702 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2703 "! TARGET_POWER"
2704 "@
2705 {muls|mullw} %0,%1,%2
2706 {muli|mulli} %0,%1,%2"
2707 [(set (attr "type")
2708 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2709 (const_string "imul3")
2710 (match_operand:SI 2 "short_cint_operand" "")
2711 (const_string "imul2")]
2712 (const_string "imul")))])
2714 (define_insn "*mulsi3_mq_internal1"
2715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2716 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2717 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2718 (const_int 0)))
2719 (clobber (match_scratch:SI 3 "=r,r"))
2720 (clobber (match_scratch:SI 4 "=q,q"))]
2721 "TARGET_POWER"
2722 "@
2723 {muls.|mullw.} %3,%1,%2
2724 #"
2725 [(set_attr "type" "imul_compare")
2726 (set_attr "length" "4,8")])
2728 (define_split
2729 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2730 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2731 (match_operand:SI 2 "gpc_reg_operand" ""))
2732 (const_int 0)))
2733 (clobber (match_scratch:SI 3 ""))
2734 (clobber (match_scratch:SI 4 ""))]
2735 "TARGET_POWER && reload_completed"
2736 [(parallel [(set (match_dup 3)
2737 (mult:SI (match_dup 1) (match_dup 2)))
2738 (clobber (match_dup 4))])
2739 (set (match_dup 0)
2740 (compare:CC (match_dup 3)
2741 (const_int 0)))]
2742 "")
2744 (define_insn "*mulsi3_no_mq_internal1"
2745 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2746 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2747 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2748 (const_int 0)))
2749 (clobber (match_scratch:SI 3 "=r,r"))]
2750 "! TARGET_POWER"
2751 "@
2752 {muls.|mullw.} %3,%1,%2
2753 #"
2754 [(set_attr "type" "imul_compare")
2755 (set_attr "length" "4,8")])
2757 (define_split
2758 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2759 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2760 (match_operand:SI 2 "gpc_reg_operand" ""))
2761 (const_int 0)))
2762 (clobber (match_scratch:SI 3 ""))]
2763 "! TARGET_POWER && reload_completed"
2764 [(set (match_dup 3)
2765 (mult:SI (match_dup 1) (match_dup 2)))
2766 (set (match_dup 0)
2767 (compare:CC (match_dup 3)
2768 (const_int 0)))]
2769 "")
2771 (define_insn "*mulsi3_mq_internal2"
2772 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2773 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2774 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2775 (const_int 0)))
2776 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2777 (mult:SI (match_dup 1) (match_dup 2)))
2778 (clobber (match_scratch:SI 4 "=q,q"))]
2779 "TARGET_POWER"
2780 "@
2781 {muls.|mullw.} %0,%1,%2
2782 #"
2783 [(set_attr "type" "imul_compare")
2784 (set_attr "length" "4,8")])
2786 (define_split
2787 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2788 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2789 (match_operand:SI 2 "gpc_reg_operand" ""))
2790 (const_int 0)))
2791 (set (match_operand:SI 0 "gpc_reg_operand" "")
2792 (mult:SI (match_dup 1) (match_dup 2)))
2793 (clobber (match_scratch:SI 4 ""))]
2794 "TARGET_POWER && reload_completed"
2795 [(parallel [(set (match_dup 0)
2796 (mult:SI (match_dup 1) (match_dup 2)))
2797 (clobber (match_dup 4))])
2798 (set (match_dup 3)
2799 (compare:CC (match_dup 0)
2800 (const_int 0)))]
2801 "")
2803 (define_insn "*mulsi3_no_mq_internal2"
2804 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2805 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2806 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2807 (const_int 0)))
2808 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2809 (mult:SI (match_dup 1) (match_dup 2)))]
2810 "! TARGET_POWER"
2811 "@
2812 {muls.|mullw.} %0,%1,%2
2813 #"
2814 [(set_attr "type" "imul_compare")
2815 (set_attr "length" "4,8")])
2817 (define_split
2818 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2819 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2820 (match_operand:SI 2 "gpc_reg_operand" ""))
2821 (const_int 0)))
2822 (set (match_operand:SI 0 "gpc_reg_operand" "")
2823 (mult:SI (match_dup 1) (match_dup 2)))]
2824 "! TARGET_POWER && reload_completed"
2825 [(set (match_dup 0)
2826 (mult:SI (match_dup 1) (match_dup 2)))
2827 (set (match_dup 3)
2828 (compare:CC (match_dup 0)
2829 (const_int 0)))]
2830 "")
2832 ;; Operand 1 is divided by operand 2; quotient goes to operand
2833 ;; 0 and remainder to operand 3.
2834 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2836 (define_expand "divmodsi4"
2837 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2838 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2839 (match_operand:SI 2 "gpc_reg_operand" "")))
2840 (set (match_operand:SI 3 "register_operand" "")
2841 (mod:SI (match_dup 1) (match_dup 2)))])]
2842 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2843 "
2844 {
2845 if (! TARGET_POWER && ! TARGET_POWERPC)
2846 {
2847 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2848 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2849 emit_insn (gen_divss_call ());
2850 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2851 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2852 DONE;
2853 }
2854 }")
2856 (define_insn "*divmodsi4_internal"
2857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2858 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2859 (match_operand:SI 2 "gpc_reg_operand" "r")))
2860 (set (match_operand:SI 3 "register_operand" "=q")
2861 (mod:SI (match_dup 1) (match_dup 2)))]
2862 "TARGET_POWER"
2863 "divs %0,%1,%2"
2864 [(set_attr "type" "idiv")])
2866 (define_expand "udiv<mode>3"
2867 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2868 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2869 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2870 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2871 "
2872 {
2873 if (! TARGET_POWER && ! TARGET_POWERPC)
2874 {
2875 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2876 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2877 emit_insn (gen_quous_call ());
2878 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2879 DONE;
2880 }
2881 else if (TARGET_POWER)
2882 {
2883 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2884 DONE;
2885 }
2886 }")
2888 (define_insn "udivsi3_mq"
2889 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2890 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2891 (match_operand:SI 2 "gpc_reg_operand" "r")))
2892 (clobber (match_scratch:SI 3 "=q"))]
2893 "TARGET_POWERPC && TARGET_POWER"
2894 "divwu %0,%1,%2"
2895 [(set_attr "type" "idiv")])
2897 (define_insn "*udivsi3_no_mq"
2898 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2899 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2900 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2901 "TARGET_POWERPC && ! TARGET_POWER"
2902 "div<wd>u %0,%1,%2"
2903 [(set (attr "type")
2904 (cond [(match_operand:SI 0 "" "")
2905 (const_string "idiv")]
2906 (const_string "ldiv")))])
2909 ;; For powers of two we can do srai/aze for divide and then adjust for
2910 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2911 ;; used; for PowerPC, force operands into register and do a normal divide;
2912 ;; for AIX common-mode, use quoss call on register operands.
2913 (define_expand "div<mode>3"
2914 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2915 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2916 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2917 ""
2918 "
2919 {
2920 if (GET_CODE (operands[2]) == CONST_INT
2921 && INTVAL (operands[2]) > 0
2922 && exact_log2 (INTVAL (operands[2])) >= 0)
2923 ;
2924 else if (TARGET_POWERPC)
2925 {
2926 operands[2] = force_reg (<MODE>mode, operands[2]);
2927 if (TARGET_POWER)
2928 {
2929 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2930 DONE;
2931 }
2932 }
2933 else if (TARGET_POWER)
2934 FAIL;
2935 else
2936 {
2937 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2938 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2939 emit_insn (gen_quoss_call ());
2940 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2941 DONE;
2942 }
2943 }")
2945 (define_insn "divsi3_mq"
2946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2947 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2948 (match_operand:SI 2 "gpc_reg_operand" "r")))
2949 (clobber (match_scratch:SI 3 "=q"))]
2950 "TARGET_POWERPC && TARGET_POWER"
2951 "divw %0,%1,%2"
2952 [(set_attr "type" "idiv")])
2954 (define_insn "*div<mode>3_no_mq"
2955 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2956 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2957 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2958 "TARGET_POWERPC && ! TARGET_POWER"
2959 "div<wd> %0,%1,%2"
2960 [(set (attr "type")
2961 (cond [(match_operand:SI 0 "" "")
2962 (const_string "idiv")]
2963 (const_string "ldiv")))])
2965 (define_expand "mod<mode>3"
2966 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2967 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2968 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2969 ""
2970 "
2971 {
2972 int i;
2973 rtx temp1;
2974 rtx temp2;
2976 if (GET_CODE (operands[2]) != CONST_INT
2977 || INTVAL (operands[2]) <= 0
2978 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2979 FAIL;
2981 temp1 = gen_reg_rtx (<MODE>mode);
2982 temp2 = gen_reg_rtx (<MODE>mode);
2984 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2985 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2986 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2987 DONE;
2988 }")
2990 (define_insn ""
2991 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2992 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2993 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2994 ""
2995 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2996 [(set_attr "type" "two")
2997 (set_attr "length" "8")])
2999 (define_insn ""
3000 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3001 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3002 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3003 (const_int 0)))
3004 (clobber (match_scratch:P 3 "=r,r"))]
3005 ""
3006 "@
3007 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3008 #"
3009 [(set_attr "type" "compare")
3010 (set_attr "length" "8,12")
3011 (set_attr "cell_micro" "not")])
3013 (define_split
3014 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3015 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3016 (match_operand:GPR 2 "exact_log2_cint_operand"
3017 ""))
3018 (const_int 0)))
3019 (clobber (match_scratch:GPR 3 ""))]
3020 "reload_completed"
3021 [(set (match_dup 3)
3022 (div:<MODE> (match_dup 1) (match_dup 2)))
3023 (set (match_dup 0)
3024 (compare:CC (match_dup 3)
3025 (const_int 0)))]
3026 "")
3028 (define_insn ""
3029 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3030 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3031 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3032 (const_int 0)))
3033 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3034 (div:P (match_dup 1) (match_dup 2)))]
3035 ""
3036 "@
3037 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3038 #"
3039 [(set_attr "type" "compare")
3040 (set_attr "length" "8,12")
3041 (set_attr "cell_micro" "not")])
3043 (define_split
3044 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3045 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3046 (match_operand:GPR 2 "exact_log2_cint_operand"
3047 ""))
3048 (const_int 0)))
3049 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3050 (div:GPR (match_dup 1) (match_dup 2)))]
3051 "reload_completed"
3052 [(set (match_dup 0)
3053 (div:<MODE> (match_dup 1) (match_dup 2)))
3054 (set (match_dup 3)
3055 (compare:CC (match_dup 0)
3056 (const_int 0)))]
3057 "")
3059 (define_insn ""
3060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3061 (udiv:SI
3062 (plus:DI (ashift:DI
3063 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3064 (const_int 32))
3065 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3066 (match_operand:SI 3 "gpc_reg_operand" "r")))
3067 (set (match_operand:SI 2 "register_operand" "=*q")
3068 (umod:SI
3069 (plus:DI (ashift:DI
3070 (zero_extend:DI (match_dup 1)) (const_int 32))
3071 (zero_extend:DI (match_dup 4)))
3072 (match_dup 3)))]
3073 "TARGET_POWER"
3074 "div %0,%1,%3"
3075 [(set_attr "type" "idiv")])
3077 ;; To do unsigned divide we handle the cases of the divisor looking like a
3078 ;; negative number. If it is a constant that is less than 2**31, we don't
3079 ;; have to worry about the branches. So make a few subroutines here.
3080 ;;
3081 ;; First comes the normal case.
3082 (define_expand "udivmodsi4_normal"
3083 [(set (match_dup 4) (const_int 0))
3084 (parallel [(set (match_operand:SI 0 "" "")
3085 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3086 (const_int 32))
3087 (zero_extend:DI (match_operand:SI 1 "" "")))
3088 (match_operand:SI 2 "" "")))
3089 (set (match_operand:SI 3 "" "")
3090 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3091 (const_int 32))
3092 (zero_extend:DI (match_dup 1)))
3093 (match_dup 2)))])]
3094 "TARGET_POWER"
3095 "
3096 { operands[4] = gen_reg_rtx (SImode); }")
3098 ;; This handles the branches.
3099 (define_expand "udivmodsi4_tests"
3100 [(set (match_operand:SI 0 "" "") (const_int 0))
3101 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3102 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3103 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3104 (label_ref (match_operand:SI 4 "" "")) (pc)))
3105 (set (match_dup 0) (const_int 1))
3106 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3107 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3108 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3109 (label_ref (match_dup 4)) (pc)))]
3110 "TARGET_POWER"
3111 "
3112 { operands[5] = gen_reg_rtx (CCUNSmode);
3113 operands[6] = gen_reg_rtx (CCmode);
3114 }")
3116 (define_expand "udivmodsi4"
3117 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3118 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3119 (match_operand:SI 2 "reg_or_cint_operand" "")))
3120 (set (match_operand:SI 3 "gpc_reg_operand" "")
3121 (umod:SI (match_dup 1) (match_dup 2)))])]
3122 ""
3123 "
3124 {
3125 rtx label = 0;
3127 if (! TARGET_POWER)
3128 {
3129 if (! TARGET_POWERPC)
3130 {
3131 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3132 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3133 emit_insn (gen_divus_call ());
3134 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3135 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3136 DONE;
3137 }
3138 else
3139 FAIL;
3140 }
3142 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3143 {
3144 operands[2] = force_reg (SImode, operands[2]);
3145 label = gen_label_rtx ();
3146 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3147 operands[3], label));
3148 }
3149 else
3150 operands[2] = force_reg (SImode, operands[2]);
3152 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3153 operands[3]));
3154 if (label)
3155 emit_label (label);
3157 DONE;
3158 }")
3160 ;; AIX architecture-independent common-mode multiply (DImode),
3161 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3162 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3163 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3164 ;; assumed unused if generating common-mode, so ignore.
3165 (define_insn "mulh_call"
3166 [(set (reg:SI 3)
3167 (truncate:SI
3168 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3169 (sign_extend:DI (reg:SI 4)))
3170 (const_int 32))))
3171 (clobber (reg:SI LR_REGNO))]
3172 "! TARGET_POWER && ! TARGET_POWERPC"
3173 "bla __mulh"
3174 [(set_attr "type" "imul")])
3176 (define_insn "mull_call"
3177 [(set (reg:DI 3)
3178 (mult:DI (sign_extend:DI (reg:SI 3))
3179 (sign_extend:DI (reg:SI 4))))
3180 (clobber (reg:SI LR_REGNO))
3181 (clobber (reg:SI 0))]
3182 "! TARGET_POWER && ! TARGET_POWERPC"
3183 "bla __mull"
3184 [(set_attr "type" "imul")])
3186 (define_insn "divss_call"
3187 [(set (reg:SI 3)
3188 (div:SI (reg:SI 3) (reg:SI 4)))
3189 (set (reg:SI 4)
3190 (mod:SI (reg:SI 3) (reg:SI 4)))
3191 (clobber (reg:SI LR_REGNO))
3192 (clobber (reg:SI 0))]
3193 "! TARGET_POWER && ! TARGET_POWERPC"
3194 "bla __divss"
3195 [(set_attr "type" "idiv")])
3197 (define_insn "divus_call"
3198 [(set (reg:SI 3)
3199 (udiv:SI (reg:SI 3) (reg:SI 4)))
3200 (set (reg:SI 4)
3201 (umod:SI (reg:SI 3) (reg:SI 4)))
3202 (clobber (reg:SI LR_REGNO))
3203 (clobber (reg:SI 0))
3204 (clobber (match_scratch:CC 0 "=x"))
3205 (clobber (reg:CC CR1_REGNO))]
3206 "! TARGET_POWER && ! TARGET_POWERPC"
3207 "bla __divus"
3208 [(set_attr "type" "idiv")])
3210 (define_insn "quoss_call"
3211 [(set (reg:SI 3)
3212 (div:SI (reg:SI 3) (reg:SI 4)))
3213 (clobber (reg:SI LR_REGNO))]
3214 "! TARGET_POWER && ! TARGET_POWERPC"
3215 "bla __quoss"
3216 [(set_attr "type" "idiv")])
3218 (define_insn "quous_call"
3219 [(set (reg:SI 3)
3220 (udiv:SI (reg:SI 3) (reg:SI 4)))
3221 (clobber (reg:SI LR_REGNO))
3222 (clobber (reg:SI 0))
3223 (clobber (match_scratch:CC 0 "=x"))
3224 (clobber (reg:CC CR1_REGNO))]
3225 "! TARGET_POWER && ! TARGET_POWERPC"
3226 "bla __quous"
3227 [(set_attr "type" "idiv")])
3228 \f
3229 ;; Logical instructions
3230 ;; The logical instructions are mostly combined by using match_operator,
3231 ;; but the plain AND insns are somewhat different because there is no
3232 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3233 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3235 (define_expand "andsi3"
3236 [(parallel
3237 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3238 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3239 (match_operand:SI 2 "and_operand" "")))
3240 (clobber (match_scratch:CC 3 ""))])]
3241 ""
3242 "")
3244 (define_insn "andsi3_mc"
3245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3246 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3247 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3248 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3249 "rs6000_gen_cell_microcode"
3250 "@
3251 and %0,%1,%2
3252 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3253 {andil.|andi.} %0,%1,%b2
3254 {andiu.|andis.} %0,%1,%u2"
3255 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3257 (define_insn "andsi3_nomc"
3258 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3259 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3260 (match_operand:SI 2 "and_operand" "?r,T")))
3261 (clobber (match_scratch:CC 3 "=X,X"))]
3262 "!rs6000_gen_cell_microcode"
3263 "@
3264 and %0,%1,%2
3265 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3267 (define_insn "andsi3_internal0_nomc"
3268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3269 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3270 (match_operand:SI 2 "and_operand" "?r,T")))]
3271 "!rs6000_gen_cell_microcode"
3272 "@
3273 and %0,%1,%2
3274 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3277 ;; Note to set cr's other than cr0 we do the and immediate and then
3278 ;; the test again -- this avoids a mfcr which on the higher end
3279 ;; machines causes an execution serialization
3281 (define_insn "*andsi3_internal2_mc"
3282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3283 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3284 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3285 (const_int 0)))
3286 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3287 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3288 "TARGET_32BIT && rs6000_gen_cell_microcode"
3289 "@
3290 and. %3,%1,%2
3291 {andil.|andi.} %3,%1,%b2
3292 {andiu.|andis.} %3,%1,%u2
3293 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3294 #
3295 #
3296 #
3297 #"
3298 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3299 compare,compare,compare,compare")
3300 (set_attr "length" "4,4,4,4,8,8,8,8")])
3302 (define_insn "*andsi3_internal3_mc"
3303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3304 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3305 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3306 (const_int 0)))
3307 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3308 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3309 "TARGET_64BIT && rs6000_gen_cell_microcode"
3310 "@
3311 #
3312 {andil.|andi.} %3,%1,%b2
3313 {andiu.|andis.} %3,%1,%u2
3314 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3315 #
3316 #
3317 #
3318 #"
3319 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3320 compare,compare,compare")
3321 (set_attr "length" "8,4,4,4,8,8,8,8")])
3323 (define_split
3324 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3325 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3326 (match_operand:GPR 2 "and_operand" ""))
3327 (const_int 0)))
3328 (clobber (match_scratch:GPR 3 ""))
3329 (clobber (match_scratch:CC 4 ""))]
3330 "reload_completed"
3331 [(parallel [(set (match_dup 3)
3332 (and:<MODE> (match_dup 1)
3333 (match_dup 2)))
3334 (clobber (match_dup 4))])
3335 (set (match_dup 0)
3336 (compare:CC (match_dup 3)
3337 (const_int 0)))]
3338 "")
3340 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3341 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3343 (define_split
3344 [(set (match_operand:CC 0 "cc_reg_operand" "")
3345 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3346 (match_operand:SI 2 "gpc_reg_operand" ""))
3347 (const_int 0)))
3348 (clobber (match_scratch:SI 3 ""))
3349 (clobber (match_scratch:CC 4 ""))]
3350 "TARGET_POWERPC64 && reload_completed"
3351 [(parallel [(set (match_dup 3)
3352 (and:SI (match_dup 1)
3353 (match_dup 2)))
3354 (clobber (match_dup 4))])
3355 (set (match_dup 0)
3356 (compare:CC (match_dup 3)
3357 (const_int 0)))]
3358 "")
3360 (define_insn "*andsi3_internal4"
3361 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3362 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3363 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3364 (const_int 0)))
3365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3366 (and:SI (match_dup 1)
3367 (match_dup 2)))
3368 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3369 "TARGET_32BIT && rs6000_gen_cell_microcode"
3370 "@
3371 and. %0,%1,%2
3372 {andil.|andi.} %0,%1,%b2
3373 {andiu.|andis.} %0,%1,%u2
3374 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3375 #
3376 #
3377 #
3378 #"
3379 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3380 compare,compare,compare,compare")
3381 (set_attr "length" "4,4,4,4,8,8,8,8")])
3383 (define_insn "*andsi3_internal5_mc"
3384 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3385 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3386 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3387 (const_int 0)))
3388 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3389 (and:SI (match_dup 1)
3390 (match_dup 2)))
3391 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3392 "TARGET_64BIT && rs6000_gen_cell_microcode"
3393 "@
3394 #
3395 {andil.|andi.} %0,%1,%b2
3396 {andiu.|andis.} %0,%1,%u2
3397 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3398 #
3399 #
3400 #
3401 #"
3402 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3403 compare,compare,compare")
3404 (set_attr "length" "8,4,4,4,8,8,8,8")])
3406 (define_split
3407 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3408 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3409 (match_operand:SI 2 "and_operand" ""))
3410 (const_int 0)))
3411 (set (match_operand:SI 0 "gpc_reg_operand" "")
3412 (and:SI (match_dup 1)
3413 (match_dup 2)))
3414 (clobber (match_scratch:CC 4 ""))]
3415 "reload_completed"
3416 [(parallel [(set (match_dup 0)
3417 (and:SI (match_dup 1)
3418 (match_dup 2)))
3419 (clobber (match_dup 4))])
3420 (set (match_dup 3)
3421 (compare:CC (match_dup 0)
3422 (const_int 0)))]
3423 "")
3425 (define_split
3426 [(set (match_operand:CC 3 "cc_reg_operand" "")
3427 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3428 (match_operand:SI 2 "gpc_reg_operand" ""))
3429 (const_int 0)))
3430 (set (match_operand:SI 0 "gpc_reg_operand" "")
3431 (and:SI (match_dup 1)
3432 (match_dup 2)))
3433 (clobber (match_scratch:CC 4 ""))]
3434 "TARGET_POWERPC64 && reload_completed"
3435 [(parallel [(set (match_dup 0)
3436 (and:SI (match_dup 1)
3437 (match_dup 2)))
3438 (clobber (match_dup 4))])
3439 (set (match_dup 3)
3440 (compare:CC (match_dup 0)
3441 (const_int 0)))]
3442 "")
3444 ;; Handle the PowerPC64 rlwinm corner case
3446 (define_insn_and_split "*andsi3_internal6"
3447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3448 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3449 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3450 "TARGET_POWERPC64"
3451 "#"
3452 "TARGET_POWERPC64"
3453 [(set (match_dup 0)
3454 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3455 (match_dup 4)))
3456 (set (match_dup 0)
3457 (rotate:SI (match_dup 0) (match_dup 5)))]
3458 "
3459 {
3460 int mb = extract_MB (operands[2]);
3461 int me = extract_ME (operands[2]);
3462 operands[3] = GEN_INT (me + 1);
3463 operands[5] = GEN_INT (32 - (me + 1));
3464 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3465 }"
3466 [(set_attr "length" "8")])
3468 (define_expand "iorsi3"
3469 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3470 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3471 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3472 ""
3473 "
3474 {
3475 if (GET_CODE (operands[2]) == CONST_INT
3476 && ! logical_operand (operands[2], SImode))
3477 {
3478 HOST_WIDE_INT value = INTVAL (operands[2]);
3479 rtx tmp = ((!can_create_pseudo_p ()
3480 || rtx_equal_p (operands[0], operands[1]))
3481 ? operands[0] : gen_reg_rtx (SImode));
3483 emit_insn (gen_iorsi3 (tmp, operands[1],
3484 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3485 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3486 DONE;
3487 }
3488 }")
3490 (define_expand "xorsi3"
3491 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3492 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3493 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3494 ""
3495 "
3496 {
3497 if (GET_CODE (operands[2]) == CONST_INT
3498 && ! logical_operand (operands[2], SImode))
3499 {
3500 HOST_WIDE_INT value = INTVAL (operands[2]);
3501 rtx tmp = ((!can_create_pseudo_p ()
3502 || rtx_equal_p (operands[0], operands[1]))
3503 ? operands[0] : gen_reg_rtx (SImode));
3505 emit_insn (gen_xorsi3 (tmp, operands[1],
3506 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3507 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3508 DONE;
3509 }
3510 }")
3512 (define_insn "*boolsi3_internal1"
3513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3514 (match_operator:SI 3 "boolean_or_operator"
3515 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3516 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3517 ""
3518 "@
3519 %q3 %0,%1,%2
3520 {%q3il|%q3i} %0,%1,%b2
3521 {%q3iu|%q3is} %0,%1,%u2")
3523 (define_insn "*boolsi3_internal2"
3524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3525 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3526 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3527 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3528 (const_int 0)))
3529 (clobber (match_scratch:SI 3 "=r,r"))]
3530 "TARGET_32BIT"
3531 "@
3532 %q4. %3,%1,%2
3533 #"
3534 [(set_attr "type" "fast_compare,compare")
3535 (set_attr "length" "4,8")])
3537 (define_split
3538 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3539 (compare:CC (match_operator:SI 4 "boolean_operator"
3540 [(match_operand:SI 1 "gpc_reg_operand" "")
3541 (match_operand:SI 2 "gpc_reg_operand" "")])
3542 (const_int 0)))
3543 (clobber (match_scratch:SI 3 ""))]
3544 "TARGET_32BIT && reload_completed"
3545 [(set (match_dup 3) (match_dup 4))
3546 (set (match_dup 0)
3547 (compare:CC (match_dup 3)
3548 (const_int 0)))]
3549 "")
3551 (define_insn "*boolsi3_internal3"
3552 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3553 (compare:CC (match_operator:SI 4 "boolean_operator"
3554 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3555 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3556 (const_int 0)))
3557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3558 (match_dup 4))]
3559 "TARGET_32BIT"
3560 "@
3561 %q4. %0,%1,%2
3562 #"
3563 [(set_attr "type" "fast_compare,compare")
3564 (set_attr "length" "4,8")])
3566 (define_split
3567 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3568 (compare:CC (match_operator:SI 4 "boolean_operator"
3569 [(match_operand:SI 1 "gpc_reg_operand" "")
3570 (match_operand:SI 2 "gpc_reg_operand" "")])
3571 (const_int 0)))
3572 (set (match_operand:SI 0 "gpc_reg_operand" "")
3573 (match_dup 4))]
3574 "TARGET_32BIT && reload_completed"
3575 [(set (match_dup 0) (match_dup 4))
3576 (set (match_dup 3)
3577 (compare:CC (match_dup 0)
3578 (const_int 0)))]
3579 "")
3581 ;; Split a logical operation that we can't do in one insn into two insns,
3582 ;; each of which does one 16-bit part. This is used by combine.
3584 (define_split
3585 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3586 (match_operator:SI 3 "boolean_or_operator"
3587 [(match_operand:SI 1 "gpc_reg_operand" "")
3588 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3589 ""
3590 [(set (match_dup 0) (match_dup 4))
3591 (set (match_dup 0) (match_dup 5))]
3592 "
3593 {
3594 rtx i;
3595 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3596 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3597 operands[1], i);
3598 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3599 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3600 operands[0], i);
3601 }")
3603 (define_insn "*boolcsi3_internal1"
3604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3605 (match_operator:SI 3 "boolean_operator"
3606 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3607 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3608 ""
3609 "%q3 %0,%2,%1")
3611 (define_insn "*boolcsi3_internal2"
3612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3613 (compare:CC (match_operator:SI 4 "boolean_operator"
3614 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3615 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3616 (const_int 0)))
3617 (clobber (match_scratch:SI 3 "=r,r"))]
3618 "TARGET_32BIT"
3619 "@
3620 %q4. %3,%2,%1
3621 #"
3622 [(set_attr "type" "compare")
3623 (set_attr "length" "4,8")])
3625 (define_split
3626 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3627 (compare:CC (match_operator:SI 4 "boolean_operator"
3628 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3629 (match_operand:SI 2 "gpc_reg_operand" "")])
3630 (const_int 0)))
3631 (clobber (match_scratch:SI 3 ""))]
3632 "TARGET_32BIT && reload_completed"
3633 [(set (match_dup 3) (match_dup 4))
3634 (set (match_dup 0)
3635 (compare:CC (match_dup 3)
3636 (const_int 0)))]
3637 "")
3639 (define_insn "*boolcsi3_internal3"
3640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3641 (compare:CC (match_operator:SI 4 "boolean_operator"
3642 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3643 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3644 (const_int 0)))
3645 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3646 (match_dup 4))]
3647 "TARGET_32BIT"
3648 "@
3649 %q4. %0,%2,%1
3650 #"
3651 [(set_attr "type" "compare")
3652 (set_attr "length" "4,8")])
3654 (define_split
3655 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3656 (compare:CC (match_operator:SI 4 "boolean_operator"
3657 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3658 (match_operand:SI 2 "gpc_reg_operand" "")])
3659 (const_int 0)))
3660 (set (match_operand:SI 0 "gpc_reg_operand" "")
3661 (match_dup 4))]
3662 "TARGET_32BIT && reload_completed"
3663 [(set (match_dup 0) (match_dup 4))
3664 (set (match_dup 3)
3665 (compare:CC (match_dup 0)
3666 (const_int 0)))]
3667 "")
3669 (define_insn "*boolccsi3_internal1"
3670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3671 (match_operator:SI 3 "boolean_operator"
3672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3673 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3674 ""
3675 "%q3 %0,%1,%2")
3677 (define_insn "*boolccsi3_internal2"
3678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3679 (compare:CC (match_operator:SI 4 "boolean_operator"
3680 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3681 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3682 (const_int 0)))
3683 (clobber (match_scratch:SI 3 "=r,r"))]
3684 "TARGET_32BIT"
3685 "@
3686 %q4. %3,%1,%2
3687 #"
3688 [(set_attr "type" "fast_compare,compare")
3689 (set_attr "length" "4,8")])
3691 (define_split
3692 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3693 (compare:CC (match_operator:SI 4 "boolean_operator"
3694 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3695 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3696 (const_int 0)))
3697 (clobber (match_scratch:SI 3 ""))]
3698 "TARGET_32BIT && reload_completed"
3699 [(set (match_dup 3) (match_dup 4))
3700 (set (match_dup 0)
3701 (compare:CC (match_dup 3)
3702 (const_int 0)))]
3703 "")
3705 (define_insn "*boolccsi3_internal3"
3706 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3707 (compare:CC (match_operator:SI 4 "boolean_operator"
3708 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3709 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3710 (const_int 0)))
3711 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3712 (match_dup 4))]
3713 "TARGET_32BIT"
3714 "@
3715 %q4. %0,%1,%2
3716 #"
3717 [(set_attr "type" "fast_compare,compare")
3718 (set_attr "length" "4,8")])
3720 (define_split
3721 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3722 (compare:CC (match_operator:SI 4 "boolean_operator"
3723 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3724 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3725 (const_int 0)))
3726 (set (match_operand:SI 0 "gpc_reg_operand" "")
3727 (match_dup 4))]
3728 "TARGET_32BIT && reload_completed"
3729 [(set (match_dup 0) (match_dup 4))
3730 (set (match_dup 3)
3731 (compare:CC (match_dup 0)
3732 (const_int 0)))]
3733 "")
3735 ;; maskir insn. We need four forms because things might be in arbitrary
3736 ;; orders. Don't define forms that only set CR fields because these
3737 ;; would modify an input register.
3739 (define_insn "*maskir_internal1"
3740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3741 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3742 (match_operand:SI 1 "gpc_reg_operand" "0"))
3743 (and:SI (match_dup 2)
3744 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3745 "TARGET_POWER"
3746 "maskir %0,%3,%2")
3748 (define_insn "*maskir_internal2"
3749 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3750 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3751 (match_operand:SI 1 "gpc_reg_operand" "0"))
3752 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3753 (match_dup 2))))]
3754 "TARGET_POWER"
3755 "maskir %0,%3,%2")
3757 (define_insn "*maskir_internal3"
3758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3759 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3760 (match_operand:SI 3 "gpc_reg_operand" "r"))
3761 (and:SI (not:SI (match_dup 2))
3762 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3763 "TARGET_POWER"
3764 "maskir %0,%3,%2")
3766 (define_insn "*maskir_internal4"
3767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3768 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3769 (match_operand:SI 2 "gpc_reg_operand" "r"))
3770 (and:SI (not:SI (match_dup 2))
3771 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3772 "TARGET_POWER"
3773 "maskir %0,%3,%2")
3775 (define_insn "*maskir_internal5"
3776 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3777 (compare:CC
3778 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3779 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3780 (and:SI (match_dup 2)
3781 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3782 (const_int 0)))
3783 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3784 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3785 (and:SI (match_dup 2) (match_dup 3))))]
3786 "TARGET_POWER"
3787 "@
3788 maskir. %0,%3,%2
3789 #"
3790 [(set_attr "type" "compare")
3791 (set_attr "length" "4,8")])
3793 (define_split
3794 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3795 (compare:CC
3796 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3797 (match_operand:SI 1 "gpc_reg_operand" ""))
3798 (and:SI (match_dup 2)
3799 (match_operand:SI 3 "gpc_reg_operand" "")))
3800 (const_int 0)))
3801 (set (match_operand:SI 0 "gpc_reg_operand" "")
3802 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3803 (and:SI (match_dup 2) (match_dup 3))))]
3804 "TARGET_POWER && reload_completed"
3805 [(set (match_dup 0)
3806 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3807 (and:SI (match_dup 2) (match_dup 3))))
3808 (set (match_dup 4)
3809 (compare:CC (match_dup 0)
3810 (const_int 0)))]
3811 "")
3813 (define_insn "*maskir_internal6"
3814 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3815 (compare:CC
3816 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3817 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3818 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3819 (match_dup 2)))
3820 (const_int 0)))
3821 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3822 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3823 (and:SI (match_dup 3) (match_dup 2))))]
3824 "TARGET_POWER"
3825 "@
3826 maskir. %0,%3,%2
3827 #"
3828 [(set_attr "type" "compare")
3829 (set_attr "length" "4,8")])
3831 (define_split
3832 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3833 (compare:CC
3834 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3835 (match_operand:SI 1 "gpc_reg_operand" ""))
3836 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3837 (match_dup 2)))
3838 (const_int 0)))
3839 (set (match_operand:SI 0 "gpc_reg_operand" "")
3840 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3841 (and:SI (match_dup 3) (match_dup 2))))]
3842 "TARGET_POWER && reload_completed"
3843 [(set (match_dup 0)
3844 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3845 (and:SI (match_dup 3) (match_dup 2))))
3846 (set (match_dup 4)
3847 (compare:CC (match_dup 0)
3848 (const_int 0)))]
3849 "")
3851 (define_insn "*maskir_internal7"
3852 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3853 (compare:CC
3854 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3855 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3856 (and:SI (not:SI (match_dup 2))
3857 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3858 (const_int 0)))
3859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3860 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3861 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3862 "TARGET_POWER"
3863 "@
3864 maskir. %0,%3,%2
3865 #"
3866 [(set_attr "type" "compare")
3867 (set_attr "length" "4,8")])
3869 (define_split
3870 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3871 (compare:CC
3872 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3873 (match_operand:SI 3 "gpc_reg_operand" ""))
3874 (and:SI (not:SI (match_dup 2))
3875 (match_operand:SI 1 "gpc_reg_operand" "")))
3876 (const_int 0)))
3877 (set (match_operand:SI 0 "gpc_reg_operand" "")
3878 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3879 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3880 "TARGET_POWER && reload_completed"
3881 [(set (match_dup 0)
3882 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3883 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3884 (set (match_dup 4)
3885 (compare:CC (match_dup 0)
3886 (const_int 0)))]
3887 "")
3889 (define_insn "*maskir_internal8"
3890 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3891 (compare:CC
3892 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3893 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3894 (and:SI (not:SI (match_dup 2))
3895 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3896 (const_int 0)))
3897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3898 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3899 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3900 "TARGET_POWER"
3901 "@
3902 maskir. %0,%3,%2
3903 #"
3904 [(set_attr "type" "compare")
3905 (set_attr "length" "4,8")])
3907 (define_split
3908 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3909 (compare:CC
3910 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3911 (match_operand:SI 2 "gpc_reg_operand" ""))
3912 (and:SI (not:SI (match_dup 2))
3913 (match_operand:SI 1 "gpc_reg_operand" "")))
3914 (const_int 0)))
3915 (set (match_operand:SI 0 "gpc_reg_operand" "")
3916 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3917 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3918 "TARGET_POWER && reload_completed"
3919 [(set (match_dup 0)
3920 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3921 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3922 (set (match_dup 4)
3923 (compare:CC (match_dup 0)
3924 (const_int 0)))]
3925 "")
3926 \f
3927 ;; Rotate and shift insns, in all their variants. These support shifts,
3928 ;; field inserts and extracts, and various combinations thereof.
3929 (define_expand "insv"
3930 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3931 (match_operand:SI 1 "const_int_operand" "")
3932 (match_operand:SI 2 "const_int_operand" ""))
3933 (match_operand 3 "gpc_reg_operand" ""))]
3934 ""
3935 "
3936 {
3937 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3938 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3939 compiler if the address of the structure is taken later. Likewise, do
3940 not handle invalid E500 subregs. */
3941 if (GET_CODE (operands[0]) == SUBREG
3942 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3943 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3944 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3945 FAIL;
3947 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3948 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3949 else
3950 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3951 DONE;
3952 }")
3954 (define_insn "insvsi"
3955 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3956 (match_operand:SI 1 "const_int_operand" "i")
3957 (match_operand:SI 2 "const_int_operand" "i"))
3958 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3959 ""
3960 "*
3961 {
3962 int start = INTVAL (operands[2]) & 31;
3963 int size = INTVAL (operands[1]) & 31;
3965 operands[4] = GEN_INT (32 - start - size);
3966 operands[1] = GEN_INT (start + size - 1);
3967 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3968 }"
3969 [(set_attr "type" "insert_word")])
3971 (define_insn "*insvsi_internal1"
3972 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3973 (match_operand:SI 1 "const_int_operand" "i")
3974 (match_operand:SI 2 "const_int_operand" "i"))
3975 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3976 (match_operand:SI 4 "const_int_operand" "i")))]
3977 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3978 "*
3979 {
3980 int shift = INTVAL (operands[4]) & 31;
3981 int start = INTVAL (operands[2]) & 31;
3982 int size = INTVAL (operands[1]) & 31;
3984 operands[4] = GEN_INT (shift - start - size);
3985 operands[1] = GEN_INT (start + size - 1);
3986 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3987 }"
3988 [(set_attr "type" "insert_word")])
3990 (define_insn "*insvsi_internal2"
3991 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3992 (match_operand:SI 1 "const_int_operand" "i")
3993 (match_operand:SI 2 "const_int_operand" "i"))
3994 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3995 (match_operand:SI 4 "const_int_operand" "i")))]
3996 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3997 "*
3998 {
3999 int shift = INTVAL (operands[4]) & 31;
4000 int start = INTVAL (operands[2]) & 31;
4001 int size = INTVAL (operands[1]) & 31;
4003 operands[4] = GEN_INT (32 - shift - start - size);
4004 operands[1] = GEN_INT (start + size - 1);
4005 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4006 }"
4007 [(set_attr "type" "insert_word")])
4009 (define_insn "*insvsi_internal3"
4010 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4011 (match_operand:SI 1 "const_int_operand" "i")
4012 (match_operand:SI 2 "const_int_operand" "i"))
4013 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4014 (match_operand:SI 4 "const_int_operand" "i")))]
4015 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4016 "*
4017 {
4018 int shift = INTVAL (operands[4]) & 31;
4019 int start = INTVAL (operands[2]) & 31;
4020 int size = INTVAL (operands[1]) & 31;
4022 operands[4] = GEN_INT (32 - shift - start - size);
4023 operands[1] = GEN_INT (start + size - 1);
4024 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4025 }"
4026 [(set_attr "type" "insert_word")])
4028 (define_insn "*insvsi_internal4"
4029 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4030 (match_operand:SI 1 "const_int_operand" "i")
4031 (match_operand:SI 2 "const_int_operand" "i"))
4032 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4033 (match_operand:SI 4 "const_int_operand" "i")
4034 (match_operand:SI 5 "const_int_operand" "i")))]
4035 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4036 "*
4037 {
4038 int extract_start = INTVAL (operands[5]) & 31;
4039 int extract_size = INTVAL (operands[4]) & 31;
4040 int insert_start = INTVAL (operands[2]) & 31;
4041 int insert_size = INTVAL (operands[1]) & 31;
4043 /* Align extract field with insert field */
4044 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4045 operands[1] = GEN_INT (insert_start + insert_size - 1);
4046 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4047 }"
4048 [(set_attr "type" "insert_word")])
4050 ;; combine patterns for rlwimi
4051 (define_insn "*insvsi_internal5"
4052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4053 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4054 (match_operand:SI 1 "mask_operand" "i"))
4055 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4056 (match_operand:SI 2 "const_int_operand" "i"))
4057 (match_operand:SI 5 "mask_operand" "i"))))]
4058 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4059 "*
4060 {
4061 int me = extract_ME(operands[5]);
4062 int mb = extract_MB(operands[5]);
4063 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4064 operands[2] = GEN_INT(mb);
4065 operands[1] = GEN_INT(me);
4066 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4067 }"
4068 [(set_attr "type" "insert_word")])
4070 (define_insn "*insvsi_internal6"
4071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4072 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4073 (match_operand:SI 2 "const_int_operand" "i"))
4074 (match_operand:SI 5 "mask_operand" "i"))
4075 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4076 (match_operand:SI 1 "mask_operand" "i"))))]
4077 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4078 "*
4079 {
4080 int me = extract_ME(operands[5]);
4081 int mb = extract_MB(operands[5]);
4082 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4083 operands[2] = GEN_INT(mb);
4084 operands[1] = GEN_INT(me);
4085 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4086 }"
4087 [(set_attr "type" "insert_word")])
4089 (define_insn "insvdi"
4090 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4091 (match_operand:SI 1 "const_int_operand" "i")
4092 (match_operand:SI 2 "const_int_operand" "i"))
4093 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4094 "TARGET_POWERPC64"
4095 "*
4096 {
4097 int start = INTVAL (operands[2]) & 63;
4098 int size = INTVAL (operands[1]) & 63;
4100 operands[1] = GEN_INT (64 - start - size);
4101 return \"rldimi %0,%3,%H1,%H2\";
4102 }"
4103 [(set_attr "type" "insert_dword")])
4105 (define_insn "*insvdi_internal2"
4106 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4107 (match_operand:SI 1 "const_int_operand" "i")
4108 (match_operand:SI 2 "const_int_operand" "i"))
4109 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4110 (match_operand:SI 4 "const_int_operand" "i")))]
4111 "TARGET_POWERPC64
4112 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4113 "*
4114 {
4115 int shift = INTVAL (operands[4]) & 63;
4116 int start = (INTVAL (operands[2]) & 63) - 32;
4117 int size = INTVAL (operands[1]) & 63;
4119 operands[4] = GEN_INT (64 - shift - start - size);
4120 operands[2] = GEN_INT (start);
4121 operands[1] = GEN_INT (start + size - 1);
4122 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4123 }")
4125 (define_insn "*insvdi_internal3"
4126 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4127 (match_operand:SI 1 "const_int_operand" "i")
4128 (match_operand:SI 2 "const_int_operand" "i"))
4129 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4130 (match_operand:SI 4 "const_int_operand" "i")))]
4131 "TARGET_POWERPC64
4132 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4133 "*
4134 {
4135 int shift = INTVAL (operands[4]) & 63;
4136 int start = (INTVAL (operands[2]) & 63) - 32;
4137 int size = INTVAL (operands[1]) & 63;
4139 operands[4] = GEN_INT (64 - shift - start - size);
4140 operands[2] = GEN_INT (start);
4141 operands[1] = GEN_INT (start + size - 1);
4142 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4143 }")
4145 (define_expand "extzv"
4146 [(set (match_operand 0 "gpc_reg_operand" "")
4147 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4148 (match_operand:SI 2 "const_int_operand" "")
4149 (match_operand:SI 3 "const_int_operand" "")))]
4150 ""
4151 "
4152 {
4153 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4154 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4155 compiler if the address of the structure is taken later. */
4156 if (GET_CODE (operands[0]) == SUBREG
4157 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4158 FAIL;
4160 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4161 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4162 else
4163 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4164 DONE;
4165 }")
4167 (define_insn "extzvsi"
4168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4169 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4170 (match_operand:SI 2 "const_int_operand" "i")
4171 (match_operand:SI 3 "const_int_operand" "i")))]
4172 ""
4173 "*
4174 {
4175 int start = INTVAL (operands[3]) & 31;
4176 int size = INTVAL (operands[2]) & 31;
4178 if (start + size >= 32)
4179 operands[3] = const0_rtx;
4180 else
4181 operands[3] = GEN_INT (start + size);
4182 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4183 }")
4185 (define_insn "*extzvsi_internal1"
4186 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4187 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4188 (match_operand:SI 2 "const_int_operand" "i,i")
4189 (match_operand:SI 3 "const_int_operand" "i,i"))
4190 (const_int 0)))
4191 (clobber (match_scratch:SI 4 "=r,r"))]
4192 ""
4193 "*
4194 {
4195 int start = INTVAL (operands[3]) & 31;
4196 int size = INTVAL (operands[2]) & 31;
4198 /* Force split for non-cc0 compare. */
4199 if (which_alternative == 1)
4200 return \"#\";
4202 /* If the bit-field being tested fits in the upper or lower half of a
4203 word, it is possible to use andiu. or andil. to test it. This is
4204 useful because the condition register set-use delay is smaller for
4205 andi[ul]. than for rlinm. This doesn't work when the starting bit
4206 position is 0 because the LT and GT bits may be set wrong. */
4208 if ((start > 0 && start + size <= 16) || start >= 16)
4209 {
4210 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4211 - (1 << (16 - (start & 15) - size))));
4212 if (start < 16)
4213 return \"{andiu.|andis.} %4,%1,%3\";
4214 else
4215 return \"{andil.|andi.} %4,%1,%3\";
4216 }
4218 if (start + size >= 32)
4219 operands[3] = const0_rtx;
4220 else
4221 operands[3] = GEN_INT (start + size);
4222 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4223 }"
4224 [(set_attr "type" "delayed_compare")
4225 (set_attr "length" "4,8")])
4227 (define_split
4228 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4229 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4230 (match_operand:SI 2 "const_int_operand" "")
4231 (match_operand:SI 3 "const_int_operand" ""))
4232 (const_int 0)))
4233 (clobber (match_scratch:SI 4 ""))]
4234 "reload_completed"
4235 [(set (match_dup 4)
4236 (zero_extract:SI (match_dup 1) (match_dup 2)
4237 (match_dup 3)))
4238 (set (match_dup 0)
4239 (compare:CC (match_dup 4)
4240 (const_int 0)))]
4241 "")
4243 (define_insn "*extzvsi_internal2"
4244 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4245 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4246 (match_operand:SI 2 "const_int_operand" "i,i")
4247 (match_operand:SI 3 "const_int_operand" "i,i"))
4248 (const_int 0)))
4249 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4250 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4251 ""
4252 "*
4253 {
4254 int start = INTVAL (operands[3]) & 31;
4255 int size = INTVAL (operands[2]) & 31;
4257 /* Force split for non-cc0 compare. */
4258 if (which_alternative == 1)
4259 return \"#\";
4261 /* Since we are using the output value, we can't ignore any need for
4262 a shift. The bit-field must end at the LSB. */
4263 if (start >= 16 && start + size == 32)
4264 {
4265 operands[3] = GEN_INT ((1 << size) - 1);
4266 return \"{andil.|andi.} %0,%1,%3\";
4267 }
4269 if (start + size >= 32)
4270 operands[3] = const0_rtx;
4271 else
4272 operands[3] = GEN_INT (start + size);
4273 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4274 }"
4275 [(set_attr "type" "delayed_compare")
4276 (set_attr "length" "4,8")])
4278 (define_split
4279 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4280 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4281 (match_operand:SI 2 "const_int_operand" "")
4282 (match_operand:SI 3 "const_int_operand" ""))
4283 (const_int 0)))
4284 (set (match_operand:SI 0 "gpc_reg_operand" "")
4285 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4286 "reload_completed"
4287 [(set (match_dup 0)
4288 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4289 (set (match_dup 4)
4290 (compare:CC (match_dup 0)
4291 (const_int 0)))]
4292 "")
4294 (define_insn "extzvdi"
4295 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4296 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4297 (match_operand:SI 2 "const_int_operand" "i")
4298 (match_operand:SI 3 "const_int_operand" "i")))]
4299 "TARGET_POWERPC64"
4300 "*
4301 {
4302 int start = INTVAL (operands[3]) & 63;
4303 int size = INTVAL (operands[2]) & 63;
4305 if (start + size >= 64)
4306 operands[3] = const0_rtx;
4307 else
4308 operands[3] = GEN_INT (start + size);
4309 operands[2] = GEN_INT (64 - size);
4310 return \"rldicl %0,%1,%3,%2\";
4311 }")
4313 (define_insn "*extzvdi_internal1"
4314 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4315 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4316 (match_operand:SI 2 "const_int_operand" "i")
4317 (match_operand:SI 3 "const_int_operand" "i"))
4318 (const_int 0)))
4319 (clobber (match_scratch:DI 4 "=r"))]
4320 "TARGET_64BIT && rs6000_gen_cell_microcode"
4321 "*
4322 {
4323 int start = INTVAL (operands[3]) & 63;
4324 int size = INTVAL (operands[2]) & 63;
4326 if (start + size >= 64)
4327 operands[3] = const0_rtx;
4328 else
4329 operands[3] = GEN_INT (start + size);
4330 operands[2] = GEN_INT (64 - size);
4331 return \"rldicl. %4,%1,%3,%2\";
4332 }"
4333 [(set_attr "type" "compare")])
4335 (define_insn "*extzvdi_internal2"
4336 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4337 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4338 (match_operand:SI 2 "const_int_operand" "i")
4339 (match_operand:SI 3 "const_int_operand" "i"))
4340 (const_int 0)))
4341 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4342 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4343 "TARGET_64BIT && rs6000_gen_cell_microcode"
4344 "*
4345 {
4346 int start = INTVAL (operands[3]) & 63;
4347 int size = INTVAL (operands[2]) & 63;
4349 if (start + size >= 64)
4350 operands[3] = const0_rtx;
4351 else
4352 operands[3] = GEN_INT (start + size);
4353 operands[2] = GEN_INT (64 - size);
4354 return \"rldicl. %0,%1,%3,%2\";
4355 }"
4356 [(set_attr "type" "compare")])
4358 (define_insn "rotlsi3"
4359 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4360 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4361 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4362 ""
4363 "@
4364 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4365 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4366 [(set_attr "type" "var_shift_rotate,integer")])
4368 (define_insn "*rotlsi3_internal2"
4369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4370 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4371 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4372 (const_int 0)))
4373 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4374 ""
4375 "@
4376 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4377 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4378 #
4379 #"
4380 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4381 (set_attr "length" "4,4,8,8")])
4383 (define_split
4384 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4385 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4386 (match_operand:SI 2 "reg_or_cint_operand" ""))
4387 (const_int 0)))
4388 (clobber (match_scratch:SI 3 ""))]
4389 "reload_completed"
4390 [(set (match_dup 3)
4391 (rotate:SI (match_dup 1) (match_dup 2)))
4392 (set (match_dup 0)
4393 (compare:CC (match_dup 3)
4394 (const_int 0)))]
4395 "")
4397 (define_insn "*rotlsi3_internal3"
4398 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4399 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4400 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4401 (const_int 0)))
4402 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4403 (rotate:SI (match_dup 1) (match_dup 2)))]
4404 ""
4405 "@
4406 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4407 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4408 #
4409 #"
4410 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4411 (set_attr "length" "4,4,8,8")])
4413 (define_split
4414 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4415 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4416 (match_operand:SI 2 "reg_or_cint_operand" ""))
4417 (const_int 0)))
4418 (set (match_operand:SI 0 "gpc_reg_operand" "")
4419 (rotate:SI (match_dup 1) (match_dup 2)))]
4420 "reload_completed"
4421 [(set (match_dup 0)
4422 (rotate:SI (match_dup 1) (match_dup 2)))
4423 (set (match_dup 3)
4424 (compare:CC (match_dup 0)
4425 (const_int 0)))]
4426 "")
4428 (define_insn "*rotlsi3_internal4"
4429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4430 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4431 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4432 (match_operand:SI 3 "mask_operand" "n,n")))]
4433 ""
4434 "@
4435 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4436 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4437 [(set_attr "type" "var_shift_rotate,integer")])
4439 (define_insn "*rotlsi3_internal5"
4440 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4441 (compare:CC (and:SI
4442 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4443 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4444 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4445 (const_int 0)))
4446 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4447 ""
4448 "@
4449 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4450 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4451 #
4452 #"
4453 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4454 (set_attr "length" "4,4,8,8")])
4456 (define_split
4457 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4458 (compare:CC (and:SI
4459 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4460 (match_operand:SI 2 "reg_or_cint_operand" ""))
4461 (match_operand:SI 3 "mask_operand" ""))
4462 (const_int 0)))
4463 (clobber (match_scratch:SI 4 ""))]
4464 "reload_completed"
4465 [(set (match_dup 4)
4466 (and:SI (rotate:SI (match_dup 1)
4467 (match_dup 2))
4468 (match_dup 3)))
4469 (set (match_dup 0)
4470 (compare:CC (match_dup 4)
4471 (const_int 0)))]
4472 "")
4474 (define_insn "*rotlsi3_internal6"
4475 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4476 (compare:CC (and:SI
4477 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4478 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4479 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4480 (const_int 0)))
4481 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4482 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4483 ""
4484 "@
4485 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4486 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4487 #
4488 #"
4489 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4490 (set_attr "length" "4,4,8,8")])
4492 (define_split
4493 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4494 (compare:CC (and:SI
4495 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4496 (match_operand:SI 2 "reg_or_cint_operand" ""))
4497 (match_operand:SI 3 "mask_operand" ""))
4498 (const_int 0)))
4499 (set (match_operand:SI 0 "gpc_reg_operand" "")
4500 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4501 "reload_completed"
4502 [(set (match_dup 0)
4503 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4504 (set (match_dup 4)
4505 (compare:CC (match_dup 0)
4506 (const_int 0)))]
4507 "")
4509 (define_insn "*rotlsi3_internal7"
4510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4511 (zero_extend:SI
4512 (subreg:QI
4513 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4514 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4515 ""
4516 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4517 [(set (attr "cell_micro")
4518 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4519 (const_string "not")
4520 (const_string "always")))])
4522 (define_insn "*rotlsi3_internal8"
4523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4524 (compare:CC (zero_extend:SI
4525 (subreg:QI
4526 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4527 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4528 (const_int 0)))
4529 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4530 ""
4531 "@
4532 {rlnm.|rlwnm.} %3,%1,%2,0xff
4533 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4534 #
4535 #"
4536 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4537 (set_attr "length" "4,4,8,8")])
4539 (define_split
4540 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4541 (compare:CC (zero_extend:SI
4542 (subreg:QI
4543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4544 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4545 (const_int 0)))
4546 (clobber (match_scratch:SI 3 ""))]
4547 "reload_completed"
4548 [(set (match_dup 3)
4549 (zero_extend:SI (subreg:QI
4550 (rotate:SI (match_dup 1)
4551 (match_dup 2)) 0)))
4552 (set (match_dup 0)
4553 (compare:CC (match_dup 3)
4554 (const_int 0)))]
4555 "")
4557 (define_insn "*rotlsi3_internal9"
4558 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4559 (compare:CC (zero_extend:SI
4560 (subreg:QI
4561 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4562 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4563 (const_int 0)))
4564 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4565 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4566 ""
4567 "@
4568 {rlnm.|rlwnm.} %0,%1,%2,0xff
4569 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4570 #
4571 #"
4572 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4573 (set_attr "length" "4,4,8,8")])
4575 (define_split
4576 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4577 (compare:CC (zero_extend:SI
4578 (subreg:QI
4579 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4580 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4581 (const_int 0)))
4582 (set (match_operand:SI 0 "gpc_reg_operand" "")
4583 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4584 "reload_completed"
4585 [(set (match_dup 0)
4586 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4587 (set (match_dup 3)
4588 (compare:CC (match_dup 0)
4589 (const_int 0)))]
4590 "")
4592 (define_insn "*rotlsi3_internal10"
4593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4594 (zero_extend:SI
4595 (subreg:HI
4596 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4597 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4598 ""
4599 "@
4600 {rlnm|rlwnm} %0,%1,%2,0xffff
4601 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4602 [(set_attr "type" "var_shift_rotate,integer")])
4605 (define_insn "*rotlsi3_internal11"
4606 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4607 (compare:CC (zero_extend:SI
4608 (subreg:HI
4609 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4610 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4611 (const_int 0)))
4612 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4613 ""
4614 "@
4615 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4616 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4617 #
4618 #"
4619 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4620 (set_attr "length" "4,4,8,8")])
4622 (define_split
4623 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4624 (compare:CC (zero_extend:SI
4625 (subreg:HI
4626 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4627 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4628 (const_int 0)))
4629 (clobber (match_scratch:SI 3 ""))]
4630 "reload_completed"
4631 [(set (match_dup 3)
4632 (zero_extend:SI (subreg:HI
4633 (rotate:SI (match_dup 1)
4634 (match_dup 2)) 0)))
4635 (set (match_dup 0)
4636 (compare:CC (match_dup 3)
4637 (const_int 0)))]
4638 "")
4640 (define_insn "*rotlsi3_internal12"
4641 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4642 (compare:CC (zero_extend:SI
4643 (subreg:HI
4644 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4645 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4646 (const_int 0)))
4647 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4648 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4649 ""
4650 "@
4651 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4652 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4653 #
4654 #"
4655 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4656 (set_attr "length" "4,4,8,8")])
4658 (define_split
4659 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4660 (compare:CC (zero_extend:SI
4661 (subreg:HI
4662 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4663 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4664 (const_int 0)))
4665 (set (match_operand:SI 0 "gpc_reg_operand" "")
4666 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4667 "reload_completed"
4668 [(set (match_dup 0)
4669 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4670 (set (match_dup 3)
4671 (compare:CC (match_dup 0)
4672 (const_int 0)))]
4673 "")
4675 ;; Note that we use "sle." instead of "sl." so that we can set
4676 ;; SHIFT_COUNT_TRUNCATED.
4678 (define_expand "ashlsi3"
4679 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4680 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4681 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4682 ""
4683 "
4684 {
4685 if (TARGET_POWER)
4686 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4687 else
4688 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4689 DONE;
4690 }")
4692 (define_insn "ashlsi3_power"
4693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4694 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4695 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4696 (clobber (match_scratch:SI 3 "=q,X"))]
4697 "TARGET_POWER"
4698 "@
4699 sle %0,%1,%2
4700 {sli|slwi} %0,%1,%h2")
4702 (define_insn "ashlsi3_no_power"
4703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4704 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4705 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4706 "! TARGET_POWER"
4707 "@
4708 {sl|slw} %0,%1,%2
4709 {sli|slwi} %0,%1,%h2"
4710 [(set_attr "type" "var_shift_rotate,shift")])
4712 (define_insn ""
4713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4714 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4715 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4716 (const_int 0)))
4717 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4718 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4719 "TARGET_POWER"
4720 "@
4721 sle. %3,%1,%2
4722 {sli.|slwi.} %3,%1,%h2
4723 #
4724 #"
4725 [(set_attr "type" "delayed_compare")
4726 (set_attr "length" "4,4,8,8")])
4728 (define_split
4729 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4730 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4731 (match_operand:SI 2 "reg_or_cint_operand" ""))
4732 (const_int 0)))
4733 (clobber (match_scratch:SI 3 ""))
4734 (clobber (match_scratch:SI 4 ""))]
4735 "TARGET_POWER && reload_completed"
4736 [(parallel [(set (match_dup 3)
4737 (ashift:SI (match_dup 1) (match_dup 2)))
4738 (clobber (match_dup 4))])
4739 (set (match_dup 0)
4740 (compare:CC (match_dup 3)
4741 (const_int 0)))]
4742 "")
4744 (define_insn ""
4745 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4746 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4747 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4748 (const_int 0)))
4749 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4750 "! TARGET_POWER && TARGET_32BIT"
4751 "@
4752 {sl.|slw.} %3,%1,%2
4753 {sli.|slwi.} %3,%1,%h2
4754 #
4755 #"
4756 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4757 (set_attr "length" "4,4,8,8")])
4759 (define_split
4760 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4761 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4762 (match_operand:SI 2 "reg_or_cint_operand" ""))
4763 (const_int 0)))
4764 (clobber (match_scratch:SI 3 ""))]
4765 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4766 [(set (match_dup 3)
4767 (ashift:SI (match_dup 1) (match_dup 2)))
4768 (set (match_dup 0)
4769 (compare:CC (match_dup 3)
4770 (const_int 0)))]
4771 "")
4773 (define_insn ""
4774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4775 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4776 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4777 (const_int 0)))
4778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4779 (ashift:SI (match_dup 1) (match_dup 2)))
4780 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4781 "TARGET_POWER"
4782 "@
4783 sle. %0,%1,%2
4784 {sli.|slwi.} %0,%1,%h2
4785 #
4786 #"
4787 [(set_attr "type" "delayed_compare")
4788 (set_attr "length" "4,4,8,8")])
4790 (define_split
4791 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4792 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4793 (match_operand:SI 2 "reg_or_cint_operand" ""))
4794 (const_int 0)))
4795 (set (match_operand:SI 0 "gpc_reg_operand" "")
4796 (ashift:SI (match_dup 1) (match_dup 2)))
4797 (clobber (match_scratch:SI 4 ""))]
4798 "TARGET_POWER && reload_completed"
4799 [(parallel [(set (match_dup 0)
4800 (ashift:SI (match_dup 1) (match_dup 2)))
4801 (clobber (match_dup 4))])
4802 (set (match_dup 3)
4803 (compare:CC (match_dup 0)
4804 (const_int 0)))]
4805 "")
4807 (define_insn ""
4808 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4809 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4810 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4811 (const_int 0)))
4812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4813 (ashift:SI (match_dup 1) (match_dup 2)))]
4814 "! TARGET_POWER && TARGET_32BIT"
4815 "@
4816 {sl.|slw.} %0,%1,%2
4817 {sli.|slwi.} %0,%1,%h2
4818 #
4819 #"
4820 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4821 (set_attr "length" "4,4,8,8")])
4823 (define_split
4824 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4825 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4826 (match_operand:SI 2 "reg_or_cint_operand" ""))
4827 (const_int 0)))
4828 (set (match_operand:SI 0 "gpc_reg_operand" "")
4829 (ashift:SI (match_dup 1) (match_dup 2)))]
4830 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4831 [(set (match_dup 0)
4832 (ashift:SI (match_dup 1) (match_dup 2)))
4833 (set (match_dup 3)
4834 (compare:CC (match_dup 0)
4835 (const_int 0)))]
4836 "")
4838 (define_insn "rlwinm"
4839 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4840 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4841 (match_operand:SI 2 "const_int_operand" "i"))
4842 (match_operand:SI 3 "mask_operand" "n")))]
4843 "includes_lshift_p (operands[2], operands[3])"
4844 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4846 (define_insn ""
4847 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4848 (compare:CC
4849 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4850 (match_operand:SI 2 "const_int_operand" "i,i"))
4851 (match_operand:SI 3 "mask_operand" "n,n"))
4852 (const_int 0)))
4853 (clobber (match_scratch:SI 4 "=r,r"))]
4854 "includes_lshift_p (operands[2], operands[3])"
4855 "@
4856 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4857 #"
4858 [(set_attr "type" "delayed_compare")
4859 (set_attr "length" "4,8")])
4861 (define_split
4862 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4863 (compare:CC
4864 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4865 (match_operand:SI 2 "const_int_operand" ""))
4866 (match_operand:SI 3 "mask_operand" ""))
4867 (const_int 0)))
4868 (clobber (match_scratch:SI 4 ""))]
4869 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4870 [(set (match_dup 4)
4871 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4872 (match_dup 3)))
4873 (set (match_dup 0)
4874 (compare:CC (match_dup 4)
4875 (const_int 0)))]
4876 "")
4878 (define_insn ""
4879 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4880 (compare:CC
4881 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4882 (match_operand:SI 2 "const_int_operand" "i,i"))
4883 (match_operand:SI 3 "mask_operand" "n,n"))
4884 (const_int 0)))
4885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4886 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4887 "includes_lshift_p (operands[2], operands[3])"
4888 "@
4889 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4890 #"
4891 [(set_attr "type" "delayed_compare")
4892 (set_attr "length" "4,8")])
4894 (define_split
4895 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4896 (compare:CC
4897 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4898 (match_operand:SI 2 "const_int_operand" ""))
4899 (match_operand:SI 3 "mask_operand" ""))
4900 (const_int 0)))
4901 (set (match_operand:SI 0 "gpc_reg_operand" "")
4902 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4903 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4904 [(set (match_dup 0)
4905 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4906 (set (match_dup 4)
4907 (compare:CC (match_dup 0)
4908 (const_int 0)))]
4909 "")
4911 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4912 ;; "sli x,x,0".
4913 (define_expand "lshrsi3"
4914 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4915 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4916 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4917 ""
4918 "
4919 {
4920 if (TARGET_POWER)
4921 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4922 else
4923 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4924 DONE;
4925 }")
4927 (define_insn "lshrsi3_power"
4928 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4929 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4930 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4931 (clobber (match_scratch:SI 3 "=q,X,X"))]
4932 "TARGET_POWER"
4933 "@
4934 sre %0,%1,%2
4935 mr %0,%1
4936 {s%A2i|s%A2wi} %0,%1,%h2")
4938 (define_insn "lshrsi3_no_power"
4939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4940 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4941 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4942 "! TARGET_POWER"
4943 "@
4944 mr %0,%1
4945 {sr|srw} %0,%1,%2
4946 {sri|srwi} %0,%1,%h2"
4947 [(set_attr "type" "integer,var_shift_rotate,shift")])
4949 (define_insn ""
4950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4951 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4952 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4953 (const_int 0)))
4954 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4955 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4956 "TARGET_POWER"
4957 "@
4958 sre. %3,%1,%2
4959 mr. %1,%1
4960 {s%A2i.|s%A2wi.} %3,%1,%h2
4961 #
4962 #
4963 #"
4964 [(set_attr "type" "delayed_compare")
4965 (set_attr "length" "4,4,4,8,8,8")])
4967 (define_split
4968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4969 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" ""))
4971 (const_int 0)))
4972 (clobber (match_scratch:SI 3 ""))
4973 (clobber (match_scratch:SI 4 ""))]
4974 "TARGET_POWER && reload_completed"
4975 [(parallel [(set (match_dup 3)
4976 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4977 (clobber (match_dup 4))])
4978 (set (match_dup 0)
4979 (compare:CC (match_dup 3)
4980 (const_int 0)))]
4981 "")
4983 (define_insn ""
4984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4985 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4986 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4987 (const_int 0)))
4988 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4989 "! TARGET_POWER && TARGET_32BIT"
4990 "@
4991 mr. %1,%1
4992 {sr.|srw.} %3,%1,%2
4993 {sri.|srwi.} %3,%1,%h2
4994 #
4995 #
4996 #"
4997 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4998 (set_attr "length" "4,4,4,8,8,8")])
5000 (define_split
5001 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5002 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5003 (match_operand:SI 2 "reg_or_cint_operand" ""))
5004 (const_int 0)))
5005 (clobber (match_scratch:SI 3 ""))]
5006 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5007 [(set (match_dup 3)
5008 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5009 (set (match_dup 0)
5010 (compare:CC (match_dup 3)
5011 (const_int 0)))]
5012 "")
5014 (define_insn ""
5015 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5016 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5017 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5018 (const_int 0)))
5019 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5020 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5021 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5022 "TARGET_POWER"
5023 "@
5024 sre. %0,%1,%2
5025 mr. %0,%1
5026 {s%A2i.|s%A2wi.} %0,%1,%h2
5027 #
5028 #
5029 #"
5030 [(set_attr "type" "delayed_compare")
5031 (set_attr "length" "4,4,4,8,8,8")])
5033 (define_split
5034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5035 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5036 (match_operand:SI 2 "reg_or_cint_operand" ""))
5037 (const_int 0)))
5038 (set (match_operand:SI 0 "gpc_reg_operand" "")
5039 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5040 (clobber (match_scratch:SI 4 ""))]
5041 "TARGET_POWER && reload_completed"
5042 [(parallel [(set (match_dup 0)
5043 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5044 (clobber (match_dup 4))])
5045 (set (match_dup 3)
5046 (compare:CC (match_dup 0)
5047 (const_int 0)))]
5048 "")
5050 (define_insn ""
5051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5052 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5053 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5054 (const_int 0)))
5055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5056 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5057 "! TARGET_POWER && TARGET_32BIT"
5058 "@
5059 mr. %0,%1
5060 {sr.|srw.} %0,%1,%2
5061 {sri.|srwi.} %0,%1,%h2
5062 #
5063 #
5064 #"
5065 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5066 (set_attr "length" "4,4,4,8,8,8")])
5068 (define_split
5069 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5070 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5071 (match_operand:SI 2 "reg_or_cint_operand" ""))
5072 (const_int 0)))
5073 (set (match_operand:SI 0 "gpc_reg_operand" "")
5074 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5075 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5076 [(set (match_dup 0)
5077 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5078 (set (match_dup 3)
5079 (compare:CC (match_dup 0)
5080 (const_int 0)))]
5081 "")
5083 (define_insn ""
5084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5085 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5086 (match_operand:SI 2 "const_int_operand" "i"))
5087 (match_operand:SI 3 "mask_operand" "n")))]
5088 "includes_rshift_p (operands[2], operands[3])"
5089 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5091 (define_insn ""
5092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5093 (compare:CC
5094 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5095 (match_operand:SI 2 "const_int_operand" "i,i"))
5096 (match_operand:SI 3 "mask_operand" "n,n"))
5097 (const_int 0)))
5098 (clobber (match_scratch:SI 4 "=r,r"))]
5099 "includes_rshift_p (operands[2], operands[3])"
5100 "@
5101 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5102 #"
5103 [(set_attr "type" "delayed_compare")
5104 (set_attr "length" "4,8")])
5106 (define_split
5107 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5108 (compare:CC
5109 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5110 (match_operand:SI 2 "const_int_operand" ""))
5111 (match_operand:SI 3 "mask_operand" ""))
5112 (const_int 0)))
5113 (clobber (match_scratch:SI 4 ""))]
5114 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5115 [(set (match_dup 4)
5116 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5117 (match_dup 3)))
5118 (set (match_dup 0)
5119 (compare:CC (match_dup 4)
5120 (const_int 0)))]
5121 "")
5123 (define_insn ""
5124 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5125 (compare:CC
5126 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5127 (match_operand:SI 2 "const_int_operand" "i,i"))
5128 (match_operand:SI 3 "mask_operand" "n,n"))
5129 (const_int 0)))
5130 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5131 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5132 "includes_rshift_p (operands[2], operands[3])"
5133 "@
5134 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5135 #"
5136 [(set_attr "type" "delayed_compare")
5137 (set_attr "length" "4,8")])
5139 (define_split
5140 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5141 (compare:CC
5142 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5143 (match_operand:SI 2 "const_int_operand" ""))
5144 (match_operand:SI 3 "mask_operand" ""))
5145 (const_int 0)))
5146 (set (match_operand:SI 0 "gpc_reg_operand" "")
5147 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5148 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5149 [(set (match_dup 0)
5150 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5151 (set (match_dup 4)
5152 (compare:CC (match_dup 0)
5153 (const_int 0)))]
5154 "")
5156 (define_insn ""
5157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5158 (zero_extend:SI
5159 (subreg:QI
5160 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5161 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5162 "includes_rshift_p (operands[2], GEN_INT (255))"
5163 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5165 (define_insn ""
5166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5167 (compare:CC
5168 (zero_extend:SI
5169 (subreg:QI
5170 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5171 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5172 (const_int 0)))
5173 (clobber (match_scratch:SI 3 "=r,r"))]
5174 "includes_rshift_p (operands[2], GEN_INT (255))"
5175 "@
5176 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5177 #"
5178 [(set_attr "type" "delayed_compare")
5179 (set_attr "length" "4,8")])
5181 (define_split
5182 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5183 (compare:CC
5184 (zero_extend:SI
5185 (subreg:QI
5186 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5187 (match_operand:SI 2 "const_int_operand" "")) 0))
5188 (const_int 0)))
5189 (clobber (match_scratch:SI 3 ""))]
5190 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5191 [(set (match_dup 3)
5192 (zero_extend:SI (subreg:QI
5193 (lshiftrt:SI (match_dup 1)
5194 (match_dup 2)) 0)))
5195 (set (match_dup 0)
5196 (compare:CC (match_dup 3)
5197 (const_int 0)))]
5198 "")
5200 (define_insn ""
5201 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5202 (compare:CC
5203 (zero_extend:SI
5204 (subreg:QI
5205 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5206 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5207 (const_int 0)))
5208 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5209 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5210 "includes_rshift_p (operands[2], GEN_INT (255))"
5211 "@
5212 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5213 #"
5214 [(set_attr "type" "delayed_compare")
5215 (set_attr "length" "4,8")])
5217 (define_split
5218 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5219 (compare:CC
5220 (zero_extend:SI
5221 (subreg:QI
5222 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5223 (match_operand:SI 2 "const_int_operand" "")) 0))
5224 (const_int 0)))
5225 (set (match_operand:SI 0 "gpc_reg_operand" "")
5226 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5227 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5228 [(set (match_dup 0)
5229 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5230 (set (match_dup 3)
5231 (compare:CC (match_dup 0)
5232 (const_int 0)))]
5233 "")
5235 (define_insn ""
5236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5237 (zero_extend:SI
5238 (subreg:HI
5239 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5240 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5241 "includes_rshift_p (operands[2], GEN_INT (65535))"
5242 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5244 (define_insn ""
5245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5246 (compare:CC
5247 (zero_extend:SI
5248 (subreg:HI
5249 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5250 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5251 (const_int 0)))
5252 (clobber (match_scratch:SI 3 "=r,r"))]
5253 "includes_rshift_p (operands[2], GEN_INT (65535))"
5254 "@
5255 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5256 #"
5257 [(set_attr "type" "delayed_compare")
5258 (set_attr "length" "4,8")])
5260 (define_split
5261 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5262 (compare:CC
5263 (zero_extend:SI
5264 (subreg:HI
5265 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5266 (match_operand:SI 2 "const_int_operand" "")) 0))
5267 (const_int 0)))
5268 (clobber (match_scratch:SI 3 ""))]
5269 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5270 [(set (match_dup 3)
5271 (zero_extend:SI (subreg:HI
5272 (lshiftrt:SI (match_dup 1)
5273 (match_dup 2)) 0)))
5274 (set (match_dup 0)
5275 (compare:CC (match_dup 3)
5276 (const_int 0)))]
5277 "")
5279 (define_insn ""
5280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5281 (compare:CC
5282 (zero_extend:SI
5283 (subreg:HI
5284 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5285 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5286 (const_int 0)))
5287 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5288 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5289 "includes_rshift_p (operands[2], GEN_INT (65535))"
5290 "@
5291 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5292 #"
5293 [(set_attr "type" "delayed_compare")
5294 (set_attr "length" "4,8")])
5296 (define_split
5297 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5298 (compare:CC
5299 (zero_extend:SI
5300 (subreg:HI
5301 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5302 (match_operand:SI 2 "const_int_operand" "")) 0))
5303 (const_int 0)))
5304 (set (match_operand:SI 0 "gpc_reg_operand" "")
5305 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5306 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5307 [(set (match_dup 0)
5308 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5309 (set (match_dup 3)
5310 (compare:CC (match_dup 0)
5311 (const_int 0)))]
5312 "")
5314 (define_insn ""
5315 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5316 (const_int 1)
5317 (match_operand:SI 1 "gpc_reg_operand" "r"))
5318 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5319 (const_int 31)))]
5320 "TARGET_POWER"
5321 "rrib %0,%1,%2")
5323 (define_insn ""
5324 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5325 (const_int 1)
5326 (match_operand:SI 1 "gpc_reg_operand" "r"))
5327 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5328 (const_int 31)))]
5329 "TARGET_POWER"
5330 "rrib %0,%1,%2")
5332 (define_insn ""
5333 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5334 (const_int 1)
5335 (match_operand:SI 1 "gpc_reg_operand" "r"))
5336 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5337 (const_int 1)
5338 (const_int 0)))]
5339 "TARGET_POWER"
5340 "rrib %0,%1,%2")
5342 (define_expand "ashrsi3"
5343 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5344 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5345 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5346 ""
5347 "
5348 {
5349 if (TARGET_POWER)
5350 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5351 else
5352 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5353 DONE;
5354 }")
5356 (define_insn "ashrsi3_power"
5357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5358 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5359 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5360 (clobber (match_scratch:SI 3 "=q,X"))]
5361 "TARGET_POWER"
5362 "@
5363 srea %0,%1,%2
5364 {srai|srawi} %0,%1,%h2"
5365 [(set_attr "type" "shift")])
5367 (define_insn "ashrsi3_no_power"
5368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5369 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5370 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5371 "! TARGET_POWER"
5372 "@
5373 {sra|sraw} %0,%1,%2
5374 {srai|srawi} %0,%1,%h2"
5375 [(set_attr "type" "var_shift_rotate,shift")])
5377 (define_insn ""
5378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5379 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5380 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5381 (const_int 0)))
5382 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5383 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5384 "TARGET_POWER"
5385 "@
5386 srea. %3,%1,%2
5387 {srai.|srawi.} %3,%1,%h2
5388 #
5389 #"
5390 [(set_attr "type" "delayed_compare")
5391 (set_attr "length" "4,4,8,8")])
5393 (define_split
5394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5395 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5396 (match_operand:SI 2 "reg_or_cint_operand" ""))
5397 (const_int 0)))
5398 (clobber (match_scratch:SI 3 ""))
5399 (clobber (match_scratch:SI 4 ""))]
5400 "TARGET_POWER && reload_completed"
5401 [(parallel [(set (match_dup 3)
5402 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5403 (clobber (match_dup 4))])
5404 (set (match_dup 0)
5405 (compare:CC (match_dup 3)
5406 (const_int 0)))]
5407 "")
5409 (define_insn ""
5410 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5411 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5412 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5413 (const_int 0)))
5414 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5415 "! TARGET_POWER"
5416 "@
5417 {sra.|sraw.} %3,%1,%2
5418 {srai.|srawi.} %3,%1,%h2
5419 #
5420 #"
5421 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5422 (set_attr "length" "4,4,8,8")])
5424 (define_split
5425 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5426 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5427 (match_operand:SI 2 "reg_or_cint_operand" ""))
5428 (const_int 0)))
5429 (clobber (match_scratch:SI 3 ""))]
5430 "! TARGET_POWER && reload_completed"
5431 [(set (match_dup 3)
5432 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5433 (set (match_dup 0)
5434 (compare:CC (match_dup 3)
5435 (const_int 0)))]
5436 "")
5438 (define_insn ""
5439 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5440 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5441 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5442 (const_int 0)))
5443 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5444 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5445 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5446 "TARGET_POWER"
5447 "@
5448 srea. %0,%1,%2
5449 {srai.|srawi.} %0,%1,%h2
5450 #
5451 #"
5452 [(set_attr "type" "delayed_compare")
5453 (set_attr "length" "4,4,8,8")])
5455 (define_split
5456 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5457 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5458 (match_operand:SI 2 "reg_or_cint_operand" ""))
5459 (const_int 0)))
5460 (set (match_operand:SI 0 "gpc_reg_operand" "")
5461 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5462 (clobber (match_scratch:SI 4 ""))]
5463 "TARGET_POWER && reload_completed"
5464 [(parallel [(set (match_dup 0)
5465 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5466 (clobber (match_dup 4))])
5467 (set (match_dup 3)
5468 (compare:CC (match_dup 0)
5469 (const_int 0)))]
5470 "")
5472 (define_insn ""
5473 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5474 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5475 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5476 (const_int 0)))
5477 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5478 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5479 "! TARGET_POWER"
5480 "@
5481 {sra.|sraw.} %0,%1,%2
5482 {srai.|srawi.} %0,%1,%h2
5483 #
5484 #"
5485 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5486 (set_attr "length" "4,4,8,8")])
5487 \f
5488 (define_split
5489 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5490 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5491 (match_operand:SI 2 "reg_or_cint_operand" ""))
5492 (const_int 0)))
5493 (set (match_operand:SI 0 "gpc_reg_operand" "")
5494 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5495 "! TARGET_POWER && reload_completed"
5496 [(set (match_dup 0)
5497 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5498 (set (match_dup 3)
5499 (compare:CC (match_dup 0)
5500 (const_int 0)))]
5501 "")
5503 ;; Floating-point insns, excluding normal data motion.
5504 ;;
5505 ;; PowerPC has a full set of single-precision floating point instructions.
5506 ;;
5507 ;; For the POWER architecture, we pretend that we have both SFmode and
5508 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5509 ;; The only conversions we will do will be when storing to memory. In that
5510 ;; case, we will use the "frsp" instruction before storing.
5511 ;;
5512 ;; Note that when we store into a single-precision memory location, we need to
5513 ;; use the frsp insn first. If the register being stored isn't dead, we
5514 ;; need a scratch register for the frsp. But this is difficult when the store
5515 ;; is done by reload. It is not incorrect to do the frsp on the register in
5516 ;; this case, we just lose precision that we would have otherwise gotten but
5517 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5519 (define_expand "extendsfdf2"
5520 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5521 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5522 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5523 "")
5525 (define_insn_and_split "*extendsfdf2_fpr"
5526 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5527 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5528 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5529 "@
5530 #
5531 fmr %0,%1
5532 lfs%U1%X1 %0,%1"
5533 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5534 [(const_int 0)]
5535 {
5536 emit_note (NOTE_INSN_DELETED);
5537 DONE;
5538 }
5539 [(set_attr "type" "fp,fp,fpload")])
5541 (define_expand "truncdfsf2"
5542 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5543 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5544 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5545 "")
5547 (define_insn "*truncdfsf2_fpr"
5548 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5549 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5550 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5551 "frsp %0,%1"
5552 [(set_attr "type" "fp")])
5554 (define_insn "aux_truncdfsf2"
5555 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5556 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5557 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5558 "frsp %0,%1"
5559 [(set_attr "type" "fp")])
5561 (define_expand "negsf2"
5562 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5563 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5564 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5565 "")
5567 (define_insn "*negsf2"
5568 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5569 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5570 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5571 "fneg %0,%1"
5572 [(set_attr "type" "fp")])
5574 (define_expand "abssf2"
5575 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5576 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5577 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5578 "")
5580 (define_insn "*abssf2"
5581 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5582 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5583 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5584 "fabs %0,%1"
5585 [(set_attr "type" "fp")])
5587 (define_insn ""
5588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5589 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5590 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5591 "fnabs %0,%1"
5592 [(set_attr "type" "fp")])
5594 (define_expand "addsf3"
5595 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5596 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5597 (match_operand:SF 2 "gpc_reg_operand" "")))]
5598 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5599 "")
5601 (define_insn ""
5602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5603 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5604 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5605 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5606 "fadds %0,%1,%2"
5607 [(set_attr "type" "fp")
5608 (set_attr "fp_type" "fp_addsub_s")])
5610 (define_insn ""
5611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5612 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5613 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5614 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5615 "{fa|fadd} %0,%1,%2"
5616 [(set_attr "type" "fp")])
5618 (define_expand "subsf3"
5619 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5620 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5621 (match_operand:SF 2 "gpc_reg_operand" "")))]
5622 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5623 "")
5625 (define_insn ""
5626 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5627 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5628 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5629 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5630 "fsubs %0,%1,%2"
5631 [(set_attr "type" "fp")
5632 (set_attr "fp_type" "fp_addsub_s")])
5634 (define_insn ""
5635 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5636 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5637 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5638 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5639 "{fs|fsub} %0,%1,%2"
5640 [(set_attr "type" "fp")])
5642 (define_expand "mulsf3"
5643 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5644 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5645 (match_operand:SF 2 "gpc_reg_operand" "")))]
5646 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5647 "")
5649 (define_insn ""
5650 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5651 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5652 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5653 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5654 "fmuls %0,%1,%2"
5655 [(set_attr "type" "fp")
5656 (set_attr "fp_type" "fp_mul_s")])
5658 (define_insn ""
5659 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5660 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5661 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5662 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5663 "{fm|fmul} %0,%1,%2"
5664 [(set_attr "type" "dmul")])
5666 (define_expand "divsf3"
5667 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5668 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5669 (match_operand:SF 2 "gpc_reg_operand" "")))]
5670 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5671 "")
5673 (define_insn ""
5674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5675 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5676 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5677 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5678 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5679 "fdivs %0,%1,%2"
5680 [(set_attr "type" "sdiv")])
5682 (define_insn ""
5683 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5684 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5685 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5686 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5687 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5688 "{fd|fdiv} %0,%1,%2"
5689 [(set_attr "type" "ddiv")])
5691 (define_expand "recipsf3"
5692 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5693 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5694 (match_operand:SF 2 "gpc_reg_operand" "f")]
5695 UNSPEC_FRES))]
5696 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5697 && flag_finite_math_only && !flag_trapping_math"
5698 {
5699 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5700 DONE;
5701 })
5703 (define_insn "fres"
5704 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5705 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5706 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5707 "fres %0,%1"
5708 [(set_attr "type" "fp")])
5710 (define_insn "*fmaddsf4_powerpc"
5711 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5712 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5713 (match_operand:SF 2 "gpc_reg_operand" "f"))
5714 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5715 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5716 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5717 "fmadds %0,%1,%2,%3"
5718 [(set_attr "type" "fp")
5719 (set_attr "fp_type" "fp_maddsub_s")])
5721 (define_insn "*fmaddsf4_power"
5722 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5723 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5724 (match_operand:SF 2 "gpc_reg_operand" "f"))
5725 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5726 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5727 "{fma|fmadd} %0,%1,%2,%3"
5728 [(set_attr "type" "dmul")])
5730 (define_insn "*fmsubsf4_powerpc"
5731 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5732 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5733 (match_operand:SF 2 "gpc_reg_operand" "f"))
5734 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5735 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5736 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5737 "fmsubs %0,%1,%2,%3"
5738 [(set_attr "type" "fp")
5739 (set_attr "fp_type" "fp_maddsub_s")])
5741 (define_insn "*fmsubsf4_power"
5742 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5743 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5744 (match_operand:SF 2 "gpc_reg_operand" "f"))
5745 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5746 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5747 "{fms|fmsub} %0,%1,%2,%3"
5748 [(set_attr "type" "dmul")])
5750 (define_insn "*fnmaddsf4_powerpc_1"
5751 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5752 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5753 (match_operand:SF 2 "gpc_reg_operand" "f"))
5754 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5755 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5756 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5757 "fnmadds %0,%1,%2,%3"
5758 [(set_attr "type" "fp")
5759 (set_attr "fp_type" "fp_maddsub_s")])
5761 (define_insn "*fnmaddsf4_powerpc_2"
5762 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5763 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5764 (match_operand:SF 2 "gpc_reg_operand" "f"))
5765 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5766 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5767 && ! HONOR_SIGNED_ZEROS (SFmode)"
5768 "fnmadds %0,%1,%2,%3"
5769 [(set_attr "type" "fp")
5770 (set_attr "fp_type" "fp_maddsub_s")])
5772 (define_insn "*fnmaddsf4_power_1"
5773 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5774 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5775 (match_operand:SF 2 "gpc_reg_operand" "f"))
5776 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5777 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5778 "{fnma|fnmadd} %0,%1,%2,%3"
5779 [(set_attr "type" "dmul")])
5781 (define_insn "*fnmaddsf4_power_2"
5782 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5783 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5784 (match_operand:SF 2 "gpc_reg_operand" "f"))
5785 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5786 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5787 && ! HONOR_SIGNED_ZEROS (SFmode)"
5788 "{fnma|fnmadd} %0,%1,%2,%3"
5789 [(set_attr "type" "dmul")])
5791 (define_insn "*fnmsubsf4_powerpc_1"
5792 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5793 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5794 (match_operand:SF 2 "gpc_reg_operand" "f"))
5795 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5796 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5797 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5798 "fnmsubs %0,%1,%2,%3"
5799 [(set_attr "type" "fp")
5800 (set_attr "fp_type" "fp_maddsub_s")])
5802 (define_insn "*fnmsubsf4_powerpc_2"
5803 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5804 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5805 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5806 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5807 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5808 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5809 "fnmsubs %0,%1,%2,%3"
5810 [(set_attr "type" "fp")
5811 (set_attr "fp_type" "fp_maddsub_s")])
5813 (define_insn "*fnmsubsf4_power_1"
5814 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5815 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5816 (match_operand:SF 2 "gpc_reg_operand" "f"))
5817 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5818 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5819 "{fnms|fnmsub} %0,%1,%2,%3"
5820 [(set_attr "type" "dmul")])
5822 (define_insn "*fnmsubsf4_power_2"
5823 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5824 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5825 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5826 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5827 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5828 && ! HONOR_SIGNED_ZEROS (SFmode)"
5829 "{fnms|fnmsub} %0,%1,%2,%3"
5830 [(set_attr "type" "dmul")])
5832 (define_expand "sqrtsf2"
5833 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5834 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5835 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5836 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5837 && !TARGET_SIMPLE_FPU"
5838 "")
5840 (define_insn ""
5841 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5842 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5843 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5844 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5845 "fsqrts %0,%1"
5846 [(set_attr "type" "ssqrt")])
5848 (define_insn ""
5849 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5850 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5851 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5852 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5853 "fsqrt %0,%1"
5854 [(set_attr "type" "dsqrt")])
5856 (define_expand "rsqrtsf2"
5857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5858 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5859 UNSPEC_RSQRT))]
5860 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5861 && flag_finite_math_only && !flag_trapping_math"
5862 {
5863 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5864 DONE;
5865 })
5867 (define_insn "*rsqrt_internal1"
5868 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5869 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5870 UNSPEC_RSQRT))]
5871 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5872 "frsqrte %0,%1"
5873 [(set_attr "type" "fp")])
5875 (define_expand "copysignsf3"
5876 [(set (match_dup 3)
5877 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5878 (set (match_dup 4)
5879 (neg:SF (abs:SF (match_dup 1))))
5880 (set (match_operand:SF 0 "gpc_reg_operand" "")
5881 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5882 (match_dup 5))
5883 (match_dup 3)
5884 (match_dup 4)))]
5885 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5886 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5887 {
5888 operands[3] = gen_reg_rtx (SFmode);
5889 operands[4] = gen_reg_rtx (SFmode);
5890 operands[5] = CONST0_RTX (SFmode);
5891 })
5893 (define_expand "copysigndf3"
5894 [(set (match_dup 3)
5895 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5896 (set (match_dup 4)
5897 (neg:DF (abs:DF (match_dup 1))))
5898 (set (match_operand:DF 0 "gpc_reg_operand" "")
5899 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5900 (match_dup 5))
5901 (match_dup 3)
5902 (match_dup 4)))]
5903 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5904 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5905 {
5906 operands[3] = gen_reg_rtx (DFmode);
5907 operands[4] = gen_reg_rtx (DFmode);
5908 operands[5] = CONST0_RTX (DFmode);
5909 })
5911 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5912 ;; fsel instruction and some auxiliary computations. Then we just have a
5913 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5914 ;; combine.
5915 (define_expand "smaxsf3"
5916 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5917 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5918 (match_operand:SF 2 "gpc_reg_operand" ""))
5919 (match_dup 1)
5920 (match_dup 2)))]
5921 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5922 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5923 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5925 (define_expand "sminsf3"
5926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5927 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5928 (match_operand:SF 2 "gpc_reg_operand" ""))
5929 (match_dup 2)
5930 (match_dup 1)))]
5931 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5932 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5933 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5935 (define_split
5936 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5937 (match_operator:SF 3 "min_max_operator"
5938 [(match_operand:SF 1 "gpc_reg_operand" "")
5939 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5940 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5941 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5942 [(const_int 0)]
5943 "
5944 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5945 operands[1], operands[2]);
5946 DONE;
5947 }")
5949 (define_expand "mov<mode>cc"
5950 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5951 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5952 (match_operand:GPR 2 "gpc_reg_operand" "")
5953 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5954 "TARGET_ISEL<sel>"
5955 "
5956 {
5957 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5958 DONE;
5959 else
5960 FAIL;
5961 }")
5963 ;; We use the BASE_REGS for the isel input operands because, if rA is
5964 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5965 ;; because we may switch the operands and rB may end up being rA.
5966 ;;
5967 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5968 ;; leave out the mode in operand 4 and use one pattern, but reload can
5969 ;; change the mode underneath our feet and then gets confused trying
5970 ;; to reload the value.
5971 (define_insn "isel_signed_<mode>"
5972 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5973 (if_then_else:GPR
5974 (match_operator 1 "comparison_operator"
5975 [(match_operand:CC 4 "cc_reg_operand" "y")
5976 (const_int 0)])
5977 (match_operand:GPR 2 "gpc_reg_operand" "b")
5978 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5979 "TARGET_ISEL<sel>"
5980 "*
5981 { return output_isel (operands); }"
5982 [(set_attr "length" "4")])
5984 (define_insn "isel_unsigned_<mode>"
5985 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5986 (if_then_else:GPR
5987 (match_operator 1 "comparison_operator"
5988 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5989 (const_int 0)])
5990 (match_operand:GPR 2 "gpc_reg_operand" "b")
5991 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5992 "TARGET_ISEL<sel>"
5993 "*
5994 { return output_isel (operands); }"
5995 [(set_attr "length" "4")])
5997 (define_expand "movsfcc"
5998 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5999 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6000 (match_operand:SF 2 "gpc_reg_operand" "")
6001 (match_operand:SF 3 "gpc_reg_operand" "")))]
6002 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6003 "
6004 {
6005 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6006 DONE;
6007 else
6008 FAIL;
6009 }")
6011 (define_insn "*fselsfsf4"
6012 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6013 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6014 (match_operand:SF 4 "zero_fp_constant" "F"))
6015 (match_operand:SF 2 "gpc_reg_operand" "f")
6016 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6017 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6018 "fsel %0,%1,%2,%3"
6019 [(set_attr "type" "fp")])
6021 (define_insn "*fseldfsf4"
6022 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6023 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6024 (match_operand:DF 4 "zero_fp_constant" "F"))
6025 (match_operand:SF 2 "gpc_reg_operand" "f")
6026 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6027 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6028 "fsel %0,%1,%2,%3"
6029 [(set_attr "type" "fp")])
6031 (define_expand "negdf2"
6032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6033 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6034 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6035 "")
6037 (define_insn "*negdf2_fpr"
6038 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6039 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6040 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6041 "fneg %0,%1"
6042 [(set_attr "type" "fp")])
6044 (define_expand "absdf2"
6045 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6046 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6047 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6048 "")
6050 (define_insn "*absdf2_fpr"
6051 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6052 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6053 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6054 "fabs %0,%1"
6055 [(set_attr "type" "fp")])
6057 (define_insn "*nabsdf2_fpr"
6058 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6059 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6060 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6061 "fnabs %0,%1"
6062 [(set_attr "type" "fp")])
6064 (define_expand "adddf3"
6065 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6066 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6067 (match_operand:DF 2 "gpc_reg_operand" "")))]
6068 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6069 "")
6071 (define_insn "*adddf3_fpr"
6072 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6073 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6074 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6075 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6076 "{fa|fadd} %0,%1,%2"
6077 [(set_attr "type" "fp")
6078 (set_attr "fp_type" "fp_addsub_d")])
6080 (define_expand "subdf3"
6081 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6082 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6083 (match_operand:DF 2 "gpc_reg_operand" "")))]
6084 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6085 "")
6087 (define_insn "*subdf3_fpr"
6088 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6089 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6090 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6091 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6092 "{fs|fsub} %0,%1,%2"
6093 [(set_attr "type" "fp")
6094 (set_attr "fp_type" "fp_addsub_d")])
6096 (define_expand "muldf3"
6097 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6098 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6099 (match_operand:DF 2 "gpc_reg_operand" "")))]
6100 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6101 "")
6103 (define_insn "*muldf3_fpr"
6104 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6105 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6106 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6107 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6108 "{fm|fmul} %0,%1,%2"
6109 [(set_attr "type" "dmul")
6110 (set_attr "fp_type" "fp_mul_d")])
6112 (define_expand "divdf3"
6113 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6114 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6115 (match_operand:DF 2 "gpc_reg_operand" "")))]
6116 "TARGET_HARD_FLOAT
6117 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6118 && !TARGET_SIMPLE_FPU"
6119 "")
6121 (define_insn "*divdf3_fpr"
6122 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6123 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6124 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6125 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
6126 "{fd|fdiv} %0,%1,%2"
6127 [(set_attr "type" "ddiv")])
6129 (define_expand "recipdf3"
6130 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6131 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
6132 (match_operand:DF 2 "gpc_reg_operand" "d")]
6133 UNSPEC_FRES))]
6134 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
6135 && flag_finite_math_only && !flag_trapping_math"
6136 {
6137 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
6138 DONE;
6139 })
6141 (define_insn "fred"
6142 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6143 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6144 "TARGET_POPCNTB && flag_finite_math_only"
6145 "fre %0,%1"
6146 [(set_attr "type" "fp")])
6148 (define_insn ""
6149 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6150 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6151 (match_operand:DF 2 "gpc_reg_operand" "d"))
6152 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6153 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
6154 "{fma|fmadd} %0,%1,%2,%3"
6155 [(set_attr "type" "dmul")
6156 (set_attr "fp_type" "fp_maddsub_d")])
6158 (define_insn ""
6159 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6160 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6161 (match_operand:DF 2 "gpc_reg_operand" "d"))
6162 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6163 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
6164 "{fms|fmsub} %0,%1,%2,%3"
6165 [(set_attr "type" "dmul")
6166 (set_attr "fp_type" "fp_maddsub_d")])
6168 (define_insn ""
6169 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6170 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6171 (match_operand:DF 2 "gpc_reg_operand" "d"))
6172 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6173 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6174 && HONOR_SIGNED_ZEROS (DFmode)"
6175 "{fnma|fnmadd} %0,%1,%2,%3"
6176 [(set_attr "type" "dmul")
6177 (set_attr "fp_type" "fp_maddsub_d")])
6179 (define_insn ""
6180 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6181 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6182 (match_operand:DF 2 "gpc_reg_operand" "d"))
6183 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6184 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6185 && ! HONOR_SIGNED_ZEROS (DFmode)"
6186 "{fnma|fnmadd} %0,%1,%2,%3"
6187 [(set_attr "type" "dmul")
6188 (set_attr "fp_type" "fp_maddsub_d")])
6190 (define_insn ""
6191 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6192 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6193 (match_operand:DF 2 "gpc_reg_operand" "d"))
6194 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6195 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6196 && HONOR_SIGNED_ZEROS (DFmode)"
6197 "{fnms|fnmsub} %0,%1,%2,%3"
6198 [(set_attr "type" "dmul")
6199 (set_attr "fp_type" "fp_maddsub_d")])
6201 (define_insn ""
6202 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6203 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6204 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6205 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6206 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6207 && ! HONOR_SIGNED_ZEROS (DFmode)"
6208 "{fnms|fnmsub} %0,%1,%2,%3"
6209 [(set_attr "type" "dmul")
6210 (set_attr "fp_type" "fp_maddsub_d")])
6212 (define_insn "sqrtdf2"
6213 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6214 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6215 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6216 && TARGET_DOUBLE_FLOAT"
6217 "fsqrt %0,%1"
6218 [(set_attr "type" "dsqrt")])
6220 ;; The conditional move instructions allow us to perform max and min
6221 ;; operations even when
6223 (define_expand "smaxdf3"
6224 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6225 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6226 (match_operand:DF 2 "gpc_reg_operand" ""))
6227 (match_dup 1)
6228 (match_dup 2)))]
6229 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6230 && !flag_trapping_math"
6231 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6233 (define_expand "smindf3"
6234 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6235 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6236 (match_operand:DF 2 "gpc_reg_operand" ""))
6237 (match_dup 2)
6238 (match_dup 1)))]
6239 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6240 && !flag_trapping_math"
6241 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6243 (define_split
6244 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6245 (match_operator:DF 3 "min_max_operator"
6246 [(match_operand:DF 1 "gpc_reg_operand" "")
6247 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6248 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6249 && !flag_trapping_math"
6250 [(const_int 0)]
6251 "
6252 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6253 operands[1], operands[2]);
6254 DONE;
6255 }")
6257 (define_expand "movdfcc"
6258 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6259 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6260 (match_operand:DF 2 "gpc_reg_operand" "")
6261 (match_operand:DF 3 "gpc_reg_operand" "")))]
6262 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6263 "
6264 {
6265 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6266 DONE;
6267 else
6268 FAIL;
6269 }")
6271 (define_insn "*fseldfdf4"
6272 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6273 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6274 (match_operand:DF 4 "zero_fp_constant" "F"))
6275 (match_operand:DF 2 "gpc_reg_operand" "d")
6276 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6277 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6278 "fsel %0,%1,%2,%3"
6279 [(set_attr "type" "fp")])
6281 (define_insn "*fselsfdf4"
6282 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6283 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6284 (match_operand:SF 4 "zero_fp_constant" "F"))
6285 (match_operand:DF 2 "gpc_reg_operand" "d")
6286 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6287 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6288 "fsel %0,%1,%2,%3"
6289 [(set_attr "type" "fp")])
6290 \f
6291 ;; Conversions to and from floating-point.
6293 (define_expand "fixuns_truncsfsi2"
6294 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6295 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6296 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6297 "")
6299 (define_expand "fix_truncsfsi2"
6300 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6301 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6302 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6303 "")
6305 (define_expand "fixuns_truncdfsi2"
6306 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6307 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6308 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6309 "")
6311 ; For each of these conversions, there is a define_expand, a define_insn
6312 ; with a '#' template, and a define_split (with C code). The idea is
6313 ; to allow constant folding with the template of the define_insn,
6314 ; then to have the insns split later (between sched1 and final).
6316 (define_expand "floatsidf2"
6317 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6318 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6319 (use (match_dup 2))
6320 (use (match_dup 3))
6321 (clobber (match_dup 4))
6322 (clobber (match_dup 5))
6323 (clobber (match_dup 6))])]
6324 "TARGET_HARD_FLOAT
6325 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6326 "
6327 {
6328 if (TARGET_E500_DOUBLE)
6329 {
6330 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6331 DONE;
6332 }
6333 if (TARGET_POWERPC64)
6334 {
6335 rtx x = convert_to_mode (DImode, operands[1], 0);
6336 emit_insn (gen_floatdidf2 (operands[0], x));
6337 DONE;
6338 }
6340 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6341 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6342 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6343 operands[5] = gen_reg_rtx (DFmode);
6344 operands[6] = gen_reg_rtx (SImode);
6345 }")
6347 (define_insn_and_split "*floatsidf2_internal"
6348 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6349 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6350 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6351 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6352 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6353 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6354 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6355 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6356 "#"
6357 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
6358 [(pc)]
6359 "
6360 {
6361 rtx lowword, highword;
6362 gcc_assert (MEM_P (operands[4]));
6363 highword = adjust_address (operands[4], SImode, 0);
6364 lowword = adjust_address (operands[4], SImode, 4);
6365 if (! WORDS_BIG_ENDIAN)
6366 {
6367 rtx tmp;
6368 tmp = highword; highword = lowword; lowword = tmp;
6369 }
6371 emit_insn (gen_xorsi3 (operands[6], operands[1],
6372 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6373 emit_move_insn (lowword, operands[6]);
6374 emit_move_insn (highword, operands[2]);
6375 emit_move_insn (operands[5], operands[4]);
6376 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6377 DONE;
6378 }"
6379 [(set_attr "length" "24")])
6381 (define_expand "floatunssisf2"
6382 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6383 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6384 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6385 "")
6387 (define_expand "floatunssidf2"
6388 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6389 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6390 (use (match_dup 2))
6391 (use (match_dup 3))
6392 (clobber (match_dup 4))
6393 (clobber (match_dup 5))])]
6394 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6395 "
6396 {
6397 if (TARGET_E500_DOUBLE)
6398 {
6399 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6400 DONE;
6401 }
6402 if (TARGET_POWERPC64)
6403 {
6404 rtx x = convert_to_mode (DImode, operands[1], 1);
6405 emit_insn (gen_floatdidf2 (operands[0], x));
6406 DONE;
6407 }
6409 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6410 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6411 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6412 operands[5] = gen_reg_rtx (DFmode);
6413 }")
6415 (define_insn_and_split "*floatunssidf2_internal"
6416 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6417 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6418 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6419 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6420 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6421 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6422 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6423 "#"
6424 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
6425 [(pc)]
6426 "
6427 {
6428 rtx lowword, highword;
6429 gcc_assert (MEM_P (operands[4]));
6430 highword = adjust_address (operands[4], SImode, 0);
6431 lowword = adjust_address (operands[4], SImode, 4);
6432 if (! WORDS_BIG_ENDIAN)
6433 {
6434 rtx tmp;
6435 tmp = highword; highword = lowword; lowword = tmp;
6436 }
6438 emit_move_insn (lowword, operands[1]);
6439 emit_move_insn (highword, operands[2]);
6440 emit_move_insn (operands[5], operands[4]);
6441 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6442 DONE;
6443 }"
6444 [(set_attr "length" "20")])
6446 (define_expand "fix_truncdfsi2"
6447 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6448 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6449 (clobber (match_dup 2))
6450 (clobber (match_dup 3))])]
6451 "(TARGET_POWER2 || TARGET_POWERPC)
6452 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6453 "
6454 {
6455 if (TARGET_E500_DOUBLE)
6456 {
6457 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6458 DONE;
6459 }
6460 operands[2] = gen_reg_rtx (DImode);
6461 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6462 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6463 {
6464 operands[3] = gen_reg_rtx (DImode);
6465 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6466 operands[2], operands[3]));
6467 DONE;
6468 }
6469 if (TARGET_PPC_GFXOPT)
6470 {
6471 rtx orig_dest = operands[0];
6472 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6473 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6474 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6475 operands[2]));
6476 if (operands[0] != orig_dest)
6477 emit_move_insn (orig_dest, operands[0]);
6478 DONE;
6479 }
6480 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6481 }")
6483 (define_insn_and_split "*fix_truncdfsi2_internal"
6484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6485 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6486 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6487 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6488 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6489 && TARGET_DOUBLE_FLOAT"
6490 "#"
6491 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6492 [(pc)]
6493 "
6494 {
6495 rtx lowword;
6496 gcc_assert (MEM_P (operands[3]));
6497 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6499 emit_insn (gen_fctiwz (operands[2], operands[1]));
6500 emit_move_insn (operands[3], operands[2]);
6501 emit_move_insn (operands[0], lowword);
6502 DONE;
6503 }"
6504 [(set_attr "length" "16")])
6506 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6507 [(set (match_operand:SI 0 "memory_operand" "=Z")
6508 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6509 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6510 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6511 && TARGET_DOUBLE_FLOAT
6512 && TARGET_PPC_GFXOPT"
6513 "#"
6514 "&& 1"
6515 [(pc)]
6516 "
6517 {
6518 emit_insn (gen_fctiwz (operands[2], operands[1]));
6519 emit_insn (gen_stfiwx (operands[0], operands[2]));
6520 DONE;
6521 }"
6522 [(set_attr "length" "16")])
6524 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6526 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6527 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6528 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6529 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6530 && TARGET_DOUBLE_FLOAT"
6531 "#"
6532 "&& 1"
6533 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6534 (set (match_dup 3) (match_dup 2))
6535 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6536 ""
6537 [(set_attr "length" "12")])
6539 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6540 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6541 ; because the first makes it clear that operand 0 is not live
6542 ; before the instruction.
6543 (define_insn "fctiwz"
6544 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6545 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6546 UNSPEC_FCTIWZ))]
6547 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6548 && TARGET_DOUBLE_FLOAT"
6549 "{fcirz|fctiwz} %0,%1"
6550 [(set_attr "type" "fp")])
6552 (define_insn "btruncdf2"
6553 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6554 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6555 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6556 "friz %0,%1"
6557 [(set_attr "type" "fp")])
6559 (define_insn "btruncsf2"
6560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6561 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6562 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6563 "friz %0,%1"
6564 [(set_attr "type" "fp")])
6566 (define_insn "ceildf2"
6567 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6568 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6569 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6570 "frip %0,%1"
6571 [(set_attr "type" "fp")])
6573 (define_insn "ceilsf2"
6574 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6575 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6576 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6577 "frip %0,%1"
6578 [(set_attr "type" "fp")])
6580 (define_insn "floordf2"
6581 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6582 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6583 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6584 "frim %0,%1"
6585 [(set_attr "type" "fp")])
6587 (define_insn "floorsf2"
6588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6589 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6590 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6591 "frim %0,%1"
6592 [(set_attr "type" "fp")])
6594 (define_insn "rounddf2"
6595 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6596 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6597 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6598 "frin %0,%1"
6599 [(set_attr "type" "fp")])
6601 (define_insn "roundsf2"
6602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6603 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6604 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6605 "frin %0,%1"
6606 [(set_attr "type" "fp")])
6608 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6609 (define_insn "stfiwx"
6610 [(set (match_operand:SI 0 "memory_operand" "=Z")
6611 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6612 UNSPEC_STFIWX))]
6613 "TARGET_PPC_GFXOPT"
6614 "stfiwx %1,%y0"
6615 [(set_attr "type" "fpstore")])
6617 (define_expand "floatsisf2"
6618 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6619 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6620 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6621 "")
6623 (define_insn "floatdidf2"
6624 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6625 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6626 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6627 "fcfid %0,%1"
6628 [(set_attr "type" "fp")])
6630 (define_insn "fix_truncdfdi2"
6631 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6632 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6633 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6634 "fctidz %0,%1"
6635 [(set_attr "type" "fp")])
6637 (define_expand "floatdisf2"
6638 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6639 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6640 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6641 "
6642 {
6643 rtx val = operands[1];
6644 if (!flag_unsafe_math_optimizations)
6645 {
6646 rtx label = gen_label_rtx ();
6647 val = gen_reg_rtx (DImode);
6648 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6649 emit_label (label);
6650 }
6651 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6652 DONE;
6653 }")
6655 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6656 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6657 ;; from double rounding.
6658 (define_insn_and_split "floatdisf2_internal1"
6659 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6660 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6661 (clobber (match_scratch:DF 2 "=d"))]
6662 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6663 "#"
6664 "&& reload_completed"
6665 [(set (match_dup 2)
6666 (float:DF (match_dup 1)))
6667 (set (match_dup 0)
6668 (float_truncate:SF (match_dup 2)))]
6669 "")
6671 ;; Twiddles bits to avoid double rounding.
6672 ;; Bits that might be truncated when converting to DFmode are replaced
6673 ;; by a bit that won't be lost at that stage, but is below the SFmode
6674 ;; rounding position.
6675 (define_expand "floatdisf2_internal2"
6676 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6677 (const_int 53)))
6678 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6679 (const_int 2047)))
6680 (clobber (scratch:CC))])
6681 (set (match_dup 3) (plus:DI (match_dup 3)
6682 (const_int 1)))
6683 (set (match_dup 0) (plus:DI (match_dup 0)
6684 (const_int 2047)))
6685 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6686 (const_int 2)))
6687 (set (match_dup 0) (ior:DI (match_dup 0)
6688 (match_dup 1)))
6689 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6690 (const_int -2048)))
6691 (clobber (scratch:CC))])
6692 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6693 (label_ref (match_operand:DI 2 "" ""))
6694 (pc)))
6695 (set (match_dup 0) (match_dup 1))]
6696 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6697 "
6698 {
6699 operands[3] = gen_reg_rtx (DImode);
6700 operands[4] = gen_reg_rtx (CCUNSmode);
6701 }")
6702 \f
6703 ;; Define the DImode operations that can be done in a small number
6704 ;; of instructions. The & constraints are to prevent the register
6705 ;; allocator from allocating registers that overlap with the inputs
6706 ;; (for example, having an input in 7,8 and an output in 6,7). We
6707 ;; also allow for the output being the same as one of the inputs.
6709 (define_insn "*adddi3_noppc64"
6710 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6711 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6712 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6713 "! TARGET_POWERPC64"
6714 "*
6715 {
6716 if (WORDS_BIG_ENDIAN)
6717 return (GET_CODE (operands[2])) != CONST_INT
6718 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6719 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6720 else
6721 return (GET_CODE (operands[2])) != CONST_INT
6722 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6723 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6724 }"
6725 [(set_attr "type" "two")
6726 (set_attr "length" "8")])
6728 (define_insn "*subdi3_noppc64"
6729 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6730 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6731 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6732 "! TARGET_POWERPC64"
6733 "*
6734 {
6735 if (WORDS_BIG_ENDIAN)
6736 return (GET_CODE (operands[1]) != CONST_INT)
6737 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6738 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6739 else
6740 return (GET_CODE (operands[1]) != CONST_INT)
6741 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6742 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6743 }"
6744 [(set_attr "type" "two")
6745 (set_attr "length" "8")])
6747 (define_insn "*negdi2_noppc64"
6748 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6749 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6750 "! TARGET_POWERPC64"
6751 "*
6752 {
6753 return (WORDS_BIG_ENDIAN)
6754 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6755 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6756 }"
6757 [(set_attr "type" "two")
6758 (set_attr "length" "8")])
6760 (define_expand "mulsidi3"
6761 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6762 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6763 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6764 "! TARGET_POWERPC64"
6765 "
6766 {
6767 if (! TARGET_POWER && ! TARGET_POWERPC)
6768 {
6769 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6770 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6771 emit_insn (gen_mull_call ());
6772 if (WORDS_BIG_ENDIAN)
6773 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6774 else
6775 {
6776 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6777 gen_rtx_REG (SImode, 3));
6778 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6779 gen_rtx_REG (SImode, 4));
6780 }
6781 DONE;
6782 }
6783 else if (TARGET_POWER)
6784 {
6785 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6786 DONE;
6787 }
6788 }")
6790 (define_insn "mulsidi3_mq"
6791 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6792 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6793 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6794 (clobber (match_scratch:SI 3 "=q"))]
6795 "TARGET_POWER"
6796 "mul %0,%1,%2\;mfmq %L0"
6797 [(set_attr "type" "imul")
6798 (set_attr "length" "8")])
6800 (define_insn "*mulsidi3_no_mq"
6801 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6802 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6803 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6804 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6805 "*
6806 {
6807 return (WORDS_BIG_ENDIAN)
6808 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6809 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6810 }"
6811 [(set_attr "type" "imul")
6812 (set_attr "length" "8")])
6814 (define_split
6815 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6816 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6817 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6818 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6819 [(set (match_dup 3)
6820 (truncate:SI
6821 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6822 (sign_extend:DI (match_dup 2)))
6823 (const_int 32))))
6824 (set (match_dup 4)
6825 (mult:SI (match_dup 1)
6826 (match_dup 2)))]
6827 "
6828 {
6829 int endian = (WORDS_BIG_ENDIAN == 0);
6830 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6831 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6832 }")
6834 (define_expand "umulsidi3"
6835 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6836 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6837 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6838 "TARGET_POWERPC && ! TARGET_POWERPC64"
6839 "
6840 {
6841 if (TARGET_POWER)
6842 {
6843 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6844 DONE;
6845 }
6846 }")
6848 (define_insn "umulsidi3_mq"
6849 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6850 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6851 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6852 (clobber (match_scratch:SI 3 "=q"))]
6853 "TARGET_POWERPC && TARGET_POWER"
6854 "*
6855 {
6856 return (WORDS_BIG_ENDIAN)
6857 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6858 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6859 }"
6860 [(set_attr "type" "imul")
6861 (set_attr "length" "8")])
6863 (define_insn "*umulsidi3_no_mq"
6864 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6865 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6866 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6867 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6868 "*
6869 {
6870 return (WORDS_BIG_ENDIAN)
6871 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6872 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6873 }"
6874 [(set_attr "type" "imul")
6875 (set_attr "length" "8")])
6877 (define_split
6878 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6879 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6880 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6881 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6882 [(set (match_dup 3)
6883 (truncate:SI
6884 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6885 (zero_extend:DI (match_dup 2)))
6886 (const_int 32))))
6887 (set (match_dup 4)
6888 (mult:SI (match_dup 1)
6889 (match_dup 2)))]
6890 "
6891 {
6892 int endian = (WORDS_BIG_ENDIAN == 0);
6893 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6894 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6895 }")
6897 (define_expand "smulsi3_highpart"
6898 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6899 (truncate:SI
6900 (lshiftrt:DI (mult:DI (sign_extend:DI
6901 (match_operand:SI 1 "gpc_reg_operand" ""))
6902 (sign_extend:DI
6903 (match_operand:SI 2 "gpc_reg_operand" "")))
6904 (const_int 32))))]
6905 ""
6906 "
6907 {
6908 if (! TARGET_POWER && ! TARGET_POWERPC)
6909 {
6910 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6911 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6912 emit_insn (gen_mulh_call ());
6913 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6914 DONE;
6915 }
6916 else if (TARGET_POWER)
6917 {
6918 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6919 DONE;
6920 }
6921 }")
6923 (define_insn "smulsi3_highpart_mq"
6924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6925 (truncate:SI
6926 (lshiftrt:DI (mult:DI (sign_extend:DI
6927 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6928 (sign_extend:DI
6929 (match_operand:SI 2 "gpc_reg_operand" "r")))
6930 (const_int 32))))
6931 (clobber (match_scratch:SI 3 "=q"))]
6932 "TARGET_POWER"
6933 "mul %0,%1,%2"
6934 [(set_attr "type" "imul")])
6936 (define_insn "*smulsi3_highpart_no_mq"
6937 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6938 (truncate:SI
6939 (lshiftrt:DI (mult:DI (sign_extend:DI
6940 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6941 (sign_extend:DI
6942 (match_operand:SI 2 "gpc_reg_operand" "r")))
6943 (const_int 32))))]
6944 "TARGET_POWERPC && ! TARGET_POWER"
6945 "mulhw %0,%1,%2"
6946 [(set_attr "type" "imul")])
6948 (define_expand "umulsi3_highpart"
6949 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6950 (truncate:SI
6951 (lshiftrt:DI (mult:DI (zero_extend:DI
6952 (match_operand:SI 1 "gpc_reg_operand" ""))
6953 (zero_extend:DI
6954 (match_operand:SI 2 "gpc_reg_operand" "")))
6955 (const_int 32))))]
6956 "TARGET_POWERPC"
6957 "
6958 {
6959 if (TARGET_POWER)
6960 {
6961 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6962 DONE;
6963 }
6964 }")
6966 (define_insn "umulsi3_highpart_mq"
6967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6968 (truncate:SI
6969 (lshiftrt:DI (mult:DI (zero_extend:DI
6970 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6971 (zero_extend:DI
6972 (match_operand:SI 2 "gpc_reg_operand" "r")))
6973 (const_int 32))))
6974 (clobber (match_scratch:SI 3 "=q"))]
6975 "TARGET_POWERPC && TARGET_POWER"
6976 "mulhwu %0,%1,%2"
6977 [(set_attr "type" "imul")])
6979 (define_insn "*umulsi3_highpart_no_mq"
6980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6981 (truncate:SI
6982 (lshiftrt:DI (mult:DI (zero_extend:DI
6983 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6984 (zero_extend:DI
6985 (match_operand:SI 2 "gpc_reg_operand" "r")))
6986 (const_int 32))))]
6987 "TARGET_POWERPC && ! TARGET_POWER"
6988 "mulhwu %0,%1,%2"
6989 [(set_attr "type" "imul")])
6991 ;; If operands 0 and 2 are in the same register, we have a problem. But
6992 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6993 ;; why we have the strange constraints below.
6994 (define_insn "ashldi3_power"
6995 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6996 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6997 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6998 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6999 "TARGET_POWER"
7000 "@
7001 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7002 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7003 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7004 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7005 [(set_attr "length" "8")])
7007 (define_insn "lshrdi3_power"
7008 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7009 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7010 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7011 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7012 "TARGET_POWER"
7013 "@
7014 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7015 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7016 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7017 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7018 [(set_attr "length" "8")])
7020 ;; Shift by a variable amount is too complex to be worth open-coding. We
7021 ;; just handle shifts by constants.
7022 (define_insn "ashrdi3_power"
7023 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7024 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7025 (match_operand:SI 2 "const_int_operand" "M,i")))
7026 (clobber (match_scratch:SI 3 "=X,q"))]
7027 "TARGET_POWER"
7028 "@
7029 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7030 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7031 [(set_attr "type" "shift")
7032 (set_attr "length" "8")])
7034 (define_insn "ashrdi3_no_power"
7035 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7036 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7037 (match_operand:SI 2 "const_int_operand" "M,i")))]
7038 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7039 "@
7040 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7041 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7042 [(set_attr "type" "two,three")
7043 (set_attr "length" "8,12")])
7045 (define_insn "*ashrdisi3_noppc64"
7046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7047 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7048 (const_int 32)) 4))]
7049 "TARGET_32BIT && !TARGET_POWERPC64"
7050 "*
7051 {
7052 if (REGNO (operands[0]) == REGNO (operands[1]))
7053 return \"\";
7054 else
7055 return \"mr %0,%1\";
7056 }"
7057 [(set_attr "length" "4")])
7059 \f
7060 ;; PowerPC64 DImode operations.
7062 (define_insn_and_split "absdi2"
7063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7064 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7065 (clobber (match_scratch:DI 2 "=&r,&r"))]
7066 "TARGET_POWERPC64"
7067 "#"
7068 "&& reload_completed"
7069 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7070 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7071 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7072 "")
7074 (define_insn_and_split "*nabsdi2"
7075 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7076 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7077 (clobber (match_scratch:DI 2 "=&r,&r"))]
7078 "TARGET_POWERPC64"
7079 "#"
7080 "&& reload_completed"
7081 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7082 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7083 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7084 "")
7086 (define_insn "muldi3"
7087 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7088 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7089 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7090 "TARGET_POWERPC64"
7091 "@
7092 mulld %0,%1,%2
7093 mulli %0,%1,%2"
7094 [(set (attr "type")
7095 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7096 (const_string "imul3")
7097 (match_operand:SI 2 "short_cint_operand" "")
7098 (const_string "imul2")]
7099 (const_string "lmul")))])
7101 (define_insn "*muldi3_internal1"
7102 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7103 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7104 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7105 (const_int 0)))
7106 (clobber (match_scratch:DI 3 "=r,r"))]
7107 "TARGET_POWERPC64"
7108 "@
7109 mulld. %3,%1,%2
7110 #"
7111 [(set_attr "type" "lmul_compare")
7112 (set_attr "length" "4,8")])
7114 (define_split
7115 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7116 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7117 (match_operand:DI 2 "gpc_reg_operand" ""))
7118 (const_int 0)))
7119 (clobber (match_scratch:DI 3 ""))]
7120 "TARGET_POWERPC64 && reload_completed"
7121 [(set (match_dup 3)
7122 (mult:DI (match_dup 1) (match_dup 2)))
7123 (set (match_dup 0)
7124 (compare:CC (match_dup 3)
7125 (const_int 0)))]
7126 "")
7128 (define_insn "*muldi3_internal2"
7129 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7130 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7131 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7132 (const_int 0)))
7133 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7134 (mult:DI (match_dup 1) (match_dup 2)))]
7135 "TARGET_POWERPC64"
7136 "@
7137 mulld. %0,%1,%2
7138 #"
7139 [(set_attr "type" "lmul_compare")
7140 (set_attr "length" "4,8")])
7142 (define_split
7143 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7144 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7145 (match_operand:DI 2 "gpc_reg_operand" ""))
7146 (const_int 0)))
7147 (set (match_operand:DI 0 "gpc_reg_operand" "")
7148 (mult:DI (match_dup 1) (match_dup 2)))]
7149 "TARGET_POWERPC64 && reload_completed"
7150 [(set (match_dup 0)
7151 (mult:DI (match_dup 1) (match_dup 2)))
7152 (set (match_dup 3)
7153 (compare:CC (match_dup 0)
7154 (const_int 0)))]
7155 "")
7157 (define_insn "smuldi3_highpart"
7158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7159 (truncate:DI
7160 (lshiftrt:TI (mult:TI (sign_extend:TI
7161 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7162 (sign_extend:TI
7163 (match_operand:DI 2 "gpc_reg_operand" "r")))
7164 (const_int 64))))]
7165 "TARGET_POWERPC64"
7166 "mulhd %0,%1,%2"
7167 [(set_attr "type" "lmul")])
7169 (define_insn "umuldi3_highpart"
7170 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7171 (truncate:DI
7172 (lshiftrt:TI (mult:TI (zero_extend:TI
7173 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7174 (zero_extend:TI
7175 (match_operand:DI 2 "gpc_reg_operand" "r")))
7176 (const_int 64))))]
7177 "TARGET_POWERPC64"
7178 "mulhdu %0,%1,%2"
7179 [(set_attr "type" "lmul")])
7181 (define_insn "rotldi3"
7182 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7183 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7184 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7185 "TARGET_POWERPC64"
7186 "@
7187 rldcl %0,%1,%2,0
7188 rldicl %0,%1,%H2,0"
7189 [(set_attr "type" "var_shift_rotate,integer")])
7191 (define_insn "*rotldi3_internal2"
7192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7193 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7194 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7195 (const_int 0)))
7196 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7197 "TARGET_64BIT"
7198 "@
7199 rldcl. %3,%1,%2,0
7200 rldicl. %3,%1,%H2,0
7201 #
7202 #"
7203 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7204 (set_attr "length" "4,4,8,8")])
7206 (define_split
7207 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7208 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "reg_or_cint_operand" ""))
7210 (const_int 0)))
7211 (clobber (match_scratch:DI 3 ""))]
7212 "TARGET_POWERPC64 && reload_completed"
7213 [(set (match_dup 3)
7214 (rotate:DI (match_dup 1) (match_dup 2)))
7215 (set (match_dup 0)
7216 (compare:CC (match_dup 3)
7217 (const_int 0)))]
7218 "")
7220 (define_insn "*rotldi3_internal3"
7221 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7222 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7223 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7224 (const_int 0)))
7225 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7226 (rotate:DI (match_dup 1) (match_dup 2)))]
7227 "TARGET_64BIT"
7228 "@
7229 rldcl. %0,%1,%2,0
7230 rldicl. %0,%1,%H2,0
7231 #
7232 #"
7233 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7234 (set_attr "length" "4,4,8,8")])
7236 (define_split
7237 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7238 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:DI 2 "reg_or_cint_operand" ""))
7240 (const_int 0)))
7241 (set (match_operand:DI 0 "gpc_reg_operand" "")
7242 (rotate:DI (match_dup 1) (match_dup 2)))]
7243 "TARGET_POWERPC64 && reload_completed"
7244 [(set (match_dup 0)
7245 (rotate:DI (match_dup 1) (match_dup 2)))
7246 (set (match_dup 3)
7247 (compare:CC (match_dup 0)
7248 (const_int 0)))]
7249 "")
7251 (define_insn "*rotldi3_internal4"
7252 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7253 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7254 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7255 (match_operand:DI 3 "mask64_operand" "n,n")))]
7256 "TARGET_POWERPC64"
7257 "@
7258 rldc%B3 %0,%1,%2,%S3
7259 rldic%B3 %0,%1,%H2,%S3"
7260 [(set_attr "type" "var_shift_rotate,integer")])
7262 (define_insn "*rotldi3_internal5"
7263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7264 (compare:CC (and:DI
7265 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7266 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7267 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7268 (const_int 0)))
7269 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7270 "TARGET_64BIT"
7271 "@
7272 rldc%B3. %4,%1,%2,%S3
7273 rldic%B3. %4,%1,%H2,%S3
7274 #
7275 #"
7276 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7277 (set_attr "length" "4,4,8,8")])
7279 (define_split
7280 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7281 (compare:CC (and:DI
7282 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7283 (match_operand:DI 2 "reg_or_cint_operand" ""))
7284 (match_operand:DI 3 "mask64_operand" ""))
7285 (const_int 0)))
7286 (clobber (match_scratch:DI 4 ""))]
7287 "TARGET_POWERPC64 && reload_completed"
7288 [(set (match_dup 4)
7289 (and:DI (rotate:DI (match_dup 1)
7290 (match_dup 2))
7291 (match_dup 3)))
7292 (set (match_dup 0)
7293 (compare:CC (match_dup 4)
7294 (const_int 0)))]
7295 "")
7297 (define_insn "*rotldi3_internal6"
7298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7299 (compare:CC (and:DI
7300 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7301 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7302 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7303 (const_int 0)))
7304 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7305 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7306 "TARGET_64BIT"
7307 "@
7308 rldc%B3. %0,%1,%2,%S3
7309 rldic%B3. %0,%1,%H2,%S3
7310 #
7311 #"
7312 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7313 (set_attr "length" "4,4,8,8")])
7315 (define_split
7316 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7317 (compare:CC (and:DI
7318 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7319 (match_operand:DI 2 "reg_or_cint_operand" ""))
7320 (match_operand:DI 3 "mask64_operand" ""))
7321 (const_int 0)))
7322 (set (match_operand:DI 0 "gpc_reg_operand" "")
7323 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7324 "TARGET_POWERPC64 && reload_completed"
7325 [(set (match_dup 0)
7326 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7327 (set (match_dup 4)
7328 (compare:CC (match_dup 0)
7329 (const_int 0)))]
7330 "")
7332 (define_insn "*rotldi3_internal7"
7333 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7334 (zero_extend:DI
7335 (subreg:QI
7336 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7337 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7338 "TARGET_POWERPC64"
7339 "@
7340 rldcl %0,%1,%2,56
7341 rldicl %0,%1,%H2,56"
7342 [(set_attr "type" "var_shift_rotate,integer")])
7344 (define_insn "*rotldi3_internal8"
7345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7346 (compare:CC (zero_extend:DI
7347 (subreg:QI
7348 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7349 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7350 (const_int 0)))
7351 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7352 "TARGET_64BIT"
7353 "@
7354 rldcl. %3,%1,%2,56
7355 rldicl. %3,%1,%H2,56
7356 #
7357 #"
7358 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7359 (set_attr "length" "4,4,8,8")])
7361 (define_split
7362 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7363 (compare:CC (zero_extend:DI
7364 (subreg:QI
7365 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7366 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7367 (const_int 0)))
7368 (clobber (match_scratch:DI 3 ""))]
7369 "TARGET_POWERPC64 && reload_completed"
7370 [(set (match_dup 3)
7371 (zero_extend:DI (subreg:QI
7372 (rotate:DI (match_dup 1)
7373 (match_dup 2)) 0)))
7374 (set (match_dup 0)
7375 (compare:CC (match_dup 3)
7376 (const_int 0)))]
7377 "")
7379 (define_insn "*rotldi3_internal9"
7380 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7381 (compare:CC (zero_extend:DI
7382 (subreg:QI
7383 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7384 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7385 (const_int 0)))
7386 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7387 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7388 "TARGET_64BIT"
7389 "@
7390 rldcl. %0,%1,%2,56
7391 rldicl. %0,%1,%H2,56
7392 #
7393 #"
7394 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7395 (set_attr "length" "4,4,8,8")])
7397 (define_split
7398 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7399 (compare:CC (zero_extend:DI
7400 (subreg:QI
7401 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7402 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7403 (const_int 0)))
7404 (set (match_operand:DI 0 "gpc_reg_operand" "")
7405 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7406 "TARGET_POWERPC64 && reload_completed"
7407 [(set (match_dup 0)
7408 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7409 (set (match_dup 3)
7410 (compare:CC (match_dup 0)
7411 (const_int 0)))]
7412 "")
7414 (define_insn "*rotldi3_internal10"
7415 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7416 (zero_extend:DI
7417 (subreg:HI
7418 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7419 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7420 "TARGET_POWERPC64"
7421 "@
7422 rldcl %0,%1,%2,48
7423 rldicl %0,%1,%H2,48"
7424 [(set_attr "type" "var_shift_rotate,integer")])
7426 (define_insn "*rotldi3_internal11"
7427 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7428 (compare:CC (zero_extend:DI
7429 (subreg:HI
7430 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7431 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7432 (const_int 0)))
7433 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7434 "TARGET_64BIT"
7435 "@
7436 rldcl. %3,%1,%2,48
7437 rldicl. %3,%1,%H2,48
7438 #
7439 #"
7440 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7441 (set_attr "length" "4,4,8,8")])
7443 (define_split
7444 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7445 (compare:CC (zero_extend:DI
7446 (subreg:HI
7447 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7448 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7449 (const_int 0)))
7450 (clobber (match_scratch:DI 3 ""))]
7451 "TARGET_POWERPC64 && reload_completed"
7452 [(set (match_dup 3)
7453 (zero_extend:DI (subreg:HI
7454 (rotate:DI (match_dup 1)
7455 (match_dup 2)) 0)))
7456 (set (match_dup 0)
7457 (compare:CC (match_dup 3)
7458 (const_int 0)))]
7459 "")
7461 (define_insn "*rotldi3_internal12"
7462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7463 (compare:CC (zero_extend:DI
7464 (subreg:HI
7465 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7466 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7467 (const_int 0)))
7468 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7469 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7470 "TARGET_64BIT"
7471 "@
7472 rldcl. %0,%1,%2,48
7473 rldicl. %0,%1,%H2,48
7474 #
7475 #"
7476 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7477 (set_attr "length" "4,4,8,8")])
7479 (define_split
7480 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7481 (compare:CC (zero_extend:DI
7482 (subreg:HI
7483 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7484 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7485 (const_int 0)))
7486 (set (match_operand:DI 0 "gpc_reg_operand" "")
7487 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7488 "TARGET_POWERPC64 && reload_completed"
7489 [(set (match_dup 0)
7490 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7491 (set (match_dup 3)
7492 (compare:CC (match_dup 0)
7493 (const_int 0)))]
7494 "")
7496 (define_insn "*rotldi3_internal13"
7497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7498 (zero_extend:DI
7499 (subreg:SI
7500 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7501 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7502 "TARGET_POWERPC64"
7503 "@
7504 rldcl %0,%1,%2,32
7505 rldicl %0,%1,%H2,32"
7506 [(set_attr "type" "var_shift_rotate,integer")])
7508 (define_insn "*rotldi3_internal14"
7509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7510 (compare:CC (zero_extend:DI
7511 (subreg:SI
7512 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7513 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7514 (const_int 0)))
7515 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7516 "TARGET_64BIT"
7517 "@
7518 rldcl. %3,%1,%2,32
7519 rldicl. %3,%1,%H2,32
7520 #
7521 #"
7522 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7523 (set_attr "length" "4,4,8,8")])
7525 (define_split
7526 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7527 (compare:CC (zero_extend:DI
7528 (subreg:SI
7529 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7530 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7531 (const_int 0)))
7532 (clobber (match_scratch:DI 3 ""))]
7533 "TARGET_POWERPC64 && reload_completed"
7534 [(set (match_dup 3)
7535 (zero_extend:DI (subreg:SI
7536 (rotate:DI (match_dup 1)
7537 (match_dup 2)) 0)))
7538 (set (match_dup 0)
7539 (compare:CC (match_dup 3)
7540 (const_int 0)))]
7541 "")
7543 (define_insn "*rotldi3_internal15"
7544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7545 (compare:CC (zero_extend:DI
7546 (subreg:SI
7547 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7548 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7549 (const_int 0)))
7550 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7551 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7552 "TARGET_64BIT"
7553 "@
7554 rldcl. %0,%1,%2,32
7555 rldicl. %0,%1,%H2,32
7556 #
7557 #"
7558 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7559 (set_attr "length" "4,4,8,8")])
7561 (define_split
7562 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7563 (compare:CC (zero_extend:DI
7564 (subreg:SI
7565 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7566 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7567 (const_int 0)))
7568 (set (match_operand:DI 0 "gpc_reg_operand" "")
7569 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7570 "TARGET_POWERPC64 && reload_completed"
7571 [(set (match_dup 0)
7572 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7573 (set (match_dup 3)
7574 (compare:CC (match_dup 0)
7575 (const_int 0)))]
7576 "")
7578 (define_expand "ashldi3"
7579 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7580 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7581 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7582 "TARGET_POWERPC64 || TARGET_POWER"
7583 "
7584 {
7585 if (TARGET_POWERPC64)
7586 ;
7587 else if (TARGET_POWER)
7588 {
7589 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7590 DONE;
7591 }
7592 else
7593 FAIL;
7594 }")
7596 (define_insn "*ashldi3_internal1"
7597 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7598 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7599 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7600 "TARGET_POWERPC64"
7601 "@
7602 sld %0,%1,%2
7603 sldi %0,%1,%H2"
7604 [(set_attr "type" "var_shift_rotate,shift")])
7606 (define_insn "*ashldi3_internal2"
7607 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7608 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7609 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7610 (const_int 0)))
7611 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7612 "TARGET_64BIT"
7613 "@
7614 sld. %3,%1,%2
7615 sldi. %3,%1,%H2
7616 #
7617 #"
7618 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7619 (set_attr "length" "4,4,8,8")])
7621 (define_split
7622 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7623 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7624 (match_operand:SI 2 "reg_or_cint_operand" ""))
7625 (const_int 0)))
7626 (clobber (match_scratch:DI 3 ""))]
7627 "TARGET_POWERPC64 && reload_completed"
7628 [(set (match_dup 3)
7629 (ashift:DI (match_dup 1) (match_dup 2)))
7630 (set (match_dup 0)
7631 (compare:CC (match_dup 3)
7632 (const_int 0)))]
7633 "")
7635 (define_insn "*ashldi3_internal3"
7636 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7637 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7638 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7639 (const_int 0)))
7640 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7641 (ashift:DI (match_dup 1) (match_dup 2)))]
7642 "TARGET_64BIT"
7643 "@
7644 sld. %0,%1,%2
7645 sldi. %0,%1,%H2
7646 #
7647 #"
7648 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7649 (set_attr "length" "4,4,8,8")])
7651 (define_split
7652 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7653 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7654 (match_operand:SI 2 "reg_or_cint_operand" ""))
7655 (const_int 0)))
7656 (set (match_operand:DI 0 "gpc_reg_operand" "")
7657 (ashift:DI (match_dup 1) (match_dup 2)))]
7658 "TARGET_POWERPC64 && reload_completed"
7659 [(set (match_dup 0)
7660 (ashift:DI (match_dup 1) (match_dup 2)))
7661 (set (match_dup 3)
7662 (compare:CC (match_dup 0)
7663 (const_int 0)))]
7664 "")
7666 (define_insn "*ashldi3_internal4"
7667 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7668 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7669 (match_operand:SI 2 "const_int_operand" "i"))
7670 (match_operand:DI 3 "const_int_operand" "n")))]
7671 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7672 "rldic %0,%1,%H2,%W3")
7674 (define_insn "ashldi3_internal5"
7675 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7676 (compare:CC
7677 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7678 (match_operand:SI 2 "const_int_operand" "i,i"))
7679 (match_operand:DI 3 "const_int_operand" "n,n"))
7680 (const_int 0)))
7681 (clobber (match_scratch:DI 4 "=r,r"))]
7682 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7683 "@
7684 rldic. %4,%1,%H2,%W3
7685 #"
7686 [(set_attr "type" "compare")
7687 (set_attr "length" "4,8")])
7689 (define_split
7690 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7691 (compare:CC
7692 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7693 (match_operand:SI 2 "const_int_operand" ""))
7694 (match_operand:DI 3 "const_int_operand" ""))
7695 (const_int 0)))
7696 (clobber (match_scratch:DI 4 ""))]
7697 "TARGET_POWERPC64 && reload_completed
7698 && includes_rldic_lshift_p (operands[2], operands[3])"
7699 [(set (match_dup 4)
7700 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7701 (match_dup 3)))
7702 (set (match_dup 0)
7703 (compare:CC (match_dup 4)
7704 (const_int 0)))]
7705 "")
7707 (define_insn "*ashldi3_internal6"
7708 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7709 (compare:CC
7710 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7711 (match_operand:SI 2 "const_int_operand" "i,i"))
7712 (match_operand:DI 3 "const_int_operand" "n,n"))
7713 (const_int 0)))
7714 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7715 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7716 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7717 "@
7718 rldic. %0,%1,%H2,%W3
7719 #"
7720 [(set_attr "type" "compare")
7721 (set_attr "length" "4,8")])
7723 (define_split
7724 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7725 (compare:CC
7726 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7727 (match_operand:SI 2 "const_int_operand" ""))
7728 (match_operand:DI 3 "const_int_operand" ""))
7729 (const_int 0)))
7730 (set (match_operand:DI 0 "gpc_reg_operand" "")
7731 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7732 "TARGET_POWERPC64 && reload_completed
7733 && includes_rldic_lshift_p (operands[2], operands[3])"
7734 [(set (match_dup 0)
7735 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7736 (match_dup 3)))
7737 (set (match_dup 4)
7738 (compare:CC (match_dup 0)
7739 (const_int 0)))]
7740 "")
7742 (define_insn "*ashldi3_internal7"
7743 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7744 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7745 (match_operand:SI 2 "const_int_operand" "i"))
7746 (match_operand:DI 3 "mask64_operand" "n")))]
7747 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7748 "rldicr %0,%1,%H2,%S3")
7750 (define_insn "ashldi3_internal8"
7751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7752 (compare:CC
7753 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7754 (match_operand:SI 2 "const_int_operand" "i,i"))
7755 (match_operand:DI 3 "mask64_operand" "n,n"))
7756 (const_int 0)))
7757 (clobber (match_scratch:DI 4 "=r,r"))]
7758 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7759 "@
7760 rldicr. %4,%1,%H2,%S3
7761 #"
7762 [(set_attr "type" "compare")
7763 (set_attr "length" "4,8")])
7765 (define_split
7766 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7767 (compare:CC
7768 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7769 (match_operand:SI 2 "const_int_operand" ""))
7770 (match_operand:DI 3 "mask64_operand" ""))
7771 (const_int 0)))
7772 (clobber (match_scratch:DI 4 ""))]
7773 "TARGET_POWERPC64 && reload_completed
7774 && includes_rldicr_lshift_p (operands[2], operands[3])"
7775 [(set (match_dup 4)
7776 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7777 (match_dup 3)))
7778 (set (match_dup 0)
7779 (compare:CC (match_dup 4)
7780 (const_int 0)))]
7781 "")
7783 (define_insn "*ashldi3_internal9"
7784 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7785 (compare:CC
7786 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7787 (match_operand:SI 2 "const_int_operand" "i,i"))
7788 (match_operand:DI 3 "mask64_operand" "n,n"))
7789 (const_int 0)))
7790 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7791 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7792 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7793 "@
7794 rldicr. %0,%1,%H2,%S3
7795 #"
7796 [(set_attr "type" "compare")
7797 (set_attr "length" "4,8")])
7799 (define_split
7800 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7801 (compare:CC
7802 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7803 (match_operand:SI 2 "const_int_operand" ""))
7804 (match_operand:DI 3 "mask64_operand" ""))
7805 (const_int 0)))
7806 (set (match_operand:DI 0 "gpc_reg_operand" "")
7807 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7808 "TARGET_POWERPC64 && reload_completed
7809 && includes_rldicr_lshift_p (operands[2], operands[3])"
7810 [(set (match_dup 0)
7811 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7812 (match_dup 3)))
7813 (set (match_dup 4)
7814 (compare:CC (match_dup 0)
7815 (const_int 0)))]
7816 "")
7818 (define_expand "lshrdi3"
7819 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7820 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7821 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7822 "TARGET_POWERPC64 || TARGET_POWER"
7823 "
7824 {
7825 if (TARGET_POWERPC64)
7826 ;
7827 else if (TARGET_POWER)
7828 {
7829 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7830 DONE;
7831 }
7832 else
7833 FAIL;
7834 }")
7836 (define_insn "*lshrdi3_internal1"
7837 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7838 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7839 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7840 "TARGET_POWERPC64"
7841 "@
7842 srd %0,%1,%2
7843 srdi %0,%1,%H2"
7844 [(set_attr "type" "var_shift_rotate,shift")])
7846 (define_insn "*lshrdi3_internal2"
7847 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7848 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7849 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7850 (const_int 0)))
7851 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7852 "TARGET_64BIT "
7853 "@
7854 srd. %3,%1,%2
7855 srdi. %3,%1,%H2
7856 #
7857 #"
7858 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7859 (set_attr "length" "4,4,8,8")])
7861 (define_split
7862 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7863 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7864 (match_operand:SI 2 "reg_or_cint_operand" ""))
7865 (const_int 0)))
7866 (clobber (match_scratch:DI 3 ""))]
7867 "TARGET_POWERPC64 && reload_completed"
7868 [(set (match_dup 3)
7869 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7870 (set (match_dup 0)
7871 (compare:CC (match_dup 3)
7872 (const_int 0)))]
7873 "")
7875 (define_insn "*lshrdi3_internal3"
7876 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7877 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7878 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7879 (const_int 0)))
7880 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7881 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7882 "TARGET_64BIT"
7883 "@
7884 srd. %0,%1,%2
7885 srdi. %0,%1,%H2
7886 #
7887 #"
7888 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7889 (set_attr "length" "4,4,8,8")])
7891 (define_split
7892 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7893 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7894 (match_operand:SI 2 "reg_or_cint_operand" ""))
7895 (const_int 0)))
7896 (set (match_operand:DI 0 "gpc_reg_operand" "")
7897 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7898 "TARGET_POWERPC64 && reload_completed"
7899 [(set (match_dup 0)
7900 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7901 (set (match_dup 3)
7902 (compare:CC (match_dup 0)
7903 (const_int 0)))]
7904 "")
7906 (define_expand "ashrdi3"
7907 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7908 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7909 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7910 "WORDS_BIG_ENDIAN"
7911 "
7912 {
7913 if (TARGET_POWERPC64)
7914 ;
7915 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7916 {
7917 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7918 DONE;
7919 }
7920 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7921 && WORDS_BIG_ENDIAN)
7922 {
7923 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7924 DONE;
7925 }
7926 else
7927 FAIL;
7928 }")
7930 (define_insn "*ashrdi3_internal1"
7931 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7932 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7933 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7934 "TARGET_POWERPC64"
7935 "@
7936 srad %0,%1,%2
7937 sradi %0,%1,%H2"
7938 [(set_attr "type" "var_shift_rotate,shift")])
7940 (define_insn "*ashrdi3_internal2"
7941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7942 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7943 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7944 (const_int 0)))
7945 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7946 "TARGET_64BIT"
7947 "@
7948 srad. %3,%1,%2
7949 sradi. %3,%1,%H2
7950 #
7951 #"
7952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7953 (set_attr "length" "4,4,8,8")])
7955 (define_split
7956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7957 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7958 (match_operand:SI 2 "reg_or_cint_operand" ""))
7959 (const_int 0)))
7960 (clobber (match_scratch:DI 3 ""))]
7961 "TARGET_POWERPC64 && reload_completed"
7962 [(set (match_dup 3)
7963 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7964 (set (match_dup 0)
7965 (compare:CC (match_dup 3)
7966 (const_int 0)))]
7967 "")
7969 (define_insn "*ashrdi3_internal3"
7970 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7971 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7972 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7973 (const_int 0)))
7974 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7975 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7976 "TARGET_64BIT"
7977 "@
7978 srad. %0,%1,%2
7979 sradi. %0,%1,%H2
7980 #
7981 #"
7982 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7983 (set_attr "length" "4,4,8,8")])
7985 (define_split
7986 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7987 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7988 (match_operand:SI 2 "reg_or_cint_operand" ""))
7989 (const_int 0)))
7990 (set (match_operand:DI 0 "gpc_reg_operand" "")
7991 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7992 "TARGET_POWERPC64 && reload_completed"
7993 [(set (match_dup 0)
7994 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7995 (set (match_dup 3)
7996 (compare:CC (match_dup 0)
7997 (const_int 0)))]
7998 "")
8000 (define_expand "anddi3"
8001 [(parallel
8002 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8003 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8004 (match_operand:DI 2 "and64_2_operand" "")))
8005 (clobber (match_scratch:CC 3 ""))])]
8006 "TARGET_POWERPC64"
8007 "")
8009 (define_insn "anddi3_mc"
8010 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8011 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8012 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8013 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8014 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8015 "@
8016 and %0,%1,%2
8017 rldic%B2 %0,%1,0,%S2
8018 rlwinm %0,%1,0,%m2,%M2
8019 andi. %0,%1,%b2
8020 andis. %0,%1,%u2
8021 #"
8022 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8023 (set_attr "length" "4,4,4,4,4,8")])
8025 (define_insn "anddi3_nomc"
8026 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8027 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8028 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8029 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8030 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8031 "@
8032 and %0,%1,%2
8033 rldic%B2 %0,%1,0,%S2
8034 rlwinm %0,%1,0,%m2,%M2
8035 #"
8036 [(set_attr "length" "4,4,4,8")])
8038 (define_split
8039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8040 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8041 (match_operand:DI 2 "mask64_2_operand" "")))
8042 (clobber (match_scratch:CC 3 ""))]
8043 "TARGET_POWERPC64
8044 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8045 && !mask_operand (operands[2], DImode)
8046 && !mask64_operand (operands[2], DImode)"
8047 [(set (match_dup 0)
8048 (and:DI (rotate:DI (match_dup 1)
8049 (match_dup 4))
8050 (match_dup 5)))
8051 (set (match_dup 0)
8052 (and:DI (rotate:DI (match_dup 0)
8053 (match_dup 6))
8054 (match_dup 7)))]
8055 {
8056 build_mask64_2_operands (operands[2], &operands[4]);
8057 })
8059 (define_insn "*anddi3_internal2_mc"
8060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8061 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8062 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8063 (const_int 0)))
8064 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8065 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8066 "TARGET_64BIT && rs6000_gen_cell_microcode"
8067 "@
8068 and. %3,%1,%2
8069 rldic%B2. %3,%1,0,%S2
8070 rlwinm. %3,%1,0,%m2,%M2
8071 andi. %3,%1,%b2
8072 andis. %3,%1,%u2
8073 #
8074 #
8075 #
8076 #
8077 #
8078 #
8079 #"
8080 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8081 fast_compare,compare,compare,compare,compare,compare,\
8082 compare,compare")
8083 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8085 (define_split
8086 [(set (match_operand:CC 0 "cc_reg_operand" "")
8087 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8088 (match_operand:DI 2 "mask64_2_operand" ""))
8089 (const_int 0)))
8090 (clobber (match_scratch:DI 3 ""))
8091 (clobber (match_scratch:CC 4 ""))]
8092 "TARGET_64BIT && reload_completed
8093 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8094 && !mask_operand (operands[2], DImode)
8095 && !mask64_operand (operands[2], DImode)"
8096 [(set (match_dup 3)
8097 (and:DI (rotate:DI (match_dup 1)
8098 (match_dup 5))
8099 (match_dup 6)))
8100 (parallel [(set (match_dup 0)
8101 (compare:CC (and:DI (rotate:DI (match_dup 3)
8102 (match_dup 7))
8103 (match_dup 8))
8104 (const_int 0)))
8105 (clobber (match_dup 3))])]
8106 "
8107 {
8108 build_mask64_2_operands (operands[2], &operands[5]);
8109 }")
8111 (define_insn "*anddi3_internal3_mc"
8112 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8113 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8114 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8115 (const_int 0)))
8116 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8117 (and:DI (match_dup 1) (match_dup 2)))
8118 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8119 "TARGET_64BIT && rs6000_gen_cell_microcode"
8120 "@
8121 and. %0,%1,%2
8122 rldic%B2. %0,%1,0,%S2
8123 rlwinm. %0,%1,0,%m2,%M2
8124 andi. %0,%1,%b2
8125 andis. %0,%1,%u2
8126 #
8127 #
8128 #
8129 #
8130 #
8131 #
8132 #"
8133 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8134 fast_compare,compare,compare,compare,compare,compare,\
8135 compare,compare")
8136 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8138 (define_split
8139 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8140 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8141 (match_operand:DI 2 "and64_2_operand" ""))
8142 (const_int 0)))
8143 (set (match_operand:DI 0 "gpc_reg_operand" "")
8144 (and:DI (match_dup 1) (match_dup 2)))
8145 (clobber (match_scratch:CC 4 ""))]
8146 "TARGET_64BIT && reload_completed"
8147 [(parallel [(set (match_dup 0)
8148 (and:DI (match_dup 1) (match_dup 2)))
8149 (clobber (match_dup 4))])
8150 (set (match_dup 3)
8151 (compare:CC (match_dup 0)
8152 (const_int 0)))]
8153 "")
8155 (define_split
8156 [(set (match_operand:CC 3 "cc_reg_operand" "")
8157 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8158 (match_operand:DI 2 "mask64_2_operand" ""))
8159 (const_int 0)))
8160 (set (match_operand:DI 0 "gpc_reg_operand" "")
8161 (and:DI (match_dup 1) (match_dup 2)))
8162 (clobber (match_scratch:CC 4 ""))]
8163 "TARGET_64BIT && reload_completed
8164 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8165 && !mask_operand (operands[2], DImode)
8166 && !mask64_operand (operands[2], DImode)"
8167 [(set (match_dup 0)
8168 (and:DI (rotate:DI (match_dup 1)
8169 (match_dup 5))
8170 (match_dup 6)))
8171 (parallel [(set (match_dup 3)
8172 (compare:CC (and:DI (rotate:DI (match_dup 0)
8173 (match_dup 7))
8174 (match_dup 8))
8175 (const_int 0)))
8176 (set (match_dup 0)
8177 (and:DI (rotate:DI (match_dup 0)
8178 (match_dup 7))
8179 (match_dup 8)))])]
8180 "
8181 {
8182 build_mask64_2_operands (operands[2], &operands[5]);
8183 }")
8185 (define_expand "iordi3"
8186 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8187 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8188 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8189 "TARGET_POWERPC64"
8190 "
8191 {
8192 if (non_logical_cint_operand (operands[2], DImode))
8193 {
8194 HOST_WIDE_INT value;
8195 rtx tmp = ((!can_create_pseudo_p ()
8196 || rtx_equal_p (operands[0], operands[1]))
8197 ? operands[0] : gen_reg_rtx (DImode));
8199 if (GET_CODE (operands[2]) == CONST_INT)
8200 {
8201 value = INTVAL (operands[2]);
8202 emit_insn (gen_iordi3 (tmp, operands[1],
8203 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8204 }
8205 else
8206 {
8207 value = CONST_DOUBLE_LOW (operands[2]);
8208 emit_insn (gen_iordi3 (tmp, operands[1],
8209 immed_double_const (value
8210 & (~ (HOST_WIDE_INT) 0xffff),
8211 0, DImode)));
8212 }
8214 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8215 DONE;
8216 }
8217 }")
8219 (define_expand "xordi3"
8220 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8221 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8222 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8223 "TARGET_POWERPC64"
8224 "
8225 {
8226 if (non_logical_cint_operand (operands[2], DImode))
8227 {
8228 HOST_WIDE_INT value;
8229 rtx tmp = ((!can_create_pseudo_p ()
8230 || rtx_equal_p (operands[0], operands[1]))
8231 ? operands[0] : gen_reg_rtx (DImode));
8233 if (GET_CODE (operands[2]) == CONST_INT)
8234 {
8235 value = INTVAL (operands[2]);
8236 emit_insn (gen_xordi3 (tmp, operands[1],
8237 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8238 }
8239 else
8240 {
8241 value = CONST_DOUBLE_LOW (operands[2]);
8242 emit_insn (gen_xordi3 (tmp, operands[1],
8243 immed_double_const (value
8244 & (~ (HOST_WIDE_INT) 0xffff),
8245 0, DImode)));
8246 }
8248 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8249 DONE;
8250 }
8251 }")
8253 (define_insn "*booldi3_internal1"
8254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8255 (match_operator:DI 3 "boolean_or_operator"
8256 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8257 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8258 "TARGET_POWERPC64"
8259 "@
8260 %q3 %0,%1,%2
8261 %q3i %0,%1,%b2
8262 %q3is %0,%1,%u2")
8264 (define_insn "*booldi3_internal2"
8265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8266 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8267 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8268 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8269 (const_int 0)))
8270 (clobber (match_scratch:DI 3 "=r,r"))]
8271 "TARGET_64BIT"
8272 "@
8273 %q4. %3,%1,%2
8274 #"
8275 [(set_attr "type" "fast_compare,compare")
8276 (set_attr "length" "4,8")])
8278 (define_split
8279 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8280 (compare:CC (match_operator:DI 4 "boolean_operator"
8281 [(match_operand:DI 1 "gpc_reg_operand" "")
8282 (match_operand:DI 2 "gpc_reg_operand" "")])
8283 (const_int 0)))
8284 (clobber (match_scratch:DI 3 ""))]
8285 "TARGET_POWERPC64 && reload_completed"
8286 [(set (match_dup 3) (match_dup 4))
8287 (set (match_dup 0)
8288 (compare:CC (match_dup 3)
8289 (const_int 0)))]
8290 "")
8292 (define_insn "*booldi3_internal3"
8293 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8294 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8295 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8296 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8297 (const_int 0)))
8298 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8299 (match_dup 4))]
8300 "TARGET_64BIT"
8301 "@
8302 %q4. %0,%1,%2
8303 #"
8304 [(set_attr "type" "fast_compare,compare")
8305 (set_attr "length" "4,8")])
8307 (define_split
8308 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8309 (compare:CC (match_operator:DI 4 "boolean_operator"
8310 [(match_operand:DI 1 "gpc_reg_operand" "")
8311 (match_operand:DI 2 "gpc_reg_operand" "")])
8312 (const_int 0)))
8313 (set (match_operand:DI 0 "gpc_reg_operand" "")
8314 (match_dup 4))]
8315 "TARGET_POWERPC64 && reload_completed"
8316 [(set (match_dup 0) (match_dup 4))
8317 (set (match_dup 3)
8318 (compare:CC (match_dup 0)
8319 (const_int 0)))]
8320 "")
8322 ;; Split a logical operation that we can't do in one insn into two insns,
8323 ;; each of which does one 16-bit part. This is used by combine.
8325 (define_split
8326 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8327 (match_operator:DI 3 "boolean_or_operator"
8328 [(match_operand:DI 1 "gpc_reg_operand" "")
8329 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8330 "TARGET_POWERPC64"
8331 [(set (match_dup 0) (match_dup 4))
8332 (set (match_dup 0) (match_dup 5))]
8333 "
8334 {
8335 rtx i3,i4;
8337 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8338 {
8339 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8340 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8341 0, DImode);
8342 i4 = GEN_INT (value & 0xffff);
8343 }
8344 else
8345 {
8346 i3 = GEN_INT (INTVAL (operands[2])
8347 & (~ (HOST_WIDE_INT) 0xffff));
8348 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8349 }
8350 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8351 operands[1], i3);
8352 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8353 operands[0], i4);
8354 }")
8356 (define_insn "*boolcdi3_internal1"
8357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8358 (match_operator:DI 3 "boolean_operator"
8359 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8360 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8361 "TARGET_POWERPC64"
8362 "%q3 %0,%2,%1")
8364 (define_insn "*boolcdi3_internal2"
8365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8366 (compare:CC (match_operator:DI 4 "boolean_operator"
8367 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8368 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8369 (const_int 0)))
8370 (clobber (match_scratch:DI 3 "=r,r"))]
8371 "TARGET_64BIT"
8372 "@
8373 %q4. %3,%2,%1
8374 #"
8375 [(set_attr "type" "fast_compare,compare")
8376 (set_attr "length" "4,8")])
8378 (define_split
8379 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8380 (compare:CC (match_operator:DI 4 "boolean_operator"
8381 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8382 (match_operand:DI 2 "gpc_reg_operand" "")])
8383 (const_int 0)))
8384 (clobber (match_scratch:DI 3 ""))]
8385 "TARGET_POWERPC64 && reload_completed"
8386 [(set (match_dup 3) (match_dup 4))
8387 (set (match_dup 0)
8388 (compare:CC (match_dup 3)
8389 (const_int 0)))]
8390 "")
8392 (define_insn "*boolcdi3_internal3"
8393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8394 (compare:CC (match_operator:DI 4 "boolean_operator"
8395 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8396 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8397 (const_int 0)))
8398 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8399 (match_dup 4))]
8400 "TARGET_64BIT"
8401 "@
8402 %q4. %0,%2,%1
8403 #"
8404 [(set_attr "type" "fast_compare,compare")
8405 (set_attr "length" "4,8")])
8407 (define_split
8408 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8409 (compare:CC (match_operator:DI 4 "boolean_operator"
8410 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8411 (match_operand:DI 2 "gpc_reg_operand" "")])
8412 (const_int 0)))
8413 (set (match_operand:DI 0 "gpc_reg_operand" "")
8414 (match_dup 4))]
8415 "TARGET_POWERPC64 && reload_completed"
8416 [(set (match_dup 0) (match_dup 4))
8417 (set (match_dup 3)
8418 (compare:CC (match_dup 0)
8419 (const_int 0)))]
8420 "")
8422 (define_insn "*boolccdi3_internal1"
8423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8424 (match_operator:DI 3 "boolean_operator"
8425 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8426 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8427 "TARGET_POWERPC64"
8428 "%q3 %0,%1,%2")
8430 (define_insn "*boolccdi3_internal2"
8431 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8432 (compare:CC (match_operator:DI 4 "boolean_operator"
8433 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8434 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8435 (const_int 0)))
8436 (clobber (match_scratch:DI 3 "=r,r"))]
8437 "TARGET_64BIT"
8438 "@
8439 %q4. %3,%1,%2
8440 #"
8441 [(set_attr "type" "fast_compare,compare")
8442 (set_attr "length" "4,8")])
8444 (define_split
8445 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8446 (compare:CC (match_operator:DI 4 "boolean_operator"
8447 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8448 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8449 (const_int 0)))
8450 (clobber (match_scratch:DI 3 ""))]
8451 "TARGET_POWERPC64 && reload_completed"
8452 [(set (match_dup 3) (match_dup 4))
8453 (set (match_dup 0)
8454 (compare:CC (match_dup 3)
8455 (const_int 0)))]
8456 "")
8458 (define_insn "*boolccdi3_internal3"
8459 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8460 (compare:CC (match_operator:DI 4 "boolean_operator"
8461 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8462 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8463 (const_int 0)))
8464 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8465 (match_dup 4))]
8466 "TARGET_64BIT"
8467 "@
8468 %q4. %0,%1,%2
8469 #"
8470 [(set_attr "type" "fast_compare,compare")
8471 (set_attr "length" "4,8")])
8473 (define_split
8474 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8475 (compare:CC (match_operator:DI 4 "boolean_operator"
8476 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8477 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8478 (const_int 0)))
8479 (set (match_operand:DI 0 "gpc_reg_operand" "")
8480 (match_dup 4))]
8481 "TARGET_POWERPC64 && reload_completed"
8482 [(set (match_dup 0) (match_dup 4))
8483 (set (match_dup 3)
8484 (compare:CC (match_dup 0)
8485 (const_int 0)))]
8486 "")
8488 (define_expand "smindi3"
8489 [(match_operand:DI 0 "gpc_reg_operand" "")
8490 (match_operand:DI 1 "gpc_reg_operand" "")
8491 (match_operand:DI 2 "gpc_reg_operand" "")]
8492 "TARGET_ISEL64"
8493 "
8494 {
8495 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8496 DONE;
8497 }")
8499 (define_expand "smaxdi3"
8500 [(match_operand:DI 0 "gpc_reg_operand" "")
8501 (match_operand:DI 1 "gpc_reg_operand" "")
8502 (match_operand:DI 2 "gpc_reg_operand" "")]
8503 "TARGET_ISEL64"
8504 "
8505 {
8506 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8507 DONE;
8508 }")
8510 (define_expand "umindi3"
8511 [(match_operand:DI 0 "gpc_reg_operand" "")
8512 (match_operand:DI 1 "gpc_reg_operand" "")
8513 (match_operand:DI 2 "gpc_reg_operand" "")]
8514 "TARGET_ISEL64"
8515 "
8516 {
8517 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8518 DONE;
8519 }")
8521 (define_expand "umaxdi3"
8522 [(match_operand:DI 0 "gpc_reg_operand" "")
8523 (match_operand:DI 1 "gpc_reg_operand" "")
8524 (match_operand:DI 2 "gpc_reg_operand" "")]
8525 "TARGET_ISEL64"
8526 "
8527 {
8528 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8529 DONE;
8530 }")
8532 \f
8533 ;; Now define ways of moving data around.
8535 ;; Set up a register with a value from the GOT table
8537 (define_expand "movsi_got"
8538 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8539 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8540 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8541 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8542 "
8543 {
8544 if (GET_CODE (operands[1]) == CONST)
8545 {
8546 rtx offset = const0_rtx;
8547 HOST_WIDE_INT value;
8549 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8550 value = INTVAL (offset);
8551 if (value != 0)
8552 {
8553 rtx tmp = (!can_create_pseudo_p ()
8554 ? operands[0]
8555 : gen_reg_rtx (Pmode));
8556 emit_insn (gen_movsi_got (tmp, operands[1]));
8557 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8558 DONE;
8559 }
8560 }
8562 operands[2] = rs6000_got_register (operands[1]);
8563 }")
8565 (define_insn "*movsi_got_internal"
8566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8567 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8568 (match_operand:SI 2 "gpc_reg_operand" "b")]
8569 UNSPEC_MOVSI_GOT))]
8570 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8571 "{l|lwz} %0,%a1@got(%2)"
8572 [(set_attr "type" "load")])
8574 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8575 ;; didn't get allocated to a hard register.
8576 (define_split
8577 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8578 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8579 (match_operand:SI 2 "memory_operand" "")]
8580 UNSPEC_MOVSI_GOT))]
8581 "DEFAULT_ABI == ABI_V4
8582 && flag_pic == 1
8583 && (reload_in_progress || reload_completed)"
8584 [(set (match_dup 0) (match_dup 2))
8585 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8586 UNSPEC_MOVSI_GOT))]
8587 "")
8589 ;; For SI, we special-case integers that can't be loaded in one insn. We
8590 ;; do the load 16-bits at a time. We could do this by loading from memory,
8591 ;; and this is even supposed to be faster, but it is simpler not to get
8592 ;; integers in the TOC.
8593 (define_insn "movsi_low"
8594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8595 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8596 (match_operand 2 "" ""))))]
8597 "TARGET_MACHO && ! TARGET_64BIT"
8598 "{l|lwz} %0,lo16(%2)(%1)"
8599 [(set_attr "type" "load")
8600 (set_attr "length" "4")])
8602 (define_insn "*movsi_internal1"
8603 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8604 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8605 "!TARGET_SINGLE_FPU &&
8606 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8607 "@
8608 mr %0,%1
8609 {cal|la} %0,%a1
8610 {l%U1%X1|lwz%U1%X1} %0,%1
8611 {st%U0%X0|stw%U0%X0} %1,%0
8612 {lil|li} %0,%1
8613 {liu|lis} %0,%v1
8614 #
8615 {cal|la} %0,%a1
8616 mf%1 %0
8617 mt%0 %1
8618 mt%0 %1
8619 mt%0 %1
8620 {cror 0,0,0|nop}"
8621 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8622 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8624 (define_insn "*movsi_internal1_single"
8625 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8626 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8627 "TARGET_SINGLE_FPU &&
8628 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8629 "@
8630 mr %0,%1
8631 {cal|la} %0,%a1
8632 {l%U1%X1|lwz%U1%X1} %0,%1
8633 {st%U0%X0|stw%U0%X0} %1,%0
8634 {lil|li} %0,%1
8635 {liu|lis} %0,%v1
8636 #
8637 {cal|la} %0,%a1
8638 mf%1 %0
8639 mt%0 %1
8640 mt%0 %1
8641 mt%0 %1
8642 {cror 0,0,0|nop}
8643 stfs%U0%X0 %1, %0
8644 lfs%U1%X1 %0, %1"
8645 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8646 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8648 ;; Split a load of a large constant into the appropriate two-insn
8649 ;; sequence.
8651 (define_split
8652 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8653 (match_operand:SI 1 "const_int_operand" ""))]
8654 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8655 && (INTVAL (operands[1]) & 0xffff) != 0"
8656 [(set (match_dup 0)
8657 (match_dup 2))
8658 (set (match_dup 0)
8659 (ior:SI (match_dup 0)
8660 (match_dup 3)))]
8661 "
8662 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8664 if (tem == operands[0])
8665 DONE;
8666 else
8667 FAIL;
8668 }")
8670 (define_insn "*mov<mode>_internal2"
8671 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8672 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8673 (const_int 0)))
8674 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8675 ""
8676 "@
8677 {cmpi|cmp<wd>i} %2,%0,0
8678 mr. %0,%1
8679 #"
8680 [(set_attr "type" "cmp,compare,cmp")
8681 (set_attr "length" "4,4,8")])
8683 (define_split
8684 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8685 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8686 (const_int 0)))
8687 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8688 "reload_completed"
8689 [(set (match_dup 0) (match_dup 1))
8690 (set (match_dup 2)
8691 (compare:CC (match_dup 0)
8692 (const_int 0)))]
8693 "")
8694 \f
8695 (define_insn "*movhi_internal"
8696 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8697 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8698 "gpc_reg_operand (operands[0], HImode)
8699 || gpc_reg_operand (operands[1], HImode)"
8700 "@
8701 mr %0,%1
8702 lhz%U1%X1 %0,%1
8703 sth%U0%X0 %1,%0
8704 {lil|li} %0,%w1
8705 mf%1 %0
8706 mt%0 %1
8707 mt%0 %1
8708 {cror 0,0,0|nop}"
8709 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8711 (define_expand "mov<mode>"
8712 [(set (match_operand:INT 0 "general_operand" "")
8713 (match_operand:INT 1 "any_operand" ""))]
8714 ""
8715 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8717 (define_insn "*movqi_internal"
8718 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8719 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8720 "gpc_reg_operand (operands[0], QImode)
8721 || gpc_reg_operand (operands[1], QImode)"
8722 "@
8723 mr %0,%1
8724 lbz%U1%X1 %0,%1
8725 stb%U0%X0 %1,%0
8726 {lil|li} %0,%1
8727 mf%1 %0
8728 mt%0 %1
8729 mt%0 %1
8730 {cror 0,0,0|nop}"
8731 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8732 \f
8733 ;; Here is how to move condition codes around. When we store CC data in
8734 ;; an integer register or memory, we store just the high-order 4 bits.
8735 ;; This lets us not shift in the most common case of CR0.
8736 (define_expand "movcc"
8737 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8738 (match_operand:CC 1 "nonimmediate_operand" ""))]
8739 ""
8740 "")
8742 (define_insn "*movcc_internal1"
8743 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8744 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8745 "register_operand (operands[0], CCmode)
8746 || register_operand (operands[1], CCmode)"
8747 "@
8748 mcrf %0,%1
8749 mtcrf 128,%1
8750 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8751 crxor %0,%0,%0
8752 mfcr %0%Q1
8753 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8754 mr %0,%1
8755 {lil|li} %0,%1
8756 mf%1 %0
8757 mt%0 %1
8758 mt%0 %1
8759 {l%U1%X1|lwz%U1%X1} %0,%1
8760 {st%U0%U1|stw%U0%U1} %1,%0"
8761 [(set (attr "type")
8762 (cond [(eq_attr "alternative" "0,3")
8763 (const_string "cr_logical")
8764 (eq_attr "alternative" "1,2")
8765 (const_string "mtcr")
8766 (eq_attr "alternative" "6,7,9")
8767 (const_string "integer")
8768 (eq_attr "alternative" "8")
8769 (const_string "mfjmpr")
8770 (eq_attr "alternative" "10")
8771 (const_string "mtjmpr")
8772 (eq_attr "alternative" "11")
8773 (const_string "load")
8774 (eq_attr "alternative" "12")
8775 (const_string "store")
8776 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8777 (const_string "mfcrf")
8778 ]
8779 (const_string "mfcr")))
8780 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8781 \f
8782 ;; For floating-point, we normally deal with the floating-point registers
8783 ;; unless -msoft-float is used. The sole exception is that parameter passing
8784 ;; can produce floating-point values in fixed-point registers. Unless the
8785 ;; value is a simple constant or already in memory, we deal with this by
8786 ;; allocating memory and copying the value explicitly via that memory location.
8787 (define_expand "movsf"
8788 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8789 (match_operand:SF 1 "any_operand" ""))]
8790 ""
8791 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8793 (define_split
8794 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8795 (match_operand:SF 1 "const_double_operand" ""))]
8796 "reload_completed
8797 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8798 || (GET_CODE (operands[0]) == SUBREG
8799 && GET_CODE (SUBREG_REG (operands[0])) == REG
8800 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8801 [(set (match_dup 2) (match_dup 3))]
8802 "
8803 {
8804 long l;
8805 REAL_VALUE_TYPE rv;
8807 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8808 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8810 if (! TARGET_POWERPC64)
8811 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8812 else
8813 operands[2] = gen_lowpart (SImode, operands[0]);
8815 operands[3] = gen_int_mode (l, SImode);
8816 }")
8818 (define_insn "*movsf_hardfloat"
8819 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8820 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8821 "(gpc_reg_operand (operands[0], SFmode)
8822 || gpc_reg_operand (operands[1], SFmode))
8823 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8824 "@
8825 mr %0,%1
8826 {l%U1%X1|lwz%U1%X1} %0,%1
8827 {st%U0%X0|stw%U0%X0} %1,%0
8828 fmr %0,%1
8829 lfs%U1%X1 %0,%1
8830 stfs%U0%X0 %1,%0
8831 mt%0 %1
8832 mt%0 %1
8833 mf%1 %0
8834 {cror 0,0,0|nop}
8835 #
8836 #"
8837 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8838 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8840 (define_insn "*movsf_softfloat"
8841 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8842 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8843 "(gpc_reg_operand (operands[0], SFmode)
8844 || gpc_reg_operand (operands[1], SFmode))
8845 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8846 "@
8847 mr %0,%1
8848 mt%0 %1
8849 mt%0 %1
8850 mf%1 %0
8851 {l%U1%X1|lwz%U1%X1} %0,%1
8852 {st%U0%X0|stw%U0%X0} %1,%0
8853 {lil|li} %0,%1
8854 {liu|lis} %0,%v1
8855 {cal|la} %0,%a1
8856 #
8857 #
8858 {cror 0,0,0|nop}"
8859 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8860 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8862 \f
8863 (define_expand "movdf"
8864 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8865 (match_operand:DF 1 "any_operand" ""))]
8866 ""
8867 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8869 (define_split
8870 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8871 (match_operand:DF 1 "const_int_operand" ""))]
8872 "! TARGET_POWERPC64 && reload_completed
8873 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8874 || (GET_CODE (operands[0]) == SUBREG
8875 && GET_CODE (SUBREG_REG (operands[0])) == REG
8876 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8877 [(set (match_dup 2) (match_dup 4))
8878 (set (match_dup 3) (match_dup 1))]
8879 "
8880 {
8881 int endian = (WORDS_BIG_ENDIAN == 0);
8882 HOST_WIDE_INT value = INTVAL (operands[1]);
8884 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8885 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8886 #if HOST_BITS_PER_WIDE_INT == 32
8887 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8888 #else
8889 operands[4] = GEN_INT (value >> 32);
8890 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8891 #endif
8892 }")
8894 (define_split
8895 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8896 (match_operand:DF 1 "const_double_operand" ""))]
8897 "! TARGET_POWERPC64 && reload_completed
8898 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8899 || (GET_CODE (operands[0]) == SUBREG
8900 && GET_CODE (SUBREG_REG (operands[0])) == REG
8901 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8902 [(set (match_dup 2) (match_dup 4))
8903 (set (match_dup 3) (match_dup 5))]
8904 "
8905 {
8906 int endian = (WORDS_BIG_ENDIAN == 0);
8907 long l[2];
8908 REAL_VALUE_TYPE rv;
8910 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8911 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8913 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8914 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8915 operands[4] = gen_int_mode (l[endian], SImode);
8916 operands[5] = gen_int_mode (l[1 - endian], SImode);
8917 }")
8919 (define_split
8920 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8921 (match_operand:DF 1 "const_double_operand" ""))]
8922 "TARGET_POWERPC64 && reload_completed
8923 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8924 || (GET_CODE (operands[0]) == SUBREG
8925 && GET_CODE (SUBREG_REG (operands[0])) == REG
8926 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8927 [(set (match_dup 2) (match_dup 3))]
8928 "
8929 {
8930 int endian = (WORDS_BIG_ENDIAN == 0);
8931 long l[2];
8932 REAL_VALUE_TYPE rv;
8933 #if HOST_BITS_PER_WIDE_INT >= 64
8934 HOST_WIDE_INT val;
8935 #endif
8937 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8938 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8940 operands[2] = gen_lowpart (DImode, operands[0]);
8941 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8942 #if HOST_BITS_PER_WIDE_INT >= 64
8943 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8944 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8946 operands[3] = gen_int_mode (val, DImode);
8947 #else
8948 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8949 #endif
8950 }")
8952 ;; Don't have reload use general registers to load a constant. First,
8953 ;; it might not work if the output operand is the equivalent of
8954 ;; a non-offsettable memref, but also it is less efficient than loading
8955 ;; the constant into an FP register, since it will probably be used there.
8956 ;; The "??" is a kludge until we can figure out a more reasonable way
8957 ;; of handling these non-offsettable values.
8958 (define_insn "*movdf_hardfloat32"
8959 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
8960 (match_operand:DF 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
8961 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8962 && (gpc_reg_operand (operands[0], DFmode)
8963 || gpc_reg_operand (operands[1], DFmode))"
8964 "*
8965 {
8966 switch (which_alternative)
8967 {
8968 default:
8969 gcc_unreachable ();
8970 case 0:
8971 /* We normally copy the low-numbered register first. However, if
8972 the first register operand 0 is the same as the second register
8973 of operand 1, we must copy in the opposite order. */
8974 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8975 return \"mr %L0,%L1\;mr %0,%1\";
8976 else
8977 return \"mr %0,%1\;mr %L0,%L1\";
8978 case 1:
8979 if (rs6000_offsettable_memref_p (operands[1])
8980 || (GET_CODE (operands[1]) == MEM
8981 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8982 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8983 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8984 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8985 {
8986 /* If the low-address word is used in the address, we must load
8987 it last. Otherwise, load it first. Note that we cannot have
8988 auto-increment in that case since the address register is
8989 known to be dead. */
8990 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8991 operands[1], 0))
8992 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8993 else
8994 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8995 }
8996 else
8997 {
8998 rtx addreg;
9000 addreg = find_addr_reg (XEXP (operands[1], 0));
9001 if (refers_to_regno_p (REGNO (operands[0]),
9002 REGNO (operands[0]) + 1,
9003 operands[1], 0))
9004 {
9005 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9006 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9007 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9008 return \"{l%X1|lwz%X1} %0,%1\";
9009 }
9010 else
9011 {
9012 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
9013 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9014 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9015 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9016 return \"\";
9017 }
9018 }
9019 case 2:
9020 if (rs6000_offsettable_memref_p (operands[0])
9021 || (GET_CODE (operands[0]) == MEM
9022 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
9023 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
9024 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
9025 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
9026 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9027 else
9028 {
9029 rtx addreg;
9031 addreg = find_addr_reg (XEXP (operands[0], 0));
9032 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
9033 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9034 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
9035 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9036 return \"\";
9037 }
9038 case 3:
9039 return \"fmr %0,%1\";
9040 case 4:
9041 return \"lfd%U1%X1 %0,%1\";
9042 case 5:
9043 return \"stfd%U0%X0 %1,%0\";
9044 case 6:
9045 case 7:
9046 case 8:
9047 return \"#\";
9048 }
9049 }"
9050 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
9051 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
9053 (define_insn "*movdf_softfloat32"
9054 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9055 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9056 "! TARGET_POWERPC64
9057 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9058 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9059 && (gpc_reg_operand (operands[0], DFmode)
9060 || gpc_reg_operand (operands[1], DFmode))"
9061 "*
9062 {
9063 switch (which_alternative)
9064 {
9065 default:
9066 gcc_unreachable ();
9067 case 0:
9068 /* We normally copy the low-numbered register first. However, if
9069 the first register operand 0 is the same as the second register of
9070 operand 1, we must copy in the opposite order. */
9071 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9072 return \"mr %L0,%L1\;mr %0,%1\";
9073 else
9074 return \"mr %0,%1\;mr %L0,%L1\";
9075 case 1:
9076 /* If the low-address word is used in the address, we must load
9077 it last. Otherwise, load it first. Note that we cannot have
9078 auto-increment in that case since the address register is
9079 known to be dead. */
9080 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9081 operands[1], 0))
9082 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9083 else
9084 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9085 case 2:
9086 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9087 case 3:
9088 case 4:
9089 case 5:
9090 return \"#\";
9091 }
9092 }"
9093 [(set_attr "type" "two,load,store,*,*,*")
9094 (set_attr "length" "8,8,8,8,12,16")])
9096 ; ld/std require word-aligned displacements -> 'Y' constraint.
9097 ; List Y->r and r->Y before r->r for reload.
9098 (define_insn "*movdf_hardfloat64_mfpgpr"
9099 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
9100 (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
9101 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9102 && TARGET_DOUBLE_FLOAT
9103 && (gpc_reg_operand (operands[0], DFmode)
9104 || gpc_reg_operand (operands[1], DFmode))"
9105 "@
9106 std%U0%X0 %1,%0
9107 ld%U1%X1 %0,%1
9108 mr %0,%1
9109 fmr %0,%1
9110 lfd%U1%X1 %0,%1
9111 stfd%U0%X0 %1,%0
9112 mt%0 %1
9113 mf%1 %0
9114 {cror 0,0,0|nop}
9115 #
9116 #
9117 #
9118 mftgpr %0,%1
9119 mffgpr %0,%1"
9120 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9121 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9123 ; ld/std require word-aligned displacements -> 'Y' constraint.
9124 ; List Y->r and r->Y before r->r for reload.
9125 (define_insn "*movdf_hardfloat64"
9126 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
9127 (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
9128 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9129 && TARGET_DOUBLE_FLOAT
9130 && (gpc_reg_operand (operands[0], DFmode)
9131 || gpc_reg_operand (operands[1], DFmode))"
9132 "@
9133 std%U0%X0 %1,%0
9134 ld%U1%X1 %0,%1
9135 mr %0,%1
9136 fmr %0,%1
9137 lfd%U1%X1 %0,%1
9138 stfd%U0%X0 %1,%0
9139 mt%0 %1
9140 mf%1 %0
9141 {cror 0,0,0|nop}
9142 #
9143 #
9144 #"
9145 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
9146 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
9148 (define_insn "*movdf_softfloat64"
9149 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9150 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9151 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9152 && (gpc_reg_operand (operands[0], DFmode)
9153 || gpc_reg_operand (operands[1], DFmode))"
9154 "@
9155 ld%U1%X1 %0,%1
9156 std%U0%X0 %1,%0
9157 mr %0,%1
9158 mt%0 %1
9159 mf%1 %0
9160 #
9161 #
9162 #
9163 {cror 0,0,0|nop}"
9164 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9165 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9166 \f
9167 (define_expand "movtf"
9168 [(set (match_operand:TF 0 "general_operand" "")
9169 (match_operand:TF 1 "any_operand" ""))]
9170 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9171 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9173 ; It's important to list the o->f and f->o moves before f->f because
9174 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9175 ; which doesn't make progress. Likewise r->Y must be before r->r.
9176 (define_insn_and_split "*movtf_internal"
9177 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9178 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9179 "!TARGET_IEEEQUAD
9180 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9181 && (gpc_reg_operand (operands[0], TFmode)
9182 || gpc_reg_operand (operands[1], TFmode))"
9183 "#"
9184 "&& reload_completed"
9185 [(pc)]
9186 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9187 [(set_attr "length" "8,8,8,20,20,16")])
9189 (define_insn_and_split "*movtf_softfloat"
9190 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9191 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9192 "!TARGET_IEEEQUAD
9193 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9194 && (gpc_reg_operand (operands[0], TFmode)
9195 || gpc_reg_operand (operands[1], TFmode))"
9196 "#"
9197 "&& reload_completed"
9198 [(pc)]
9199 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9200 [(set_attr "length" "20,20,16")])
9202 (define_expand "extenddftf2"
9203 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9204 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9205 "!TARGET_IEEEQUAD
9206 && TARGET_HARD_FLOAT
9207 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9208 && TARGET_LONG_DOUBLE_128"
9209 {
9210 if (TARGET_E500_DOUBLE)
9211 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9212 else
9213 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9214 DONE;
9215 })
9217 (define_expand "extenddftf2_fprs"
9218 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9219 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9220 (use (match_dup 2))])]
9221 "!TARGET_IEEEQUAD
9222 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9223 && TARGET_LONG_DOUBLE_128"
9224 {
9225 operands[2] = CONST0_RTX (DFmode);
9226 /* Generate GOT reference early for SVR4 PIC. */
9227 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9228 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9229 })
9231 (define_insn_and_split "*extenddftf2_internal"
9232 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9233 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9234 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9235 "!TARGET_IEEEQUAD
9236 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9237 && TARGET_LONG_DOUBLE_128"
9238 "#"
9239 "&& reload_completed"
9240 [(pc)]
9241 {
9242 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9243 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9244 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9245 operands[1]);
9246 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9247 operands[2]);
9248 DONE;
9249 })
9251 (define_expand "extendsftf2"
9252 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9253 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9254 "!TARGET_IEEEQUAD
9255 && TARGET_HARD_FLOAT
9256 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9257 && TARGET_LONG_DOUBLE_128"
9258 {
9259 rtx tmp = gen_reg_rtx (DFmode);
9260 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9261 emit_insn (gen_extenddftf2 (operands[0], tmp));
9262 DONE;
9263 })
9265 (define_expand "trunctfdf2"
9266 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9267 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9268 "!TARGET_IEEEQUAD
9269 && TARGET_HARD_FLOAT
9270 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9271 && TARGET_LONG_DOUBLE_128"
9272 "")
9274 (define_insn_and_split "trunctfdf2_internal1"
9275 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9276 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9277 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9278 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9279 "@
9280 #
9281 fmr %0,%1"
9282 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9283 [(const_int 0)]
9284 {
9285 emit_note (NOTE_INSN_DELETED);
9286 DONE;
9287 }
9288 [(set_attr "type" "fp")])
9290 (define_insn "trunctfdf2_internal2"
9291 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9292 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9293 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9294 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9295 && TARGET_LONG_DOUBLE_128"
9296 "fadd %0,%1,%L1"
9297 [(set_attr "type" "fp")
9298 (set_attr "fp_type" "fp_addsub_d")])
9300 (define_expand "trunctfsf2"
9301 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9302 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9303 "!TARGET_IEEEQUAD
9304 && TARGET_HARD_FLOAT
9305 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9306 && TARGET_LONG_DOUBLE_128"
9307 {
9308 if (TARGET_E500_DOUBLE)
9309 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9310 else
9311 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9312 DONE;
9313 })
9315 (define_insn_and_split "trunctfsf2_fprs"
9316 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9317 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9318 (clobber (match_scratch:DF 2 "=d"))]
9319 "!TARGET_IEEEQUAD
9320 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9321 && TARGET_LONG_DOUBLE_128"
9322 "#"
9323 "&& reload_completed"
9324 [(set (match_dup 2)
9325 (float_truncate:DF (match_dup 1)))
9326 (set (match_dup 0)
9327 (float_truncate:SF (match_dup 2)))]
9328 "")
9330 (define_expand "floatsitf2"
9331 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9332 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9333 "!TARGET_IEEEQUAD
9334 && TARGET_HARD_FLOAT
9335 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9336 && TARGET_LONG_DOUBLE_128"
9337 {
9338 rtx tmp = gen_reg_rtx (DFmode);
9339 expand_float (tmp, operands[1], false);
9340 emit_insn (gen_extenddftf2 (operands[0], tmp));
9341 DONE;
9342 })
9344 ; fadd, but rounding towards zero.
9345 ; This is probably not the optimal code sequence.
9346 (define_insn "fix_trunc_helper"
9347 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9348 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9349 UNSPEC_FIX_TRUNC_TF))
9350 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9351 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9352 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9353 [(set_attr "type" "fp")
9354 (set_attr "length" "20")])
9356 (define_expand "fix_trunctfsi2"
9357 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9358 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9359 "!TARGET_IEEEQUAD
9360 && (TARGET_POWER2 || TARGET_POWERPC)
9361 && TARGET_HARD_FLOAT
9362 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9363 && TARGET_LONG_DOUBLE_128"
9364 {
9365 if (TARGET_E500_DOUBLE)
9366 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9367 else
9368 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9369 DONE;
9370 })
9372 (define_expand "fix_trunctfsi2_fprs"
9373 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9374 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9375 (clobber (match_dup 2))
9376 (clobber (match_dup 3))
9377 (clobber (match_dup 4))
9378 (clobber (match_dup 5))])]
9379 "!TARGET_IEEEQUAD
9380 && (TARGET_POWER2 || TARGET_POWERPC)
9381 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9382 {
9383 operands[2] = gen_reg_rtx (DFmode);
9384 operands[3] = gen_reg_rtx (DFmode);
9385 operands[4] = gen_reg_rtx (DImode);
9386 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9387 })
9389 (define_insn_and_split "*fix_trunctfsi2_internal"
9390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9391 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9392 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9393 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9394 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9395 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9396 "!TARGET_IEEEQUAD
9397 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9398 "#"
9399 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
9400 [(pc)]
9401 {
9402 rtx lowword;
9403 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9405 gcc_assert (MEM_P (operands[5]));
9406 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9408 emit_insn (gen_fctiwz (operands[4], operands[2]));
9409 emit_move_insn (operands[5], operands[4]);
9410 emit_move_insn (operands[0], lowword);
9411 DONE;
9412 })
9414 (define_expand "negtf2"
9415 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9416 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9417 "!TARGET_IEEEQUAD
9418 && TARGET_HARD_FLOAT
9419 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9420 && TARGET_LONG_DOUBLE_128"
9421 "")
9423 (define_insn "negtf2_internal"
9424 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9425 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9426 "!TARGET_IEEEQUAD
9427 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9428 "*
9429 {
9430 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9431 return \"fneg %L0,%L1\;fneg %0,%1\";
9432 else
9433 return \"fneg %0,%1\;fneg %L0,%L1\";
9434 }"
9435 [(set_attr "type" "fp")
9436 (set_attr "length" "8")])
9438 (define_expand "abstf2"
9439 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9440 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9441 "!TARGET_IEEEQUAD
9442 && TARGET_HARD_FLOAT
9443 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9444 && TARGET_LONG_DOUBLE_128"
9445 "
9446 {
9447 rtx label = gen_label_rtx ();
9448 if (TARGET_E500_DOUBLE)
9449 {
9450 if (flag_finite_math_only && !flag_trapping_math)
9451 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9452 else
9453 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9454 }
9455 else
9456 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9457 emit_label (label);
9458 DONE;
9459 }")
9461 (define_expand "abstf2_internal"
9462 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9463 (match_operand:TF 1 "gpc_reg_operand" ""))
9464 (set (match_dup 3) (match_dup 5))
9465 (set (match_dup 5) (abs:DF (match_dup 5)))
9466 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9467 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9468 (label_ref (match_operand 2 "" ""))
9469 (pc)))
9470 (set (match_dup 6) (neg:DF (match_dup 6)))]
9471 "!TARGET_IEEEQUAD
9472 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9473 && TARGET_LONG_DOUBLE_128"
9474 "
9475 {
9476 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9477 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9478 operands[3] = gen_reg_rtx (DFmode);
9479 operands[4] = gen_reg_rtx (CCFPmode);
9480 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9481 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9482 }")
9483 \f
9484 ;; Next come the multi-word integer load and store and the load and store
9485 ;; multiple insns.
9487 ; List r->r after r->"o<>", otherwise reload will try to reload a
9488 ; non-offsettable address by using r->r which won't make progress.
9489 (define_insn "*movdi_internal32"
9490 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9491 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9492 "! TARGET_POWERPC64
9493 && (gpc_reg_operand (operands[0], DImode)
9494 || gpc_reg_operand (operands[1], DImode))"
9495 "@
9496 #
9497 #
9498 #
9499 fmr %0,%1
9500 lfd%U1%X1 %0,%1
9501 stfd%U0%X0 %1,%0
9502 #"
9503 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9505 (define_split
9506 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9507 (match_operand:DI 1 "const_int_operand" ""))]
9508 "! TARGET_POWERPC64 && reload_completed"
9509 [(set (match_dup 2) (match_dup 4))
9510 (set (match_dup 3) (match_dup 1))]
9511 "
9512 {
9513 HOST_WIDE_INT value = INTVAL (operands[1]);
9514 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9515 DImode);
9516 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9517 DImode);
9518 #if HOST_BITS_PER_WIDE_INT == 32
9519 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9520 #else
9521 operands[4] = GEN_INT (value >> 32);
9522 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9523 #endif
9524 }")
9526 (define_split
9527 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9528 (match_operand:DI 1 "input_operand" ""))]
9529 "reload_completed && !TARGET_POWERPC64
9530 && gpr_or_gpr_p (operands[0], operands[1])"
9531 [(pc)]
9532 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9534 (define_insn "*movdi_mfpgpr"
9535 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9536 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9537 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9538 && (gpc_reg_operand (operands[0], DImode)
9539 || gpc_reg_operand (operands[1], DImode))"
9540 "@
9541 mr %0,%1
9542 ld%U1%X1 %0,%1
9543 std%U0%X0 %1,%0
9544 li %0,%1
9545 lis %0,%v1
9546 #
9547 {cal|la} %0,%a1
9548 fmr %0,%1
9549 lfd%U1%X1 %0,%1
9550 stfd%U0%X0 %1,%0
9551 mf%1 %0
9552 mt%0 %1
9553 {cror 0,0,0|nop}
9554 mftgpr %0,%1
9555 mffgpr %0,%1"
9556 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9557 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9559 (define_insn "*movdi_internal64"
9560 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9561 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9562 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9563 && (gpc_reg_operand (operands[0], DImode)
9564 || gpc_reg_operand (operands[1], DImode))"
9565 "@
9566 mr %0,%1
9567 ld%U1%X1 %0,%1
9568 std%U0%X0 %1,%0
9569 li %0,%1
9570 lis %0,%v1
9571 #
9572 {cal|la} %0,%a1
9573 fmr %0,%1
9574 lfd%U1%X1 %0,%1
9575 stfd%U0%X0 %1,%0
9576 mf%1 %0
9577 mt%0 %1
9578 {cror 0,0,0|nop}"
9579 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9580 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9582 ;; immediate value valid for a single instruction hiding in a const_double
9583 (define_insn ""
9584 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9585 (match_operand:DI 1 "const_double_operand" "F"))]
9586 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9587 && GET_CODE (operands[1]) == CONST_DOUBLE
9588 && num_insns_constant (operands[1], DImode) == 1"
9589 "*
9590 {
9591 return ((unsigned HOST_WIDE_INT)
9592 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9593 ? \"li %0,%1\" : \"lis %0,%v1\";
9594 }")
9596 ;; Generate all one-bits and clear left or right.
9597 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9598 (define_split
9599 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9600 (match_operand:DI 1 "mask64_operand" ""))]
9601 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9602 [(set (match_dup 0) (const_int -1))
9603 (set (match_dup 0)
9604 (and:DI (rotate:DI (match_dup 0)
9605 (const_int 0))
9606 (match_dup 1)))]
9607 "")
9609 ;; Split a load of a large constant into the appropriate five-instruction
9610 ;; sequence. Handle anything in a constant number of insns.
9611 ;; When non-easy constants can go in the TOC, this should use
9612 ;; easy_fp_constant predicate.
9613 (define_split
9614 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9615 (match_operand:DI 1 "const_int_operand" ""))]
9616 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9617 [(set (match_dup 0) (match_dup 2))
9618 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9619 "
9620 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9622 if (tem == operands[0])
9623 DONE;
9624 else
9625 FAIL;
9626 }")
9628 (define_split
9629 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9630 (match_operand:DI 1 "const_double_operand" ""))]
9631 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9632 [(set (match_dup 0) (match_dup 2))
9633 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9634 "
9635 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9637 if (tem == operands[0])
9638 DONE;
9639 else
9640 FAIL;
9641 }")
9642 \f
9643 ;; TImode is similar, except that we usually want to compute the address into
9644 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9645 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9647 ;; We say that MQ is clobbered in the last alternative because the first
9648 ;; alternative would never get used otherwise since it would need a reload
9649 ;; while the 2nd alternative would not. We put memory cases first so they
9650 ;; are preferred. Otherwise, we'd try to reload the output instead of
9651 ;; giving the SCRATCH mq.
9653 (define_insn "*movti_power"
9654 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9655 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9656 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9657 "TARGET_POWER && ! TARGET_POWERPC64
9658 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9659 "*
9660 {
9661 switch (which_alternative)
9662 {
9663 default:
9664 gcc_unreachable ();
9666 case 0:
9667 if (TARGET_STRING)
9668 return \"{stsi|stswi} %1,%P0,16\";
9669 case 1:
9670 case 2:
9671 return \"#\";
9672 case 3:
9673 /* If the address is not used in the output, we can use lsi. Otherwise,
9674 fall through to generating four loads. */
9675 if (TARGET_STRING
9676 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9677 return \"{lsi|lswi} %0,%P1,16\";
9678 /* ... fall through ... */
9679 case 4:
9680 case 5:
9681 return \"#\";
9682 }
9683 }"
9684 [(set_attr "type" "store,store,*,load,load,*")])
9686 (define_insn "*movti_string"
9687 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9688 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9689 "! TARGET_POWER && ! TARGET_POWERPC64
9690 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9691 "*
9692 {
9693 switch (which_alternative)
9694 {
9695 default:
9696 gcc_unreachable ();
9697 case 0:
9698 if (TARGET_STRING)
9699 return \"{stsi|stswi} %1,%P0,16\";
9700 case 1:
9701 case 2:
9702 return \"#\";
9703 case 3:
9704 /* If the address is not used in the output, we can use lsi. Otherwise,
9705 fall through to generating four loads. */
9706 if (TARGET_STRING
9707 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9708 return \"{lsi|lswi} %0,%P1,16\";
9709 /* ... fall through ... */
9710 case 4:
9711 case 5:
9712 return \"#\";
9713 }
9714 }"
9715 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9716 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9717 (const_string "always")
9718 (const_string "conditional")))])
9720 (define_insn "*movti_ppc64"
9721 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9722 (match_operand:TI 1 "input_operand" "r,r,m"))]
9723 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9724 || gpc_reg_operand (operands[1], TImode))"
9725 "#"
9726 [(set_attr "type" "*,store,load")])
9728 (define_split
9729 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9730 (match_operand:TI 1 "const_double_operand" ""))]
9731 "TARGET_POWERPC64"
9732 [(set (match_dup 2) (match_dup 4))
9733 (set (match_dup 3) (match_dup 5))]
9734 "
9735 {
9736 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9737 TImode);
9738 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9739 TImode);
9740 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9741 {
9742 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9743 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9744 }
9745 else if (GET_CODE (operands[1]) == CONST_INT)
9746 {
9747 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9748 operands[5] = operands[1];
9749 }
9750 else
9751 FAIL;
9752 }")
9754 (define_split
9755 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9756 (match_operand:TI 1 "input_operand" ""))]
9757 "reload_completed
9758 && gpr_or_gpr_p (operands[0], operands[1])"
9759 [(pc)]
9760 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9761 \f
9762 (define_expand "load_multiple"
9763 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9764 (match_operand:SI 1 "" ""))
9765 (use (match_operand:SI 2 "" ""))])]
9766 "TARGET_STRING && !TARGET_POWERPC64"
9767 "
9768 {
9769 int regno;
9770 int count;
9771 rtx op1;
9772 int i;
9774 /* Support only loading a constant number of fixed-point registers from
9775 memory and only bother with this if more than two; the machine
9776 doesn't support more than eight. */
9777 if (GET_CODE (operands[2]) != CONST_INT
9778 || INTVAL (operands[2]) <= 2
9779 || INTVAL (operands[2]) > 8
9780 || GET_CODE (operands[1]) != MEM
9781 || GET_CODE (operands[0]) != REG
9782 || REGNO (operands[0]) >= 32)
9783 FAIL;
9785 count = INTVAL (operands[2]);
9786 regno = REGNO (operands[0]);
9788 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9789 op1 = replace_equiv_address (operands[1],
9790 force_reg (SImode, XEXP (operands[1], 0)));
9792 for (i = 0; i < count; i++)
9793 XVECEXP (operands[3], 0, i)
9794 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9795 adjust_address_nv (op1, SImode, i * 4));
9796 }")
9798 (define_insn "*ldmsi8"
9799 [(match_parallel 0 "load_multiple_operation"
9800 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9801 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9802 (set (match_operand:SI 3 "gpc_reg_operand" "")
9803 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9804 (set (match_operand:SI 4 "gpc_reg_operand" "")
9805 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9806 (set (match_operand:SI 5 "gpc_reg_operand" "")
9807 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9808 (set (match_operand:SI 6 "gpc_reg_operand" "")
9809 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9810 (set (match_operand:SI 7 "gpc_reg_operand" "")
9811 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9812 (set (match_operand:SI 8 "gpc_reg_operand" "")
9813 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9814 (set (match_operand:SI 9 "gpc_reg_operand" "")
9815 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9816 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9817 "*
9818 { return rs6000_output_load_multiple (operands); }"
9819 [(set_attr "type" "load_ux")
9820 (set_attr "length" "32")])
9822 (define_insn "*ldmsi7"
9823 [(match_parallel 0 "load_multiple_operation"
9824 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9825 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9826 (set (match_operand:SI 3 "gpc_reg_operand" "")
9827 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9828 (set (match_operand:SI 4 "gpc_reg_operand" "")
9829 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9830 (set (match_operand:SI 5 "gpc_reg_operand" "")
9831 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9832 (set (match_operand:SI 6 "gpc_reg_operand" "")
9833 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9834 (set (match_operand:SI 7 "gpc_reg_operand" "")
9835 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9836 (set (match_operand:SI 8 "gpc_reg_operand" "")
9837 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9838 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9839 "*
9840 { return rs6000_output_load_multiple (operands); }"
9841 [(set_attr "type" "load_ux")
9842 (set_attr "length" "32")])
9844 (define_insn "*ldmsi6"
9845 [(match_parallel 0 "load_multiple_operation"
9846 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9847 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9848 (set (match_operand:SI 3 "gpc_reg_operand" "")
9849 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9850 (set (match_operand:SI 4 "gpc_reg_operand" "")
9851 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9852 (set (match_operand:SI 5 "gpc_reg_operand" "")
9853 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9854 (set (match_operand:SI 6 "gpc_reg_operand" "")
9855 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9856 (set (match_operand:SI 7 "gpc_reg_operand" "")
9857 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9858 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9859 "*
9860 { return rs6000_output_load_multiple (operands); }"
9861 [(set_attr "type" "load_ux")
9862 (set_attr "length" "32")])
9864 (define_insn "*ldmsi5"
9865 [(match_parallel 0 "load_multiple_operation"
9866 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9867 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9868 (set (match_operand:SI 3 "gpc_reg_operand" "")
9869 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9870 (set (match_operand:SI 4 "gpc_reg_operand" "")
9871 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9872 (set (match_operand:SI 5 "gpc_reg_operand" "")
9873 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9874 (set (match_operand:SI 6 "gpc_reg_operand" "")
9875 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9876 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9877 "*
9878 { return rs6000_output_load_multiple (operands); }"
9879 [(set_attr "type" "load_ux")
9880 (set_attr "length" "32")])
9882 (define_insn "*ldmsi4"
9883 [(match_parallel 0 "load_multiple_operation"
9884 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9885 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9886 (set (match_operand:SI 3 "gpc_reg_operand" "")
9887 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9888 (set (match_operand:SI 4 "gpc_reg_operand" "")
9889 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9890 (set (match_operand:SI 5 "gpc_reg_operand" "")
9891 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9892 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9893 "*
9894 { return rs6000_output_load_multiple (operands); }"
9895 [(set_attr "type" "load_ux")
9896 (set_attr "length" "32")])
9898 (define_insn "*ldmsi3"
9899 [(match_parallel 0 "load_multiple_operation"
9900 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9901 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9902 (set (match_operand:SI 3 "gpc_reg_operand" "")
9903 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9904 (set (match_operand:SI 4 "gpc_reg_operand" "")
9905 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9906 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9907 "*
9908 { return rs6000_output_load_multiple (operands); }"
9909 [(set_attr "type" "load_ux")
9910 (set_attr "length" "32")])
9912 (define_expand "store_multiple"
9913 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9914 (match_operand:SI 1 "" ""))
9915 (clobber (scratch:SI))
9916 (use (match_operand:SI 2 "" ""))])]
9917 "TARGET_STRING && !TARGET_POWERPC64"
9918 "
9919 {
9920 int regno;
9921 int count;
9922 rtx to;
9923 rtx op0;
9924 int i;
9926 /* Support only storing a constant number of fixed-point registers to
9927 memory and only bother with this if more than two; the machine
9928 doesn't support more than eight. */
9929 if (GET_CODE (operands[2]) != CONST_INT
9930 || INTVAL (operands[2]) <= 2
9931 || INTVAL (operands[2]) > 8
9932 || GET_CODE (operands[0]) != MEM
9933 || GET_CODE (operands[1]) != REG
9934 || REGNO (operands[1]) >= 32)
9935 FAIL;
9937 count = INTVAL (operands[2]);
9938 regno = REGNO (operands[1]);
9940 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9941 to = force_reg (SImode, XEXP (operands[0], 0));
9942 op0 = replace_equiv_address (operands[0], to);
9944 XVECEXP (operands[3], 0, 0)
9945 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9946 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9947 gen_rtx_SCRATCH (SImode));
9949 for (i = 1; i < count; i++)
9950 XVECEXP (operands[3], 0, i + 1)
9951 = gen_rtx_SET (VOIDmode,
9952 adjust_address_nv (op0, SImode, i * 4),
9953 gen_rtx_REG (SImode, regno + i));
9954 }")
9956 (define_insn "*stmsi8"
9957 [(match_parallel 0 "store_multiple_operation"
9958 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9959 (match_operand:SI 2 "gpc_reg_operand" "r"))
9960 (clobber (match_scratch:SI 3 "=X"))
9961 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9962 (match_operand:SI 4 "gpc_reg_operand" "r"))
9963 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9964 (match_operand:SI 5 "gpc_reg_operand" "r"))
9965 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9966 (match_operand:SI 6 "gpc_reg_operand" "r"))
9967 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9968 (match_operand:SI 7 "gpc_reg_operand" "r"))
9969 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9970 (match_operand:SI 8 "gpc_reg_operand" "r"))
9971 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9972 (match_operand:SI 9 "gpc_reg_operand" "r"))
9973 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9974 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9975 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9976 "{stsi|stswi} %2,%1,%O0"
9977 [(set_attr "type" "store_ux")
9978 (set_attr "cell_micro" "always")])
9980 (define_insn "*stmsi7"
9981 [(match_parallel 0 "store_multiple_operation"
9982 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9983 (match_operand:SI 2 "gpc_reg_operand" "r"))
9984 (clobber (match_scratch:SI 3 "=X"))
9985 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9986 (match_operand:SI 4 "gpc_reg_operand" "r"))
9987 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9988 (match_operand:SI 5 "gpc_reg_operand" "r"))
9989 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9990 (match_operand:SI 6 "gpc_reg_operand" "r"))
9991 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9992 (match_operand:SI 7 "gpc_reg_operand" "r"))
9993 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9994 (match_operand:SI 8 "gpc_reg_operand" "r"))
9995 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9996 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9997 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9998 "{stsi|stswi} %2,%1,%O0"
9999 [(set_attr "type" "store_ux")
10000 (set_attr "cell_micro" "always")])
10002 (define_insn "*stmsi6"
10003 [(match_parallel 0 "store_multiple_operation"
10004 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10005 (match_operand:SI 2 "gpc_reg_operand" "r"))
10006 (clobber (match_scratch:SI 3 "=X"))
10007 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10008 (match_operand:SI 4 "gpc_reg_operand" "r"))
10009 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10010 (match_operand:SI 5 "gpc_reg_operand" "r"))
10011 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10012 (match_operand:SI 6 "gpc_reg_operand" "r"))
10013 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10014 (match_operand:SI 7 "gpc_reg_operand" "r"))
10015 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10016 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10017 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10018 "{stsi|stswi} %2,%1,%O0"
10019 [(set_attr "type" "store_ux")
10020 (set_attr "cell_micro" "always")])
10022 (define_insn "*stmsi5"
10023 [(match_parallel 0 "store_multiple_operation"
10024 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10025 (match_operand:SI 2 "gpc_reg_operand" "r"))
10026 (clobber (match_scratch:SI 3 "=X"))
10027 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10028 (match_operand:SI 4 "gpc_reg_operand" "r"))
10029 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10030 (match_operand:SI 5 "gpc_reg_operand" "r"))
10031 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10032 (match_operand:SI 6 "gpc_reg_operand" "r"))
10033 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10034 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10035 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10036 "{stsi|stswi} %2,%1,%O0"
10037 [(set_attr "type" "store_ux")
10038 (set_attr "cell_micro" "always")])
10040 (define_insn "*stmsi4"
10041 [(match_parallel 0 "store_multiple_operation"
10042 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10043 (match_operand:SI 2 "gpc_reg_operand" "r"))
10044 (clobber (match_scratch:SI 3 "=X"))
10045 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10046 (match_operand:SI 4 "gpc_reg_operand" "r"))
10047 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10048 (match_operand:SI 5 "gpc_reg_operand" "r"))
10049 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10050 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10051 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10052 "{stsi|stswi} %2,%1,%O0"
10053 [(set_attr "type" "store_ux")
10054 (set_attr "cell_micro" "always")])
10056 (define_insn "*stmsi3"
10057 [(match_parallel 0 "store_multiple_operation"
10058 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10059 (match_operand:SI 2 "gpc_reg_operand" "r"))
10060 (clobber (match_scratch:SI 3 "=X"))
10061 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10062 (match_operand:SI 4 "gpc_reg_operand" "r"))
10063 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10064 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10065 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10066 "{stsi|stswi} %2,%1,%O0"
10067 [(set_attr "type" "store_ux")
10068 (set_attr "cell_micro" "always")])
10070 (define_insn "*stmsi8_power"
10071 [(match_parallel 0 "store_multiple_operation"
10072 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10073 (match_operand:SI 2 "gpc_reg_operand" "r"))
10074 (clobber (match_scratch:SI 3 "=q"))
10075 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10076 (match_operand:SI 4 "gpc_reg_operand" "r"))
10077 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10078 (match_operand:SI 5 "gpc_reg_operand" "r"))
10079 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10080 (match_operand:SI 6 "gpc_reg_operand" "r"))
10081 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10082 (match_operand:SI 7 "gpc_reg_operand" "r"))
10083 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10084 (match_operand:SI 8 "gpc_reg_operand" "r"))
10085 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10086 (match_operand:SI 9 "gpc_reg_operand" "r"))
10087 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10088 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10089 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10090 "{stsi|stswi} %2,%1,%O0"
10091 [(set_attr "type" "store_ux")
10092 (set_attr "cell_micro" "always")])
10094 (define_insn "*stmsi7_power"
10095 [(match_parallel 0 "store_multiple_operation"
10096 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10097 (match_operand:SI 2 "gpc_reg_operand" "r"))
10098 (clobber (match_scratch:SI 3 "=q"))
10099 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10100 (match_operand:SI 4 "gpc_reg_operand" "r"))
10101 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10102 (match_operand:SI 5 "gpc_reg_operand" "r"))
10103 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10104 (match_operand:SI 6 "gpc_reg_operand" "r"))
10105 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10106 (match_operand:SI 7 "gpc_reg_operand" "r"))
10107 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10108 (match_operand:SI 8 "gpc_reg_operand" "r"))
10109 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10110 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10111 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10112 "{stsi|stswi} %2,%1,%O0"
10113 [(set_attr "type" "store_ux")
10114 (set_attr "cell_micro" "always")])
10116 (define_insn "*stmsi6_power"
10117 [(match_parallel 0 "store_multiple_operation"
10118 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10119 (match_operand:SI 2 "gpc_reg_operand" "r"))
10120 (clobber (match_scratch:SI 3 "=q"))
10121 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10122 (match_operand:SI 4 "gpc_reg_operand" "r"))
10123 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10124 (match_operand:SI 5 "gpc_reg_operand" "r"))
10125 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10126 (match_operand:SI 6 "gpc_reg_operand" "r"))
10127 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10128 (match_operand:SI 7 "gpc_reg_operand" "r"))
10129 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10130 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10131 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10132 "{stsi|stswi} %2,%1,%O0"
10133 [(set_attr "type" "store_ux")
10134 (set_attr "cell_micro" "always")])
10136 (define_insn "*stmsi5_power"
10137 [(match_parallel 0 "store_multiple_operation"
10138 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10139 (match_operand:SI 2 "gpc_reg_operand" "r"))
10140 (clobber (match_scratch:SI 3 "=q"))
10141 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10142 (match_operand:SI 4 "gpc_reg_operand" "r"))
10143 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10144 (match_operand:SI 5 "gpc_reg_operand" "r"))
10145 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10146 (match_operand:SI 6 "gpc_reg_operand" "r"))
10147 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10148 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10149 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10150 "{stsi|stswi} %2,%1,%O0"
10151 [(set_attr "type" "store_ux")
10152 (set_attr "cell_micro" "always")])
10154 (define_insn "*stmsi4_power"
10155 [(match_parallel 0 "store_multiple_operation"
10156 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10157 (match_operand:SI 2 "gpc_reg_operand" "r"))
10158 (clobber (match_scratch:SI 3 "=q"))
10159 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10160 (match_operand:SI 4 "gpc_reg_operand" "r"))
10161 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10162 (match_operand:SI 5 "gpc_reg_operand" "r"))
10163 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10164 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10165 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10166 "{stsi|stswi} %2,%1,%O0"
10167 [(set_attr "type" "store_ux")
10168 (set_attr "cell_micro" "always")])
10170 (define_insn "*stmsi3_power"
10171 [(match_parallel 0 "store_multiple_operation"
10172 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10173 (match_operand:SI 2 "gpc_reg_operand" "r"))
10174 (clobber (match_scratch:SI 3 "=q"))
10175 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10176 (match_operand:SI 4 "gpc_reg_operand" "r"))
10177 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10178 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10179 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10180 "{stsi|stswi} %2,%1,%O0"
10181 [(set_attr "type" "store_ux")
10182 (set_attr "cell_micro" "always")])
10183 \f
10184 (define_expand "setmemsi"
10185 [(parallel [(set (match_operand:BLK 0 "" "")
10186 (match_operand 2 "const_int_operand" ""))
10187 (use (match_operand:SI 1 "" ""))
10188 (use (match_operand:SI 3 "" ""))])]
10189 ""
10190 "
10191 {
10192 /* If value to set is not zero, use the library routine. */
10193 if (operands[2] != const0_rtx)
10194 FAIL;
10196 if (expand_block_clear (operands))
10197 DONE;
10198 else
10199 FAIL;
10200 }")
10202 ;; String/block move insn.
10203 ;; Argument 0 is the destination
10204 ;; Argument 1 is the source
10205 ;; Argument 2 is the length
10206 ;; Argument 3 is the alignment
10208 (define_expand "movmemsi"
10209 [(parallel [(set (match_operand:BLK 0 "" "")
10210 (match_operand:BLK 1 "" ""))
10211 (use (match_operand:SI 2 "" ""))
10212 (use (match_operand:SI 3 "" ""))])]
10213 ""
10214 "
10215 {
10216 if (expand_block_move (operands))
10217 DONE;
10218 else
10219 FAIL;
10220 }")
10222 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10223 ;; register allocator doesn't have a clue about allocating 8 word registers.
10224 ;; rD/rS = r5 is preferred, efficient form.
10225 (define_expand "movmemsi_8reg"
10226 [(parallel [(set (match_operand 0 "" "")
10227 (match_operand 1 "" ""))
10228 (use (match_operand 2 "" ""))
10229 (use (match_operand 3 "" ""))
10230 (clobber (reg:SI 5))
10231 (clobber (reg:SI 6))
10232 (clobber (reg:SI 7))
10233 (clobber (reg:SI 8))
10234 (clobber (reg:SI 9))
10235 (clobber (reg:SI 10))
10236 (clobber (reg:SI 11))
10237 (clobber (reg:SI 12))
10238 (clobber (match_scratch:SI 4 ""))])]
10239 "TARGET_STRING"
10240 "")
10242 (define_insn ""
10243 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10244 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10245 (use (match_operand:SI 2 "immediate_operand" "i"))
10246 (use (match_operand:SI 3 "immediate_operand" "i"))
10247 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10248 (clobber (reg:SI 6))
10249 (clobber (reg:SI 7))
10250 (clobber (reg:SI 8))
10251 (clobber (reg:SI 9))
10252 (clobber (reg:SI 10))
10253 (clobber (reg:SI 11))
10254 (clobber (reg:SI 12))
10255 (clobber (match_scratch:SI 5 "=q"))]
10256 "TARGET_STRING && TARGET_POWER
10257 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10258 || INTVAL (operands[2]) == 0)
10259 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10260 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10261 && REGNO (operands[4]) == 5"
10262 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10263 [(set_attr "type" "store_ux")
10264 (set_attr "cell_micro" "always")
10265 (set_attr "length" "8")])
10267 (define_insn ""
10268 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10269 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10270 (use (match_operand:SI 2 "immediate_operand" "i"))
10271 (use (match_operand:SI 3 "immediate_operand" "i"))
10272 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10273 (clobber (reg:SI 6))
10274 (clobber (reg:SI 7))
10275 (clobber (reg:SI 8))
10276 (clobber (reg:SI 9))
10277 (clobber (reg:SI 10))
10278 (clobber (reg:SI 11))
10279 (clobber (reg:SI 12))
10280 (clobber (match_scratch:SI 5 "=X"))]
10281 "TARGET_STRING && ! TARGET_POWER
10282 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10283 || INTVAL (operands[2]) == 0)
10284 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10285 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10286 && REGNO (operands[4]) == 5"
10287 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10288 [(set_attr "type" "store_ux")
10289 (set_attr "cell_micro" "always")
10290 (set_attr "length" "8")])
10292 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10293 ;; register allocator doesn't have a clue about allocating 6 word registers.
10294 ;; rD/rS = r5 is preferred, efficient form.
10295 (define_expand "movmemsi_6reg"
10296 [(parallel [(set (match_operand 0 "" "")
10297 (match_operand 1 "" ""))
10298 (use (match_operand 2 "" ""))
10299 (use (match_operand 3 "" ""))
10300 (clobber (reg:SI 5))
10301 (clobber (reg:SI 6))
10302 (clobber (reg:SI 7))
10303 (clobber (reg:SI 8))
10304 (clobber (reg:SI 9))
10305 (clobber (reg:SI 10))
10306 (clobber (match_scratch:SI 4 ""))])]
10307 "TARGET_STRING"
10308 "")
10310 (define_insn ""
10311 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10312 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10313 (use (match_operand:SI 2 "immediate_operand" "i"))
10314 (use (match_operand:SI 3 "immediate_operand" "i"))
10315 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10316 (clobber (reg:SI 6))
10317 (clobber (reg:SI 7))
10318 (clobber (reg:SI 8))
10319 (clobber (reg:SI 9))
10320 (clobber (reg:SI 10))
10321 (clobber (match_scratch:SI 5 "=q"))]
10322 "TARGET_STRING && TARGET_POWER
10323 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10324 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10325 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10326 && REGNO (operands[4]) == 5"
10327 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10328 [(set_attr "type" "store_ux")
10329 (set_attr "cell_micro" "always")
10330 (set_attr "length" "8")])
10332 (define_insn ""
10333 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10334 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10335 (use (match_operand:SI 2 "immediate_operand" "i"))
10336 (use (match_operand:SI 3 "immediate_operand" "i"))
10337 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10338 (clobber (reg:SI 6))
10339 (clobber (reg:SI 7))
10340 (clobber (reg:SI 8))
10341 (clobber (reg:SI 9))
10342 (clobber (reg:SI 10))
10343 (clobber (match_scratch:SI 5 "=X"))]
10344 "TARGET_STRING && ! TARGET_POWER
10345 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10346 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10347 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10348 && REGNO (operands[4]) == 5"
10349 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10350 [(set_attr "type" "store_ux")
10351 (set_attr "cell_micro" "always")
10352 (set_attr "length" "8")])
10354 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10355 ;; problems with TImode.
10356 ;; rD/rS = r5 is preferred, efficient form.
10357 (define_expand "movmemsi_4reg"
10358 [(parallel [(set (match_operand 0 "" "")
10359 (match_operand 1 "" ""))
10360 (use (match_operand 2 "" ""))
10361 (use (match_operand 3 "" ""))
10362 (clobber (reg:SI 5))
10363 (clobber (reg:SI 6))
10364 (clobber (reg:SI 7))
10365 (clobber (reg:SI 8))
10366 (clobber (match_scratch:SI 4 ""))])]
10367 "TARGET_STRING"
10368 "")
10370 (define_insn ""
10371 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10372 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10373 (use (match_operand:SI 2 "immediate_operand" "i"))
10374 (use (match_operand:SI 3 "immediate_operand" "i"))
10375 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10376 (clobber (reg:SI 6))
10377 (clobber (reg:SI 7))
10378 (clobber (reg:SI 8))
10379 (clobber (match_scratch:SI 5 "=q"))]
10380 "TARGET_STRING && TARGET_POWER
10381 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10382 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10383 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10384 && REGNO (operands[4]) == 5"
10385 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10386 [(set_attr "type" "store_ux")
10387 (set_attr "cell_micro" "always")
10388 (set_attr "length" "8")])
10390 (define_insn ""
10391 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10392 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10393 (use (match_operand:SI 2 "immediate_operand" "i"))
10394 (use (match_operand:SI 3 "immediate_operand" "i"))
10395 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10396 (clobber (reg:SI 6))
10397 (clobber (reg:SI 7))
10398 (clobber (reg:SI 8))
10399 (clobber (match_scratch:SI 5 "=X"))]
10400 "TARGET_STRING && ! TARGET_POWER
10401 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10402 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10403 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10404 && REGNO (operands[4]) == 5"
10405 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10406 [(set_attr "type" "store_ux")
10407 (set_attr "cell_micro" "always")
10408 (set_attr "length" "8")])
10410 ;; Move up to 8 bytes at a time.
10411 (define_expand "movmemsi_2reg"
10412 [(parallel [(set (match_operand 0 "" "")
10413 (match_operand 1 "" ""))
10414 (use (match_operand 2 "" ""))
10415 (use (match_operand 3 "" ""))
10416 (clobber (match_scratch:DI 4 ""))
10417 (clobber (match_scratch:SI 5 ""))])]
10418 "TARGET_STRING && ! TARGET_POWERPC64"
10419 "")
10421 (define_insn ""
10422 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10423 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10424 (use (match_operand:SI 2 "immediate_operand" "i"))
10425 (use (match_operand:SI 3 "immediate_operand" "i"))
10426 (clobber (match_scratch:DI 4 "=&r"))
10427 (clobber (match_scratch:SI 5 "=q"))]
10428 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10429 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10430 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10431 [(set_attr "type" "store_ux")
10432 (set_attr "cell_micro" "always")
10433 (set_attr "length" "8")])
10435 (define_insn ""
10436 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10437 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10438 (use (match_operand:SI 2 "immediate_operand" "i"))
10439 (use (match_operand:SI 3 "immediate_operand" "i"))
10440 (clobber (match_scratch:DI 4 "=&r"))
10441 (clobber (match_scratch:SI 5 "=X"))]
10442 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10443 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10444 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10445 [(set_attr "type" "store_ux")
10446 (set_attr "cell_micro" "always")
10447 (set_attr "length" "8")])
10449 ;; Move up to 4 bytes at a time.
10450 (define_expand "movmemsi_1reg"
10451 [(parallel [(set (match_operand 0 "" "")
10452 (match_operand 1 "" ""))
10453 (use (match_operand 2 "" ""))
10454 (use (match_operand 3 "" ""))
10455 (clobber (match_scratch:SI 4 ""))
10456 (clobber (match_scratch:SI 5 ""))])]
10457 "TARGET_STRING"
10458 "")
10460 (define_insn ""
10461 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10462 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10463 (use (match_operand:SI 2 "immediate_operand" "i"))
10464 (use (match_operand:SI 3 "immediate_operand" "i"))
10465 (clobber (match_scratch:SI 4 "=&r"))
10466 (clobber (match_scratch:SI 5 "=q"))]
10467 "TARGET_STRING && TARGET_POWER
10468 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10469 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10470 [(set_attr "type" "store_ux")
10471 (set_attr "cell_micro" "always")
10472 (set_attr "length" "8")])
10474 (define_insn ""
10475 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10476 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10477 (use (match_operand:SI 2 "immediate_operand" "i"))
10478 (use (match_operand:SI 3 "immediate_operand" "i"))
10479 (clobber (match_scratch:SI 4 "=&r"))
10480 (clobber (match_scratch:SI 5 "=X"))]
10481 "TARGET_STRING && ! TARGET_POWER
10482 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10483 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10484 [(set_attr "type" "store_ux")
10485 (set_attr "cell_micro" "always")
10486 (set_attr "length" "8")])
10487 \f
10488 ;; Define insns that do load or store with update. Some of these we can
10489 ;; get by using pre-decrement or pre-increment, but the hardware can also
10490 ;; do cases where the increment is not the size of the object.
10491 ;;
10492 ;; In all these cases, we use operands 0 and 1 for the register being
10493 ;; incremented because those are the operands that local-alloc will
10494 ;; tie and these are the pair most likely to be tieable (and the ones
10495 ;; that will benefit the most).
10497 (define_insn "*movdi_update1"
10498 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10499 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10500 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10501 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10502 (plus:DI (match_dup 1) (match_dup 2)))]
10503 "TARGET_POWERPC64 && TARGET_UPDATE
10504 && (!avoiding_indexed_address_p (DImode)
10505 || !gpc_reg_operand (operands[2], DImode))"
10506 "@
10507 ldux %3,%0,%2
10508 ldu %3,%2(%0)"
10509 [(set_attr "type" "load_ux,load_u")])
10511 (define_insn "movdi_<mode>_update"
10512 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10513 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10514 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10515 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10516 (plus:P (match_dup 1) (match_dup 2)))]
10517 "TARGET_POWERPC64 && TARGET_UPDATE
10518 && (!avoiding_indexed_address_p (Pmode)
10519 || !gpc_reg_operand (operands[2], Pmode)
10520 || (REG_P (operands[0])
10521 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10522 "@
10523 stdux %3,%0,%2
10524 stdu %3,%2(%0)"
10525 [(set_attr "type" "store_ux,store_u")])
10527 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10528 ;; needed for stack allocation, even if the user passes -mno-update.
10529 (define_insn "movdi_<mode>_update_stack"
10530 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10531 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10532 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10533 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10534 (plus:P (match_dup 1) (match_dup 2)))]
10535 "TARGET_POWERPC64"
10536 "@
10537 stdux %3,%0,%2
10538 stdu %3,%2(%0)"
10539 [(set_attr "type" "store_ux,store_u")])
10541 (define_insn "*movsi_update1"
10542 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10543 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10544 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10545 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10546 (plus:SI (match_dup 1) (match_dup 2)))]
10547 "TARGET_UPDATE
10548 && (!avoiding_indexed_address_p (SImode)
10549 || !gpc_reg_operand (operands[2], SImode))"
10550 "@
10551 {lux|lwzux} %3,%0,%2
10552 {lu|lwzu} %3,%2(%0)"
10553 [(set_attr "type" "load_ux,load_u")])
10555 (define_insn "*movsi_update2"
10556 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10557 (sign_extend:DI
10558 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10559 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10560 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10561 (plus:DI (match_dup 1) (match_dup 2)))]
10562 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10563 && !avoiding_indexed_address_p (DImode)"
10564 "lwaux %3,%0,%2"
10565 [(set_attr "type" "load_ext_ux")])
10567 (define_insn "movsi_update"
10568 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10569 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10570 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10571 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10572 (plus:SI (match_dup 1) (match_dup 2)))]
10573 "TARGET_UPDATE
10574 && (!avoiding_indexed_address_p (SImode)
10575 || !gpc_reg_operand (operands[2], SImode)
10576 || (REG_P (operands[0])
10577 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10578 "@
10579 {stux|stwux} %3,%0,%2
10580 {stu|stwu} %3,%2(%0)"
10581 [(set_attr "type" "store_ux,store_u")])
10583 ;; This is an unconditional pattern; needed for stack allocation, even
10584 ;; if the user passes -mno-update.
10585 (define_insn "movsi_update_stack"
10586 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10587 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10588 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10589 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10590 (plus:SI (match_dup 1) (match_dup 2)))]
10591 ""
10592 "@
10593 {stux|stwux} %3,%0,%2
10594 {stu|stwu} %3,%2(%0)"
10595 [(set_attr "type" "store_ux,store_u")])
10597 (define_insn "*movhi_update1"
10598 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10599 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10600 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10601 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10602 (plus:SI (match_dup 1) (match_dup 2)))]
10603 "TARGET_UPDATE
10604 && (!avoiding_indexed_address_p (SImode)
10605 || !gpc_reg_operand (operands[2], SImode))"
10606 "@
10607 lhzux %3,%0,%2
10608 lhzu %3,%2(%0)"
10609 [(set_attr "type" "load_ux,load_u")])
10611 (define_insn "*movhi_update2"
10612 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10613 (zero_extend:SI
10614 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10615 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10616 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10617 (plus:SI (match_dup 1) (match_dup 2)))]
10618 "TARGET_UPDATE
10619 && (!avoiding_indexed_address_p (SImode)
10620 || !gpc_reg_operand (operands[2], SImode))"
10621 "@
10622 lhzux %3,%0,%2
10623 lhzu %3,%2(%0)"
10624 [(set_attr "type" "load_ux,load_u")])
10626 (define_insn "*movhi_update3"
10627 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10628 (sign_extend:SI
10629 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10630 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10631 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10632 (plus:SI (match_dup 1) (match_dup 2)))]
10633 "TARGET_UPDATE && rs6000_gen_cell_microcode
10634 && (!avoiding_indexed_address_p (SImode)
10635 || !gpc_reg_operand (operands[2], SImode))"
10636 "@
10637 lhaux %3,%0,%2
10638 lhau %3,%2(%0)"
10639 [(set_attr "type" "load_ext_ux,load_ext_u")])
10641 (define_insn "*movhi_update4"
10642 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10643 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10644 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10645 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10646 (plus:SI (match_dup 1) (match_dup 2)))]
10647 "TARGET_UPDATE
10648 && (!avoiding_indexed_address_p (SImode)
10649 || !gpc_reg_operand (operands[2], SImode))"
10650 "@
10651 sthux %3,%0,%2
10652 sthu %3,%2(%0)"
10653 [(set_attr "type" "store_ux,store_u")])
10655 (define_insn "*movqi_update1"
10656 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10657 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10658 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10659 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10660 (plus:SI (match_dup 1) (match_dup 2)))]
10661 "TARGET_UPDATE
10662 && (!avoiding_indexed_address_p (SImode)
10663 || !gpc_reg_operand (operands[2], SImode))"
10664 "@
10665 lbzux %3,%0,%2
10666 lbzu %3,%2(%0)"
10667 [(set_attr "type" "load_ux,load_u")])
10669 (define_insn "*movqi_update2"
10670 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10671 (zero_extend:SI
10672 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10673 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10674 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10675 (plus:SI (match_dup 1) (match_dup 2)))]
10676 "TARGET_UPDATE
10677 && (!avoiding_indexed_address_p (SImode)
10678 || !gpc_reg_operand (operands[2], SImode))"
10679 "@
10680 lbzux %3,%0,%2
10681 lbzu %3,%2(%0)"
10682 [(set_attr "type" "load_ux,load_u")])
10684 (define_insn "*movqi_update3"
10685 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10686 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10687 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10688 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10689 (plus:SI (match_dup 1) (match_dup 2)))]
10690 "TARGET_UPDATE
10691 && (!avoiding_indexed_address_p (SImode)
10692 || !gpc_reg_operand (operands[2], SImode))"
10693 "@
10694 stbux %3,%0,%2
10695 stbu %3,%2(%0)"
10696 [(set_attr "type" "store_ux,store_u")])
10698 (define_insn "*movsf_update1"
10699 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10700 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10701 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10702 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10703 (plus:SI (match_dup 1) (match_dup 2)))]
10704 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10705 && (!avoiding_indexed_address_p (SImode)
10706 || !gpc_reg_operand (operands[2], SImode))"
10707 "@
10708 lfsux %3,%0,%2
10709 lfsu %3,%2(%0)"
10710 [(set_attr "type" "fpload_ux,fpload_u")])
10712 (define_insn "*movsf_update2"
10713 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10714 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10715 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10716 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10717 (plus:SI (match_dup 1) (match_dup 2)))]
10718 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10719 && (!avoiding_indexed_address_p (SImode)
10720 || !gpc_reg_operand (operands[2], SImode))"
10721 "@
10722 stfsux %3,%0,%2
10723 stfsu %3,%2(%0)"
10724 [(set_attr "type" "fpstore_ux,fpstore_u")])
10726 (define_insn "*movsf_update3"
10727 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10728 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10729 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10730 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10731 (plus:SI (match_dup 1) (match_dup 2)))]
10732 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10733 && (!avoiding_indexed_address_p (SImode)
10734 || !gpc_reg_operand (operands[2], SImode))"
10735 "@
10736 {lux|lwzux} %3,%0,%2
10737 {lu|lwzu} %3,%2(%0)"
10738 [(set_attr "type" "load_ux,load_u")])
10740 (define_insn "*movsf_update4"
10741 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10742 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10743 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10744 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10745 (plus:SI (match_dup 1) (match_dup 2)))]
10746 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10747 && (!avoiding_indexed_address_p (SImode)
10748 || !gpc_reg_operand (operands[2], SImode))"
10749 "@
10750 {stux|stwux} %3,%0,%2
10751 {stu|stwu} %3,%2(%0)"
10752 [(set_attr "type" "store_ux,store_u")])
10754 (define_insn "*movdf_update1"
10755 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10756 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10757 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10758 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10759 (plus:SI (match_dup 1) (match_dup 2)))]
10760 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10761 && (!avoiding_indexed_address_p (SImode)
10762 || !gpc_reg_operand (operands[2], SImode))"
10763 "@
10764 lfdux %3,%0,%2
10765 lfdu %3,%2(%0)"
10766 [(set_attr "type" "fpload_ux,fpload_u")])
10768 (define_insn "*movdf_update2"
10769 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10770 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10771 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10772 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10773 (plus:SI (match_dup 1) (match_dup 2)))]
10774 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10775 && (!avoiding_indexed_address_p (SImode)
10776 || !gpc_reg_operand (operands[2], SImode))"
10777 "@
10778 stfdux %3,%0,%2
10779 stfdu %3,%2(%0)"
10780 [(set_attr "type" "fpstore_ux,fpstore_u")])
10782 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10784 (define_insn "*lfq_power2"
10785 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10786 (match_operand:V2DF 1 "memory_operand" ""))]
10787 "TARGET_POWER2
10788 && TARGET_HARD_FLOAT && TARGET_FPRS"
10789 "lfq%U1%X1 %0,%1")
10791 (define_peephole2
10792 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10793 (match_operand:DF 1 "memory_operand" ""))
10794 (set (match_operand:DF 2 "gpc_reg_operand" "")
10795 (match_operand:DF 3 "memory_operand" ""))]
10796 "TARGET_POWER2
10797 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10798 && registers_ok_for_quad_peep (operands[0], operands[2])
10799 && mems_ok_for_quad_peep (operands[1], operands[3])"
10800 [(set (match_dup 0)
10801 (match_dup 1))]
10802 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10803 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10805 (define_insn "*stfq_power2"
10806 [(set (match_operand:V2DF 0 "memory_operand" "")
10807 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10808 "TARGET_POWER2
10809 && TARGET_HARD_FLOAT && TARGET_FPRS"
10810 "stfq%U0%X0 %1,%0")
10813 (define_peephole2
10814 [(set (match_operand:DF 0 "memory_operand" "")
10815 (match_operand:DF 1 "gpc_reg_operand" ""))
10816 (set (match_operand:DF 2 "memory_operand" "")
10817 (match_operand:DF 3 "gpc_reg_operand" ""))]
10818 "TARGET_POWER2
10819 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10820 && registers_ok_for_quad_peep (operands[1], operands[3])
10821 && mems_ok_for_quad_peep (operands[0], operands[2])"
10822 [(set (match_dup 0)
10823 (match_dup 1))]
10824 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10825 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10827 ;; After inserting conditional returns we can sometimes have
10828 ;; unnecessary register moves. Unfortunately we cannot have a
10829 ;; modeless peephole here, because some single SImode sets have early
10830 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10831 ;; sequences, using get_attr_length here will smash the operands
10832 ;; array. Neither is there an early_cobbler_p predicate.
10833 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10834 (define_peephole2
10835 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10836 (match_operand:DF 1 "any_operand" ""))
10837 (set (match_operand:DF 2 "gpc_reg_operand" "")
10838 (match_dup 0))]
10839 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10840 && peep2_reg_dead_p (2, operands[0])"
10841 [(set (match_dup 2) (match_dup 1))])
10843 (define_peephole2
10844 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10845 (match_operand:SF 1 "any_operand" ""))
10846 (set (match_operand:SF 2 "gpc_reg_operand" "")
10847 (match_dup 0))]
10848 "peep2_reg_dead_p (2, operands[0])"
10849 [(set (match_dup 2) (match_dup 1))])
10851 \f
10852 ;; TLS support.
10854 ;; Mode attributes for different ABIs.
10855 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10856 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10857 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10858 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10860 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10861 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10862 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10863 (match_operand 4 "" "g")))
10864 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10865 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10866 UNSPEC_TLSGD)
10867 (clobber (reg:SI LR_REGNO))]
10868 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10869 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10870 "&& TARGET_TLS_MARKERS"
10871 [(set (match_dup 0)
10872 (unspec:TLSmode [(match_dup 1)
10873 (match_dup 2)]
10874 UNSPEC_TLSGD))
10875 (parallel [(set (match_dup 0)
10876 (call (mem:TLSmode (match_dup 3))
10877 (match_dup 4)))
10878 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10879 (clobber (reg:SI LR_REGNO))])]
10880 ""
10881 [(set_attr "type" "two")
10882 (set_attr "length" "12")])
10884 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10885 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10886 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10887 (match_operand 4 "" "g")))
10888 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10889 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10890 UNSPEC_TLSGD)
10891 (clobber (reg:SI LR_REGNO))]
10892 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10893 {
10894 if (flag_pic)
10895 {
10896 if (TARGET_SECURE_PLT && flag_pic == 2)
10897 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10898 else
10899 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10900 }
10901 else
10902 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10903 }
10904 "&& TARGET_TLS_MARKERS"
10905 [(set (match_dup 0)
10906 (unspec:TLSmode [(match_dup 1)
10907 (match_dup 2)]
10908 UNSPEC_TLSGD))
10909 (parallel [(set (match_dup 0)
10910 (call (mem:TLSmode (match_dup 3))
10911 (match_dup 4)))
10912 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10913 (clobber (reg:SI LR_REGNO))])]
10914 ""
10915 [(set_attr "type" "two")
10916 (set_attr "length" "8")])
10918 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
10919 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10920 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10921 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10922 UNSPEC_TLSGD))]
10923 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10924 "addi %0,%1,%2@got@tlsgd"
10925 [(set_attr "length" "4")])
10927 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10928 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10929 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10930 (match_operand 2 "" "g")))
10931 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10932 UNSPEC_TLSGD)
10933 (clobber (reg:SI LR_REGNO))]
10934 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10935 "bl %z1(%3@tlsgd)\;%."
10936 [(set_attr "type" "branch")
10937 (set_attr "length" "8")])
10939 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10940 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10941 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10942 (match_operand 2 "" "g")))
10943 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10944 UNSPEC_TLSGD)
10945 (clobber (reg:SI LR_REGNO))]
10946 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10947 {
10948 if (flag_pic)
10949 {
10950 if (TARGET_SECURE_PLT && flag_pic == 2)
10951 return "bl %z1+32768(%3@tlsgd)@plt";
10952 return "bl %z1(%3@tlsgd)@plt";
10953 }
10954 return "bl %z1(%3@tlsgd)";
10955 }
10956 [(set_attr "type" "branch")
10957 (set_attr "length" "4")])
10959 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10960 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10961 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10962 (match_operand 3 "" "g")))
10963 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10964 UNSPEC_TLSLD)
10965 (clobber (reg:SI LR_REGNO))]
10966 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10967 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10968 "&& TARGET_TLS_MARKERS"
10969 [(set (match_dup 0)
10970 (unspec:TLSmode [(match_dup 1)]
10971 UNSPEC_TLSLD))
10972 (parallel [(set (match_dup 0)
10973 (call (mem:TLSmode (match_dup 2))
10974 (match_dup 3)))
10975 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10976 (clobber (reg:SI LR_REGNO))])]
10977 ""
10978 [(set_attr "length" "12")])
10980 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10981 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10982 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10983 (match_operand 3 "" "g")))
10984 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10985 UNSPEC_TLSLD)
10986 (clobber (reg:SI LR_REGNO))]
10987 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10988 {
10989 if (flag_pic)
10990 {
10991 if (TARGET_SECURE_PLT && flag_pic == 2)
10992 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10993 else
10994 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10995 }
10996 else
10997 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10998 }
10999 "&& TARGET_TLS_MARKERS"
11000 [(set (match_dup 0)
11001 (unspec:TLSmode [(match_dup 1)]
11002 UNSPEC_TLSLD))
11003 (parallel [(set (match_dup 0)
11004 (call (mem:TLSmode (match_dup 2))
11005 (match_dup 3)))
11006 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11007 (clobber (reg:SI LR_REGNO))])]
11008 ""
11009 [(set_attr "length" "8")])
11011 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11012 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11013 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11014 UNSPEC_TLSLD))]
11015 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11016 "addi %0,%1,%&@got@tlsld"
11017 [(set_attr "length" "4")])
11019 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11020 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11021 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11022 (match_operand 2 "" "g")))
11023 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11024 (clobber (reg:SI LR_REGNO))]
11025 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11026 "bl %z1(%&@tlsld)\;%."
11027 [(set_attr "type" "branch")
11028 (set_attr "length" "8")])
11030 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11031 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11032 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11033 (match_operand 2 "" "g")))
11034 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11035 (clobber (reg:SI LR_REGNO))]
11036 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11037 {
11038 if (flag_pic)
11039 {
11040 if (TARGET_SECURE_PLT && flag_pic == 2)
11041 return "bl %z1+32768(%&@tlsld)@plt";
11042 return "bl %z1(%&@tlsld)@plt";
11043 }
11044 return "bl %z1(%&@tlsld)";
11045 }
11046 [(set_attr "type" "branch")
11047 (set_attr "length" "4")])
11049 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11050 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11051 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11052 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11053 UNSPEC_TLSDTPREL))]
11054 "HAVE_AS_TLS"
11055 "addi %0,%1,%2@dtprel")
11057 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11058 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11059 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11060 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11061 UNSPEC_TLSDTPRELHA))]
11062 "HAVE_AS_TLS"
11063 "addis %0,%1,%2@dtprel@ha")
11065 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11066 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11067 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11068 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11069 UNSPEC_TLSDTPRELLO))]
11070 "HAVE_AS_TLS"
11071 "addi %0,%1,%2@dtprel@l")
11073 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11074 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11075 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11076 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11077 UNSPEC_TLSGOTDTPREL))]
11078 "HAVE_AS_TLS"
11079 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
11081 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11082 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11083 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11084 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11085 UNSPEC_TLSTPREL))]
11086 "HAVE_AS_TLS"
11087 "addi %0,%1,%2@tprel")
11089 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11090 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11091 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11092 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11093 UNSPEC_TLSTPRELHA))]
11094 "HAVE_AS_TLS"
11095 "addis %0,%1,%2@tprel@ha")
11097 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11098 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11099 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11100 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11101 UNSPEC_TLSTPRELLO))]
11102 "HAVE_AS_TLS"
11103 "addi %0,%1,%2@tprel@l")
11105 ;; "b" output constraint here and on tls_tls input to support linker tls
11106 ;; optimization. The linker may edit the instructions emitted by a
11107 ;; tls_got_tprel/tls_tls pair to addis,addi.
11108 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11109 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11110 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11111 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11112 UNSPEC_TLSGOTTPREL))]
11113 "HAVE_AS_TLS"
11114 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
11116 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11117 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11118 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11119 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11120 UNSPEC_TLSTLS))]
11121 "HAVE_AS_TLS"
11122 "add %0,%1,%2@tls")
11124 \f
11125 ;; Next come insns related to the calling sequence.
11126 ;;
11127 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11128 ;; We move the back-chain and decrement the stack pointer.
11130 (define_expand "allocate_stack"
11131 [(set (match_operand 0 "gpc_reg_operand" "")
11132 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11133 (set (reg 1)
11134 (minus (reg 1) (match_dup 1)))]
11135 ""
11136 "
11137 { rtx chain = gen_reg_rtx (Pmode);
11138 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11139 rtx neg_op0;
11140 rtx insn, par, set, mem;
11142 emit_move_insn (chain, stack_bot);
11144 /* Check stack bounds if necessary. */
11145 if (crtl->limit_stack)
11146 {
11147 rtx available;
11148 available = expand_binop (Pmode, sub_optab,
11149 stack_pointer_rtx, stack_limit_rtx,
11150 NULL_RTX, 1, OPTAB_WIDEN);
11151 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11152 }
11154 if (GET_CODE (operands[1]) != CONST_INT
11155 || INTVAL (operands[1]) < -32767
11156 || INTVAL (operands[1]) > 32768)
11157 {
11158 neg_op0 = gen_reg_rtx (Pmode);
11159 if (TARGET_32BIT)
11160 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11161 else
11162 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11163 }
11164 else
11165 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11167 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11168 : gen_movdi_di_update_stack))
11169 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11170 chain));
11171 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11172 it now and set the alias set/attributes. The above gen_*_update
11173 calls will generate a PARALLEL with the MEM set being the first
11174 operation. */
11175 par = PATTERN (insn);
11176 gcc_assert (GET_CODE (par) == PARALLEL);
11177 set = XVECEXP (par, 0, 0);
11178 gcc_assert (GET_CODE (set) == SET);
11179 mem = SET_DEST (set);
11180 gcc_assert (MEM_P (mem));
11181 MEM_NOTRAP_P (mem) = 1;
11182 set_mem_alias_set (mem, get_frame_alias_set ());
11184 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11185 DONE;
11186 }")
11188 ;; These patterns say how to save and restore the stack pointer. We need not
11189 ;; save the stack pointer at function level since we are careful to
11190 ;; preserve the backchain. At block level, we have to restore the backchain
11191 ;; when we restore the stack pointer.
11192 ;;
11193 ;; For nonlocal gotos, we must save both the stack pointer and its
11194 ;; backchain and restore both. Note that in the nonlocal case, the
11195 ;; save area is a memory location.
11197 (define_expand "save_stack_function"
11198 [(match_operand 0 "any_operand" "")
11199 (match_operand 1 "any_operand" "")]
11200 ""
11201 "DONE;")
11203 (define_expand "restore_stack_function"
11204 [(match_operand 0 "any_operand" "")
11205 (match_operand 1 "any_operand" "")]
11206 ""
11207 "DONE;")
11209 ;; Adjust stack pointer (op0) to a new value (op1).
11210 ;; First copy old stack backchain to new location, and ensure that the
11211 ;; scheduler won't reorder the sp assignment before the backchain write.
11212 (define_expand "restore_stack_block"
11213 [(set (match_dup 2) (match_dup 3))
11214 (set (match_dup 4) (match_dup 2))
11215 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11216 (set (match_operand 0 "register_operand" "")
11217 (match_operand 1 "register_operand" ""))]
11218 ""
11219 "
11220 {
11221 operands[1] = force_reg (Pmode, operands[1]);
11222 operands[2] = gen_reg_rtx (Pmode);
11223 operands[3] = gen_frame_mem (Pmode, operands[0]);
11224 operands[4] = gen_frame_mem (Pmode, operands[1]);
11225 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11226 }")
11228 (define_expand "save_stack_nonlocal"
11229 [(set (match_dup 3) (match_dup 4))
11230 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11231 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11232 ""
11233 "
11234 {
11235 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11237 /* Copy the backchain to the first word, sp to the second. */
11238 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11239 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11240 operands[3] = gen_reg_rtx (Pmode);
11241 operands[4] = gen_frame_mem (Pmode, operands[1]);
11242 }")
11244 (define_expand "restore_stack_nonlocal"
11245 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11246 (set (match_dup 3) (match_dup 4))
11247 (set (match_dup 5) (match_dup 2))
11248 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11249 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11250 ""
11251 "
11252 {
11253 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11255 /* Restore the backchain from the first word, sp from the second. */
11256 operands[2] = gen_reg_rtx (Pmode);
11257 operands[3] = gen_reg_rtx (Pmode);
11258 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11259 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11260 operands[5] = gen_frame_mem (Pmode, operands[3]);
11261 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11262 }")
11263 \f
11264 ;; TOC register handling.
11266 ;; Code to initialize the TOC register...
11268 (define_insn "load_toc_aix_si"
11269 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11270 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11271 (use (reg:SI 2))])]
11272 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11273 "*
11274 {
11275 char buf[30];
11276 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11277 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11278 operands[2] = gen_rtx_REG (Pmode, 2);
11279 return \"{l|lwz} %0,%1(%2)\";
11280 }"
11281 [(set_attr "type" "load")])
11283 (define_insn "load_toc_aix_di"
11284 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11285 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11286 (use (reg:DI 2))])]
11287 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11288 "*
11289 {
11290 char buf[30];
11291 #ifdef TARGET_RELOCATABLE
11292 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11293 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11294 #else
11295 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11296 #endif
11297 if (TARGET_ELF)
11298 strcat (buf, \"@toc\");
11299 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11300 operands[2] = gen_rtx_REG (Pmode, 2);
11301 return \"ld %0,%1(%2)\";
11302 }"
11303 [(set_attr "type" "load")])
11305 (define_insn "load_toc_v4_pic_si"
11306 [(set (reg:SI LR_REGNO)
11307 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11308 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11309 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11310 [(set_attr "type" "branch")
11311 (set_attr "length" "4")])
11313 (define_insn "load_toc_v4_PIC_1"
11314 [(set (reg:SI LR_REGNO)
11315 (match_operand:SI 0 "immediate_operand" "s"))
11316 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11317 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11318 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11319 "bcl 20,31,%0\\n%0:"
11320 [(set_attr "type" "branch")
11321 (set_attr "length" "4")])
11323 (define_insn "load_toc_v4_PIC_1b"
11324 [(set (reg:SI LR_REGNO)
11325 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
11326 UNSPEC_TOCPTR))]
11327 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11328 "bcl 20,31,$+8\\n\\t.long %0-$"
11329 [(set_attr "type" "branch")
11330 (set_attr "length" "8")])
11332 (define_insn "load_toc_v4_PIC_2"
11333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11334 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11335 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11336 (match_operand:SI 3 "immediate_operand" "s")))))]
11337 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11338 "{l|lwz} %0,%2-%3(%1)"
11339 [(set_attr "type" "load")])
11341 (define_insn "load_toc_v4_PIC_3b"
11342 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11343 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11344 (high:SI
11345 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11346 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11347 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11348 "{cau|addis} %0,%1,%2-%3@ha")
11350 (define_insn "load_toc_v4_PIC_3c"
11351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11352 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11353 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11354 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11355 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11356 "{cal|addi} %0,%1,%2-%3@l")
11358 ;; If the TOC is shared over a translation unit, as happens with all
11359 ;; the kinds of PIC that we support, we need to restore the TOC
11360 ;; pointer only when jumping over units of translation.
11361 ;; On Darwin, we need to reload the picbase.
11363 (define_expand "builtin_setjmp_receiver"
11364 [(use (label_ref (match_operand 0 "" "")))]
11365 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11366 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11367 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11368 "
11369 {
11370 #if TARGET_MACHO
11371 if (DEFAULT_ABI == ABI_DARWIN)
11372 {
11373 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11374 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11375 rtx tmplabrtx;
11376 char tmplab[20];
11378 crtl->uses_pic_offset_table = 1;
11379 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11380 CODE_LABEL_NUMBER (operands[0]));
11381 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11383 emit_insn (gen_load_macho_picbase (tmplabrtx));
11384 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11385 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11386 }
11387 else
11388 #endif
11389 rs6000_emit_load_toc_table (FALSE);
11390 DONE;
11391 }")
11393 ;; Elf specific ways of loading addresses for non-PIC code.
11394 ;; The output of this could be r0, but we make a very strong
11395 ;; preference for a base register because it will usually
11396 ;; be needed there.
11397 (define_insn "elf_high"
11398 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11399 (high:SI (match_operand 1 "" "")))]
11400 "TARGET_ELF && ! TARGET_64BIT"
11401 "{liu|lis} %0,%1@ha")
11403 (define_insn "elf_low"
11404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11405 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11406 (match_operand 2 "" "")))]
11407 "TARGET_ELF && ! TARGET_64BIT"
11408 "@
11409 {cal|la} %0,%2@l(%1)
11410 {ai|addic} %0,%1,%K2")
11411 \f
11412 ;; A function pointer under AIX is a pointer to a data area whose first word
11413 ;; contains the actual address of the function, whose second word contains a
11414 ;; pointer to its TOC, and whose third word contains a value to place in the
11415 ;; static chain register (r11). Note that if we load the static chain, our
11416 ;; "trampoline" need not have any executable code.
11418 (define_expand "call_indirect_aix32"
11419 [(set (match_dup 2)
11420 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11421 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11422 (reg:SI 2))
11423 (set (reg:SI 11)
11424 (mem:SI (plus:SI (match_dup 0)
11425 (const_int 8))))
11426 (parallel [(call (mem:SI (match_dup 2))
11427 (match_operand 1 "" ""))
11428 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11429 (use (reg:SI 11))
11430 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11431 (clobber (reg:SI LR_REGNO))])]
11432 "TARGET_32BIT"
11433 "
11434 { operands[2] = gen_reg_rtx (SImode); }")
11436 (define_expand "call_indirect_aix64"
11437 [(set (match_dup 2)
11438 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11439 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11440 (reg:DI 2))
11441 (set (reg:DI 11)
11442 (mem:DI (plus:DI (match_dup 0)
11443 (const_int 16))))
11444 (parallel [(call (mem:SI (match_dup 2))
11445 (match_operand 1 "" ""))
11446 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11447 (use (reg:DI 11))
11448 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11449 (clobber (reg:SI LR_REGNO))])]
11450 "TARGET_64BIT"
11451 "
11452 { operands[2] = gen_reg_rtx (DImode); }")
11454 (define_expand "call_value_indirect_aix32"
11455 [(set (match_dup 3)
11456 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11457 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11458 (reg:SI 2))
11459 (set (reg:SI 11)
11460 (mem:SI (plus:SI (match_dup 1)
11461 (const_int 8))))
11462 (parallel [(set (match_operand 0 "" "")
11463 (call (mem:SI (match_dup 3))
11464 (match_operand 2 "" "")))
11465 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11466 (use (reg:SI 11))
11467 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11468 (clobber (reg:SI LR_REGNO))])]
11469 "TARGET_32BIT"
11470 "
11471 { operands[3] = gen_reg_rtx (SImode); }")
11473 (define_expand "call_value_indirect_aix64"
11474 [(set (match_dup 3)
11475 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11476 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11477 (reg:DI 2))
11478 (set (reg:DI 11)
11479 (mem:DI (plus:DI (match_dup 1)
11480 (const_int 16))))
11481 (parallel [(set (match_operand 0 "" "")
11482 (call (mem:SI (match_dup 3))
11483 (match_operand 2 "" "")))
11484 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11485 (use (reg:DI 11))
11486 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11487 (clobber (reg:SI LR_REGNO))])]
11488 "TARGET_64BIT"
11489 "
11490 { operands[3] = gen_reg_rtx (DImode); }")
11492 ;; Now the definitions for the call and call_value insns
11493 (define_expand "call"
11494 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11495 (match_operand 1 "" ""))
11496 (use (match_operand 2 "" ""))
11497 (clobber (reg:SI LR_REGNO))])]
11498 ""
11499 "
11500 {
11501 #if TARGET_MACHO
11502 if (MACHOPIC_INDIRECT)
11503 operands[0] = machopic_indirect_call_target (operands[0]);
11504 #endif
11506 gcc_assert (GET_CODE (operands[0]) == MEM);
11507 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11509 operands[0] = XEXP (operands[0], 0);
11511 if (GET_CODE (operands[0]) != SYMBOL_REF
11512 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11513 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11514 {
11515 if (INTVAL (operands[2]) & CALL_LONG)
11516 operands[0] = rs6000_longcall_ref (operands[0]);
11518 switch (DEFAULT_ABI)
11519 {
11520 case ABI_V4:
11521 case ABI_DARWIN:
11522 operands[0] = force_reg (Pmode, operands[0]);
11523 break;
11525 case ABI_AIX:
11526 /* AIX function pointers are really pointers to a three word
11527 area. */
11528 emit_call_insn (TARGET_32BIT
11529 ? gen_call_indirect_aix32 (force_reg (SImode,
11530 operands[0]),
11531 operands[1])
11532 : gen_call_indirect_aix64 (force_reg (DImode,
11533 operands[0]),
11534 operands[1]));
11535 DONE;
11537 default:
11538 gcc_unreachable ();
11539 }
11540 }
11541 }")
11543 (define_expand "call_value"
11544 [(parallel [(set (match_operand 0 "" "")
11545 (call (mem:SI (match_operand 1 "address_operand" ""))
11546 (match_operand 2 "" "")))
11547 (use (match_operand 3 "" ""))
11548 (clobber (reg:SI LR_REGNO))])]
11549 ""
11550 "
11551 {
11552 #if TARGET_MACHO
11553 if (MACHOPIC_INDIRECT)
11554 operands[1] = machopic_indirect_call_target (operands[1]);
11555 #endif
11557 gcc_assert (GET_CODE (operands[1]) == MEM);
11558 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11560 operands[1] = XEXP (operands[1], 0);
11562 if (GET_CODE (operands[1]) != SYMBOL_REF
11563 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11564 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11565 {
11566 if (INTVAL (operands[3]) & CALL_LONG)
11567 operands[1] = rs6000_longcall_ref (operands[1]);
11569 switch (DEFAULT_ABI)
11570 {
11571 case ABI_V4:
11572 case ABI_DARWIN:
11573 operands[1] = force_reg (Pmode, operands[1]);
11574 break;
11576 case ABI_AIX:
11577 /* AIX function pointers are really pointers to a three word
11578 area. */
11579 emit_call_insn (TARGET_32BIT
11580 ? gen_call_value_indirect_aix32 (operands[0],
11581 force_reg (SImode,
11582 operands[1]),
11583 operands[2])
11584 : gen_call_value_indirect_aix64 (operands[0],
11585 force_reg (DImode,
11586 operands[1]),
11587 operands[2]));
11588 DONE;
11590 default:
11591 gcc_unreachable ();
11592 }
11593 }
11594 }")
11596 ;; Call to function in current module. No TOC pointer reload needed.
11597 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11598 ;; either the function was not prototyped, or it was prototyped as a
11599 ;; variable argument function. It is > 0 if FP registers were passed
11600 ;; and < 0 if they were not.
11602 (define_insn "*call_local32"
11603 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11604 (match_operand 1 "" "g,g"))
11605 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11606 (clobber (reg:SI LR_REGNO))]
11607 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11608 "*
11609 {
11610 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11611 output_asm_insn (\"crxor 6,6,6\", operands);
11613 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11614 output_asm_insn (\"creqv 6,6,6\", operands);
11616 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11617 }"
11618 [(set_attr "type" "branch")
11619 (set_attr "length" "4,8")])
11621 (define_insn "*call_local64"
11622 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11623 (match_operand 1 "" "g,g"))
11624 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11625 (clobber (reg:SI LR_REGNO))]
11626 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11627 "*
11628 {
11629 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11630 output_asm_insn (\"crxor 6,6,6\", operands);
11632 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11633 output_asm_insn (\"creqv 6,6,6\", operands);
11635 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11636 }"
11637 [(set_attr "type" "branch")
11638 (set_attr "length" "4,8")])
11640 (define_insn "*call_value_local32"
11641 [(set (match_operand 0 "" "")
11642 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11643 (match_operand 2 "" "g,g")))
11644 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11645 (clobber (reg:SI LR_REGNO))]
11646 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11647 "*
11648 {
11649 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11650 output_asm_insn (\"crxor 6,6,6\", operands);
11652 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11653 output_asm_insn (\"creqv 6,6,6\", operands);
11655 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11656 }"
11657 [(set_attr "type" "branch")
11658 (set_attr "length" "4,8")])
11661 (define_insn "*call_value_local64"
11662 [(set (match_operand 0 "" "")
11663 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11664 (match_operand 2 "" "g,g")))
11665 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11666 (clobber (reg:SI LR_REGNO))]
11667 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11668 "*
11669 {
11670 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11671 output_asm_insn (\"crxor 6,6,6\", operands);
11673 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11674 output_asm_insn (\"creqv 6,6,6\", operands);
11676 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11677 }"
11678 [(set_attr "type" "branch")
11679 (set_attr "length" "4,8")])
11681 ;; Call to function which may be in another module. Restore the TOC
11682 ;; pointer (r2) after the call unless this is System V.
11683 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11684 ;; either the function was not prototyped, or it was prototyped as a
11685 ;; variable argument function. It is > 0 if FP registers were passed
11686 ;; and < 0 if they were not.
11688 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11689 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11690 (match_operand 1 "" "g,g"))
11691 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11692 (use (reg:SI 11))
11693 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11694 (clobber (reg:SI LR_REGNO))]
11695 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11696 "#"
11697 "&& reload_completed"
11698 [(set (reg:SI 2)
11699 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11700 (parallel [(call (mem:SI (match_dup 0))
11701 (match_dup 1))
11702 (use (reg:SI 2))
11703 (use (reg:SI 11))
11704 (set (reg:SI 2)
11705 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11706 (clobber (reg:SI LR_REGNO))])]
11707 ""
11708 [(set_attr "type" "jmpreg")
11709 (set_attr "length" "12")])
11711 (define_insn "*call_indirect_nonlocal_aix32"
11712 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11713 (match_operand 1 "" "g,g"))
11714 (use (reg:SI 2))
11715 (use (reg:SI 11))
11716 (set (reg:SI 2)
11717 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11718 (clobber (reg:SI LR_REGNO))]
11719 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11720 "b%T0l\;{l|lwz} 2,20(1)"
11721 [(set_attr "type" "jmpreg")
11722 (set_attr "length" "8")])
11724 (define_insn "*call_nonlocal_aix32"
11725 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11726 (match_operand 1 "" "g"))
11727 (use (match_operand:SI 2 "immediate_operand" "O"))
11728 (clobber (reg:SI LR_REGNO))]
11729 "TARGET_32BIT
11730 && DEFAULT_ABI == ABI_AIX
11731 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11732 "bl %z0\;%."
11733 [(set_attr "type" "branch")
11734 (set_attr "length" "8")])
11736 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11737 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11738 (match_operand 1 "" "g,g"))
11739 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11740 (const_int 8))))
11741 (use (reg:DI 11))
11742 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11743 (clobber (reg:SI LR_REGNO))]
11744 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11745 "#"
11746 "&& reload_completed"
11747 [(set (reg:DI 2)
11748 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11749 (parallel [(call (mem:SI (match_dup 0))
11750 (match_dup 1))
11751 (use (reg:DI 2))
11752 (use (reg:DI 11))
11753 (set (reg:DI 2)
11754 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11755 (clobber (reg:SI LR_REGNO))])]
11756 ""
11757 [(set_attr "type" "jmpreg")
11758 (set_attr "length" "12")])
11760 (define_insn "*call_indirect_nonlocal_aix64"
11761 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11762 (match_operand 1 "" "g,g"))
11763 (use (reg:DI 2))
11764 (use (reg:DI 11))
11765 (set (reg:DI 2)
11766 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11767 (clobber (reg:SI LR_REGNO))]
11768 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11769 "b%T0l\;ld 2,40(1)"
11770 [(set_attr "type" "jmpreg")
11771 (set_attr "length" "8")])
11773 (define_insn "*call_nonlocal_aix64"
11774 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11775 (match_operand 1 "" "g"))
11776 (use (match_operand:SI 2 "immediate_operand" "O"))
11777 (clobber (reg:SI LR_REGNO))]
11778 "TARGET_64BIT
11779 && DEFAULT_ABI == ABI_AIX
11780 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11781 "bl %z0\;%."
11782 [(set_attr "type" "branch")
11783 (set_attr "length" "8")])
11785 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11786 [(set (match_operand 0 "" "")
11787 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11788 (match_operand 2 "" "g,g")))
11789 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11790 (const_int 4))))
11791 (use (reg:SI 11))
11792 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11793 (clobber (reg:SI LR_REGNO))]
11794 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11795 "#"
11796 "&& reload_completed"
11797 [(set (reg:SI 2)
11798 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11799 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11800 (match_dup 2)))
11801 (use (reg:SI 2))
11802 (use (reg:SI 11))
11803 (set (reg:SI 2)
11804 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11805 (clobber (reg:SI LR_REGNO))])]
11806 ""
11807 [(set_attr "type" "jmpreg")
11808 (set_attr "length" "12")])
11810 (define_insn "*call_value_indirect_nonlocal_aix32"
11811 [(set (match_operand 0 "" "")
11812 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11813 (match_operand 2 "" "g,g")))
11814 (use (reg:SI 2))
11815 (use (reg:SI 11))
11816 (set (reg:SI 2)
11817 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11818 (clobber (reg:SI LR_REGNO))]
11819 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11820 "b%T1l\;{l|lwz} 2,20(1)"
11821 [(set_attr "type" "jmpreg")
11822 (set_attr "length" "8")])
11824 (define_insn "*call_value_nonlocal_aix32"
11825 [(set (match_operand 0 "" "")
11826 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11827 (match_operand 2 "" "g")))
11828 (use (match_operand:SI 3 "immediate_operand" "O"))
11829 (clobber (reg:SI LR_REGNO))]
11830 "TARGET_32BIT
11831 && DEFAULT_ABI == ABI_AIX
11832 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11833 "bl %z1\;%."
11834 [(set_attr "type" "branch")
11835 (set_attr "length" "8")])
11837 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11838 [(set (match_operand 0 "" "")
11839 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11840 (match_operand 2 "" "g,g")))
11841 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11842 (const_int 8))))
11843 (use (reg:DI 11))
11844 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11845 (clobber (reg:SI LR_REGNO))]
11846 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11847 "#"
11848 "&& reload_completed"
11849 [(set (reg:DI 2)
11850 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11851 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11852 (match_dup 2)))
11853 (use (reg:DI 2))
11854 (use (reg:DI 11))
11855 (set (reg:DI 2)
11856 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11857 (clobber (reg:SI LR_REGNO))])]
11858 ""
11859 [(set_attr "type" "jmpreg")
11860 (set_attr "length" "12")])
11862 (define_insn "*call_value_indirect_nonlocal_aix64"
11863 [(set (match_operand 0 "" "")
11864 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11865 (match_operand 2 "" "g,g")))
11866 (use (reg:DI 2))
11867 (use (reg:DI 11))
11868 (set (reg:DI 2)
11869 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11870 (clobber (reg:SI LR_REGNO))]
11871 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11872 "b%T1l\;ld 2,40(1)"
11873 [(set_attr "type" "jmpreg")
11874 (set_attr "length" "8")])
11876 (define_insn "*call_value_nonlocal_aix64"
11877 [(set (match_operand 0 "" "")
11878 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11879 (match_operand 2 "" "g")))
11880 (use (match_operand:SI 3 "immediate_operand" "O"))
11881 (clobber (reg:SI LR_REGNO))]
11882 "TARGET_64BIT
11883 && DEFAULT_ABI == ABI_AIX
11884 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11885 "bl %z1\;%."
11886 [(set_attr "type" "branch")
11887 (set_attr "length" "8")])
11889 ;; A function pointer under System V is just a normal pointer
11890 ;; operands[0] is the function pointer
11891 ;; operands[1] is the stack size to clean up
11892 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11893 ;; which indicates how to set cr1
11895 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11896 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11897 (match_operand 1 "" "g,g,g,g"))
11898 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11899 (clobber (reg:SI LR_REGNO))]
11900 "DEFAULT_ABI == ABI_V4
11901 || DEFAULT_ABI == ABI_DARWIN"
11902 {
11903 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11904 output_asm_insn ("crxor 6,6,6", operands);
11906 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11907 output_asm_insn ("creqv 6,6,6", operands);
11909 return "b%T0l";
11910 }
11911 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11912 (set_attr "length" "4,4,8,8")])
11914 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11915 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11916 (match_operand 1 "" "g,g"))
11917 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11918 (clobber (reg:SI LR_REGNO))]
11919 "(DEFAULT_ABI == ABI_DARWIN
11920 || (DEFAULT_ABI == ABI_V4
11921 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11922 {
11923 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11924 output_asm_insn ("crxor 6,6,6", operands);
11926 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11927 output_asm_insn ("creqv 6,6,6", operands);
11929 #if TARGET_MACHO
11930 return output_call(insn, operands, 0, 2);
11931 #else
11932 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11933 {
11934 gcc_assert (!TARGET_SECURE_PLT);
11935 return "bl %z0@plt";
11936 }
11937 else
11938 return "bl %z0";
11939 #endif
11940 }
11941 "DEFAULT_ABI == ABI_V4
11942 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11943 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11944 [(parallel [(call (mem:SI (match_dup 0))
11945 (match_dup 1))
11946 (use (match_dup 2))
11947 (use (match_dup 3))
11948 (clobber (reg:SI LR_REGNO))])]
11949 {
11950 operands[3] = pic_offset_table_rtx;
11951 }
11952 [(set_attr "type" "branch,branch")
11953 (set_attr "length" "4,8")])
11955 (define_insn "*call_nonlocal_sysv_secure<mode>"
11956 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11957 (match_operand 1 "" "g,g"))
11958 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11959 (use (match_operand:SI 3 "register_operand" "r,r"))
11960 (clobber (reg:SI LR_REGNO))]
11961 "(DEFAULT_ABI == ABI_V4
11962 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11963 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11964 {
11965 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11966 output_asm_insn ("crxor 6,6,6", operands);
11968 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11969 output_asm_insn ("creqv 6,6,6", operands);
11971 if (flag_pic == 2)
11972 /* The magic 32768 offset here and in the other sysv call insns
11973 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11974 See sysv4.h:toc_section. */
11975 return "bl %z0+32768@plt";
11976 else
11977 return "bl %z0@plt";
11978 }
11979 [(set_attr "type" "branch,branch")
11980 (set_attr "length" "4,8")])
11982 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11983 [(set (match_operand 0 "" "")
11984 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11985 (match_operand 2 "" "g,g,g,g")))
11986 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11987 (clobber (reg:SI LR_REGNO))]
11988 "DEFAULT_ABI == ABI_V4
11989 || DEFAULT_ABI == ABI_DARWIN"
11990 {
11991 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11992 output_asm_insn ("crxor 6,6,6", operands);
11994 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11995 output_asm_insn ("creqv 6,6,6", operands);
11997 return "b%T1l";
11998 }
11999 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12000 (set_attr "length" "4,4,8,8")])
12002 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12003 [(set (match_operand 0 "" "")
12004 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12005 (match_operand 2 "" "g,g")))
12006 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12007 (clobber (reg:SI LR_REGNO))]
12008 "(DEFAULT_ABI == ABI_DARWIN
12009 || (DEFAULT_ABI == ABI_V4
12010 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12011 {
12012 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12013 output_asm_insn ("crxor 6,6,6", operands);
12015 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12016 output_asm_insn ("creqv 6,6,6", operands);
12018 #if TARGET_MACHO
12019 return output_call(insn, operands, 1, 3);
12020 #else
12021 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12022 {
12023 gcc_assert (!TARGET_SECURE_PLT);
12024 return "bl %z1@plt";
12025 }
12026 else
12027 return "bl %z1";
12028 #endif
12029 }
12030 "DEFAULT_ABI == ABI_V4
12031 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12032 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12033 [(parallel [(set (match_dup 0)
12034 (call (mem:SI (match_dup 1))
12035 (match_dup 2)))
12036 (use (match_dup 3))
12037 (use (match_dup 4))
12038 (clobber (reg:SI LR_REGNO))])]
12039 {
12040 operands[4] = pic_offset_table_rtx;
12041 }
12042 [(set_attr "type" "branch,branch")
12043 (set_attr "length" "4,8")])
12045 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12046 [(set (match_operand 0 "" "")
12047 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12048 (match_operand 2 "" "g,g")))
12049 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12050 (use (match_operand:SI 4 "register_operand" "r,r"))
12051 (clobber (reg:SI LR_REGNO))]
12052 "(DEFAULT_ABI == ABI_V4
12053 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12054 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12055 {
12056 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12057 output_asm_insn ("crxor 6,6,6", operands);
12059 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12060 output_asm_insn ("creqv 6,6,6", operands);
12062 if (flag_pic == 2)
12063 return "bl %z1+32768@plt";
12064 else
12065 return "bl %z1@plt";
12066 }
12067 [(set_attr "type" "branch,branch")
12068 (set_attr "length" "4,8")])
12070 ;; Call subroutine returning any type.
12071 (define_expand "untyped_call"
12072 [(parallel [(call (match_operand 0 "" "")
12073 (const_int 0))
12074 (match_operand 1 "" "")
12075 (match_operand 2 "" "")])]
12076 ""
12077 "
12078 {
12079 int i;
12081 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12083 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12084 {
12085 rtx set = XVECEXP (operands[2], 0, i);
12086 emit_move_insn (SET_DEST (set), SET_SRC (set));
12087 }
12089 /* The optimizer does not know that the call sets the function value
12090 registers we stored in the result block. We avoid problems by
12091 claiming that all hard registers are used and clobbered at this
12092 point. */
12093 emit_insn (gen_blockage ());
12095 DONE;
12096 }")
12098 ;; sibling call patterns
12099 (define_expand "sibcall"
12100 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12101 (match_operand 1 "" ""))
12102 (use (match_operand 2 "" ""))
12103 (use (reg:SI LR_REGNO))
12104 (return)])]
12105 ""
12106 "
12107 {
12108 #if TARGET_MACHO
12109 if (MACHOPIC_INDIRECT)
12110 operands[0] = machopic_indirect_call_target (operands[0]);
12111 #endif
12113 gcc_assert (GET_CODE (operands[0]) == MEM);
12114 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12116 operands[0] = XEXP (operands[0], 0);
12117 }")
12119 ;; this and similar patterns must be marked as using LR, otherwise
12120 ;; dataflow will try to delete the store into it. This is true
12121 ;; even when the actual reg to jump to is in CTR, when LR was
12122 ;; saved and restored around the PIC-setting BCL.
12123 (define_insn "*sibcall_local32"
12124 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12125 (match_operand 1 "" "g,g"))
12126 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12127 (use (reg:SI LR_REGNO))
12128 (return)]
12129 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12130 "*
12131 {
12132 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12133 output_asm_insn (\"crxor 6,6,6\", operands);
12135 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12136 output_asm_insn (\"creqv 6,6,6\", operands);
12138 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12139 }"
12140 [(set_attr "type" "branch")
12141 (set_attr "length" "4,8")])
12143 (define_insn "*sibcall_local64"
12144 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12145 (match_operand 1 "" "g,g"))
12146 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12147 (use (reg:SI LR_REGNO))
12148 (return)]
12149 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12150 "*
12151 {
12152 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12153 output_asm_insn (\"crxor 6,6,6\", operands);
12155 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12156 output_asm_insn (\"creqv 6,6,6\", operands);
12158 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12159 }"
12160 [(set_attr "type" "branch")
12161 (set_attr "length" "4,8")])
12163 (define_insn "*sibcall_value_local32"
12164 [(set (match_operand 0 "" "")
12165 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12166 (match_operand 2 "" "g,g")))
12167 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12168 (use (reg:SI LR_REGNO))
12169 (return)]
12170 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12171 "*
12172 {
12173 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12174 output_asm_insn (\"crxor 6,6,6\", operands);
12176 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12177 output_asm_insn (\"creqv 6,6,6\", operands);
12179 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12180 }"
12181 [(set_attr "type" "branch")
12182 (set_attr "length" "4,8")])
12185 (define_insn "*sibcall_value_local64"
12186 [(set (match_operand 0 "" "")
12187 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12188 (match_operand 2 "" "g,g")))
12189 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12190 (use (reg:SI LR_REGNO))
12191 (return)]
12192 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12193 "*
12194 {
12195 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12196 output_asm_insn (\"crxor 6,6,6\", operands);
12198 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12199 output_asm_insn (\"creqv 6,6,6\", operands);
12201 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12202 }"
12203 [(set_attr "type" "branch")
12204 (set_attr "length" "4,8")])
12206 (define_insn "*sibcall_nonlocal_aix32"
12207 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12208 (match_operand 1 "" "g"))
12209 (use (match_operand:SI 2 "immediate_operand" "O"))
12210 (use (reg:SI LR_REGNO))
12211 (return)]
12212 "TARGET_32BIT
12213 && DEFAULT_ABI == ABI_AIX
12214 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12215 "b %z0"
12216 [(set_attr "type" "branch")
12217 (set_attr "length" "4")])
12219 (define_insn "*sibcall_nonlocal_aix64"
12220 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12221 (match_operand 1 "" "g"))
12222 (use (match_operand:SI 2 "immediate_operand" "O"))
12223 (use (reg:SI LR_REGNO))
12224 (return)]
12225 "TARGET_64BIT
12226 && DEFAULT_ABI == ABI_AIX
12227 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12228 "b %z0"
12229 [(set_attr "type" "branch")
12230 (set_attr "length" "4")])
12232 (define_insn "*sibcall_value_nonlocal_aix32"
12233 [(set (match_operand 0 "" "")
12234 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12235 (match_operand 2 "" "g")))
12236 (use (match_operand:SI 3 "immediate_operand" "O"))
12237 (use (reg:SI LR_REGNO))
12238 (return)]
12239 "TARGET_32BIT
12240 && DEFAULT_ABI == ABI_AIX
12241 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12242 "b %z1"
12243 [(set_attr "type" "branch")
12244 (set_attr "length" "4")])
12246 (define_insn "*sibcall_value_nonlocal_aix64"
12247 [(set (match_operand 0 "" "")
12248 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12249 (match_operand 2 "" "g")))
12250 (use (match_operand:SI 3 "immediate_operand" "O"))
12251 (use (reg:SI LR_REGNO))
12252 (return)]
12253 "TARGET_64BIT
12254 && DEFAULT_ABI == ABI_AIX
12255 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12256 "b %z1"
12257 [(set_attr "type" "branch")
12258 (set_attr "length" "4")])
12260 (define_insn "*sibcall_nonlocal_sysv<mode>"
12261 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12262 (match_operand 1 "" ""))
12263 (use (match_operand 2 "immediate_operand" "O,n"))
12264 (use (reg:SI LR_REGNO))
12265 (return)]
12266 "(DEFAULT_ABI == ABI_DARWIN
12267 || DEFAULT_ABI == ABI_V4)
12268 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12269 "*
12270 {
12271 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12272 output_asm_insn (\"crxor 6,6,6\", operands);
12274 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12275 output_asm_insn (\"creqv 6,6,6\", operands);
12277 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12278 {
12279 gcc_assert (!TARGET_SECURE_PLT);
12280 return \"b %z0@plt\";
12281 }
12282 else
12283 return \"b %z0\";
12284 }"
12285 [(set_attr "type" "branch,branch")
12286 (set_attr "length" "4,8")])
12288 (define_expand "sibcall_value"
12289 [(parallel [(set (match_operand 0 "register_operand" "")
12290 (call (mem:SI (match_operand 1 "address_operand" ""))
12291 (match_operand 2 "" "")))
12292 (use (match_operand 3 "" ""))
12293 (use (reg:SI LR_REGNO))
12294 (return)])]
12295 ""
12296 "
12297 {
12298 #if TARGET_MACHO
12299 if (MACHOPIC_INDIRECT)
12300 operands[1] = machopic_indirect_call_target (operands[1]);
12301 #endif
12303 gcc_assert (GET_CODE (operands[1]) == MEM);
12304 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12306 operands[1] = XEXP (operands[1], 0);
12307 }")
12309 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12310 [(set (match_operand 0 "" "")
12311 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12312 (match_operand 2 "" "")))
12313 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12314 (use (reg:SI LR_REGNO))
12315 (return)]
12316 "(DEFAULT_ABI == ABI_DARWIN
12317 || DEFAULT_ABI == ABI_V4)
12318 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12319 "*
12320 {
12321 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12322 output_asm_insn (\"crxor 6,6,6\", operands);
12324 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12325 output_asm_insn (\"creqv 6,6,6\", operands);
12327 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12328 {
12329 gcc_assert (!TARGET_SECURE_PLT);
12330 return \"b %z1@plt\";
12331 }
12332 else
12333 return \"b %z1\";
12334 }"
12335 [(set_attr "type" "branch,branch")
12336 (set_attr "length" "4,8")])
12338 (define_expand "sibcall_epilogue"
12339 [(use (const_int 0))]
12340 "TARGET_SCHED_PROLOG"
12341 "
12342 {
12343 rs6000_emit_epilogue (TRUE);
12344 DONE;
12345 }")
12347 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12348 ;; all of memory. This blocks insns from being moved across this point.
12350 (define_insn "blockage"
12351 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12352 ""
12353 "")
12354 \f
12355 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12356 ;; signed & unsigned, and one type of branch.
12357 ;;
12358 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12359 ;; insns, and branches.
12361 (define_expand "cbranch<mode>4"
12362 [(use (match_operator 0 "rs6000_cbranch_operator"
12363 [(match_operand:GPR 1 "gpc_reg_operand" "")
12364 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12365 (use (match_operand 3 ""))]
12366 ""
12367 "
12368 {
12369 /* Take care of the possibility that operands[2] might be negative but
12370 this might be a logical operation. That insn doesn't exist. */
12371 if (GET_CODE (operands[2]) == CONST_INT
12372 && INTVAL (operands[2]) < 0)
12373 {
12374 operands[2] = force_reg (<MODE>mode, operands[2]);
12375 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12376 GET_MODE (operands[0]),
12377 operands[1], operands[2]);
12378 }
12380 rs6000_emit_cbranch (<MODE>mode, operands);
12381 DONE;
12382 }")
12384 (define_expand "cbranch<mode>4"
12385 [(use (match_operator 0 "rs6000_cbranch_operator"
12386 [(match_operand:FP 1 "gpc_reg_operand" "")
12387 (match_operand:FP 2 "gpc_reg_operand" "")]))
12388 (use (match_operand 3 ""))]
12389 ""
12390 "
12391 {
12392 rs6000_emit_cbranch (<MODE>mode, operands);
12393 DONE;
12394 }")
12396 (define_expand "cstore<mode>4"
12397 [(use (match_operator 1 "rs6000_cbranch_operator"
12398 [(match_operand:GPR 2 "gpc_reg_operand" "")
12399 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12400 (clobber (match_operand:SI 0 "register_operand"))]
12401 ""
12402 "
12403 {
12404 /* Take care of the possibility that operands[3] might be negative but
12405 this might be a logical operation. That insn doesn't exist. */
12406 if (GET_CODE (operands[3]) == CONST_INT
12407 && INTVAL (operands[3]) < 0)
12408 {
12409 operands[3] = force_reg (<MODE>mode, operands[3]);
12410 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12411 GET_MODE (operands[1]),
12412 operands[2], operands[3]);
12413 }
12415 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12416 For SEQ, likewise, except that comparisons with zero should be done
12417 with an scc insns. However, due to the order that combine see the
12418 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12419 the cases we don't want to handle or are best handled by portable
12420 code. */
12421 if (GET_CODE (operands[1]) == NE)
12422 FAIL;
12423 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12424 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12425 && operands[3] == const0_rtx)
12426 FAIL;
12427 rs6000_emit_sCOND (<MODE>mode, operands);
12428 DONE;
12429 }")
12431 (define_expand "cstore<mode>4"
12432 [(use (match_operator 1 "rs6000_cbranch_operator"
12433 [(match_operand:FP 2 "gpc_reg_operand" "")
12434 (match_operand:FP 3 "gpc_reg_operand" "")]))
12435 (clobber (match_operand:SI 0 "register_operand"))]
12436 ""
12437 "
12438 {
12439 rs6000_emit_sCOND (<MODE>mode, operands);
12440 DONE;
12441 }")
12444 (define_expand "stack_protect_set"
12445 [(match_operand 0 "memory_operand" "")
12446 (match_operand 1 "memory_operand" "")]
12447 ""
12448 {
12449 #ifdef TARGET_THREAD_SSP_OFFSET
12450 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12451 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12452 operands[1] = gen_rtx_MEM (Pmode, addr);
12453 #endif
12454 if (TARGET_64BIT)
12455 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12456 else
12457 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12458 DONE;
12459 })
12461 (define_insn "stack_protect_setsi"
12462 [(set (match_operand:SI 0 "memory_operand" "=m")
12463 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12464 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12465 "TARGET_32BIT"
12466 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12467 [(set_attr "type" "three")
12468 (set_attr "length" "12")])
12470 (define_insn "stack_protect_setdi"
12471 [(set (match_operand:DI 0 "memory_operand" "=m")
12472 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12473 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12474 "TARGET_64BIT"
12475 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12476 [(set_attr "type" "three")
12477 (set_attr "length" "12")])
12479 (define_expand "stack_protect_test"
12480 [(match_operand 0 "memory_operand" "")
12481 (match_operand 1 "memory_operand" "")
12482 (match_operand 2 "" "")]
12483 ""
12484 {
12485 rtx test, op0, op1;
12486 #ifdef TARGET_THREAD_SSP_OFFSET
12487 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12488 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12489 operands[1] = gen_rtx_MEM (Pmode, addr);
12490 #endif
12491 op0 = operands[0];
12492 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12493 test = gen_rtx_EQ (VOIDmode, op0, op1);
12494 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12495 DONE;
12496 })
12498 (define_insn "stack_protect_testsi"
12499 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12500 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12501 (match_operand:SI 2 "memory_operand" "m,m")]
12502 UNSPEC_SP_TEST))
12503 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12504 (clobber (match_scratch:SI 3 "=&r,&r"))]
12505 "TARGET_32BIT"
12506 "@
12507 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12508 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12509 [(set_attr "length" "16,20")])
12511 (define_insn "stack_protect_testdi"
12512 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12513 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12514 (match_operand:DI 2 "memory_operand" "m,m")]
12515 UNSPEC_SP_TEST))
12516 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12517 (clobber (match_scratch:DI 3 "=&r,&r"))]
12518 "TARGET_64BIT"
12519 "@
12520 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12521 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12522 [(set_attr "length" "16,20")])
12524 \f
12525 ;; Here are the actual compare insns.
12526 (define_insn "*cmp<mode>_internal1"
12527 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12528 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12529 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12530 ""
12531 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12532 [(set_attr "type" "cmp")])
12534 ;; If we are comparing a register for equality with a large constant,
12535 ;; we can do this with an XOR followed by a compare. But this is profitable
12536 ;; only if the large constant is only used for the comparison (and in this
12537 ;; case we already have a register to reuse as scratch).
12538 ;;
12539 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12540 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12542 (define_peephole2
12543 [(set (match_operand:SI 0 "register_operand")
12544 (match_operand:SI 1 "logical_const_operand" ""))
12545 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12546 [(match_dup 0)
12547 (match_operand:SI 2 "logical_const_operand" "")]))
12548 (set (match_operand:CC 4 "cc_reg_operand" "")
12549 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12550 (match_dup 0)))
12551 (set (pc)
12552 (if_then_else (match_operator 6 "equality_operator"
12553 [(match_dup 4) (const_int 0)])
12554 (match_operand 7 "" "")
12555 (match_operand 8 "" "")))]
12556 "peep2_reg_dead_p (3, operands[0])
12557 && peep2_reg_dead_p (4, operands[4])"
12558 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12559 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12560 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12562 {
12563 /* Get the constant we are comparing against, and see what it looks like
12564 when sign-extended from 16 to 32 bits. Then see what constant we could
12565 XOR with SEXTC to get the sign-extended value. */
12566 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12567 SImode,
12568 operands[1], operands[2]);
12569 HOST_WIDE_INT c = INTVAL (cnst);
12570 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12571 HOST_WIDE_INT xorv = c ^ sextc;
12573 operands[9] = GEN_INT (xorv);
12574 operands[10] = GEN_INT (sextc);
12575 })
12577 (define_insn "*cmpsi_internal2"
12578 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12579 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12580 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12581 ""
12582 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12583 [(set_attr "type" "cmp")])
12585 (define_insn "*cmpdi_internal2"
12586 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12587 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12588 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12589 ""
12590 "cmpld%I2 %0,%1,%b2"
12591 [(set_attr "type" "cmp")])
12593 ;; The following two insns don't exist as single insns, but if we provide
12594 ;; them, we can swap an add and compare, which will enable us to overlap more
12595 ;; of the required delay between a compare and branch. We generate code for
12596 ;; them by splitting.
12598 (define_insn ""
12599 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12600 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12601 (match_operand:SI 2 "short_cint_operand" "i")))
12602 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12603 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12604 ""
12605 "#"
12606 [(set_attr "length" "8")])
12608 (define_insn ""
12609 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12610 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12611 (match_operand:SI 2 "u_short_cint_operand" "i")))
12612 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12613 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12614 ""
12615 "#"
12616 [(set_attr "length" "8")])
12618 (define_split
12619 [(set (match_operand:CC 3 "cc_reg_operand" "")
12620 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12621 (match_operand:SI 2 "short_cint_operand" "")))
12622 (set (match_operand:SI 0 "gpc_reg_operand" "")
12623 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12624 ""
12625 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12626 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12628 (define_split
12629 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12630 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12631 (match_operand:SI 2 "u_short_cint_operand" "")))
12632 (set (match_operand:SI 0 "gpc_reg_operand" "")
12633 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12634 ""
12635 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12636 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12638 (define_insn "*cmpsf_internal1"
12639 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12640 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12641 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12642 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12643 "fcmpu %0,%1,%2"
12644 [(set_attr "type" "fpcompare")])
12646 (define_insn "*cmpdf_internal1"
12647 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12648 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12649 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12650 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
12651 "fcmpu %0,%1,%2"
12652 [(set_attr "type" "fpcompare")])
12654 ;; Only need to compare second words if first words equal
12655 (define_insn "*cmptf_internal1"
12656 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12657 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12658 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12659 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12660 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12661 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12662 [(set_attr "type" "fpcompare")
12663 (set_attr "length" "12")])
12665 (define_insn_and_split "*cmptf_internal2"
12666 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12667 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12668 (match_operand:TF 2 "gpc_reg_operand" "d")))
12669 (clobber (match_scratch:DF 3 "=d"))
12670 (clobber (match_scratch:DF 4 "=d"))
12671 (clobber (match_scratch:DF 5 "=d"))
12672 (clobber (match_scratch:DF 6 "=d"))
12673 (clobber (match_scratch:DF 7 "=d"))
12674 (clobber (match_scratch:DF 8 "=d"))
12675 (clobber (match_scratch:DF 9 "=d"))
12676 (clobber (match_scratch:DF 10 "=d"))]
12677 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12678 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12679 "#"
12680 "&& reload_completed"
12681 [(set (match_dup 3) (match_dup 13))
12682 (set (match_dup 4) (match_dup 14))
12683 (set (match_dup 9) (abs:DF (match_dup 5)))
12684 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12685 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12686 (label_ref (match_dup 11))
12687 (pc)))
12688 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12689 (set (pc) (label_ref (match_dup 12)))
12690 (match_dup 11)
12691 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12692 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12693 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12694 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12695 (match_dup 12)]
12696 {
12697 REAL_VALUE_TYPE rv;
12698 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12699 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12701 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12702 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12703 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12704 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12705 operands[11] = gen_label_rtx ();
12706 operands[12] = gen_label_rtx ();
12707 real_inf (&rv);
12708 operands[13] = force_const_mem (DFmode,
12709 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12710 operands[14] = force_const_mem (DFmode,
12711 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12712 DFmode));
12713 if (TARGET_TOC)
12714 {
12715 operands[13] = gen_const_mem (DFmode,
12716 create_TOC_reference (XEXP (operands[13], 0)));
12717 operands[14] = gen_const_mem (DFmode,
12718 create_TOC_reference (XEXP (operands[14], 0)));
12719 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12720 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12721 }
12722 })
12723 \f
12724 ;; Now we have the scc insns. We can do some combinations because of the
12725 ;; way the machine works.
12726 ;;
12727 ;; Note that this is probably faster if we can put an insn between the
12728 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12729 ;; cases the insns below which don't use an intermediate CR field will
12730 ;; be used instead.
12731 (define_insn ""
12732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12733 (match_operator:SI 1 "scc_comparison_operator"
12734 [(match_operand 2 "cc_reg_operand" "y")
12735 (const_int 0)]))]
12736 ""
12737 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12738 [(set (attr "type")
12739 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12740 (const_string "mfcrf")
12741 ]
12742 (const_string "mfcr")))
12743 (set_attr "length" "8")])
12745 ;; Same as above, but get the GT bit.
12746 (define_insn "move_from_CR_gt_bit"
12747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12748 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12749 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12750 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12751 [(set_attr "type" "mfcr")
12752 (set_attr "length" "8")])
12754 ;; Same as above, but get the OV/ORDERED bit.
12755 (define_insn "move_from_CR_ov_bit"
12756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12757 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12758 "TARGET_ISEL"
12759 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12760 [(set_attr "type" "mfcr")
12761 (set_attr "length" "8")])
12763 (define_insn ""
12764 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12765 (match_operator:DI 1 "scc_comparison_operator"
12766 [(match_operand 2 "cc_reg_operand" "y")
12767 (const_int 0)]))]
12768 "TARGET_POWERPC64"
12769 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12770 [(set (attr "type")
12771 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12772 (const_string "mfcrf")
12773 ]
12774 (const_string "mfcr")))
12775 (set_attr "length" "8")])
12777 (define_insn ""
12778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12779 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12780 [(match_operand 2 "cc_reg_operand" "y,y")
12781 (const_int 0)])
12782 (const_int 0)))
12783 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12784 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12785 "TARGET_32BIT"
12786 "@
12787 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12788 #"
12789 [(set_attr "type" "delayed_compare")
12790 (set_attr "length" "8,16")])
12792 (define_split
12793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12794 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12795 [(match_operand 2 "cc_reg_operand" "")
12796 (const_int 0)])
12797 (const_int 0)))
12798 (set (match_operand:SI 3 "gpc_reg_operand" "")
12799 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12800 "TARGET_32BIT && reload_completed"
12801 [(set (match_dup 3)
12802 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12803 (set (match_dup 0)
12804 (compare:CC (match_dup 3)
12805 (const_int 0)))]
12806 "")
12808 (define_insn ""
12809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12810 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12811 [(match_operand 2 "cc_reg_operand" "y")
12812 (const_int 0)])
12813 (match_operand:SI 3 "const_int_operand" "n")))]
12814 ""
12815 "*
12816 {
12817 int is_bit = ccr_bit (operands[1], 1);
12818 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12819 int count;
12821 if (is_bit >= put_bit)
12822 count = is_bit - put_bit;
12823 else
12824 count = 32 - (put_bit - is_bit);
12826 operands[4] = GEN_INT (count);
12827 operands[5] = GEN_INT (put_bit);
12829 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12830 }"
12831 [(set (attr "type")
12832 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12833 (const_string "mfcrf")
12834 ]
12835 (const_string "mfcr")))
12836 (set_attr "length" "8")])
12838 (define_insn ""
12839 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12840 (compare:CC
12841 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12842 [(match_operand 2 "cc_reg_operand" "y,y")
12843 (const_int 0)])
12844 (match_operand:SI 3 "const_int_operand" "n,n"))
12845 (const_int 0)))
12846 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12847 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12848 (match_dup 3)))]
12849 ""
12850 "*
12851 {
12852 int is_bit = ccr_bit (operands[1], 1);
12853 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12854 int count;
12856 /* Force split for non-cc0 compare. */
12857 if (which_alternative == 1)
12858 return \"#\";
12860 if (is_bit >= put_bit)
12861 count = is_bit - put_bit;
12862 else
12863 count = 32 - (put_bit - is_bit);
12865 operands[5] = GEN_INT (count);
12866 operands[6] = GEN_INT (put_bit);
12868 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12869 }"
12870 [(set_attr "type" "delayed_compare")
12871 (set_attr "length" "8,16")])
12873 (define_split
12874 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12875 (compare:CC
12876 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12877 [(match_operand 2 "cc_reg_operand" "")
12878 (const_int 0)])
12879 (match_operand:SI 3 "const_int_operand" ""))
12880 (const_int 0)))
12881 (set (match_operand:SI 4 "gpc_reg_operand" "")
12882 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12883 (match_dup 3)))]
12884 "reload_completed"
12885 [(set (match_dup 4)
12886 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12887 (match_dup 3)))
12888 (set (match_dup 0)
12889 (compare:CC (match_dup 4)
12890 (const_int 0)))]
12891 "")
12893 ;; There is a 3 cycle delay between consecutive mfcr instructions
12894 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12896 (define_peephole
12897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12898 (match_operator:SI 1 "scc_comparison_operator"
12899 [(match_operand 2 "cc_reg_operand" "y")
12900 (const_int 0)]))
12901 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12902 (match_operator:SI 4 "scc_comparison_operator"
12903 [(match_operand 5 "cc_reg_operand" "y")
12904 (const_int 0)]))]
12905 "REGNO (operands[2]) != REGNO (operands[5])"
12906 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12907 [(set_attr "type" "mfcr")
12908 (set_attr "length" "12")])
12910 (define_peephole
12911 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12912 (match_operator:DI 1 "scc_comparison_operator"
12913 [(match_operand 2 "cc_reg_operand" "y")
12914 (const_int 0)]))
12915 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12916 (match_operator:DI 4 "scc_comparison_operator"
12917 [(match_operand 5 "cc_reg_operand" "y")
12918 (const_int 0)]))]
12919 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12920 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12921 [(set_attr "type" "mfcr")
12922 (set_attr "length" "12")])
12924 ;; There are some scc insns that can be done directly, without a compare.
12925 ;; These are faster because they don't involve the communications between
12926 ;; the FXU and branch units. In fact, we will be replacing all of the
12927 ;; integer scc insns here or in the portable methods in emit_store_flag.
12928 ;;
12929 ;; Also support (neg (scc ..)) since that construct is used to replace
12930 ;; branches, (plus (scc ..) ..) since that construct is common and
12931 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12932 ;; cases where it is no more expensive than (neg (scc ..)).
12934 ;; Have reload force a constant into a register for the simple insns that
12935 ;; otherwise won't accept constants. We do this because it is faster than
12936 ;; the cmp/mfcr sequence we would otherwise generate.
12938 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12939 (DI "rKJI")])
12941 (define_insn_and_split "*eq<mode>"
12942 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12943 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12944 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12945 "!TARGET_POWER"
12946 "#"
12947 "!TARGET_POWER"
12948 [(set (match_dup 0)
12949 (clz:GPR (match_dup 3)))
12950 (set (match_dup 0)
12951 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12952 {
12953 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12954 {
12955 /* Use output operand as intermediate. */
12956 operands[3] = operands[0];
12958 if (logical_operand (operands[2], <MODE>mode))
12959 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12960 gen_rtx_XOR (<MODE>mode,
12961 operands[1], operands[2])));
12962 else
12963 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12964 gen_rtx_PLUS (<MODE>mode, operands[1],
12965 negate_rtx (<MODE>mode,
12966 operands[2]))));
12967 }
12968 else
12969 operands[3] = operands[1];
12971 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12972 })
12974 (define_insn_and_split "*eq<mode>_compare"
12975 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12976 (compare:CC
12977 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12978 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12979 (const_int 0)))
12980 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12981 (eq:P (match_dup 1) (match_dup 2)))]
12982 "!TARGET_POWER && optimize_size"
12983 "#"
12984 "!TARGET_POWER && optimize_size"
12985 [(set (match_dup 0)
12986 (clz:P (match_dup 4)))
12987 (parallel [(set (match_dup 3)
12988 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12989 (const_int 0)))
12990 (set (match_dup 0)
12991 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12992 {
12993 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12994 {
12995 /* Use output operand as intermediate. */
12996 operands[4] = operands[0];
12998 if (logical_operand (operands[2], <MODE>mode))
12999 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13000 gen_rtx_XOR (<MODE>mode,
13001 operands[1], operands[2])));
13002 else
13003 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13004 gen_rtx_PLUS (<MODE>mode, operands[1],
13005 negate_rtx (<MODE>mode,
13006 operands[2]))));
13007 }
13008 else
13009 operands[4] = operands[1];
13011 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13012 })
13014 (define_insn "*eqsi_power"
13015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13016 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13017 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13018 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13019 "TARGET_POWER"
13020 "@
13021 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13022 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13023 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13024 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13025 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13026 [(set_attr "type" "three,two,three,three,three")
13027 (set_attr "length" "12,8,12,12,12")])
13029 ;; We have insns of the form shown by the first define_insn below. If
13030 ;; there is something inside the comparison operation, we must split it.
13031 (define_split
13032 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13033 (plus:SI (match_operator 1 "comparison_operator"
13034 [(match_operand:SI 2 "" "")
13035 (match_operand:SI 3
13036 "reg_or_cint_operand" "")])
13037 (match_operand:SI 4 "gpc_reg_operand" "")))
13038 (clobber (match_operand:SI 5 "register_operand" ""))]
13039 "! gpc_reg_operand (operands[2], SImode)"
13040 [(set (match_dup 5) (match_dup 2))
13041 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13042 (match_dup 4)))])
13044 (define_insn "*plus_eqsi"
13045 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13046 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13047 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13048 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13049 "TARGET_32BIT"
13050 "@
13051 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13052 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13053 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13054 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13055 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13056 [(set_attr "type" "three,two,three,three,three")
13057 (set_attr "length" "12,8,12,12,12")])
13059 (define_insn "*compare_plus_eqsi"
13060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13061 (compare:CC
13062 (plus:SI
13063 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13064 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13065 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13066 (const_int 0)))
13067 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13068 "TARGET_32BIT && optimize_size"
13069 "@
13070 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13071 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13072 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13073 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13074 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13075 #
13076 #
13077 #
13078 #
13079 #"
13080 [(set_attr "type" "compare")
13081 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13083 (define_split
13084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13085 (compare:CC
13086 (plus:SI
13087 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13088 (match_operand:SI 2 "scc_eq_operand" ""))
13089 (match_operand:SI 3 "gpc_reg_operand" ""))
13090 (const_int 0)))
13091 (clobber (match_scratch:SI 4 ""))]
13092 "TARGET_32BIT && optimize_size && reload_completed"
13093 [(set (match_dup 4)
13094 (plus:SI (eq:SI (match_dup 1)
13095 (match_dup 2))
13096 (match_dup 3)))
13097 (set (match_dup 0)
13098 (compare:CC (match_dup 4)
13099 (const_int 0)))]
13100 "")
13102 (define_insn "*plus_eqsi_compare"
13103 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13104 (compare:CC
13105 (plus:SI
13106 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13107 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13108 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13109 (const_int 0)))
13110 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13111 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13112 "TARGET_32BIT && optimize_size"
13113 "@
13114 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13115 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13116 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13117 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13118 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13119 #
13120 #
13121 #
13122 #
13123 #"
13124 [(set_attr "type" "compare")
13125 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13127 (define_split
13128 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13129 (compare:CC
13130 (plus:SI
13131 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13132 (match_operand:SI 2 "scc_eq_operand" ""))
13133 (match_operand:SI 3 "gpc_reg_operand" ""))
13134 (const_int 0)))
13135 (set (match_operand:SI 0 "gpc_reg_operand" "")
13136 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13137 "TARGET_32BIT && optimize_size && reload_completed"
13138 [(set (match_dup 0)
13139 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13140 (set (match_dup 4)
13141 (compare:CC (match_dup 0)
13142 (const_int 0)))]
13143 "")
13145 (define_insn "*neg_eq0<mode>"
13146 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13147 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13148 (const_int 0))))]
13149 ""
13150 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13151 [(set_attr "type" "two")
13152 (set_attr "length" "8")])
13154 (define_insn_and_split "*neg_eq<mode>"
13155 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13156 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13157 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13158 ""
13159 "#"
13160 ""
13161 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13162 {
13163 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13164 {
13165 /* Use output operand as intermediate. */
13166 operands[3] = operands[0];
13168 if (logical_operand (operands[2], <MODE>mode))
13169 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13170 gen_rtx_XOR (<MODE>mode,
13171 operands[1], operands[2])));
13172 else
13173 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13174 gen_rtx_PLUS (<MODE>mode, operands[1],
13175 negate_rtx (<MODE>mode,
13176 operands[2]))));
13177 }
13178 else
13179 operands[3] = operands[1];
13180 })
13182 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13183 ;; since it nabs/sr is just as fast.
13184 (define_insn "*ne0si"
13185 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13186 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13187 (const_int 31)))
13188 (clobber (match_scratch:SI 2 "=&r"))]
13189 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13190 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13191 [(set_attr "type" "two")
13192 (set_attr "length" "8")])
13194 (define_insn "*ne0di"
13195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13196 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13197 (const_int 63)))
13198 (clobber (match_scratch:DI 2 "=&r"))]
13199 "TARGET_64BIT"
13200 "addic %2,%1,-1\;subfe %0,%2,%1"
13201 [(set_attr "type" "two")
13202 (set_attr "length" "8")])
13204 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13205 (define_insn "*plus_ne0si"
13206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13207 (plus:SI (lshiftrt:SI
13208 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13209 (const_int 31))
13210 (match_operand:SI 2 "gpc_reg_operand" "r")))
13211 (clobber (match_scratch:SI 3 "=&r"))]
13212 "TARGET_32BIT"
13213 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13214 [(set_attr "type" "two")
13215 (set_attr "length" "8")])
13217 (define_insn "*plus_ne0di"
13218 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13219 (plus:DI (lshiftrt:DI
13220 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13221 (const_int 63))
13222 (match_operand:DI 2 "gpc_reg_operand" "r")))
13223 (clobber (match_scratch:DI 3 "=&r"))]
13224 "TARGET_64BIT"
13225 "addic %3,%1,-1\;addze %0,%2"
13226 [(set_attr "type" "two")
13227 (set_attr "length" "8")])
13229 (define_insn "*compare_plus_ne0si"
13230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13231 (compare:CC
13232 (plus:SI (lshiftrt:SI
13233 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13234 (const_int 31))
13235 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13236 (const_int 0)))
13237 (clobber (match_scratch:SI 3 "=&r,&r"))
13238 (clobber (match_scratch:SI 4 "=X,&r"))]
13239 "TARGET_32BIT"
13240 "@
13241 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13242 #"
13243 [(set_attr "type" "compare")
13244 (set_attr "length" "8,12")])
13246 (define_split
13247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13248 (compare:CC
13249 (plus:SI (lshiftrt:SI
13250 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13251 (const_int 31))
13252 (match_operand:SI 2 "gpc_reg_operand" ""))
13253 (const_int 0)))
13254 (clobber (match_scratch:SI 3 ""))
13255 (clobber (match_scratch:SI 4 ""))]
13256 "TARGET_32BIT && reload_completed"
13257 [(parallel [(set (match_dup 3)
13258 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13259 (const_int 31))
13260 (match_dup 2)))
13261 (clobber (match_dup 4))])
13262 (set (match_dup 0)
13263 (compare:CC (match_dup 3)
13264 (const_int 0)))]
13265 "")
13267 (define_insn "*compare_plus_ne0di"
13268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13269 (compare:CC
13270 (plus:DI (lshiftrt:DI
13271 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13272 (const_int 63))
13273 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13274 (const_int 0)))
13275 (clobber (match_scratch:DI 3 "=&r,&r"))]
13276 "TARGET_64BIT"
13277 "@
13278 addic %3,%1,-1\;addze. %3,%2
13279 #"
13280 [(set_attr "type" "compare")
13281 (set_attr "length" "8,12")])
13283 (define_split
13284 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13285 (compare:CC
13286 (plus:DI (lshiftrt:DI
13287 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13288 (const_int 63))
13289 (match_operand:DI 2 "gpc_reg_operand" ""))
13290 (const_int 0)))
13291 (clobber (match_scratch:DI 3 ""))]
13292 "TARGET_64BIT && reload_completed"
13293 [(set (match_dup 3)
13294 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13295 (const_int 63))
13296 (match_dup 2)))
13297 (set (match_dup 0)
13298 (compare:CC (match_dup 3)
13299 (const_int 0)))]
13300 "")
13302 (define_insn "*plus_ne0si_compare"
13303 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13304 (compare:CC
13305 (plus:SI (lshiftrt:SI
13306 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13307 (const_int 31))
13308 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13309 (const_int 0)))
13310 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13311 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13312 (match_dup 2)))
13313 (clobber (match_scratch:SI 3 "=&r,&r"))]
13314 "TARGET_32BIT"
13315 "@
13316 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13317 #"
13318 [(set_attr "type" "compare")
13319 (set_attr "length" "8,12")])
13321 (define_split
13322 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13323 (compare:CC
13324 (plus:SI (lshiftrt:SI
13325 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13326 (const_int 31))
13327 (match_operand:SI 2 "gpc_reg_operand" ""))
13328 (const_int 0)))
13329 (set (match_operand:SI 0 "gpc_reg_operand" "")
13330 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13331 (match_dup 2)))
13332 (clobber (match_scratch:SI 3 ""))]
13333 "TARGET_32BIT && reload_completed"
13334 [(parallel [(set (match_dup 0)
13335 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13336 (match_dup 2)))
13337 (clobber (match_dup 3))])
13338 (set (match_dup 4)
13339 (compare:CC (match_dup 0)
13340 (const_int 0)))]
13341 "")
13343 (define_insn "*plus_ne0di_compare"
13344 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13345 (compare:CC
13346 (plus:DI (lshiftrt:DI
13347 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13348 (const_int 63))
13349 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13350 (const_int 0)))
13351 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13352 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13353 (match_dup 2)))
13354 (clobber (match_scratch:DI 3 "=&r,&r"))]
13355 "TARGET_64BIT"
13356 "@
13357 addic %3,%1,-1\;addze. %0,%2
13358 #"
13359 [(set_attr "type" "compare")
13360 (set_attr "length" "8,12")])
13362 (define_split
13363 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13364 (compare:CC
13365 (plus:DI (lshiftrt:DI
13366 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13367 (const_int 63))
13368 (match_operand:DI 2 "gpc_reg_operand" ""))
13369 (const_int 0)))
13370 (set (match_operand:DI 0 "gpc_reg_operand" "")
13371 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13372 (match_dup 2)))
13373 (clobber (match_scratch:DI 3 ""))]
13374 "TARGET_64BIT && reload_completed"
13375 [(parallel [(set (match_dup 0)
13376 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13377 (match_dup 2)))
13378 (clobber (match_dup 3))])
13379 (set (match_dup 4)
13380 (compare:CC (match_dup 0)
13381 (const_int 0)))]
13382 "")
13384 (define_insn ""
13385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13386 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13387 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13388 (clobber (match_scratch:SI 3 "=r,X"))]
13389 "TARGET_POWER"
13390 "@
13391 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13392 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13393 [(set_attr "length" "12")])
13395 (define_insn ""
13396 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13397 (compare:CC
13398 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13399 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13400 (const_int 0)))
13401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13402 (le:SI (match_dup 1) (match_dup 2)))
13403 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13404 "TARGET_POWER"
13405 "@
13406 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13407 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13408 #
13409 #"
13410 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13411 (set_attr "length" "12,12,16,16")])
13413 (define_split
13414 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13415 (compare:CC
13416 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13417 (match_operand:SI 2 "reg_or_short_operand" ""))
13418 (const_int 0)))
13419 (set (match_operand:SI 0 "gpc_reg_operand" "")
13420 (le:SI (match_dup 1) (match_dup 2)))
13421 (clobber (match_scratch:SI 3 ""))]
13422 "TARGET_POWER && reload_completed"
13423 [(parallel [(set (match_dup 0)
13424 (le:SI (match_dup 1) (match_dup 2)))
13425 (clobber (match_dup 3))])
13426 (set (match_dup 4)
13427 (compare:CC (match_dup 0)
13428 (const_int 0)))]
13429 "")
13431 (define_insn ""
13432 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13433 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13434 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13435 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13436 "TARGET_POWER"
13437 "@
13438 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13439 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13440 [(set_attr "length" "12")])
13442 (define_insn ""
13443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13444 (compare:CC
13445 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13446 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13447 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13448 (const_int 0)))
13449 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13450 "TARGET_POWER"
13451 "@
13452 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13453 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13454 #
13455 #"
13456 [(set_attr "type" "compare")
13457 (set_attr "length" "12,12,16,16")])
13459 (define_split
13460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13461 (compare:CC
13462 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13463 (match_operand:SI 2 "reg_or_short_operand" ""))
13464 (match_operand:SI 3 "gpc_reg_operand" ""))
13465 (const_int 0)))
13466 (clobber (match_scratch:SI 4 ""))]
13467 "TARGET_POWER && reload_completed"
13468 [(set (match_dup 4)
13469 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13470 (match_dup 3)))
13471 (set (match_dup 0)
13472 (compare:CC (match_dup 4)
13473 (const_int 0)))]
13474 "")
13476 (define_insn ""
13477 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13478 (compare:CC
13479 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13480 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13481 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13482 (const_int 0)))
13483 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13484 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13485 "TARGET_POWER"
13486 "@
13487 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13488 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13489 #
13490 #"
13491 [(set_attr "type" "compare")
13492 (set_attr "length" "12,12,16,16")])
13494 (define_split
13495 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13496 (compare:CC
13497 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13498 (match_operand:SI 2 "reg_or_short_operand" ""))
13499 (match_operand:SI 3 "gpc_reg_operand" ""))
13500 (const_int 0)))
13501 (set (match_operand:SI 0 "gpc_reg_operand" "")
13502 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13503 "TARGET_POWER && reload_completed"
13504 [(set (match_dup 0)
13505 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13506 (set (match_dup 4)
13507 (compare:CC (match_dup 0)
13508 (const_int 0)))]
13509 "")
13511 (define_insn ""
13512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13513 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13514 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13515 "TARGET_POWER"
13516 "@
13517 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13518 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13519 [(set_attr "length" "12")])
13521 (define_insn "*leu<mode>"
13522 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13523 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13524 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13525 ""
13526 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13527 [(set_attr "type" "three")
13528 (set_attr "length" "12")])
13530 (define_insn "*leu<mode>_compare"
13531 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13532 (compare:CC
13533 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13534 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13535 (const_int 0)))
13536 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13537 (leu:P (match_dup 1) (match_dup 2)))]
13538 ""
13539 "@
13540 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13541 #"
13542 [(set_attr "type" "compare")
13543 (set_attr "length" "12,16")])
13545 (define_split
13546 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13547 (compare:CC
13548 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13549 (match_operand:P 2 "reg_or_short_operand" ""))
13550 (const_int 0)))
13551 (set (match_operand:P 0 "gpc_reg_operand" "")
13552 (leu:P (match_dup 1) (match_dup 2)))]
13553 "reload_completed"
13554 [(set (match_dup 0)
13555 (leu:P (match_dup 1) (match_dup 2)))
13556 (set (match_dup 3)
13557 (compare:CC (match_dup 0)
13558 (const_int 0)))]
13559 "")
13561 (define_insn "*plus_leu<mode>"
13562 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13563 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13564 (match_operand:P 2 "reg_or_short_operand" "rI"))
13565 (match_operand:P 3 "gpc_reg_operand" "r")))]
13566 ""
13567 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13568 [(set_attr "type" "two")
13569 (set_attr "length" "8")])
13571 (define_insn ""
13572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13573 (compare:CC
13574 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13575 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13576 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13577 (const_int 0)))
13578 (clobber (match_scratch:SI 4 "=&r,&r"))]
13579 "TARGET_32BIT"
13580 "@
13581 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13582 #"
13583 [(set_attr "type" "compare")
13584 (set_attr "length" "8,12")])
13586 (define_split
13587 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13588 (compare:CC
13589 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13590 (match_operand:SI 2 "reg_or_short_operand" ""))
13591 (match_operand:SI 3 "gpc_reg_operand" ""))
13592 (const_int 0)))
13593 (clobber (match_scratch:SI 4 ""))]
13594 "TARGET_32BIT && reload_completed"
13595 [(set (match_dup 4)
13596 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13597 (match_dup 3)))
13598 (set (match_dup 0)
13599 (compare:CC (match_dup 4)
13600 (const_int 0)))]
13601 "")
13603 (define_insn ""
13604 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13605 (compare:CC
13606 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13607 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13608 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13609 (const_int 0)))
13610 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13611 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13612 "TARGET_32BIT"
13613 "@
13614 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13615 #"
13616 [(set_attr "type" "compare")
13617 (set_attr "length" "8,12")])
13619 (define_split
13620 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13621 (compare:CC
13622 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13623 (match_operand:SI 2 "reg_or_short_operand" ""))
13624 (match_operand:SI 3 "gpc_reg_operand" ""))
13625 (const_int 0)))
13626 (set (match_operand:SI 0 "gpc_reg_operand" "")
13627 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13628 "TARGET_32BIT && reload_completed"
13629 [(set (match_dup 0)
13630 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13631 (set (match_dup 4)
13632 (compare:CC (match_dup 0)
13633 (const_int 0)))]
13634 "")
13636 (define_insn "*neg_leu<mode>"
13637 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13638 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13639 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13640 ""
13641 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13642 [(set_attr "type" "three")
13643 (set_attr "length" "12")])
13645 (define_insn "*and_neg_leu<mode>"
13646 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13647 (and:P (neg:P
13648 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13649 (match_operand:P 2 "reg_or_short_operand" "rI")))
13650 (match_operand:P 3 "gpc_reg_operand" "r")))]
13651 ""
13652 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13653 [(set_attr "type" "three")
13654 (set_attr "length" "12")])
13656 (define_insn ""
13657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13658 (compare:CC
13659 (and:SI (neg:SI
13660 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13661 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13662 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13663 (const_int 0)))
13664 (clobber (match_scratch:SI 4 "=&r,&r"))]
13665 "TARGET_32BIT"
13666 "@
13667 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13668 #"
13669 [(set_attr "type" "compare")
13670 (set_attr "length" "12,16")])
13672 (define_split
13673 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13674 (compare:CC
13675 (and:SI (neg:SI
13676 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13677 (match_operand:SI 2 "reg_or_short_operand" "")))
13678 (match_operand:SI 3 "gpc_reg_operand" ""))
13679 (const_int 0)))
13680 (clobber (match_scratch:SI 4 ""))]
13681 "TARGET_32BIT && reload_completed"
13682 [(set (match_dup 4)
13683 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13684 (match_dup 3)))
13685 (set (match_dup 0)
13686 (compare:CC (match_dup 4)
13687 (const_int 0)))]
13688 "")
13690 (define_insn ""
13691 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13692 (compare:CC
13693 (and:SI (neg:SI
13694 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13695 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13696 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13697 (const_int 0)))
13698 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13699 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13700 "TARGET_32BIT"
13701 "@
13702 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13703 #"
13704 [(set_attr "type" "compare")
13705 (set_attr "length" "12,16")])
13707 (define_split
13708 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13709 (compare:CC
13710 (and:SI (neg:SI
13711 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13712 (match_operand:SI 2 "reg_or_short_operand" "")))
13713 (match_operand:SI 3 "gpc_reg_operand" ""))
13714 (const_int 0)))
13715 (set (match_operand:SI 0 "gpc_reg_operand" "")
13716 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13717 "TARGET_32BIT && reload_completed"
13718 [(set (match_dup 0)
13719 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13720 (match_dup 3)))
13721 (set (match_dup 4)
13722 (compare:CC (match_dup 0)
13723 (const_int 0)))]
13724 "")
13726 (define_insn ""
13727 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13728 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13729 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13730 "TARGET_POWER"
13731 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13732 [(set_attr "length" "12")])
13734 (define_insn ""
13735 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13736 (compare:CC
13737 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13738 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13739 (const_int 0)))
13740 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13741 (lt:SI (match_dup 1) (match_dup 2)))]
13742 "TARGET_POWER"
13743 "@
13744 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13745 #"
13746 [(set_attr "type" "delayed_compare")
13747 (set_attr "length" "12,16")])
13749 (define_split
13750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13751 (compare:CC
13752 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13753 (match_operand:SI 2 "reg_or_short_operand" ""))
13754 (const_int 0)))
13755 (set (match_operand:SI 0 "gpc_reg_operand" "")
13756 (lt:SI (match_dup 1) (match_dup 2)))]
13757 "TARGET_POWER && reload_completed"
13758 [(set (match_dup 0)
13759 (lt:SI (match_dup 1) (match_dup 2)))
13760 (set (match_dup 3)
13761 (compare:CC (match_dup 0)
13762 (const_int 0)))]
13763 "")
13765 (define_insn ""
13766 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13767 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13768 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13769 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13770 "TARGET_POWER"
13771 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13772 [(set_attr "length" "12")])
13774 (define_insn ""
13775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13776 (compare:CC
13777 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13778 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13779 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13780 (const_int 0)))
13781 (clobber (match_scratch:SI 4 "=&r,&r"))]
13782 "TARGET_POWER"
13783 "@
13784 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13785 #"
13786 [(set_attr "type" "compare")
13787 (set_attr "length" "12,16")])
13789 (define_split
13790 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13791 (compare:CC
13792 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13793 (match_operand:SI 2 "reg_or_short_operand" ""))
13794 (match_operand:SI 3 "gpc_reg_operand" ""))
13795 (const_int 0)))
13796 (clobber (match_scratch:SI 4 ""))]
13797 "TARGET_POWER && reload_completed"
13798 [(set (match_dup 4)
13799 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13800 (match_dup 3)))
13801 (set (match_dup 0)
13802 (compare:CC (match_dup 4)
13803 (const_int 0)))]
13804 "")
13806 (define_insn ""
13807 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13808 (compare:CC
13809 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13810 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13811 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13812 (const_int 0)))
13813 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13814 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13815 "TARGET_POWER"
13816 "@
13817 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13818 #"
13819 [(set_attr "type" "compare")
13820 (set_attr "length" "12,16")])
13822 (define_split
13823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13824 (compare:CC
13825 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13826 (match_operand:SI 2 "reg_or_short_operand" ""))
13827 (match_operand:SI 3 "gpc_reg_operand" ""))
13828 (const_int 0)))
13829 (set (match_operand:SI 0 "gpc_reg_operand" "")
13830 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13831 "TARGET_POWER && reload_completed"
13832 [(set (match_dup 0)
13833 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13834 (set (match_dup 4)
13835 (compare:CC (match_dup 0)
13836 (const_int 0)))]
13837 "")
13839 (define_insn ""
13840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13841 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13842 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13843 "TARGET_POWER"
13844 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13845 [(set_attr "length" "12")])
13847 (define_insn_and_split "*ltu<mode>"
13848 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13849 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13850 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13851 ""
13852 "#"
13853 ""
13854 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13855 (set (match_dup 0) (neg:P (match_dup 0)))]
13856 "")
13858 (define_insn_and_split "*ltu<mode>_compare"
13859 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13860 (compare:CC
13861 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13862 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13863 (const_int 0)))
13864 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13865 (ltu:P (match_dup 1) (match_dup 2)))]
13866 ""
13867 "#"
13868 ""
13869 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13870 (parallel [(set (match_dup 3)
13871 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13872 (set (match_dup 0) (neg:P (match_dup 0)))])]
13873 "")
13875 (define_insn_and_split "*plus_ltu<mode>"
13876 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13877 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13878 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13879 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13880 ""
13881 "#"
13882 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13883 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13884 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13885 "")
13887 (define_insn_and_split "*plus_ltu<mode>_compare"
13888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13889 (compare:CC
13890 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13891 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13892 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13893 (const_int 0)))
13894 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13895 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13896 ""
13897 "#"
13898 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13899 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13900 (parallel [(set (match_dup 4)
13901 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13902 (const_int 0)))
13903 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13904 "")
13906 (define_insn "*neg_ltu<mode>"
13907 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13908 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13909 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13910 ""
13911 "@
13912 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13913 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13914 [(set_attr "type" "two")
13915 (set_attr "length" "8")])
13917 (define_insn ""
13918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13919 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13920 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13921 (clobber (match_scratch:SI 3 "=r"))]
13922 "TARGET_POWER"
13923 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13924 [(set_attr "length" "12")])
13926 (define_insn ""
13927 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13928 (compare:CC
13929 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13930 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13931 (const_int 0)))
13932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13933 (ge:SI (match_dup 1) (match_dup 2)))
13934 (clobber (match_scratch:SI 3 "=r,r"))]
13935 "TARGET_POWER"
13936 "@
13937 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13938 #"
13939 [(set_attr "type" "compare")
13940 (set_attr "length" "12,16")])
13942 (define_split
13943 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13944 (compare:CC
13945 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13946 (match_operand:SI 2 "reg_or_short_operand" ""))
13947 (const_int 0)))
13948 (set (match_operand:SI 0 "gpc_reg_operand" "")
13949 (ge:SI (match_dup 1) (match_dup 2)))
13950 (clobber (match_scratch:SI 3 ""))]
13951 "TARGET_POWER && reload_completed"
13952 [(parallel [(set (match_dup 0)
13953 (ge:SI (match_dup 1) (match_dup 2)))
13954 (clobber (match_dup 3))])
13955 (set (match_dup 4)
13956 (compare:CC (match_dup 0)
13957 (const_int 0)))]
13958 "")
13960 (define_insn ""
13961 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13962 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13963 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13964 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13965 "TARGET_POWER"
13966 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13967 [(set_attr "length" "12")])
13969 (define_insn ""
13970 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13971 (compare:CC
13972 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13973 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13974 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13975 (const_int 0)))
13976 (clobber (match_scratch:SI 4 "=&r,&r"))]
13977 "TARGET_POWER"
13978 "@
13979 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13980 #"
13981 [(set_attr "type" "compare")
13982 (set_attr "length" "12,16")])
13984 (define_split
13985 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13986 (compare:CC
13987 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13988 (match_operand:SI 2 "reg_or_short_operand" ""))
13989 (match_operand:SI 3 "gpc_reg_operand" ""))
13990 (const_int 0)))
13991 (clobber (match_scratch:SI 4 ""))]
13992 "TARGET_POWER && reload_completed"
13993 [(set (match_dup 4)
13994 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13995 (match_dup 3)))
13996 (set (match_dup 0)
13997 (compare:CC (match_dup 4)
13998 (const_int 0)))]
13999 "")
14001 (define_insn ""
14002 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14003 (compare:CC
14004 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14005 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14006 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14007 (const_int 0)))
14008 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14009 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14010 "TARGET_POWER"
14011 "@
14012 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14013 #"
14014 [(set_attr "type" "compare")
14015 (set_attr "length" "12,16")])
14017 (define_split
14018 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14019 (compare:CC
14020 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14021 (match_operand:SI 2 "reg_or_short_operand" ""))
14022 (match_operand:SI 3 "gpc_reg_operand" ""))
14023 (const_int 0)))
14024 (set (match_operand:SI 0 "gpc_reg_operand" "")
14025 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14026 "TARGET_POWER && reload_completed"
14027 [(set (match_dup 0)
14028 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14029 (set (match_dup 4)
14030 (compare:CC (match_dup 0)
14031 (const_int 0)))]
14032 "")
14034 (define_insn ""
14035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14036 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14037 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14038 "TARGET_POWER"
14039 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14040 [(set_attr "length" "12")])
14042 (define_insn "*geu<mode>"
14043 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14044 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14045 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14046 ""
14047 "@
14048 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14049 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14050 [(set_attr "type" "three")
14051 (set_attr "length" "12")])
14053 (define_insn "*geu<mode>_compare"
14054 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14055 (compare:CC
14056 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14057 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14058 (const_int 0)))
14059 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14060 (geu:P (match_dup 1) (match_dup 2)))]
14061 ""
14062 "@
14063 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14064 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14065 #
14066 #"
14067 [(set_attr "type" "compare")
14068 (set_attr "length" "12,12,16,16")])
14070 (define_split
14071 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14072 (compare:CC
14073 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14074 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14075 (const_int 0)))
14076 (set (match_operand:P 0 "gpc_reg_operand" "")
14077 (geu:P (match_dup 1) (match_dup 2)))]
14078 "reload_completed"
14079 [(set (match_dup 0)
14080 (geu:P (match_dup 1) (match_dup 2)))
14081 (set (match_dup 3)
14082 (compare:CC (match_dup 0)
14083 (const_int 0)))]
14084 "")
14086 (define_insn "*plus_geu<mode>"
14087 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14088 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14089 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14090 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14091 ""
14092 "@
14093 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14094 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14095 [(set_attr "type" "two")
14096 (set_attr "length" "8")])
14098 (define_insn ""
14099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14100 (compare:CC
14101 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14102 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14103 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14104 (const_int 0)))
14105 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14106 "TARGET_32BIT"
14107 "@
14108 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14109 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14110 #
14111 #"
14112 [(set_attr "type" "compare")
14113 (set_attr "length" "8,8,12,12")])
14115 (define_split
14116 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14117 (compare:CC
14118 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14119 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14120 (match_operand:SI 3 "gpc_reg_operand" ""))
14121 (const_int 0)))
14122 (clobber (match_scratch:SI 4 ""))]
14123 "TARGET_32BIT && reload_completed"
14124 [(set (match_dup 4)
14125 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14126 (match_dup 3)))
14127 (set (match_dup 0)
14128 (compare:CC (match_dup 4)
14129 (const_int 0)))]
14130 "")
14132 (define_insn ""
14133 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14134 (compare:CC
14135 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14136 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14137 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14138 (const_int 0)))
14139 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14140 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14141 "TARGET_32BIT"
14142 "@
14143 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14144 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14145 #
14146 #"
14147 [(set_attr "type" "compare")
14148 (set_attr "length" "8,8,12,12")])
14150 (define_split
14151 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14152 (compare:CC
14153 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14154 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14155 (match_operand:SI 3 "gpc_reg_operand" ""))
14156 (const_int 0)))
14157 (set (match_operand:SI 0 "gpc_reg_operand" "")
14158 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14159 "TARGET_32BIT && reload_completed"
14160 [(set (match_dup 0)
14161 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14162 (set (match_dup 4)
14163 (compare:CC (match_dup 0)
14164 (const_int 0)))]
14165 "")
14167 (define_insn "*neg_geu<mode>"
14168 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14169 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14170 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14171 ""
14172 "@
14173 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14174 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14175 [(set_attr "type" "three")
14176 (set_attr "length" "12")])
14178 (define_insn "*and_neg_geu<mode>"
14179 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14180 (and:P (neg:P
14181 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14182 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14183 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14184 ""
14185 "@
14186 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14187 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14188 [(set_attr "type" "three")
14189 (set_attr "length" "12")])
14191 (define_insn ""
14192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14193 (compare:CC
14194 (and:SI (neg:SI
14195 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14196 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14197 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14198 (const_int 0)))
14199 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14200 "TARGET_32BIT"
14201 "@
14202 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14203 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14204 #
14205 #"
14206 [(set_attr "type" "compare")
14207 (set_attr "length" "12,12,16,16")])
14209 (define_split
14210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14211 (compare:CC
14212 (and:SI (neg:SI
14213 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14214 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14215 (match_operand:SI 3 "gpc_reg_operand" ""))
14216 (const_int 0)))
14217 (clobber (match_scratch:SI 4 ""))]
14218 "TARGET_32BIT && reload_completed"
14219 [(set (match_dup 4)
14220 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14221 (match_dup 3)))
14222 (set (match_dup 0)
14223 (compare:CC (match_dup 4)
14224 (const_int 0)))]
14225 "")
14227 (define_insn ""
14228 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14229 (compare:CC
14230 (and:SI (neg:SI
14231 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14232 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14233 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14234 (const_int 0)))
14235 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14236 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14237 "TARGET_32BIT"
14238 "@
14239 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14240 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14241 #
14242 #"
14243 [(set_attr "type" "compare")
14244 (set_attr "length" "12,12,16,16")])
14246 (define_split
14247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14248 (compare:CC
14249 (and:SI (neg:SI
14250 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14251 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14252 (match_operand:SI 3 "gpc_reg_operand" ""))
14253 (const_int 0)))
14254 (set (match_operand:SI 0 "gpc_reg_operand" "")
14255 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14256 "TARGET_32BIT && reload_completed"
14257 [(set (match_dup 0)
14258 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14259 (set (match_dup 4)
14260 (compare:CC (match_dup 0)
14261 (const_int 0)))]
14262 "")
14264 (define_insn ""
14265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14266 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14267 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14268 "TARGET_POWER"
14269 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14270 [(set_attr "length" "12")])
14272 (define_insn ""
14273 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14274 (compare:CC
14275 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14276 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14277 (const_int 0)))
14278 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14279 (gt:SI (match_dup 1) (match_dup 2)))]
14280 "TARGET_POWER"
14281 "@
14282 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14283 #"
14284 [(set_attr "type" "delayed_compare")
14285 (set_attr "length" "12,16")])
14287 (define_split
14288 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14289 (compare:CC
14290 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14291 (match_operand:SI 2 "reg_or_short_operand" ""))
14292 (const_int 0)))
14293 (set (match_operand:SI 0 "gpc_reg_operand" "")
14294 (gt:SI (match_dup 1) (match_dup 2)))]
14295 "TARGET_POWER && reload_completed"
14296 [(set (match_dup 0)
14297 (gt:SI (match_dup 1) (match_dup 2)))
14298 (set (match_dup 3)
14299 (compare:CC (match_dup 0)
14300 (const_int 0)))]
14301 "")
14303 (define_insn "*plus_gt0<mode>"
14304 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14305 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14306 (const_int 0))
14307 (match_operand:P 2 "gpc_reg_operand" "r")))]
14308 ""
14309 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14310 [(set_attr "type" "three")
14311 (set_attr "length" "12")])
14313 (define_insn ""
14314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14315 (compare:CC
14316 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14317 (const_int 0))
14318 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14319 (const_int 0)))
14320 (clobber (match_scratch:SI 3 "=&r,&r"))]
14321 "TARGET_32BIT"
14322 "@
14323 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14324 #"
14325 [(set_attr "type" "compare")
14326 (set_attr "length" "12,16")])
14328 (define_split
14329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14330 (compare:CC
14331 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14332 (const_int 0))
14333 (match_operand:SI 2 "gpc_reg_operand" ""))
14334 (const_int 0)))
14335 (clobber (match_scratch:SI 3 ""))]
14336 "TARGET_32BIT && reload_completed"
14337 [(set (match_dup 3)
14338 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14339 (match_dup 2)))
14340 (set (match_dup 0)
14341 (compare:CC (match_dup 3)
14342 (const_int 0)))]
14343 "")
14345 (define_insn ""
14346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14347 (compare:CC
14348 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14349 (const_int 0))
14350 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14351 (const_int 0)))
14352 (clobber (match_scratch:DI 3 "=&r,&r"))]
14353 "TARGET_64BIT"
14354 "@
14355 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14356 #"
14357 [(set_attr "type" "compare")
14358 (set_attr "length" "12,16")])
14360 (define_split
14361 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14362 (compare:CC
14363 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14364 (const_int 0))
14365 (match_operand:DI 2 "gpc_reg_operand" ""))
14366 (const_int 0)))
14367 (clobber (match_scratch:DI 3 ""))]
14368 "TARGET_64BIT && reload_completed"
14369 [(set (match_dup 3)
14370 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14371 (match_dup 2)))
14372 (set (match_dup 0)
14373 (compare:CC (match_dup 3)
14374 (const_int 0)))]
14375 "")
14377 (define_insn ""
14378 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14379 (compare:CC
14380 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14381 (const_int 0))
14382 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14383 (const_int 0)))
14384 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14385 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14386 "TARGET_32BIT"
14387 "@
14388 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14389 #"
14390 [(set_attr "type" "compare")
14391 (set_attr "length" "12,16")])
14393 (define_split
14394 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14395 (compare:CC
14396 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14397 (const_int 0))
14398 (match_operand:SI 2 "gpc_reg_operand" ""))
14399 (const_int 0)))
14400 (set (match_operand:SI 0 "gpc_reg_operand" "")
14401 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14402 "TARGET_32BIT && reload_completed"
14403 [(set (match_dup 0)
14404 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14405 (set (match_dup 3)
14406 (compare:CC (match_dup 0)
14407 (const_int 0)))]
14408 "")
14410 (define_insn ""
14411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14412 (compare:CC
14413 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14414 (const_int 0))
14415 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14416 (const_int 0)))
14417 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14418 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14419 "TARGET_64BIT"
14420 "@
14421 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14422 #"
14423 [(set_attr "type" "compare")
14424 (set_attr "length" "12,16")])
14426 (define_split
14427 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14428 (compare:CC
14429 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14430 (const_int 0))
14431 (match_operand:DI 2 "gpc_reg_operand" ""))
14432 (const_int 0)))
14433 (set (match_operand:DI 0 "gpc_reg_operand" "")
14434 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14435 "TARGET_64BIT && reload_completed"
14436 [(set (match_dup 0)
14437 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14438 (set (match_dup 3)
14439 (compare:CC (match_dup 0)
14440 (const_int 0)))]
14441 "")
14443 (define_insn ""
14444 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14445 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14446 (match_operand:SI 2 "reg_or_short_operand" "r"))
14447 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14448 "TARGET_POWER"
14449 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14450 [(set_attr "length" "12")])
14452 (define_insn ""
14453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14454 (compare:CC
14455 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14456 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14457 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14458 (const_int 0)))
14459 (clobber (match_scratch:SI 4 "=&r,&r"))]
14460 "TARGET_POWER"
14461 "@
14462 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14463 #"
14464 [(set_attr "type" "compare")
14465 (set_attr "length" "12,16")])
14467 (define_split
14468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14469 (compare:CC
14470 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14471 (match_operand:SI 2 "reg_or_short_operand" ""))
14472 (match_operand:SI 3 "gpc_reg_operand" ""))
14473 (const_int 0)))
14474 (clobber (match_scratch:SI 4 ""))]
14475 "TARGET_POWER && reload_completed"
14476 [(set (match_dup 4)
14477 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14478 (set (match_dup 0)
14479 (compare:CC (match_dup 4)
14480 (const_int 0)))]
14481 "")
14483 (define_insn ""
14484 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14485 (compare:CC
14486 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14487 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14488 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14489 (const_int 0)))
14490 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14491 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14492 "TARGET_POWER"
14493 "@
14494 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14495 #"
14496 [(set_attr "type" "compare")
14497 (set_attr "length" "12,16")])
14499 (define_split
14500 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14501 (compare:CC
14502 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14503 (match_operand:SI 2 "reg_or_short_operand" ""))
14504 (match_operand:SI 3 "gpc_reg_operand" ""))
14505 (const_int 0)))
14506 (set (match_operand:SI 0 "gpc_reg_operand" "")
14507 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14508 "TARGET_POWER && reload_completed"
14509 [(set (match_dup 0)
14510 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14511 (set (match_dup 4)
14512 (compare:CC (match_dup 0)
14513 (const_int 0)))]
14514 "")
14516 (define_insn ""
14517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14518 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14519 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14520 "TARGET_POWER"
14521 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14522 [(set_attr "length" "12")])
14524 (define_insn_and_split "*gtu<mode>"
14525 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14526 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14527 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14528 ""
14529 "#"
14530 ""
14531 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14532 (set (match_dup 0) (neg:P (match_dup 0)))]
14533 "")
14535 (define_insn_and_split "*gtu<mode>_compare"
14536 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14537 (compare:CC
14538 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14539 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14540 (const_int 0)))
14541 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14542 (gtu:P (match_dup 1) (match_dup 2)))]
14543 ""
14544 "#"
14545 ""
14546 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14547 (parallel [(set (match_dup 3)
14548 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14549 (set (match_dup 0) (neg:P (match_dup 0)))])]
14550 "")
14552 (define_insn_and_split "*plus_gtu<mode>"
14553 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14554 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14555 (match_operand:P 2 "reg_or_short_operand" "rI"))
14556 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14557 ""
14558 "#"
14559 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14560 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14561 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14562 "")
14564 (define_insn_and_split "*plus_gtu<mode>_compare"
14565 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14566 (compare:CC
14567 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14568 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14569 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14570 (const_int 0)))
14571 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14572 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14573 ""
14574 "#"
14575 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14576 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14577 (parallel [(set (match_dup 4)
14578 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14579 (const_int 0)))
14580 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14581 "")
14583 (define_insn "*neg_gtu<mode>"
14584 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14585 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14586 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14587 ""
14588 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14589 [(set_attr "type" "two")
14590 (set_attr "length" "8")])
14592 \f
14593 ;; Define both directions of branch and return. If we need a reload
14594 ;; register, we'd rather use CR0 since it is much easier to copy a
14595 ;; register CC value to there.
14597 (define_insn ""
14598 [(set (pc)
14599 (if_then_else (match_operator 1 "branch_comparison_operator"
14600 [(match_operand 2
14601 "cc_reg_operand" "y")
14602 (const_int 0)])
14603 (label_ref (match_operand 0 "" ""))
14604 (pc)))]
14605 ""
14606 "*
14607 {
14608 return output_cbranch (operands[1], \"%l0\", 0, insn);
14609 }"
14610 [(set_attr "type" "branch")])
14612 (define_insn ""
14613 [(set (pc)
14614 (if_then_else (match_operator 0 "branch_comparison_operator"
14615 [(match_operand 1
14616 "cc_reg_operand" "y")
14617 (const_int 0)])
14618 (return)
14619 (pc)))]
14620 "direct_return ()"
14621 "*
14622 {
14623 return output_cbranch (operands[0], NULL, 0, insn);
14624 }"
14625 [(set_attr "type" "jmpreg")
14626 (set_attr "length" "4")])
14628 (define_insn ""
14629 [(set (pc)
14630 (if_then_else (match_operator 1 "branch_comparison_operator"
14631 [(match_operand 2
14632 "cc_reg_operand" "y")
14633 (const_int 0)])
14634 (pc)
14635 (label_ref (match_operand 0 "" ""))))]
14636 ""
14637 "*
14638 {
14639 return output_cbranch (operands[1], \"%l0\", 1, insn);
14640 }"
14641 [(set_attr "type" "branch")])
14643 (define_insn ""
14644 [(set (pc)
14645 (if_then_else (match_operator 0 "branch_comparison_operator"
14646 [(match_operand 1
14647 "cc_reg_operand" "y")
14648 (const_int 0)])
14649 (pc)
14650 (return)))]
14651 "direct_return ()"
14652 "*
14653 {
14654 return output_cbranch (operands[0], NULL, 1, insn);
14655 }"
14656 [(set_attr "type" "jmpreg")
14657 (set_attr "length" "4")])
14659 ;; Logic on condition register values.
14661 ; This pattern matches things like
14662 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14663 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14664 ; (const_int 1)))
14665 ; which are generated by the branch logic.
14666 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14668 (define_insn "*cceq_ior_compare"
14669 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14670 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14671 [(match_operator:SI 2
14672 "branch_positive_comparison_operator"
14673 [(match_operand 3
14674 "cc_reg_operand" "y,y")
14675 (const_int 0)])
14676 (match_operator:SI 4
14677 "branch_positive_comparison_operator"
14678 [(match_operand 5
14679 "cc_reg_operand" "0,y")
14680 (const_int 0)])])
14681 (const_int 1)))]
14682 ""
14683 "cr%q1 %E0,%j2,%j4"
14684 [(set_attr "type" "cr_logical,delayed_cr")])
14686 ; Why is the constant -1 here, but 1 in the previous pattern?
14687 ; Because ~1 has all but the low bit set.
14688 (define_insn ""
14689 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14690 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14691 [(not:SI (match_operator:SI 2
14692 "branch_positive_comparison_operator"
14693 [(match_operand 3
14694 "cc_reg_operand" "y,y")
14695 (const_int 0)]))
14696 (match_operator:SI 4
14697 "branch_positive_comparison_operator"
14698 [(match_operand 5
14699 "cc_reg_operand" "0,y")
14700 (const_int 0)])])
14701 (const_int -1)))]
14702 ""
14703 "cr%q1 %E0,%j2,%j4"
14704 [(set_attr "type" "cr_logical,delayed_cr")])
14706 (define_insn "*cceq_rev_compare"
14707 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14708 (compare:CCEQ (match_operator:SI 1
14709 "branch_positive_comparison_operator"
14710 [(match_operand 2
14711 "cc_reg_operand" "0,y")
14712 (const_int 0)])
14713 (const_int 0)))]
14714 ""
14715 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14716 [(set_attr "type" "cr_logical,delayed_cr")])
14718 ;; If we are comparing the result of two comparisons, this can be done
14719 ;; using creqv or crxor.
14721 (define_insn_and_split ""
14722 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14723 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14724 [(match_operand 2 "cc_reg_operand" "y")
14725 (const_int 0)])
14726 (match_operator 3 "branch_comparison_operator"
14727 [(match_operand 4 "cc_reg_operand" "y")
14728 (const_int 0)])))]
14729 ""
14730 "#"
14731 ""
14732 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14733 (match_dup 5)))]
14734 "
14735 {
14736 int positive_1, positive_2;
14738 positive_1 = branch_positive_comparison_operator (operands[1],
14739 GET_MODE (operands[1]));
14740 positive_2 = branch_positive_comparison_operator (operands[3],
14741 GET_MODE (operands[3]));
14743 if (! positive_1)
14744 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14745 GET_CODE (operands[1])),
14746 SImode,
14747 operands[2], const0_rtx);
14748 else if (GET_MODE (operands[1]) != SImode)
14749 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14750 operands[2], const0_rtx);
14752 if (! positive_2)
14753 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14754 GET_CODE (operands[3])),
14755 SImode,
14756 operands[4], const0_rtx);
14757 else if (GET_MODE (operands[3]) != SImode)
14758 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14759 operands[4], const0_rtx);
14761 if (positive_1 == positive_2)
14762 {
14763 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14764 operands[5] = constm1_rtx;
14765 }
14766 else
14767 {
14768 operands[5] = const1_rtx;
14769 }
14770 }")
14772 ;; Unconditional branch and return.
14774 (define_insn "jump"
14775 [(set (pc)
14776 (label_ref (match_operand 0 "" "")))]
14777 ""
14778 "b %l0"
14779 [(set_attr "type" "branch")])
14781 (define_insn "return"
14782 [(return)]
14783 "direct_return ()"
14784 "{br|blr}"
14785 [(set_attr "type" "jmpreg")])
14787 (define_expand "indirect_jump"
14788 [(set (pc) (match_operand 0 "register_operand" ""))])
14790 (define_insn "*indirect_jump<mode>"
14791 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14792 ""
14793 "@
14794 bctr
14795 {br|blr}"
14796 [(set_attr "type" "jmpreg")])
14798 ;; Table jump for switch statements:
14799 (define_expand "tablejump"
14800 [(use (match_operand 0 "" ""))
14801 (use (label_ref (match_operand 1 "" "")))]
14802 ""
14803 "
14804 {
14805 if (TARGET_32BIT)
14806 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14807 else
14808 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14809 DONE;
14810 }")
14812 (define_expand "tablejumpsi"
14813 [(set (match_dup 3)
14814 (plus:SI (match_operand:SI 0 "" "")
14815 (match_dup 2)))
14816 (parallel [(set (pc) (match_dup 3))
14817 (use (label_ref (match_operand 1 "" "")))])]
14818 "TARGET_32BIT"
14819 "
14820 { operands[0] = force_reg (SImode, operands[0]);
14821 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14822 operands[3] = gen_reg_rtx (SImode);
14823 }")
14825 (define_expand "tablejumpdi"
14826 [(set (match_dup 4)
14827 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14828 (set (match_dup 3)
14829 (plus:DI (match_dup 4)
14830 (match_dup 2)))
14831 (parallel [(set (pc) (match_dup 3))
14832 (use (label_ref (match_operand 1 "" "")))])]
14833 "TARGET_64BIT"
14834 "
14835 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14836 operands[3] = gen_reg_rtx (DImode);
14837 operands[4] = gen_reg_rtx (DImode);
14838 }")
14840 (define_insn "*tablejump<mode>_internal1"
14841 [(set (pc)
14842 (match_operand:P 0 "register_operand" "c,*l"))
14843 (use (label_ref (match_operand 1 "" "")))]
14844 ""
14845 "@
14846 bctr
14847 {br|blr}"
14848 [(set_attr "type" "jmpreg")])
14850 (define_insn "nop"
14851 [(const_int 0)]
14852 ""
14853 "{cror 0,0,0|nop}")
14854 \f
14855 ;; Define the subtract-one-and-jump insns, starting with the template
14856 ;; so loop.c knows what to generate.
14858 (define_expand "doloop_end"
14859 [(use (match_operand 0 "" "")) ; loop pseudo
14860 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14861 (use (match_operand 2 "" "")) ; max iterations
14862 (use (match_operand 3 "" "")) ; loop level
14863 (use (match_operand 4 "" ""))] ; label
14864 ""
14865 "
14866 {
14867 /* Only use this on innermost loops. */
14868 if (INTVAL (operands[3]) > 1)
14869 FAIL;
14870 if (TARGET_64BIT)
14871 {
14872 if (GET_MODE (operands[0]) != DImode)
14873 FAIL;
14874 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14875 }
14876 else
14877 {
14878 if (GET_MODE (operands[0]) != SImode)
14879 FAIL;
14880 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14881 }
14882 DONE;
14883 }")
14885 (define_expand "ctr<mode>"
14886 [(parallel [(set (pc)
14887 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14888 (const_int 1))
14889 (label_ref (match_operand 1 "" ""))
14890 (pc)))
14891 (set (match_dup 0)
14892 (plus:P (match_dup 0)
14893 (const_int -1)))
14894 (clobber (match_scratch:CC 2 ""))
14895 (clobber (match_scratch:P 3 ""))])]
14896 ""
14897 "")
14899 ;; We need to be able to do this for any operand, including MEM, or we
14900 ;; will cause reload to blow up since we don't allow output reloads on
14901 ;; JUMP_INSNs.
14902 ;; For the length attribute to be calculated correctly, the
14903 ;; label MUST be operand 0.
14905 (define_insn "*ctr<mode>_internal1"
14906 [(set (pc)
14907 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14908 (const_int 1))
14909 (label_ref (match_operand 0 "" ""))
14910 (pc)))
14911 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14912 (plus:P (match_dup 1)
14913 (const_int -1)))
14914 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14915 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14916 ""
14917 "*
14918 {
14919 if (which_alternative != 0)
14920 return \"#\";
14921 else if (get_attr_length (insn) == 4)
14922 return \"{bdn|bdnz} %l0\";
14923 else
14924 return \"bdz $+8\;b %l0\";
14925 }"
14926 [(set_attr "type" "branch")
14927 (set_attr "length" "*,12,16,16")])
14929 (define_insn "*ctr<mode>_internal2"
14930 [(set (pc)
14931 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14932 (const_int 1))
14933 (pc)
14934 (label_ref (match_operand 0 "" ""))))
14935 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14936 (plus:P (match_dup 1)
14937 (const_int -1)))
14938 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14939 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14940 ""
14941 "*
14942 {
14943 if (which_alternative != 0)
14944 return \"#\";
14945 else if (get_attr_length (insn) == 4)
14946 return \"bdz %l0\";
14947 else
14948 return \"{bdn|bdnz} $+8\;b %l0\";
14949 }"
14950 [(set_attr "type" "branch")
14951 (set_attr "length" "*,12,16,16")])
14953 ;; Similar but use EQ
14955 (define_insn "*ctr<mode>_internal5"
14956 [(set (pc)
14957 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14958 (const_int 1))
14959 (label_ref (match_operand 0 "" ""))
14960 (pc)))
14961 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14962 (plus:P (match_dup 1)
14963 (const_int -1)))
14964 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14965 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14966 ""
14967 "*
14968 {
14969 if (which_alternative != 0)
14970 return \"#\";
14971 else if (get_attr_length (insn) == 4)
14972 return \"bdz %l0\";
14973 else
14974 return \"{bdn|bdnz} $+8\;b %l0\";
14975 }"
14976 [(set_attr "type" "branch")
14977 (set_attr "length" "*,12,16,16")])
14979 (define_insn "*ctr<mode>_internal6"
14980 [(set (pc)
14981 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14982 (const_int 1))
14983 (pc)
14984 (label_ref (match_operand 0 "" ""))))
14985 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14986 (plus:P (match_dup 1)
14987 (const_int -1)))
14988 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14989 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14990 ""
14991 "*
14992 {
14993 if (which_alternative != 0)
14994 return \"#\";
14995 else if (get_attr_length (insn) == 4)
14996 return \"{bdn|bdnz} %l0\";
14997 else
14998 return \"bdz $+8\;b %l0\";
14999 }"
15000 [(set_attr "type" "branch")
15001 (set_attr "length" "*,12,16,16")])
15003 ;; Now the splitters if we could not allocate the CTR register
15005 (define_split
15006 [(set (pc)
15007 (if_then_else (match_operator 2 "comparison_operator"
15008 [(match_operand:P 1 "gpc_reg_operand" "")
15009 (const_int 1)])
15010 (match_operand 5 "" "")
15011 (match_operand 6 "" "")))
15012 (set (match_operand:P 0 "gpc_reg_operand" "")
15013 (plus:P (match_dup 1) (const_int -1)))
15014 (clobber (match_scratch:CC 3 ""))
15015 (clobber (match_scratch:P 4 ""))]
15016 "reload_completed"
15017 [(parallel [(set (match_dup 3)
15018 (compare:CC (plus:P (match_dup 1)
15019 (const_int -1))
15020 (const_int 0)))
15021 (set (match_dup 0)
15022 (plus:P (match_dup 1)
15023 (const_int -1)))])
15024 (set (pc) (if_then_else (match_dup 7)
15025 (match_dup 5)
15026 (match_dup 6)))]
15027 "
15028 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15029 operands[3], const0_rtx); }")
15031 (define_split
15032 [(set (pc)
15033 (if_then_else (match_operator 2 "comparison_operator"
15034 [(match_operand:P 1 "gpc_reg_operand" "")
15035 (const_int 1)])
15036 (match_operand 5 "" "")
15037 (match_operand 6 "" "")))
15038 (set (match_operand:P 0 "nonimmediate_operand" "")
15039 (plus:P (match_dup 1) (const_int -1)))
15040 (clobber (match_scratch:CC 3 ""))
15041 (clobber (match_scratch:P 4 ""))]
15042 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15043 [(parallel [(set (match_dup 3)
15044 (compare:CC (plus:P (match_dup 1)
15045 (const_int -1))
15046 (const_int 0)))
15047 (set (match_dup 4)
15048 (plus:P (match_dup 1)
15049 (const_int -1)))])
15050 (set (match_dup 0)
15051 (match_dup 4))
15052 (set (pc) (if_then_else (match_dup 7)
15053 (match_dup 5)
15054 (match_dup 6)))]
15055 "
15056 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15057 operands[3], const0_rtx); }")
15058 \f
15059 (define_insn "trap"
15060 [(trap_if (const_int 1) (const_int 0))]
15061 ""
15062 "{t 31,0,0|trap}"
15063 [(set_attr "type" "trap")])
15065 (define_expand "ctrap<mode>4"
15066 [(trap_if (match_operator 0 "ordered_comparison_operator"
15067 [(match_operand:GPR 1 "register_operand")
15068 (match_operand:GPR 2 "reg_or_short_operand")])
15069 (match_operand 3 "zero_constant" ""))]
15070 ""
15071 "")
15073 (define_insn ""
15074 [(trap_if (match_operator 0 "ordered_comparison_operator"
15075 [(match_operand:GPR 1 "register_operand" "r")
15076 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15077 (const_int 0))]
15078 ""
15079 "{t|t<wd>}%V0%I2 %1,%2"
15080 [(set_attr "type" "trap")])
15081 \f
15082 ;; Insns related to generating the function prologue and epilogue.
15084 (define_expand "prologue"
15085 [(use (const_int 0))]
15086 "TARGET_SCHED_PROLOG"
15087 "
15088 {
15089 rs6000_emit_prologue ();
15090 DONE;
15091 }")
15093 (define_insn "*movesi_from_cr_one"
15094 [(match_parallel 0 "mfcr_operation"
15095 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15096 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15097 (match_operand 3 "immediate_operand" "n")]
15098 UNSPEC_MOVESI_FROM_CR))])]
15099 "TARGET_MFCRF"
15100 "*
15101 {
15102 int mask = 0;
15103 int i;
15104 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15105 {
15106 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15107 operands[4] = GEN_INT (mask);
15108 output_asm_insn (\"mfcr %1,%4\", operands);
15109 }
15110 return \"\";
15111 }"
15112 [(set_attr "type" "mfcrf")])
15114 (define_insn "movesi_from_cr"
15115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15116 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15117 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15118 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15119 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15120 UNSPEC_MOVESI_FROM_CR))]
15121 ""
15122 "mfcr %0"
15123 [(set_attr "type" "mfcr")])
15125 (define_insn "*stmw"
15126 [(match_parallel 0 "stmw_operation"
15127 [(set (match_operand:SI 1 "memory_operand" "=m")
15128 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15129 "TARGET_MULTIPLE"
15130 "{stm|stmw} %2,%1"
15131 [(set_attr "type" "store_ux")])
15133 (define_insn "*save_gpregs_<mode>"
15134 [(match_parallel 0 "any_parallel_operand"
15135 [(clobber (reg:P 65))
15136 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15137 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15138 (set (match_operand:P 3 "memory_operand" "=m")
15139 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15140 ""
15141 "bl %z1"
15142 [(set_attr "type" "branch")
15143 (set_attr "length" "4")])
15145 (define_insn "*save_fpregs_<mode>"
15146 [(match_parallel 0 "any_parallel_operand"
15147 [(clobber (reg:P 65))
15148 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15149 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15150 (set (match_operand:DF 3 "memory_operand" "=m")
15151 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15152 ""
15153 "bl %z1"
15154 [(set_attr "type" "branch")
15155 (set_attr "length" "4")])
15157 ; These are to explain that changes to the stack pointer should
15158 ; not be moved over stores to stack memory.
15159 (define_insn "stack_tie"
15160 [(set (match_operand:BLK 0 "memory_operand" "+m")
15161 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15162 ""
15163 ""
15164 [(set_attr "length" "0")])
15167 (define_expand "epilogue"
15168 [(use (const_int 0))]
15169 "TARGET_SCHED_PROLOG"
15170 "
15171 {
15172 rs6000_emit_epilogue (FALSE);
15173 DONE;
15174 }")
15176 ; On some processors, doing the mtcrf one CC register at a time is
15177 ; faster (like on the 604e). On others, doing them all at once is
15178 ; faster; for instance, on the 601 and 750.
15180 (define_expand "movsi_to_cr_one"
15181 [(set (match_operand:CC 0 "cc_reg_operand" "")
15182 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15183 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15184 ""
15185 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15187 (define_insn "*movsi_to_cr"
15188 [(match_parallel 0 "mtcrf_operation"
15189 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15190 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15191 (match_operand 3 "immediate_operand" "n")]
15192 UNSPEC_MOVESI_TO_CR))])]
15193 ""
15194 "*
15195 {
15196 int mask = 0;
15197 int i;
15198 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15199 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15200 operands[4] = GEN_INT (mask);
15201 return \"mtcrf %4,%2\";
15202 }"
15203 [(set_attr "type" "mtcr")])
15205 (define_insn "*mtcrfsi"
15206 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15207 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15208 (match_operand 2 "immediate_operand" "n")]
15209 UNSPEC_MOVESI_TO_CR))]
15210 "GET_CODE (operands[0]) == REG
15211 && CR_REGNO_P (REGNO (operands[0]))
15212 && GET_CODE (operands[2]) == CONST_INT
15213 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15214 "mtcrf %R0,%1"
15215 [(set_attr "type" "mtcr")])
15217 ; The load-multiple instructions have similar properties.
15218 ; Note that "load_multiple" is a name known to the machine-independent
15219 ; code that actually corresponds to the PowerPC load-string.
15221 (define_insn "*lmw"
15222 [(match_parallel 0 "lmw_operation"
15223 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15224 (match_operand:SI 2 "memory_operand" "m"))])]
15225 "TARGET_MULTIPLE"
15226 "{lm|lmw} %1,%2"
15227 [(set_attr "type" "load_ux")
15228 (set_attr "cell_micro" "always")])
15230 (define_insn "*return_internal_<mode>"
15231 [(return)
15232 (use (match_operand:P 0 "register_operand" "lc"))]
15233 ""
15234 "b%T0"
15235 [(set_attr "type" "jmpreg")])
15237 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15238 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15240 (define_insn "*restore_gpregs_<mode>"
15241 [(match_parallel 0 "any_parallel_operand"
15242 [(clobber (match_operand:P 1 "register_operand" "=l"))
15243 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15244 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15245 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15246 (match_operand:P 5 "memory_operand" "m"))])]
15247 ""
15248 "bl %z2"
15249 [(set_attr "type" "branch")
15250 (set_attr "length" "4")])
15252 (define_insn "*return_and_restore_gpregs_<mode>"
15253 [(match_parallel 0 "any_parallel_operand"
15254 [(return)
15255 (clobber (match_operand:P 1 "register_operand" "=l"))
15256 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15257 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15258 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15259 (match_operand:P 5 "memory_operand" "m"))])]
15260 ""
15261 "b %z2"
15262 [(set_attr "type" "branch")
15263 (set_attr "length" "4")])
15265 (define_insn "*return_and_restore_fpregs_<mode>"
15266 [(match_parallel 0 "any_parallel_operand"
15267 [(return)
15268 (clobber (match_operand:P 1 "register_operand" "=l"))
15269 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15270 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15271 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15272 (match_operand:DF 5 "memory_operand" "m"))])]
15273 ""
15274 "b %z2"
15275 [(set_attr "type" "branch")
15276 (set_attr "length" "4")])
15278 ; This is used in compiling the unwind routines.
15279 (define_expand "eh_return"
15280 [(use (match_operand 0 "general_operand" ""))]
15281 ""
15282 "
15283 {
15284 if (TARGET_32BIT)
15285 emit_insn (gen_eh_set_lr_si (operands[0]));
15286 else
15287 emit_insn (gen_eh_set_lr_di (operands[0]));
15288 DONE;
15289 }")
15291 ; We can't expand this before we know where the link register is stored.
15292 (define_insn "eh_set_lr_<mode>"
15293 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15294 UNSPECV_EH_RR)
15295 (clobber (match_scratch:P 1 "=&b"))]
15296 ""
15297 "#")
15299 (define_split
15300 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15301 (clobber (match_scratch 1 ""))]
15302 "reload_completed"
15303 [(const_int 0)]
15304 "
15305 {
15306 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15307 DONE;
15308 }")
15310 (define_insn "prefetch"
15311 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15312 (match_operand:SI 1 "const_int_operand" "n")
15313 (match_operand:SI 2 "const_int_operand" "n"))]
15314 "TARGET_POWERPC"
15315 "*
15316 {
15317 if (GET_CODE (operands[0]) == REG)
15318 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15319 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15320 }"
15321 [(set_attr "type" "load")])
15322 \f
15324 (include "sync.md")
15325 (include "altivec.md")
15326 (include "spe.md")
15327 (include "dfp.md")
15328 (include "paired.md")