gcc/config/picochip/picochip.h

   1 /* Definitions of target machine for GNU compiler for picoChip
   2    Copyright (C) 2001, 2008 Free Software Foundation, Inc.
   3
   4    Contributed by picoChip Designs Ltd. (http://www.picochip.com)
   5    Maintained by Daniel Towner (daniel.towner@picochip.com) and
   6    Hariharan Sandanagobalane (hariharan@picochip.com).
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 3, or (at your option)
  13 any later version.
  14
  15 GCC is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not, see
  22 <http://www.gnu.org/licenses/>. */
  23
  24 /* Which type of DFA scheduling to use - schedule for speed (VLIW), or
  25    schedule for space.  When scheduling for space, attempt to schedule
  26    into stall cycles, but don't pack instructions. */
  27
  28 enum picochip_dfa_type
  29 {
  30   DFA_TYPE_NONE,
  31   DFA_TYPE_SPACE,
  32   DFA_TYPE_SPEED
  33 };
  34
  35 extern enum picochip_dfa_type picochip_schedule_type;
  36
  37 /* Controlling the Compilation Driver */
  38
  39 /* Pass through the save-temps command option. */
  40 #define LINK_SPEC " %{save-temps:--save-temps}"
  41
  42 /* This is an embedded processor, and only supports a cut-down version of
  43  * the standard C library. */
  44 #define LIB_SPEC "-lpicoC"
  45
  46 /* The start file is automatically provided by the linker. */
  47 #define STARTFILE_SPEC ""
  48 \f
  49 /* Run-time Target Specification  */
  50
  51 /* Define some additional pre-processor macros. */
  52 #define TARGET_CPU_CPP_BUILTINS()                       \
  53   do                                                    \
  54     {                                                   \
  55       builtin_define ("NO_TRAMPOLINES");                \
  56       builtin_define ("PICOCHIP");                      \
  57       builtin_define ("__PICOCHIP__");                      \
  58     }                                                   \
  59   while (0)
  60
  61 /* Translate requests for particular AEs into their respective ISA
  62    options. Note that byte access is enabled by default. */
  63 #define TARGET_OPTION_TRANSLATE_TABLE                         \
  64   { "-mae=ANY",   "-mmul-type=none -mno-byte-access" },       \
  65   { "-mae=ANY2",  "-mmul-type=none -mno-byte-access" },       \
  66   { "-mae=ANY3",  "-mmul-type=none" },                        \
  67   { "-mae=STAN",  "-mmul-type=none -mno-byte-access" },       \
  68   { "-mae=STAN2", "-mmul-type=mac -mno-byte-access" },        \
  69   { "-mae=STAN3", "-mmul-type=mac " },                        \
  70   { "-mae=MAC",   "-mmul-type=mac -mno-byte-access" },        \
  71   { "-mae=MUL",   "-mmul-type=mul" },                         \
  72   { "-mae=MEM",   "-mmul-type=mul" },                         \
  73   { "-mae=MEM2",  "-mmul-type=mul" },                         \
  74   { "-mae=CTRL",  "-mmul-type=mul" },                         \
  75   { "-mae=CTRL2", "-mmul-type=mul" }
  76
  77 /* Specify the default options, so that the multilib build doesn't
  78    need to provide special cases for the defaults. */
  79 #define MULTILIB_DEFAULTS \
  80   { "mmul-type=mul", "mbyte-access"}
  81
  82 #define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
  83 #define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
  84 #define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
  85 #define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
  86
  87 /* Allow some options to be overriden.  In particular, the 2nd
  88    scheduling pass option is switched off, and a machine dependent
  89    reorganisation ensures that it is run later on, after the second
  90    jump optimisation. */
  91 #define OVERRIDE_OPTIONS picochip_override_options()
  92
  93 #define CAN_DEBUG_WITHOUT_FP 1
  94
  95 #define TARGET_VERSION fprintf(stderr, "(picoChip)");
  96 \f
  97 /* Storage Layout */
  98
  99 /* picoChip processors are 16-bit machines, little endian. */
 100
 101 #define BITS_BIG_ENDIAN 0
 102 #define BYTES_BIG_ENDIAN 0
 103 #define WORDS_BIG_ENDIAN 0
 104
 105 #define BITS_PER_UNIT 8
 106
 107 #define BITS_PER_WORD 16
 108 #define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
 109
 110 #define POINTER_SIZE BITS_PER_WORD
 111
 112 /* Promote those modes that are smaller than an int, to int mode.  */
 113 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
 114   ((GET_MODE_CLASS (MODE) == MODE_INT                   \
 115       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)         \
 116       ? (MODE) = HImode : 0)
 117
 118 /* All parameters are at least this aligned.  Parameters are passed
 119    one-per-register. */
 120 #define PARM_BOUNDARY BITS_PER_WORD
 121
 122 /* The main stack pointer is guaranteed to be aligned to the most
 123    strict data alignment. */
 124 #define STACK_BOUNDARY 32
 125
 126 /* Function entry point is byte aligned. */
 127 #define FUNCTION_BOUNDARY 8
 128
 129 /* This is the biggest alignment that can be allowed on this machine.
 130    Since the STANs have only 256 byte memory, it doesnt make sense
 131    to have alignments greater than 32 bytes. Hence the value */
 132 #define MAX_OFILE_ALIGNMENT 32*8
 133
 134 /* The strictest data object alignment, which repesents a register pair. */
 135 #define BIGGEST_ALIGNMENT 32
 136
 137 /* The hardware doesn't allow unaligned memory access.  */
 138 #define STRICT_ALIGNMENT 1
 139
 140 /* We want the 'unix' style bitfield packing algorithm.  */
 141 #define PCC_BITFIELD_TYPE_MATTERS 1
 142
 143 /* Support up to 64-bit integers. */
 144 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
 145
 146 /* We don't support floating point, but give it a sensible definition. */
 147 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 148 \f
 149 /* Layout of Source Language Data Types.  */
 150
 151 #define INT_TYPE_SIZE BITS_PER_WORD
 152
 153 /* The normal sizes for C scalar data. */
 154 #define CHAR_TYPE_SIZE 8
 155 #define SHORT_TYPE_SIZE 16
 156 #define LONG_TYPE_SIZE 32
 157 #define LONG_LONG_TYPE_SIZE 64
 158
 159 /* We don't support the following data types, but still give them
 160    sensible values.  */
 161 #define FLOAT_TYPE_SIZE 32
 162 #define DOUBLE_TYPE_SIZE 32
 163 #define LONG_DOUBLE_TYPE_SIZE 32
 164
 165 /* Plain `char' is a signed type, since the hardware sign-extends
 166    bytes when loading them from memory into a register. */
 167 #define DEFAULT_SIGNED_CHAR 1
 168
 169 /* Note that the names of the types used in the following macros must
 170    be precisely the same as those defined internally in gcc.  For
 171    example, `unsigned short' wouldn't work as a type string, since gcc
 172    doesn't define any type with this exact string.  The correct string
 173    to use is `short unsigned int'. */
 174
 175 #define SIZE_TYPE "unsigned int"
 176
 177 #define PTRDIFF_TYPE "int"
 178
 179 #define WCHAR_TYPE "short unsigned int"
 180 #define WCHAR_TYPE_SIZE 16
 181
 182 #define WINT_TYPE "unsigned int"
 183 \f
 184 /* Register Usage  */
 185
 186 /* Picochip has 16 16-bit registers, a condition code register and an
 187    (inaccessible) instruction pointer.  One of these registers (r15) is
 188    special, and is either used to load a constant anywhere a register
 189    can normally be used, or is used to specify a dummy destination
 190    (e.g., when setting condition flags).  We also define some pseudo
 191    registers to represent condition codes, the frame pointer and the
 192    argument pointer.  The latter two are eliminated wherever possible.
 193
 194    Pairs of general registers may be combined to form 32-bit registers.
 195
 196    The picoChip registers are as follows:
 197
 198    0..1 - function return value
 199    0..5 - first 6 function parameters
 200    6..11 - General purpose
 201    12 - link register
 202    13 - stack pointer
 203    14 - specialized pointer
 204    15 - long constant or /dev/null
 205    (16) acc0
 206    (17) pseudo condition code
 207    (18) pseudo frame pointer
 208    (19) pseudo arg pointer
 209
 210    Registers 0..6, 12, 13, 14, 15 are caller save
 211    Registers 0..12, 14 are available to the register allocator.
 212
 213    In addition, the DSP variant of the ISA allows extra accumulator
 214    registers to be accessed.  These are special purpose registers,
 215    which are not currently used by the compiler.
 216
 217   */
 218
 219 /* Basic Characteristics of Registers  */
 220
 221 /* We have 16 hard registers plus 3 pseudo hard registers and an accumulator.  */
 222 #define FIRST_PSEUDO_REGISTER 20
 223
 224 /* The first non-hard register.  Only used internally by the picoChip port. */
 225 #define FIRST_NONHARD_REGISTER 18
 226
 227 /* Cannot use SP, CST, CC, FP, AP */
 228 #define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
 229
 230 /* Those that are clobbered by a function call (includes pseudo-regs) */
 231 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
 232 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
 233
 234 /* Define the number of the picoChip link and condition psuedo registers. */
 235 #define LINK_REGNUM 12
 236 #define CC_REGNUM 17
 237 #define ACC_REGNUM 16
 238
 239 /* Order of Allocation of Registers  */
 240
 241 /* The registers are allocated starting with the caller-clobbered
 242    registers, in reverse order.  The registers are then listed in an
 243    order which means that they are efficiently saved in pairs (i.e.,
 244    one 32-bit store can be used instead of two 16-bit stores to save
 245    the registers into the stack). The exception to this is the use of
 246    r14 (AP) register, which also appears early on.  This is because the
 247    AP register can be used to encode memory operations more
 248    efficiently than other registers.  Some code can be made more
 249    compact as a result. */
 250    /* My current feeling is that r14 should go to the end and maybe even r12.
 251    It seems like the overhead of store/load that will occur since we cant
 252    pair anything up with r14 will be higher than the advantage of smaller
 253    encoding.
 254    Also r12 is put towards the end for leaf functions. Since leaf functions
 255    do not have any calls, the prologue/epilogue for them wouldnt save up/
 256    restore its value. So, it doesnt make sense for us to use it in the middle,
 257    if we can avoid it. */
 258 #define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
 259 #define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
 260
 261 /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
 262    It would be desirable to change it for leaf functions so we can put
 263    r12 at the end of this list.*/
 264 #define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc ()
 265
 266 /* How Values Fit in Registers  */
 267
 268 /* Number of consecutive hard regs needed starting at reg REGNO
 269    to hold something of mode MODE.  */
 270 #define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
 271
 272 /* Is it ok to place MODE in REGNO?  Require that the register number
 273    be aligned. */
 274 #define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
 275
 276 #define MODES_TIEABLE_P(MODE1,MODE2) 1
 277
 278 /* Don't copy the cc register ('cos you can't put it back).  */
 279 #define AVOID_CCMODE_COPIES 1
 280 \f
 281 /* Register Classes */
 282
 283 enum reg_class
 284 {
 285   NO_REGS,                      /* no registers in set */
 286   FRAME_REGS,                   /* registers with a long offset  */
 287   PTR_REGS,                     /* registers without an offset  */
 288   CONST_REGS,                   /* registers for long constants  */
 289   NULL_REGS,                    /* registers which ignore writes  */
 290   CC_REGS,                      /* condition code registers  */
 291   ACC_REGS,                     /* Accumulator registers  */
 292   TWIN_REGS,                    /* registers which can be paired */
 293   GR_REGS,                      /* general purpose registers */
 294   ALL_REGS,                     /* all registers */
 295   LIM_REG_CLASSES,              /* max value + 1 */
 296
 297   /* Some aliases  */
 298   GENERAL_REGS = GR_REGS
 299 };
 300
 301 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 302
 303 /* The following macro defines cover classes for Integrated Register
 304    Allocator.  Cover classes is a set of non-intersected register
 305    classes covering all hard registers used for register allocation
 306    purpose.  Any move between two registers of a cover class should be
 307    cheaper than load or store of the registers.  The macro value is
 308    array of register classes with LIM_REG_CLASSES used as the end
 309    marker.  */
 310
 311 #define IRA_COVER_CLASSES                                               \
 312 {                                                                       \
 313   GR_REGS, LIM_REG_CLASSES                                              \
 314 }
 315
 316
 317 /* The names of the register classes  */
 318 #define REG_CLASS_NAMES                                                 \
 319 {                                                                       \
 320   "NO_REGS",                                                            \
 321   "FRAME_REGS",                                                         \
 322   "PTR_REGS",                                                           \
 323   "CONST_REGS",                                                         \
 324   "NULL_REGS",                                                          \
 325   "CC_REGS",                                                            \
 326   "ACC_REGS",                                                           \
 327   "TWIN_REGS",                                                          \
 328   "GR_REGS",                                                            \
 329   "ALL_REGS"                                                            \
 330 }
 331
 332 /* Each reg class is an array of 32-bit integers.  Each array must be
 333    long enough to store one bit for every pseudo register. Thus in the
 334    following code, each array only stores one 32-bit value. */
 335 #define REG_CLASS_CONTENTS                                              \
 336 {                                                                       \
 337   {0x00000000}, /* no registers */                                      \
 338   {0x00002000}, /* frame */                                             \
 339   {0x00004000}, /* pointer  */                                          \
 340   {0x00008000}, /* const */                                             \
 341   {0x00008000}, /* null  */                                             \
 342   {0x00020000}, /* cc */                                                \
 343   {0x00010000}, /* acc0 */                                              \
 344   {0x00000FFF}, /* twin */                                              \
 345   {0x000CFFFF}, /* general registers - includes pseudo-arg */           \
 346   {0x000FFFFF}  /* all registers - includes pseudo-arg */               \
 347 }
 348
 349 /* The earliest register class containing the given register.  */
 350 extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
 351 #define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
 352
 353 /* Any register can be a base pointer.  */
 354 #define BASE_REG_CLASS GR_REGS
 355
 356 /* Any register can be an index.  */
 357 #define INDEX_REG_CLASS GR_REGS
 358
 359 #define REGNO_OK_FOR_BASE_P(REGNO)                                      \
 360   (REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
 361
 362 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 363
 364 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
 365
 366 #define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
 367
 368 \f
 369 /* Stack Layout and Calling Conventions  */
 370
 371 #define STACK_GROWS_DOWNWARD 1
 372
 373 /* The frame pointer points to the outgoing argument area, so the
 374    locals are above that.  */
 375 #define STARTING_FRAME_OFFSET 0
 376
 377 #define FIRST_PARM_OFFSET(FNDECL) 0
 378
 379 /* Specify where the return address lives before entry to the
 380    prologue.  This is required to enable DWARF debug information to be
 381    generated. */
 382 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, LINK_REGNUM)
 383
 384 #define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
 385
 386 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
 387
 388 /* Registers that Address the Stack Frame  */
 389
 390 #define STACK_POINTER_REGNUM 13
 391 #define FRAME_POINTER_REGNUM 18
 392 #define ARG_POINTER_REGNUM   19
 393
 394 /* Static chain is used to pass the local variables of the enclosing function.
 395    The static chain is passed in memory. The first long-word location
 396    beneath the stack pointer is used. In the presence of pretend
 397    arguments, which are written into that location, this mechanism
 398    complicates matters. */
 399
 400 /* Location seen by the caller. */
 401 #define STATIC_CHAIN                                                    \
 402   gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -2 * UNITS_PER_WORD))
 403
 404 /* Location seen by the callee. */
 405 #define STATIC_CHAIN_INCOMING                                           \
 406   gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, 0))
 407
 408 /* Eliminating Frame Pointer and Arg Pointer.  The frame and argument
 409    pointers are eliminated wherever possible, by replacing them with
 410    offsets from the stack pointer. */
 411
 412 #define ELIMINABLE_REGS                                                 \
 413   {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},                          \
 414    {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
 415
 416 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
 417   OFFSET = initial_elimination_offset(FROM, TO);
 418
 419 #define ACCUMULATE_OUTGOING_ARGS 1
 420
 421 #define PUSH_ARGS 0
 422
 423 /* Functions don't pop their args.  */
 424 #define RETURN_POPS_ARGS(FNDECL, FNTYPE, STACK) 0
 425
 426 /* Passing Arguments in Registers  */
 427
 428 /* Store the offset of the next argument. */
 429 #define CUMULATIVE_ARGS unsigned
 430
 431 /* Decide how function arguments are handled. */
 432 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
 433   picochip_function_arg (CUM, MODE, TYPE, NAMED)
 434
 435 /* Incoming arguments are always the same as normal arguments, except
 436    for a function which uses variadic arguments, in which case all
 437    arguments are effectively passed on the stack. */
 438 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
 439   picochip_incoming_function_arg(CUM, MODE, TYPE, NAMED)
 440
 441 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
 442   ((CUM) = 0)
 443
 444 #define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \
 445   (CUM) = picochip_arg_advance (CUM, MODE, TYPE, NAMED)
 446
 447 /* Originally this used TYPE_ALIGN to determine the
 448    alignment.  Unfortunately, this fails in some cases, because the
 449    type is unknown (e.g., libcall's). Instead, use GET_MODE_ALIGNMENT
 450    since the mode is always present. */
 451 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
 452   picochip_get_function_arg_boundary(MODE)
 453
 454 /* The first 6 registers can hold parameters.  */
 455 #define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
 456
 457 /* How Scalar Function Values are Returned
 458    Do we need this?? */
 459 #define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
 460
 461 #define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
 462
 463 /* Results are in register zero.  If an SImode register is returned,
 464    reg0 will suffice to mean R[0:1]. */
 465 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
 466
 467 /* Don't automatically pass struct's in memory - use the
 468  * RETURN_IN_MEMORY macro to determine when structs are returned in
 469  * memory, and when in registers. */
 470 #define DEFAULT_PCC_STRUCT_RETURN 0
 471
 472 /* Function Entry and Exit  */
 473
 474 /* The epilogue doesn't clobber anything.  */
 475 #define EPILOGUE_USES(REGNO) 0
 476
 477 /* Generating Code for Profiling.  No profiling implemented  */
 478
 479 #define FUNCTION_PROFILER(FILE,LABELNO)
 480 \f
 481 /* Trampolines for Nested Functions  */
 482
 483 /* No trampolines.  */
 484 #define TRAMPOLINE_SIZE 0
 485 #define INITIALIZE_TRAMPOLINE(ADDR,FNADDR,CHAIN)
 486 \f
 487 /* Addressing Modes  */
 488
 489 #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
 490
 491 #define MAX_REGS_PER_ADDRESS 1
 492
 493 /* Legitimize reload address tries machine dependent means of
 494    reloading addresses.  There seems to be a strange error in gcc,
 495    which necessitates this macro.  Consider:
 496
 497      set (reg A) (symbol_ref)
 498      set (reg B) (plus (reg A) (const_int))
 499
 500    A symbol_ref is a valid constant, so the symbol_ref is propagated
 501    into the second instruction to generate the instruction:
 502
 503      set (reg B) (plus (symbol_ref) (const_int))
 504
 505    This is an invalid address, and find_reloads_address correctly
 506    determines this.  However, that function doesn't generate a valid
 507    replacement for the now invalid address, and the invalid address is
 508    output into the assembly language.  To fix the problem without
 509    changing gcc itself, the following macro tests when such an invalid
 510    address has been computed, and wraps it up inside a constant rtx.  A
 511    constant rtx can be correctly reloaded by the function, and hence
 512    correct code is generated. */
 513
 514 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)          \
 515 if (picochip_symbol_offset(X)) { X = gen_rtx_CONST(MODE, X); }
 516
 517 /* Nonzero if the constant rtx X is a legitimate general operand.  X
 518    satisfies CONSTANT_P.  */
 519
 520 #define LEGITIMATE_CONSTANT_P(X) 1
 521
 522 \f
 523 /* Condition Code Status  */
 524
 525 #define CC_STATUS_MDEP unsigned
 526 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
 527 \f
 528 /* Describing Relative Costs of Operations  */
 529
 530 /* Bytes are no faster than words.  */
 531 #define SLOW_BYTE_ACCESS 1
 532
 533 /* The assembler is often able to optimise function call branches, so
 534    don't try to CSE them in the compiler. This was the thinking before.
 535    But now, we realise that the benefits from CSE would mostly outweigh
 536    the disadvantages. */
 537 #define NO_FUNCTION_CSE
 538
 539 \f
 540 /* Dividing the Output into Sections  */
 541
 542 #define TEXT_SECTION_ASM_OP ".section .text\n"
 543 #define DATA_SECTION_ASM_OP ".section .data\n"
 544 #define BSS_SECTION_ASM_OP ".section .bss\n"
 545 /* picoChip is Harvard (separate data/instruction memories), so
 546    read-only data must go into the data section. */
 547 #define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
 548 \f
 549 /* Defining the Output Assembler Language  */
 550
 551 /* The Overall Framework of an Assembler File  */
 552
 553 #define ASM_FILE_COMMENT "// "
 554
 555 #define ASM_APP_ON "// High-level ASM start\n"
 556 #define ASM_APP_OFF "// High-level ASM end\n"
 557
 558 #define ASM_OUTPUT_IDENT(STREAM,STRING) fprintf(STREAM, ".ident %s\n", STRING)
 559
 560 /* Output of Data  */
 561
 562 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
 563
 564 /* Output of Uninitialized Variables  */
 565 #define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
 566   picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
 567
 568 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
 569   picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
 570
 571 /* Output and Generation of Labels  */
 572
 573 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
 574   do { picochip_output_label(STREAM, NAME); } while (0);
 575
 576 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 577   { picochip_output_labelref(STREAM, NAME); }
 578
 579 /* Format must match that of picochip_output_label. */
 580 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
 581  picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
 582
 583 #define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
 584
 585 /* Store in OUTPUT a string (made with alloca) containing an
 586    assembler-name for a local static variable named NAME.  LABELNO is
 587    an integer which is different for each call.  The assembler can't
 588    use periods to generate the name, so we use a ___ separator
 589    instead. */
 590
 591 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  \
 592 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15),    \
 593   sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
 594
 595 /* Macros Controlling Initialization Routines  */
 596
 597 /* By defining this, the main function won't try to call `__main'. */
 598 #define HAS_INIT_SECTION
 599
 600 /* Output of Assembler Instructions  */
 601
 602 #define REGISTER_NAMES                                                  \
 603 {"R0",  "R1",  "R2",  "R3",                                             \
 604  "R4",  "R5",  "R6",  "R7",                                             \
 605  "R8",  "R9",  "R10", "R11",                                            \
 606  "R12", "FP", "R14", "R15",                                             \
 607  "acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
 608
 609 #define ADDITIONAL_REGISTER_NAMES                                       \
 610 {                                                                       \
 611   { "R0",        0},                                                    \
 612   { "R1",        1},                                                    \
 613   { "R2",        2},                                                    \
 614   { "R3",        3},                                                    \
 615   { "R4",        4},                                                    \
 616   { "R5",        5},                                                    \
 617   { "R6",        6},                                                    \
 618   { "R7",        7},                                                    \
 619   { "R8",        8},                                                    \
 620   { "R9",        9},                                                    \
 621   { "R10",      10},                                                    \
 622   { "R11",      11},                                                    \
 623   { "R12",      12},                                                    \
 624   { "FP",       13},                                                    \
 625   { "R14",      14},                                                    \
 626   { "R15",      15},                                                    \
 627   { "acc0",     16},                                                    \
 628   { "sp",       12}, /* ABI stack pointer */                            \
 629   { "ln",       13}, /* arch link register */                           \
 630   { "ptr",      14}, /* arch constant pointer */                        \
 631   { "rc",       15}, /* arch constant register */                       \
 632   { "rz",       15}, /* arch zero */                                    \
 633 }
 634
 635 /* Final prescan insn is called just before an instruction is
 636    output.  In our case, we use this to detect the VLIW slot to which
 637    the instruction has been assigned, preparatory to generating the
 638    VLIW output in ASM_OUTPUT_OPCODE. */
 639 #define FINAL_PRESCAN_INSN(insn, operand, nop) \
 640   picochip_final_prescan_insn (insn, operand,nop)
 641
 642 #define ASM_OUTPUT_OPCODE(FILE,PTR) \
 643   { PTR = picochip_asm_output_opcode(FILE, PTR); }
 644
 645 #define PRINT_OPERAND(STREAM,X,CODE) \
 646   picochip_print_operand(STREAM, X, CODE)
 647
 648 #define PRINT_OPERAND_PUNCT_VALID_P(code) \
 649   (((code) == '|') || ((code) == '#') || ((code) == '>'))
 650
 651 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
 652   picochip_print_operand_address(STREAM,X)
 653
 654 /* Output of Dispatch Tables  */
 655
 656 /* Initialise a data memory location to an absolute code label.  Used
 657    for building switch statement jump tables.  Note - the format of the
 658    label must match that of the function picochip_output_label. */
 659 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 660   fprintf (stream, ".initWord _L%d\n", value);
 661
 662 /* Assembler Commands for Alignment  */
 663
 664 #define ASM_OUTPUT_SKIP(STREAM,BYTES) \
 665   fprintf(STREAM, ".skip %u\n", BYTES);
 666 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 667   fprintf(STREAM, ".align %u\n", 1 << POWER);
 668
 669 /* The elaborator doesn't output zero bytes in the text section. */
 670 #define ASM_NO_SKIP_IN_TEXT 1
 671 \f
 672 /* Controlling Debugging Information Format  */
 673
 674 /* Macros Affecting All Debugging Formats  */
 675
 676 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
 677
 678 #define DWARF2_DEBUGGING_INFO
 679 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 680 #define DWARF2_FRAME_INFO 1
 681
 682 /* Generate .file/.loc directives, so that the assembler generates the
 683    line table. */
 684 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 685 \f
 686 /* Miscellaneous Parameters  */
 687
 688 #define CASE_VECTOR_MODE HImode
 689 #define WORD_REGISTER_OPERATIONS
 690 #define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
 691 #define MOVE_MAX 4
 692 #define SHIFT_COUNT_TRUNCATED 1
 693 #define Pmode HImode
 694 #define FUNCTION_MODE QImode
 695 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
 696
 697 #define ASM_LONG ":TODO:.word\t"
 698
 699 /* Define builtins for selected special-purpose instructions. */
 700 enum picochip_builtins
 701 {
 702   PICOCHIP_BUILTIN_SBC,
 703   PICOCHIP_BUILTIN_PUT,
 704   PICOCHIP_BUILTIN_GET,
 705   PICOCHIP_BUILTIN_TESTPORT,
 706   PICOCHIP_BUILTIN_COPYSW,
 707   PICOCHIP_BUILTIN_ADDS,
 708   PICOCHIP_BUILTIN_SUBS,
 709   PICOCHIP_BUILTIN_BREV,
 710   PICOCHIP_BUILTIN_BYTESWAP,
 711   PICOCHIP_BUILTIN_GET_ARRAY,
 712   PICOCHIP_BUILTIN_PUT_ARRAY,
 713   PICOCHIP_BUILTIN_TESTPORT_ARRAY,
 714   PICOCHIP_BUILTIN_ASRI,
 715   PICOCHIP_BUILTIN_HALT
 716 };
 717
 718 #define NO_DOLLAR_IN_LABEL 1
 719 #define NO_DOT_IN_LABEL 1
 720
 721 /* The assembler does support LEB128, despite the auto-configure test
 722    not detecting this. */
 723 #define HAVE_AS_LEB128 1
 724
 725 /* The End */