1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "print-tree.h"
30 #include "stringpool.h"
31 #include "stor-layout.h"
36 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
40 #include "insn-attr.h"
52 #include "diagnostic-core.h"
54 #include "dominance.h"
60 #include "cfgcleanup.h"
61 #include "basic-block.h"
64 #include "target-def.h"
66 #include "langhooks.h"
67 #include "insn-codes.h"
69 #include "hash-table.h"
70 #include "tree-ssa-alias.h"
71 #include "internal-fn.h"
72 #include "gimple-fold.h"
74 #include "gimple-expr.h"
82 #include "tree-pass.h"
87 /* Define the specific costs for a given cpu. */
89 struct processor_costs
92 const int m
; /* cost of an M instruction. */
93 const int mghi
; /* cost of an MGHI instruction. */
94 const int mh
; /* cost of an MH instruction. */
95 const int mhi
; /* cost of an MHI instruction. */
96 const int ml
; /* cost of an ML instruction. */
97 const int mr
; /* cost of an MR instruction. */
98 const int ms
; /* cost of an MS instruction. */
99 const int msg
; /* cost of an MSG instruction. */
100 const int msgf
; /* cost of an MSGF instruction. */
101 const int msgfr
; /* cost of an MSGFR instruction. */
102 const int msgr
; /* cost of an MSGR instruction. */
103 const int msr
; /* cost of an MSR instruction. */
104 const int mult_df
; /* cost of multiplication in DFmode. */
107 const int sqxbr
; /* cost of square root in TFmode. */
108 const int sqdbr
; /* cost of square root in DFmode. */
109 const int sqebr
; /* cost of square root in SFmode. */
110 /* multiply and add */
111 const int madbr
; /* cost of multiply and add in DFmode. */
112 const int maebr
; /* cost of multiply and add in SFmode. */
124 const struct processor_costs
*s390_cost
;
127 struct processor_costs z900_cost
=
129 COSTS_N_INSNS (5), /* M */
130 COSTS_N_INSNS (10), /* MGHI */
131 COSTS_N_INSNS (5), /* MH */
132 COSTS_N_INSNS (4), /* MHI */
133 COSTS_N_INSNS (5), /* ML */
134 COSTS_N_INSNS (5), /* MR */
135 COSTS_N_INSNS (4), /* MS */
136 COSTS_N_INSNS (15), /* MSG */
137 COSTS_N_INSNS (7), /* MSGF */
138 COSTS_N_INSNS (7), /* MSGFR */
139 COSTS_N_INSNS (10), /* MSGR */
140 COSTS_N_INSNS (4), /* MSR */
141 COSTS_N_INSNS (7), /* multiplication in DFmode */
142 COSTS_N_INSNS (13), /* MXBR */
143 COSTS_N_INSNS (136), /* SQXBR */
144 COSTS_N_INSNS (44), /* SQDBR */
145 COSTS_N_INSNS (35), /* SQEBR */
146 COSTS_N_INSNS (18), /* MADBR */
147 COSTS_N_INSNS (13), /* MAEBR */
148 COSTS_N_INSNS (134), /* DXBR */
149 COSTS_N_INSNS (30), /* DDBR */
150 COSTS_N_INSNS (27), /* DEBR */
151 COSTS_N_INSNS (220), /* DLGR */
152 COSTS_N_INSNS (34), /* DLR */
153 COSTS_N_INSNS (34), /* DR */
154 COSTS_N_INSNS (32), /* DSGFR */
155 COSTS_N_INSNS (32), /* DSGR */
159 struct processor_costs z990_cost
=
161 COSTS_N_INSNS (4), /* M */
162 COSTS_N_INSNS (2), /* MGHI */
163 COSTS_N_INSNS (2), /* MH */
164 COSTS_N_INSNS (2), /* MHI */
165 COSTS_N_INSNS (4), /* ML */
166 COSTS_N_INSNS (4), /* MR */
167 COSTS_N_INSNS (5), /* MS */
168 COSTS_N_INSNS (6), /* MSG */
169 COSTS_N_INSNS (4), /* MSGF */
170 COSTS_N_INSNS (4), /* MSGFR */
171 COSTS_N_INSNS (4), /* MSGR */
172 COSTS_N_INSNS (4), /* MSR */
173 COSTS_N_INSNS (1), /* multiplication in DFmode */
174 COSTS_N_INSNS (28), /* MXBR */
175 COSTS_N_INSNS (130), /* SQXBR */
176 COSTS_N_INSNS (66), /* SQDBR */
177 COSTS_N_INSNS (38), /* SQEBR */
178 COSTS_N_INSNS (1), /* MADBR */
179 COSTS_N_INSNS (1), /* MAEBR */
180 COSTS_N_INSNS (60), /* DXBR */
181 COSTS_N_INSNS (40), /* DDBR */
182 COSTS_N_INSNS (26), /* DEBR */
183 COSTS_N_INSNS (176), /* DLGR */
184 COSTS_N_INSNS (31), /* DLR */
185 COSTS_N_INSNS (31), /* DR */
186 COSTS_N_INSNS (31), /* DSGFR */
187 COSTS_N_INSNS (31), /* DSGR */
191 struct processor_costs z9_109_cost
=
193 COSTS_N_INSNS (4), /* M */
194 COSTS_N_INSNS (2), /* MGHI */
195 COSTS_N_INSNS (2), /* MH */
196 COSTS_N_INSNS (2), /* MHI */
197 COSTS_N_INSNS (4), /* ML */
198 COSTS_N_INSNS (4), /* MR */
199 COSTS_N_INSNS (5), /* MS */
200 COSTS_N_INSNS (6), /* MSG */
201 COSTS_N_INSNS (4), /* MSGF */
202 COSTS_N_INSNS (4), /* MSGFR */
203 COSTS_N_INSNS (4), /* MSGR */
204 COSTS_N_INSNS (4), /* MSR */
205 COSTS_N_INSNS (1), /* multiplication in DFmode */
206 COSTS_N_INSNS (28), /* MXBR */
207 COSTS_N_INSNS (130), /* SQXBR */
208 COSTS_N_INSNS (66), /* SQDBR */
209 COSTS_N_INSNS (38), /* SQEBR */
210 COSTS_N_INSNS (1), /* MADBR */
211 COSTS_N_INSNS (1), /* MAEBR */
212 COSTS_N_INSNS (60), /* DXBR */
213 COSTS_N_INSNS (40), /* DDBR */
214 COSTS_N_INSNS (26), /* DEBR */
215 COSTS_N_INSNS (30), /* DLGR */
216 COSTS_N_INSNS (23), /* DLR */
217 COSTS_N_INSNS (23), /* DR */
218 COSTS_N_INSNS (24), /* DSGFR */
219 COSTS_N_INSNS (24), /* DSGR */
223 struct processor_costs z10_cost
=
225 COSTS_N_INSNS (10), /* M */
226 COSTS_N_INSNS (10), /* MGHI */
227 COSTS_N_INSNS (10), /* MH */
228 COSTS_N_INSNS (10), /* MHI */
229 COSTS_N_INSNS (10), /* ML */
230 COSTS_N_INSNS (10), /* MR */
231 COSTS_N_INSNS (10), /* MS */
232 COSTS_N_INSNS (10), /* MSG */
233 COSTS_N_INSNS (10), /* MSGF */
234 COSTS_N_INSNS (10), /* MSGFR */
235 COSTS_N_INSNS (10), /* MSGR */
236 COSTS_N_INSNS (10), /* MSR */
237 COSTS_N_INSNS (1) , /* multiplication in DFmode */
238 COSTS_N_INSNS (50), /* MXBR */
239 COSTS_N_INSNS (120), /* SQXBR */
240 COSTS_N_INSNS (52), /* SQDBR */
241 COSTS_N_INSNS (38), /* SQEBR */
242 COSTS_N_INSNS (1), /* MADBR */
243 COSTS_N_INSNS (1), /* MAEBR */
244 COSTS_N_INSNS (111), /* DXBR */
245 COSTS_N_INSNS (39), /* DDBR */
246 COSTS_N_INSNS (32), /* DEBR */
247 COSTS_N_INSNS (160), /* DLGR */
248 COSTS_N_INSNS (71), /* DLR */
249 COSTS_N_INSNS (71), /* DR */
250 COSTS_N_INSNS (71), /* DSGFR */
251 COSTS_N_INSNS (71), /* DSGR */
255 struct processor_costs z196_cost
=
257 COSTS_N_INSNS (7), /* M */
258 COSTS_N_INSNS (5), /* MGHI */
259 COSTS_N_INSNS (5), /* MH */
260 COSTS_N_INSNS (5), /* MHI */
261 COSTS_N_INSNS (7), /* ML */
262 COSTS_N_INSNS (7), /* MR */
263 COSTS_N_INSNS (6), /* MS */
264 COSTS_N_INSNS (8), /* MSG */
265 COSTS_N_INSNS (6), /* MSGF */
266 COSTS_N_INSNS (6), /* MSGFR */
267 COSTS_N_INSNS (8), /* MSGR */
268 COSTS_N_INSNS (6), /* MSR */
269 COSTS_N_INSNS (1) , /* multiplication in DFmode */
270 COSTS_N_INSNS (40), /* MXBR B+40 */
271 COSTS_N_INSNS (100), /* SQXBR B+100 */
272 COSTS_N_INSNS (42), /* SQDBR B+42 */
273 COSTS_N_INSNS (28), /* SQEBR B+28 */
274 COSTS_N_INSNS (1), /* MADBR B */
275 COSTS_N_INSNS (1), /* MAEBR B */
276 COSTS_N_INSNS (101), /* DXBR B+101 */
277 COSTS_N_INSNS (29), /* DDBR */
278 COSTS_N_INSNS (22), /* DEBR */
279 COSTS_N_INSNS (160), /* DLGR cracked */
280 COSTS_N_INSNS (160), /* DLR cracked */
281 COSTS_N_INSNS (160), /* DR expanded */
282 COSTS_N_INSNS (160), /* DSGFR cracked */
283 COSTS_N_INSNS (160), /* DSGR cracked */
287 struct processor_costs zEC12_cost
=
289 COSTS_N_INSNS (7), /* M */
290 COSTS_N_INSNS (5), /* MGHI */
291 COSTS_N_INSNS (5), /* MH */
292 COSTS_N_INSNS (5), /* MHI */
293 COSTS_N_INSNS (7), /* ML */
294 COSTS_N_INSNS (7), /* MR */
295 COSTS_N_INSNS (6), /* MS */
296 COSTS_N_INSNS (8), /* MSG */
297 COSTS_N_INSNS (6), /* MSGF */
298 COSTS_N_INSNS (6), /* MSGFR */
299 COSTS_N_INSNS (8), /* MSGR */
300 COSTS_N_INSNS (6), /* MSR */
301 COSTS_N_INSNS (1) , /* multiplication in DFmode */
302 COSTS_N_INSNS (40), /* MXBR B+40 */
303 COSTS_N_INSNS (100), /* SQXBR B+100 */
304 COSTS_N_INSNS (42), /* SQDBR B+42 */
305 COSTS_N_INSNS (28), /* SQEBR B+28 */
306 COSTS_N_INSNS (1), /* MADBR B */
307 COSTS_N_INSNS (1), /* MAEBR B */
308 COSTS_N_INSNS (131), /* DXBR B+131 */
309 COSTS_N_INSNS (29), /* DDBR */
310 COSTS_N_INSNS (22), /* DEBR */
311 COSTS_N_INSNS (160), /* DLGR cracked */
312 COSTS_N_INSNS (160), /* DLR cracked */
313 COSTS_N_INSNS (160), /* DR expanded */
314 COSTS_N_INSNS (160), /* DSGFR cracked */
315 COSTS_N_INSNS (160), /* DSGR cracked */
318 extern int reload_completed
;
320 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
321 static rtx_insn
*last_scheduled_insn
;
323 /* Structure used to hold the components of a S/390 memory
324 address. A legitimate address on S/390 is of the general
326 base + index + displacement
327 where any of the components is optional.
329 base and index are registers of the class ADDR_REGS,
330 displacement is an unsigned 12-bit immediate constant. */
341 /* The following structure is embedded in the machine
342 specific part of struct function. */
344 struct GTY (()) s390_frame_layout
346 /* Offset within stack frame. */
347 HOST_WIDE_INT gprs_offset
;
348 HOST_WIDE_INT f0_offset
;
349 HOST_WIDE_INT f4_offset
;
350 HOST_WIDE_INT f8_offset
;
351 HOST_WIDE_INT backchain_offset
;
353 /* Number of first and last gpr where slots in the register
354 save area are reserved for. */
355 int first_save_gpr_slot
;
356 int last_save_gpr_slot
;
358 /* Location (FP register number) where GPRs (r0-r15) should
360 0 - does not need to be saved at all
362 signed char gpr_save_slots
[16];
364 /* Number of first and last gpr to be saved, restored. */
366 int first_restore_gpr
;
368 int last_restore_gpr
;
370 /* Bits standing for floating point registers. Set, if the
371 respective register has to be saved. Starting with reg 16 (f0)
372 at the rightmost bit.
373 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
374 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
375 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
376 unsigned int fpr_bitmap
;
378 /* Number of floating point registers f8-f15 which must be saved. */
381 /* Set if return address needs to be saved.
382 This flag is set by s390_return_addr_rtx if it could not use
383 the initial value of r14 and therefore depends on r14 saved
385 bool save_return_addr_p
;
387 /* Size of stack frame. */
388 HOST_WIDE_INT frame_size
;
391 /* Define the structure for the machine field in struct function. */
393 struct GTY(()) machine_function
395 struct s390_frame_layout frame_layout
;
397 /* Literal pool base register. */
400 /* True if we may need to perform branch splitting. */
401 bool split_branches_pending_p
;
403 bool has_landing_pad_p
;
405 /* True if the current function may contain a tbegin clobbering
410 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
412 #define cfun_frame_layout (cfun->machine->frame_layout)
413 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
414 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
415 ? cfun_frame_layout.fpr_bitmap & 0x0f \
416 : cfun_frame_layout.fpr_bitmap & 0x03))
417 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
418 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
419 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
420 (1 << (REGNO - FPR0_REGNUM)))
421 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
422 (1 << (REGNO - FPR0_REGNUM))))
423 #define cfun_gpr_save_slot(REGNO) \
424 cfun->machine->frame_layout.gpr_save_slots[REGNO]
426 /* Number of GPRs and FPRs used for argument passing. */
427 #define GP_ARG_NUM_REG 5
428 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
430 /* A couple of shortcuts. */
431 #define CONST_OK_FOR_J(x) \
432 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
433 #define CONST_OK_FOR_K(x) \
434 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
435 #define CONST_OK_FOR_Os(x) \
436 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
437 #define CONST_OK_FOR_Op(x) \
438 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
439 #define CONST_OK_FOR_On(x) \
440 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
442 #define REGNO_PAIR_OK(REGNO, MODE) \
443 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
445 /* That's the read ahead of the dynamic branch prediction unit in
446 bytes on a z10 (or higher) CPU. */
447 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
449 static const int s390_hotpatch_trampoline_halfwords_default
= 12;
450 static const int s390_hotpatch_trampoline_halfwords_max
= 1000000;
451 static int s390_hotpatch_trampoline_halfwords
= -1;
453 /* Return the argument of the given hotpatch attribute or the default value if
454 no argument is present. */
457 get_hotpatch_attribute (tree hotpatch_attr
)
461 args
= TREE_VALUE (hotpatch_attr
);
464 TREE_INT_CST_LOW (TREE_VALUE (args
)):
465 s390_hotpatch_trampoline_halfwords_default
;
468 /* Check whether the hotpatch attribute is applied to a function and, if it has
469 an argument, the argument is valid. */
472 s390_handle_hotpatch_attribute (tree
*node
, tree name
, tree args
,
473 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
475 if (TREE_CODE (*node
) != FUNCTION_DECL
)
477 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
479 *no_add_attrs
= true;
483 tree expr
= TREE_VALUE (args
);
485 if (TREE_CODE (expr
) != INTEGER_CST
486 || !INTEGRAL_TYPE_P (TREE_TYPE (expr
))
487 || wi::gtu_p (expr
, s390_hotpatch_trampoline_halfwords_max
))
489 error ("requested %qE attribute is not a non-negative integer"
490 " constant or too large (max. %d)", name
,
491 s390_hotpatch_trampoline_halfwords_max
);
492 *no_add_attrs
= true;
499 static const struct attribute_spec s390_attribute_table
[] = {
500 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute
, NULL
,
504 { NULL
, 0, 0, false, false, false, NULL
, NULL
, false }
507 /* Return the alignment for LABEL. We default to the -falign-labels
508 value except for the literal pool base label. */
510 s390_label_align (rtx label
)
512 rtx_insn
*prev_insn
= prev_active_insn (label
);
515 if (prev_insn
== NULL_RTX
)
518 set
= single_set (prev_insn
);
525 /* Don't align literal pool base labels. */
526 if (GET_CODE (src
) == UNSPEC
527 && XINT (src
, 1) == UNSPEC_MAIN_BASE
)
531 return align_labels_log
;
535 s390_libgcc_cmp_return_mode (void)
537 return TARGET_64BIT
? DImode
: SImode
;
541 s390_libgcc_shift_count_mode (void)
543 return TARGET_64BIT
? DImode
: SImode
;
547 s390_unwind_word_mode (void)
549 return TARGET_64BIT
? DImode
: SImode
;
552 /* Return true if the back end supports mode MODE. */
554 s390_scalar_mode_supported_p (machine_mode mode
)
556 /* In contrast to the default implementation reject TImode constants on 31bit
557 TARGET_ZARCH for ABI compliance. */
558 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
561 if (DECIMAL_FLOAT_MODE_P (mode
))
562 return default_decimal_float_supported_p ();
564 return default_scalar_mode_supported_p (mode
);
567 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
570 s390_set_has_landing_pad_p (bool value
)
572 cfun
->machine
->has_landing_pad_p
= value
;
575 /* If two condition code modes are compatible, return a condition code
576 mode which is compatible with both. Otherwise, return
580 s390_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
588 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
589 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
610 /* Return true if SET either doesn't set the CC register, or else
611 the source and destination have matching CC modes and that
612 CC mode is at least as constrained as REQ_MODE. */
615 s390_match_ccmode_set (rtx set
, machine_mode req_mode
)
617 machine_mode set_mode
;
619 gcc_assert (GET_CODE (set
) == SET
);
621 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
624 set_mode
= GET_MODE (SET_DEST (set
));
638 if (req_mode
!= set_mode
)
643 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
644 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
650 if (req_mode
!= CCAmode
)
658 return (GET_MODE (SET_SRC (set
)) == set_mode
);
661 /* Return true if every SET in INSN that sets the CC register
662 has source and destination with matching CC modes and that
663 CC mode is at least as constrained as REQ_MODE.
664 If REQ_MODE is VOIDmode, always return false. */
667 s390_match_ccmode (rtx_insn
*insn
, machine_mode req_mode
)
671 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
672 if (req_mode
== VOIDmode
)
675 if (GET_CODE (PATTERN (insn
)) == SET
)
676 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
678 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
679 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
681 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
682 if (GET_CODE (set
) == SET
)
683 if (!s390_match_ccmode_set (set
, req_mode
))
690 /* If a test-under-mask instruction can be used to implement
691 (compare (and ... OP1) OP2), return the CC mode required
692 to do that. Otherwise, return VOIDmode.
693 MIXED is true if the instruction can distinguish between
694 CC1 and CC2 for mixed selected bits (TMxx), it is false
695 if the instruction cannot (TM). */
698 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
702 /* ??? Fixme: should work on CONST_DOUBLE as well. */
703 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
706 /* Selected bits all zero: CC0.
707 e.g.: int a; if ((a & (16 + 128)) == 0) */
708 if (INTVAL (op2
) == 0)
711 /* Selected bits all one: CC3.
712 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
713 if (INTVAL (op2
) == INTVAL (op1
))
716 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
718 if ((a & (16 + 128)) == 16) -> CCT1
719 if ((a & (16 + 128)) == 128) -> CCT2 */
722 bit1
= exact_log2 (INTVAL (op2
));
723 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
724 if (bit0
!= -1 && bit1
!= -1)
725 return bit0
> bit1
? CCT1mode
: CCT2mode
;
731 /* Given a comparison code OP (EQ, NE, etc.) and the operands
732 OP0 and OP1 of a COMPARE, return the mode to be used for the
736 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
742 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
743 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
745 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
746 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
748 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
749 || GET_CODE (op1
) == NEG
)
750 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
753 if (GET_CODE (op0
) == AND
)
755 /* Check whether we can potentially do it via TM. */
757 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
758 if (ccmode
!= VOIDmode
)
760 /* Relax CCTmode to CCZmode to allow fall-back to AND
761 if that turns out to be beneficial. */
762 return ccmode
== CCTmode
? CCZmode
: ccmode
;
766 if (register_operand (op0
, HImode
)
767 && GET_CODE (op1
) == CONST_INT
768 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
770 if (register_operand (op0
, QImode
)
771 && GET_CODE (op1
) == CONST_INT
772 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
781 /* The only overflow condition of NEG and ABS happens when
782 -INT_MAX is used as parameter, which stays negative. So
783 we have an overflow from a positive value to a negative.
784 Using CCAP mode the resulting cc can be used for comparisons. */
785 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
786 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
789 /* If constants are involved in an add instruction it is possible to use
790 the resulting cc for comparisons with zero. Knowing the sign of the
791 constant the overflow behavior gets predictable. e.g.:
792 int a, b; if ((b = a + c) > 0)
793 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
794 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
795 && (CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1)))
796 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0
, 1)), 'O', "Os")
797 /* Avoid INT32_MIN on 32 bit. */
798 && (!TARGET_ZARCH
|| INTVAL (XEXP (op0
, 1)) != -0x7fffffff - 1))))
800 if (INTVAL (XEXP((op0
), 1)) < 0)
814 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
815 && GET_CODE (op1
) != CONST_INT
)
821 if (GET_CODE (op0
) == PLUS
822 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
825 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
826 && GET_CODE (op1
) != CONST_INT
)
832 if (GET_CODE (op0
) == MINUS
833 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
836 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
837 && GET_CODE (op1
) != CONST_INT
)
846 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
847 that we can implement more efficiently. */
850 s390_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
851 bool op0_preserve_value
)
853 if (op0_preserve_value
)
856 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
857 if ((*code
== EQ
|| *code
== NE
)
858 && *op1
== const0_rtx
859 && GET_CODE (*op0
) == ZERO_EXTRACT
860 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
861 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
862 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
864 rtx inner
= XEXP (*op0
, 0);
865 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
866 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
867 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
869 if (len
> 0 && len
< modesize
870 && pos
>= 0 && pos
+ len
<= modesize
871 && modesize
<= HOST_BITS_PER_WIDE_INT
)
873 unsigned HOST_WIDE_INT block
;
874 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
875 block
<<= modesize
- pos
- len
;
877 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
878 gen_int_mode (block
, GET_MODE (inner
)));
882 /* Narrow AND of memory against immediate to enable TM. */
883 if ((*code
== EQ
|| *code
== NE
)
884 && *op1
== const0_rtx
885 && GET_CODE (*op0
) == AND
886 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
887 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
889 rtx inner
= XEXP (*op0
, 0);
890 rtx mask
= XEXP (*op0
, 1);
892 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
893 if (GET_CODE (inner
) == SUBREG
894 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
895 && (GET_MODE_SIZE (GET_MODE (inner
))
896 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
898 & GET_MODE_MASK (GET_MODE (inner
))
899 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
901 inner
= SUBREG_REG (inner
);
903 /* Do not change volatile MEMs. */
904 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
906 int part
= s390_single_part (XEXP (*op0
, 1),
907 GET_MODE (inner
), QImode
, 0);
910 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
911 inner
= adjust_address_nv (inner
, QImode
, part
);
912 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
917 /* Narrow comparisons against 0xffff to HImode if possible. */
918 if ((*code
== EQ
|| *code
== NE
)
919 && GET_CODE (*op1
) == CONST_INT
920 && INTVAL (*op1
) == 0xffff
921 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
922 && (nonzero_bits (*op0
, GET_MODE (*op0
))
923 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
925 *op0
= gen_lowpart (HImode
, *op0
);
929 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
930 if (GET_CODE (*op0
) == UNSPEC
931 && XINT (*op0
, 1) == UNSPEC_STRCMPCC_TO_INT
932 && XVECLEN (*op0
, 0) == 1
933 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
934 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
935 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
936 && *op1
== const0_rtx
)
938 enum rtx_code new_code
= UNKNOWN
;
941 case EQ
: new_code
= EQ
; break;
942 case NE
: new_code
= NE
; break;
943 case LT
: new_code
= GTU
; break;
944 case GT
: new_code
= LTU
; break;
945 case LE
: new_code
= GEU
; break;
946 case GE
: new_code
= LEU
; break;
950 if (new_code
!= UNKNOWN
)
952 *op0
= XVECEXP (*op0
, 0, 0);
957 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
958 if (GET_CODE (*op0
) == UNSPEC
959 && XINT (*op0
, 1) == UNSPEC_CC_TO_INT
960 && XVECLEN (*op0
, 0) == 1
961 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
962 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
963 && CONST_INT_P (*op1
))
965 enum rtx_code new_code
= UNKNOWN
;
966 switch (GET_MODE (XVECEXP (*op0
, 0, 0)))
972 case EQ
: new_code
= EQ
; break;
973 case NE
: new_code
= NE
; break;
980 if (new_code
!= UNKNOWN
)
982 /* For CCRAWmode put the required cc mask into the second
984 if (GET_MODE (XVECEXP (*op0
, 0, 0)) == CCRAWmode
985 && INTVAL (*op1
) >= 0 && INTVAL (*op1
) <= 3)
986 *op1
= gen_rtx_CONST_INT (VOIDmode
, 1 << (3 - INTVAL (*op1
)));
987 *op0
= XVECEXP (*op0
, 0, 0);
992 /* Simplify cascaded EQ, NE with const0_rtx. */
993 if ((*code
== NE
|| *code
== EQ
)
994 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
995 && GET_MODE (*op0
) == SImode
996 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
997 && REG_P (XEXP (*op0
, 0))
998 && XEXP (*op0
, 1) == const0_rtx
999 && *op1
== const0_rtx
)
1001 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
1002 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
1006 *op0
= XEXP (*op0
, 0);
1009 /* Prefer register over memory as first operand. */
1010 if (MEM_P (*op0
) && REG_P (*op1
))
1012 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
1013 *code
= (int)swap_condition ((enum rtx_code
)*code
);
1017 /* Emit a compare instruction suitable to implement the comparison
1018 OP0 CODE OP1. Return the correct condition RTL to be placed in
1019 the IF_THEN_ELSE of the conditional branch testing the result. */
1022 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
1024 machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
1027 /* Do not output a redundant compare instruction if a compare_and_swap
1028 pattern already computed the result and the machine modes are compatible. */
1029 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
1031 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
1037 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
1038 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
1041 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
1044 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1046 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1047 conditional branch testing the result. */
1050 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
1051 rtx cmp
, rtx new_rtx
)
1053 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
, new_rtx
));
1054 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
),
1058 /* Emit a jump instruction to TARGET and return it. If COND is
1059 NULL_RTX, emit an unconditional jump, else a conditional jump under
1063 s390_emit_jump (rtx target
, rtx cond
)
1067 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
1069 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
1071 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
1072 return emit_jump_insn (insn
);
1075 /* Return branch condition mask to implement a branch
1076 specified by CODE. Return -1 for invalid comparisons. */
1079 s390_branch_condition_mask (rtx code
)
1081 const int CC0
= 1 << 3;
1082 const int CC1
= 1 << 2;
1083 const int CC2
= 1 << 1;
1084 const int CC3
= 1 << 0;
1086 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
1087 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
1088 gcc_assert (XEXP (code
, 1) == const0_rtx
1089 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1090 && CONST_INT_P (XEXP (code
, 1))));
1093 switch (GET_MODE (XEXP (code
, 0)))
1097 switch (GET_CODE (code
))
1099 case EQ
: return CC0
;
1100 case NE
: return CC1
| CC2
| CC3
;
1106 switch (GET_CODE (code
))
1108 case EQ
: return CC1
;
1109 case NE
: return CC0
| CC2
| CC3
;
1115 switch (GET_CODE (code
))
1117 case EQ
: return CC2
;
1118 case NE
: return CC0
| CC1
| CC3
;
1124 switch (GET_CODE (code
))
1126 case EQ
: return CC3
;
1127 case NE
: return CC0
| CC1
| CC2
;
1133 switch (GET_CODE (code
))
1135 case EQ
: return CC0
| CC2
;
1136 case NE
: return CC1
| CC3
;
1142 switch (GET_CODE (code
))
1144 case LTU
: return CC2
| CC3
; /* carry */
1145 case GEU
: return CC0
| CC1
; /* no carry */
1151 switch (GET_CODE (code
))
1153 case GTU
: return CC0
| CC1
; /* borrow */
1154 case LEU
: return CC2
| CC3
; /* no borrow */
1160 switch (GET_CODE (code
))
1162 case EQ
: return CC0
| CC2
;
1163 case NE
: return CC1
| CC3
;
1164 case LTU
: return CC1
;
1165 case GTU
: return CC3
;
1166 case LEU
: return CC1
| CC2
;
1167 case GEU
: return CC2
| CC3
;
1172 switch (GET_CODE (code
))
1174 case EQ
: return CC0
;
1175 case NE
: return CC1
| CC2
| CC3
;
1176 case LTU
: return CC1
;
1177 case GTU
: return CC2
;
1178 case LEU
: return CC0
| CC1
;
1179 case GEU
: return CC0
| CC2
;
1185 switch (GET_CODE (code
))
1187 case EQ
: return CC0
;
1188 case NE
: return CC2
| CC1
| CC3
;
1189 case LTU
: return CC2
;
1190 case GTU
: return CC1
;
1191 case LEU
: return CC0
| CC2
;
1192 case GEU
: return CC0
| CC1
;
1198 switch (GET_CODE (code
))
1200 case EQ
: return CC0
;
1201 case NE
: return CC1
| CC2
| CC3
;
1202 case LT
: return CC1
| CC3
;
1203 case GT
: return CC2
;
1204 case LE
: return CC0
| CC1
| CC3
;
1205 case GE
: return CC0
| CC2
;
1211 switch (GET_CODE (code
))
1213 case EQ
: return CC0
;
1214 case NE
: return CC1
| CC2
| CC3
;
1215 case LT
: return CC1
;
1216 case GT
: return CC2
| CC3
;
1217 case LE
: return CC0
| CC1
;
1218 case GE
: return CC0
| CC2
| CC3
;
1224 switch (GET_CODE (code
))
1226 case EQ
: return CC0
;
1227 case NE
: return CC1
| CC2
| CC3
;
1228 case LT
: return CC1
;
1229 case GT
: return CC2
;
1230 case LE
: return CC0
| CC1
;
1231 case GE
: return CC0
| CC2
;
1232 case UNORDERED
: return CC3
;
1233 case ORDERED
: return CC0
| CC1
| CC2
;
1234 case UNEQ
: return CC0
| CC3
;
1235 case UNLT
: return CC1
| CC3
;
1236 case UNGT
: return CC2
| CC3
;
1237 case UNLE
: return CC0
| CC1
| CC3
;
1238 case UNGE
: return CC0
| CC2
| CC3
;
1239 case LTGT
: return CC1
| CC2
;
1245 switch (GET_CODE (code
))
1247 case EQ
: return CC0
;
1248 case NE
: return CC2
| CC1
| CC3
;
1249 case LT
: return CC2
;
1250 case GT
: return CC1
;
1251 case LE
: return CC0
| CC2
;
1252 case GE
: return CC0
| CC1
;
1253 case UNORDERED
: return CC3
;
1254 case ORDERED
: return CC0
| CC2
| CC1
;
1255 case UNEQ
: return CC0
| CC3
;
1256 case UNLT
: return CC2
| CC3
;
1257 case UNGT
: return CC1
| CC3
;
1258 case UNLE
: return CC0
| CC2
| CC3
;
1259 case UNGE
: return CC0
| CC1
| CC3
;
1260 case LTGT
: return CC2
| CC1
;
1266 switch (GET_CODE (code
))
1269 return INTVAL (XEXP (code
, 1));
1271 return (INTVAL (XEXP (code
, 1))) ^ 0xf;
1282 /* Return branch condition mask to implement a compare and branch
1283 specified by CODE. Return -1 for invalid comparisons. */
1286 s390_compare_and_branch_condition_mask (rtx code
)
1288 const int CC0
= 1 << 3;
1289 const int CC1
= 1 << 2;
1290 const int CC2
= 1 << 1;
1292 switch (GET_CODE (code
))
1316 /* If INV is false, return assembler mnemonic string to implement
1317 a branch specified by CODE. If INV is true, return mnemonic
1318 for the corresponding inverted branch. */
1321 s390_branch_condition_mnemonic (rtx code
, int inv
)
1325 static const char *const mnemonic
[16] =
1327 NULL
, "o", "h", "nle",
1328 "l", "nhe", "lh", "ne",
1329 "e", "nlh", "he", "nl",
1330 "le", "nh", "no", NULL
1333 if (GET_CODE (XEXP (code
, 0)) == REG
1334 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1335 && (XEXP (code
, 1) == const0_rtx
1336 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1337 && CONST_INT_P (XEXP (code
, 1)))))
1338 mask
= s390_branch_condition_mask (code
);
1340 mask
= s390_compare_and_branch_condition_mask (code
);
1342 gcc_assert (mask
>= 0);
1347 gcc_assert (mask
>= 1 && mask
<= 14);
1349 return mnemonic
[mask
];
1352 /* Return the part of op which has a value different from def.
1353 The size of the part is determined by mode.
1354 Use this function only if you already know that op really
1355 contains such a part. */
1357 unsigned HOST_WIDE_INT
1358 s390_extract_part (rtx op
, machine_mode mode
, int def
)
1360 unsigned HOST_WIDE_INT value
= 0;
1361 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1362 int part_bits
= GET_MODE_BITSIZE (mode
);
1363 unsigned HOST_WIDE_INT part_mask
1364 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1367 for (i
= 0; i
< max_parts
; i
++)
1370 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1372 value
>>= part_bits
;
1374 if ((value
& part_mask
) != (def
& part_mask
))
1375 return value
& part_mask
;
1381 /* If OP is an integer constant of mode MODE with exactly one
1382 part of mode PART_MODE unequal to DEF, return the number of that
1383 part. Otherwise, return -1. */
1386 s390_single_part (rtx op
,
1388 machine_mode part_mode
,
1391 unsigned HOST_WIDE_INT value
= 0;
1392 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1393 unsigned HOST_WIDE_INT part_mask
1394 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1397 if (GET_CODE (op
) != CONST_INT
)
1400 for (i
= 0; i
< n_parts
; i
++)
1403 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1405 value
>>= GET_MODE_BITSIZE (part_mode
);
1407 if ((value
& part_mask
) != (def
& part_mask
))
1415 return part
== -1 ? -1 : n_parts
- 1 - part
;
1418 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1419 bits and no other bits are set in IN. POS and LENGTH can be used
1420 to obtain the start position and the length of the bitfield.
1422 POS gives the position of the first bit of the bitfield counting
1423 from the lowest order bit starting with zero. In order to use this
1424 value for S/390 instructions this has to be converted to "bits big
1428 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1429 int *pos
, int *length
)
1434 unsigned HOST_WIDE_INT mask
= 1ULL;
1435 bool contiguous
= false;
1437 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1461 /* Calculate a mask for all bits beyond the contiguous bits. */
1462 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1467 if (tmp_length
+ tmp_pos
- 1 > size
)
1471 *length
= tmp_length
;
1479 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
1480 equivalent to a shift followed by the AND. In particular, CONTIG
1481 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1482 for ROTL indicate a rotate to the right. */
1485 s390_extzv_shift_ok (int bitsize
, int rotl
, unsigned HOST_WIDE_INT contig
)
1490 ok
= s390_contiguous_bitmask_p (contig
, bitsize
, &pos
, &len
);
1493 return ((rotl
>= 0 && rotl
<= pos
)
1494 || (rotl
< 0 && -rotl
<= bitsize
- len
- pos
));
1497 /* Check whether we can (and want to) split a double-word
1498 move in mode MODE from SRC to DST into two single-word
1499 moves, moving the subword FIRST_SUBWORD first. */
1502 s390_split_ok_p (rtx dst
, rtx src
, machine_mode mode
, int first_subword
)
1504 /* Floating point registers cannot be split. */
1505 if (FP_REG_P (src
) || FP_REG_P (dst
))
1508 /* We don't need to split if operands are directly accessible. */
1509 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1512 /* Non-offsettable memory references cannot be split. */
1513 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1514 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1517 /* Moving the first subword must not clobber a register
1518 needed to move the second subword. */
1519 if (register_operand (dst
, mode
))
1521 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1522 if (reg_overlap_mentioned_p (subreg
, src
))
1529 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1530 and [MEM2, MEM2 + SIZE] do overlap and false
1534 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1536 rtx addr1
, addr2
, addr_delta
;
1537 HOST_WIDE_INT delta
;
1539 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1545 addr1
= XEXP (mem1
, 0);
1546 addr2
= XEXP (mem2
, 0);
1548 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1550 /* This overlapping check is used by peepholes merging memory block operations.
1551 Overlapping operations would otherwise be recognized by the S/390 hardware
1552 and would fall back to a slower implementation. Allowing overlapping
1553 operations would lead to slow code but not to wrong code. Therefore we are
1554 somewhat optimistic if we cannot prove that the memory blocks are
1556 That's why we return false here although this may accept operations on
1557 overlapping memory areas. */
1558 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1561 delta
= INTVAL (addr_delta
);
1564 || (delta
> 0 && delta
< size
)
1565 || (delta
< 0 && -delta
< size
))
1571 /* Check whether the address of memory reference MEM2 equals exactly
1572 the address of memory reference MEM1 plus DELTA. Return true if
1573 we can prove this to be the case, false otherwise. */
1576 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1578 rtx addr1
, addr2
, addr_delta
;
1580 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1583 addr1
= XEXP (mem1
, 0);
1584 addr2
= XEXP (mem2
, 0);
1586 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1587 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1593 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1596 s390_expand_logical_operator (enum rtx_code code
, machine_mode mode
,
1599 machine_mode wmode
= mode
;
1600 rtx dst
= operands
[0];
1601 rtx src1
= operands
[1];
1602 rtx src2
= operands
[2];
1605 /* If we cannot handle the operation directly, use a temp register. */
1606 if (!s390_logical_operator_ok_p (operands
))
1607 dst
= gen_reg_rtx (mode
);
1609 /* QImode and HImode patterns make sense only if we have a destination
1610 in memory. Otherwise perform the operation in SImode. */
1611 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1614 /* Widen operands if required. */
1617 if (GET_CODE (dst
) == SUBREG
1618 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1620 else if (REG_P (dst
))
1621 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1623 dst
= gen_reg_rtx (wmode
);
1625 if (GET_CODE (src1
) == SUBREG
1626 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1628 else if (GET_MODE (src1
) != VOIDmode
)
1629 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1631 if (GET_CODE (src2
) == SUBREG
1632 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1634 else if (GET_MODE (src2
) != VOIDmode
)
1635 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1638 /* Emit the instruction. */
1639 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1640 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1641 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1643 /* Fix up the destination if needed. */
1644 if (dst
!= operands
[0])
1645 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1648 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1651 s390_logical_operator_ok_p (rtx
*operands
)
1653 /* If the destination operand is in memory, it needs to coincide
1654 with one of the source operands. After reload, it has to be
1655 the first source operand. */
1656 if (GET_CODE (operands
[0]) == MEM
)
1657 return rtx_equal_p (operands
[0], operands
[1])
1658 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1663 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1664 operand IMMOP to switch from SS to SI type instructions. */
1667 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1669 int def
= code
== AND
? -1 : 0;
1673 gcc_assert (GET_CODE (*memop
) == MEM
);
1674 gcc_assert (!MEM_VOLATILE_P (*memop
));
1676 mask
= s390_extract_part (*immop
, QImode
, def
);
1677 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1678 gcc_assert (part
>= 0);
1680 *memop
= adjust_address (*memop
, QImode
, part
);
1681 *immop
= gen_int_mode (mask
, QImode
);
1685 /* How to allocate a 'struct machine_function'. */
1687 static struct machine_function
*
1688 s390_init_machine_status (void)
1690 return ggc_cleared_alloc
<machine_function
> ();
1693 /* Map for smallest class containing reg regno. */
1695 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1696 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1697 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1698 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1699 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1700 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1701 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1702 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1703 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1704 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1705 ACCESS_REGS
, ACCESS_REGS
1708 /* Return attribute type of insn. */
1710 static enum attr_type
1711 s390_safe_attr_type (rtx_insn
*insn
)
1713 if (recog_memoized (insn
) >= 0)
1714 return get_attr_type (insn
);
1719 /* Return true if DISP is a valid short displacement. */
1722 s390_short_displacement (rtx disp
)
1724 /* No displacement is OK. */
1728 /* Without the long displacement facility we don't need to
1729 distingiush between long and short displacement. */
1730 if (!TARGET_LONG_DISPLACEMENT
)
1733 /* Integer displacement in range. */
1734 if (GET_CODE (disp
) == CONST_INT
)
1735 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1737 /* GOT offset is not OK, the GOT can be large. */
1738 if (GET_CODE (disp
) == CONST
1739 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1740 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1741 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1744 /* All other symbolic constants are literal pool references,
1745 which are OK as the literal pool must be small. */
1746 if (GET_CODE (disp
) == CONST
)
1752 /* Decompose a RTL expression ADDR for a memory address into
1753 its components, returned in OUT.
1755 Returns false if ADDR is not a valid memory address, true
1756 otherwise. If OUT is NULL, don't return the components,
1757 but check for validity only.
1759 Note: Only addresses in canonical form are recognized.
1760 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1761 canonical form so that they will be recognized. */
1764 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1766 HOST_WIDE_INT offset
= 0;
1767 rtx base
= NULL_RTX
;
1768 rtx indx
= NULL_RTX
;
1769 rtx disp
= NULL_RTX
;
1771 bool pointer
= false;
1772 bool base_ptr
= false;
1773 bool indx_ptr
= false;
1774 bool literal_pool
= false;
1776 /* We may need to substitute the literal pool base register into the address
1777 below. However, at this point we do not know which register is going to
1778 be used as base, so we substitute the arg pointer register. This is going
1779 to be treated as holding a pointer below -- it shouldn't be used for any
1781 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1783 /* Decompose address into base + index + displacement. */
1785 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1788 else if (GET_CODE (addr
) == PLUS
)
1790 rtx op0
= XEXP (addr
, 0);
1791 rtx op1
= XEXP (addr
, 1);
1792 enum rtx_code code0
= GET_CODE (op0
);
1793 enum rtx_code code1
= GET_CODE (op1
);
1795 if (code0
== REG
|| code0
== UNSPEC
)
1797 if (code1
== REG
|| code1
== UNSPEC
)
1799 indx
= op0
; /* index + base */
1805 base
= op0
; /* base + displacement */
1810 else if (code0
== PLUS
)
1812 indx
= XEXP (op0
, 0); /* index + base + disp */
1813 base
= XEXP (op0
, 1);
1824 disp
= addr
; /* displacement */
1826 /* Extract integer part of displacement. */
1830 if (GET_CODE (disp
) == CONST_INT
)
1832 offset
= INTVAL (disp
);
1835 else if (GET_CODE (disp
) == CONST
1836 && GET_CODE (XEXP (disp
, 0)) == PLUS
1837 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1839 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1840 disp
= XEXP (XEXP (disp
, 0), 0);
1844 /* Strip off CONST here to avoid special case tests later. */
1845 if (disp
&& GET_CODE (disp
) == CONST
)
1846 disp
= XEXP (disp
, 0);
1848 /* We can convert literal pool addresses to
1849 displacements by basing them off the base register. */
1850 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1852 /* Either base or index must be free to hold the base register. */
1854 base
= fake_pool_base
, literal_pool
= true;
1856 indx
= fake_pool_base
, literal_pool
= true;
1860 /* Mark up the displacement. */
1861 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1862 UNSPEC_LTREL_OFFSET
);
1865 /* Validate base register. */
1868 if (GET_CODE (base
) == UNSPEC
)
1869 switch (XINT (base
, 1))
1873 disp
= gen_rtx_UNSPEC (Pmode
,
1874 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1875 UNSPEC_LTREL_OFFSET
);
1879 base
= XVECEXP (base
, 0, 1);
1882 case UNSPEC_LTREL_BASE
:
1883 if (XVECLEN (base
, 0) == 1)
1884 base
= fake_pool_base
, literal_pool
= true;
1886 base
= XVECEXP (base
, 0, 1);
1894 || (GET_MODE (base
) != SImode
1895 && GET_MODE (base
) != Pmode
))
1898 if (REGNO (base
) == STACK_POINTER_REGNUM
1899 || REGNO (base
) == FRAME_POINTER_REGNUM
1900 || ((reload_completed
|| reload_in_progress
)
1901 && frame_pointer_needed
1902 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1903 || REGNO (base
) == ARG_POINTER_REGNUM
1905 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1906 pointer
= base_ptr
= true;
1908 if ((reload_completed
|| reload_in_progress
)
1909 && base
== cfun
->machine
->base_reg
)
1910 pointer
= base_ptr
= literal_pool
= true;
1913 /* Validate index register. */
1916 if (GET_CODE (indx
) == UNSPEC
)
1917 switch (XINT (indx
, 1))
1921 disp
= gen_rtx_UNSPEC (Pmode
,
1922 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1923 UNSPEC_LTREL_OFFSET
);
1927 indx
= XVECEXP (indx
, 0, 1);
1930 case UNSPEC_LTREL_BASE
:
1931 if (XVECLEN (indx
, 0) == 1)
1932 indx
= fake_pool_base
, literal_pool
= true;
1934 indx
= XVECEXP (indx
, 0, 1);
1942 || (GET_MODE (indx
) != SImode
1943 && GET_MODE (indx
) != Pmode
))
1946 if (REGNO (indx
) == STACK_POINTER_REGNUM
1947 || REGNO (indx
) == FRAME_POINTER_REGNUM
1948 || ((reload_completed
|| reload_in_progress
)
1949 && frame_pointer_needed
1950 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1951 || REGNO (indx
) == ARG_POINTER_REGNUM
1953 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1954 pointer
= indx_ptr
= true;
1956 if ((reload_completed
|| reload_in_progress
)
1957 && indx
== cfun
->machine
->base_reg
)
1958 pointer
= indx_ptr
= literal_pool
= true;
1961 /* Prefer to use pointer as base, not index. */
1962 if (base
&& indx
&& !base_ptr
1963 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1970 /* Validate displacement. */
1973 /* If virtual registers are involved, the displacement will change later
1974 anyway as the virtual registers get eliminated. This could make a
1975 valid displacement invalid, but it is more likely to make an invalid
1976 displacement valid, because we sometimes access the register save area
1977 via negative offsets to one of those registers.
1978 Thus we don't check the displacement for validity here. If after
1979 elimination the displacement turns out to be invalid after all,
1980 this is fixed up by reload in any case. */
1981 /* LRA maintains always displacements up to date and we need to
1982 know the displacement is right during all LRA not only at the
1983 final elimination. */
1985 || (base
!= arg_pointer_rtx
1986 && indx
!= arg_pointer_rtx
1987 && base
!= return_address_pointer_rtx
1988 && indx
!= return_address_pointer_rtx
1989 && base
!= frame_pointer_rtx
1990 && indx
!= frame_pointer_rtx
1991 && base
!= virtual_stack_vars_rtx
1992 && indx
!= virtual_stack_vars_rtx
))
1993 if (!DISP_IN_RANGE (offset
))
1998 /* All the special cases are pointers. */
2001 /* In the small-PIC case, the linker converts @GOT
2002 and @GOTNTPOFF offsets to possible displacements. */
2003 if (GET_CODE (disp
) == UNSPEC
2004 && (XINT (disp
, 1) == UNSPEC_GOT
2005 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2011 /* Accept pool label offsets. */
2012 else if (GET_CODE (disp
) == UNSPEC
2013 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2016 /* Accept literal pool references. */
2017 else if (GET_CODE (disp
) == UNSPEC
2018 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2020 /* In case CSE pulled a non literal pool reference out of
2021 the pool we have to reject the address. This is
2022 especially important when loading the GOT pointer on non
2023 zarch CPUs. In this case the literal pool contains an lt
2024 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2025 will most likely exceed the displacement. */
2026 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2027 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2030 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2033 /* If we have an offset, make sure it does not
2034 exceed the size of the constant pool entry. */
2035 rtx sym
= XVECEXP (disp
, 0, 0);
2036 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2039 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
2054 out
->disp
= orig_disp
;
2055 out
->pointer
= pointer
;
2056 out
->literal_pool
= literal_pool
;
2062 /* Decompose a RTL expression OP for a shift count into its components,
2063 and return the base register in BASE and the offset in OFFSET.
2065 Return true if OP is a valid shift count, false if not. */
2068 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2070 HOST_WIDE_INT off
= 0;
2072 /* We can have an integer constant, an address register,
2073 or a sum of the two. */
2074 if (GET_CODE (op
) == CONST_INT
)
2079 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2081 off
= INTVAL (XEXP (op
, 1));
2084 while (op
&& GET_CODE (op
) == SUBREG
)
2085 op
= SUBREG_REG (op
);
2087 if (op
&& GET_CODE (op
) != REG
)
2099 /* Return true if CODE is a valid address without index. */
2102 s390_legitimate_address_without_index_p (rtx op
)
2104 struct s390_address addr
;
2106 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2115 /* Return TRUE if ADDR is an operand valid for a load/store relative
2116 instruction. Be aware that the alignment of the operand needs to
2117 be checked separately.
2118 Valid addresses are single references or a sum of a reference and a
2119 constant integer. Return these parts in SYMREF and ADDEND. You can
2120 pass NULL in REF and/or ADDEND if you are not interested in these
2121 values. Literal pool references are *not* considered symbol
2125 s390_loadrelative_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2127 HOST_WIDE_INT tmpaddend
= 0;
2129 if (GET_CODE (addr
) == CONST
)
2130 addr
= XEXP (addr
, 0);
2132 if (GET_CODE (addr
) == PLUS
)
2134 if (!CONST_INT_P (XEXP (addr
, 1)))
2137 tmpaddend
= INTVAL (XEXP (addr
, 1));
2138 addr
= XEXP (addr
, 0);
2141 if ((GET_CODE (addr
) == SYMBOL_REF
&& !CONSTANT_POOL_ADDRESS_P (addr
))
2142 || (GET_CODE (addr
) == UNSPEC
2143 && (XINT (addr
, 1) == UNSPEC_GOTENT
2144 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
2149 *addend
= tmpaddend
;
2156 /* Return true if the address in OP is valid for constraint letter C
2157 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2158 pool MEMs should be accepted. Only the Q, R, S, T constraint
2159 letters are allowed for C. */
2162 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2164 struct s390_address addr
;
2165 bool decomposed
= false;
2167 /* This check makes sure that no symbolic address (except literal
2168 pool references) are accepted by the R or T constraints. */
2169 if (s390_loadrelative_operand_p (op
, NULL
, NULL
))
2172 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2175 if (!s390_decompose_address (op
, &addr
))
2177 if (addr
.literal_pool
)
2184 case 'Q': /* no index short displacement */
2185 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2189 if (!s390_short_displacement (addr
.disp
))
2193 case 'R': /* with index short displacement */
2194 if (TARGET_LONG_DISPLACEMENT
)
2196 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2198 if (!s390_short_displacement (addr
.disp
))
2201 /* Any invalid address here will be fixed up by reload,
2202 so accept it for the most generic constraint. */
2205 case 'S': /* no index long displacement */
2206 if (!TARGET_LONG_DISPLACEMENT
)
2208 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2212 if (s390_short_displacement (addr
.disp
))
2216 case 'T': /* with index long displacement */
2217 if (!TARGET_LONG_DISPLACEMENT
)
2219 /* Any invalid address here will be fixed up by reload,
2220 so accept it for the most generic constraint. */
2221 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2222 && s390_short_displacement (addr
.disp
))
2232 /* Evaluates constraint strings described by the regular expression
2233 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2234 the constraint given in STR, or 0 else. */
2237 s390_mem_constraint (const char *str
, rtx op
)
2244 /* Check for offsettable variants of memory constraints. */
2245 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2247 if ((reload_completed
|| reload_in_progress
)
2248 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2250 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2252 /* Check for non-literal-pool variants of memory constraints. */
2255 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2260 if (GET_CODE (op
) != MEM
)
2262 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2264 return (s390_check_qrst_address ('Q', op
, true)
2265 || s390_check_qrst_address ('R', op
, true));
2267 return (s390_check_qrst_address ('S', op
, true)
2268 || s390_check_qrst_address ('T', op
, true));
2270 /* Simply check for the basic form of a shift count. Reload will
2271 take care of making sure we have a proper base register. */
2272 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2276 return s390_check_qrst_address (str
[1], op
, true);
2284 /* Evaluates constraint strings starting with letter O. Input
2285 parameter C is the second letter following the "O" in the constraint
2286 string. Returns 1 if VALUE meets the respective constraint and 0
2290 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2298 return trunc_int_for_mode (value
, SImode
) == value
;
2302 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2305 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2313 /* Evaluates constraint strings starting with letter N. Parameter STR
2314 contains the letters following letter "N" in the constraint string.
2315 Returns true if VALUE matches the constraint. */
2318 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2320 machine_mode mode
, part_mode
;
2322 int part
, part_goal
;
2328 part_goal
= str
[0] - '0';
2372 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2375 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2378 if (part_goal
!= -1 && part_goal
!= part
)
2385 /* Returns true if the input parameter VALUE is a float zero. */
2388 s390_float_const_zero_p (rtx value
)
2390 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2391 && value
== CONST0_RTX (GET_MODE (value
)));
2394 /* Implement TARGET_REGISTER_MOVE_COST. */
2397 s390_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2398 reg_class_t from
, reg_class_t to
)
2400 /* On s390, copy between fprs and gprs is expensive as long as no
2401 ldgr/lgdr can be used. */
2402 if ((!TARGET_Z10
|| GET_MODE_SIZE (mode
) != 8)
2403 && ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2404 && reg_classes_intersect_p (to
, FP_REGS
))
2405 || (reg_classes_intersect_p (from
, FP_REGS
)
2406 && reg_classes_intersect_p (to
, GENERAL_REGS
))))
2412 /* Implement TARGET_MEMORY_MOVE_COST. */
2415 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2416 reg_class_t rclass ATTRIBUTE_UNUSED
,
2417 bool in ATTRIBUTE_UNUSED
)
2422 /* Compute a (partial) cost for rtx X. Return true if the complete
2423 cost has been computed, and false if subexpressions should be
2424 scanned. In either case, *TOTAL contains the cost result.
2425 CODE contains GET_CODE (x), OUTER_CODE contains the code
2426 of the superexpression of x. */
2429 s390_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2430 int *total
, bool speed ATTRIBUTE_UNUSED
)
2453 *total
= COSTS_N_INSNS (1);
2458 *total
= COSTS_N_INSNS (1);
2462 switch (GET_MODE (x
))
2466 rtx left
= XEXP (x
, 0);
2467 rtx right
= XEXP (x
, 1);
2468 if (GET_CODE (right
) == CONST_INT
2469 && CONST_OK_FOR_K (INTVAL (right
)))
2470 *total
= s390_cost
->mhi
;
2471 else if (GET_CODE (left
) == SIGN_EXTEND
)
2472 *total
= s390_cost
->mh
;
2474 *total
= s390_cost
->ms
; /* msr, ms, msy */
2479 rtx left
= XEXP (x
, 0);
2480 rtx right
= XEXP (x
, 1);
2483 if (GET_CODE (right
) == CONST_INT
2484 && CONST_OK_FOR_K (INTVAL (right
)))
2485 *total
= s390_cost
->mghi
;
2486 else if (GET_CODE (left
) == SIGN_EXTEND
)
2487 *total
= s390_cost
->msgf
;
2489 *total
= s390_cost
->msg
; /* msgr, msg */
2491 else /* TARGET_31BIT */
2493 if (GET_CODE (left
) == SIGN_EXTEND
2494 && GET_CODE (right
) == SIGN_EXTEND
)
2495 /* mulsidi case: mr, m */
2496 *total
= s390_cost
->m
;
2497 else if (GET_CODE (left
) == ZERO_EXTEND
2498 && GET_CODE (right
) == ZERO_EXTEND
2499 && TARGET_CPU_ZARCH
)
2500 /* umulsidi case: ml, mlr */
2501 *total
= s390_cost
->ml
;
2503 /* Complex calculation is required. */
2504 *total
= COSTS_N_INSNS (40);
2510 *total
= s390_cost
->mult_df
;
2513 *total
= s390_cost
->mxbr
;
2521 switch (GET_MODE (x
))
2524 *total
= s390_cost
->madbr
;
2527 *total
= s390_cost
->maebr
;
2532 /* Negate in the third argument is free: FMSUB. */
2533 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2535 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, 0, speed
)
2536 + rtx_cost (XEXP (x
, 1), FMA
, 1, speed
)
2537 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, 2, speed
));
2544 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2545 *total
= s390_cost
->dlgr
;
2546 else if (GET_MODE (x
) == DImode
)
2548 rtx right
= XEXP (x
, 1);
2549 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2550 *total
= s390_cost
->dlr
;
2551 else /* 64 by 64 bit division */
2552 *total
= s390_cost
->dlgr
;
2554 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2555 *total
= s390_cost
->dlr
;
2560 if (GET_MODE (x
) == DImode
)
2562 rtx right
= XEXP (x
, 1);
2563 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2565 *total
= s390_cost
->dsgfr
;
2567 *total
= s390_cost
->dr
;
2568 else /* 64 by 64 bit division */
2569 *total
= s390_cost
->dsgr
;
2571 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2572 *total
= s390_cost
->dlr
;
2573 else if (GET_MODE (x
) == SFmode
)
2575 *total
= s390_cost
->debr
;
2577 else if (GET_MODE (x
) == DFmode
)
2579 *total
= s390_cost
->ddbr
;
2581 else if (GET_MODE (x
) == TFmode
)
2583 *total
= s390_cost
->dxbr
;
2588 if (GET_MODE (x
) == SFmode
)
2589 *total
= s390_cost
->sqebr
;
2590 else if (GET_MODE (x
) == DFmode
)
2591 *total
= s390_cost
->sqdbr
;
2593 *total
= s390_cost
->sqxbr
;
2598 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2599 || outer_code
== PLUS
|| outer_code
== MINUS
2600 || outer_code
== COMPARE
)
2605 *total
= COSTS_N_INSNS (1);
2606 if (GET_CODE (XEXP (x
, 0)) == AND
2607 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2608 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2610 rtx op0
= XEXP (XEXP (x
, 0), 0);
2611 rtx op1
= XEXP (XEXP (x
, 0), 1);
2612 rtx op2
= XEXP (x
, 1);
2614 if (memory_operand (op0
, GET_MODE (op0
))
2615 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2617 if (register_operand (op0
, GET_MODE (op0
))
2618 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2628 /* Return the cost of an address rtx ADDR. */
2631 s390_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
2632 addr_space_t as ATTRIBUTE_UNUSED
,
2633 bool speed ATTRIBUTE_UNUSED
)
2635 struct s390_address ad
;
2636 if (!s390_decompose_address (addr
, &ad
))
2639 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2642 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2643 otherwise return 0. */
2646 tls_symbolic_operand (rtx op
)
2648 if (GET_CODE (op
) != SYMBOL_REF
)
2650 return SYMBOL_REF_TLS_MODEL (op
);
2653 /* Split DImode access register reference REG (on 64-bit) into its constituent
2654 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2655 gen_highpart cannot be used as they assume all registers are word-sized,
2656 while our access registers have only half that size. */
2659 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2661 gcc_assert (TARGET_64BIT
);
2662 gcc_assert (ACCESS_REG_P (reg
));
2663 gcc_assert (GET_MODE (reg
) == DImode
);
2664 gcc_assert (!(REGNO (reg
) & 1));
2666 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2667 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2670 /* Return true if OP contains a symbol reference */
2673 symbolic_reference_mentioned_p (rtx op
)
2678 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2681 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2682 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2688 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2689 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2693 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2700 /* Return true if OP contains a reference to a thread-local symbol. */
2703 tls_symbolic_reference_mentioned_p (rtx op
)
2708 if (GET_CODE (op
) == SYMBOL_REF
)
2709 return tls_symbolic_operand (op
);
2711 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2712 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2718 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2719 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2723 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2731 /* Return true if OP is a legitimate general operand when
2732 generating PIC code. It is given that flag_pic is on
2733 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2736 legitimate_pic_operand_p (rtx op
)
2738 /* Accept all non-symbolic constants. */
2739 if (!SYMBOLIC_CONST (op
))
2742 /* Reject everything else; must be handled
2743 via emit_symbolic_move. */
2747 /* Returns true if the constant value OP is a legitimate general operand.
2748 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2751 s390_legitimate_constant_p (machine_mode mode
, rtx op
)
2753 /* Accept all non-symbolic constants. */
2754 if (!SYMBOLIC_CONST (op
))
2757 /* Accept immediate LARL operands. */
2758 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
2761 /* Thread-local symbols are never legal constants. This is
2762 so that emit_call knows that computing such addresses
2763 might require a function call. */
2764 if (TLS_SYMBOLIC_CONST (op
))
2767 /* In the PIC case, symbolic constants must *not* be
2768 forced into the literal pool. We accept them here,
2769 so that they will be handled by emit_symbolic_move. */
2773 /* All remaining non-PIC symbolic constants are
2774 forced into the literal pool. */
2778 /* Determine if it's legal to put X into the constant pool. This
2779 is not possible if X contains the address of a symbol that is
2780 not constant (TLS) or not known at final link time (PIC). */
2783 s390_cannot_force_const_mem (machine_mode mode
, rtx x
)
2785 switch (GET_CODE (x
))
2789 /* Accept all non-symbolic constants. */
2793 /* Labels are OK iff we are non-PIC. */
2794 return flag_pic
!= 0;
2797 /* 'Naked' TLS symbol references are never OK,
2798 non-TLS symbols are OK iff we are non-PIC. */
2799 if (tls_symbolic_operand (x
))
2802 return flag_pic
!= 0;
2805 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
2808 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
2809 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
2812 switch (XINT (x
, 1))
2814 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2815 case UNSPEC_LTREL_OFFSET
:
2823 case UNSPEC_GOTNTPOFF
:
2824 case UNSPEC_INDNTPOFF
:
2827 /* If the literal pool shares the code section, be put
2828 execute template placeholders into the pool as well. */
2830 return TARGET_CPU_ZARCH
;
2842 /* Returns true if the constant value OP is a legitimate general
2843 operand during and after reload. The difference to
2844 legitimate_constant_p is that this function will not accept
2845 a constant that would need to be forced to the literal pool
2846 before it can be used as operand.
2847 This function accepts all constants which can be loaded directly
2851 legitimate_reload_constant_p (rtx op
)
2853 /* Accept la(y) operands. */
2854 if (GET_CODE (op
) == CONST_INT
2855 && DISP_IN_RANGE (INTVAL (op
)))
2858 /* Accept l(g)hi/l(g)fi operands. */
2859 if (GET_CODE (op
) == CONST_INT
2860 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2863 /* Accept lliXX operands. */
2865 && GET_CODE (op
) == CONST_INT
2866 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2867 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2871 && GET_CODE (op
) == CONST_INT
2872 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2873 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2876 /* Accept larl operands. */
2877 if (TARGET_CPU_ZARCH
2878 && larl_operand (op
, VOIDmode
))
2881 /* Accept floating-point zero operands that fit into a single GPR. */
2882 if (GET_CODE (op
) == CONST_DOUBLE
2883 && s390_float_const_zero_p (op
)
2884 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2887 /* Accept double-word operands that can be split. */
2888 if (GET_CODE (op
) == CONST_INT
2889 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2891 machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2892 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2893 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2894 return legitimate_reload_constant_p (hi
)
2895 && legitimate_reload_constant_p (lo
);
2898 /* Everything else cannot be handled without reload. */
2902 /* Returns true if the constant value OP is a legitimate fp operand
2903 during and after reload.
2904 This function accepts all constants which can be loaded directly
2908 legitimate_reload_fp_constant_p (rtx op
)
2910 /* Accept floating-point zero operands if the load zero instruction
2911 can be used. Prior to z196 the load fp zero instruction caused a
2912 performance penalty if the result is used as BFP number. */
2914 && GET_CODE (op
) == CONST_DOUBLE
2915 && s390_float_const_zero_p (op
))
2921 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2922 return the class of reg to actually use. */
2925 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
2927 switch (GET_CODE (op
))
2929 /* Constants we cannot reload into general registers
2930 must be forced into the literal pool. */
2933 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2934 && legitimate_reload_constant_p (op
))
2935 return GENERAL_REGS
;
2936 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2937 && legitimate_reload_constant_p (op
))
2939 else if (reg_class_subset_p (FP_REGS
, rclass
)
2940 && legitimate_reload_fp_constant_p (op
))
2944 /* If a symbolic constant or a PLUS is reloaded,
2945 it is most likely being used as an address, so
2946 prefer ADDR_REGS. If 'class' is not a superset
2947 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2949 /* Symrefs cannot be pushed into the literal pool with -fPIC
2950 so we *MUST NOT* return NO_REGS for these cases
2951 (s390_cannot_force_const_mem will return true).
2953 On the other hand we MUST return NO_REGS for symrefs with
2954 invalid addend which might have been pushed to the literal
2955 pool (no -fPIC). Usually we would expect them to be
2956 handled via secondary reload but this does not happen if
2957 they are used as literal pool slot replacement in reload
2958 inheritance (see emit_input_reload_insns). */
2959 if (TARGET_CPU_ZARCH
2960 && GET_CODE (XEXP (op
, 0)) == PLUS
2961 && GET_CODE (XEXP (XEXP(op
, 0), 0)) == SYMBOL_REF
2962 && GET_CODE (XEXP (XEXP(op
, 0), 1)) == CONST_INT
)
2964 if (flag_pic
&& reg_class_subset_p (ADDR_REGS
, rclass
))
2972 if (!legitimate_reload_constant_p (op
))
2976 /* load address will be used. */
2977 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2989 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2990 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2994 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2996 HOST_WIDE_INT addend
;
2999 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3002 if (addend
& (alignment
- 1))
3005 if (GET_CODE (symref
) == SYMBOL_REF
3006 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
))
3009 if (GET_CODE (symref
) == UNSPEC
3010 && alignment
<= UNITS_PER_LONG
)
3016 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3017 operand SCRATCH is used to reload the even part of the address and
3021 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
3023 HOST_WIDE_INT addend
;
3026 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3030 /* Easy case. The addend is even so larl will do fine. */
3031 emit_move_insn (reg
, addr
);
3034 /* We can leave the scratch register untouched if the target
3035 register is a valid base register. */
3036 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3037 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3040 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3041 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3044 emit_move_insn (scratch
,
3045 gen_rtx_CONST (Pmode
,
3046 gen_rtx_PLUS (Pmode
, symref
,
3047 GEN_INT (addend
- 1))));
3049 emit_move_insn (scratch
, symref
);
3051 /* Increment the address using la in order to avoid clobbering cc. */
3052 s390_load_address (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3056 /* Generate what is necessary to move between REG and MEM using
3057 SCRATCH. The direction is given by TOMEM. */
3060 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3062 /* Reload might have pulled a constant out of the literal pool.
3063 Force it back in. */
3064 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3065 || GET_CODE (mem
) == CONST
)
3066 mem
= force_const_mem (GET_MODE (reg
), mem
);
3068 gcc_assert (MEM_P (mem
));
3070 /* For a load from memory we can leave the scratch register
3071 untouched if the target register is a valid base register. */
3073 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3074 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3075 && GET_MODE (reg
) == GET_MODE (scratch
))
3078 /* Load address into scratch register. Since we can't have a
3079 secondary reload for a secondary reload we have to cover the case
3080 where larl would need a secondary reload here as well. */
3081 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3083 /* Now we can use a standard load/store to do the move. */
3085 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3087 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3090 /* Inform reload about cases where moving X with a mode MODE to a register in
3091 RCLASS requires an extra scratch or immediate register. Return the class
3092 needed for the immediate register. */
3095 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3096 machine_mode mode
, secondary_reload_info
*sri
)
3098 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3100 /* Intermediate register needed. */
3101 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3102 return GENERAL_REGS
;
3106 HOST_WIDE_INT offset
;
3109 /* On z10 several optimizer steps may generate larl operands with
3112 && s390_loadrelative_operand_p (x
, &symref
, &offset
)
3114 && !SYMBOL_REF_ALIGN1_P (symref
)
3115 && (offset
& 1) == 1)
3116 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3117 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3119 /* On z10 we need a scratch register when moving QI, TI or floating
3120 point mode values from or to a memory location with a SYMBOL_REF
3121 or if the symref addend of a SI or DI move is not aligned to the
3122 width of the access. */
3124 && s390_loadrelative_operand_p (XEXP (x
, 0), NULL
, NULL
)
3125 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3126 || (!TARGET_ZARCH
&& mode
== DImode
)
3127 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3128 && (!s390_check_symref_alignment (XEXP (x
, 0),
3129 GET_MODE_SIZE (mode
))))))
3131 #define __SECONDARY_RELOAD_CASE(M,m) \
3134 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3135 CODE_FOR_reload##m##di_tomem_z10; \
3137 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3138 CODE_FOR_reload##m##si_tomem_z10; \
3141 switch (GET_MODE (x
))
3143 __SECONDARY_RELOAD_CASE (QI
, qi
);
3144 __SECONDARY_RELOAD_CASE (HI
, hi
);
3145 __SECONDARY_RELOAD_CASE (SI
, si
);
3146 __SECONDARY_RELOAD_CASE (DI
, di
);
3147 __SECONDARY_RELOAD_CASE (TI
, ti
);
3148 __SECONDARY_RELOAD_CASE (SF
, sf
);
3149 __SECONDARY_RELOAD_CASE (DF
, df
);
3150 __SECONDARY_RELOAD_CASE (TF
, tf
);
3151 __SECONDARY_RELOAD_CASE (SD
, sd
);
3152 __SECONDARY_RELOAD_CASE (DD
, dd
);
3153 __SECONDARY_RELOAD_CASE (TD
, td
);
3158 #undef __SECONDARY_RELOAD_CASE
3162 /* We need a scratch register when loading a PLUS expression which
3163 is not a legitimate operand of the LOAD ADDRESS instruction. */
3164 /* LRA can deal with transformation of plus op very well -- so we
3165 don't need to prompt LRA in this case. */
3166 if (! lra_in_progress
&& in_p
&& s390_plus_operand (x
, mode
))
3167 sri
->icode
= (TARGET_64BIT
?
3168 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3170 /* Performing a multiword move from or to memory we have to make sure the
3171 second chunk in memory is addressable without causing a displacement
3172 overflow. If that would be the case we calculate the address in
3173 a scratch register. */
3175 && GET_CODE (XEXP (x
, 0)) == PLUS
3176 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3177 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3178 + GET_MODE_SIZE (mode
) - 1))
3180 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3181 in a s_operand address since we may fallback to lm/stm. So we only
3182 have to care about overflows in the b+i+d case. */
3183 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3184 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3185 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3186 /* For FP_REGS no lm/stm is available so this check is triggered
3187 for displacement overflows in b+i+d and b+d like addresses. */
3188 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3189 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3192 sri
->icode
= (TARGET_64BIT
?
3193 CODE_FOR_reloaddi_nonoffmem_in
:
3194 CODE_FOR_reloadsi_nonoffmem_in
);
3196 sri
->icode
= (TARGET_64BIT
?
3197 CODE_FOR_reloaddi_nonoffmem_out
:
3198 CODE_FOR_reloadsi_nonoffmem_out
);
3202 /* A scratch address register is needed when a symbolic constant is
3203 copied to r0 compiling with -fPIC. In other cases the target
3204 register might be used as temporary (see legitimize_pic_address). */
3205 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3206 sri
->icode
= (TARGET_64BIT
?
3207 CODE_FOR_reloaddi_PIC_addr
:
3208 CODE_FOR_reloadsi_PIC_addr
);
3210 /* Either scratch or no register needed. */
3214 /* Generate code to load SRC, which is PLUS that is not a
3215 legitimate operand for the LA instruction, into TARGET.
3216 SCRATCH may be used as scratch register. */
3219 s390_expand_plus_operand (rtx target
, rtx src
,
3223 struct s390_address ad
;
3225 /* src must be a PLUS; get its two operands. */
3226 gcc_assert (GET_CODE (src
) == PLUS
);
3227 gcc_assert (GET_MODE (src
) == Pmode
);
3229 /* Check if any of the two operands is already scheduled
3230 for replacement by reload. This can happen e.g. when
3231 float registers occur in an address. */
3232 sum1
= find_replacement (&XEXP (src
, 0));
3233 sum2
= find_replacement (&XEXP (src
, 1));
3234 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3236 /* If the address is already strictly valid, there's nothing to do. */
3237 if (!s390_decompose_address (src
, &ad
)
3238 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3239 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3241 /* Otherwise, one of the operands cannot be an address register;
3242 we reload its value into the scratch register. */
3243 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3245 emit_move_insn (scratch
, sum1
);
3248 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3250 emit_move_insn (scratch
, sum2
);
3254 /* According to the way these invalid addresses are generated
3255 in reload.c, it should never happen (at least on s390) that
3256 *neither* of the PLUS components, after find_replacements
3257 was applied, is an address register. */
3258 if (sum1
== scratch
&& sum2
== scratch
)
3264 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3267 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3268 is only ever performed on addresses, so we can mark the
3269 sum as legitimate for LA in any case. */
3270 s390_load_address (target
, src
);
3274 /* Return true if ADDR is a valid memory address.
3275 STRICT specifies whether strict register checking applies. */
3278 s390_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
3280 struct s390_address ad
;
3283 && larl_operand (addr
, VOIDmode
)
3284 && (mode
== VOIDmode
3285 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3288 if (!s390_decompose_address (addr
, &ad
))
3293 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3296 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3302 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3303 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3307 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3308 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3314 /* Return true if OP is a valid operand for the LA instruction.
3315 In 31-bit, we need to prove that the result is used as an
3316 address, as LA performs only a 31-bit addition. */
3319 legitimate_la_operand_p (rtx op
)
3321 struct s390_address addr
;
3322 if (!s390_decompose_address (op
, &addr
))
3325 return (TARGET_64BIT
|| addr
.pointer
);
3328 /* Return true if it is valid *and* preferable to use LA to
3329 compute the sum of OP1 and OP2. */
3332 preferred_la_operand_p (rtx op1
, rtx op2
)
3334 struct s390_address addr
;
3336 if (op2
!= const0_rtx
)
3337 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3339 if (!s390_decompose_address (op1
, &addr
))
3341 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3343 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3346 /* Avoid LA instructions with index register on z196; it is
3347 preferable to use regular add instructions when possible.
3348 Starting with zEC12 the la with index register is "uncracked"
3350 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3353 if (!TARGET_64BIT
&& !addr
.pointer
)
3359 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3360 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3366 /* Emit a forced load-address operation to load SRC into DST.
3367 This will use the LOAD ADDRESS instruction even in situations
3368 where legitimate_la_operand_p (SRC) returns false. */
3371 s390_load_address (rtx dst
, rtx src
)
3374 emit_move_insn (dst
, src
);
3376 emit_insn (gen_force_la_31 (dst
, src
));
3379 /* Return a legitimate reference for ORIG (an address) using the
3380 register REG. If REG is 0, a new pseudo is generated.
3382 There are two types of references that must be handled:
3384 1. Global data references must load the address from the GOT, via
3385 the PIC reg. An insn is emitted to do this load, and the reg is
3388 2. Static data references, constant pool addresses, and code labels
3389 compute the address as an offset from the GOT, whose base is in
3390 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3391 differentiate them from global data objects. The returned
3392 address is the PIC reg + an unspec constant.
3394 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3395 reg also appears in the address. */
3398 legitimize_pic_address (rtx orig
, rtx reg
)
3401 rtx addend
= const0_rtx
;
3404 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3406 if (GET_CODE (addr
) == CONST
)
3407 addr
= XEXP (addr
, 0);
3409 if (GET_CODE (addr
) == PLUS
)
3411 addend
= XEXP (addr
, 1);
3412 addr
= XEXP (addr
, 0);
3415 if ((GET_CODE (addr
) == LABEL_REF
3416 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
))
3417 || (GET_CODE (addr
) == UNSPEC
&&
3418 (XINT (addr
, 1) == UNSPEC_GOTENT
3419 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
3420 && GET_CODE (addend
) == CONST_INT
)
3422 /* This can be locally addressed. */
3424 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3425 rtx const_addr
= (GET_CODE (addr
) == UNSPEC
?
3426 gen_rtx_CONST (Pmode
, addr
) : addr
);
3428 if (TARGET_CPU_ZARCH
3429 && larl_operand (const_addr
, VOIDmode
)
3430 && INTVAL (addend
) < (HOST_WIDE_INT
)1 << 31
3431 && INTVAL (addend
) >= -((HOST_WIDE_INT
)1 << 31))
3433 if (INTVAL (addend
) & 1)
3435 /* LARL can't handle odd offsets, so emit a pair of LARL
3437 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3439 if (!DISP_IN_RANGE (INTVAL (addend
)))
3441 HOST_WIDE_INT even
= INTVAL (addend
) - 1;
3442 addr
= gen_rtx_PLUS (Pmode
, addr
, GEN_INT (even
));
3443 addr
= gen_rtx_CONST (Pmode
, addr
);
3444 addend
= const1_rtx
;
3447 emit_move_insn (temp
, addr
);
3448 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, addend
);
3452 s390_load_address (reg
, new_rtx
);
3458 /* If the offset is even, we can just use LARL. This
3459 will happen automatically. */
3464 /* No larl - Access local symbols relative to the GOT. */
3466 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3468 if (reload_in_progress
|| reload_completed
)
3469 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3471 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3472 if (addend
!= const0_rtx
)
3473 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
3474 addr
= gen_rtx_CONST (Pmode
, addr
);
3475 addr
= force_const_mem (Pmode
, addr
);
3476 emit_move_insn (temp
, addr
);
3478 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3481 s390_load_address (reg
, new_rtx
);
3486 else if (GET_CODE (addr
) == SYMBOL_REF
&& addend
== const0_rtx
)
3488 /* A non-local symbol reference without addend.
3490 The symbol ref is wrapped into an UNSPEC to make sure the
3491 proper operand modifier (@GOT or @GOTENT) will be emitted.
3492 This will tell the linker to put the symbol into the GOT.
3494 Additionally the code dereferencing the GOT slot is emitted here.
3496 An addend to the symref needs to be added afterwards.
3497 legitimize_pic_address calls itself recursively to handle
3498 that case. So no need to do it here. */
3501 reg
= gen_reg_rtx (Pmode
);
3505 /* Use load relative if possible.
3506 lgrl <target>, sym@GOTENT */
3507 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3508 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3509 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
3511 emit_move_insn (reg
, new_rtx
);
3514 else if (flag_pic
== 1)
3516 /* Assume GOT offset is a valid displacement operand (< 4k
3517 or < 512k with z990). This is handled the same way in
3518 both 31- and 64-bit code (@GOT).
3519 lg <target>, sym@GOT(r12) */
3521 if (reload_in_progress
|| reload_completed
)
3522 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3524 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3525 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3526 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3527 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3528 emit_move_insn (reg
, new_rtx
);
3531 else if (TARGET_CPU_ZARCH
)
3533 /* If the GOT offset might be >= 4k, we determine the position
3534 of the GOT entry via a PC-relative LARL (@GOTENT).
3535 larl temp, sym@GOTENT
3536 lg <target>, 0(temp) */
3538 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3540 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3541 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3543 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3544 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3545 emit_move_insn (temp
, new_rtx
);
3547 new_rtx
= gen_const_mem (Pmode
, temp
);
3548 emit_move_insn (reg
, new_rtx
);
3554 /* If the GOT offset might be >= 4k, we have to load it
3555 from the literal pool (@GOT).
3557 lg temp, lit-litbase(r13)
3558 lg <target>, 0(temp)
3559 lit: .long sym@GOT */
3561 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3563 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3564 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3566 if (reload_in_progress
|| reload_completed
)
3567 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3569 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3570 addr
= gen_rtx_CONST (Pmode
, addr
);
3571 addr
= force_const_mem (Pmode
, addr
);
3572 emit_move_insn (temp
, addr
);
3574 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3575 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3576 emit_move_insn (reg
, new_rtx
);
3580 else if (GET_CODE (addr
) == UNSPEC
&& GET_CODE (addend
) == CONST_INT
)
3582 gcc_assert (XVECLEN (addr
, 0) == 1);
3583 switch (XINT (addr
, 1))
3585 /* These address symbols (or PLT slots) relative to the GOT
3586 (not GOT slots!). In general this will exceed the
3587 displacement range so these value belong into the literal
3591 new_rtx
= force_const_mem (Pmode
, orig
);
3594 /* For -fPIC the GOT size might exceed the displacement
3595 range so make sure the value is in the literal pool. */
3598 new_rtx
= force_const_mem (Pmode
, orig
);
3601 /* For @GOTENT larl is used. This is handled like local
3607 /* @PLT is OK as is on 64-bit, must be converted to
3608 GOT-relative @PLTOFF on 31-bit. */
3610 if (!TARGET_CPU_ZARCH
)
3612 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3614 if (reload_in_progress
|| reload_completed
)
3615 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3617 addr
= XVECEXP (addr
, 0, 0);
3618 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3620 if (addend
!= const0_rtx
)
3621 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
3622 addr
= gen_rtx_CONST (Pmode
, addr
);
3623 addr
= force_const_mem (Pmode
, addr
);
3624 emit_move_insn (temp
, addr
);
3626 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3629 s390_load_address (reg
, new_rtx
);
3634 /* On 64 bit larl can be used. This case is handled like
3635 local symbol refs. */
3639 /* Everything else cannot happen. */
3644 else if (addend
!= const0_rtx
)
3646 /* Otherwise, compute the sum. */
3648 rtx base
= legitimize_pic_address (addr
, reg
);
3649 new_rtx
= legitimize_pic_address (addend
,
3650 base
== reg
? NULL_RTX
: reg
);
3651 if (GET_CODE (new_rtx
) == CONST_INT
)
3652 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
3655 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3657 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3658 new_rtx
= XEXP (new_rtx
, 1);
3660 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3663 if (GET_CODE (new_rtx
) == CONST
)
3664 new_rtx
= XEXP (new_rtx
, 0);
3665 new_rtx
= force_operand (new_rtx
, 0);
3671 /* Load the thread pointer into a register. */
3674 s390_get_thread_pointer (void)
3676 rtx tp
= gen_reg_rtx (Pmode
);
3678 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3679 mark_reg_pointer (tp
, BITS_PER_WORD
);
3684 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3685 in s390_tls_symbol which always refers to __tls_get_offset.
3686 The returned offset is written to RESULT_REG and an USE rtx is
3687 generated for TLS_CALL. */
3689 static GTY(()) rtx s390_tls_symbol
;
3692 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3697 emit_insn (s390_load_got ());
3699 if (!s390_tls_symbol
)
3700 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3702 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3703 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3705 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3706 RTL_CONST_CALL_P (insn
) = 1;
3709 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3710 this (thread-local) address. REG may be used as temporary. */
3713 legitimize_tls_address (rtx addr
, rtx reg
)
3715 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3717 if (GET_CODE (addr
) == SYMBOL_REF
)
3718 switch (tls_symbolic_operand (addr
))
3720 case TLS_MODEL_GLOBAL_DYNAMIC
:
3722 r2
= gen_rtx_REG (Pmode
, 2);
3723 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3724 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3725 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3726 emit_move_insn (r2
, new_rtx
);
3727 s390_emit_tls_call_insn (r2
, tls_call
);
3728 insn
= get_insns ();
3731 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3732 temp
= gen_reg_rtx (Pmode
);
3733 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3735 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3738 s390_load_address (reg
, new_rtx
);
3743 case TLS_MODEL_LOCAL_DYNAMIC
:
3745 r2
= gen_rtx_REG (Pmode
, 2);
3746 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3747 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3748 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3749 emit_move_insn (r2
, new_rtx
);
3750 s390_emit_tls_call_insn (r2
, tls_call
);
3751 insn
= get_insns ();
3754 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3755 temp
= gen_reg_rtx (Pmode
);
3756 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3758 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3759 base
= gen_reg_rtx (Pmode
);
3760 s390_load_address (base
, new_rtx
);
3762 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3763 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3764 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3765 temp
= gen_reg_rtx (Pmode
);
3766 emit_move_insn (temp
, new_rtx
);
3768 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3771 s390_load_address (reg
, new_rtx
);
3776 case TLS_MODEL_INITIAL_EXEC
:
3779 /* Assume GOT offset < 4k. This is handled the same way
3780 in both 31- and 64-bit code. */
3782 if (reload_in_progress
|| reload_completed
)
3783 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3785 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3786 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3787 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3788 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3789 temp
= gen_reg_rtx (Pmode
);
3790 emit_move_insn (temp
, new_rtx
);
3792 else if (TARGET_CPU_ZARCH
)
3794 /* If the GOT offset might be >= 4k, we determine the position
3795 of the GOT entry via a PC-relative LARL. */
3797 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3798 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3799 temp
= gen_reg_rtx (Pmode
);
3800 emit_move_insn (temp
, new_rtx
);
3802 new_rtx
= gen_const_mem (Pmode
, temp
);
3803 temp
= gen_reg_rtx (Pmode
);
3804 emit_move_insn (temp
, new_rtx
);
3808 /* If the GOT offset might be >= 4k, we have to load it
3809 from the literal pool. */
3811 if (reload_in_progress
|| reload_completed
)
3812 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3814 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3815 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3816 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3817 temp
= gen_reg_rtx (Pmode
);
3818 emit_move_insn (temp
, new_rtx
);
3820 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3821 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3823 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3824 temp
= gen_reg_rtx (Pmode
);
3825 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3829 /* In position-dependent code, load the absolute address of
3830 the GOT entry from the literal pool. */
3832 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3833 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3834 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3835 temp
= gen_reg_rtx (Pmode
);
3836 emit_move_insn (temp
, new_rtx
);
3839 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3840 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3841 temp
= gen_reg_rtx (Pmode
);
3842 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3845 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3848 s390_load_address (reg
, new_rtx
);
3853 case TLS_MODEL_LOCAL_EXEC
:
3854 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3855 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3856 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3857 temp
= gen_reg_rtx (Pmode
);
3858 emit_move_insn (temp
, new_rtx
);
3860 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3863 s390_load_address (reg
, new_rtx
);
3872 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3874 switch (XINT (XEXP (addr
, 0), 1))
3876 case UNSPEC_INDNTPOFF
:
3877 gcc_assert (TARGET_CPU_ZARCH
);
3886 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3887 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3889 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3890 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3891 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3893 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3894 new_rtx
= plus_constant (Pmode
, new_rtx
,
3895 INTVAL (XEXP (XEXP (addr
, 0), 1)));
3896 new_rtx
= force_operand (new_rtx
, 0);
3900 gcc_unreachable (); /* for now ... */
3905 /* Emit insns making the address in operands[1] valid for a standard
3906 move to operands[0]. operands[1] is replaced by an address which
3907 should be used instead of the former RTX to emit the move
3911 emit_symbolic_move (rtx
*operands
)
3913 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3915 if (GET_CODE (operands
[0]) == MEM
)
3916 operands
[1] = force_reg (Pmode
, operands
[1]);
3917 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3918 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3920 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3923 /* Try machine-dependent ways of modifying an illegitimate address X
3924 to be legitimate. If we find one, return the new, valid address.
3926 OLDX is the address as it was before break_out_memory_refs was called.
3927 In some cases it is useful to look at this to decide what needs to be done.
3929 MODE is the mode of the operand pointed to by X.
3931 When -fpic is used, special handling is needed for symbolic references.
3932 See comments by legitimize_pic_address for details. */
3935 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3936 machine_mode mode ATTRIBUTE_UNUSED
)
3938 rtx constant_term
= const0_rtx
;
3940 if (TLS_SYMBOLIC_CONST (x
))
3942 x
= legitimize_tls_address (x
, 0);
3944 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3947 else if (GET_CODE (x
) == PLUS
3948 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3949 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3955 if (SYMBOLIC_CONST (x
)
3956 || (GET_CODE (x
) == PLUS
3957 && (SYMBOLIC_CONST (XEXP (x
, 0))
3958 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3959 x
= legitimize_pic_address (x
, 0);
3961 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3965 x
= eliminate_constant_term (x
, &constant_term
);
3967 /* Optimize loading of large displacements by splitting them
3968 into the multiple of 4K and the rest; this allows the
3969 former to be CSE'd if possible.
3971 Don't do this if the displacement is added to a register
3972 pointing into the stack frame, as the offsets will
3973 change later anyway. */
3975 if (GET_CODE (constant_term
) == CONST_INT
3976 && !TARGET_LONG_DISPLACEMENT
3977 && !DISP_IN_RANGE (INTVAL (constant_term
))
3978 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3980 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3981 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3983 rtx temp
= gen_reg_rtx (Pmode
);
3984 rtx val
= force_operand (GEN_INT (upper
), temp
);
3986 emit_move_insn (temp
, val
);
3988 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3989 constant_term
= GEN_INT (lower
);
3992 if (GET_CODE (x
) == PLUS
)
3994 if (GET_CODE (XEXP (x
, 0)) == REG
)
3996 rtx temp
= gen_reg_rtx (Pmode
);
3997 rtx val
= force_operand (XEXP (x
, 1), temp
);
3999 emit_move_insn (temp
, val
);
4001 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
4004 else if (GET_CODE (XEXP (x
, 1)) == REG
)
4006 rtx temp
= gen_reg_rtx (Pmode
);
4007 rtx val
= force_operand (XEXP (x
, 0), temp
);
4009 emit_move_insn (temp
, val
);
4011 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
4015 if (constant_term
!= const0_rtx
)
4016 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
4021 /* Try a machine-dependent way of reloading an illegitimate address AD
4022 operand. If we find one, push the reload and return the new address.
4024 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4025 and TYPE is the reload type of the current reload. */
4028 legitimize_reload_address (rtx ad
, machine_mode mode ATTRIBUTE_UNUSED
,
4029 int opnum
, int type
)
4031 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
4034 if (GET_CODE (ad
) == PLUS
)
4036 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
4037 XEXP (ad
, 0), XEXP (ad
, 1));
4042 if (GET_CODE (ad
) == PLUS
4043 && GET_CODE (XEXP (ad
, 0)) == REG
4044 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
4045 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
4047 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
4048 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
4049 rtx cst
, tem
, new_rtx
;
4051 cst
= GEN_INT (upper
);
4052 if (!legitimate_reload_constant_p (cst
))
4053 cst
= force_const_mem (Pmode
, cst
);
4055 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
4056 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
4058 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
4059 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4060 opnum
, (enum reload_type
) type
);
4067 /* Emit code to move LEN bytes from DST to SRC. */
4070 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4072 /* When tuning for z10 or higher we rely on the Glibc functions to
4073 do the right thing. Only for constant lengths below 64k we will
4074 generate inline code. */
4075 if (s390_tune
>= PROCESSOR_2097_Z10
4076 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
4079 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4081 if (INTVAL (len
) > 0)
4082 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4085 else if (TARGET_MVCLE
)
4087 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4092 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4093 rtx_code_label
*loop_start_label
= gen_label_rtx ();
4094 rtx_code_label
*loop_end_label
= gen_label_rtx ();
4095 rtx_code_label
*end_label
= gen_label_rtx ();
4098 mode
= GET_MODE (len
);
4099 if (mode
== VOIDmode
)
4102 dst_addr
= gen_reg_rtx (Pmode
);
4103 src_addr
= gen_reg_rtx (Pmode
);
4104 count
= gen_reg_rtx (mode
);
4105 blocks
= gen_reg_rtx (mode
);
4107 convert_move (count
, len
, 1);
4108 emit_cmp_and_jump_insns (count
, const0_rtx
,
4109 EQ
, NULL_RTX
, mode
, 1, end_label
);
4111 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4112 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4113 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4114 src
= change_address (src
, VOIDmode
, src_addr
);
4116 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4119 emit_move_insn (count
, temp
);
4121 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4124 emit_move_insn (blocks
, temp
);
4126 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4127 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4129 emit_label (loop_start_label
);
4132 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4136 /* Issue a read prefetch for the +3 cache line. */
4137 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4138 const0_rtx
, const0_rtx
);
4139 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4140 emit_insn (prefetch
);
4142 /* Issue a write prefetch for the +3 cache line. */
4143 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4144 const1_rtx
, const0_rtx
);
4145 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4146 emit_insn (prefetch
);
4149 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4150 s390_load_address (dst_addr
,
4151 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4152 s390_load_address (src_addr
,
4153 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4155 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4158 emit_move_insn (blocks
, temp
);
4160 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4161 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4163 emit_jump (loop_start_label
);
4164 emit_label (loop_end_label
);
4166 emit_insn (gen_movmem_short (dst
, src
,
4167 convert_to_mode (Pmode
, count
, 1)));
4168 emit_label (end_label
);
4173 /* Emit code to set LEN bytes at DST to VAL.
4174 Make use of clrmem if VAL is zero. */
4177 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4179 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4182 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4184 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4186 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4187 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4190 /* Initialize memory by storing the first byte. */
4191 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4193 if (INTVAL (len
) > 1)
4195 /* Initiate 1 byte overlap move.
4196 The first byte of DST is propagated through DSTP1.
4197 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4198 DST is set to size 1 so the rest of the memory location
4199 does not count as source operand. */
4200 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4201 set_mem_size (dst
, 1);
4203 emit_insn (gen_movmem_short (dstp1
, dst
,
4204 GEN_INT (INTVAL (len
) - 2)));
4209 else if (TARGET_MVCLE
)
4211 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4212 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4217 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4218 rtx_code_label
*loop_start_label
= gen_label_rtx ();
4219 rtx_code_label
*loop_end_label
= gen_label_rtx ();
4220 rtx_code_label
*end_label
= gen_label_rtx ();
4223 mode
= GET_MODE (len
);
4224 if (mode
== VOIDmode
)
4227 dst_addr
= gen_reg_rtx (Pmode
);
4228 count
= gen_reg_rtx (mode
);
4229 blocks
= gen_reg_rtx (mode
);
4231 convert_move (count
, len
, 1);
4232 emit_cmp_and_jump_insns (count
, const0_rtx
,
4233 EQ
, NULL_RTX
, mode
, 1, end_label
);
4235 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4236 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4238 if (val
== const0_rtx
)
4239 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4243 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4244 set_mem_size (dst
, 1);
4246 /* Initialize memory by storing the first byte. */
4247 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4249 /* If count is 1 we are done. */
4250 emit_cmp_and_jump_insns (count
, const1_rtx
,
4251 EQ
, NULL_RTX
, mode
, 1, end_label
);
4253 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4257 emit_move_insn (count
, temp
);
4259 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4262 emit_move_insn (blocks
, temp
);
4264 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4265 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4267 emit_label (loop_start_label
);
4270 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4272 /* Issue a write prefetch for the +4 cache line. */
4273 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4275 const1_rtx
, const0_rtx
);
4276 emit_insn (prefetch
);
4277 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4280 if (val
== const0_rtx
)
4281 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4283 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4284 s390_load_address (dst_addr
,
4285 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4287 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4290 emit_move_insn (blocks
, temp
);
4292 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4293 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4295 emit_jump (loop_start_label
);
4296 emit_label (loop_end_label
);
4298 if (val
== const0_rtx
)
4299 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4301 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4302 emit_label (end_label
);
4306 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4307 and return the result in TARGET. */
4310 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4312 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4315 /* When tuning for z10 or higher we rely on the Glibc functions to
4316 do the right thing. Only for constant lengths below 64k we will
4317 generate inline code. */
4318 if (s390_tune
>= PROCESSOR_2097_Z10
4319 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
4322 /* As the result of CMPINT is inverted compared to what we need,
4323 we have to swap the operands. */
4324 tmp
= op0
; op0
= op1
; op1
= tmp
;
4326 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4328 if (INTVAL (len
) > 0)
4330 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4331 emit_insn (gen_cmpint (target
, ccreg
));
4334 emit_move_insn (target
, const0_rtx
);
4336 else if (TARGET_MVCLE
)
4338 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4339 emit_insn (gen_cmpint (target
, ccreg
));
4343 rtx addr0
, addr1
, count
, blocks
, temp
;
4344 rtx_code_label
*loop_start_label
= gen_label_rtx ();
4345 rtx_code_label
*loop_end_label
= gen_label_rtx ();
4346 rtx_code_label
*end_label
= gen_label_rtx ();
4349 mode
= GET_MODE (len
);
4350 if (mode
== VOIDmode
)
4353 addr0
= gen_reg_rtx (Pmode
);
4354 addr1
= gen_reg_rtx (Pmode
);
4355 count
= gen_reg_rtx (mode
);
4356 blocks
= gen_reg_rtx (mode
);
4358 convert_move (count
, len
, 1);
4359 emit_cmp_and_jump_insns (count
, const0_rtx
,
4360 EQ
, NULL_RTX
, mode
, 1, end_label
);
4362 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4363 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4364 op0
= change_address (op0
, VOIDmode
, addr0
);
4365 op1
= change_address (op1
, VOIDmode
, addr1
);
4367 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4370 emit_move_insn (count
, temp
);
4372 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4375 emit_move_insn (blocks
, temp
);
4377 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4378 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4380 emit_label (loop_start_label
);
4383 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4387 /* Issue a read prefetch for the +2 cache line of operand 1. */
4388 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4389 const0_rtx
, const0_rtx
);
4390 emit_insn (prefetch
);
4391 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4393 /* Issue a read prefetch for the +2 cache line of operand 2. */
4394 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4395 const0_rtx
, const0_rtx
);
4396 emit_insn (prefetch
);
4397 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4400 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4401 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4402 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4403 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4404 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4405 emit_jump_insn (temp
);
4407 s390_load_address (addr0
,
4408 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4409 s390_load_address (addr1
,
4410 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4412 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4415 emit_move_insn (blocks
, temp
);
4417 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4418 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4420 emit_jump (loop_start_label
);
4421 emit_label (loop_end_label
);
4423 emit_insn (gen_cmpmem_short (op0
, op1
,
4424 convert_to_mode (Pmode
, count
, 1)));
4425 emit_label (end_label
);
4427 emit_insn (gen_cmpint (target
, ccreg
));
4433 /* Expand conditional increment or decrement using alc/slb instructions.
4434 Should generate code setting DST to either SRC or SRC + INCREMENT,
4435 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4436 Returns true if successful, false otherwise.
4438 That makes it possible to implement some if-constructs without jumps e.g.:
4439 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4440 unsigned int a, b, c;
4441 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4442 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4443 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4444 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4446 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4447 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4448 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4449 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4450 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4453 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4454 rtx dst
, rtx src
, rtx increment
)
4456 machine_mode cmp_mode
;
4457 machine_mode cc_mode
;
4463 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4464 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4466 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4467 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4472 /* Try ADD LOGICAL WITH CARRY. */
4473 if (increment
== const1_rtx
)
4475 /* Determine CC mode to use. */
4476 if (cmp_code
== EQ
|| cmp_code
== NE
)
4478 if (cmp_op1
!= const0_rtx
)
4480 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4481 NULL_RTX
, 0, OPTAB_WIDEN
);
4482 cmp_op1
= const0_rtx
;
4485 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4488 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4493 cmp_code
= swap_condition (cmp_code
);
4510 /* Emit comparison instruction pattern. */
4511 if (!register_operand (cmp_op0
, cmp_mode
))
4512 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4514 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4515 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4516 /* We use insn_invalid_p here to add clobbers if required. */
4517 ret
= insn_invalid_p (emit_insn (insn
), false);
4520 /* Emit ALC instruction pattern. */
4521 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4522 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4525 if (src
!= const0_rtx
)
4527 if (!register_operand (src
, GET_MODE (dst
)))
4528 src
= force_reg (GET_MODE (dst
), src
);
4530 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4531 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4534 p
= rtvec_alloc (2);
4536 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4538 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4539 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4544 /* Try SUBTRACT LOGICAL WITH BORROW. */
4545 if (increment
== constm1_rtx
)
4547 /* Determine CC mode to use. */
4548 if (cmp_code
== EQ
|| cmp_code
== NE
)
4550 if (cmp_op1
!= const0_rtx
)
4552 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4553 NULL_RTX
, 0, OPTAB_WIDEN
);
4554 cmp_op1
= const0_rtx
;
4557 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4560 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4565 cmp_code
= swap_condition (cmp_code
);
4582 /* Emit comparison instruction pattern. */
4583 if (!register_operand (cmp_op0
, cmp_mode
))
4584 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4586 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4587 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4588 /* We use insn_invalid_p here to add clobbers if required. */
4589 ret
= insn_invalid_p (emit_insn (insn
), false);
4592 /* Emit SLB instruction pattern. */
4593 if (!register_operand (src
, GET_MODE (dst
)))
4594 src
= force_reg (GET_MODE (dst
), src
);
4596 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4597 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4598 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4599 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4601 p
= rtvec_alloc (2);
4603 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4605 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4606 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4614 /* Expand code for the insv template. Return true if successful. */
4617 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4619 int bitsize
= INTVAL (op1
);
4620 int bitpos
= INTVAL (op2
);
4621 machine_mode mode
= GET_MODE (dest
);
4623 int smode_bsize
, mode_bsize
;
4626 if (bitsize
+ bitpos
> GET_MODE_BITSIZE (mode
))
4629 /* Generate INSERT IMMEDIATE (IILL et al). */
4630 /* (set (ze (reg)) (const_int)). */
4632 && register_operand (dest
, word_mode
)
4633 && (bitpos
% 16) == 0
4634 && (bitsize
% 16) == 0
4635 && const_int_operand (src
, VOIDmode
))
4637 HOST_WIDE_INT val
= INTVAL (src
);
4638 int regpos
= bitpos
+ bitsize
;
4640 while (regpos
> bitpos
)
4642 machine_mode putmode
;
4645 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4650 putsize
= GET_MODE_BITSIZE (putmode
);
4652 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4655 gen_int_mode (val
, putmode
));
4658 gcc_assert (regpos
== bitpos
);
4662 smode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4663 smode_bsize
= GET_MODE_BITSIZE (smode
);
4664 mode_bsize
= GET_MODE_BITSIZE (mode
);
4666 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4668 && (bitsize
% BITS_PER_UNIT
) == 0
4670 && (register_operand (src
, word_mode
)
4671 || const_int_operand (src
, VOIDmode
)))
4673 /* Emit standard pattern if possible. */
4674 if (smode_bsize
== bitsize
)
4676 emit_move_insn (adjust_address (dest
, smode
, 0),
4677 gen_lowpart (smode
, src
));
4681 /* (set (ze (mem)) (const_int)). */
4682 else if (const_int_operand (src
, VOIDmode
))
4684 int size
= bitsize
/ BITS_PER_UNIT
;
4685 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
4687 UNITS_PER_WORD
- size
);
4689 dest
= adjust_address (dest
, BLKmode
, 0);
4690 set_mem_size (dest
, size
);
4691 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4695 /* (set (ze (mem)) (reg)). */
4696 else if (register_operand (src
, word_mode
))
4699 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4703 /* Emit st,stcmh sequence. */
4704 int stcmh_width
= bitsize
- 32;
4705 int size
= stcmh_width
/ BITS_PER_UNIT
;
4707 emit_move_insn (adjust_address (dest
, SImode
, size
),
4708 gen_lowpart (SImode
, src
));
4709 set_mem_size (dest
, size
);
4710 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4711 GEN_INT (stcmh_width
),
4713 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
4719 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4720 if ((bitpos
% BITS_PER_UNIT
) == 0
4721 && (bitsize
% BITS_PER_UNIT
) == 0
4722 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
4724 && (mode
== DImode
|| mode
== SImode
)
4725 && register_operand (dest
, mode
))
4727 /* Emit a strict_low_part pattern if possible. */
4728 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
4730 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
4731 op
= gen_rtx_SET (VOIDmode
, op
, gen_lowpart (smode
, src
));
4732 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4733 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4737 /* ??? There are more powerful versions of ICM that are not
4738 completely represented in the md file. */
4741 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4742 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
4744 machine_mode mode_s
= GET_MODE (src
);
4746 if (mode_s
== VOIDmode
)
4748 /* Assume const_int etc already in the proper mode. */
4749 src
= force_reg (mode
, src
);
4751 else if (mode_s
!= mode
)
4753 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
4754 src
= force_reg (mode_s
, src
);
4755 src
= gen_lowpart (mode
, src
);
4758 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
4759 op
= gen_rtx_SET (VOIDmode
, op
, src
);
4763 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4764 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
4774 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4775 register that holds VAL of mode MODE shifted by COUNT bits. */
4778 s390_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
4780 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4781 NULL_RTX
, 1, OPTAB_DIRECT
);
4782 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4783 NULL_RTX
, 1, OPTAB_DIRECT
);
4786 /* Structure to hold the initial parameters for a compare_and_swap operation
4787 in HImode and QImode. */
4789 struct alignment_context
4791 rtx memsi
; /* SI aligned memory location. */
4792 rtx shift
; /* Bit offset with regard to lsb. */
4793 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4794 rtx modemaski
; /* ~modemask */
4795 bool aligned
; /* True if memory is aligned, false else. */
4798 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4799 structure AC for transparent simplifying, if the memory alignment is known
4800 to be at least 32bit. MEM is the memory location for the actual operation
4801 and MODE its mode. */
4804 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4807 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4808 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4811 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4814 /* Alignment is unknown. */
4815 rtx byteoffset
, addr
, align
;
4817 /* Force the address into a register. */
4818 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4820 /* Align it to SImode. */
4821 align
= expand_simple_binop (Pmode
, AND
, addr
,
4822 GEN_INT (-GET_MODE_SIZE (SImode
)),
4823 NULL_RTX
, 1, OPTAB_DIRECT
);
4825 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4826 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4827 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4828 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4830 /* Calculate shiftcount. */
4831 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4832 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4833 NULL_RTX
, 1, OPTAB_DIRECT
);
4834 /* As we already have some offset, evaluate the remaining distance. */
4835 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4836 NULL_RTX
, 1, OPTAB_DIRECT
);
4839 /* Shift is the byte count, but we need the bitcount. */
4840 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
4841 NULL_RTX
, 1, OPTAB_DIRECT
);
4843 /* Calculate masks. */
4844 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4845 GEN_INT (GET_MODE_MASK (mode
)),
4846 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
4847 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
4851 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4852 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4853 perform the merge in SEQ2. */
4856 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
4857 machine_mode mode
, rtx val
, rtx ins
)
4864 tmp
= copy_to_mode_reg (SImode
, val
);
4865 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
4869 *seq2
= get_insns ();
4876 /* Failed to use insv. Generate a two part shift and mask. */
4878 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
4879 *seq1
= get_insns ();
4883 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
4884 *seq2
= get_insns ();
4890 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4891 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4892 value to set if CMP == MEM. */
4895 s390_expand_cs_hqi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
4896 rtx cmp
, rtx new_rtx
, bool is_weak
)
4898 struct alignment_context ac
;
4899 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
4900 rtx res
= gen_reg_rtx (SImode
);
4901 rtx_code_label
*csloop
= NULL
, *csend
= NULL
;
4903 gcc_assert (MEM_P (mem
));
4905 init_alignment_context (&ac
, mem
, mode
);
4907 /* Load full word. Subsequent loads are performed by CS. */
4908 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4909 NULL_RTX
, 1, OPTAB_DIRECT
);
4911 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4912 possible, we try to use insv to make this happen efficiently. If
4913 that fails we'll generate code both inside and outside the loop. */
4914 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
4915 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
4922 /* Start CS loop. */
4925 /* Begin assuming success. */
4926 emit_move_insn (btarget
, const1_rtx
);
4928 csloop
= gen_label_rtx ();
4929 csend
= gen_label_rtx ();
4930 emit_label (csloop
);
4933 /* val = "<mem>00..0<mem>"
4934 * cmp = "00..0<cmp>00..0"
4935 * new = "00..0<new>00..0"
4941 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
);
4943 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
4948 /* Jump to end if we're done (likely?). */
4949 s390_emit_jump (csend
, cc
);
4951 /* Check for changes outside mode, and loop internal if so.
4952 Arrange the moves so that the compare is adjacent to the
4953 branch so that we can generate CRJ. */
4954 tmp
= copy_to_reg (val
);
4955 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
4957 cc
= s390_emit_compare (NE
, val
, tmp
);
4958 s390_emit_jump (csloop
, cc
);
4961 emit_move_insn (btarget
, const0_rtx
);
4965 /* Return the correct part of the bitfield. */
4966 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4967 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4970 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4971 and VAL the value to play with. If AFTER is true then store the value
4972 MEM holds after the operation, if AFTER is false then store the value MEM
4973 holds before the operation. If TARGET is zero then discard that value, else
4974 store it to TARGET. */
4977 s390_expand_atomic (machine_mode mode
, enum rtx_code code
,
4978 rtx target
, rtx mem
, rtx val
, bool after
)
4980 struct alignment_context ac
;
4982 rtx new_rtx
= gen_reg_rtx (SImode
);
4983 rtx orig
= gen_reg_rtx (SImode
);
4984 rtx_code_label
*csloop
= gen_label_rtx ();
4986 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4987 gcc_assert (MEM_P (mem
));
4989 init_alignment_context (&ac
, mem
, mode
);
4991 /* Shift val to the correct bit positions.
4992 Preserve "icm", but prevent "ex icm". */
4993 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4994 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4996 /* Further preparation insns. */
4997 if (code
== PLUS
|| code
== MINUS
)
4998 emit_move_insn (orig
, val
);
4999 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
5000 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
5001 NULL_RTX
, 1, OPTAB_DIRECT
);
5003 /* Load full word. Subsequent loads are performed by CS. */
5004 cmp
= force_reg (SImode
, ac
.memsi
);
5006 /* Start CS loop. */
5007 emit_label (csloop
);
5008 emit_move_insn (new_rtx
, cmp
);
5010 /* Patch new with val at correct position. */
5015 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
5016 NULL_RTX
, 1, OPTAB_DIRECT
);
5017 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
5018 NULL_RTX
, 1, OPTAB_DIRECT
);
5021 if (ac
.aligned
&& MEM_P (val
))
5022 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
5026 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
5027 NULL_RTX
, 1, OPTAB_DIRECT
);
5028 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
5029 NULL_RTX
, 1, OPTAB_DIRECT
);
5035 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
5036 NULL_RTX
, 1, OPTAB_DIRECT
);
5038 case MULT
: /* NAND */
5039 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
5040 NULL_RTX
, 1, OPTAB_DIRECT
);
5041 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
5042 NULL_RTX
, 1, OPTAB_DIRECT
);
5048 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
5049 ac
.memsi
, cmp
, new_rtx
));
5051 /* Return the correct part of the bitfield. */
5053 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
5054 after
? new_rtx
: cmp
, ac
.shift
,
5055 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
5058 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5059 We need to emit DTP-relative relocations. */
5061 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
5064 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5069 fputs ("\t.long\t", file
);
5072 fputs ("\t.quad\t", file
);
5077 output_addr_const (file
, x
);
5078 fputs ("@DTPOFF", file
);
5081 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5082 /* Implement TARGET_MANGLE_TYPE. */
5085 s390_mangle_type (const_tree type
)
5087 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
5088 && TARGET_LONG_DOUBLE_128
)
5091 /* For all other types, use normal C++ mangling. */
5096 /* In the name of slightly smaller debug output, and to cater to
5097 general assembler lossage, recognize various UNSPEC sequences
5098 and turn them back into a direct symbol reference. */
5101 s390_delegitimize_address (rtx orig_x
)
5105 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5108 /* Extract the symbol ref from:
5109 (plus:SI (reg:SI 12 %r12)
5110 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5111 UNSPEC_GOTOFF/PLTOFF)))
5113 (plus:SI (reg:SI 12 %r12)
5114 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5115 UNSPEC_GOTOFF/PLTOFF)
5116 (const_int 4 [0x4])))) */
5117 if (GET_CODE (x
) == PLUS
5118 && REG_P (XEXP (x
, 0))
5119 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
5120 && GET_CODE (XEXP (x
, 1)) == CONST
)
5122 HOST_WIDE_INT offset
= 0;
5124 /* The const operand. */
5125 y
= XEXP (XEXP (x
, 1), 0);
5127 if (GET_CODE (y
) == PLUS
5128 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
5130 offset
= INTVAL (XEXP (y
, 1));
5134 if (GET_CODE (y
) == UNSPEC
5135 && (XINT (y
, 1) == UNSPEC_GOTOFF
5136 || XINT (y
, 1) == UNSPEC_PLTOFF
))
5137 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
5140 if (GET_CODE (x
) != MEM
)
5144 if (GET_CODE (x
) == PLUS
5145 && GET_CODE (XEXP (x
, 1)) == CONST
5146 && GET_CODE (XEXP (x
, 0)) == REG
5147 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5149 y
= XEXP (XEXP (x
, 1), 0);
5150 if (GET_CODE (y
) == UNSPEC
5151 && XINT (y
, 1) == UNSPEC_GOT
)
5152 y
= XVECEXP (y
, 0, 0);
5156 else if (GET_CODE (x
) == CONST
)
5158 /* Extract the symbol ref from:
5159 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5160 UNSPEC_PLT/GOTENT))) */
5163 if (GET_CODE (y
) == UNSPEC
5164 && (XINT (y
, 1) == UNSPEC_GOTENT
5165 || XINT (y
, 1) == UNSPEC_PLT
))
5166 y
= XVECEXP (y
, 0, 0);
5173 if (GET_MODE (orig_x
) != Pmode
)
5175 if (GET_MODE (orig_x
) == BLKmode
)
5177 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
5184 /* Output operand OP to stdio stream FILE.
5185 OP is an address (register + offset) which is not used to address data;
5186 instead the rightmost bits are interpreted as the value. */
5189 print_shift_count_operand (FILE *file
, rtx op
)
5191 HOST_WIDE_INT offset
;
5194 /* Extract base register and offset. */
5195 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5201 gcc_assert (GET_CODE (base
) == REG
);
5202 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5203 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5206 /* Offsets are constricted to twelve bits. */
5207 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5209 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5212 /* Returns -1 if the function should not be made hotpatchable. Otherwise it
5213 returns a number >= 0 that is the desired size of the hotpatch trampoline
5216 static int s390_function_num_hotpatch_trampoline_halfwords (tree decl
,
5221 if (DECL_DECLARED_INLINE_P (decl
)
5222 || DECL_ARTIFICIAL (decl
)
5223 || MAIN_NAME_P (DECL_NAME (decl
)))
5225 /* - Explicitly inlined functions cannot be hotpatched.
5226 - Artificial functions need not be hotpatched.
5227 - Making the main function hotpatchable is useless. */
5230 attr
= lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl
));
5231 if (attr
|| s390_hotpatch_trampoline_halfwords
>= 0)
5233 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl
)))
5236 warning (OPT_Wattributes
, "function %qE with the %qs attribute"
5237 " is not hotpatchable", DECL_NAME (decl
), "always_inline");
5243 get_hotpatch_attribute (attr
) : s390_hotpatch_trampoline_halfwords
;
5250 /* Hook to determine if one function can safely inline another. */
5253 s390_can_inline_p (tree caller
, tree callee
)
5255 if (s390_function_num_hotpatch_trampoline_halfwords (callee
, false) >= 0)
5258 return default_target_can_inline_p (caller
, callee
);
5261 /* Write the extra assembler code needed to declare a function properly. */
5264 s390_asm_output_function_label (FILE *asm_out_file
, const char *fname
,
5267 int hotpatch_trampoline_halfwords
= -1;
5271 hotpatch_trampoline_halfwords
=
5272 s390_function_num_hotpatch_trampoline_halfwords (decl
, true);
5273 if (hotpatch_trampoline_halfwords
>= 0
5274 && decl_function_context (decl
) != NULL_TREE
)
5276 warning_at (DECL_SOURCE_LOCATION (decl
), OPT_mhotpatch
,
5277 "hotpatching is not compatible with nested functions");
5278 hotpatch_trampoline_halfwords
= -1;
5282 if (hotpatch_trampoline_halfwords
> 0)
5286 /* Add a trampoline code area before the function label and initialize it
5287 with two-byte nop instructions. This area can be overwritten with code
5288 that jumps to a patched version of the function. */
5289 for (i
= 0; i
< hotpatch_trampoline_halfwords
; i
++)
5290 asm_fprintf (asm_out_file
, "\tnopr\t%%r7\n");
5291 /* Note: The function label must be aligned so that (a) the bytes of the
5292 following nop do not cross a cacheline boundary, and (b) a jump address
5293 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5294 stored directly before the label without crossing a cacheline
5295 boundary. All this is necessary to make sure the trampoline code can
5296 be changed atomically. */
5299 ASM_OUTPUT_LABEL (asm_out_file
, fname
);
5301 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5302 atomically with a relative backwards jump to the trampoline area. */
5303 if (hotpatch_trampoline_halfwords
>= 0)
5304 asm_fprintf (asm_out_file
, "\tnop\t0\n");
5307 /* Output machine-dependent UNSPECs occurring in address constant X
5308 in assembler syntax to stdio stream FILE. Returns true if the
5309 constant X could be recognized, false otherwise. */
5312 s390_output_addr_const_extra (FILE *file
, rtx x
)
5314 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5315 switch (XINT (x
, 1))
5318 output_addr_const (file
, XVECEXP (x
, 0, 0));
5319 fprintf (file
, "@GOTENT");
5322 output_addr_const (file
, XVECEXP (x
, 0, 0));
5323 fprintf (file
, "@GOT");
5326 output_addr_const (file
, XVECEXP (x
, 0, 0));
5327 fprintf (file
, "@GOTOFF");
5330 output_addr_const (file
, XVECEXP (x
, 0, 0));
5331 fprintf (file
, "@PLT");
5334 output_addr_const (file
, XVECEXP (x
, 0, 0));
5335 fprintf (file
, "@PLTOFF");
5338 output_addr_const (file
, XVECEXP (x
, 0, 0));
5339 fprintf (file
, "@TLSGD");
5342 assemble_name (file
, get_some_local_dynamic_name ());
5343 fprintf (file
, "@TLSLDM");
5346 output_addr_const (file
, XVECEXP (x
, 0, 0));
5347 fprintf (file
, "@DTPOFF");
5350 output_addr_const (file
, XVECEXP (x
, 0, 0));
5351 fprintf (file
, "@NTPOFF");
5353 case UNSPEC_GOTNTPOFF
:
5354 output_addr_const (file
, XVECEXP (x
, 0, 0));
5355 fprintf (file
, "@GOTNTPOFF");
5357 case UNSPEC_INDNTPOFF
:
5358 output_addr_const (file
, XVECEXP (x
, 0, 0));
5359 fprintf (file
, "@INDNTPOFF");
5363 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5364 switch (XINT (x
, 1))
5366 case UNSPEC_POOL_OFFSET
:
5367 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5368 output_addr_const (file
, x
);
5374 /* Output address operand ADDR in assembler syntax to
5375 stdio stream FILE. */
5378 print_operand_address (FILE *file
, rtx addr
)
5380 struct s390_address ad
;
5382 if (s390_loadrelative_operand_p (addr
, NULL
, NULL
))
5386 output_operand_lossage ("symbolic memory references are "
5387 "only supported on z10 or later");
5390 output_addr_const (file
, addr
);
5394 if (!s390_decompose_address (addr
, &ad
)
5395 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5396 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5397 output_operand_lossage ("cannot decompose address");
5400 output_addr_const (file
, ad
.disp
);
5402 fprintf (file
, "0");
5404 if (ad
.base
&& ad
.indx
)
5405 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5406 reg_names
[REGNO (ad
.base
)]);
5408 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5411 /* Output operand X in assembler syntax to stdio stream FILE.
5412 CODE specified the format flag. The following format flags
5415 'C': print opcode suffix for branch condition.
5416 'D': print opcode suffix for inverse branch condition.
5417 'E': print opcode suffix for branch on index instruction.
5418 'G': print the size of the operand in bytes.
5419 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5420 'M': print the second word of a TImode operand.
5421 'N': print the second word of a DImode operand.
5422 'O': print only the displacement of a memory reference.
5423 'R': print only the base register of a memory reference.
5424 'S': print S-type memory reference (base+displacement).
5425 'Y': print shift count operand.
5427 'b': print integer X as if it's an unsigned byte.
5428 'c': print integer X as if it's an signed byte.
5429 'e': "end" of DImode contiguous bitmask X.
5430 'f': "end" of SImode contiguous bitmask X.
5431 'h': print integer X as if it's a signed halfword.
5432 'i': print the first nonzero HImode part of X.
5433 'j': print the first HImode part unequal to -1 of X.
5434 'k': print the first nonzero SImode part of X.
5435 'm': print the first SImode part unequal to -1 of X.
5436 'o': print integer X as if it's an unsigned 32bit word.
5437 's': "start" of DImode contiguous bitmask X.
5438 't': "start" of SImode contiguous bitmask X.
5439 'x': print integer X as if it's an unsigned halfword.
5443 print_operand (FILE *file
, rtx x
, int code
)
5450 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5454 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5458 if (GET_CODE (x
) == LE
)
5459 fprintf (file
, "l");
5460 else if (GET_CODE (x
) == GT
)
5461 fprintf (file
, "h");
5463 output_operand_lossage ("invalid comparison operator "
5464 "for 'E' output modifier");
5468 if (GET_CODE (x
) == SYMBOL_REF
)
5470 fprintf (file
, "%s", ":tls_load:");
5471 output_addr_const (file
, x
);
5473 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5475 fprintf (file
, "%s", ":tls_gdcall:");
5476 output_addr_const (file
, XVECEXP (x
, 0, 0));
5478 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5480 fprintf (file
, "%s", ":tls_ldcall:");
5481 const char *name
= get_some_local_dynamic_name ();
5483 assemble_name (file
, name
);
5486 output_operand_lossage ("invalid reference for 'J' output modifier");
5490 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5495 struct s390_address ad
;
5500 output_operand_lossage ("memory reference expected for "
5501 "'O' output modifier");
5505 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5508 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5511 output_operand_lossage ("invalid address for 'O' output modifier");
5516 output_addr_const (file
, ad
.disp
);
5518 fprintf (file
, "0");
5524 struct s390_address ad
;
5529 output_operand_lossage ("memory reference expected for "
5530 "'R' output modifier");
5534 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5537 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5540 output_operand_lossage ("invalid address for 'R' output modifier");
5545 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5547 fprintf (file
, "0");
5553 struct s390_address ad
;
5558 output_operand_lossage ("memory reference expected for "
5559 "'S' output modifier");
5562 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5565 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5568 output_operand_lossage ("invalid address for 'S' output modifier");
5573 output_addr_const (file
, ad
.disp
);
5575 fprintf (file
, "0");
5578 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5583 if (GET_CODE (x
) == REG
)
5584 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5585 else if (GET_CODE (x
) == MEM
)
5586 x
= change_address (x
, VOIDmode
,
5587 plus_constant (Pmode
, XEXP (x
, 0), 4));
5589 output_operand_lossage ("register or memory expression expected "
5590 "for 'N' output modifier");
5594 if (GET_CODE (x
) == REG
)
5595 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5596 else if (GET_CODE (x
) == MEM
)
5597 x
= change_address (x
, VOIDmode
,
5598 plus_constant (Pmode
, XEXP (x
, 0), 8));
5600 output_operand_lossage ("register or memory expression expected "
5601 "for 'M' output modifier");
5605 print_shift_count_operand (file
, x
);
5609 switch (GET_CODE (x
))
5612 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5616 output_address (XEXP (x
, 0));
5623 output_addr_const (file
, x
);
5636 ival
= ((ival
& 0xff) ^ 0x80) - 0x80;
5642 ival
= ((ival
& 0xffff) ^ 0x8000) - 0x8000;
5645 ival
= s390_extract_part (x
, HImode
, 0);
5648 ival
= s390_extract_part (x
, HImode
, -1);
5651 ival
= s390_extract_part (x
, SImode
, 0);
5654 ival
= s390_extract_part (x
, SImode
, -1);
5665 len
= (code
== 's' || code
== 'e' ? 64 : 32);
5666 ok
= s390_contiguous_bitmask_p (ival
, len
, &pos
, &len
);
5668 if (code
== 's' || code
== 't')
5669 ival
= 64 - pos
- len
;
5671 ival
= 64 - 1 - pos
;
5675 output_operand_lossage ("invalid constant for output modifier '%c'", code
);
5677 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
5681 gcc_assert (GET_MODE (x
) == VOIDmode
);
5683 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5684 else if (code
== 'x')
5685 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5686 else if (code
== 'h')
5687 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5688 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5692 output_operand_lossage ("invalid constant - try using "
5693 "an output modifier");
5695 output_operand_lossage ("invalid constant for output modifier '%c'",
5702 output_operand_lossage ("invalid expression - try using "
5703 "an output modifier");
5705 output_operand_lossage ("invalid expression for output "
5706 "modifier '%c'", code
);
5711 /* Target hook for assembling integer objects. We need to define it
5712 here to work a round a bug in some versions of GAS, which couldn't
5713 handle values smaller than INT_MIN when printed in decimal. */
5716 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5718 if (size
== 8 && aligned_p
5719 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5721 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5725 return default_assemble_integer (x
, size
, aligned_p
);
5728 /* Returns true if register REGNO is used for forming
5729 a memory address in expression X. */
5732 reg_used_in_mem_p (int regno
, rtx x
)
5734 enum rtx_code code
= GET_CODE (x
);
5740 if (refers_to_regno_p (regno
, regno
+1,
5744 else if (code
== SET
5745 && GET_CODE (SET_DEST (x
)) == PC
)
5747 if (refers_to_regno_p (regno
, regno
+1,
5752 fmt
= GET_RTX_FORMAT (code
);
5753 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5756 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5759 else if (fmt
[i
] == 'E')
5760 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5761 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5767 /* Returns true if expression DEP_RTX sets an address register
5768 used by instruction INSN to address memory. */
5771 addr_generation_dependency_p (rtx dep_rtx
, rtx_insn
*insn
)
5775 if (NONJUMP_INSN_P (dep_rtx
))
5776 dep_rtx
= PATTERN (dep_rtx
);
5778 if (GET_CODE (dep_rtx
) == SET
)
5780 target
= SET_DEST (dep_rtx
);
5781 if (GET_CODE (target
) == STRICT_LOW_PART
)
5782 target
= XEXP (target
, 0);
5783 while (GET_CODE (target
) == SUBREG
)
5784 target
= SUBREG_REG (target
);
5786 if (GET_CODE (target
) == REG
)
5788 int regno
= REGNO (target
);
5790 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5792 pat
= PATTERN (insn
);
5793 if (GET_CODE (pat
) == PARALLEL
)
5795 gcc_assert (XVECLEN (pat
, 0) == 2);
5796 pat
= XVECEXP (pat
, 0, 0);
5798 gcc_assert (GET_CODE (pat
) == SET
);
5799 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5801 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5802 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5808 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5811 s390_agen_dep_p (rtx_insn
*dep_insn
, rtx_insn
*insn
)
5813 rtx dep_rtx
= PATTERN (dep_insn
);
5816 if (GET_CODE (dep_rtx
) == SET
5817 && addr_generation_dependency_p (dep_rtx
, insn
))
5819 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5821 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5823 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5831 /* A C statement (sans semicolon) to update the integer scheduling priority
5832 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5833 reduce the priority to execute INSN later. Do not define this macro if
5834 you do not need to adjust the scheduling priorities of insns.
5836 A STD instruction should be scheduled earlier,
5837 in order to use the bypass. */
5839 s390_adjust_priority (rtx_insn
*insn
, int priority
)
5841 if (! INSN_P (insn
))
5844 if (s390_tune
!= PROCESSOR_2084_Z990
5845 && s390_tune
!= PROCESSOR_2094_Z9_109
5846 && s390_tune
!= PROCESSOR_2097_Z10
5847 && s390_tune
!= PROCESSOR_2817_Z196
5848 && s390_tune
!= PROCESSOR_2827_ZEC12
)
5851 switch (s390_safe_attr_type (insn
))
5855 priority
= priority
<< 3;
5859 priority
= priority
<< 1;
5868 /* The number of instructions that can be issued per cycle. */
5871 s390_issue_rate (void)
5875 case PROCESSOR_2084_Z990
:
5876 case PROCESSOR_2094_Z9_109
:
5877 case PROCESSOR_2817_Z196
:
5879 case PROCESSOR_2097_Z10
:
5880 case PROCESSOR_2827_ZEC12
:
5888 s390_first_cycle_multipass_dfa_lookahead (void)
5893 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5894 Fix up MEMs as required. */
5897 annotate_constant_pool_refs (rtx
*x
)
5902 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5903 || !CONSTANT_POOL_ADDRESS_P (*x
));
5905 /* Literal pool references can only occur inside a MEM ... */
5906 if (GET_CODE (*x
) == MEM
)
5908 rtx memref
= XEXP (*x
, 0);
5910 if (GET_CODE (memref
) == SYMBOL_REF
5911 && CONSTANT_POOL_ADDRESS_P (memref
))
5913 rtx base
= cfun
->machine
->base_reg
;
5914 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5917 *x
= replace_equiv_address (*x
, addr
);
5921 if (GET_CODE (memref
) == CONST
5922 && GET_CODE (XEXP (memref
, 0)) == PLUS
5923 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5924 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5925 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5927 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5928 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5929 rtx base
= cfun
->machine
->base_reg
;
5930 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5933 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
5938 /* ... or a load-address type pattern. */
5939 if (GET_CODE (*x
) == SET
)
5941 rtx addrref
= SET_SRC (*x
);
5943 if (GET_CODE (addrref
) == SYMBOL_REF
5944 && CONSTANT_POOL_ADDRESS_P (addrref
))
5946 rtx base
= cfun
->machine
->base_reg
;
5947 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5950 SET_SRC (*x
) = addr
;
5954 if (GET_CODE (addrref
) == CONST
5955 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5956 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5957 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5958 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5960 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5961 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5962 rtx base
= cfun
->machine
->base_reg
;
5963 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5966 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
5971 /* Annotate LTREL_BASE as well. */
5972 if (GET_CODE (*x
) == UNSPEC
5973 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5975 rtx base
= cfun
->machine
->base_reg
;
5976 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5981 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5982 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5986 annotate_constant_pool_refs (&XEXP (*x
, i
));
5988 else if (fmt
[i
] == 'E')
5990 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5991 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5996 /* Split all branches that exceed the maximum distance.
5997 Returns true if this created a new literal pool entry. */
6000 s390_split_branches (void)
6002 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
6003 int new_literal
= 0, ret
;
6008 /* We need correct insn addresses. */
6010 shorten_branches (get_insns ());
6012 /* Find all branches that exceed 64KB, and split them. */
6014 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6016 if (! JUMP_P (insn
) || tablejump_p (insn
, NULL
, NULL
))
6019 pat
= PATTERN (insn
);
6020 if (GET_CODE (pat
) == PARALLEL
)
6021 pat
= XVECEXP (pat
, 0, 0);
6022 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
6025 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
6027 label
= &SET_SRC (pat
);
6029 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
6031 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
6032 label
= &XEXP (SET_SRC (pat
), 1);
6033 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
6034 label
= &XEXP (SET_SRC (pat
), 2);
6041 if (get_attr_length (insn
) <= 4)
6044 /* We are going to use the return register as scratch register,
6045 make sure it will be saved/restored by the prologue/epilogue. */
6046 cfun_frame_layout
.save_return_addr_p
= 1;
6051 rtx mem
= force_const_mem (Pmode
, *label
);
6052 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, mem
), insn
);
6053 INSN_ADDRESSES_NEW (set_insn
, -1);
6054 annotate_constant_pool_refs (&PATTERN (set_insn
));
6061 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
6062 UNSPEC_LTREL_OFFSET
);
6063 target
= gen_rtx_CONST (Pmode
, target
);
6064 target
= force_const_mem (Pmode
, target
);
6065 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
6066 INSN_ADDRESSES_NEW (set_insn
, -1);
6067 annotate_constant_pool_refs (&PATTERN (set_insn
));
6069 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
6070 cfun
->machine
->base_reg
),
6072 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
6075 ret
= validate_change (insn
, label
, target
, 0);
6083 /* Find an annotated literal pool symbol referenced in RTX X,
6084 and store it at REF. Will abort if X contains references to
6085 more than one such pool symbol; multiple references to the same
6086 symbol are allowed, however.
6088 The rtx pointed to by REF must be initialized to NULL_RTX
6089 by the caller before calling this routine. */
6092 find_constant_pool_ref (rtx x
, rtx
*ref
)
6097 /* Ignore LTREL_BASE references. */
6098 if (GET_CODE (x
) == UNSPEC
6099 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6101 /* Likewise POOL_ENTRY insns. */
6102 if (GET_CODE (x
) == UNSPEC_VOLATILE
6103 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
6106 gcc_assert (GET_CODE (x
) != SYMBOL_REF
6107 || !CONSTANT_POOL_ADDRESS_P (x
));
6109 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
6111 rtx sym
= XVECEXP (x
, 0, 0);
6112 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
6113 && CONSTANT_POOL_ADDRESS_P (sym
));
6115 if (*ref
== NULL_RTX
)
6118 gcc_assert (*ref
== sym
);
6123 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6124 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6128 find_constant_pool_ref (XEXP (x
, i
), ref
);
6130 else if (fmt
[i
] == 'E')
6132 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6133 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
6138 /* Replace every reference to the annotated literal pool
6139 symbol REF in X by its base plus OFFSET. */
6142 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
6147 gcc_assert (*x
!= ref
);
6149 if (GET_CODE (*x
) == UNSPEC
6150 && XINT (*x
, 1) == UNSPEC_LTREF
6151 && XVECEXP (*x
, 0, 0) == ref
)
6153 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
6157 if (GET_CODE (*x
) == PLUS
6158 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
6159 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
6160 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
6161 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
6163 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
6164 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
6168 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6169 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6173 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
6175 else if (fmt
[i
] == 'E')
6177 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6178 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
6183 /* Check whether X contains an UNSPEC_LTREL_BASE.
6184 Return its constant pool symbol if found, NULL_RTX otherwise. */
6187 find_ltrel_base (rtx x
)
6192 if (GET_CODE (x
) == UNSPEC
6193 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6194 return XVECEXP (x
, 0, 0);
6196 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6197 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6201 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
6205 else if (fmt
[i
] == 'E')
6207 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6209 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
6219 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6222 replace_ltrel_base (rtx
*x
)
6227 if (GET_CODE (*x
) == UNSPEC
6228 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
6230 *x
= XVECEXP (*x
, 0, 1);
6234 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6235 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6239 replace_ltrel_base (&XEXP (*x
, i
));
6241 else if (fmt
[i
] == 'E')
6243 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6244 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
6250 /* We keep a list of constants which we have to add to internal
6251 constant tables in the middle of large functions. */
6253 #define NR_C_MODES 11
6254 machine_mode constant_modes
[NR_C_MODES
] =
6256 TFmode
, TImode
, TDmode
,
6257 DFmode
, DImode
, DDmode
,
6258 SFmode
, SImode
, SDmode
,
6265 struct constant
*next
;
6267 rtx_code_label
*label
;
6270 struct constant_pool
6272 struct constant_pool
*next
;
6273 rtx_insn
*first_insn
;
6274 rtx_insn
*pool_insn
;
6276 rtx_insn
*emit_pool_after
;
6278 struct constant
*constants
[NR_C_MODES
];
6279 struct constant
*execute
;
6280 rtx_code_label
*label
;
6284 /* Allocate new constant_pool structure. */
6286 static struct constant_pool
*
6287 s390_alloc_pool (void)
6289 struct constant_pool
*pool
;
6292 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6294 for (i
= 0; i
< NR_C_MODES
; i
++)
6295 pool
->constants
[i
] = NULL
;
6297 pool
->execute
= NULL
;
6298 pool
->label
= gen_label_rtx ();
6299 pool
->first_insn
= NULL
;
6300 pool
->pool_insn
= NULL
;
6301 pool
->insns
= BITMAP_ALLOC (NULL
);
6303 pool
->emit_pool_after
= NULL
;
6308 /* Create new constant pool covering instructions starting at INSN
6309 and chain it to the end of POOL_LIST. */
6311 static struct constant_pool
*
6312 s390_start_pool (struct constant_pool
**pool_list
, rtx_insn
*insn
)
6314 struct constant_pool
*pool
, **prev
;
6316 pool
= s390_alloc_pool ();
6317 pool
->first_insn
= insn
;
6319 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6326 /* End range of instructions covered by POOL at INSN and emit
6327 placeholder insn representing the pool. */
6330 s390_end_pool (struct constant_pool
*pool
, rtx_insn
*insn
)
6332 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6335 insn
= get_last_insn ();
6337 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6338 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6341 /* Add INSN to the list of insns covered by POOL. */
6344 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6346 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6349 /* Return pool out of POOL_LIST that covers INSN. */
6351 static struct constant_pool
*
6352 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6354 struct constant_pool
*pool
;
6356 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6357 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6363 /* Add constant VAL of mode MODE to the constant pool POOL. */
6366 s390_add_constant (struct constant_pool
*pool
, rtx val
, machine_mode mode
)
6371 for (i
= 0; i
< NR_C_MODES
; i
++)
6372 if (constant_modes
[i
] == mode
)
6374 gcc_assert (i
!= NR_C_MODES
);
6376 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6377 if (rtx_equal_p (val
, c
->value
))
6382 c
= (struct constant
*) xmalloc (sizeof *c
);
6384 c
->label
= gen_label_rtx ();
6385 c
->next
= pool
->constants
[i
];
6386 pool
->constants
[i
] = c
;
6387 pool
->size
+= GET_MODE_SIZE (mode
);
6391 /* Return an rtx that represents the offset of X from the start of
6395 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6399 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6400 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6401 UNSPEC_POOL_OFFSET
);
6402 return gen_rtx_CONST (GET_MODE (x
), x
);
6405 /* Find constant VAL of mode MODE in the constant pool POOL.
6406 Return an RTX describing the distance from the start of
6407 the pool to the location of the new constant. */
6410 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6416 for (i
= 0; i
< NR_C_MODES
; i
++)
6417 if (constant_modes
[i
] == mode
)
6419 gcc_assert (i
!= NR_C_MODES
);
6421 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6422 if (rtx_equal_p (val
, c
->value
))
6427 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6430 /* Check whether INSN is an execute. Return the label_ref to its
6431 execute target template if so, NULL_RTX otherwise. */
6434 s390_execute_label (rtx insn
)
6436 if (NONJUMP_INSN_P (insn
)
6437 && GET_CODE (PATTERN (insn
)) == PARALLEL
6438 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6439 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6440 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6445 /* Add execute target for INSN to the constant pool POOL. */
6448 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6452 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6453 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6458 c
= (struct constant
*) xmalloc (sizeof *c
);
6460 c
->label
= gen_label_rtx ();
6461 c
->next
= pool
->execute
;
6467 /* Find execute target for INSN in the constant pool POOL.
6468 Return an RTX describing the distance from the start of
6469 the pool to the location of the execute target. */
6472 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6476 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6477 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6482 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6485 /* For an execute INSN, extract the execute target template. */
6488 s390_execute_target (rtx insn
)
6490 rtx pattern
= PATTERN (insn
);
6491 gcc_assert (s390_execute_label (insn
));
6493 if (XVECLEN (pattern
, 0) == 2)
6495 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6499 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6502 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6503 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6505 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6511 /* Indicate that INSN cannot be duplicated. This is the case for
6512 execute insns that carry a unique label. */
6515 s390_cannot_copy_insn_p (rtx_insn
*insn
)
6517 rtx label
= s390_execute_label (insn
);
6518 return label
&& label
!= const0_rtx
;
6521 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6522 do not emit the pool base label. */
6525 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6528 rtx_insn
*insn
= pool
->pool_insn
;
6531 /* Switch to rodata section. */
6532 if (TARGET_CPU_ZARCH
)
6534 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6535 INSN_ADDRESSES_NEW (insn
, -1);
6538 /* Ensure minimum pool alignment. */
6539 if (TARGET_CPU_ZARCH
)
6540 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6542 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6543 INSN_ADDRESSES_NEW (insn
, -1);
6545 /* Emit pool base label. */
6548 insn
= emit_label_after (pool
->label
, insn
);
6549 INSN_ADDRESSES_NEW (insn
, -1);
6552 /* Dump constants in descending alignment requirement order,
6553 ensuring proper alignment for every constant. */
6554 for (i
= 0; i
< NR_C_MODES
; i
++)
6555 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6557 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6558 rtx value
= copy_rtx (c
->value
);
6559 if (GET_CODE (value
) == CONST
6560 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6561 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6562 && XVECLEN (XEXP (value
, 0), 0) == 1)
6563 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6565 insn
= emit_label_after (c
->label
, insn
);
6566 INSN_ADDRESSES_NEW (insn
, -1);
6568 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6569 gen_rtvec (1, value
),
6570 UNSPECV_POOL_ENTRY
);
6571 insn
= emit_insn_after (value
, insn
);
6572 INSN_ADDRESSES_NEW (insn
, -1);
6575 /* Ensure minimum alignment for instructions. */
6576 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6577 INSN_ADDRESSES_NEW (insn
, -1);
6579 /* Output in-pool execute template insns. */
6580 for (c
= pool
->execute
; c
; c
= c
->next
)
6582 insn
= emit_label_after (c
->label
, insn
);
6583 INSN_ADDRESSES_NEW (insn
, -1);
6585 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6586 INSN_ADDRESSES_NEW (insn
, -1);
6589 /* Switch back to previous section. */
6590 if (TARGET_CPU_ZARCH
)
6592 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6593 INSN_ADDRESSES_NEW (insn
, -1);
6596 insn
= emit_barrier_after (insn
);
6597 INSN_ADDRESSES_NEW (insn
, -1);
6599 /* Remove placeholder insn. */
6600 remove_insn (pool
->pool_insn
);
6603 /* Free all memory used by POOL. */
6606 s390_free_pool (struct constant_pool
*pool
)
6608 struct constant
*c
, *next
;
6611 for (i
= 0; i
< NR_C_MODES
; i
++)
6612 for (c
= pool
->constants
[i
]; c
; c
= next
)
6618 for (c
= pool
->execute
; c
; c
= next
)
6624 BITMAP_FREE (pool
->insns
);
6629 /* Collect main literal pool. Return NULL on overflow. */
6631 static struct constant_pool
*
6632 s390_mainpool_start (void)
6634 struct constant_pool
*pool
;
6637 pool
= s390_alloc_pool ();
6639 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6641 if (NONJUMP_INSN_P (insn
)
6642 && GET_CODE (PATTERN (insn
)) == SET
6643 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6644 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6646 /* There might be two main_pool instructions if base_reg
6647 is call-clobbered; one for shrink-wrapped code and one
6648 for the rest. We want to keep the first. */
6649 if (pool
->pool_insn
)
6651 insn
= PREV_INSN (insn
);
6652 delete_insn (NEXT_INSN (insn
));
6655 pool
->pool_insn
= insn
;
6658 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6660 s390_add_execute (pool
, insn
);
6662 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
6664 rtx pool_ref
= NULL_RTX
;
6665 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6668 rtx constant
= get_pool_constant (pool_ref
);
6669 machine_mode mode
= get_pool_mode (pool_ref
);
6670 s390_add_constant (pool
, constant
, mode
);
6674 /* If hot/cold partitioning is enabled we have to make sure that
6675 the literal pool is emitted in the same section where the
6676 initialization of the literal pool base pointer takes place.
6677 emit_pool_after is only used in the non-overflow case on non
6678 Z cpus where we can emit the literal pool at the end of the
6679 function body within the text section. */
6681 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6682 && !pool
->emit_pool_after
)
6683 pool
->emit_pool_after
= PREV_INSN (insn
);
6686 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6688 if (pool
->size
>= 4096)
6690 /* We're going to chunkify the pool, so remove the main
6691 pool placeholder insn. */
6692 remove_insn (pool
->pool_insn
);
6694 s390_free_pool (pool
);
6698 /* If the functions ends with the section where the literal pool
6699 should be emitted set the marker to its end. */
6700 if (pool
&& !pool
->emit_pool_after
)
6701 pool
->emit_pool_after
= get_last_insn ();
6706 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6707 Modify the current function to output the pool constants as well as
6708 the pool register setup instruction. */
6711 s390_mainpool_finish (struct constant_pool
*pool
)
6713 rtx base_reg
= cfun
->machine
->base_reg
;
6715 /* If the pool is empty, we're done. */
6716 if (pool
->size
== 0)
6718 /* We don't actually need a base register after all. */
6719 cfun
->machine
->base_reg
= NULL_RTX
;
6721 if (pool
->pool_insn
)
6722 remove_insn (pool
->pool_insn
);
6723 s390_free_pool (pool
);
6727 /* We need correct insn addresses. */
6728 shorten_branches (get_insns ());
6730 /* On zSeries, we use a LARL to load the pool register. The pool is
6731 located in the .rodata section, so we emit it after the function. */
6732 if (TARGET_CPU_ZARCH
)
6734 rtx set
= gen_main_base_64 (base_reg
, pool
->label
);
6735 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
6736 INSN_ADDRESSES_NEW (insn
, -1);
6737 remove_insn (pool
->pool_insn
);
6739 insn
= get_last_insn ();
6740 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6741 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6743 s390_dump_pool (pool
, 0);
6746 /* On S/390, if the total size of the function's code plus literal pool
6747 does not exceed 4096 bytes, we use BASR to set up a function base
6748 pointer, and emit the literal pool at the end of the function. */
6749 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6750 + pool
->size
+ 8 /* alignment slop */ < 4096)
6752 rtx set
= gen_main_base_31_small (base_reg
, pool
->label
);
6753 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
6754 INSN_ADDRESSES_NEW (insn
, -1);
6755 remove_insn (pool
->pool_insn
);
6757 insn
= emit_label_after (pool
->label
, insn
);
6758 INSN_ADDRESSES_NEW (insn
, -1);
6760 /* emit_pool_after will be set by s390_mainpool_start to the
6761 last insn of the section where the literal pool should be
6763 insn
= pool
->emit_pool_after
;
6765 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6766 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6768 s390_dump_pool (pool
, 1);
6771 /* Otherwise, we emit an inline literal pool and use BASR to branch
6772 over it, setting up the pool register at the same time. */
6775 rtx_code_label
*pool_end
= gen_label_rtx ();
6777 rtx pat
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6778 rtx_insn
*insn
= emit_jump_insn_after (pat
, pool
->pool_insn
);
6779 JUMP_LABEL (insn
) = pool_end
;
6780 INSN_ADDRESSES_NEW (insn
, -1);
6781 remove_insn (pool
->pool_insn
);
6783 insn
= emit_label_after (pool
->label
, insn
);
6784 INSN_ADDRESSES_NEW (insn
, -1);
6786 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6787 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6789 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6790 INSN_ADDRESSES_NEW (insn
, -1);
6792 s390_dump_pool (pool
, 1);
6796 /* Replace all literal pool references. */
6798 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6801 replace_ltrel_base (&PATTERN (insn
));
6803 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
6805 rtx addr
, pool_ref
= NULL_RTX
;
6806 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6809 if (s390_execute_label (insn
))
6810 addr
= s390_find_execute (pool
, insn
);
6812 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6813 get_pool_mode (pool_ref
));
6815 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6816 INSN_CODE (insn
) = -1;
6822 /* Free the pool. */
6823 s390_free_pool (pool
);
6826 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6827 We have decided we cannot use this pool, so revert all changes
6828 to the current function that were done by s390_mainpool_start. */
6830 s390_mainpool_cancel (struct constant_pool
*pool
)
6832 /* We didn't actually change the instruction stream, so simply
6833 free the pool memory. */
6834 s390_free_pool (pool
);
6838 /* Chunkify the literal pool. */
6840 #define S390_POOL_CHUNK_MIN 0xc00
6841 #define S390_POOL_CHUNK_MAX 0xe00
6843 static struct constant_pool
*
6844 s390_chunkify_start (void)
6846 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6849 rtx pending_ltrel
= NULL_RTX
;
6852 rtx (*gen_reload_base
) (rtx
, rtx
) =
6853 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6856 /* We need correct insn addresses. */
6858 shorten_branches (get_insns ());
6860 /* Scan all insns and move literals to pool chunks. */
6862 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6864 bool section_switch_p
= false;
6866 /* Check for pending LTREL_BASE. */
6869 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6872 gcc_assert (ltrel_base
== pending_ltrel
);
6873 pending_ltrel
= NULL_RTX
;
6877 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6880 curr_pool
= s390_start_pool (&pool_list
, insn
);
6882 s390_add_execute (curr_pool
, insn
);
6883 s390_add_pool_insn (curr_pool
, insn
);
6885 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
6887 rtx pool_ref
= NULL_RTX
;
6888 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6891 rtx constant
= get_pool_constant (pool_ref
);
6892 machine_mode mode
= get_pool_mode (pool_ref
);
6895 curr_pool
= s390_start_pool (&pool_list
, insn
);
6897 s390_add_constant (curr_pool
, constant
, mode
);
6898 s390_add_pool_insn (curr_pool
, insn
);
6900 /* Don't split the pool chunk between a LTREL_OFFSET load
6901 and the corresponding LTREL_BASE. */
6902 if (GET_CODE (constant
) == CONST
6903 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6904 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6906 gcc_assert (!pending_ltrel
);
6907 pending_ltrel
= pool_ref
;
6912 if (JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
) || LABEL_P (insn
))
6915 s390_add_pool_insn (curr_pool
, insn
);
6916 /* An LTREL_BASE must follow within the same basic block. */
6917 gcc_assert (!pending_ltrel
);
6921 switch (NOTE_KIND (insn
))
6923 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
6924 section_switch_p
= true;
6926 case NOTE_INSN_VAR_LOCATION
:
6927 case NOTE_INSN_CALL_ARG_LOCATION
:
6934 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6935 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6938 if (TARGET_CPU_ZARCH
)
6940 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6943 s390_end_pool (curr_pool
, NULL
);
6948 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6949 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6952 /* We will later have to insert base register reload insns.
6953 Those will have an effect on code size, which we need to
6954 consider here. This calculation makes rather pessimistic
6955 worst-case assumptions. */
6959 if (chunk_size
< S390_POOL_CHUNK_MIN
6960 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6961 && !section_switch_p
)
6964 /* Pool chunks can only be inserted after BARRIERs ... */
6965 if (BARRIER_P (insn
))
6967 s390_end_pool (curr_pool
, insn
);
6972 /* ... so if we don't find one in time, create one. */
6973 else if (chunk_size
> S390_POOL_CHUNK_MAX
6974 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6975 || section_switch_p
)
6977 rtx_insn
*label
, *jump
, *barrier
, *next
, *prev
;
6979 if (!section_switch_p
)
6981 /* We can insert the barrier only after a 'real' insn. */
6982 if (! NONJUMP_INSN_P (insn
) && ! CALL_P (insn
))
6984 if (get_attr_length (insn
) == 0)
6986 /* Don't separate LTREL_BASE from the corresponding
6987 LTREL_OFFSET load. */
6994 next
= NEXT_INSN (insn
);
6998 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
6999 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
7003 gcc_assert (!pending_ltrel
);
7005 /* The old pool has to end before the section switch
7006 note in order to make it part of the current
7008 insn
= PREV_INSN (insn
);
7011 label
= gen_label_rtx ();
7013 if (prev
&& NOTE_P (prev
))
7014 prev
= prev_nonnote_insn (prev
);
7016 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
7017 INSN_LOCATION (prev
));
7019 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
7020 barrier
= emit_barrier_after (jump
);
7021 insn
= emit_label_after (label
, barrier
);
7022 JUMP_LABEL (jump
) = label
;
7023 LABEL_NUSES (label
) = 1;
7025 INSN_ADDRESSES_NEW (jump
, -1);
7026 INSN_ADDRESSES_NEW (barrier
, -1);
7027 INSN_ADDRESSES_NEW (insn
, -1);
7029 s390_end_pool (curr_pool
, barrier
);
7037 s390_end_pool (curr_pool
, NULL
);
7038 gcc_assert (!pending_ltrel
);
7040 /* Find all labels that are branched into
7041 from an insn belonging to a different chunk. */
7043 far_labels
= BITMAP_ALLOC (NULL
);
7045 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7047 rtx_jump_table_data
*table
;
7049 /* Labels marked with LABEL_PRESERVE_P can be target
7050 of non-local jumps, so we have to mark them.
7051 The same holds for named labels.
7053 Don't do that, however, if it is the label before
7057 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
7059 rtx_insn
*vec_insn
= NEXT_INSN (insn
);
7060 if (! vec_insn
|| ! JUMP_TABLE_DATA_P (vec_insn
))
7061 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
7063 /* Check potential targets in a table jump (casesi_jump). */
7064 else if (tablejump_p (insn
, NULL
, &table
))
7066 rtx vec_pat
= PATTERN (table
);
7067 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
7069 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
7071 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
7073 if (s390_find_pool (pool_list
, label
)
7074 != s390_find_pool (pool_list
, insn
))
7075 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
7078 /* If we have a direct jump (conditional or unconditional),
7079 check all potential targets. */
7080 else if (JUMP_P (insn
))
7082 rtx pat
= PATTERN (insn
);
7084 if (GET_CODE (pat
) == PARALLEL
)
7085 pat
= XVECEXP (pat
, 0, 0);
7087 if (GET_CODE (pat
) == SET
)
7089 rtx label
= JUMP_LABEL (insn
);
7090 if (label
&& !ANY_RETURN_P (label
))
7092 if (s390_find_pool (pool_list
, label
)
7093 != s390_find_pool (pool_list
, insn
))
7094 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
7100 /* Insert base register reload insns before every pool. */
7102 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7104 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
7106 rtx_insn
*insn
= curr_pool
->first_insn
;
7107 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
7110 /* Insert base register reload insns at every far label. */
7112 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7114 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
7116 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
7119 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
7121 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
7126 BITMAP_FREE (far_labels
);
7129 /* Recompute insn addresses. */
7131 init_insn_lengths ();
7132 shorten_branches (get_insns ());
7137 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7138 After we have decided to use this list, finish implementing
7139 all changes to the current function as required. */
7142 s390_chunkify_finish (struct constant_pool
*pool_list
)
7144 struct constant_pool
*curr_pool
= NULL
;
7148 /* Replace all literal pool references. */
7150 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7153 replace_ltrel_base (&PATTERN (insn
));
7155 curr_pool
= s390_find_pool (pool_list
, insn
);
7159 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
7161 rtx addr
, pool_ref
= NULL_RTX
;
7162 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
7165 if (s390_execute_label (insn
))
7166 addr
= s390_find_execute (curr_pool
, insn
);
7168 addr
= s390_find_constant (curr_pool
,
7169 get_pool_constant (pool_ref
),
7170 get_pool_mode (pool_ref
));
7172 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
7173 INSN_CODE (insn
) = -1;
7178 /* Dump out all literal pools. */
7180 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7181 s390_dump_pool (curr_pool
, 0);
7183 /* Free pool list. */
7187 struct constant_pool
*next
= pool_list
->next
;
7188 s390_free_pool (pool_list
);
7193 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7194 We have decided we cannot use this list, so revert all changes
7195 to the current function that were done by s390_chunkify_start. */
7198 s390_chunkify_cancel (struct constant_pool
*pool_list
)
7200 struct constant_pool
*curr_pool
= NULL
;
7203 /* Remove all pool placeholder insns. */
7205 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7207 /* Did we insert an extra barrier? Remove it. */
7208 rtx_insn
*barrier
= PREV_INSN (curr_pool
->pool_insn
);
7209 rtx_insn
*jump
= barrier
? PREV_INSN (barrier
) : NULL
;
7210 rtx_insn
*label
= NEXT_INSN (curr_pool
->pool_insn
);
7212 if (jump
&& JUMP_P (jump
)
7213 && barrier
&& BARRIER_P (barrier
)
7214 && label
&& LABEL_P (label
)
7215 && GET_CODE (PATTERN (jump
)) == SET
7216 && SET_DEST (PATTERN (jump
)) == pc_rtx
7217 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
7218 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
7221 remove_insn (barrier
);
7222 remove_insn (label
);
7225 remove_insn (curr_pool
->pool_insn
);
7228 /* Remove all base register reload insns. */
7230 for (insn
= get_insns (); insn
; )
7232 rtx_insn
*next_insn
= NEXT_INSN (insn
);
7234 if (NONJUMP_INSN_P (insn
)
7235 && GET_CODE (PATTERN (insn
)) == SET
7236 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
7237 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
7243 /* Free pool list. */
7247 struct constant_pool
*next
= pool_list
->next
;
7248 s390_free_pool (pool_list
);
7253 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7256 s390_output_pool_entry (rtx exp
, machine_mode mode
, unsigned int align
)
7260 switch (GET_MODE_CLASS (mode
))
7263 case MODE_DECIMAL_FLOAT
:
7264 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
7266 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
7267 assemble_real (r
, mode
, align
);
7271 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
7272 mark_symbol_refs_as_used (exp
);
7281 /* Return an RTL expression representing the value of the return address
7282 for the frame COUNT steps up from the current frame. FRAME is the
7283 frame pointer of that frame. */
7286 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
7291 /* Without backchain, we fail for all but the current frame. */
7293 if (!TARGET_BACKCHAIN
&& count
> 0)
7296 /* For the current frame, we need to make sure the initial
7297 value of RETURN_REGNUM is actually saved. */
7301 /* On non-z architectures branch splitting could overwrite r14. */
7302 if (TARGET_CPU_ZARCH
)
7303 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7306 cfun_frame_layout
.save_return_addr_p
= true;
7307 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7311 if (TARGET_PACKED_STACK
)
7312 offset
= -2 * UNITS_PER_LONG
;
7314 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7316 addr
= plus_constant (Pmode
, frame
, offset
);
7317 addr
= memory_address (Pmode
, addr
);
7318 return gen_rtx_MEM (Pmode
, addr
);
7321 /* Return an RTL expression representing the back chain stored in
7322 the current stack frame. */
7325 s390_back_chain_rtx (void)
7329 gcc_assert (TARGET_BACKCHAIN
);
7331 if (TARGET_PACKED_STACK
)
7332 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
7333 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7335 chain
= stack_pointer_rtx
;
7337 chain
= gen_rtx_MEM (Pmode
, chain
);
7341 /* Find first call clobbered register unused in a function.
7342 This could be used as base register in a leaf function
7343 or for holding the return address before epilogue. */
7346 find_unused_clobbered_reg (void)
7349 for (i
= 0; i
< 6; i
++)
7350 if (!df_regs_ever_live_p (i
))
7356 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7357 clobbered hard regs in SETREG. */
7360 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7362 char *regs_ever_clobbered
= (char *)data
;
7363 unsigned int i
, regno
;
7364 machine_mode mode
= GET_MODE (setreg
);
7366 if (GET_CODE (setreg
) == SUBREG
)
7368 rtx inner
= SUBREG_REG (setreg
);
7369 if (!GENERAL_REG_P (inner
) && !FP_REG_P (inner
))
7371 regno
= subreg_regno (setreg
);
7373 else if (GENERAL_REG_P (setreg
) || FP_REG_P (setreg
))
7374 regno
= REGNO (setreg
);
7379 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7381 regs_ever_clobbered
[i
] = 1;
7384 /* Walks through all basic blocks of the current function looking
7385 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7386 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7387 each of those regs. */
7390 s390_regs_ever_clobbered (char regs_ever_clobbered
[])
7396 memset (regs_ever_clobbered
, 0, 32);
7398 /* For non-leaf functions we have to consider all call clobbered regs to be
7402 for (i
= 0; i
< 32; i
++)
7403 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7406 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7407 this work is done by liveness analysis (mark_regs_live_at_end).
7408 Special care is needed for functions containing landing pads. Landing pads
7409 may use the eh registers, but the code which sets these registers is not
7410 contained in that function. Hence s390_regs_ever_clobbered is not able to
7411 deal with this automatically. */
7412 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7413 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7414 if (crtl
->calls_eh_return
7415 || (cfun
->machine
->has_landing_pad_p
7416 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7417 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7419 /* For nonlocal gotos all call-saved registers have to be saved.
7420 This flag is also set for the unwinding code in libgcc.
7421 See expand_builtin_unwind_init. For regs_ever_live this is done by
7423 if (crtl
->saves_all_registers
)
7424 for (i
= 0; i
< 32; i
++)
7425 if (!call_really_used_regs
[i
])
7426 regs_ever_clobbered
[i
] = 1;
7428 FOR_EACH_BB_FN (cur_bb
, cfun
)
7430 FOR_BB_INSNS (cur_bb
, cur_insn
)
7434 if (!INSN_P (cur_insn
))
7437 pat
= PATTERN (cur_insn
);
7439 /* Ignore GPR restore insns. */
7440 if (epilogue_completed
&& RTX_FRAME_RELATED_P (cur_insn
))
7442 if (GET_CODE (pat
) == SET
7443 && GENERAL_REG_P (SET_DEST (pat
)))
7446 if (GET_MODE (SET_SRC (pat
)) == DImode
7447 && FP_REG_P (SET_SRC (pat
)))
7451 if (GET_CODE (SET_SRC (pat
)) == MEM
)
7456 if (GET_CODE (pat
) == PARALLEL
7457 && load_multiple_operation (pat
, VOIDmode
))
7462 s390_reg_clobbered_rtx
,
7463 regs_ever_clobbered
);
7468 /* Determine the frame area which actually has to be accessed
7469 in the function epilogue. The values are stored at the
7470 given pointers AREA_BOTTOM (address of the lowest used stack
7471 address) and AREA_TOP (address of the first item which does
7472 not belong to the stack frame). */
7475 s390_frame_area (int *area_bottom
, int *area_top
)
7482 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7484 b
= (cfun_frame_layout
.gprs_offset
7485 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7486 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7487 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7490 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7492 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7493 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7494 + cfun_frame_layout
.high_fprs
* 8));
7499 if (cfun_fpr_save_p (FPR4_REGNUM
))
7501 b
= MIN (b
, cfun_frame_layout
.f4_offset
);
7502 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 8);
7504 if (cfun_fpr_save_p (FPR6_REGNUM
))
7506 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ 8);
7507 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 16);
7513 /* Update gpr_save_slots in the frame layout trying to make use of
7514 FPRs as GPR save slots.
7515 This is a helper routine of s390_register_info. */
7518 s390_register_info_gprtofpr ()
7520 int save_reg_slot
= FPR0_REGNUM
;
7523 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
7526 for (i
= 15; i
>= 6; i
--)
7528 if (cfun_gpr_save_slot (i
) == 0)
7531 /* Advance to the next FP register which can be used as a
7533 while ((!call_really_used_regs
[save_reg_slot
]
7534 || df_regs_ever_live_p (save_reg_slot
)
7535 || cfun_fpr_save_p (save_reg_slot
))
7536 && FP_REGNO_P (save_reg_slot
))
7538 if (!FP_REGNO_P (save_reg_slot
))
7540 /* We only want to use ldgr/lgdr if we can get rid of
7541 stm/lm entirely. So undo the gpr slot allocation in
7542 case we ran out of FPR save slots. */
7543 for (j
= 6; j
<= 15; j
++)
7544 if (FP_REGNO_P (cfun_gpr_save_slot (j
)))
7545 cfun_gpr_save_slot (j
) = -1;
7548 cfun_gpr_save_slot (i
) = save_reg_slot
++;
7552 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7554 This is a helper routine for s390_register_info. */
7557 s390_register_info_stdarg_fpr ()
7563 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7564 f0-f4 for 64 bit. */
7566 || !TARGET_HARD_FLOAT
7567 || !cfun
->va_list_fpr_size
7568 || crtl
->args
.info
.fprs
>= FP_ARG_NUM_REG
)
7571 min_fpr
= crtl
->args
.info
.fprs
;
7572 max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7573 if (max_fpr
> FP_ARG_NUM_REG
)
7574 max_fpr
= FP_ARG_NUM_REG
;
7576 for (i
= min_fpr
; i
< max_fpr
; i
++)
7577 cfun_set_fpr_save (i
+ FPR0_REGNUM
);
7580 /* Reserve the GPR save slots for GPRs which need to be saved due to
7582 This is a helper routine for s390_register_info. */
7585 s390_register_info_stdarg_gpr ()
7592 || !cfun
->va_list_gpr_size
7593 || crtl
->args
.info
.gprs
>= GP_ARG_NUM_REG
)
7596 min_gpr
= crtl
->args
.info
.gprs
;
7597 max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7598 if (max_gpr
> GP_ARG_NUM_REG
)
7599 max_gpr
= GP_ARG_NUM_REG
;
7601 for (i
= min_gpr
; i
< max_gpr
; i
++)
7602 cfun_gpr_save_slot (2 + i
) = -1;
7605 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
7606 for registers which need to be saved in function prologue.
7607 This function can be used until the insns emitted for save/restore
7608 of the regs are visible in the RTL stream. */
7611 s390_register_info ()
7614 char clobbered_regs
[32];
7616 gcc_assert (!epilogue_completed
);
7618 if (reload_completed
)
7619 /* After reload we rely on our own routine to determine which
7620 registers need saving. */
7621 s390_regs_ever_clobbered (clobbered_regs
);
7623 /* During reload we use regs_ever_live as a base since reload
7624 does changes in there which we otherwise would not be aware
7626 for (i
= 0; i
< 32; i
++)
7627 clobbered_regs
[i
] = df_regs_ever_live_p (i
);
7629 for (i
= 0; i
< 32; i
++)
7630 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
7632 /* Mark the call-saved FPRs which need to be saved.
7633 This needs to be done before checking the special GPRs since the
7634 stack pointer usage depends on whether high FPRs have to be saved
7636 cfun_frame_layout
.fpr_bitmap
= 0;
7637 cfun_frame_layout
.high_fprs
= 0;
7638 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
7639 if (clobbered_regs
[i
] && !call_really_used_regs
[i
])
7641 cfun_set_fpr_save (i
);
7642 if (i
>= FPR8_REGNUM
)
7643 cfun_frame_layout
.high_fprs
++;
7647 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7648 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7650 clobbered_regs
[BASE_REGNUM
]
7651 |= (cfun
->machine
->base_reg
7652 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7654 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
]
7655 |= !!frame_pointer_needed
;
7657 /* On pre z900 machines this might take until machine dependent
7659 save_return_addr_p will only be set on non-zarch machines so
7660 there is no risk that r14 goes into an FPR instead of a stack
7662 clobbered_regs
[RETURN_REGNUM
]
7664 || TARGET_TPF_PROFILING
7665 || cfun
->machine
->split_branches_pending_p
7666 || cfun_frame_layout
.save_return_addr_p
7667 || crtl
->calls_eh_return
);
7669 clobbered_regs
[STACK_POINTER_REGNUM
]
7671 || TARGET_TPF_PROFILING
7672 || cfun_save_high_fprs_p
7673 || get_frame_size () > 0
7674 || (reload_completed
&& cfun_frame_layout
.frame_size
> 0)
7675 || cfun
->calls_alloca
);
7677 memset (cfun_frame_layout
.gpr_save_slots
, 0, 16);
7679 for (i
= 6; i
< 16; i
++)
7680 if (clobbered_regs
[i
])
7681 cfun_gpr_save_slot (i
) = -1;
7683 s390_register_info_stdarg_fpr ();
7684 s390_register_info_gprtofpr ();
7686 /* First find the range of GPRs to be restored. Vararg regs don't
7687 need to be restored so we do it before assigning slots to the
7689 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7690 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7691 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
7692 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
7694 /* stdarg functions might need to save GPRs 2 to 6. This might
7695 override the GPR->FPR save decision made above for r6 since
7696 vararg regs must go to the stack. */
7697 s390_register_info_stdarg_gpr ();
7699 /* Now the range of GPRs which need saving. */
7700 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7701 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7702 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
7703 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
7706 /* This function is called by s390_optimize_prologue in order to get
7707 rid of unnecessary GPR save/restore instructions. The register info
7708 for the GPRs is re-computed and the ranges are re-calculated. */
7711 s390_optimize_register_info ()
7713 char clobbered_regs
[32];
7716 gcc_assert (epilogue_completed
);
7717 gcc_assert (!cfun
->machine
->split_branches_pending_p
);
7719 s390_regs_ever_clobbered (clobbered_regs
);
7721 for (i
= 0; i
< 32; i
++)
7722 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
7724 /* There is still special treatment needed for cases invisible to
7725 s390_regs_ever_clobbered. */
7726 clobbered_regs
[RETURN_REGNUM
]
7727 |= (TARGET_TPF_PROFILING
7728 /* When expanding builtin_return_addr in ESA mode we do not
7729 know whether r14 will later be needed as scratch reg when
7730 doing branch splitting. So the builtin always accesses the
7731 r14 save slot and we need to stick to the save/restore
7732 decision for r14 even if it turns out that it didn't get
7734 || cfun_frame_layout
.save_return_addr_p
7735 || crtl
->calls_eh_return
);
7737 memset (cfun_frame_layout
.gpr_save_slots
, 0, 6);
7739 for (i
= 6; i
< 16; i
++)
7740 if (!clobbered_regs
[i
])
7741 cfun_gpr_save_slot (i
) = 0;
7743 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7744 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7745 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
7746 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
7748 s390_register_info_stdarg_gpr ();
7750 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7751 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7752 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
7753 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
7756 /* Fill cfun->machine with info about frame of current function. */
7759 s390_frame_info (void)
7761 HOST_WIDE_INT lowest_offset
;
7763 cfun_frame_layout
.first_save_gpr_slot
= cfun_frame_layout
.first_save_gpr
;
7764 cfun_frame_layout
.last_save_gpr_slot
= cfun_frame_layout
.last_save_gpr
;
7766 /* The va_arg builtin uses a constant distance of 16 *
7767 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7768 pointer. So even if we are going to save the stack pointer in an
7769 FPR we need the stack space in order to keep the offsets
7771 if (cfun
->stdarg
&& cfun_save_arg_fprs_p
)
7773 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
7775 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
7776 cfun_frame_layout
.first_save_gpr_slot
= STACK_POINTER_REGNUM
;
7779 cfun_frame_layout
.frame_size
= get_frame_size ();
7780 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7781 fatal_error ("total size of local variables exceeds architecture limit");
7783 if (!TARGET_PACKED_STACK
)
7785 /* Fixed stack layout. */
7786 cfun_frame_layout
.backchain_offset
= 0;
7787 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7788 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7789 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7790 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7793 else if (TARGET_BACKCHAIN
)
7795 /* Kernel stack layout - packed stack, backchain, no float */
7796 gcc_assert (TARGET_SOFT_FLOAT
);
7797 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7800 /* The distance between the backchain and the return address
7801 save slot must not change. So we always need a slot for the
7802 stack pointer which resides in between. */
7803 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
7805 cfun_frame_layout
.gprs_offset
7806 = cfun_frame_layout
.backchain_offset
- cfun_gprs_save_area_size
;
7808 /* FPRs will not be saved. Nevertheless pick sane values to
7809 keep area calculations valid. */
7810 cfun_frame_layout
.f0_offset
=
7811 cfun_frame_layout
.f4_offset
=
7812 cfun_frame_layout
.f8_offset
= cfun_frame_layout
.gprs_offset
;
7818 /* Packed stack layout without backchain. */
7820 /* With stdarg FPRs need their dedicated slots. */
7821 num_fprs
= (TARGET_64BIT
&& cfun
->stdarg
? 2
7822 : (cfun_fpr_save_p (FPR4_REGNUM
) +
7823 cfun_fpr_save_p (FPR6_REGNUM
)));
7824 cfun_frame_layout
.f4_offset
= STACK_POINTER_OFFSET
- 8 * num_fprs
;
7826 num_fprs
= (cfun
->stdarg
? 2
7827 : (cfun_fpr_save_p (FPR0_REGNUM
)
7828 + cfun_fpr_save_p (FPR2_REGNUM
)));
7829 cfun_frame_layout
.f0_offset
= cfun_frame_layout
.f4_offset
- 8 * num_fprs
;
7831 cfun_frame_layout
.gprs_offset
7832 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7834 cfun_frame_layout
.f8_offset
= (cfun_frame_layout
.gprs_offset
7835 - cfun_frame_layout
.high_fprs
* 8);
7838 if (cfun_save_high_fprs_p
)
7839 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7842 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7844 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7845 sized area at the bottom of the stack. This is required also for
7846 leaf functions. When GCC generates a local stack reference it
7847 will always add STACK_POINTER_OFFSET to all these references. */
7849 && !TARGET_TPF_PROFILING
7850 && cfun_frame_layout
.frame_size
== 0
7851 && !cfun
->calls_alloca
)
7854 /* Calculate the number of bytes we have used in our own register
7855 save area. With the packed stack layout we can re-use the
7856 remaining bytes for normal stack elements. */
7858 if (TARGET_PACKED_STACK
)
7859 lowest_offset
= MIN (MIN (cfun_frame_layout
.f0_offset
,
7860 cfun_frame_layout
.f4_offset
),
7861 cfun_frame_layout
.gprs_offset
);
7865 if (TARGET_BACKCHAIN
)
7866 lowest_offset
= MIN (lowest_offset
, cfun_frame_layout
.backchain_offset
);
7868 cfun_frame_layout
.frame_size
+= STACK_POINTER_OFFSET
- lowest_offset
;
7870 /* If under 31 bit an odd number of gprs has to be saved we have to
7871 adjust the frame size to sustain 8 byte alignment of stack
7873 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7874 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7875 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7878 /* Generate frame layout. Fills in register and frame data for the current
7879 function in cfun->machine. This routine can be called multiple times;
7880 it will re-do the complete frame layout every time. */
7883 s390_init_frame_layout (void)
7885 HOST_WIDE_INT frame_size
;
7888 gcc_assert (!reload_completed
);
7890 /* On S/390 machines, we may need to perform branch splitting, which
7891 will require both base and return address register. We have no
7892 choice but to assume we're going to need them until right at the
7893 end of the machine dependent reorg phase. */
7894 if (!TARGET_CPU_ZARCH
)
7895 cfun
->machine
->split_branches_pending_p
= true;
7899 frame_size
= cfun_frame_layout
.frame_size
;
7901 /* Try to predict whether we'll need the base register. */
7902 base_used
= cfun
->machine
->split_branches_pending_p
7903 || crtl
->uses_const_pool
7904 || (!DISP_IN_RANGE (frame_size
)
7905 && !CONST_OK_FOR_K (frame_size
));
7907 /* Decide which register to use as literal pool base. In small
7908 leaf functions, try to use an unused call-clobbered register
7909 as base register to avoid save/restore overhead. */
7911 cfun
->machine
->base_reg
= NULL_RTX
;
7912 else if (crtl
->is_leaf
&& !df_regs_ever_live_p (5))
7913 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7915 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7917 s390_register_info ();
7920 while (frame_size
!= cfun_frame_layout
.frame_size
);
7923 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
7924 the TX is nonescaping. A transaction is considered escaping if
7925 there is at least one path from tbegin returning CC0 to the
7926 function exit block without an tend.
7928 The check so far has some limitations:
7929 - only single tbegin/tend BBs are supported
7930 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7931 - when CC is copied to a GPR and the CC0 check is done with the GPR
7932 this is not supported
7936 s390_optimize_nonescaping_tx (void)
7938 const unsigned int CC0
= 1 << 3;
7939 basic_block tbegin_bb
= NULL
;
7940 basic_block tend_bb
= NULL
;
7945 rtx_insn
*tbegin_insn
= NULL
;
7947 if (!cfun
->machine
->tbegin_p
)
7950 for (bb_index
= 0; bb_index
< n_basic_blocks_for_fn (cfun
); bb_index
++)
7952 bb
= BASIC_BLOCK_FOR_FN (cfun
, bb_index
);
7957 FOR_BB_INSNS (bb
, insn
)
7959 rtx ite
, cc
, pat
, target
;
7960 unsigned HOST_WIDE_INT mask
;
7962 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
7965 pat
= PATTERN (insn
);
7967 if (GET_CODE (pat
) == PARALLEL
)
7968 pat
= XVECEXP (pat
, 0, 0);
7970 if (GET_CODE (pat
) != SET
7971 || GET_CODE (SET_SRC (pat
)) != UNSPEC_VOLATILE
)
7974 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TBEGIN
)
7980 /* Just return if the tbegin doesn't have clobbers. */
7981 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
7984 if (tbegin_bb
!= NULL
)
7987 /* Find the next conditional jump. */
7988 for (tmp
= NEXT_INSN (insn
);
7990 tmp
= NEXT_INSN (tmp
))
7992 if (reg_set_p (gen_rtx_REG (CCmode
, CC_REGNUM
), tmp
))
7997 ite
= SET_SRC (PATTERN (tmp
));
7998 if (GET_CODE (ite
) != IF_THEN_ELSE
)
8001 cc
= XEXP (XEXP (ite
, 0), 0);
8002 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
))
8003 || GET_MODE (cc
) != CCRAWmode
8004 || GET_CODE (XEXP (XEXP (ite
, 0), 1)) != CONST_INT
)
8007 if (bb
->succs
->length () != 2)
8010 mask
= INTVAL (XEXP (XEXP (ite
, 0), 1));
8011 if (GET_CODE (XEXP (ite
, 0)) == NE
)
8015 target
= XEXP (ite
, 1);
8016 else if (mask
== (CC0
^ 0xf))
8017 target
= XEXP (ite
, 2);
8025 ei
= ei_start (bb
->succs
);
8026 e1
= ei_safe_edge (ei
);
8028 e2
= ei_safe_edge (ei
);
8030 if (e2
->flags
& EDGE_FALLTHRU
)
8033 e1
= ei_safe_edge (ei
);
8036 if (!(e1
->flags
& EDGE_FALLTHRU
))
8039 tbegin_bb
= (target
== pc_rtx
) ? e1
->dest
: e2
->dest
;
8041 if (tmp
== BB_END (bb
))
8046 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TEND
)
8048 if (tend_bb
!= NULL
)
8055 /* Either we successfully remove the FPR clobbers here or we are not
8056 able to do anything for this TX. Both cases don't qualify for
8058 cfun
->machine
->tbegin_p
= false;
8060 if (tbegin_bb
== NULL
|| tend_bb
== NULL
)
8063 calculate_dominance_info (CDI_POST_DOMINATORS
);
8064 result
= dominated_by_p (CDI_POST_DOMINATORS
, tbegin_bb
, tend_bb
);
8065 free_dominance_info (CDI_POST_DOMINATORS
);
8070 PATTERN (tbegin_insn
) = gen_rtx_PARALLEL (VOIDmode
,
8072 XVECEXP (PATTERN (tbegin_insn
), 0, 0),
8073 XVECEXP (PATTERN (tbegin_insn
), 0, 1)));
8074 INSN_CODE (tbegin_insn
) = -1;
8075 df_insn_rescan (tbegin_insn
);
8080 /* Return true if it is legal to put a value with MODE into REGNO. */
8083 s390_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
8085 switch (REGNO_REG_CLASS (regno
))
8088 if (REGNO_PAIR_OK (regno
, mode
))
8090 if (mode
== SImode
|| mode
== DImode
)
8093 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
8098 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
8103 if (REGNO_PAIR_OK (regno
, mode
))
8106 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
8111 if (GET_MODE_CLASS (mode
) == MODE_CC
)
8115 if (REGNO_PAIR_OK (regno
, mode
))
8117 if (mode
== SImode
|| mode
== Pmode
)
8128 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8131 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
8133 /* Once we've decided upon a register to use as base register, it must
8134 no longer be used for any other purpose. */
8135 if (cfun
->machine
->base_reg
)
8136 if (REGNO (cfun
->machine
->base_reg
) == old_reg
8137 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
8140 /* Prevent regrename from using call-saved regs which haven't
8141 actually been saved. This is necessary since regrename assumes
8142 the backend save/restore decisions are based on
8143 df_regs_ever_live. Since we have our own routine we have to tell
8144 regrename manually about it. */
8145 if (GENERAL_REGNO_P (new_reg
)
8146 && !call_really_used_regs
[new_reg
]
8147 && cfun_gpr_save_slot (new_reg
) == 0)
8153 /* Return nonzero if register REGNO can be used as a scratch register
8157 s390_hard_regno_scratch_ok (unsigned int regno
)
8159 /* See s390_hard_regno_rename_ok. */
8160 if (GENERAL_REGNO_P (regno
)
8161 && !call_really_used_regs
[regno
]
8162 && cfun_gpr_save_slot (regno
) == 0)
8168 /* Maximum number of registers to represent a value of mode MODE
8169 in a register of class RCLASS. */
8172 s390_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
8177 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
8178 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
8180 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
8182 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
8186 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8189 /* Return true if we use LRA instead of reload pass. */
8193 return s390_lra_flag
;
8196 /* Return true if register FROM can be eliminated via register TO. */
8199 s390_can_eliminate (const int from
, const int to
)
8201 /* On zSeries machines, we have not marked the base register as fixed.
8202 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8203 If a function requires the base register, we say here that this
8204 elimination cannot be performed. This will cause reload to free
8205 up the base register (as if it were fixed). On the other hand,
8206 if the current function does *not* require the base register, we
8207 say here the elimination succeeds, which in turn allows reload
8208 to allocate the base register for any other purpose. */
8209 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
8211 if (TARGET_CPU_ZARCH
)
8213 s390_init_frame_layout ();
8214 return cfun
->machine
->base_reg
== NULL_RTX
;
8220 /* Everything else must point into the stack frame. */
8221 gcc_assert (to
== STACK_POINTER_REGNUM
8222 || to
== HARD_FRAME_POINTER_REGNUM
);
8224 gcc_assert (from
== FRAME_POINTER_REGNUM
8225 || from
== ARG_POINTER_REGNUM
8226 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
8228 /* Make sure we actually saved the return address. */
8229 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
8230 if (!crtl
->calls_eh_return
8232 && !cfun_frame_layout
.save_return_addr_p
)
8238 /* Return offset between register FROM and TO initially after prolog. */
8241 s390_initial_elimination_offset (int from
, int to
)
8243 HOST_WIDE_INT offset
;
8245 /* ??? Why are we called for non-eliminable pairs? */
8246 if (!s390_can_eliminate (from
, to
))
8251 case FRAME_POINTER_REGNUM
:
8252 offset
= (get_frame_size()
8253 + STACK_POINTER_OFFSET
8254 + crtl
->outgoing_args_size
);
8257 case ARG_POINTER_REGNUM
:
8258 s390_init_frame_layout ();
8259 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
8262 case RETURN_ADDRESS_POINTER_REGNUM
:
8263 s390_init_frame_layout ();
8265 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
8267 /* If it turns out that for stdarg nothing went into the reg
8268 save area we also do not need the return address
8270 if (cfun
->stdarg
&& !cfun_save_arg_fprs_p
)
8276 /* In order to make the following work it is not necessary for
8277 r14 to have a save slot. It is sufficient if one other GPR
8278 got one. Since the GPRs are always stored without gaps we
8279 are able to calculate where the r14 save slot would
8281 offset
= (cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
+
8282 (RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
) *
8297 /* Emit insn to save fpr REGNUM at offset OFFSET relative
8298 to register BASE. Return generated insn. */
8301 save_fpr (rtx base
, int offset
, int regnum
)
8304 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
8306 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
8307 set_mem_alias_set (addr
, get_varargs_alias_set ());
8309 set_mem_alias_set (addr
, get_frame_alias_set ());
8311 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
8314 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
8315 to register BASE. Return generated insn. */
8318 restore_fpr (rtx base
, int offset
, int regnum
)
8321 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
8322 set_mem_alias_set (addr
, get_frame_alias_set ());
8324 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
8327 /* Return true if REGNO is a global register, but not one
8328 of the special ones that need to be saved/restored in anyway. */
8331 global_not_special_regno_p (int regno
)
8333 return (global_regs
[regno
]
8334 /* These registers are special and need to be
8335 restored in any case. */
8336 && !(regno
== STACK_POINTER_REGNUM
8337 || regno
== RETURN_REGNUM
8338 || regno
== BASE_REGNUM
8339 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
8342 /* Generate insn to save registers FIRST to LAST into
8343 the register save area located at offset OFFSET
8344 relative to register BASE. */
8347 save_gprs (rtx base
, int offset
, int first
, int last
)
8349 rtx addr
, insn
, note
;
8352 addr
= plus_constant (Pmode
, base
, offset
);
8353 addr
= gen_rtx_MEM (Pmode
, addr
);
8355 set_mem_alias_set (addr
, get_frame_alias_set ());
8357 /* Special-case single register. */
8361 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
8363 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
8365 if (!global_not_special_regno_p (first
))
8366 RTX_FRAME_RELATED_P (insn
) = 1;
8371 insn
= gen_store_multiple (addr
,
8372 gen_rtx_REG (Pmode
, first
),
8373 GEN_INT (last
- first
+ 1));
8375 if (first
<= 6 && cfun
->stdarg
)
8376 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
8378 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
8381 set_mem_alias_set (mem
, get_varargs_alias_set ());
8384 /* We need to set the FRAME_RELATED flag on all SETs
8385 inside the store-multiple pattern.
8387 However, we must not emit DWARF records for registers 2..5
8388 if they are stored for use by variable arguments ...
8390 ??? Unfortunately, it is not enough to simply not the
8391 FRAME_RELATED flags for those SETs, because the first SET
8392 of the PARALLEL is always treated as if it had the flag
8393 set, even if it does not. Therefore we emit a new pattern
8394 without those registers as REG_FRAME_RELATED_EXPR note. */
8396 if (first
>= 6 && !global_not_special_regno_p (first
))
8398 rtx pat
= PATTERN (insn
);
8400 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
8401 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
8402 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
8404 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
8406 RTX_FRAME_RELATED_P (insn
) = 1;
8412 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
8413 if (!global_not_special_regno_p (start
))
8419 addr
= plus_constant (Pmode
, base
,
8420 offset
+ (start
- first
) * UNITS_PER_LONG
);
8425 note
= gen_movdi (gen_rtx_MEM (Pmode
, addr
),
8426 gen_rtx_REG (Pmode
, start
));
8428 note
= gen_movsi (gen_rtx_MEM (Pmode
, addr
),
8429 gen_rtx_REG (Pmode
, start
));
8430 note
= PATTERN (note
);
8432 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
8433 RTX_FRAME_RELATED_P (insn
) = 1;
8438 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
8439 gen_rtx_REG (Pmode
, start
),
8440 GEN_INT (last
- start
+ 1));
8441 note
= PATTERN (note
);
8443 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
8445 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
8446 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
8447 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
8449 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
8451 RTX_FRAME_RELATED_P (insn
) = 1;
8457 /* Generate insn to restore registers FIRST to LAST from
8458 the register save area located at offset OFFSET
8459 relative to register BASE. */
8462 restore_gprs (rtx base
, int offset
, int first
, int last
)
8466 addr
= plus_constant (Pmode
, base
, offset
);
8467 addr
= gen_rtx_MEM (Pmode
, addr
);
8468 set_mem_alias_set (addr
, get_frame_alias_set ());
8470 /* Special-case single register. */
8474 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
8476 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
8478 RTX_FRAME_RELATED_P (insn
) = 1;
8482 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
8484 GEN_INT (last
- first
+ 1));
8485 RTX_FRAME_RELATED_P (insn
) = 1;
8489 /* Return insn sequence to load the GOT register. */
8491 static GTY(()) rtx got_symbol
;
8493 s390_load_got (void)
8497 /* We cannot use pic_offset_table_rtx here since we use this
8498 function also for non-pic if __tls_get_offset is called and in
8499 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8501 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
8505 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8506 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
8511 if (TARGET_CPU_ZARCH
)
8513 emit_move_insn (got_rtx
, got_symbol
);
8519 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
8520 UNSPEC_LTREL_OFFSET
);
8521 offset
= gen_rtx_CONST (Pmode
, offset
);
8522 offset
= force_const_mem (Pmode
, offset
);
8524 emit_move_insn (got_rtx
, offset
);
8526 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
8528 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
8530 emit_move_insn (got_rtx
, offset
);
8533 insns
= get_insns ();
8538 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8539 and the change to the stack pointer. */
8542 s390_emit_stack_tie (void)
8544 rtx mem
= gen_frame_mem (BLKmode
,
8545 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
8547 emit_insn (gen_stack_tie (mem
));
8550 /* Copy GPRS into FPR save slots. */
8553 s390_save_gprs_to_fprs (void)
8557 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
8560 for (i
= 6; i
< 16; i
++)
8562 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
8565 emit_move_insn (gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)),
8566 gen_rtx_REG (DImode
, i
));
8567 RTX_FRAME_RELATED_P (insn
) = 1;
8572 /* Restore GPRs from FPR save slots. */
8575 s390_restore_gprs_from_fprs (void)
8579 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
8582 for (i
= 6; i
< 16; i
++)
8584 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
8587 emit_move_insn (gen_rtx_REG (DImode
, i
),
8588 gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)));
8589 df_set_regs_ever_live (i
, true);
8590 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (DImode
, i
));
8591 if (i
== STACK_POINTER_REGNUM
)
8592 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8593 plus_constant (Pmode
, stack_pointer_rtx
,
8594 STACK_POINTER_OFFSET
));
8595 RTX_FRAME_RELATED_P (insn
) = 1;
8601 /* A pass run immediately before shrink-wrapping and prologue and epilogue
8606 const pass_data pass_data_s390_early_mach
=
8608 RTL_PASS
, /* type */
8609 "early_mach", /* name */
8610 OPTGROUP_NONE
, /* optinfo_flags */
8611 TV_MACH_DEP
, /* tv_id */
8612 0, /* properties_required */
8613 0, /* properties_provided */
8614 0, /* properties_destroyed */
8615 0, /* todo_flags_start */
8616 ( TODO_df_verify
| TODO_df_finish
), /* todo_flags_finish */
8619 class pass_s390_early_mach
: public rtl_opt_pass
8622 pass_s390_early_mach (gcc::context
*ctxt
)
8623 : rtl_opt_pass (pass_data_s390_early_mach
, ctxt
)
8626 /* opt_pass methods: */
8627 virtual unsigned int execute (function
*);
8629 }; // class pass_s390_early_mach
8632 pass_s390_early_mach::execute (function
*fun
)
8636 /* Try to get rid of the FPR clobbers. */
8637 s390_optimize_nonescaping_tx ();
8639 /* Re-compute register info. */
8640 s390_register_info ();
8642 /* If we're using a base register, ensure that it is always valid for
8643 the first non-prologue instruction. */
8644 if (fun
->machine
->base_reg
)
8645 emit_insn_at_entry (gen_main_pool (fun
->machine
->base_reg
));
8647 /* Annotate all constant pool references to let the scheduler know
8648 they implicitly use the base register. */
8649 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8652 annotate_constant_pool_refs (&PATTERN (insn
));
8653 df_insn_rescan (insn
);
8660 /* Expand the prologue into a bunch of separate insns. */
8663 s390_emit_prologue (void)
8671 /* Choose best register to use for temp use within prologue.
8672 See below for why TPF must use the register 1. */
8674 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
8676 && !TARGET_TPF_PROFILING
)
8677 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8679 temp_reg
= gen_rtx_REG (Pmode
, 1);
8681 s390_save_gprs_to_fprs ();
8683 /* Save call saved gprs. */
8684 if (cfun_frame_layout
.first_save_gpr
!= -1)
8686 insn
= save_gprs (stack_pointer_rtx
,
8687 cfun_frame_layout
.gprs_offset
+
8688 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
8689 - cfun_frame_layout
.first_save_gpr_slot
),
8690 cfun_frame_layout
.first_save_gpr
,
8691 cfun_frame_layout
.last_save_gpr
);
8695 /* Dummy insn to mark literal pool slot. */
8697 if (cfun
->machine
->base_reg
)
8698 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
8700 offset
= cfun_frame_layout
.f0_offset
;
8702 /* Save f0 and f2. */
8703 for (i
= FPR0_REGNUM
; i
<= FPR0_REGNUM
+ 1; i
++)
8705 if (cfun_fpr_save_p (i
))
8707 save_fpr (stack_pointer_rtx
, offset
, i
);
8710 else if (!TARGET_PACKED_STACK
|| cfun
->stdarg
)
8714 /* Save f4 and f6. */
8715 offset
= cfun_frame_layout
.f4_offset
;
8716 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
8718 if (cfun_fpr_save_p (i
))
8720 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
8723 /* If f4 and f6 are call clobbered they are saved due to
8724 stdargs and therefore are not frame related. */
8725 if (!call_really_used_regs
[i
])
8726 RTX_FRAME_RELATED_P (insn
) = 1;
8728 else if (!TARGET_PACKED_STACK
|| call_really_used_regs
[i
])
8732 if (TARGET_PACKED_STACK
8733 && cfun_save_high_fprs_p
8734 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8736 offset
= (cfun_frame_layout
.f8_offset
8737 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8739 for (i
= FPR15_REGNUM
; i
>= FPR8_REGNUM
&& offset
>= 0; i
--)
8740 if (cfun_fpr_save_p (i
))
8742 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
8744 RTX_FRAME_RELATED_P (insn
) = 1;
8747 if (offset
>= cfun_frame_layout
.f8_offset
)
8751 if (!TARGET_PACKED_STACK
)
8752 next_fpr
= cfun_save_high_fprs_p
? FPR15_REGNUM
: 0;
8754 if (flag_stack_usage_info
)
8755 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8757 /* Decrement stack pointer. */
8759 if (cfun_frame_layout
.frame_size
> 0)
8761 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8764 if (s390_stack_size
)
8766 HOST_WIDE_INT stack_guard
;
8768 if (s390_stack_guard
)
8769 stack_guard
= s390_stack_guard
;
8772 /* If no value for stack guard is provided the smallest power of 2
8773 larger than the current frame size is chosen. */
8775 while (stack_guard
< cfun_frame_layout
.frame_size
)
8779 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8781 warning (0, "frame size of function %qs is %wd"
8782 " bytes exceeding user provided stack limit of "
8784 "An unconditional trap is added.",
8785 current_function_name(), cfun_frame_layout
.frame_size
,
8787 emit_insn (gen_trap ());
8791 /* stack_guard has to be smaller than s390_stack_size.
8792 Otherwise we would emit an AND with zero which would
8793 not match the test under mask pattern. */
8794 if (stack_guard
>= s390_stack_size
)
8796 warning (0, "frame size of function %qs is %wd"
8797 " bytes which is more than half the stack size. "
8798 "The dynamic check would not be reliable. "
8799 "No check emitted for this function.",
8800 current_function_name(),
8801 cfun_frame_layout
.frame_size
);
8805 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8806 & ~(stack_guard
- 1));
8808 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8809 GEN_INT (stack_check_mask
));
8811 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8813 t
, const0_rtx
, const0_rtx
));
8815 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8817 t
, const0_rtx
, const0_rtx
));
8822 if (s390_warn_framesize
> 0
8823 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8824 warning (0, "frame size of %qs is %wd bytes",
8825 current_function_name (), cfun_frame_layout
.frame_size
);
8827 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8828 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8830 /* Save incoming stack pointer into temp reg. */
8831 if (TARGET_BACKCHAIN
|| next_fpr
)
8832 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8834 /* Subtract frame size from stack pointer. */
8836 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8838 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8839 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8841 insn
= emit_insn (insn
);
8845 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8846 frame_off
= force_const_mem (Pmode
, frame_off
);
8848 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8849 annotate_constant_pool_refs (&PATTERN (insn
));
8852 RTX_FRAME_RELATED_P (insn
) = 1;
8853 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8854 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8855 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8856 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8859 /* Set backchain. */
8861 if (TARGET_BACKCHAIN
)
8863 if (cfun_frame_layout
.backchain_offset
)
8864 addr
= gen_rtx_MEM (Pmode
,
8865 plus_constant (Pmode
, stack_pointer_rtx
,
8866 cfun_frame_layout
.backchain_offset
));
8868 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8869 set_mem_alias_set (addr
, get_frame_alias_set ());
8870 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8873 /* If we support non-call exceptions (e.g. for Java),
8874 we need to make sure the backchain pointer is set up
8875 before any possibly trapping memory access. */
8876 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8878 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8879 emit_clobber (addr
);
8883 /* Save fprs 8 - 15 (64 bit ABI). */
8885 if (cfun_save_high_fprs_p
&& next_fpr
)
8887 /* If the stack might be accessed through a different register
8888 we have to make sure that the stack pointer decrement is not
8889 moved below the use of the stack slots. */
8890 s390_emit_stack_tie ();
8892 insn
= emit_insn (gen_add2_insn (temp_reg
,
8893 GEN_INT (cfun_frame_layout
.f8_offset
)));
8897 for (i
= FPR8_REGNUM
; i
<= next_fpr
; i
++)
8898 if (cfun_fpr_save_p (i
))
8900 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
8901 cfun_frame_layout
.frame_size
8902 + cfun_frame_layout
.f8_offset
8905 insn
= save_fpr (temp_reg
, offset
, i
);
8907 RTX_FRAME_RELATED_P (insn
) = 1;
8908 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8909 gen_rtx_SET (VOIDmode
,
8910 gen_rtx_MEM (DFmode
, addr
),
8911 gen_rtx_REG (DFmode
, i
)));
8915 /* Set frame pointer, if needed. */
8917 if (frame_pointer_needed
)
8919 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8920 RTX_FRAME_RELATED_P (insn
) = 1;
8923 /* Set up got pointer, if needed. */
8925 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8927 rtx_insn
*insns
= s390_load_got ();
8929 for (rtx_insn
*insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8930 annotate_constant_pool_refs (&PATTERN (insn
));
8935 if (TARGET_TPF_PROFILING
)
8937 /* Generate a BAS instruction to serve as a function
8938 entry intercept to facilitate the use of tracing
8939 algorithms located at the branch target. */
8940 emit_insn (gen_prologue_tpf ());
8942 /* Emit a blockage here so that all code
8943 lies between the profiling mechanisms. */
8944 emit_insn (gen_blockage ());
8948 /* Expand the epilogue into a bunch of separate insns. */
8951 s390_emit_epilogue (bool sibcall
)
8953 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8954 int area_bottom
, area_top
, offset
= 0;
8959 if (TARGET_TPF_PROFILING
)
8962 /* Generate a BAS instruction to serve as a function
8963 entry intercept to facilitate the use of tracing
8964 algorithms located at the branch target. */
8966 /* Emit a blockage here so that all code
8967 lies between the profiling mechanisms. */
8968 emit_insn (gen_blockage ());
8970 emit_insn (gen_epilogue_tpf ());
8973 /* Check whether to use frame or stack pointer for restore. */
8975 frame_pointer
= (frame_pointer_needed
8976 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8978 s390_frame_area (&area_bottom
, &area_top
);
8980 /* Check whether we can access the register save area.
8981 If not, increment the frame pointer as required. */
8983 if (area_top
<= area_bottom
)
8985 /* Nothing to restore. */
8987 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8988 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8990 /* Area is in range. */
8991 offset
= cfun_frame_layout
.frame_size
;
8995 rtx insn
, frame_off
, cfa
;
8997 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8998 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
9000 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
9001 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
9002 if (DISP_IN_RANGE (INTVAL (frame_off
)))
9004 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
9005 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
9006 insn
= emit_insn (insn
);
9010 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
9011 frame_off
= force_const_mem (Pmode
, frame_off
);
9013 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
9014 annotate_constant_pool_refs (&PATTERN (insn
));
9016 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
9017 RTX_FRAME_RELATED_P (insn
) = 1;
9020 /* Restore call saved fprs. */
9024 if (cfun_save_high_fprs_p
)
9026 next_offset
= cfun_frame_layout
.f8_offset
;
9027 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
9029 if (cfun_fpr_save_p (i
))
9031 restore_fpr (frame_pointer
,
9032 offset
+ next_offset
, i
);
9034 = alloc_reg_note (REG_CFA_RESTORE
,
9035 gen_rtx_REG (DFmode
, i
), cfa_restores
);
9044 next_offset
= cfun_frame_layout
.f4_offset
;
9046 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
9048 if (cfun_fpr_save_p (i
))
9050 restore_fpr (frame_pointer
,
9051 offset
+ next_offset
, i
);
9053 = alloc_reg_note (REG_CFA_RESTORE
,
9054 gen_rtx_REG (DFmode
, i
), cfa_restores
);
9057 else if (!TARGET_PACKED_STACK
)
9063 /* Return register. */
9065 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9067 /* Restore call saved gprs. */
9069 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9074 /* Check for global register and save them
9075 to stack location from where they get restored. */
9077 for (i
= cfun_frame_layout
.first_restore_gpr
;
9078 i
<= cfun_frame_layout
.last_restore_gpr
;
9081 if (global_not_special_regno_p (i
))
9083 addr
= plus_constant (Pmode
, frame_pointer
,
9084 offset
+ cfun_frame_layout
.gprs_offset
9085 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
9087 addr
= gen_rtx_MEM (Pmode
, addr
);
9088 set_mem_alias_set (addr
, get_frame_alias_set ());
9089 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
9093 = alloc_reg_note (REG_CFA_RESTORE
,
9094 gen_rtx_REG (Pmode
, i
), cfa_restores
);
9099 /* Fetch return address from stack before load multiple,
9100 this will do good for scheduling.
9102 Only do this if we already decided that r14 needs to be
9103 saved to a stack slot. (And not just because r14 happens to
9104 be in between two GPRs which need saving.) Otherwise it
9105 would be difficult to take that decision back in
9106 s390_optimize_prologue. */
9107 if (cfun_gpr_save_slot (RETURN_REGNUM
) == -1)
9109 int return_regnum
= find_unused_clobbered_reg();
9112 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
9114 addr
= plus_constant (Pmode
, frame_pointer
,
9115 offset
+ cfun_frame_layout
.gprs_offset
9117 - cfun_frame_layout
.first_save_gpr_slot
)
9119 addr
= gen_rtx_MEM (Pmode
, addr
);
9120 set_mem_alias_set (addr
, get_frame_alias_set ());
9121 emit_move_insn (return_reg
, addr
);
9123 /* Once we did that optimization we have to make sure
9124 s390_optimize_prologue does not try to remove the
9125 store of r14 since we will not be able to find the
9126 load issued here. */
9127 cfun_frame_layout
.save_return_addr_p
= true;
9131 insn
= restore_gprs (frame_pointer
,
9132 offset
+ cfun_frame_layout
.gprs_offset
9133 + (cfun_frame_layout
.first_restore_gpr
9134 - cfun_frame_layout
.first_save_gpr_slot
)
9136 cfun_frame_layout
.first_restore_gpr
,
9137 cfun_frame_layout
.last_restore_gpr
);
9138 insn
= emit_insn (insn
);
9139 REG_NOTES (insn
) = cfa_restores
;
9140 add_reg_note (insn
, REG_CFA_DEF_CFA
,
9141 plus_constant (Pmode
, stack_pointer_rtx
,
9142 STACK_POINTER_OFFSET
));
9143 RTX_FRAME_RELATED_P (insn
) = 1;
9146 s390_restore_gprs_from_fprs ();
9151 /* Return to caller. */
9153 p
= rtvec_alloc (2);
9155 RTVEC_ELT (p
, 0) = ret_rtx
;
9156 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
9157 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
9161 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
9164 s300_set_up_by_prologue (hard_reg_set_container
*regs
)
9166 if (cfun
->machine
->base_reg
9167 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
9168 SET_HARD_REG_BIT (regs
->set
, REGNO (cfun
->machine
->base_reg
));
9171 /* Return true if the function can use simple_return to return outside
9172 of a shrink-wrapped region. At present shrink-wrapping is supported
9176 s390_can_use_simple_return_insn (void)
9181 /* Return true if the epilogue is guaranteed to contain only a return
9182 instruction and if a direct return can therefore be used instead.
9183 One of the main advantages of using direct return instructions
9184 is that we can then use conditional returns. */
9187 s390_can_use_return_insn (void)
9191 if (!reload_completed
)
9197 if (TARGET_TPF_PROFILING
)
9200 for (i
= 0; i
< 16; i
++)
9201 if (cfun_gpr_save_slot (i
))
9204 /* For 31 bit this is not covered by the frame_size check below
9205 since f4, f6 are saved in the register save area without needing
9206 additional stack space. */
9208 && (cfun_fpr_save_p (FPR4_REGNUM
) || cfun_fpr_save_p (FPR6_REGNUM
)))
9211 if (cfun
->machine
->base_reg
9212 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
9215 return cfun_frame_layout
.frame_size
== 0;
9218 /* Return the size in bytes of a function argument of
9219 type TYPE and/or mode MODE. At least one of TYPE or
9220 MODE must be specified. */
9223 s390_function_arg_size (machine_mode mode
, const_tree type
)
9226 return int_size_in_bytes (type
);
9228 /* No type info available for some library calls ... */
9229 if (mode
!= BLKmode
)
9230 return GET_MODE_SIZE (mode
);
9232 /* If we have neither type nor mode, abort */
9236 /* Return true if a function argument of type TYPE and mode MODE
9237 is to be passed in a floating-point register, if available. */
9240 s390_function_arg_float (machine_mode mode
, const_tree type
)
9242 int size
= s390_function_arg_size (mode
, type
);
9246 /* Soft-float changes the ABI: no floating-point registers are used. */
9247 if (TARGET_SOFT_FLOAT
)
9250 /* No type info available for some library calls ... */
9252 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
9254 /* The ABI says that record types with a single member are treated
9255 just like that member would be. */
9256 while (TREE_CODE (type
) == RECORD_TYPE
)
9258 tree field
, single
= NULL_TREE
;
9260 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
9262 if (TREE_CODE (field
) != FIELD_DECL
)
9265 if (single
== NULL_TREE
)
9266 single
= TREE_TYPE (field
);
9271 if (single
== NULL_TREE
)
9277 return TREE_CODE (type
) == REAL_TYPE
;
9280 /* Return true if a function argument of type TYPE and mode MODE
9281 is to be passed in an integer register, or a pair of integer
9282 registers, if available. */
9285 s390_function_arg_integer (machine_mode mode
, const_tree type
)
9287 int size
= s390_function_arg_size (mode
, type
);
9291 /* No type info available for some library calls ... */
9293 return GET_MODE_CLASS (mode
) == MODE_INT
9294 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
9296 /* We accept small integral (and similar) types. */
9297 if (INTEGRAL_TYPE_P (type
)
9298 || POINTER_TYPE_P (type
)
9299 || TREE_CODE (type
) == NULLPTR_TYPE
9300 || TREE_CODE (type
) == OFFSET_TYPE
9301 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
9304 /* We also accept structs of size 1, 2, 4, 8 that are not
9305 passed in floating-point registers. */
9306 if (AGGREGATE_TYPE_P (type
)
9307 && exact_log2 (size
) >= 0
9308 && !s390_function_arg_float (mode
, type
))
9314 /* Return 1 if a function argument of type TYPE and mode MODE
9315 is to be passed by reference. The ABI specifies that only
9316 structures of size 1, 2, 4, or 8 bytes are passed by value,
9317 all other structures (and complex numbers) are passed by
9321 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
9322 machine_mode mode
, const_tree type
,
9323 bool named ATTRIBUTE_UNUSED
)
9325 int size
= s390_function_arg_size (mode
, type
);
9331 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
9334 if (TREE_CODE (type
) == COMPLEX_TYPE
9335 || TREE_CODE (type
) == VECTOR_TYPE
)
9342 /* Update the data in CUM to advance over an argument of mode MODE and
9343 data type TYPE. (TYPE is null for libcalls where that information
9344 may not be available.). The boolean NAMED specifies whether the
9345 argument is a named argument (as opposed to an unnamed argument
9346 matching an ellipsis). */
9349 s390_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
9350 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9352 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9354 if (s390_function_arg_float (mode
, type
))
9358 else if (s390_function_arg_integer (mode
, type
))
9360 int size
= s390_function_arg_size (mode
, type
);
9361 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
9367 /* Define where to put the arguments to a function.
9368 Value is zero to push the argument on the stack,
9369 or a hard register in which to store the argument.
9371 MODE is the argument's machine mode.
9372 TYPE is the data type of the argument (as a tree).
9373 This is null for libcalls where that information may
9375 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9376 the preceding args and about the function being called.
9377 NAMED is nonzero if this argument is a named parameter
9378 (otherwise it is an extra parameter matching an ellipsis).
9380 On S/390, we use general purpose registers 2 through 6 to
9381 pass integer, pointer, and certain structure arguments, and
9382 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9383 to pass floating point arguments. All remaining arguments
9384 are pushed to the stack. */
9387 s390_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
9388 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9390 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9392 if (s390_function_arg_float (mode
, type
))
9394 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
9397 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
9399 else if (s390_function_arg_integer (mode
, type
))
9401 int size
= s390_function_arg_size (mode
, type
);
9402 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9404 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
9406 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
9407 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
9408 else if (n_gprs
== 2)
9410 rtvec p
= rtvec_alloc (2);
9413 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
9416 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
9419 return gen_rtx_PARALLEL (mode
, p
);
9423 /* After the real arguments, expand_call calls us once again
9424 with a void_type_node type. Whatever we return here is
9425 passed as operand 2 to the call expanders.
9427 We don't need this feature ... */
9428 else if (type
== void_type_node
)
9434 /* Return true if return values of type TYPE should be returned
9435 in a memory buffer whose address is passed by the caller as
9436 hidden first argument. */
9439 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
9441 /* We accept small integral (and similar) types. */
9442 if (INTEGRAL_TYPE_P (type
)
9443 || POINTER_TYPE_P (type
)
9444 || TREE_CODE (type
) == OFFSET_TYPE
9445 || TREE_CODE (type
) == REAL_TYPE
)
9446 return int_size_in_bytes (type
) > 8;
9448 /* Aggregates and similar constructs are always returned
9450 if (AGGREGATE_TYPE_P (type
)
9451 || TREE_CODE (type
) == COMPLEX_TYPE
9452 || TREE_CODE (type
) == VECTOR_TYPE
)
9455 /* ??? We get called on all sorts of random stuff from
9456 aggregate_value_p. We can't abort, but it's not clear
9457 what's safe to return. Pretend it's a struct I guess. */
9461 /* Function arguments and return values are promoted to word size. */
9464 s390_promote_function_mode (const_tree type
, machine_mode mode
,
9466 const_tree fntype ATTRIBUTE_UNUSED
,
9467 int for_return ATTRIBUTE_UNUSED
)
9469 if (INTEGRAL_MODE_P (mode
)
9470 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
9472 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
9473 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
9480 /* Define where to return a (scalar) value of type RET_TYPE.
9481 If RET_TYPE is null, define where to return a (scalar)
9482 value of mode MODE from a libcall. */
9485 s390_function_and_libcall_value (machine_mode mode
,
9486 const_tree ret_type
,
9487 const_tree fntype_or_decl
,
9488 bool outgoing ATTRIBUTE_UNUSED
)
9490 /* For normal functions perform the promotion as
9491 promote_function_mode would do. */
9494 int unsignedp
= TYPE_UNSIGNED (ret_type
);
9495 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
9499 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
9500 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
9502 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
9503 return gen_rtx_REG (mode
, 16);
9504 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
9505 || UNITS_PER_LONG
== UNITS_PER_WORD
)
9506 return gen_rtx_REG (mode
, 2);
9507 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
9509 /* This case is triggered when returning a 64 bit value with
9510 -m31 -mzarch. Although the value would fit into a single
9511 register it has to be forced into a 32 bit register pair in
9512 order to match the ABI. */
9513 rtvec p
= rtvec_alloc (2);
9516 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
9518 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
9520 return gen_rtx_PARALLEL (mode
, p
);
9526 /* Define where to return a scalar return value of type RET_TYPE. */
9529 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
9532 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
9533 fn_decl_or_type
, outgoing
);
9536 /* Define where to return a scalar libcall return value of mode
9540 s390_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
9542 return s390_function_and_libcall_value (mode
, NULL_TREE
,
9547 /* Create and return the va_list datatype.
9549 On S/390, va_list is an array type equivalent to
9551 typedef struct __va_list_tag
9555 void *__overflow_arg_area;
9556 void *__reg_save_area;
9559 where __gpr and __fpr hold the number of general purpose
9560 or floating point arguments used up to now, respectively,
9561 __overflow_arg_area points to the stack location of the
9562 next argument passed on the stack, and __reg_save_area
9563 always points to the start of the register area in the
9564 call frame of the current function. The function prologue
9565 saves all registers used for argument passing into this
9566 area if the function uses variable arguments. */
9569 s390_build_builtin_va_list (void)
9571 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
9573 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
9576 build_decl (BUILTINS_LOCATION
,
9577 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
9579 f_gpr
= build_decl (BUILTINS_LOCATION
,
9580 FIELD_DECL
, get_identifier ("__gpr"),
9581 long_integer_type_node
);
9582 f_fpr
= build_decl (BUILTINS_LOCATION
,
9583 FIELD_DECL
, get_identifier ("__fpr"),
9584 long_integer_type_node
);
9585 f_ovf
= build_decl (BUILTINS_LOCATION
,
9586 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
9588 f_sav
= build_decl (BUILTINS_LOCATION
,
9589 FIELD_DECL
, get_identifier ("__reg_save_area"),
9592 va_list_gpr_counter_field
= f_gpr
;
9593 va_list_fpr_counter_field
= f_fpr
;
9595 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9596 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9597 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9598 DECL_FIELD_CONTEXT (f_sav
) = record
;
9600 TYPE_STUB_DECL (record
) = type_decl
;
9601 TYPE_NAME (record
) = type_decl
;
9602 TYPE_FIELDS (record
) = f_gpr
;
9603 DECL_CHAIN (f_gpr
) = f_fpr
;
9604 DECL_CHAIN (f_fpr
) = f_ovf
;
9605 DECL_CHAIN (f_ovf
) = f_sav
;
9607 layout_type (record
);
9609 /* The correct type is an array type of one element. */
9610 return build_array_type (record
, build_index_type (size_zero_node
));
9613 /* Implement va_start by filling the va_list structure VALIST.
9614 STDARG_P is always true, and ignored.
9615 NEXTARG points to the first anonymous stack argument.
9617 The following global variables are used to initialize
9618 the va_list structure:
9621 holds number of gprs and fprs used for named arguments.
9622 crtl->args.arg_offset_rtx:
9623 holds the offset of the first anonymous stack argument
9624 (relative to the virtual arg pointer). */
9627 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
9629 HOST_WIDE_INT n_gpr
, n_fpr
;
9631 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9632 tree gpr
, fpr
, ovf
, sav
, t
;
9634 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9635 f_fpr
= DECL_CHAIN (f_gpr
);
9636 f_ovf
= DECL_CHAIN (f_fpr
);
9637 f_sav
= DECL_CHAIN (f_ovf
);
9639 valist
= build_simple_mem_ref (valist
);
9640 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9641 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9642 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9643 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9645 /* Count number of gp and fp argument registers used. */
9647 n_gpr
= crtl
->args
.info
.gprs
;
9648 n_fpr
= crtl
->args
.info
.fprs
;
9650 if (cfun
->va_list_gpr_size
)
9652 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9653 build_int_cst (NULL_TREE
, n_gpr
));
9654 TREE_SIDE_EFFECTS (t
) = 1;
9655 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9658 if (cfun
->va_list_fpr_size
)
9660 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9661 build_int_cst (NULL_TREE
, n_fpr
));
9662 TREE_SIDE_EFFECTS (t
) = 1;
9663 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9666 /* Find the overflow area. */
9667 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
9668 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
9670 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9672 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
9673 off
= off
< 0 ? 0 : off
;
9674 if (TARGET_DEBUG_ARG
)
9675 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9676 (int)n_gpr
, (int)n_fpr
, off
);
9678 t
= fold_build_pointer_plus_hwi (t
, off
);
9680 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9681 TREE_SIDE_EFFECTS (t
) = 1;
9682 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9685 /* Find the register save area. */
9686 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
9687 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
9689 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
9690 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
9692 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9693 TREE_SIDE_EFFECTS (t
) = 1;
9694 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9698 /* Implement va_arg by updating the va_list structure
9699 VALIST as required to retrieve an argument of type
9700 TYPE, and returning that argument.
9702 Generates code equivalent to:
9704 if (integral value) {
9705 if (size <= 4 && args.gpr < 5 ||
9706 size > 4 && args.gpr < 4 )
9707 ret = args.reg_save_area[args.gpr+8]
9709 ret = *args.overflow_arg_area++;
9710 } else if (float value) {
9712 ret = args.reg_save_area[args.fpr+64]
9714 ret = *args.overflow_arg_area++;
9715 } else if (aggregate value) {
9717 ret = *args.reg_save_area[args.gpr]
9719 ret = **args.overflow_arg_area++;
9723 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9724 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
9726 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9727 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9728 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
9729 tree lab_false
, lab_over
, addr
;
9731 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9732 f_fpr
= DECL_CHAIN (f_gpr
);
9733 f_ovf
= DECL_CHAIN (f_fpr
);
9734 f_sav
= DECL_CHAIN (f_ovf
);
9736 valist
= build_va_arg_indirect_ref (valist
);
9737 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9738 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9739 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9741 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9742 both appear on a lhs. */
9743 valist
= unshare_expr (valist
);
9744 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9746 size
= int_size_in_bytes (type
);
9748 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9750 if (TARGET_DEBUG_ARG
)
9752 fprintf (stderr
, "va_arg: aggregate type");
9756 /* Aggregates are passed by reference. */
9761 /* kernel stack layout on 31 bit: It is assumed here that no padding
9762 will be added by s390_frame_info because for va_args always an even
9763 number of gprs has to be saved r15-r2 = 14 regs. */
9764 sav_ofs
= 2 * UNITS_PER_LONG
;
9765 sav_scale
= UNITS_PER_LONG
;
9766 size
= UNITS_PER_LONG
;
9767 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9769 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
9771 if (TARGET_DEBUG_ARG
)
9773 fprintf (stderr
, "va_arg: float type");
9777 /* FP args go in FP registers, if present. */
9781 sav_ofs
= 16 * UNITS_PER_LONG
;
9783 max_reg
= FP_ARG_NUM_REG
- n_reg
;
9787 if (TARGET_DEBUG_ARG
)
9789 fprintf (stderr
, "va_arg: other type");
9793 /* Otherwise into GP registers. */
9796 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9798 /* kernel stack layout on 31 bit: It is assumed here that no padding
9799 will be added by s390_frame_info because for va_args always an even
9800 number of gprs has to be saved r15-r2 = 14 regs. */
9801 sav_ofs
= 2 * UNITS_PER_LONG
;
9803 if (size
< UNITS_PER_LONG
)
9804 sav_ofs
+= UNITS_PER_LONG
- size
;
9806 sav_scale
= UNITS_PER_LONG
;
9807 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9810 /* Pull the value out of the saved registers ... */
9812 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9813 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9814 addr
= create_tmp_var (ptr_type_node
, "addr");
9816 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9817 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9818 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9819 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9820 gimplify_and_add (t
, pre_p
);
9822 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9823 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9824 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9825 t
= fold_build_pointer_plus (t
, u
);
9827 gimplify_assign (addr
, t
, pre_p
);
9829 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9831 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9834 /* ... Otherwise out of the overflow area. */
9837 if (size
< UNITS_PER_LONG
)
9838 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
9840 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9842 gimplify_assign (addr
, t
, pre_p
);
9844 t
= fold_build_pointer_plus_hwi (t
, size
);
9845 gimplify_assign (ovf
, t
, pre_p
);
9847 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9850 /* Increment register save count. */
9852 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9853 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9854 gimplify_and_add (u
, pre_p
);
9858 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9860 addr
= fold_convert (t
, addr
);
9861 addr
= build_va_arg_indirect_ref (addr
);
9865 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9866 addr
= fold_convert (t
, addr
);
9869 return build_va_arg_indirect_ref (addr
);
9872 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9874 DEST - Register location where CC will be stored.
9875 TDB - Pointer to a 256 byte area where to store the transaction.
9876 diagnostic block. NULL if TDB is not needed.
9877 RETRY - Retry count value. If non-NULL a retry loop for CC2
9879 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9880 of the tbegin instruction pattern. */
9883 s390_expand_tbegin (rtx dest
, rtx tdb
, rtx retry
, bool clobber_fprs_p
)
9885 rtx retry_plus_two
= gen_reg_rtx (SImode
);
9886 rtx retry_reg
= gen_reg_rtx (SImode
);
9887 rtx_code_label
*retry_label
= NULL
;
9889 if (retry
!= NULL_RTX
)
9891 emit_move_insn (retry_reg
, retry
);
9892 emit_insn (gen_addsi3 (retry_plus_two
, retry_reg
, const2_rtx
));
9893 emit_insn (gen_addsi3 (retry_reg
, retry_reg
, const1_rtx
));
9894 retry_label
= gen_label_rtx ();
9895 emit_label (retry_label
);
9899 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
), tdb
));
9901 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
9904 emit_move_insn (dest
, gen_rtx_UNSPEC (SImode
,
9905 gen_rtvec (1, gen_rtx_REG (CCRAWmode
,
9908 if (retry
!= NULL_RTX
)
9910 const int CC0
= 1 << 3;
9911 const int CC1
= 1 << 2;
9912 const int CC3
= 1 << 0;
9914 rtx count
= gen_reg_rtx (SImode
);
9915 rtx_code_label
*leave_label
= gen_label_rtx ();
9917 /* Exit for success and permanent failures. */
9918 jump
= s390_emit_jump (leave_label
,
9919 gen_rtx_EQ (VOIDmode
,
9920 gen_rtx_REG (CCRAWmode
, CC_REGNUM
),
9921 gen_rtx_CONST_INT (VOIDmode
, CC0
| CC1
| CC3
)));
9922 LABEL_NUSES (leave_label
) = 1;
9924 /* CC2 - transient failure. Perform retry with ppa. */
9925 emit_move_insn (count
, retry_plus_two
);
9926 emit_insn (gen_subsi3 (count
, count
, retry_reg
));
9927 emit_insn (gen_tx_assist (count
));
9928 jump
= emit_jump_insn (gen_doloop_si64 (retry_label
,
9931 JUMP_LABEL (jump
) = retry_label
;
9932 LABEL_NUSES (retry_label
) = 1;
9933 emit_label (leave_label
);
9941 S390_BUILTIN_TBEGIN
,
9942 S390_BUILTIN_TBEGIN_NOFLOAT
,
9943 S390_BUILTIN_TBEGIN_RETRY
,
9944 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT
,
9945 S390_BUILTIN_TBEGINC
,
9947 S390_BUILTIN_TABORT
,
9948 S390_BUILTIN_NON_TX_STORE
,
9949 S390_BUILTIN_TX_NESTING_DEPTH
,
9950 S390_BUILTIN_TX_ASSIST
,
9955 static enum insn_code
const code_for_builtin
[S390_BUILTIN_max
] = {
9957 CODE_FOR_tbegin_nofloat
,
9958 CODE_FOR_tbegin_retry
,
9959 CODE_FOR_tbegin_retry_nofloat
,
9969 s390_init_builtins (void)
9971 tree ftype
, uint64_type
;
9972 tree returns_twice_attr
= tree_cons (get_identifier ("returns_twice"),
9974 tree noreturn_attr
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
9976 /* void foo (void) */
9977 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
9978 add_builtin_function ("__builtin_tbeginc", ftype
, S390_BUILTIN_TBEGINC
,
9979 BUILT_IN_MD
, NULL
, NULL_TREE
);
9981 /* void foo (int) */
9982 ftype
= build_function_type_list (void_type_node
, integer_type_node
,
9984 add_builtin_function ("__builtin_tabort", ftype
,
9985 S390_BUILTIN_TABORT
, BUILT_IN_MD
, NULL
, noreturn_attr
);
9986 add_builtin_function ("__builtin_tx_assist", ftype
,
9987 S390_BUILTIN_TX_ASSIST
, BUILT_IN_MD
, NULL
, NULL_TREE
);
9989 /* int foo (void *) */
9990 ftype
= build_function_type_list (integer_type_node
, ptr_type_node
, NULL_TREE
);
9991 add_builtin_function ("__builtin_tbegin", ftype
, S390_BUILTIN_TBEGIN
,
9992 BUILT_IN_MD
, NULL
, returns_twice_attr
);
9993 add_builtin_function ("__builtin_tbegin_nofloat", ftype
,
9994 S390_BUILTIN_TBEGIN_NOFLOAT
,
9995 BUILT_IN_MD
, NULL
, returns_twice_attr
);
9997 /* int foo (void *, int) */
9998 ftype
= build_function_type_list (integer_type_node
, ptr_type_node
,
9999 integer_type_node
, NULL_TREE
);
10000 add_builtin_function ("__builtin_tbegin_retry", ftype
,
10001 S390_BUILTIN_TBEGIN_RETRY
,
10003 NULL
, returns_twice_attr
);
10004 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype
,
10005 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT
,
10007 NULL
, returns_twice_attr
);
10009 /* int foo (void) */
10010 ftype
= build_function_type_list (integer_type_node
, NULL_TREE
);
10011 add_builtin_function ("__builtin_tx_nesting_depth", ftype
,
10012 S390_BUILTIN_TX_NESTING_DEPTH
,
10013 BUILT_IN_MD
, NULL
, NULL_TREE
);
10014 add_builtin_function ("__builtin_tend", ftype
,
10015 S390_BUILTIN_TEND
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10017 /* void foo (uint64_t *, uint64_t) */
10019 uint64_type
= long_unsigned_type_node
;
10021 uint64_type
= long_long_unsigned_type_node
;
10023 ftype
= build_function_type_list (void_type_node
,
10024 build_pointer_type (uint64_type
),
10025 uint64_type
, NULL_TREE
);
10026 add_builtin_function ("__builtin_non_tx_store", ftype
,
10027 S390_BUILTIN_NON_TX_STORE
,
10028 BUILT_IN_MD
, NULL
, NULL_TREE
);
10031 /* Expand an expression EXP that calls a built-in function,
10032 with result going to TARGET if that's convenient
10033 (and in mode MODE if that's convenient).
10034 SUBTARGET may be used as the target for computing one of EXP's operands.
10035 IGNORE is nonzero if the value is to be ignored. */
10038 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10039 machine_mode mode ATTRIBUTE_UNUSED
,
10040 int ignore ATTRIBUTE_UNUSED
)
10044 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10045 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10046 enum insn_code icode
;
10047 rtx op
[MAX_ARGS
], pat
;
10051 call_expr_arg_iterator iter
;
10053 if (fcode
>= S390_BUILTIN_max
)
10054 internal_error ("bad builtin fcode");
10055 icode
= code_for_builtin
[fcode
];
10057 internal_error ("bad builtin fcode");
10060 error ("Transactional execution builtins not enabled (-mhtm)\n");
10062 /* Set a flag in the machine specific cfun part in order to support
10063 saving/restoring of FPRs. */
10064 if (fcode
== S390_BUILTIN_TBEGIN
|| fcode
== S390_BUILTIN_TBEGIN_RETRY
)
10065 cfun
->machine
->tbegin_p
= true;
10067 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10070 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10072 const struct insn_operand_data
*insn_op
;
10074 if (arg
== error_mark_node
)
10076 if (arity
>= MAX_ARGS
)
10079 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
10081 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
10083 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
10085 if (insn_op
->predicate
== memory_operand
)
10087 /* Don't move a NULL pointer into a register. Otherwise
10088 we have to rely on combine being able to move it back
10089 in order to get an immediate 0 in the instruction. */
10090 if (op
[arity
] != const0_rtx
)
10091 op
[arity
] = copy_to_mode_reg (Pmode
, op
[arity
]);
10092 op
[arity
] = gen_rtx_MEM (insn_op
->mode
, op
[arity
]);
10095 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
10103 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10105 || GET_MODE (target
) != tmode
10106 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10107 target
= gen_reg_rtx (tmode
);
10113 pat
= GEN_FCN (icode
) (target
);
10117 pat
= GEN_FCN (icode
) (target
, op
[0]);
10119 pat
= GEN_FCN (icode
) (op
[0]);
10123 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
10125 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10128 gcc_unreachable ();
10140 /* We call mcount before the function prologue. So a profiled leaf
10141 function should stay a leaf function. */
10144 s390_keep_leaf_when_profiled ()
10149 /* Output assembly code for the trampoline template to
10152 On S/390, we use gpr 1 internally in the trampoline code;
10153 gpr 0 is used to hold the static chain. */
10156 s390_asm_trampoline_template (FILE *file
)
10159 op
[0] = gen_rtx_REG (Pmode
, 0);
10160 op
[1] = gen_rtx_REG (Pmode
, 1);
10164 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
10165 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
10166 output_asm_insn ("br\t%1", op
); /* 2 byte */
10167 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
10171 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
10172 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
10173 output_asm_insn ("br\t%1", op
); /* 2 byte */
10174 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
10178 /* Emit RTL insns to initialize the variable parts of a trampoline.
10179 FNADDR is an RTX for the address of the function's pure code.
10180 CXT is an RTX for the static chain value for the function. */
10183 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
10185 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10188 emit_block_move (m_tramp
, assemble_trampoline_template (),
10189 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
10191 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
10192 emit_move_insn (mem
, cxt
);
10193 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
10194 emit_move_insn (mem
, fnaddr
);
10197 /* Output assembler code to FILE to increment profiler label # LABELNO
10198 for profiling a function entry. */
10201 s390_function_profiler (FILE *file
, int labelno
)
10206 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
10208 fprintf (file
, "# function profiler \n");
10210 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10211 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
10212 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
10214 op
[2] = gen_rtx_REG (Pmode
, 1);
10215 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
10216 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
10218 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
10221 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
10222 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
10227 output_asm_insn ("stg\t%0,%1", op
);
10228 output_asm_insn ("larl\t%2,%3", op
);
10229 output_asm_insn ("brasl\t%0,%4", op
);
10230 output_asm_insn ("lg\t%0,%1", op
);
10232 else if (!flag_pic
)
10234 op
[6] = gen_label_rtx ();
10236 output_asm_insn ("st\t%0,%1", op
);
10237 output_asm_insn ("bras\t%2,%l6", op
);
10238 output_asm_insn (".long\t%4", op
);
10239 output_asm_insn (".long\t%3", op
);
10240 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
10241 output_asm_insn ("l\t%0,0(%2)", op
);
10242 output_asm_insn ("l\t%2,4(%2)", op
);
10243 output_asm_insn ("basr\t%0,%0", op
);
10244 output_asm_insn ("l\t%0,%1", op
);
10248 op
[5] = gen_label_rtx ();
10249 op
[6] = gen_label_rtx ();
10251 output_asm_insn ("st\t%0,%1", op
);
10252 output_asm_insn ("bras\t%2,%l6", op
);
10253 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
10254 output_asm_insn (".long\t%4-%l5", op
);
10255 output_asm_insn (".long\t%3-%l5", op
);
10256 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
10257 output_asm_insn ("lr\t%0,%2", op
);
10258 output_asm_insn ("a\t%0,0(%2)", op
);
10259 output_asm_insn ("a\t%2,4(%2)", op
);
10260 output_asm_insn ("basr\t%0,%0", op
);
10261 output_asm_insn ("l\t%0,%1", op
);
10265 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10266 into its SYMBOL_REF_FLAGS. */
10269 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
10271 default_encode_section_info (decl
, rtl
, first
);
10273 if (TREE_CODE (decl
) == VAR_DECL
)
10275 /* If a variable has a forced alignment to < 2 bytes, mark it
10276 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10278 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
10279 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
10280 if (!DECL_SIZE (decl
)
10281 || !DECL_ALIGN (decl
)
10282 || !tree_fits_shwi_p (DECL_SIZE (decl
))
10283 || (DECL_ALIGN (decl
) <= 64
10284 && DECL_ALIGN (decl
) != tree_to_shwi (DECL_SIZE (decl
))))
10285 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
10288 /* Literal pool references don't have a decl so they are handled
10289 differently here. We rely on the information in the MEM_ALIGN
10290 entry to decide upon natural alignment. */
10292 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
10293 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
10294 && (MEM_ALIGN (rtl
) == 0
10295 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
10296 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
10297 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
10300 /* Output thunk to FILE that implements a C++ virtual function call (with
10301 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10302 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10303 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10304 relative to the resulting this pointer. */
10307 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
10308 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10314 /* Make sure unwind info is emitted for the thunk if needed. */
10315 final_start_function (emit_barrier (), file
, 1);
10317 /* Operand 0 is the target function. */
10318 op
[0] = XEXP (DECL_RTL (function
), 0);
10319 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
10322 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
10323 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
10324 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
10327 /* Operand 1 is the 'this' pointer. */
10328 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10329 op
[1] = gen_rtx_REG (Pmode
, 3);
10331 op
[1] = gen_rtx_REG (Pmode
, 2);
10333 /* Operand 2 is the delta. */
10334 op
[2] = GEN_INT (delta
);
10336 /* Operand 3 is the vcall_offset. */
10337 op
[3] = GEN_INT (vcall_offset
);
10339 /* Operand 4 is the temporary register. */
10340 op
[4] = gen_rtx_REG (Pmode
, 1);
10342 /* Operands 5 to 8 can be used as labels. */
10348 /* Operand 9 can be used for temporary register. */
10351 /* Generate code. */
10354 /* Setup literal pool pointer if required. */
10355 if ((!DISP_IN_RANGE (delta
)
10356 && !CONST_OK_FOR_K (delta
)
10357 && !CONST_OK_FOR_Os (delta
))
10358 || (!DISP_IN_RANGE (vcall_offset
)
10359 && !CONST_OK_FOR_K (vcall_offset
)
10360 && !CONST_OK_FOR_Os (vcall_offset
)))
10362 op
[5] = gen_label_rtx ();
10363 output_asm_insn ("larl\t%4,%5", op
);
10366 /* Add DELTA to this pointer. */
10369 if (CONST_OK_FOR_J (delta
))
10370 output_asm_insn ("la\t%1,%2(%1)", op
);
10371 else if (DISP_IN_RANGE (delta
))
10372 output_asm_insn ("lay\t%1,%2(%1)", op
);
10373 else if (CONST_OK_FOR_K (delta
))
10374 output_asm_insn ("aghi\t%1,%2", op
);
10375 else if (CONST_OK_FOR_Os (delta
))
10376 output_asm_insn ("agfi\t%1,%2", op
);
10379 op
[6] = gen_label_rtx ();
10380 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
10384 /* Perform vcall adjustment. */
10387 if (DISP_IN_RANGE (vcall_offset
))
10389 output_asm_insn ("lg\t%4,0(%1)", op
);
10390 output_asm_insn ("ag\t%1,%3(%4)", op
);
10392 else if (CONST_OK_FOR_K (vcall_offset
))
10394 output_asm_insn ("lghi\t%4,%3", op
);
10395 output_asm_insn ("ag\t%4,0(%1)", op
);
10396 output_asm_insn ("ag\t%1,0(%4)", op
);
10398 else if (CONST_OK_FOR_Os (vcall_offset
))
10400 output_asm_insn ("lgfi\t%4,%3", op
);
10401 output_asm_insn ("ag\t%4,0(%1)", op
);
10402 output_asm_insn ("ag\t%1,0(%4)", op
);
10406 op
[7] = gen_label_rtx ();
10407 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
10408 output_asm_insn ("ag\t%4,0(%1)", op
);
10409 output_asm_insn ("ag\t%1,0(%4)", op
);
10413 /* Jump to target. */
10414 output_asm_insn ("jg\t%0", op
);
10416 /* Output literal pool if required. */
10419 output_asm_insn (".align\t4", op
);
10420 targetm
.asm_out
.internal_label (file
, "L",
10421 CODE_LABEL_NUMBER (op
[5]));
10425 targetm
.asm_out
.internal_label (file
, "L",
10426 CODE_LABEL_NUMBER (op
[6]));
10427 output_asm_insn (".long\t%2", op
);
10431 targetm
.asm_out
.internal_label (file
, "L",
10432 CODE_LABEL_NUMBER (op
[7]));
10433 output_asm_insn (".long\t%3", op
);
10438 /* Setup base pointer if required. */
10440 || (!DISP_IN_RANGE (delta
)
10441 && !CONST_OK_FOR_K (delta
)
10442 && !CONST_OK_FOR_Os (delta
))
10443 || (!DISP_IN_RANGE (delta
)
10444 && !CONST_OK_FOR_K (vcall_offset
)
10445 && !CONST_OK_FOR_Os (vcall_offset
)))
10447 op
[5] = gen_label_rtx ();
10448 output_asm_insn ("basr\t%4,0", op
);
10449 targetm
.asm_out
.internal_label (file
, "L",
10450 CODE_LABEL_NUMBER (op
[5]));
10453 /* Add DELTA to this pointer. */
10456 if (CONST_OK_FOR_J (delta
))
10457 output_asm_insn ("la\t%1,%2(%1)", op
);
10458 else if (DISP_IN_RANGE (delta
))
10459 output_asm_insn ("lay\t%1,%2(%1)", op
);
10460 else if (CONST_OK_FOR_K (delta
))
10461 output_asm_insn ("ahi\t%1,%2", op
);
10462 else if (CONST_OK_FOR_Os (delta
))
10463 output_asm_insn ("afi\t%1,%2", op
);
10466 op
[6] = gen_label_rtx ();
10467 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
10471 /* Perform vcall adjustment. */
10474 if (CONST_OK_FOR_J (vcall_offset
))
10476 output_asm_insn ("l\t%4,0(%1)", op
);
10477 output_asm_insn ("a\t%1,%3(%4)", op
);
10479 else if (DISP_IN_RANGE (vcall_offset
))
10481 output_asm_insn ("l\t%4,0(%1)", op
);
10482 output_asm_insn ("ay\t%1,%3(%4)", op
);
10484 else if (CONST_OK_FOR_K (vcall_offset
))
10486 output_asm_insn ("lhi\t%4,%3", op
);
10487 output_asm_insn ("a\t%4,0(%1)", op
);
10488 output_asm_insn ("a\t%1,0(%4)", op
);
10490 else if (CONST_OK_FOR_Os (vcall_offset
))
10492 output_asm_insn ("iilf\t%4,%3", op
);
10493 output_asm_insn ("a\t%4,0(%1)", op
);
10494 output_asm_insn ("a\t%1,0(%4)", op
);
10498 op
[7] = gen_label_rtx ();
10499 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
10500 output_asm_insn ("a\t%4,0(%1)", op
);
10501 output_asm_insn ("a\t%1,0(%4)", op
);
10504 /* We had to clobber the base pointer register.
10505 Re-setup the base pointer (with a different base). */
10506 op
[5] = gen_label_rtx ();
10507 output_asm_insn ("basr\t%4,0", op
);
10508 targetm
.asm_out
.internal_label (file
, "L",
10509 CODE_LABEL_NUMBER (op
[5]));
10512 /* Jump to target. */
10513 op
[8] = gen_label_rtx ();
10516 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
10517 else if (!nonlocal
)
10518 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
10519 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10520 else if (flag_pic
== 1)
10522 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
10523 output_asm_insn ("l\t%4,%0(%4)", op
);
10525 else if (flag_pic
== 2)
10527 op
[9] = gen_rtx_REG (Pmode
, 0);
10528 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
10529 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
10530 output_asm_insn ("ar\t%4,%9", op
);
10531 output_asm_insn ("l\t%4,0(%4)", op
);
10534 output_asm_insn ("br\t%4", op
);
10536 /* Output literal pool. */
10537 output_asm_insn (".align\t4", op
);
10539 if (nonlocal
&& flag_pic
== 2)
10540 output_asm_insn (".long\t%0", op
);
10543 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
10544 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
10547 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
10549 output_asm_insn (".long\t%0", op
);
10551 output_asm_insn (".long\t%0-%5", op
);
10555 targetm
.asm_out
.internal_label (file
, "L",
10556 CODE_LABEL_NUMBER (op
[6]));
10557 output_asm_insn (".long\t%2", op
);
10561 targetm
.asm_out
.internal_label (file
, "L",
10562 CODE_LABEL_NUMBER (op
[7]));
10563 output_asm_insn (".long\t%3", op
);
10566 final_end_function ();
10570 s390_valid_pointer_mode (machine_mode mode
)
10572 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
10575 /* Checks whether the given CALL_EXPR would use a caller
10576 saved register. This is used to decide whether sibling call
10577 optimization could be performed on the respective function
10581 s390_call_saved_register_used (tree call_expr
)
10583 CUMULATIVE_ARGS cum_v
;
10584 cumulative_args_t cum
;
10591 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
10592 cum
= pack_cumulative_args (&cum_v
);
10594 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
10596 parameter
= CALL_EXPR_ARG (call_expr
, i
);
10597 gcc_assert (parameter
);
10599 /* For an undeclared variable passed as parameter we will get
10600 an ERROR_MARK node here. */
10601 if (TREE_CODE (parameter
) == ERROR_MARK
)
10604 type
= TREE_TYPE (parameter
);
10607 mode
= TYPE_MODE (type
);
10610 if (pass_by_reference (&cum_v
, mode
, type
, true))
10613 type
= build_pointer_type (type
);
10616 parm_rtx
= s390_function_arg (cum
, mode
, type
, 0);
10618 s390_function_arg_advance (cum
, mode
, type
, 0);
10623 if (REG_P (parm_rtx
))
10626 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
10628 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
10632 if (GET_CODE (parm_rtx
) == PARALLEL
)
10636 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
10638 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
10640 gcc_assert (REG_P (r
));
10643 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
10645 if (!call_used_regs
[reg
+ REGNO (r
)])
10654 /* Return true if the given call expression can be
10655 turned into a sibling call.
10656 DECL holds the declaration of the function to be called whereas
10657 EXP is the call expression itself. */
10660 s390_function_ok_for_sibcall (tree decl
, tree exp
)
10662 /* The TPF epilogue uses register 1. */
10663 if (TARGET_TPF_PROFILING
)
10666 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10667 which would have to be restored before the sibcall. */
10668 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
10671 /* Register 6 on s390 is available as an argument register but unfortunately
10672 "caller saved". This makes functions needing this register for arguments
10673 not suitable for sibcalls. */
10674 return !s390_call_saved_register_used (exp
);
10677 /* Return the fixed registers used for condition codes. */
10680 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
10683 *p2
= INVALID_REGNUM
;
10688 /* This function is used by the call expanders of the machine description.
10689 It emits the call insn itself together with the necessary operations
10690 to adjust the target address and returns the emitted insn.
10691 ADDR_LOCATION is the target address rtx
10692 TLS_CALL the location of the thread-local symbol
10693 RESULT_REG the register where the result of the call should be stored
10694 RETADDR_REG the register where the return address should be stored
10695 If this parameter is NULL_RTX the call is considered
10696 to be a sibling call. */
10699 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
10702 bool plt_call
= false;
10708 /* Direct function calls need special treatment. */
10709 if (GET_CODE (addr_location
) == SYMBOL_REF
)
10711 /* When calling a global routine in PIC mode, we must
10712 replace the symbol itself with the PLT stub. */
10713 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
10715 if (retaddr_reg
!= NULL_RTX
)
10717 addr_location
= gen_rtx_UNSPEC (Pmode
,
10718 gen_rtvec (1, addr_location
),
10720 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
10724 /* For -fpic code the PLT entries might use r12 which is
10725 call-saved. Therefore we cannot do a sibcall when
10726 calling directly using a symbol ref. When reaching
10727 this point we decided (in s390_function_ok_for_sibcall)
10728 to do a sibcall for a function pointer but one of the
10729 optimizers was able to get rid of the function pointer
10730 by propagating the symbol ref into the call. This
10731 optimization is illegal for S/390 so we turn the direct
10732 call into a indirect call again. */
10733 addr_location
= force_reg (Pmode
, addr_location
);
10736 /* Unless we can use the bras(l) insn, force the
10737 routine address into a register. */
10738 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
10741 addr_location
= legitimize_pic_address (addr_location
, 0);
10743 addr_location
= force_reg (Pmode
, addr_location
);
10747 /* If it is already an indirect call or the code above moved the
10748 SYMBOL_REF to somewhere else make sure the address can be found in
10750 if (retaddr_reg
== NULL_RTX
10751 && GET_CODE (addr_location
) != SYMBOL_REF
10754 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
10755 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
10758 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
10759 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
10761 if (result_reg
!= NULL_RTX
)
10762 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
10764 if (retaddr_reg
!= NULL_RTX
)
10766 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
10768 if (tls_call
!= NULL_RTX
)
10769 vec
= gen_rtvec (3, call
, clobber
,
10770 gen_rtx_USE (VOIDmode
, tls_call
));
10772 vec
= gen_rtvec (2, call
, clobber
);
10774 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
10777 insn
= emit_call_insn (call
);
10779 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10780 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
10782 /* s390_function_ok_for_sibcall should
10783 have denied sibcalls in this case. */
10784 gcc_assert (retaddr_reg
!= NULL_RTX
);
10785 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
10790 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10793 s390_conditional_register_usage (void)
10799 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10800 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10802 if (TARGET_CPU_ZARCH
)
10804 fixed_regs
[BASE_REGNUM
] = 0;
10805 call_used_regs
[BASE_REGNUM
] = 0;
10806 fixed_regs
[RETURN_REGNUM
] = 0;
10807 call_used_regs
[RETURN_REGNUM
] = 0;
10811 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10812 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
10816 call_used_regs
[FPR4_REGNUM
] = call_really_used_regs
[FPR4_REGNUM
] = 0;
10817 call_used_regs
[FPR6_REGNUM
] = call_really_used_regs
[FPR6_REGNUM
] = 0;
10820 if (TARGET_SOFT_FLOAT
)
10822 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10823 call_used_regs
[i
] = fixed_regs
[i
] = 1;
10827 /* Corresponding function to eh_return expander. */
10829 static GTY(()) rtx s390_tpf_eh_return_symbol
;
10831 s390_emit_tpf_eh_return (rtx target
)
10836 if (!s390_tpf_eh_return_symbol
)
10837 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
10839 reg
= gen_rtx_REG (Pmode
, 2);
10840 orig_ra
= gen_rtx_REG (Pmode
, 3);
10842 emit_move_insn (reg
, target
);
10843 emit_move_insn (orig_ra
, get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
));
10844 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
10845 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
10846 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
10847 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), orig_ra
);
10849 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
10852 /* Rework the prologue/epilogue to avoid saving/restoring
10853 registers unnecessarily. */
10856 s390_optimize_prologue (void)
10858 rtx_insn
*insn
, *new_insn
, *next_insn
;
10860 /* Do a final recompute of the frame-related data. */
10861 s390_optimize_register_info ();
10863 /* If all special registers are in fact used, there's nothing we
10864 can do, so no point in walking the insn list. */
10866 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
10867 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
10868 && (TARGET_CPU_ZARCH
10869 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
10870 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
10873 /* Search for prologue/epilogue insns and replace them. */
10875 for (insn
= get_insns (); insn
; insn
= next_insn
)
10877 int first
, last
, off
;
10878 rtx set
, base
, offset
;
10881 next_insn
= NEXT_INSN (insn
);
10883 if (! NONJUMP_INSN_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
10886 pat
= PATTERN (insn
);
10888 /* Remove ldgr/lgdr instructions used for saving and restore
10889 GPRs if possible. */
10891 && GET_CODE (pat
) == SET
10892 && GET_MODE (SET_SRC (pat
)) == DImode
10893 && REG_P (SET_SRC (pat
))
10894 && REG_P (SET_DEST (pat
)))
10896 int src_regno
= REGNO (SET_SRC (pat
));
10897 int dest_regno
= REGNO (SET_DEST (pat
));
10901 if (!((GENERAL_REGNO_P (src_regno
) && FP_REGNO_P (dest_regno
))
10902 || (FP_REGNO_P (src_regno
) && GENERAL_REGNO_P (dest_regno
))))
10905 gpr_regno
= GENERAL_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
10906 fpr_regno
= FP_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
10908 /* GPR must be call-saved, FPR must be call-clobbered. */
10909 if (!call_really_used_regs
[fpr_regno
]
10910 || call_really_used_regs
[gpr_regno
])
10913 /* It must not happen that what we once saved in an FPR now
10914 needs a stack slot. */
10915 gcc_assert (cfun_gpr_save_slot (gpr_regno
) != -1);
10917 if (cfun_gpr_save_slot (gpr_regno
) == 0)
10919 remove_insn (insn
);
10924 if (GET_CODE (pat
) == PARALLEL
10925 && store_multiple_operation (pat
, VOIDmode
))
10927 set
= XVECEXP (pat
, 0, 0);
10928 first
= REGNO (SET_SRC (set
));
10929 last
= first
+ XVECLEN (pat
, 0) - 1;
10930 offset
= const0_rtx
;
10931 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10932 off
= INTVAL (offset
);
10934 if (GET_CODE (base
) != REG
|| off
< 0)
10936 if (cfun_frame_layout
.first_save_gpr
!= -1
10937 && (cfun_frame_layout
.first_save_gpr
< first
10938 || cfun_frame_layout
.last_save_gpr
> last
))
10940 if (REGNO (base
) != STACK_POINTER_REGNUM
10941 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10943 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10946 if (cfun_frame_layout
.first_save_gpr
!= -1)
10948 rtx s_pat
= save_gprs (base
,
10949 off
+ (cfun_frame_layout
.first_save_gpr
10950 - first
) * UNITS_PER_LONG
,
10951 cfun_frame_layout
.first_save_gpr
,
10952 cfun_frame_layout
.last_save_gpr
);
10953 new_insn
= emit_insn_before (s_pat
, insn
);
10954 INSN_ADDRESSES_NEW (new_insn
, -1);
10957 remove_insn (insn
);
10961 if (cfun_frame_layout
.first_save_gpr
== -1
10962 && GET_CODE (pat
) == SET
10963 && GENERAL_REG_P (SET_SRC (pat
))
10964 && GET_CODE (SET_DEST (pat
)) == MEM
)
10967 first
= REGNO (SET_SRC (set
));
10968 offset
= const0_rtx
;
10969 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10970 off
= INTVAL (offset
);
10972 if (GET_CODE (base
) != REG
|| off
< 0)
10974 if (REGNO (base
) != STACK_POINTER_REGNUM
10975 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10978 remove_insn (insn
);
10982 if (GET_CODE (pat
) == PARALLEL
10983 && load_multiple_operation (pat
, VOIDmode
))
10985 set
= XVECEXP (pat
, 0, 0);
10986 first
= REGNO (SET_DEST (set
));
10987 last
= first
+ XVECLEN (pat
, 0) - 1;
10988 offset
= const0_rtx
;
10989 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10990 off
= INTVAL (offset
);
10992 if (GET_CODE (base
) != REG
|| off
< 0)
10995 if (cfun_frame_layout
.first_restore_gpr
!= -1
10996 && (cfun_frame_layout
.first_restore_gpr
< first
10997 || cfun_frame_layout
.last_restore_gpr
> last
))
10999 if (REGNO (base
) != STACK_POINTER_REGNUM
11000 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
11002 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
11005 if (cfun_frame_layout
.first_restore_gpr
!= -1)
11007 rtx rpat
= restore_gprs (base
,
11008 off
+ (cfun_frame_layout
.first_restore_gpr
11009 - first
) * UNITS_PER_LONG
,
11010 cfun_frame_layout
.first_restore_gpr
,
11011 cfun_frame_layout
.last_restore_gpr
);
11013 /* Remove REG_CFA_RESTOREs for registers that we no
11014 longer need to save. */
11015 REG_NOTES (rpat
) = REG_NOTES (insn
);
11016 for (rtx
*ptr
= ®_NOTES (rpat
); *ptr
; )
11017 if (REG_NOTE_KIND (*ptr
) == REG_CFA_RESTORE
11018 && ((int) REGNO (XEXP (*ptr
, 0))
11019 < cfun_frame_layout
.first_restore_gpr
))
11020 *ptr
= XEXP (*ptr
, 1);
11022 ptr
= &XEXP (*ptr
, 1);
11023 new_insn
= emit_insn_before (rpat
, insn
);
11024 RTX_FRAME_RELATED_P (new_insn
) = 1;
11025 INSN_ADDRESSES_NEW (new_insn
, -1);
11028 remove_insn (insn
);
11032 if (cfun_frame_layout
.first_restore_gpr
== -1
11033 && GET_CODE (pat
) == SET
11034 && GENERAL_REG_P (SET_DEST (pat
))
11035 && GET_CODE (SET_SRC (pat
)) == MEM
)
11038 first
= REGNO (SET_DEST (set
));
11039 offset
= const0_rtx
;
11040 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
11041 off
= INTVAL (offset
);
11043 if (GET_CODE (base
) != REG
|| off
< 0)
11046 if (REGNO (base
) != STACK_POINTER_REGNUM
11047 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
11050 remove_insn (insn
);
11056 /* On z10 and later the dynamic branch prediction must see the
11057 backward jump within a certain windows. If not it falls back to
11058 the static prediction. This function rearranges the loop backward
11059 branch in a way which makes the static prediction always correct.
11060 The function returns true if it added an instruction. */
11062 s390_fix_long_loop_prediction (rtx_insn
*insn
)
11064 rtx set
= single_set (insn
);
11065 rtx code_label
, label_ref
, new_label
;
11066 rtx_insn
*uncond_jump
;
11067 rtx_insn
*cur_insn
;
11071 /* This will exclude branch on count and branch on index patterns
11072 since these are correctly statically predicted. */
11074 || SET_DEST (set
) != pc_rtx
11075 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
11078 /* Skip conditional returns. */
11079 if (ANY_RETURN_P (XEXP (SET_SRC (set
), 1))
11080 && XEXP (SET_SRC (set
), 2) == pc_rtx
)
11083 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
11084 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
11086 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
11088 code_label
= XEXP (label_ref
, 0);
11090 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
11091 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
11092 || (INSN_ADDRESSES (INSN_UID (insn
))
11093 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
11096 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
11097 distance
< PREDICT_DISTANCE
- 6;
11098 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
11099 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
11102 new_label
= gen_label_rtx ();
11103 uncond_jump
= emit_jump_insn_after (
11104 gen_rtx_SET (VOIDmode
, pc_rtx
,
11105 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
11107 emit_label_after (new_label
, uncond_jump
);
11109 tmp
= XEXP (SET_SRC (set
), 1);
11110 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
11111 XEXP (SET_SRC (set
), 2) = tmp
;
11112 INSN_CODE (insn
) = -1;
11114 XEXP (label_ref
, 0) = new_label
;
11115 JUMP_LABEL (insn
) = new_label
;
11116 JUMP_LABEL (uncond_jump
) = code_label
;
11121 /* Returns 1 if INSN reads the value of REG for purposes not related
11122 to addressing of memory, and 0 otherwise. */
11124 s390_non_addr_reg_read_p (rtx reg
, rtx_insn
*insn
)
11126 return reg_referenced_p (reg
, PATTERN (insn
))
11127 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
11130 /* Starting from INSN find_cond_jump looks downwards in the insn
11131 stream for a single jump insn which is the last user of the
11132 condition code set in INSN. */
11134 find_cond_jump (rtx_insn
*insn
)
11136 for (; insn
; insn
= NEXT_INSN (insn
))
11140 if (LABEL_P (insn
))
11143 if (!JUMP_P (insn
))
11145 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
11150 /* This will be triggered by a return. */
11151 if (GET_CODE (PATTERN (insn
)) != SET
)
11154 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
11155 ite
= SET_SRC (PATTERN (insn
));
11157 if (GET_CODE (ite
) != IF_THEN_ELSE
)
11160 cc
= XEXP (XEXP (ite
, 0), 0);
11161 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
11164 if (find_reg_note (insn
, REG_DEAD
, cc
))
11172 /* Swap the condition in COND and the operands in OP0 and OP1 so that
11173 the semantics does not change. If NULL_RTX is passed as COND the
11174 function tries to find the conditional jump starting with INSN. */
11176 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx_insn
*insn
)
11180 if (cond
== NULL_RTX
)
11182 rtx_insn
*jump
= find_cond_jump (NEXT_INSN (insn
));
11183 rtx set
= jump
? single_set (jump
) : NULL_RTX
;
11185 if (set
== NULL_RTX
)
11188 cond
= XEXP (SET_SRC (set
), 0);
11193 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
11196 /* On z10, instructions of the compare-and-branch family have the
11197 property to access the register occurring as second operand with
11198 its bits complemented. If such a compare is grouped with a second
11199 instruction that accesses the same register non-complemented, and
11200 if that register's value is delivered via a bypass, then the
11201 pipeline recycles, thereby causing significant performance decline.
11202 This function locates such situations and exchanges the two
11203 operands of the compare. The function return true whenever it
11206 s390_z10_optimize_cmp (rtx_insn
*insn
)
11208 rtx_insn
*prev_insn
, *next_insn
;
11209 bool insn_added_p
= false;
11210 rtx cond
, *op0
, *op1
;
11212 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
11214 /* Handle compare and branch and branch on count
11216 rtx pattern
= single_set (insn
);
11219 || SET_DEST (pattern
) != pc_rtx
11220 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
11223 cond
= XEXP (SET_SRC (pattern
), 0);
11224 op0
= &XEXP (cond
, 0);
11225 op1
= &XEXP (cond
, 1);
11227 else if (GET_CODE (PATTERN (insn
)) == SET
)
11231 /* Handle normal compare instructions. */
11232 src
= SET_SRC (PATTERN (insn
));
11233 dest
= SET_DEST (PATTERN (insn
));
11236 || !CC_REGNO_P (REGNO (dest
))
11237 || GET_CODE (src
) != COMPARE
)
11240 /* s390_swap_cmp will try to find the conditional
11241 jump when passing NULL_RTX as condition. */
11243 op0
= &XEXP (src
, 0);
11244 op1
= &XEXP (src
, 1);
11249 if (!REG_P (*op0
) || !REG_P (*op1
))
11252 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
11255 /* Swap the COMPARE arguments and its mask if there is a
11256 conflicting access in the previous insn. */
11257 prev_insn
= prev_active_insn (insn
);
11258 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
11259 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
11260 s390_swap_cmp (cond
, op0
, op1
, insn
);
11262 /* Check if there is a conflict with the next insn. If there
11263 was no conflict with the previous insn, then swap the
11264 COMPARE arguments and its mask. If we already swapped
11265 the operands, or if swapping them would cause a conflict
11266 with the previous insn, issue a NOP after the COMPARE in
11267 order to separate the two instuctions. */
11268 next_insn
= next_active_insn (insn
);
11269 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
11270 && s390_non_addr_reg_read_p (*op1
, next_insn
))
11272 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
11273 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
11275 if (REGNO (*op1
) == 0)
11276 emit_insn_after (gen_nop1 (), insn
);
11278 emit_insn_after (gen_nop (), insn
);
11279 insn_added_p
= true;
11282 s390_swap_cmp (cond
, op0
, op1
, insn
);
11284 return insn_added_p
;
11287 /* Perform machine-dependent processing. */
11292 bool pool_overflow
= false;
11294 /* Make sure all splits have been performed; splits after
11295 machine_dependent_reorg might confuse insn length counts. */
11296 split_all_insns_noflow ();
11298 /* Install the main literal pool and the associated base
11299 register load insns.
11301 In addition, there are two problematic situations we need
11304 - the literal pool might be > 4096 bytes in size, so that
11305 some of its elements cannot be directly accessed
11307 - a branch target might be > 64K away from the branch, so that
11308 it is not possible to use a PC-relative instruction.
11310 To fix those, we split the single literal pool into multiple
11311 pool chunks, reloading the pool base register at various
11312 points throughout the function to ensure it always points to
11313 the pool chunk the following code expects, and / or replace
11314 PC-relative branches by absolute branches.
11316 However, the two problems are interdependent: splitting the
11317 literal pool can move a branch further away from its target,
11318 causing the 64K limit to overflow, and on the other hand,
11319 replacing a PC-relative branch by an absolute branch means
11320 we need to put the branch target address into the literal
11321 pool, possibly causing it to overflow.
11323 So, we loop trying to fix up both problems until we manage
11324 to satisfy both conditions at the same time. Note that the
11325 loop is guaranteed to terminate as every pass of the loop
11326 strictly decreases the total number of PC-relative branches
11327 in the function. (This is not completely true as there
11328 might be branch-over-pool insns introduced by chunkify_start.
11329 Those never need to be split however.) */
11333 struct constant_pool
*pool
= NULL
;
11335 /* Collect the literal pool. */
11336 if (!pool_overflow
)
11338 pool
= s390_mainpool_start ();
11340 pool_overflow
= true;
11343 /* If literal pool overflowed, start to chunkify it. */
11345 pool
= s390_chunkify_start ();
11347 /* Split out-of-range branches. If this has created new
11348 literal pool entries, cancel current chunk list and
11349 recompute it. zSeries machines have large branch
11350 instructions, so we never need to split a branch. */
11351 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
11354 s390_chunkify_cancel (pool
);
11356 s390_mainpool_cancel (pool
);
11361 /* If we made it up to here, both conditions are satisfied.
11362 Finish up literal pool related changes. */
11364 s390_chunkify_finish (pool
);
11366 s390_mainpool_finish (pool
);
11368 /* We're done splitting branches. */
11369 cfun
->machine
->split_branches_pending_p
= false;
11373 /* Generate out-of-pool execute target insns. */
11374 if (TARGET_CPU_ZARCH
)
11376 rtx_insn
*insn
, *target
;
11379 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11381 label
= s390_execute_label (insn
);
11385 gcc_assert (label
!= const0_rtx
);
11387 target
= emit_label (XEXP (label
, 0));
11388 INSN_ADDRESSES_NEW (target
, -1);
11390 target
= emit_insn (s390_execute_target (insn
));
11391 INSN_ADDRESSES_NEW (target
, -1);
11395 /* Try to optimize prologue and epilogue further. */
11396 s390_optimize_prologue ();
11398 /* Walk over the insns and do some >=z10 specific changes. */
11399 if (s390_tune
== PROCESSOR_2097_Z10
11400 || s390_tune
== PROCESSOR_2817_Z196
11401 || s390_tune
== PROCESSOR_2827_ZEC12
)
11404 bool insn_added_p
= false;
11406 /* The insn lengths and addresses have to be up to date for the
11407 following manipulations. */
11408 shorten_branches (get_insns ());
11410 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11412 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
11416 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
11418 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
11419 || GET_CODE (PATTERN (insn
)) == SET
)
11420 && s390_tune
== PROCESSOR_2097_Z10
)
11421 insn_added_p
|= s390_z10_optimize_cmp (insn
);
11424 /* Adjust branches if we added new instructions. */
11426 shorten_branches (get_insns ());
11430 /* Return true if INSN is a fp load insn writing register REGNO. */
11432 s390_fpload_toreg (rtx_insn
*insn
, unsigned int regno
)
11435 enum attr_type flag
= s390_safe_attr_type (insn
);
11437 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
11440 set
= single_set (insn
);
11442 if (set
== NULL_RTX
)
11445 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
11448 if (REGNO (SET_DEST (set
)) != regno
)
11454 /* This value describes the distance to be avoided between an
11455 aritmetic fp instruction and an fp load writing the same register.
11456 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11457 fine but the exact value has to be avoided. Otherwise the FP
11458 pipeline will throw an exception causing a major penalty. */
11459 #define Z10_EARLYLOAD_DISTANCE 7
11461 /* Rearrange the ready list in order to avoid the situation described
11462 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11463 moved to the very end of the ready list. */
11465 s390_z10_prevent_earlyload_conflicts (rtx_insn
**ready
, int *nready_p
)
11467 unsigned int regno
;
11468 int nready
= *nready_p
;
11473 enum attr_type flag
;
11476 /* Skip DISTANCE - 1 active insns. */
11477 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
11478 distance
> 0 && insn
!= NULL_RTX
;
11479 distance
--, insn
= prev_active_insn (insn
))
11480 if (CALL_P (insn
) || JUMP_P (insn
))
11483 if (insn
== NULL_RTX
)
11486 set
= single_set (insn
);
11488 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
11489 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
11492 flag
= s390_safe_attr_type (insn
);
11494 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
11497 regno
= REGNO (SET_DEST (set
));
11500 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
11507 memmove (&ready
[1], &ready
[0], sizeof (rtx_insn
*) * i
);
11512 /* The s390_sched_state variable tracks the state of the current or
11513 the last instruction group.
11515 0,1,2 number of instructions scheduled in the current group
11516 3 the last group is complete - normal insns
11517 4 the last group was a cracked/expanded insn */
11519 static int s390_sched_state
;
11521 #define S390_OOO_SCHED_STATE_NORMAL 3
11522 #define S390_OOO_SCHED_STATE_CRACKED 4
11524 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11525 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11526 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11527 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11529 static unsigned int
11530 s390_get_sched_attrmask (rtx_insn
*insn
)
11532 unsigned int mask
= 0;
11534 if (get_attr_ooo_cracked (insn
))
11535 mask
|= S390_OOO_SCHED_ATTR_MASK_CRACKED
;
11536 if (get_attr_ooo_expanded (insn
))
11537 mask
|= S390_OOO_SCHED_ATTR_MASK_EXPANDED
;
11538 if (get_attr_ooo_endgroup (insn
))
11539 mask
|= S390_OOO_SCHED_ATTR_MASK_ENDGROUP
;
11540 if (get_attr_ooo_groupalone (insn
))
11541 mask
|= S390_OOO_SCHED_ATTR_MASK_GROUPALONE
;
11545 /* Return the scheduling score for INSN. The higher the score the
11546 better. The score is calculated from the OOO scheduling attributes
11547 of INSN and the scheduling state s390_sched_state. */
11549 s390_sched_score (rtx_insn
*insn
)
11551 unsigned int mask
= s390_get_sched_attrmask (insn
);
11554 switch (s390_sched_state
)
11557 /* Try to put insns into the first slot which would otherwise
11559 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
11560 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
11562 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
11565 /* Prefer not cracked insns while trying to put together a
11567 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
11568 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
11569 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
11571 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) == 0)
11575 /* Prefer not cracked insns while trying to put together a
11577 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
11578 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
11579 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
11581 /* Prefer endgroup insns in the last slot. */
11582 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0)
11585 case S390_OOO_SCHED_STATE_NORMAL
:
11586 /* Prefer not cracked insns if the last was not cracked. */
11587 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
11588 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0)
11590 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
11593 case S390_OOO_SCHED_STATE_CRACKED
:
11594 /* Try to keep cracked insns together to prevent them from
11595 interrupting groups. */
11596 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
11597 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
11604 /* This function is called via hook TARGET_SCHED_REORDER before
11605 issuing one insn from list READY which contains *NREADYP entries.
11606 For target z10 it reorders load instructions to avoid early load
11607 conflicts in the floating point pipeline */
11609 s390_sched_reorder (FILE *file
, int verbose
,
11610 rtx_insn
**ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
11612 if (s390_tune
== PROCESSOR_2097_Z10
)
11613 if (reload_completed
&& *nreadyp
> 1)
11614 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
11616 if (s390_tune
== PROCESSOR_2827_ZEC12
11617 && reload_completed
11621 int last_index
= *nreadyp
- 1;
11622 int max_index
= -1;
11623 int max_score
= -1;
11626 /* Just move the insn with the highest score to the top (the
11627 end) of the list. A full sort is not needed since a conflict
11628 in the hazard recognition cannot happen. So the top insn in
11629 the ready list will always be taken. */
11630 for (i
= last_index
; i
>= 0; i
--)
11634 if (recog_memoized (ready
[i
]) < 0)
11637 score
= s390_sched_score (ready
[i
]);
11638 if (score
> max_score
)
11645 if (max_index
!= -1)
11647 if (max_index
!= last_index
)
11649 tmp
= ready
[max_index
];
11650 ready
[max_index
] = ready
[last_index
];
11651 ready
[last_index
] = tmp
;
11655 "move insn %d to the top of list\n",
11656 INSN_UID (ready
[last_index
]));
11658 else if (verbose
> 5)
11660 "best insn %d already on top\n",
11661 INSN_UID (ready
[last_index
]));
11666 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
11669 for (i
= last_index
; i
>= 0; i
--)
11671 if (recog_memoized (ready
[i
]) < 0)
11673 fprintf (file
, "insn %d score: %d: ", INSN_UID (ready
[i
]),
11674 s390_sched_score (ready
[i
]));
11675 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11676 PRINT_OOO_ATTR (ooo_cracked
);
11677 PRINT_OOO_ATTR (ooo_expanded
);
11678 PRINT_OOO_ATTR (ooo_endgroup
);
11679 PRINT_OOO_ATTR (ooo_groupalone
);
11680 #undef PRINT_OOO_ATTR
11681 fprintf (file
, "\n");
11686 return s390_issue_rate ();
11690 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11691 the scheduler has issued INSN. It stores the last issued insn into
11692 last_scheduled_insn in order to make it available for
11693 s390_sched_reorder. */
11695 s390_sched_variable_issue (FILE *file
, int verbose
, rtx_insn
*insn
, int more
)
11697 last_scheduled_insn
= insn
;
11699 if (s390_tune
== PROCESSOR_2827_ZEC12
11700 && reload_completed
11701 && recog_memoized (insn
) >= 0)
11703 unsigned int mask
= s390_get_sched_attrmask (insn
);
11705 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
11706 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
11707 s390_sched_state
= S390_OOO_SCHED_STATE_CRACKED
;
11708 else if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0
11709 || (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
11710 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
11713 /* Only normal insns are left (mask == 0). */
11714 switch (s390_sched_state
)
11719 case S390_OOO_SCHED_STATE_NORMAL
:
11720 if (s390_sched_state
== S390_OOO_SCHED_STATE_NORMAL
)
11721 s390_sched_state
= 1;
11723 s390_sched_state
++;
11726 case S390_OOO_SCHED_STATE_CRACKED
:
11727 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
11733 fprintf (file
, "insn %d: ", INSN_UID (insn
));
11734 #define PRINT_OOO_ATTR(ATTR) \
11735 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11736 PRINT_OOO_ATTR (ooo_cracked
);
11737 PRINT_OOO_ATTR (ooo_expanded
);
11738 PRINT_OOO_ATTR (ooo_endgroup
);
11739 PRINT_OOO_ATTR (ooo_groupalone
);
11740 #undef PRINT_OOO_ATTR
11741 fprintf (file
, "\n");
11742 fprintf (file
, "sched state: %d\n", s390_sched_state
);
11746 if (GET_CODE (PATTERN (insn
)) != USE
11747 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
11754 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
11755 int verbose ATTRIBUTE_UNUSED
,
11756 int max_ready ATTRIBUTE_UNUSED
)
11758 last_scheduled_insn
= NULL
;
11759 s390_sched_state
= 0;
11762 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
11763 a new number struct loop *loop should be unrolled if tuned for cpus with
11764 a built-in stride prefetcher.
11765 The loop is analyzed for memory accesses by calling check_dpu for
11766 each rtx of the loop. Depending on the loop_depth and the amount of
11767 memory accesses a new number <=nunroll is returned to improve the
11768 behaviour of the hardware prefetch unit. */
11770 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
11775 unsigned mem_count
= 0;
11777 if (s390_tune
!= PROCESSOR_2097_Z10
11778 && s390_tune
!= PROCESSOR_2817_Z196
11779 && s390_tune
!= PROCESSOR_2827_ZEC12
)
11782 /* Count the number of memory references within the loop body. */
11783 bbs
= get_loop_body (loop
);
11784 subrtx_iterator::array_type array
;
11785 for (i
= 0; i
< loop
->num_nodes
; i
++)
11786 FOR_BB_INSNS (bbs
[i
], insn
)
11787 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
11788 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
11793 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11794 if (mem_count
== 0)
11797 switch (loop_depth(loop
))
11800 return MIN (nunroll
, 28 / mem_count
);
11802 return MIN (nunroll
, 22 / mem_count
);
11804 return MIN (nunroll
, 16 / mem_count
);
11809 s390_option_override (void)
11812 cl_deferred_option
*opt
;
11813 vec
<cl_deferred_option
> *v
=
11814 (vec
<cl_deferred_option
> *) s390_deferred_options
;
11817 FOR_EACH_VEC_ELT (*v
, i
, opt
)
11819 switch (opt
->opt_index
)
11821 case OPT_mhotpatch
:
11822 s390_hotpatch_trampoline_halfwords
= (opt
->value
) ?
11823 s390_hotpatch_trampoline_halfwords_default
: -1;
11825 case OPT_mhotpatch_
:
11829 val
= integral_argument (opt
->arg
);
11832 /* argument is not a plain number */
11833 error ("argument to %qs should be a non-negative integer",
11837 else if (val
> s390_hotpatch_trampoline_halfwords_max
)
11839 error ("argument to %qs is too large (max. %d)",
11840 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max
);
11843 s390_hotpatch_trampoline_halfwords
= val
;
11847 gcc_unreachable ();
11851 /* Set up function hooks. */
11852 init_machine_status
= s390_init_machine_status
;
11854 /* Architecture mode defaults according to ABI. */
11855 if (!(target_flags_explicit
& MASK_ZARCH
))
11858 target_flags
|= MASK_ZARCH
;
11860 target_flags
&= ~MASK_ZARCH
;
11863 /* Set the march default in case it hasn't been specified on
11865 if (s390_arch
== PROCESSOR_max
)
11867 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
11868 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
11869 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
11872 /* Determine processor to tune for. */
11873 if (s390_tune
== PROCESSOR_max
)
11875 s390_tune
= s390_arch
;
11876 s390_tune_flags
= s390_arch_flags
;
11879 /* Sanity checks. */
11880 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
11881 error ("z/Architecture mode not supported on %s", s390_arch_string
);
11882 if (TARGET_64BIT
&& !TARGET_ZARCH
)
11883 error ("64-bit ABI not supported in ESA/390 mode");
11885 /* Use hardware DFP if available and not explicitly disabled by
11886 user. E.g. with -m31 -march=z10 -mzarch */
11887 if (!(target_flags_explicit
& MASK_HARD_DFP
) && TARGET_DFP
)
11888 target_flags
|= MASK_HARD_DFP
;
11890 /* Enable hardware transactions if available and not explicitly
11891 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11892 if (!(target_flags_explicit
& MASK_OPT_HTM
) && TARGET_CPU_HTM
&& TARGET_ZARCH
)
11893 target_flags
|= MASK_OPT_HTM
;
11895 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
11897 if (target_flags_explicit
& MASK_HARD_DFP
)
11899 if (!TARGET_CPU_DFP
)
11900 error ("hardware decimal floating point instructions"
11901 " not available on %s", s390_arch_string
);
11903 error ("hardware decimal floating point instructions"
11904 " not available in ESA/390 mode");
11907 target_flags
&= ~MASK_HARD_DFP
;
11910 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
11912 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
11913 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11915 target_flags
&= ~MASK_HARD_DFP
;
11918 /* Set processor cost function. */
11921 case PROCESSOR_2084_Z990
:
11922 s390_cost
= &z990_cost
;
11924 case PROCESSOR_2094_Z9_109
:
11925 s390_cost
= &z9_109_cost
;
11927 case PROCESSOR_2097_Z10
:
11928 s390_cost
= &z10_cost
;
11930 case PROCESSOR_2817_Z196
:
11931 s390_cost
= &z196_cost
;
11933 case PROCESSOR_2827_ZEC12
:
11934 s390_cost
= &zEC12_cost
;
11937 s390_cost
= &z900_cost
;
11940 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
11941 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11944 if (s390_stack_size
)
11946 if (s390_stack_guard
>= s390_stack_size
)
11947 error ("stack size must be greater than the stack guard value");
11948 else if (s390_stack_size
> 1 << 16)
11949 error ("stack size must not be greater than 64k");
11951 else if (s390_stack_guard
)
11952 error ("-mstack-guard implies use of -mstack-size");
11954 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11955 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
11956 target_flags
|= MASK_LONG_DOUBLE_128
;
11959 if (s390_tune
== PROCESSOR_2097_Z10
11960 || s390_tune
== PROCESSOR_2817_Z196
11961 || s390_tune
== PROCESSOR_2827_ZEC12
)
11963 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
11964 global_options
.x_param_values
,
11965 global_options_set
.x_param_values
);
11966 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
11967 global_options
.x_param_values
,
11968 global_options_set
.x_param_values
);
11969 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
11970 global_options
.x_param_values
,
11971 global_options_set
.x_param_values
);
11972 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
11973 global_options
.x_param_values
,
11974 global_options_set
.x_param_values
);
11977 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
11978 global_options
.x_param_values
,
11979 global_options_set
.x_param_values
);
11980 /* values for loop prefetching */
11981 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
11982 global_options
.x_param_values
,
11983 global_options_set
.x_param_values
);
11984 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
11985 global_options
.x_param_values
,
11986 global_options_set
.x_param_values
);
11987 /* s390 has more than 2 levels and the size is much larger. Since
11988 we are always running virtualized assume that we only get a small
11989 part of the caches above l1. */
11990 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
11991 global_options
.x_param_values
,
11992 global_options_set
.x_param_values
);
11993 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
11994 global_options
.x_param_values
,
11995 global_options_set
.x_param_values
);
11996 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
11997 global_options
.x_param_values
,
11998 global_options_set
.x_param_values
);
12000 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
12001 requires the arch flags to be evaluated already. Since prefetching
12002 is beneficial on s390, we enable it if available. */
12003 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
12004 flag_prefetch_loop_arrays
= 1;
12006 /* Use the alternative scheduling-pressure algorithm by default. */
12007 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
12008 global_options
.x_param_values
,
12009 global_options_set
.x_param_values
);
12013 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12014 debuggers do not yet support DWARF 3/4. */
12015 if (!global_options_set
.x_dwarf_strict
)
12017 if (!global_options_set
.x_dwarf_version
)
12021 /* Register a target-specific optimization-and-lowering pass
12022 to run immediately before prologue and epilogue generation.
12024 Registering the pass must be done at start up. It's
12025 convenient to do it here. */
12026 opt_pass
*new_pass
= new pass_s390_early_mach (g
);
12027 struct register_pass_info insert_pass_s390_early_mach
=
12029 new_pass
, /* pass */
12030 "pro_and_epilogue", /* reference_pass_name */
12031 1, /* ref_pass_instance_number */
12032 PASS_POS_INSERT_BEFORE
/* po_op */
12034 register_pass (&insert_pass_s390_early_mach
);
12037 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12040 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
12041 unsigned int align ATTRIBUTE_UNUSED
,
12042 enum by_pieces_operation op ATTRIBUTE_UNUSED
,
12043 bool speed_p ATTRIBUTE_UNUSED
)
12045 return (size
== 1 || size
== 2
12046 || size
== 4 || (TARGET_ZARCH
&& size
== 8));
12049 /* Initialize GCC target structure. */
12051 #undef TARGET_ASM_ALIGNED_HI_OP
12052 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12053 #undef TARGET_ASM_ALIGNED_DI_OP
12054 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12055 #undef TARGET_ASM_INTEGER
12056 #define TARGET_ASM_INTEGER s390_assemble_integer
12058 #undef TARGET_ASM_OPEN_PAREN
12059 #define TARGET_ASM_OPEN_PAREN ""
12061 #undef TARGET_ASM_CLOSE_PAREN
12062 #define TARGET_ASM_CLOSE_PAREN ""
12064 #undef TARGET_OPTION_OVERRIDE
12065 #define TARGET_OPTION_OVERRIDE s390_option_override
12067 #undef TARGET_ENCODE_SECTION_INFO
12068 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
12070 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12071 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12074 #undef TARGET_HAVE_TLS
12075 #define TARGET_HAVE_TLS true
12077 #undef TARGET_CANNOT_FORCE_CONST_MEM
12078 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
12080 #undef TARGET_DELEGITIMIZE_ADDRESS
12081 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
12083 #undef TARGET_LEGITIMIZE_ADDRESS
12084 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12086 #undef TARGET_RETURN_IN_MEMORY
12087 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
12089 #undef TARGET_INIT_BUILTINS
12090 #define TARGET_INIT_BUILTINS s390_init_builtins
12091 #undef TARGET_EXPAND_BUILTIN
12092 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
12094 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12095 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12097 #undef TARGET_ASM_OUTPUT_MI_THUNK
12098 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12099 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12100 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12102 #undef TARGET_SCHED_ADJUST_PRIORITY
12103 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12104 #undef TARGET_SCHED_ISSUE_RATE
12105 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12106 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12107 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
12109 #undef TARGET_SCHED_VARIABLE_ISSUE
12110 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12111 #undef TARGET_SCHED_REORDER
12112 #define TARGET_SCHED_REORDER s390_sched_reorder
12113 #undef TARGET_SCHED_INIT
12114 #define TARGET_SCHED_INIT s390_sched_init
12116 #undef TARGET_CANNOT_COPY_INSN_P
12117 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12118 #undef TARGET_RTX_COSTS
12119 #define TARGET_RTX_COSTS s390_rtx_costs
12120 #undef TARGET_ADDRESS_COST
12121 #define TARGET_ADDRESS_COST s390_address_cost
12122 #undef TARGET_REGISTER_MOVE_COST
12123 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12124 #undef TARGET_MEMORY_MOVE_COST
12125 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
12127 #undef TARGET_MACHINE_DEPENDENT_REORG
12128 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
12130 #undef TARGET_VALID_POINTER_MODE
12131 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
12133 #undef TARGET_BUILD_BUILTIN_VA_LIST
12134 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
12135 #undef TARGET_EXPAND_BUILTIN_VA_START
12136 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
12137 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12138 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
12140 #undef TARGET_PROMOTE_FUNCTION_MODE
12141 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
12142 #undef TARGET_PASS_BY_REFERENCE
12143 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
12145 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12146 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
12147 #undef TARGET_FUNCTION_ARG
12148 #define TARGET_FUNCTION_ARG s390_function_arg
12149 #undef TARGET_FUNCTION_ARG_ADVANCE
12150 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
12151 #undef TARGET_FUNCTION_VALUE
12152 #define TARGET_FUNCTION_VALUE s390_function_value
12153 #undef TARGET_LIBCALL_VALUE
12154 #define TARGET_LIBCALL_VALUE s390_libcall_value
12156 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
12157 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12159 #undef TARGET_FIXED_CONDITION_CODE_REGS
12160 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
12162 #undef TARGET_CC_MODES_COMPATIBLE
12163 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
12165 #undef TARGET_INVALID_WITHIN_DOLOOP
12166 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
12169 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12170 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12173 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12174 #undef TARGET_MANGLE_TYPE
12175 #define TARGET_MANGLE_TYPE s390_mangle_type
12178 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12179 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12181 #undef TARGET_PREFERRED_RELOAD_CLASS
12182 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12184 #undef TARGET_SECONDARY_RELOAD
12185 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
12187 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12188 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12190 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12191 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12193 #undef TARGET_LEGITIMATE_ADDRESS_P
12194 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12196 #undef TARGET_LEGITIMATE_CONSTANT_P
12197 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12199 #undef TARGET_LRA_P
12200 #define TARGET_LRA_P s390_lra_p
12202 #undef TARGET_CAN_ELIMINATE
12203 #define TARGET_CAN_ELIMINATE s390_can_eliminate
12205 #undef TARGET_CONDITIONAL_REGISTER_USAGE
12206 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12208 #undef TARGET_LOOP_UNROLL_ADJUST
12209 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12211 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12212 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12213 #undef TARGET_TRAMPOLINE_INIT
12214 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12216 #undef TARGET_UNWIND_WORD_MODE
12217 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12219 #undef TARGET_CANONICALIZE_COMPARISON
12220 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12222 #undef TARGET_HARD_REGNO_SCRATCH_OK
12223 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12225 #undef TARGET_ATTRIBUTE_TABLE
12226 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12228 #undef TARGET_CAN_INLINE_P
12229 #define TARGET_CAN_INLINE_P s390_can_inline_p
12231 #undef TARGET_SET_UP_BY_PROLOGUE
12232 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12234 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12235 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12236 s390_use_by_pieces_infrastructure_p
12238 struct gcc_target targetm
= TARGET_INITIALIZER
;
12240 #include "gt-s390.h"