| blob | 32762759dc311e1618d28229ab56c5b9349dae88 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
110 #ifndef CHECK_STACK_LIMIT
111 #define CHECK_STACK_LIMIT (-1)
112 #endif
114 /* Return index of given mode in mult and division cost tables. */
115 #define MODE_INDEX(mode) \
116 ((mode) == QImode ? 0 \
117 : (mode) == HImode ? 1 \
118 : (mode) == SImode ? 2 \
119 : (mode) == DImode ? 3 \
120 : 4)
122 /* Processor costs (relative to an add) */
123 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
124 #define COSTS_N_BYTES(N) ((N) * 2)
126 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
135 const
158 in QImode, HImode and SImode.
159 Relative to reg-reg move (2). */
163 in SFmode, DFmode and XFmode */
165 in SFmode, DFmode and XFmode */
168 in SImode and DImode */
170 in SImode and DImode */
173 in SImode, DImode and TImode */
175 in SImode, DImode and TImode */
188 ix86_size_memcpy,
189 ix86_size_memset,
201 };
203 /* Processor costs (relative to an add) */
206 DUMMY_STRINGOP_ALGS};
209 DUMMY_STRINGOP_ALGS};
211 static const
234 in QImode, HImode and SImode.
235 Relative to reg-reg move (2). */
239 in SFmode, DFmode and XFmode */
241 in SFmode, DFmode and XFmode */
244 in SImode and DImode */
246 in SImode and DImode */
249 in SImode, DImode and TImode */
251 in SImode, DImode and TImode */
264 i386_memcpy,
265 i386_memset,
277 };
281 DUMMY_STRINGOP_ALGS};
284 DUMMY_STRINGOP_ALGS};
286 static const
309 in QImode, HImode and SImode.
310 Relative to reg-reg move (2). */
314 in SFmode, DFmode and XFmode */
316 in SFmode, DFmode and XFmode */
319 in SImode and DImode */
321 in SImode and DImode */
324 in SImode, DImode and TImode */
326 in SImode, DImode and TImode */
329 shared for code and data, so 4kB is
330 not really precise. */
341 i486_memcpy,
342 i486_memset,
354 };
358 DUMMY_STRINGOP_ALGS};
361 DUMMY_STRINGOP_ALGS};
363 static const
386 in QImode, HImode and SImode.
387 Relative to reg-reg move (2). */
391 in SFmode, DFmode and XFmode */
393 in SFmode, DFmode and XFmode */
396 in SImode and DImode */
398 in SImode and DImode */
401 in SImode, DImode and TImode */
403 in SImode, DImode and TImode */
416 pentium_memcpy,
417 pentium_memset,
429 };
431 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
432 (we ensure the alignment). For small blocks inline loop is still a
433 noticeable win, for bigger blocks either rep movsl or rep movsb is
434 way to go. Rep movsb has apparently more expensive startup time in CPU,
435 but after 4K the difference is down in the noise. */
440 DUMMY_STRINGOP_ALGS};
445 DUMMY_STRINGOP_ALGS};
446 static const
469 in QImode, HImode and SImode.
470 Relative to reg-reg move (2). */
474 in SFmode, DFmode and XFmode */
476 in SFmode, DFmode and XFmode */
479 in SImode and DImode */
481 in SImode and DImode */
484 in SImode, DImode and TImode */
486 in SImode, DImode and TImode */
499 pentiumpro_memcpy,
500 pentiumpro_memset,
512 };
516 DUMMY_STRINGOP_ALGS};
519 DUMMY_STRINGOP_ALGS};
520 static const
543 in QImode, HImode and SImode.
544 Relative to reg-reg move (2). */
548 in SFmode, DFmode and XFmode */
550 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
574 geode_memcpy,
575 geode_memset,
587 };
591 DUMMY_STRINGOP_ALGS};
594 DUMMY_STRINGOP_ALGS};
595 static const
618 in QImode, HImode and SImode.
619 Relative to reg-reg move (2). */
623 in SFmode, DFmode and XFmode */
625 in SFmode, DFmode and XFmode */
628 in SImode and DImode */
630 in SImode and DImode */
633 in SImode, DImode and TImode */
635 in SImode, DImode and TImode */
639 have integrated l2 cache, but
640 optimizing for k6 is not important
641 enough to worry about that. */
651 k6_memcpy,
652 k6_memset,
664 };
666 /* For some reason, Athlon deals better with REP prefix (relative to loops)
667 compared to K8. Alignment becomes important after 8 bytes for memcpy and
668 128 bytes for memset. */
671 DUMMY_STRINGOP_ALGS};
674 DUMMY_STRINGOP_ALGS};
675 static const
698 in QImode, HImode and SImode.
699 Relative to reg-reg move (2). */
703 in SFmode, DFmode and XFmode */
705 in SFmode, DFmode and XFmode */
708 in SImode and DImode */
710 in SImode and DImode */
713 in SImode, DImode and TImode */
715 in SImode, DImode and TImode */
728 athlon_memcpy,
729 athlon_memset,
741 };
743 /* K8 has optimized REP instruction for medium sized blocks, but for very
744 small blocks it is better to use loop. For large blocks, libcall can
745 do nontemporary accesses and beat inline considerably. */
756 static const
779 in QImode, HImode and SImode.
780 Relative to reg-reg move (2). */
784 in SFmode, DFmode and XFmode */
786 in SFmode, DFmode and XFmode */
789 in SImode and DImode */
791 in SImode and DImode */
794 in SImode, DImode and TImode */
796 in SImode, DImode and TImode */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 k8_memcpy,
816 k8_memset,
828 };
830 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
831 very small blocks it is better to use loop. For large blocks, libcall can
832 do nontemporary accesses and beat inline considerably. */
865 in QImode, HImode and SImode.
866 Relative to reg-reg move (2). */
870 in SFmode, DFmode and XFmode */
872 in SFmode, DFmode and XFmode */
875 in SImode and DImode */
877 in SImode and DImode */
880 in SImode, DImode and TImode */
882 in SImode, DImode and TImode */
884 /* On K8:
885 MOVD reg64, xmmreg Double FSTORE 4
886 MOVD reg32, xmmreg Double FSTORE 4
887 On AMDFAM10:
888 MOVD reg64, xmmreg Double FADD 3
889 1/1 1/1
890 MOVD reg32, xmmreg Double FADD 3
891 1/1 1/1 */
895 /* New AMD processors never drop prefetches; if they cannot be performed
896 immediately, they are queued. We set number of simultaneous prefetches
897 to a large constant to reflect this (it probably is not a good idea not
898 to limit number of prefetches at all, as their execution also takes some
899 time). */
909 amdfam10_memcpy,
910 amdfam10_memset,
922 };
924 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
925 very small blocks it is better to use loop. For large blocks, libcall
926 can do nontemporary accesses and beat inline considerably. */
960 in QImode, HImode and SImode.
961 Relative to reg-reg move (2). */
965 in SFmode, DFmode and XFmode */
967 in SFmode, DFmode and XFmode */
970 in SImode and DImode */
972 in SImode and DImode */
975 in SImode, DImode and TImode */
977 in SImode, DImode and TImode */
979 /* On K8:
980 MOVD reg64, xmmreg Double FSTORE 4
981 MOVD reg32, xmmreg Double FSTORE 4
982 On AMDFAM10:
983 MOVD reg64, xmmreg Double FADD 3
984 1/1 1/1
985 MOVD reg32, xmmreg Double FADD 3
986 1/1 1/1 */
990 /* New AMD processors never drop prefetches; if they cannot be performed
991 immediately, they are queued. We set number of simultaneous prefetches
992 to a large constant to reflect this (it probably is not a good idea not
993 to limit number of prefetches at all, as their execution also takes some
994 time). */
1004 bdver1_memcpy,
1005 bdver1_memset,
1017 };
1019 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1020 very small blocks it is better to use loop. For large blocks, libcall
1021 can do nontemporary accesses and beat inline considerably. */
1056 in QImode, HImode and SImode.
1057 Relative to reg-reg move (2). */
1061 in SFmode, DFmode and XFmode */
1063 in SFmode, DFmode and XFmode */
1066 in SImode and DImode */
1068 in SImode and DImode */
1071 in SImode, DImode and TImode */
1073 in SImode, DImode and TImode */
1075 /* On K8:
1076 MOVD reg64, xmmreg Double FSTORE 4
1077 MOVD reg32, xmmreg Double FSTORE 4
1078 On AMDFAM10:
1079 MOVD reg64, xmmreg Double FADD 3
1080 1/1 1/1
1081 MOVD reg32, xmmreg Double FADD 3
1082 1/1 1/1 */
1086 /* New AMD processors never drop prefetches; if they cannot be performed
1087 immediately, they are queued. We set number of simultaneous prefetches
1088 to a large constant to reflect this (it probably is not a good idea not
1089 to limit number of prefetches at all, as their execution also takes some
1090 time). */
1100 bdver2_memcpy,
1101 bdver2_memset,
1113 };
1116 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1117 very small blocks it is better to use loop. For large blocks, libcall
1118 can do nontemporary accesses and beat inline considerably. */
1151 in QImode, HImode and SImode.
1152 Relative to reg-reg move (2). */
1156 in SFmode, DFmode and XFmode */
1158 in SFmode, DFmode and XFmode */
1161 in SImode and DImode */
1163 in SImode and DImode */
1166 in SImode, DImode and TImode */
1168 in SImode, DImode and TImode */
1173 /* New AMD processors never drop prefetches; if they cannot be performed
1174 immediately, they are queued. We set number of simultaneous prefetches
1175 to a large constant to reflect this (it probably is not a good idea not
1176 to limit number of prefetches at all, as their execution also takes some
1177 time). */
1187 bdver3_memcpy,
1188 bdver3_memset,
1200 };
1202 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1203 very small blocks it is better to use loop. For large blocks, libcall
1204 can do nontemporary accesses and beat inline considerably. */
1237 in QImode, HImode and SImode.
1238 Relative to reg-reg move (2). */
1242 in SFmode, DFmode and XFmode */
1244 in SFmode, DFmode and XFmode */
1247 in SImode and DImode */
1249 in SImode and DImode */
1252 in SImode, DImode and TImode */
1254 in SImode, DImode and TImode */
1259 /* New AMD processors never drop prefetches; if they cannot be performed
1260 immediately, they are queued. We set number of simultaneous prefetches
1261 to a large constant to reflect this (it probably is not a good idea not
1262 to limit number of prefetches at all, as their execution also takes some
1263 time). */
1273 bdver4_memcpy,
1274 bdver4_memset,
1286 };
1288 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1289 very small blocks it is better to use loop. For large blocks, libcall can
1290 do nontemporary accesses and beat inline considerably. */
1323 in QImode, HImode and SImode.
1324 Relative to reg-reg move (2). */
1328 in SFmode, DFmode and XFmode */
1330 in SFmode, DFmode and XFmode */
1333 in SImode and DImode */
1335 in SImode and DImode */
1338 in SImode, DImode and TImode */
1340 in SImode, DImode and TImode */
1342 /* On K8:
1343 MOVD reg64, xmmreg Double FSTORE 4
1344 MOVD reg32, xmmreg Double FSTORE 4
1345 On AMDFAM10:
1346 MOVD reg64, xmmreg Double FADD 3
1347 1/1 1/1
1348 MOVD reg32, xmmreg Double FADD 3
1349 1/1 1/1 */
1362 btver1_memcpy,
1363 btver1_memset,
1375 };
1409 in QImode, HImode and SImode.
1410 Relative to reg-reg move (2). */
1414 in SFmode, DFmode and XFmode */
1416 in SFmode, DFmode and XFmode */
1419 in SImode and DImode */
1421 in SImode and DImode */
1424 in SImode, DImode and TImode */
1426 in SImode, DImode and TImode */
1428 /* On K8:
1429 MOVD reg64, xmmreg Double FSTORE 4
1430 MOVD reg32, xmmreg Double FSTORE 4
1431 On AMDFAM10:
1432 MOVD reg64, xmmreg Double FADD 3
1433 1/1 1/1
1434 MOVD reg32, xmmreg Double FADD 3
1435 1/1 1/1 */
1447 btver2_memcpy,
1448 btver2_memset,
1460 };
1464 DUMMY_STRINGOP_ALGS};
1468 DUMMY_STRINGOP_ALGS};
1470 static const
1493 in QImode, HImode and SImode.
1494 Relative to reg-reg move (2). */
1498 in SFmode, DFmode and XFmode */
1500 in SFmode, DFmode and XFmode */
1503 in SImode and DImode */
1505 in SImode and DImode */
1508 in SImode, DImode and TImode */
1510 in SImode, DImode and TImode */
1523 pentium4_memcpy,
1524 pentium4_memset,
1536 };
1549 static const
1572 in QImode, HImode and SImode.
1573 Relative to reg-reg move (2). */
1577 in SFmode, DFmode and XFmode */
1579 in SFmode, DFmode and XFmode */
1582 in SImode and DImode */
1584 in SImode and DImode */
1587 in SImode, DImode and TImode */
1589 in SImode, DImode and TImode */
1602 nocona_memcpy,
1603 nocona_memset,
1615 };
1626 static const
1649 in QImode, HImode and SImode.
1650 Relative to reg-reg move (2). */
1654 in SFmode, DFmode and XFmode */
1656 in SFmode, DFmode and XFmode */
1659 in SImode and DImode */
1661 in SImode and DImode */
1664 in SImode, DImode and TImode */
1666 in SImode, DImode and TImode */
1679 atom_memcpy,
1680 atom_memset,
1692 };
1703 static const
1726 in QImode, HImode and SImode.
1727 Relative to reg-reg move (2). */
1731 in SFmode, DFmode and XFmode */
1733 in SFmode, DFmode and XFmode */
1736 in SImode and DImode */
1738 in SImode and DImode */
1741 in SImode, DImode and TImode */
1743 in SImode, DImode and TImode */
1756 slm_memcpy,
1757 slm_memset,
1769 };
1780 static const
1803 in QImode, HImode and SImode.
1804 Relative to reg-reg move (2). */
1808 in SFmode, DFmode and XFmode */
1810 in SFmode, DFmode and XFmode */
1813 in SImode and DImode */
1815 in SImode and DImode */
1818 in SImode, DImode and TImode */
1820 in SImode, DImode and TImode */
1833 intel_memcpy,
1834 intel_memset,
1846 };
1848 /* Generic should produce code tuned for Core-i7 (and newer chips)
1849 and btver1 (and newer chips). */
1861 static const
1864 /* On all chips taken into consideration lea is 2 cycles and more. With
1865 this cost however our current implementation of synth_mult results in
1866 use of unnecessary temporary registers causing regression on several
1867 SPECfp benchmarks. */
1888 in QImode, HImode and SImode.
1889 Relative to reg-reg move (2). */
1893 in SFmode, DFmode and XFmode */
1895 in SFmode, DFmode and XFmode */
1898 in SImode and DImode */
1900 in SImode and DImode */
1903 in SImode, DImode and TImode */
1905 in SImode, DImode and TImode */
1911 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1912 value is increased to perhaps more appropriate value of 5. */
1920 generic_memcpy,
1921 generic_memset,
1933 };
1935 /* core_cost should produce code tuned for Core familly of CPUs. */
1948 static const
1951 /* On all chips taken into consideration lea is 2 cycles and more. With
1952 this cost however our current implementation of synth_mult results in
1953 use of unnecessary temporary registers causing regression on several
1954 SPECfp benchmarks. */
1975 in QImode, HImode and SImode.
1976 Relative to reg-reg move (2). */
1980 in SFmode, DFmode and XFmode */
1982 in SFmode, DFmode and XFmode */
1985 in SImode and DImode */
1987 in SImode and DImode */
1990 in SImode, DImode and TImode */
1992 in SImode, DImode and TImode */
1998 /* FIXME perhaps more appropriate value is 5. */
2006 core_memcpy,
2007 core_memset,
2019 };
2022 /* Set by -mtune. */
2025 /* Set by -mtune or -Os. */
2028 /* Processor feature/optimization bitmasks. */
2029 #define m_386 (1<<PROCESSOR_I386)
2030 #define m_486 (1<<PROCESSOR_I486)
2031 #define m_PENT (1<<PROCESSOR_PENTIUM)
2032 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2033 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2034 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2035 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2036 #define m_CORE2 (1<<PROCESSOR_CORE2)
2037 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2038 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2039 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2040 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2041 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2042 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2043 #define m_KNL (1<<PROCESSOR_KNL)
2044 #define m_INTEL (1<<PROCESSOR_INTEL)
2046 #define m_GEODE (1<<PROCESSOR_GEODE)
2047 #define m_K6 (1<<PROCESSOR_K6)
2048 #define m_K6_GEODE (m_K6 | m_GEODE)
2049 #define m_K8 (1<<PROCESSOR_K8)
2050 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2051 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2052 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2053 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2054 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2055 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2056 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2057 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2058 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2059 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2060 #define m_BTVER (m_BTVER1 | m_BTVER2)
2061 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2063 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2066 #undef DEF_TUNE
2067 #define DEF_TUNE(tune, name, selector) name,
2069 #undef DEF_TUNE
2070 };
2072 /* Feature tests against the various tunings. */
2075 /* Feature tests against the various tunings used to create ix86_tune_features
2076 based on the processor mask. */
2078 #undef DEF_TUNE
2079 #define DEF_TUNE(tune, name, selector) selector,
2081 #undef DEF_TUNE
2082 };
2084 /* Feature tests against the various architecture variations. */
2087 /* Feature tests against the various architecture variations, used to create
2088 ix86_arch_features based on the processor mask. */
2090 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2093 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2096 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2099 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2102 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2104 };
2106 /* In case the average insn count for single function invocation is
2107 lower than this constant, emit fast (but longer) prologue and
2108 epilogue code. */
2109 #define FAST_PROLOGUE_INSN_COUNT 20
2111 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2116 /* Array of the smallest class containing reg number REGNO, indexed by
2117 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2120 {
2121 /* ax, dx, cx, bx */
2123 /* si, di, bp, sp */
2125 /* FP registers */
2128 /* arg pointer */
2129 NON_Q_REGS,
2130 /* flags, fpsr, fpcr, frame */
2132 /* SSE registers */
2135 /* MMX registers */
2138 /* REX registers */
2141 /* SSE REX registers */
2144 /* AVX-512 SSE registers */
2149 /* Mask registers. */
2152 /* MPX bound registers */
2154 };
2156 /* The "default" register map used in 32bit mode. */
2159 {
2171 };
2173 /* The "default" register map used in 64bit mode. */
2176 {
2188 };
2190 /* Define the register numbers to be used in Dwarf debugging information.
2191 The SVR4 reference port C compiler uses the following register numbers
2192 in its Dwarf output code:
2193 0 for %eax (gcc regno = 0)
2194 1 for %ecx (gcc regno = 2)
2195 2 for %edx (gcc regno = 1)
2196 3 for %ebx (gcc regno = 3)
2197 4 for %esp (gcc regno = 7)
2198 5 for %ebp (gcc regno = 6)
2199 6 for %esi (gcc regno = 4)
2200 7 for %edi (gcc regno = 5)
2201 The following three DWARF register numbers are never generated by
2202 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2203 believes these numbers have these meanings.
2204 8 for %eip (no gcc equivalent)
2205 9 for %eflags (gcc regno = 17)
2206 10 for %trapno (no gcc equivalent)
2207 It is not at all clear how we should number the FP stack registers
2208 for the x86 architecture. If the version of SDB on x86/svr4 were
2209 a bit less brain dead with respect to floating-point then we would
2210 have a precedent to follow with respect to DWARF register numbers
2211 for x86 FP registers, but the SDB on x86/svr4 is so completely
2212 broken with respect to FP registers that it is hardly worth thinking
2213 of it as something to strive for compatibility with.
2214 The version of x86/svr4 SDB I have at the moment does (partially)
2215 seem to believe that DWARF register number 11 is associated with
2216 the x86 register %st(0), but that's about all. Higher DWARF
2217 register numbers don't seem to be associated with anything in
2218 particular, and even for DWARF regno 11, SDB only seems to under-
2219 stand that it should say that a variable lives in %st(0) (when
2220 asked via an `=' command) if we said it was in DWARF regno 11,
2221 but SDB still prints garbage when asked for the value of the
2222 variable in question (via a `/' command).
2223 (Also note that the labels SDB prints for various FP stack regs
2224 when doing an `x' command are all wrong.)
2225 Note that these problems generally don't affect the native SVR4
2226 C compiler because it doesn't allow the use of -O with -g and
2227 because when it is *not* optimizing, it allocates a memory
2228 location for each floating-point variable, and the memory
2229 location is what gets described in the DWARF AT_location
2230 attribute for the variable in question.
2231 Regardless of the severe mental illness of the x86/svr4 SDB, we
2232 do something sensible here and we use the following DWARF
2233 register numbers. Note that these are all stack-top-relative
2234 numbers.
2235 11 for %st(0) (gcc regno = 8)
2236 12 for %st(1) (gcc regno = 9)
2237 13 for %st(2) (gcc regno = 10)
2238 14 for %st(3) (gcc regno = 11)
2239 15 for %st(4) (gcc regno = 12)
2240 16 for %st(5) (gcc regno = 13)
2241 17 for %st(6) (gcc regno = 14)
2242 18 for %st(7) (gcc regno = 15)
2243 */
2245 {
2257 };
2259 /* Define parameter passing and return registers. */
2262 {
2264 };
2267 {
2269 };
2272 {
2274 };
2276 /* Additional registers that are clobbered by SYSV calls. */
2279 {
2284 };
2286 /* Define the structure for the machine field in struct function. */
2291 rtx rtl;
2293 };
2295 /* Structure describing stack frame layout.
2296 Stack grows downward:
2298 [arguments]
2299 <- ARG_POINTER
2300 saved pc
2302 saved static chain if ix86_static_chain_on_stack
2304 saved frame pointer if frame_pointer_needed
2305 <- HARD_FRAME_POINTER
2306 [saved regs]
2307 <- regs_save_offset
2308 [padding0]
2310 [saved SSE regs]
2311 <- sse_regs_save_offset
2312 [padding1] |
2313 | <- FRAME_POINTER
2314 [va_arg registers] |
2315 |
2316 [frame] |
2317 |
2318 [padding2] | = to_allocate
2319 <- STACK_POINTER
2320 */
2321 struct ix86_frame
2322 {
2329 /* The offsets relative to ARG_POINTER. */
2330 HOST_WIDE_INT frame_pointer_offset;
2331 HOST_WIDE_INT hard_frame_pointer_offset;
2332 HOST_WIDE_INT stack_pointer_offset;
2333 HOST_WIDE_INT hfp_save_offset;
2334 HOST_WIDE_INT reg_save_offset;
2335 HOST_WIDE_INT sse_reg_save_offset;
2337 /* When save_regs_using_mov is set, emit prologue using
2338 move instead of push instructions. */
2340 };
2342 /* Which cpu are we scheduling for. */
2345 /* Which cpu are we optimizing for. */
2348 /* Which instruction set architecture to use. */
2351 /* True if processor has SSE prefetch instruction. */
2354 /* -mstackrealign option */
2371 /* Preferred alignment for stack boundary in bits. */
2374 /* Alignment for incoming stack boundary in bits specified at
2375 command line. */
2378 /* Default alignment for incoming stack boundary in bits. */
2381 /* Alignment for incoming stack boundary in bits. */
2384 /* Calling abi specific va_list type nodes. */
2388 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2392 /* Fence to use after loop using movnt. */
2393 tree x86_mfence;
2395 /* Register class used for passing given 64bit part of the argument.
2396 These represent classes as documented by the PS ABI, with the exception
2397 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2398 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2400 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2401 whenever possible (upper half does contain padding). */
2402 enum x86_64_reg_class
2403 {
2404 X86_64_NO_CLASS,
2405 X86_64_INTEGER_CLASS,
2406 X86_64_INTEGERSI_CLASS,
2407 X86_64_SSE_CLASS,
2408 X86_64_SSESF_CLASS,
2409 X86_64_SSEDF_CLASS,
2410 X86_64_SSEUP_CLASS,
2411 X86_64_X87_CLASS,
2412 X86_64_X87UP_CLASS,
2413 X86_64_COMPLEX_X87_CLASS,
2414 X86_64_MEMORY_CLASS
2415 };
2417 #define MAX_CLASSES 8
2419 /* Table of constants used by fldpi, fldln2, etc.... */
2423 \f
2428 const_tree);
2440 enum ix86_function_specific_strings
2441 {
2442 IX86_FUNCTION_SPECIFIC_ARCH,
2443 IX86_FUNCTION_SPECIFIC_TUNE,
2444 IX86_FUNCTION_SPECIFIC_MAX
2445 };
2466 \f
2467 #ifndef SUBTARGET32_DEFAULT_CPU
2469 #endif
2471 /* Whether -mtune= or -march= were specified */
2475 /* Vectorization library interface and handlers. */
2481 /* Processor target table, indexed by processor number */
2482 struct ptt
2483 {
2491 };
2493 /* This table must be in sync with enum processor_type in i386.h. */
2495 {
2522 };
2523 \f
2524 static unsigned int
2526 {
2529 /* vzeroupper instructions are inserted immediately after reload to
2530 account for possible spills from 256bit registers. The pass
2531 reuses mode switching infrastructure by re-running mode insertion
2532 pass, so disable entities that have already been processed. */
2538 /* Call optimize_mode_switching. */
2541 }
2546 {
2556 };
2559 {
2563 {}
2565 /* opt_pass methods: */
2567 {
2569 }
2572 {
2574 }
2580 rtl_opt_pass *
2582 {
2584 }
2586 /* Return true if a red-zone is in use. */
2590 {
2592 }
2593 \f
2594 /* Return a string that documents the current -m options. The caller is
2595 responsible for freeing the string. */
2601 {
2602 struct ix86_target_opts
2603 {
2606 };
2608 /* This table is ordered so that options like -msse4.2 that imply
2609 preceding options while match those first. */
2611 {
2664 };
2666 /* Flag options. */
2668 {
2697 };
2714 /* Add -march= option. */
2716 {
2719 }
2721 /* Add -mtune= option. */
2723 {
2726 }
2728 /* Add -m32/-m64/-mx32. */
2730 {
2733 else
2735 isa &= ~ (OPTION_MASK_ISA_64BIT
2736 | OPTION_MASK_ABI_64
2738 }
2739 else
2743 /* Pick out the options in isa options. */
2745 {
2747 {
2750 }
2751 }
2754 {
2757 isa);
2758 }
2760 /* Add flag options. */
2762 {
2764 {
2767 }
2768 }
2771 {
2774 }
2776 /* Add -fpmath= option. */
2778 {
2781 {
2796 }
2797 }
2799 /* Any options? */
2805 /* Size the string. */
2809 {
2814 }
2816 /* Build the string. */
2821 {
2828 {
2830 line_len++;
2833 {
2837 }
2838 }
2842 {
2846 }
2847 }
2853 }
2855 /* Return true, if profiling code should be emitted before
2856 prologue. Otherwise it returns false.
2857 Note: For x86 with "hotfix" it is sorried. */
2858 static bool
2860 {
2862 }
2864 /* Function that is callable from the debugger to print the current
2865 options. */
2866 void ATTRIBUTE_UNUSED
2868 {
2874 {
2877 }
2878 else
2882 }
2885 #define DEF_ENUM
2886 #define DEF_ALG(alg, name) #name,
2888 #undef DEF_ENUM
2889 #undef DEF_ALG
2890 };
2892 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2893 The string is of the following form (or comma separated list of it):
2895 strategy_alg:max_size:[align|noalign]
2897 where the full size range for the strategy is either [0, max_size] or
2898 [min_size, max_size], in which min_size is the max_size + 1 of the
2899 preceding range. The last size range must have max_size == -1.
2901 Examples:
2903 1.
2904 -mmemcpy-strategy=libcall:-1:noalign
2906 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2909 2.
2910 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2912 This is to tell the compiler to use the following strategy for memset
2913 1) when the expected size is between [1, 16], use rep_8byte strategy;
2914 2) when the size is between [17, 2048], use vector_loop;
2915 3) when the size is > 2048, use libcall. */
2917 struct stringop_size_range
2918 {
2920 stringop_alg alg;
2922 };
2924 static void
2926 {
2934 else
2939 do
2940 {
2950 {
2954 }
2957 {
2961 }
2968 {
2970 alg_name,
2973 }
2981 else
2982 {
2986 }
2987 n++;
2989 }
2993 {
2998 }
3001 {
3005 }
3007 /* Now override the default algs array. */
3009 {
3015 }
3016 }
3018 \f
3019 /* parse -mtune-ctrl= option. When DUMP is true,
3020 print the features that are explicitly set. */
3022 static void
3024 {
3032 do
3033 {
3040 {
3041 curr_feature_string++;
3043 }
3045 {
3047 {
3053 }
3054 }
3059 }
3062 }
3064 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3065 processor type. */
3067 static void
3069 {
3074 {
3077 else
3079 }
3082 {
3087 }
3090 }
3093 /* Override various settings based on options. If MAIN_ARGS_P, the
3094 options are from the command line, otherwise they are from
3095 attributes. */
3097 static void
3101 {
3109 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3110 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3111 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3112 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3113 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3114 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3115 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3116 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3117 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3118 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3119 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3120 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3121 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3122 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3123 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3124 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3125 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3126 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3127 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3128 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3129 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3130 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3131 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3132 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3133 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3134 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3135 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3136 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3137 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3138 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3139 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3140 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3141 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3142 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3143 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3144 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3145 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3146 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3147 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3148 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3149 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3150 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3151 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3152 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3153 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3154 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3155 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3156 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3157 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3158 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3159 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3160 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3161 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3162 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3163 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3164 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3165 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3167 #define PTA_CORE2 \
3168 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3169 | PTA_CX16 | PTA_FXSR)
3170 #define PTA_NEHALEM \
3171 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3172 #define PTA_WESTMERE \
3173 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3174 #define PTA_SANDYBRIDGE \
3175 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3176 #define PTA_IVYBRIDGE \
3177 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3178 #define PTA_HASWELL \
3179 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3180 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3181 #define PTA_BROADWELL \
3182 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3183 #define PTA_KNL \
3184 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3185 #define PTA_BONNELL \
3186 (PTA_CORE2 | PTA_MOVBE)
3187 #define PTA_SILVERMONT \
3188 (PTA_WESTMERE | PTA_MOVBE)
3190 /* if this reaches 64, need to widen struct pta flags below */
3192 static struct pta
3193 {
3198 }
3200 {
3234 PTA_SANDYBRIDGE},
3236 PTA_SANDYBRIDGE},
3238 PTA_IVYBRIDGE},
3240 PTA_IVYBRIDGE},
3332 PTA_64BIT
3334 };
3336 /* -mrecip options. */
3337 static struct
3338 {
3341 }
3343 {
3350 };
3354 /* Set up prefix/suffix so the error messages refer to either the command
3355 line argument, or the attribute(target). */
3357 {
3361 }
3362 else
3363 {
3367 }
3369 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3370 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3373 #ifdef TARGET_BI_ARCH
3374 else
3375 {
3376 #if TARGET_BI_ARCH == 1
3377 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3378 is on and OPTION_MASK_ABI_X32 is off. We turn off
3379 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3380 -mx32. */
3383 #else
3384 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3385 on and OPTION_MASK_ABI_64 is off. We turn off
3386 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3387 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3391 #endif
3392 }
3393 #endif
3396 {
3397 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3398 OPTION_MASK_ABI_64 for TARGET_X32. */
3401 }
3404 | OPTION_MASK_ABI_X32
3407 {
3408 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3409 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3412 }
3414 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3415 SUBTARGET_OVERRIDE_OPTIONS;
3416 #endif
3418 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3419 SUBSUBTARGET_OVERRIDE_OPTIONS;
3420 #endif
3422 /* -fPIC is the default for x86_64. */
3426 /* Need to check -mtune=generic first. */
3428 {
3429 /* As special support for cross compilers we read -mtune=native
3430 as -mtune=generic. With native compilers we won't see the
3431 -mtune=native, as it was changed by the driver. */
3433 {
3435 }
3440 }
3441 else
3442 {
3446 {
3447 opts->x_ix86_tune_string
3450 }
3452 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3453 or defaulted. We need to use a sensible tune option. */
3455 {
3457 }
3458 }
3462 {
3463 /* rep; movq isn't available in 32-bit code. */
3466 }
3469 opts->x_ix86_arch_string
3472 else
3476 {
3484 }
3485 else
3492 /* For targets using ms ABI enable ms-extensions, if not
3493 explicit turned off. For non-ms ABI we turn off this
3494 option. */
3499 {
3501 {
3545 {
3548 }
3556 }
3557 }
3558 else
3559 {
3560 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3561 use of rip-relative addressing. This eliminates fixups that
3562 would otherwise be needed if this object is to be placed in a
3563 DLL, and is essentially just as efficient as direct addressing. */
3569 else
3571 }
3573 {
3576 }
3584 {
3587 /* Default cpu tuning to the architecture. */
3765 }
3789 {
3793 {
3795 {
3797 {
3805 }
3806 else
3809 }
3810 }
3811 /* Intel CPUs have always interpreted SSE prefetch instructions as
3812 NOPs; so, we can enable SSE prefetch instructions even when
3813 -mtune (rather than -march) points us to a processor that has them.
3814 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3815 higher processors. */
3820 }
3828 #ifndef USE_IX86_FRAME_POINTER
3829 #define USE_IX86_FRAME_POINTER 0
3830 #endif
3832 #ifndef USE_X86_64_FRAME_POINTER
3833 #define USE_X86_64_FRAME_POINTER 0
3834 #endif
3836 /* Set the default values for switches whose default depends on TARGET_64BIT
3837 in case they weren't overwritten by command line options. */
3839 {
3847 opts->x_flag_unwind_tables
3851 }
3852 else
3853 {
3855 opts->x_flag_omit_frame_pointer
3861 }
3866 else
3869 /* Arrange to set up i386_stack_locals for all functions. */
3872 /* Validate -mregparm= value. */
3874 {
3878 {
3882 }
3883 }
3887 /* Default align_* from the processor table. */
3889 {
3892 }
3894 {
3897 }
3899 {
3901 }
3903 /* Provide default for -mbranch-cost= value. */
3908 {
3909 opts->x_target_flags
3912 /* Enable by default the SSE and MMX builtins. Do allow the user to
3913 explicitly disable any of these. In particular, disabling SSE and
3914 MMX for kernel code is extremely useful. */
3916 opts->x_ix86_isa_flags
3923 }
3924 else
3925 {
3926 opts->x_target_flags
3930 opts->x_ix86_isa_flags
3933 /* i386 ABI does not specify red zone. It still makes sense to use it
3934 when programmer takes care to stack from being destroyed. */
3937 }
3939 /* Keep nonleaf frame pointers. */
3945 /* If we're doing fast math, we don't care about comparison order
3946 wrt NaNs. This lets us use a shorter comparison sequence. */
3950 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3951 since the insns won't need emulation. */
3955 /* Likewise, if the target doesn't have a 387, or we've specified
3956 software floating point, don't use 387 inline intrinsics. */
3960 /* Turn on MMX builtins for -msse. */
3962 opts->x_ix86_isa_flags
3965 /* Enable SSE prefetch. */
3970 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3973 opts->x_ix86_isa_flags
3976 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3979 opts->x_ix86_isa_flags
3982 /* Enable lzcnt instruction for -mabm. */
3984 opts->x_ix86_isa_flags
3987 /* Validate -mpreferred-stack-boundary= value or default it to
3988 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3991 {
3998 {
4002 else
4005 }
4006 else
4007 ix86_preferred_stack_boundary
4009 }
4011 /* Set the default value for -mstackrealign. */
4017 /* Validate -mincoming-stack-boundary= value or default it to
4018 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4021 {
4028 else
4029 {
4030 ix86_user_incoming_stack_boundary
4032 ix86_incoming_stack_boundary
4034 }
4035 }
4037 #ifndef NO_PROFILE_COUNTERS
4040 #endif
4044 /* Accept -msseregparm only if at least SSE support is enabled. */
4050 {
4052 {
4054 {
4057 }
4060 {
4063 }
4064 }
4065 }
4066 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4067 fpmath=387. The second is however default at many targets since the
4068 extra 80bit precision of temporaries is considered to be part of ABI.
4069 Overwrite the default at least for -ffast-math.
4070 TODO: -mfpmath=both seems to produce same performing code with bit
4071 smaller binaries. It is however not clear if register allocation is
4072 ready for this setting.
4073 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4074 codegen. We may switch to 387 with -ffast-math for size optimized
4075 functions. */
4079 else
4082 /* If the i387 is disabled, then do not return values in it. */
4086 /* Use external vectorized library in vectorizing intrinsics. */
4089 {
4100 }
4107 /* If stack probes are required, the space used for large function
4108 arguments on the stack must also be probed, so enable
4109 -maccumulate-outgoing-args so this happens in the prologue. */
4112 {
4117 }
4119 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4120 {
4126 }
4128 /* When scheduling description is not available, disable scheduler pass
4129 so it won't slow down the compilation and make x87 code slower. */
4150 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4152 && HAVE_prefetch
4157 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4158 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4163 {
4166 {
4168 ix86_gen_tls_local_dynamic_base_64
4170 }
4171 else
4172 {
4174 ix86_gen_tls_local_dynamic_base_64
4176 }
4177 }
4178 else
4182 {
4192 }
4193 else
4194 {
4204 }
4206 #ifdef USE_IX86_CLD
4207 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4210 #endif
4213 {
4218 }
4220 {
4224 }
4226 {
4227 #if defined(PROFILE_BEFORE_PROLOGUE)
4229 #else
4231 #endif
4232 }
4234 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4235 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4236 AVX unaligned load/store. */
4238 {
4248 /* Enable 128-bit AVX instruction generation
4249 for the auto-vectorizer. */
4253 }
4256 {
4263 {
4266 {
4268 q++;
4269 }
4270 else
4275 else
4276 {
4279 {
4282 }
4285 {
4289 }
4290 }
4295 else
4297 }
4298 }
4305 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4306 for 64-bit Bionic. */
4311 ? MASK_LONG_DOUBLE_128
4314 /* Only one of them can be active. */
4318 /* Save the initial options in case the user does function specific
4319 options. */
4321 target_option_default_node = target_option_current_node
4324 /* Handle stack protector */
4326 opts->x_ix86_stack_protector_guard
4329 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4331 {
4335 }
4338 {
4342 }
4343 }
4345 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4347 static void
4349 {
4351 struct register_pass_info insert_vzeroupper_info
4354 };
4359 /* This needs to be done at start up. It's convenient to do it here. */
4361 }
4363 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4366 {
4370 }
4372 /* Update register usage after having seen the compiler flags. */
4374 static void
4376 {
4380 /* The PIC register, if it exists, is fixed. */
4385 /* For 32-bit targets, squash the REX registers. */
4387 {
4394 }
4396 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4404 {
4405 /* Set/reset conditionally defined registers from
4406 CALL_USED_REGISTERS initializer. */
4410 /* Calculate registers of CLOBBERED_REGS register set
4411 as call used registers from GENERAL_REGS register set. */
4415 }
4417 /* If MMX is disabled, squash the registers. */
4423 /* If SSE is disabled, squash the registers. */
4429 /* If the FPU is disabled, squash the registers. */
4435 /* If AVX512F is disabled, squash the registers. */
4437 {
4443 }
4445 /* If MPX is disabled, squash the registers. */
4449 }
4451 \f
4452 /* Save the current options */
4454 static void
4457 {
4492 /* The fields are char but the variables are not; make sure the
4493 values fit in the fields. */
4498 }
4500 /* Restore the current options */
4502 static void
4505 {
4511 /* We don't change -fPIC. */
4548 /* Recreate the arch feature tests if the arch changed */
4550 {
4555 }
4557 /* Recreate the tune optimization tests */
4560 }
4562 /* Print the current options */
4564 static void
4567 {
4585 {
4588 }
4589 }
4591 \f
4592 /* Inner function to process the attribute((target(...))), take an argument and
4593 set the current options from the argument. If we have a list, recursively go
4594 over the list. */
4596 static bool
4601 {
4605 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4606 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4607 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4608 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4609 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4611 enum ix86_opt_type
4612 {
4613 ix86_opt_unknown,
4614 ix86_opt_yes,
4615 ix86_opt_no,
4616 ix86_opt_str,
4617 ix86_opt_enum,
4618 ix86_opt_isa
4619 };
4621 static const struct
4622 {
4629 /* isa options */
4682 /* enum options */
4685 /* string options */
4689 /* flag options */
4691 OPT_mcld,
4692 MASK_CLD),
4695 OPT_mfancy_math_387,
4696 MASK_NO_FANCY_MATH_387),
4699 OPT_mieee_fp,
4700 MASK_IEEE_FP),
4703 OPT_minline_all_stringops,
4704 MASK_INLINE_ALL_STRINGOPS),
4707 OPT_minline_stringops_dynamically,
4708 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4711 OPT_mno_align_stringops,
4712 MASK_NO_ALIGN_STRINGOPS),
4715 OPT_mrecip,
4716 MASK_RECIP),
4718 };
4720 /* If this is a list, recurse to get the options. */
4722 {
4729 enum_opts_set))
4733 }
4736 {
4739 }
4741 /* Handle multiple arguments separated by commas. */
4745 {
4759 {
4763 }
4764 else
4765 {
4768 }
4770 /* Recognize no-xxx. */
4772 {
4776 }
4777 else
4780 /* Find the option. */
4784 {
4792 {
4797 }
4798 }
4800 /* Process the option. */
4802 {
4805 }
4808 {
4814 }
4817 {
4823 else
4825 }
4828 {
4830 {
4833 }
4834 else
4836 }
4839 {
4847 global_dc);
4848 else
4849 {
4852 }
4853 }
4855 else
4857 }
4860 }
4862 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4864 tree
4868 {
4883 /* Process each of the options on the chain. */
4888 /* If the changed options are different from the default, rerun
4889 ix86_option_override_internal, and then save the options away.
4890 The string options are are attribute options, and will be undone
4891 when we copy the save structure. */
4897 {
4898 /* If we are using the default tune= or arch=, undo the string assigned,
4899 and use the default. */
4910 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4915 {
4918 }
4920 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4923 /* Add any builtin functions with the new isa if any. */
4926 /* Save the current options unless we are validating options for
4927 #pragma. */
4934 /* Free up memory allocated to hold the strings */
4937 }
4940 }
4942 /* Hook to validate attribute((target("string"))). */
4944 static bool
4947 tree args,
4949 {
4954 /* attribute((target("default"))) does nothing, beyond
4955 affecting multi-versioning. */
4964 /* Get the optimization options of the current function. */
4970 /* Init func_options. */
4978 /* Initialize func_options to the default before its target options can
4979 be set. */
4992 {
4997 }
5000 }
5002 \f
5003 /* Hook to determine if one function can safely inline another. */
5005 static bool
5007 {
5012 /* If callee has no option attributes, then it is ok to inline. */
5016 /* If caller has no option attributes, but callee does then it is not ok to
5017 inline. */
5021 else
5022 {
5026 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5027 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5028 function. */
5033 /* See if we have the same non-isa options. */
5037 /* See if arch, tune, etc. are the same. */
5050 else
5052 }
5055 }
5057 \f
5058 /* Remember the last target of ix86_set_current_function. */
5061 /* Set target globals to default. */
5063 static void
5065 {
5066 tree old_tree = (ix86_previous_fndecl
5071 {
5079 else
5082 }
5083 }
5085 /* Invalidate ix86_previous_fndecl cache. */
5086 void
5088 {
5091 }
5093 /* Establish appropriate back-end context for processing the function
5094 FNDECL. The argument might be NULL to indicate processing at top
5095 level, outside of any function scope. */
5096 static void
5098 {
5099 /* Only change the context if the function changes. This hook is called
5100 several times in the course of compiling a function, and we don't want to
5101 slow things down too much or call target_reinit when it isn't safe. */
5103 {
5104 tree old_tree = (ix86_previous_fndecl
5108 tree new_tree = (fndecl
5113 ;
5116 {
5121 else
5124 }
5129 }
5130 }
5132 \f
5133 /* Return true if this goes in large data/bss. */
5135 static bool
5137 {
5141 /* Functions are never large data. */
5145 /* Automatic variables are never large data. */
5150 {
5156 }
5157 else
5158 {
5161 /* If this is an incomplete type with size 0, then we can't put it
5162 in data because it might be too big when completed. Also,
5163 int_size_in_bytes returns -1 if size can vary or is larger than
5164 an integer in which case also it is safer to assume that it goes in
5165 large data. */
5168 }
5171 }
5173 /* Switch to the appropriate section for output of DECL.
5174 DECL is either a `VAR_DECL' node or a constant of some sort.
5175 RELOC indicates whether forming the initial value of DECL requires
5176 link-time relocations. */
5181 {
5183 {
5187 {
5221 /* We don't split these for medium model. Place them into
5222 default sections and hope for best. */
5224 }
5226 {
5227 /* We might get called with string constants, but get_named_section
5228 doesn't like them as they are not DECLs. Also, we need to set
5229 flags in that case. */
5233 }
5234 }
5236 }
5238 /* Select a set of attributes for section NAME based on the properties
5239 of DECL and whether or not RELOC indicates that DECL's initializer
5240 might contain runtime relocations. */
5242 static unsigned int ATTRIBUTE_UNUSED
5244 {
5258 }
5260 /* Build up a unique section name, expressed as a
5261 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5262 RELOC indicates whether the initial value of EXP requires
5263 link-time relocations. */
5265 static void ATTRIBUTE_UNUSED
5267 {
5269 {
5271 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5275 {
5299 /* We don't split these for medium model. Place them into
5300 default sections and hope for best. */
5302 }
5304 {
5311 /* If we're using one_only, then there needs to be a .gnu.linkonce
5312 prefix to the section name. */
5319 }
5320 }
5322 }
5324 #ifdef COMMON_ASM_OP
5325 /* This says how to output assembler code to declare an
5326 uninitialized external linkage data object.
5328 For medium model x86-64 we need to use .largecomm opcode for
5329 large objects. */
5330 void
5334 {
5338 else
5343 }
5344 #endif
5346 /* Utility function for targets to use in implementing
5347 ASM_OUTPUT_ALIGNED_BSS. */
5349 void
5352 {
5356 else
5359 #ifdef ASM_DECLARE_OBJECT_NAME
5362 #else
5363 /* Standard thing is just output label for the object. */
5367 }
5368 \f
5369 /* Decide whether we must probe the stack before any space allocation
5370 on this target. It's essentially TARGET_STACK_PROBE except when
5371 -fstack-check causes the stack to be already probed differently. */
5373 bool
5375 {
5376 /* Do not probe the stack twice if static stack checking is enabled. */
5381 }
5382 \f
5383 /* Decide whether we can make a sibling call to a function. DECL is the
5384 declaration of the function being targeted by the call and EXP is the
5385 CALL_EXPR representing the call. */
5387 static bool
5389 {
5393 /* If we are generating position-independent code, we cannot sibcall
5394 optimize any indirect call, or a direct call to a global function,
5395 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5397 && !TARGET_64BIT
5398 && flag_pic
5402 /* If we need to align the outgoing stack, then sibcalling would
5403 unalign the stack, which may break the called function. */
5409 {
5412 }
5413 else
5414 {
5415 /* We're looking at the CALL_EXPR, we need the type of the function. */
5420 }
5422 /* Check that the return value locations are the same. Like
5423 if we are returning floats on the 80387 register stack, we cannot
5424 make a sibcall from a function that doesn't return a float to a
5425 function that does or, conversely, from a function that does return
5426 a float to a function that doesn't; the necessary stack adjustment
5427 would not be executed. This is also the place we notice
5428 differences in the return value ABI. Note that it is ok for one
5429 of the functions to have void return type as long as the return
5430 value of the other is passed in a register. */
5435 {
5438 }
5440 ;
5445 {
5446 /* The SYSV ABI has more call-clobbered registers;
5447 disallow sibcalls from MS to SYSV. */
5451 }
5452 else
5453 {
5454 /* If this call is indirect, we'll need to be able to use a
5455 call-clobbered register for the address of the target function.
5456 Make sure that all such registers are not used for passing
5457 parameters. Note that DLLIMPORT functions are indirect. */
5460 {
5462 {
5463 /* ??? Need to count the actual number of registers to be used,
5464 not the possible number of registers. Fix later. */
5466 }
5467 }
5468 }
5470 /* Otherwise okay. That also includes certain types of indirect calls. */
5472 }
5474 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5475 and "sseregparm" calling convention attributes;
5476 arguments as in struct attribute_spec.handler. */
5478 static tree
5480 tree args,
5483 {
5486 {
5488 name);
5491 }
5493 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5495 {
5496 tree cst;
5499 {
5501 }
5504 {
5506 }
5510 {
5513 name);
5515 }
5517 {
5521 }
5524 }
5527 {
5528 /* Do not warn when emulating the MS ABI. */
5533 name);
5536 }
5538 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5540 {
5542 {
5544 }
5546 {
5548 }
5550 {
5552 }
5554 {
5556 }
5557 }
5559 /* Can combine stdcall with fastcall (redundant), regparm and
5560 sseregparm. */
5562 {
5564 {
5566 }
5568 {
5570 }
5572 {
5574 }
5575 }
5577 /* Can combine cdecl with regparm and sseregparm. */
5579 {
5581 {
5583 }
5585 {
5587 }
5589 {
5591 }
5592 }
5594 {
5597 name);
5599 {
5601 }
5603 {
5605 }
5607 {
5609 }
5610 }
5612 /* Can combine sseregparm with all attributes. */
5615 }
5617 /* The transactional memory builtins are implicitly regparm or fastcall
5618 depending on the ABI. Override the generic do-nothing attribute that
5619 these builtins were declared with, and replace it with one of the two
5620 attributes that we expect elsewhere. */
5622 static tree
5625 {
5626 tree alt;
5628 /* In no case do we want to add the placeholder attribute. */
5631 /* The 64-bit ABI is unchanged for transactional memory. */
5635 /* ??? Is there a better way to validate 32-bit windows? We have
5636 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5639 else
5640 {
5643 }
5646 else
5650 }
5652 /* This function determines from TYPE the calling-convention. */
5654 unsigned int
5656 {
5659 tree attrs;
5666 {
5676 /* Regparam isn't allowed for thiscall and fastcall. */
5678 {
5683 }
5687 }
5694 || is_stdarg
5700 }
5702 /* Return 0 if the attributes for two types are incompatible, 1 if they
5703 are compatible, and 2 if they are nearly compatible (which causes a
5704 warning to be generated). */
5706 static int
5708 {
5724 }
5725 \f
5726 /* Return the regparm value for a function with the indicated TYPE and DECL.
5727 DECL may be NULL when calling function indirectly
5728 or considering a libcall. */
5730 static int
5732 {
5733 tree attr;
5744 {
5747 {
5750 }
5751 }
5757 /* Use register calling convention for local functions when possible. */
5760 /* Caller and callee must agree on the calling convention, so
5761 checking here just optimize means that with
5762 __attribute__((optimize (...))) caller could use regparm convention
5763 and callee not, or vice versa. Instead look at whether the callee
5764 is optimized or not. */
5767 {
5768 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5771 {
5774 /* Make sure no regparm register is taken by a
5775 fixed register variable. */
5780 /* We don't want to use regparm(3) for nested functions as
5781 these use a static chain pointer in the third argument. */
5785 /* In 32-bit mode save a register for the split stack. */
5789 /* Each fixed register usage increases register pressure,
5790 so less registers should be used for argument passing.
5791 This functionality can be overriden by an explicit
5792 regparm value. */
5795 globals++;
5797 local_regparm
5802 }
5803 }
5806 }
5808 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5809 DFmode (2) arguments in SSE registers for a function with the
5810 indicated TYPE and DECL. DECL may be NULL when calling function
5811 indirectly or considering a libcall. Otherwise return 0. */
5813 static int
5815 {
5818 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5819 by the sseregparm attribute. */
5822 {
5824 {
5826 {
5830 else
5833 }
5835 }
5838 }
5840 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5841 (and DFmode for SSE2) arguments in SSE registers. */
5844 {
5845 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5849 }
5852 }
5854 /* Return true if EAX is live at the start of the function. Used by
5855 ix86_expand_prologue to determine if we need special help before
5856 calling allocate_stack_worker. */
5858 static bool
5860 {
5861 /* Cheat. Don't bother working forward from ix86_function_regparm
5862 to the function type to whether an actual argument is located in
5863 eax. Instead just look at cfg info, which is still close enough
5864 to correct at this point. This gives false positives for broken
5865 functions that might use uninitialized data that happens to be
5866 allocated in eax, but who cares? */
5868 }
5870 static bool
5872 {
5873 tree attr;
5876 {
5882 /* For 32-bit MS-ABI the default is to keep aggregate
5883 return pointer. */
5886 }
5888 }
5890 /* Value is the number of bytes of arguments automatically
5891 popped when returning from a subroutine call.
5892 FUNDECL is the declaration node of the function (as a tree),
5893 FUNTYPE is the data type of the function (as a tree),
5894 or for a library call it is an identifier node for the subroutine name.
5895 SIZE is the number of bytes of arguments passed on the stack.
5897 On the 80386, the RTD insn may be used to pop them if the number
5898 of args is fixed, but if the number is variable then the caller
5899 must pop them all. RTD can't be used for library calls now
5900 because the library is compiled with the Unix compiler.
5901 Use of RTD is a selectable option, since it is incompatible with
5902 standard Unix calling sequences. If the option is not selected,
5903 the caller must always pop the args.
5905 The attribute stdcall is equivalent to RTD on a per module basis. */
5907 static int
5909 {
5912 /* None of the 64-bit ABIs pop arguments. */
5923 /* Lose any fake structure return argument if it is passed on the stack. */
5926 {
5930 }
5933 }
5935 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5937 static bool
5939 {
5940 /* Check operand constraints in case hard registers were propagated
5941 into insn pattern. This check prevents combine pass from
5942 generating insn patterns with invalid hard register operands.
5943 These invalid insns can eventually confuse reload to error out
5944 with a spill failure. See also PRs 46829 and 46843. */
5946 {
5955 {
5963 /* For pre-AVX disallow unaligned loads/stores where the
5964 instructions don't support it. */
5968 {
5972 }
5974 /* A unary operator may be accepted by the predicate, but it
5975 is irrelevant for matching constraints. */
5980 {
5988 }
5995 /* Operand has no constraints, anything is OK. */
6000 {
6005 && operands_match_p
6009 {
6012 }
6013 }
6017 }
6018 }
6021 }
6022 \f
6023 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6025 static unsigned HOST_WIDE_INT
6027 {
6031 }
6032 \f
6033 /* Argument support functions. */
6035 /* Return true when register may be used to pass function parameters. */
6036 bool
6038 {
6043 {
6047 else
6053 }
6059 /* TODO: The function should depend on current function ABI but
6060 builtins.c would need updating then. Therefore we use the
6061 default ABI. */
6063 /* RAX is used as hidden argument to va_arg functions. */
6069 else
6076 }
6078 /* Return if we do not know how to pass TYPE solely in registers. */
6080 static bool
6082 {
6086 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6087 The layout_type routine is crafty and tries to trick us into passing
6088 currently unsupported vector types on the stack by using TImode. */
6091 }
6093 /* It returns the size, in bytes, of the area reserved for arguments passed
6094 in registers for the function represented by fndecl dependent to the used
6095 abi format. */
6096 int
6098 {
6102 else
6107 }
6109 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6110 call abi used. */
6111 enum calling_abi
6113 {
6115 {
6118 {
6121 }
6125 }
6127 }
6129 /* We add this as a workaround in order to use libc_has_function
6130 hook in i386.md. */
6131 bool
6133 {
6135 }
6137 static bool
6139 {
6141 {
6145 else
6147 }
6149 }
6151 static enum calling_abi
6153 {
6157 }
6159 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6160 call abi used. */
6161 enum calling_abi
6163 {
6167 }
6169 /* Write the extra assembler code needed to declare a function properly. */
6171 void
6173 tree decl)
6174 {
6178 {
6184 }
6186 #ifdef SUBTARGET_ASM_UNWIND_INIT
6188 #endif
6192 /* Output magic byte marker, if hot-patch attribute is set. */
6194 {
6196 {
6197 /* leaq [%rsp + 0], %rsp */
6200 }
6201 else
6202 {
6203 /* movl.s %edi, %edi
6204 push %ebp
6205 movl.s %esp, %ebp */
6208 }
6209 }
6210 }
6212 /* regclass.c */
6215 /* Implementation of call abi switching target hook. Specific to FNDECL
6216 the specific call register sets are set. See also
6217 ix86_conditional_register_usage for more details. */
6218 void
6220 {
6223 else
6225 }
6227 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6228 expensive re-initialization of init_regs each time we switch function context
6229 since this is needed only during RTL expansion. */
6230 static void
6232 {
6236 }
6238 /* Return 1 if pseudo register should be created and used to hold
6239 GOT address for PIC code. */
6240 static bool
6242 {
6249 }
6251 /* Initialize large model PIC register. */
6253 static void
6255 {
6257 rtx tmp_reg;
6266 label));
6270 }
6272 /* Create and initialize PIC register if required. */
6273 static void
6275 {
6276 edge entry_edge;
6285 {
6288 else
6290 }
6291 else
6292 {
6293 /* If there is future mcount call in the function it is more profitable
6294 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6303 }
6311 }
6313 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6314 for a call to a function whose data type is FNTYPE.
6315 For a library call, FNTYPE is 0. */
6317 void
6321 tree fndecl,
6323 {
6329 {
6332 }
6333 else
6334 {
6337 }
6341 /* Set up the number of registers to use for passing arguments. */
6344 {
6346 ? X86_64_REGPARM_MAX
6348 }
6350 {
6353 {
6355 ? X86_64_SSE_REGPARM_MAX
6357 }
6358 }
6366 /* Because type might mismatch in between caller and callee, we need to
6367 use actual type of function for local calls.
6368 FIXME: cgraph_analyze can be told to actually record if function uses
6369 va_start so for local functions maybe_vaarg can be made aggressive
6370 helping K&R code.
6371 FIXME: once typesytem is fixed, we won't need this code anymore. */
6384 {
6385 /* If there are variable arguments, then we won't pass anything
6386 in registers in 32-bit mode. */
6388 {
6397 }
6399 /* Use ecx and edx registers if function has fastcall attribute,
6400 else look for regparm information. */
6402 {
6405 {
6408 }
6410 {
6413 }
6414 else
6416 }
6418 /* Set up the number of SSE registers used for passing SFmode
6419 and DFmode arguments. Warn for mismatching ABI. */
6421 }
6422 }
6424 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6425 But in the case of vector types, it is some vector mode.
6427 When we have only some of our vector isa extensions enabled, then there
6428 are some modes for which vector_mode_supported_p is false. For these
6429 modes, the generic vector support in gcc will choose some non-vector mode
6430 in order to implement the type. By computing the natural mode, we'll
6431 select the proper ABI location for the operand and not depend on whatever
6432 the middle-end decides to do with these vector types.
6434 The midde-end can't deal with the vector types > 16 bytes. In this
6435 case, we return the original mode and warn ABI change if CUM isn't
6436 NULL.
6438 If INT_RETURN is true, warn ABI change if the vector mode isn't
6439 available for function return value. */
6441 static machine_mode
6444 {
6448 {
6451 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6453 {
6458 else
6461 /* Get the mode which has this inner mode and number of units. */
6465 {
6467 {
6472 {
6476 }
6478 {
6482 }
6485 }
6487 {
6492 {
6496 }
6498 {
6502 }
6505 }
6508 {
6513 {
6517 }
6519 {
6523 }
6524 }
6526 {
6531 {
6535 }
6537 {
6541 }
6542 }
6544 }
6547 }
6548 }
6551 }
6553 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6554 this may not agree with the mode that the type system has chosen for the
6555 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6556 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6558 static rtx
6561 {
6562 rtx tmp;
6566 else
6567 {
6571 }
6574 }
6576 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6577 of this code is to classify each 8bytes of incoming argument by the register
6578 class and assign registers accordingly. */
6580 /* Return the union class of CLASS1 and CLASS2.
6581 See the x86-64 PS ABI for details. */
6583 static enum x86_64_reg_class
6585 {
6586 /* Rule #1: If both classes are equal, this is the resulting class. */
6590 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6591 the other class. */
6597 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6601 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6609 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6610 MEMORY is used. */
6619 /* Rule #6: Otherwise class SSE is used. */
6621 }
6623 /* Classify the argument of type TYPE and mode MODE.
6624 CLASSES will be filled by the register class used to pass each word
6625 of the operand. The number of words is returned. In case the parameter
6626 should be passed in memory, 0 is returned. As a special case for zero
6627 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6629 BIT_OFFSET is used internally for handling records and specifies offset
6630 of the offset in bits modulo 512 to avoid overflow cases.
6632 See the x86-64 PS ABI for details.
6633 */
6635 static int
6638 {
6639 HOST_WIDE_INT bytes =
6641 int words
6644 /* Variable sized entities are always passed/returned in memory. */
6653 {
6655 tree field;
6658 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6665 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6666 signalize memory class, so handle it as special case. */
6668 {
6671 }
6673 /* Classify each field of record and merge classes. */
6675 {
6677 /* And now merge the fields of structure. */
6679 {
6681 {
6687 /* Bitfields are always classified as integer. Handle them
6688 early, since later code would consider them to be
6689 misaligned integers. */
6691 {
6700 }
6701 else
6702 {
6707 /* Flexible array member is ignored. */
6714 {
6718 {
6721 "the ABI of passing struct with"
6722 " a flexible array member has"
6724 }
6726 }
6728 subclasses,
6738 }
6739 }
6740 }
6744 /* Arrays are handled as small records. */
6745 {
6752 /* The partial classes are now full classes. */
6763 }
6766 /* Unions are similar to RECORD_TYPE but offset is always 0.
6767 */
6769 {
6771 {
6779 bit_offset);
6784 }
6785 }
6790 }
6793 {
6794 /* When size > 16 bytes, if the first one isn't
6795 X86_64_SSE_CLASS or any other ones aren't
6796 X86_64_SSEUP_CLASS, everything should be passed in
6797 memory. */
6804 }
6806 /* Final merger cleanup. */
6808 {
6809 /* If one class is MEMORY, everything should be passed in
6810 memory. */
6814 /* The X86_64_SSEUP_CLASS should be always preceded by
6815 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6819 {
6820 /* The first one should never be X86_64_SSEUP_CLASS. */
6823 }
6825 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6826 everything should be passed in memory. */
6829 {
6832 /* The first one should never be X86_64_X87UP_CLASS. */
6835 {
6838 "the ABI of passing union with long double"
6840 }
6842 }
6843 }
6845 }
6847 /* Compute alignment needed. We align all types to natural boundaries with
6848 exception of XFmode that is aligned to 64bits. */
6850 {
6859 /* Misaligned fields are always returned in memory. */
6862 }
6864 /* for V1xx modes, just use the base mode */
6869 /* Classification of atomic types. */
6871 {
6887 {
6890 /* Analyze last 128 bits only. */
6894 {
6897 }
6899 {
6902 }
6904 {
6908 }
6910 {
6913 }
6914 else
6916 }
6923 /* OImode shouldn't be used directly. */
6930 else
6948 else
6949 {
6953 {
6956 "the ABI of passing structure with complex float"
6958 }
6961 }
6970 /* This modes is larger than 16 bytes. */
7028 else
7032 }
7033 }
7035 /* Examine the argument and return set number of register required in each
7036 class. Return true iff parameter should be passed in memory. */
7038 static bool
7041 {
7052 {
7073 }
7076 }
7078 /* Construct container for the argument used by GCC interface. See
7079 FUNCTION_ARG for the detailed description. */
7081 static rtx
7085 {
7086 /* The following variables hold the static issued_error state. */
7091 machine_mode tmpmode;
7100 rtx ret;
7111 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7112 some less clueful developer tries to use floating-point anyway. */
7114 {
7116 {
7118 {
7121 }
7122 }
7124 {
7127 }
7129 }
7131 /* Likewise, error if the ABI requires us to return values in the
7132 x87 registers and the user specified -mno-80387. */
7138 {
7140 {
7143 }
7145 }
7147 /* First construct simple cases. Avoid SCmode, since we want to use
7148 single register to pass this type. */
7151 {
7166 /* Zero sized array, struct or class. */
7170 }
7209 /* Otherwise figure out the entries of the PARALLEL. */
7211 {
7215 {
7220 /* Merge TImodes on aligned occasions here too. */
7222 tmpmode
7226 else
7228 /* We've requested 24 bytes we
7229 don't have mode for. Use DImode. */
7236 intreg++;
7244 sse_regno++;
7252 sse_regno++;
7257 {
7263 {
7265 i++;
7266 }
7267 else
7292 }
7298 sse_regno++;
7302 }
7303 }
7305 /* Empty aligned struct, union or class. */
7313 }
7315 /* Update the data in CUM to advance over an argument of mode MODE
7316 and data type TYPE. (TYPE is null for libcalls where that information
7317 may not be available.)
7319 Return a number of integer regsiters advanced over. */
7321 static int
7324 HOST_WIDE_INT words)
7325 {
7329 {
7336 /* FALLTHRU */
7348 {
7351 }
7355 /* OImode shouldn't be used directly. */
7364 /* FALLTHRU */
7386 {
7391 {
7394 }
7395 }
7405 {
7410 {
7413 }
7414 }
7416 }
7419 }
7421 static int
7424 {
7427 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7434 {
7440 }
7441 else
7442 {
7447 }
7448 }
7450 static int
7452 HOST_WIDE_INT words)
7453 {
7454 /* Otherwise, this should be passed indirect. */
7459 {
7463 }
7465 }
7467 /* Update the data in CUM to advance over an argument of mode MODE and
7468 data type TYPE. (TYPE is null for libcalls where that information
7469 may not be available.) */
7471 static void
7474 {
7481 else
7490 {
7491 /* If we pass bounds in BT then just update remained bounds count. */
7493 {
7496 }
7498 /* Update remained number of bounds to force. */
7505 }
7507 /* The first arg not going to Bounds Tables resets this counter. */
7509 /* For unnamed args we always pass bounds to avoid bounds mess when
7510 passed and received types do not match. If bounds do not follow
7511 unnamed arg, still pretend required number of bounds were passed. */
7513 {
7516 }
7522 else
7525 /* For stdarg we expect bounds to be passed for each value passed
7526 in register. */
7529 /* For pointers passed in memory we expect bounds passed in Bounds
7530 Table. */
7533 }
7535 /* Define where to put the arguments to a function.
7536 Value is zero to push the argument on the stack,
7537 or a hard register in which to store the argument.
7539 MODE is the argument's machine mode.
7540 TYPE is the data type of the argument (as a tree).
7541 This is null for libcalls where that information may
7542 not be available.
7543 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7544 the preceding args and about the function being called.
7545 NAMED is nonzero if this argument is a named parameter
7546 (otherwise it is an extra parameter matching an ellipsis). */
7548 static rtx
7552 {
7553 /* Avoid the AL settings for the Unix64 ABI. */
7558 {
7565 /* FALLTHRU */
7571 {
7574 /* Fastcall allocates the first two DWORD (SImode) or
7575 smaller arguments to ECX and EDX if it isn't an
7576 aggregate type . */
7578 {
7584 /* ECX not EAX is the first allocated register. */
7587 }
7589 }
7598 /* FALLTHRU */
7600 /* In 32bit, we pass TImode in xmm registers. */
7608 {
7612 }
7617 /* OImode and XImode shouldn't be used directly. */
7633 {
7637 }
7647 {
7651 }
7653 }
7656 }
7658 static rtx
7661 {
7662 /* Handle a hidden AL argument containing number of registers
7663 for varargs x86-64 functions. */
7667 ? X86_64_SSE_REGPARM_MAX
7672 {
7688 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7692 }
7698 }
7700 static rtx
7703 HOST_WIDE_INT bytes)
7704 {
7707 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7708 We use value of -2 to specify that current function call is MSABI. */
7712 /* If we've run out of registers, it goes on the stack. */
7718 /* Only floating point modes are passed in anything but integer regs. */
7720 {
7723 else
7724 {
7727 /* Unnamed floating parameters are passed in both the
7728 SSE and integer registers. */
7734 }
7735 }
7736 /* Handle aggregated types passed in register. */
7738 {
7743 }
7746 }
7748 /* Return where to put the arguments to a function.
7749 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7751 MODE is the argument's machine mode. TYPE is the data type of the
7752 argument. It is null for libcalls where that information may not be
7753 available. CUM gives information about the preceding args and about
7754 the function being called. NAMED is nonzero if this argument is a
7755 named parameter (otherwise it is an extra parameter matching an
7756 ellipsis). */
7758 static rtx
7761 {
7765 rtx arg;
7767 /* All pointer bounds argumntas are handled separately here. */
7770 {
7771 /* Return NULL if bounds are forced to go in Bounds Table. */
7774 /* Return the next available bound reg if any. */
7777 /* Return the next special slot number otherwise. */
7778 else
7782 }
7786 else
7790 /* To simplify the code below, represent vector types with a vector mode
7791 even if MMX/SSE are not active. */
7799 else
7803 }
7805 /* A C expression that indicates when an argument must be passed by
7806 reference. If nonzero for an argument, a copy of that argument is
7807 made in memory and a pointer to the argument is passed instead of
7808 the argument itself. The pointer is passed in whatever way is
7809 appropriate for passing a pointer to that type. */
7811 static bool
7814 {
7817 /* See Windows x64 Software Convention. */
7819 {
7822 {
7823 /* Arrays are passed by reference. */
7828 {
7829 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7830 are passed by reference. */
7832 }
7833 }
7835 /* __m128 is passed by reference. */
7841 }
7842 }
7847 }
7849 /* Return true when TYPE should be 128bit aligned for 32bit argument
7850 passing ABI. XXX: This function is obsolete and is only used for
7851 checking psABI compatibility with previous versions of GCC. */
7853 static bool
7855 {
7867 {
7868 /* Walk the aggregates recursively. */
7870 {
7874 {
7875 tree field;
7877 /* Walk all the structure fields. */
7879 {
7883 }
7885 }
7888 /* Just for use if some languages passes arrays by value. */
7895 }
7896 }
7898 }
7900 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7901 XXX: This function is obsolete and is only used for checking psABI
7902 compatibility with previous versions of GCC. */
7904 static unsigned int
7907 {
7908 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7909 natural boundaries. */
7911 {
7912 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7913 make an exception for SSE modes since these require 128bit
7914 alignment.
7916 The handling here differs from field_alignment. ICC aligns MMX
7917 arguments to 4 byte boundaries, while structure fields are aligned
7918 to 8 byte boundaries. */
7920 {
7923 }
7924 else
7925 {
7928 }
7929 }
7933 }
7935 /* Return true when TYPE should be 128bit aligned for 32bit argument
7936 passing ABI. */
7938 static bool
7940 {
7950 {
7951 /* Walk the aggregates recursively. */
7953 {
7957 {
7958 tree field;
7960 /* Walk all the structure fields. */
7962 field;
7964 {
7968 }
7970 }
7973 /* Just for use if some languages passes arrays by value. */
7980 }
7981 }
7982 else
7986 }
7988 /* Gives the alignment boundary, in bits, of an argument with the
7989 specified mode and type. */
7991 static unsigned int
7993 {
7996 {
7997 /* Since the main variant type is used for call, we convert it to
7998 the main variant type. */
8001 }
8002 else
8006 else
8007 {
8012 {
8013 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8015 {
8018 }
8024 }
8027 && !warned
8029 saved_align))
8030 {
8033 "The ABI for passing parameters with %d-byte"
8036 }
8037 }
8040 }
8042 /* Return true if N is a possible register number of function value. */
8044 static bool
8046 {
8048 {
8060 /* Complex values are returned in %st(0)/%st(1) pair. */
8063 /* TODO: The function should depend on current function ABI but
8064 builtins.c would need updating then. Therefore we use the
8065 default ABI. */
8070 /* Complex values are returned in %xmm0/%xmm1 pair. */
8079 }
8082 }
8084 /* Define how to find the value returned by a function.
8085 VALTYPE is the data type of the value (as a tree).
8086 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8087 otherwise, FUNC is 0. */
8089 static rtx
8092 {
8095 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8096 we normally prevent this case when mmx is not available. However
8097 some ABIs may require the result to be returned like DImode. */
8101 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8102 we prevent this case when sse is not available. However some ABIs
8103 may require the result to be returned like integer TImode. */
8108 /* 32-byte vector modes in %ymm0. */
8112 /* 64-byte vector modes in %zmm0. */
8116 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8119 else
8120 /* Most things go in %eax. */
8123 /* Override FP return register with %xmm0 for local functions when
8124 SSE math is enabled or for functions with sseregparm attribute. */
8126 {
8131 }
8133 /* OImode shouldn't be used directly. */
8137 }
8139 static rtx
8141 const_tree valtype)
8142 {
8143 rtx ret;
8145 /* Handle libcalls, which don't provide a type node. */
8147 {
8151 {
8170 }
8173 }
8175 {
8176 /* Pointers are always returned in word_mode. */
8178 }
8184 /* For zero sized structures, construct_container returns NULL, but we
8185 need to keep rest of compiler happy by returning meaningful value. */
8190 }
8192 static rtx
8194 const_tree valtype)
8195 {
8199 {
8201 {
8220 }
8221 }
8223 }
8225 static rtx
8228 {
8243 else
8245 }
8247 static rtx
8249 {
8255 }
8257 /* Return an RTX representing a place where a function returns
8258 or recieves pointer bounds or NULL if no bounds are returned.
8260 VALTYPE is a data type of a value returned by the function.
8262 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8263 or FUNCTION_TYPE of the function.
8265 If OUTGOING is false, return a place in which the caller will
8266 see the return value. Otherwise, return a place where a
8267 function returns a value. */
8269 static rtx
8271 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8273 {
8279 {
8280 bitmap slots;
8282 bitmap_iterator bi;
8290 {
8295 }
8301 }
8302 else
8306 }
8308 /* Pointer function arguments and return values are promoted to
8309 word_mode. */
8311 static machine_mode
8315 {
8317 {
8320 }
8322 for_return);
8323 }
8325 /* Return true if a structure, union or array with MODE containing FIELD
8326 should be accessed using BLKmode. */
8328 static bool
8330 {
8331 /* Union with XFmode must be in BLKmode. */
8335 }
8337 rtx
8339 {
8341 }
8343 /* Return true iff type is returned in memory. */
8345 static bool
8347 {
8348 #ifdef SUBTARGET_RETURN_IN_MEMORY
8350 #else
8352 HOST_WIDE_INT size;
8358 {
8360 {
8363 /* __m128 is returned in xmm0. */
8372 /* Otherwise, the size must be exactly in [1248]. */
8374 }
8375 else
8376 {
8381 }
8382 }
8383 else
8384 {
8394 {
8395 /* User-created vectors small enough to fit in EAX. */
8399 /* Unless ABI prescibes otherwise,
8400 MMX/3dNow values are returned in MM0 if available. */
8405 /* SSE values are returned in XMM0 if available. */
8409 /* AVX values are returned in YMM0 if available. */
8413 /* AVX512F values are returned in ZMM0 if available. */
8416 }
8424 /* OImode shouldn't be used directly. */
8428 }
8429 #endif
8430 }
8432 \f
8433 /* Create the va_list data type. */
8435 /* Returns the calling convention specific va_list date type.
8436 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8438 static tree
8440 {
8443 /* For i386 we use plain pointer to argument area. */
8453 unsigned_type_node);
8456 unsigned_type_node);
8459 ptr_type_node);
8462 ptr_type_node);
8481 /* The correct type is an array type of one element. */
8483 }
8485 /* Setup the builtin va_list data type and for 64-bit the additional
8486 calling convention specific va_list data types. */
8488 static tree
8490 {
8493 /* Initialize abi specific va_list builtin types. */
8495 {
8496 tree t;
8498 {
8503 }
8504 else
8505 {
8510 }
8512 {
8517 }
8518 else
8519 {
8524 }
8525 }
8528 }
8530 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8532 static void
8534 {
8536 alias_set_type set;
8539 /* GPR size of varargs save area. */
8542 else
8545 /* FPR size of varargs save area. We don't need it if we don't pass
8546 anything in SSE registers. */
8549 else
8563 {
8571 }
8574 {
8575 machine_mode smode;
8577 rtx test;
8579 /* Now emit code to save SSE registers. The AX parameter contains number
8580 of SSE parameter registers used to call this function, though all we
8581 actually check here is the zero/non-zero status. */
8586 label));
8588 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8589 we used movdqa (i.e. TImode) instead? Perhaps even better would
8590 be if we could determine the real mode of the data, via a hook
8591 into pass_stdarg. Ignore all that for now. */
8601 {
8610 }
8613 }
8614 }
8616 static void
8618 {
8622 /* Reset to zero, as there might be a sysv vaarg used
8623 before. */
8628 {
8639 }
8640 }
8642 static void
8645 {
8647 CUMULATIVE_ARGS next_cum;
8648 tree fntype;
8650 /* This argument doesn't appear to be used anymore. Which is good,
8651 because the old code here didn't suppress rtl generation. */
8659 /* For varargs, we do not want to skip the dummy va_dcl argument.
8660 For stdargs, we do want to skip the last named argument. */
8668 else
8670 }
8672 static void
8675 tree type,
8678 {
8680 CUMULATIVE_ARGS next_cum;
8681 tree fntype;
8682 rtx save_area;
8687 /* Do nothing if we use plain pointer to argument area. */
8693 /* For varargs, we do not want to skip the dummy va_dcl argument.
8694 For stdargs, we do want to skip the last named argument. */
8708 {
8713 rtx bounds;
8717 else
8718 {
8719 rtx ldx_addr =
8726 }
8732 bnd_reg++;
8733 }
8734 }
8737 /* Checks if TYPE is of kind va_list char *. */
8739 static bool
8741 {
8742 tree canonic;
8744 /* For 32-bit it is always true. */
8750 }
8752 /* Implement va_start. */
8754 static void
8756 {
8760 tree type;
8761 rtx ovf_rtx;
8765 {
8768 /* When we are splitting the stack, we can't refer to the stack
8769 arguments using internal_arg_pointer, because they may be on
8770 the old stack. The split stack prologue will arrange to
8771 leave a pointer to the old stack arguments in a scratch
8772 register, which we here copy to a pseudo-register. The split
8773 stack prologue can't set the pseudo-register directly because
8774 it (the prologue) runs before any registers have been saved. */
8778 {
8779 rtx reg;
8793 }
8794 }
8796 /* Only 64bit target needs something special. */
8798 {
8801 else
8802 {
8812 /* Store zero bounds for va_list. */
8816 next));
8818 }
8820 }
8829 /* The following should be folded into the MEM_REF offset. */
8839 /* Count number of gp and fp argument registers used. */
8845 {
8851 }
8854 {
8860 }
8862 /* Find the overflow area. */
8866 else
8872 /* Store zero bounds for overflow area pointer. */
8881 {
8882 /* Find the register save area.
8883 Prologue of the function save it right above stack frame. */
8889 /* Store zero bounds for save area pointer. */
8896 }
8897 }
8899 /* Implement va_arg. */
8901 static tree
8904 {
8911 rtx container;
8913 tree ptrtype;
8914 machine_mode nat_mode;
8917 /* Only 64bit target needs something special. */
8941 {
8954 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8956 {
8959 }
8967 }
8969 /* Pull the value out of the saved registers. */
8974 {
8988 /* In case we are passing structure, verify that it is consecutive block
8989 on the register save area. If not we need to do moves. */
8991 {
8992 /* Verify that all registers are strictly consecutive */
8994 {
8998 {
9003 }
9004 }
9005 else
9006 {
9010 {
9015 }
9016 }
9017 }
9019 {
9022 }
9023 else
9024 {
9027 }
9029 /* First ensure that we fit completely in registers. */
9031 {
9038 }
9040 {
9048 }
9050 /* Compute index to start of area used for integer regs. */
9052 {
9053 /* int_addr = gpr + sav; */
9056 }
9058 {
9059 /* sse_addr = fpr + sav; */
9062 }
9064 {
9068 /* addr = &temp; */
9073 {
9077 tree piece_type;
9078 tree addr_type;
9079 tree daddr_type;
9088 {
9093 }
9097 else
9104 {
9107 }
9108 else
9109 {
9112 }
9119 {
9124 }
9125 else
9126 {
9127 tree copy
9132 }
9134 }
9135 }
9138 {
9142 }
9145 {
9149 }
9154 }
9156 /* ... otherwise out of the overflow area. */
9158 /* When we align parameter on stack for caller, if the parameter
9159 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9160 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9161 here with caller. */
9166 /* Care for on-stack alignment if needed. */
9169 else
9170 {
9175 }
9192 }
9193 \f
9194 /* Return true if OPNUM's MEM should be matched
9195 in movabs* patterns. */
9197 bool
9199 {
9211 }
9212 \f
9213 /* Initialize the table of extra 80387 mathematical constants. */
9215 static void
9217 {
9219 {
9225 };
9229 {
9231 /* Ensure each constant is rounded to XFmode precision. */
9234 }
9237 }
9239 /* Return non-zero if the constant is something that
9240 can be loaded with a special instruction. */
9242 int
9244 {
9247 REAL_VALUE_TYPE r;
9259 /* For XFmode constants, try to find a special 80387 instruction when
9260 optimizing for size or on those CPUs that benefit from them. */
9263 {
9272 }
9274 /* Load of the constant -0.0 or -1.0 will be split as
9275 fldz;fchs or fld1;fchs sequence. */
9282 }
9284 /* Return the opcode of the special instruction to be used to load
9285 the constant X. */
9289 {
9291 {
9311 }
9312 }
9314 /* Return the CONST_DOUBLE representing the 80387 constant that is
9315 loaded by the specified special instruction. The argument IDX
9316 matches the return value from standard_80387_constant_p. */
9318 rtx
9320 {
9327 {
9338 }
9341 XFmode);
9342 }
9344 /* Return 1 if X is all 0s and 2 if x is all 1s
9345 in supported SSE/AVX vector mode. */
9347 int
9349 {
9356 {
9377 }
9380 }
9382 /* Return the opcode of the special instruction to be used to load
9383 the constant X. */
9387 {
9389 {
9392 {
9419 }
9429 else
9434 }
9436 }
9438 /* Returns true if OP contains a symbol reference */
9440 bool
9442 {
9451 {
9453 {
9459 }
9463 }
9466 }
9468 /* Return true if it is appropriate to emit `ret' instructions in the
9469 body of a function. Do this only if the epilogue is simple, needing a
9470 couple of insns. Prior to reloading, we can't tell how many registers
9471 must be saved, so return false then. Return false if there is no frame
9472 marker to de-allocate. */
9474 bool
9476 {
9482 /* Don't allow more than 32k pop, since that's all we can do
9483 with one instruction. */
9490 }
9491 \f
9492 /* Value should be nonzero if functions must have frame pointers.
9493 Zero means the frame pointer need not be set up (and parms may
9494 be accessed via the stack pointer) in functions that seem suitable. */
9496 static bool
9498 {
9499 /* If we accessed previous frames, then the generated code expects
9500 to be able to access the saved ebp value in our frame. */
9504 /* Several x86 os'es need a frame pointer for other reasons,
9505 usually pertaining to setjmp. */
9509 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9513 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9514 allocation is 4GB. */
9518 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9519 turns off the frame pointer by default. Turn it back on now if
9520 we've not got a leaf function. */
9530 }
9532 /* Record that the current function accesses previous call frames. */
9534 void
9536 {
9538 }
9539 \f
9540 #ifndef USE_HIDDEN_LINKONCE
9541 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9542 # define USE_HIDDEN_LINKONCE 1
9543 # else
9544 # define USE_HIDDEN_LINKONCE 0
9545 # endif
9546 #endif
9550 /* Fills in the label name that should be used for a pc thunk for
9551 the given register. */
9553 static void
9555 {
9560 else
9562 }
9565 /* This function generates code for -fpic that loads %ebx with
9566 the return address of the caller and then returns. */
9568 static void
9570 {
9575 {
9577 tree decl;
9593 #if TARGET_MACHO
9595 {
9604 }
9605 else
9606 #endif
9608 {
9619 }
9620 else
9621 {
9624 }
9630 /* Make sure unwind info is emitted for the thunk if needed. */
9633 /* Pad stack IP move with 4 instructions (two NOPs count
9634 as one instruction). */
9636 {
9641 }
9652 }
9656 }
9658 /* Emit code for the SET_GOT patterns. */
9662 {
9668 {
9669 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9674 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9675 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9676 an unadorned address. */
9681 }
9686 {
9688 /* We don't need a pic base, we're not producing pic. */
9695 }
9696 else
9697 {
9706 #if TARGET_MACHO
9707 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9708 This is what will be referenced by the Mach-O PIC subsystem. */
9712 /* When we are restoring the pic base at the site of a nonlocal label,
9713 and we decided to emit the pic base above, we will still output a
9714 local label used for calculating the correction offset (even though
9715 the offset will be 0 in that case). */
9719 #endif
9720 }
9726 }
9728 /* Generate an "push" pattern for input ARG. */
9730 static rtx
9732 {
9745 stack_pointer_rtx)),
9746 arg);
9747 }
9749 /* Generate an "pop" pattern for input ARG. */
9751 static rtx
9753 {
9758 arg,
9761 stack_pointer_rtx)));
9762 }
9764 /* Return >= 0 if there is an unused call-clobbered register available
9765 for the entire function. */
9767 static unsigned int
9769 {
9776 {
9778 /* Can't use the same register for both PIC and DRAP. */
9781 else
9786 }
9789 }
9791 /* Return TRUE if we need to save REGNO. */
9793 static bool
9795 {
9798 {
9800 {
9801 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9802 _mcount in prologue. */
9805 }
9812 }
9815 {
9818 {
9824 }
9825 }
9836 }
9838 /* Return number of saved general prupose registers. */
9840 static int
9842 {
9848 nregs ++;
9850 }
9852 /* Return number of saved SSE registrers. */
9854 static int
9856 {
9864 nregs ++;
9866 }
9868 /* Given FROM and TO register numbers, say whether this elimination is
9869 allowed. If stack alignment is needed, we can only replace argument
9870 pointer with hard frame pointer, or replace frame pointer with stack
9871 pointer. Otherwise, frame pointer elimination is automatically
9872 handled and all other eliminations are valid. */
9874 static bool
9876 {
9882 else
9884 }
9886 /* Return the offset between two registers, one to be eliminated, and the other
9887 its replacement, at the start of a routine. */
9889 HOST_WIDE_INT
9891 {
9900 else
9901 {
9909 }
9910 }
9912 /* In a dynamically-aligned function, we can't know the offset from
9913 stack pointer to frame pointer, so we must ensure that setjmp
9914 eliminates fp against the hard fp (%ebp) rather than trying to
9915 index from %esp up to the top of the frame across a gap that is
9916 of unknown (at compile-time) size. */
9917 static rtx
9919 {
9921 }
9923 /* When using -fsplit-stack, the allocation routines set a field in
9924 the TCB to the bottom of the stack plus this much space, measured
9925 in bytes. */
9927 #define SPLIT_STACK_AVAILABLE 256
9929 /* Fill structure ix86_frame about frame of currently computed function. */
9931 static void
9933 {
9935 HOST_WIDE_INT offset;
9938 HOST_WIDE_INT to_allocate;
9943 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9944 function prologues and leaf. */
9948 {
9951 }
9952 /* preferred_stack_boundary is never updated for call
9953 expanded from tls descriptor. Update it here. We don't update it in
9954 expand stage because according to the comments before
9955 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9956 away. */
9959 {
9963 }
9972 /* For SEH we have to limit the amount of code movement into the prologue.
9973 At present we do this via a BLOCKAGE, at which point there's very little
9974 scheduling that can be done, which means that there's very little point
9975 in doing anything except PUSHs. */
9979 /* During reload iteration the amount of registers saved can change.
9980 Recompute the value as needed. Do not recompute when amount of registers
9981 didn't change as reload does multiple calls to the function and does not
9982 expect the decision to change within single iteration. */
9985 {
9991 /* The fast prologue uses move instead of push to save registers. This
9992 is significantly longer, but also executes faster as modern hardware
9993 can execute the moves in parallel, but can't do that for push/pop.
9995 Be careful about choosing what prologue to emit: When function takes
9996 many instructions to execute we may use slow version as well as in
9997 case function is known to be outside hot spot (this is known with
9998 feedback only). Weight the size of function by number of registers
9999 to save as it is cheap to use one or two push instructions but very
10000 slow to use many of them. */
10004 || (flag_branch_probabilities
10007 else
10010 }
10012 frame->save_regs_using_mov
10014 /* If static stack checking is enabled and done with probes,
10015 the registers need to be saved before allocating the frame. */
10018 /* Skip return address. */
10021 /* Skip pushed static chain. */
10025 /* Skip saved base pointer. */
10030 /* The traditional frame pointer location is at the top of the frame. */
10033 /* Register save area */
10037 /* On SEH target, registers are pushed just before the frame pointer
10038 location. */
10042 /* Align and set SSE register save area. */
10044 {
10045 /* The only ABI that has saved SSE registers (Win64) also has a
10046 16-byte aligned default stack, and thus we don't need to be
10047 within the re-aligned local stack frame to save them. */
10051 }
10054 /* The re-aligned stack starts here. Values before this point are not
10055 directly comparable with values below this point. In order to make
10056 sure that no value happens to be the same before and after, force
10057 the alignment computation below to add a non-zero value. */
10061 /* Va-arg area */
10065 /* Align start of frame for local function. */
10074 /* Frame pointer points here. */
10079 /* Add outgoing arguments area. Can be skipped if we eliminated
10080 all the function calls as dead code.
10081 Skipping is however impossible when function calls alloca. Alloca
10082 expander assumes that last crtl->outgoing_args_size
10083 of stack frame are unused. */
10087 {
10090 }
10091 else
10094 /* Align stack boundary. Only needed if we're calling another function
10095 or using alloca. */
10100 /* We've reached end of stack frame. */
10103 /* Size prologue needs to allocate. */
10114 {
10120 }
10121 else
10125 /* The SEH frame pointer location is near the bottom of the frame.
10126 This is enforced by the fact that the difference between the
10127 stack pointer and the frame pointer is limited to 240 bytes in
10128 the unwind data structure. */
10130 {
10131 HOST_WIDE_INT diff;
10133 /* If we can leave the frame pointer where it is, do so. Also, returns
10134 the establisher frame for __builtin_frame_address (0). */
10139 {
10140 /* Ideally we'd determine what portion of the local stack frame
10141 (within the constraint of the lowest 240) is most heavily used.
10142 But without that complication, simply bias the frame pointer
10143 by 128 bytes so as to maximize the amount of the local stack
10144 frame that is addressable with 8-bit offsets. */
10146 }
10147 }
10148 }
10150 /* This is semi-inlined memory_address_length, but simplified
10151 since we know that we're always dealing with reg+offset, and
10152 to avoid having to create and discard all that rtl. */
10156 {
10160 {
10161 /* EBP and R13 cannot be encoded without an offset. */
10163 }
10167 /* ESP and R12 must be encoded with a SIB byte. */
10169 len++;
10172 }
10174 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10175 The valid base registers are taken from CFUN->MACHINE->FS. */
10177 static rtx
10179 {
10185 {
10186 /* Choose the base register most likely to allow the most scheduling
10187 opportunities. Generally FP is valid throughout the function,
10188 while DRAP must be reloaded within the epilogue. But choose either
10189 over the SP due to increased encoding size. */
10192 {
10195 }
10197 {
10200 }
10202 {
10205 }
10206 }
10207 else
10208 {
10209 HOST_WIDE_INT toffset;
10212 /* Choose the base register with the smallest address encoding.
10213 With a tie, choose FP > DRAP > SP. */
10215 {
10219 }
10221 {
10225 {
10229 }
10230 }
10232 {
10236 {
10240 }
10241 }
10242 }
10246 }
10248 /* Emit code to save registers in the prologue. */
10250 static void
10252 {
10254 rtx insn;
10258 {
10261 }
10262 }
10264 /* Emit a single register save at CFA - CFA_OFFSET. */
10266 static void
10268 HOST_WIDE_INT cfa_offset)
10269 {
10277 /* For SSE saves, we need to indicate the 128-bit alignment. */
10288 /* When saving registers into a re-aligned local stack frame, avoid
10289 any tricky guessing by dwarf2out. */
10291 {
10295 {
10296 /* A bit of a hack. We force the DRAP register to be saved in
10297 the re-aligned stack frame, which provides us with a copy
10298 of the CFA that will last past the prologue. Install it. */
10304 }
10305 else
10306 {
10307 /* The frame pointer is a stable reference within the
10308 aligned frame. Use it. */
10315 }
10316 }
10318 /* The memory may not be relative to the current CFA register,
10319 which means that we may need to generate a new pattern for
10320 use by the unwind info. */
10322 {
10327 }
10328 }
10330 /* Emit code to save registers using MOV insns.
10331 First register is stored at CFA - CFA_OFFSET. */
10332 static void
10334 {
10339 {
10342 }
10343 }
10345 /* Emit code to save SSE registers using MOV insns.
10346 First register is stored at CFA - CFA_OFFSET. */
10347 static void
10349 {
10354 {
10357 }
10358 }
10362 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10363 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10364 Don't add the note if the previously saved value will be left untouched
10365 within stack red-zone till return, as unwinders can find the same value
10366 in the register and on the stack. */
10368 static void
10370 {
10376 {
10379 }
10380 else
10381 queued_cfa_restores
10383 }
10385 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10387 static void
10389 {
10390 rtx last;
10394 ;
10399 }
10401 /* Expand prologue or epilogue stack adjustment.
10402 The pattern exist to put a dependency on all ebp-based memory accesses.
10403 STYLE should be negative if instructions should be marked as frame related,
10404 zero if %r11 register is live and cannot be freely used and positive
10405 otherwise. */
10407 static void
10410 {
10412 rtx insn;
10419 else
10420 {
10421 rtx tmp;
10422 /* r11 is used by indirect sibcall return as well, set before the
10423 epilogue and used after the epilogue. */
10426 else
10427 {
10431 }
10437 }
10444 {
10445 rtx r;
10455 }
10457 {
10460 {
10464 }
10465 }
10468 {
10473 {
10476 }
10478 {
10481 }
10482 else
10483 {
10484 /* Else there are two possibilities: SP itself, which we set
10485 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10486 taken care of this by hand along the eh_return path. */
10489 }
10493 }
10494 }
10496 /* Find an available register to be used as dynamic realign argument
10497 pointer regsiter. Such a register will be written in prologue and
10498 used in begin of body, so it must not be
10499 1. parameter passing register.
10500 2. GOT pointer.
10501 We reuse static-chain register if it is available. Otherwise, we
10502 use DI for i386 and R13 for x86-64. We chose R13 since it has
10503 shorter encoding.
10505 Return: the regno of chosen register. */
10507 static unsigned int
10509 {
10513 {
10514 /* Use R13 for nested function or function need static chain.
10515 Since function with tail call may use any caller-saved
10516 registers in epilogue, DRAP must not use caller-saved
10517 register in such case. */
10522 }
10523 else
10524 {
10525 /* Use DI for nested function or function need static chain.
10526 Since function with tail call may use any caller-saved
10527 registers in epilogue, DRAP must not use caller-saved
10528 register in such case. */
10532 /* Reuse static chain register if it isn't used for parameter
10533 passing. */
10535 {
10539 }
10541 }
10542 }
10544 /* Return minimum incoming stack alignment. */
10546 static unsigned int
10548 {
10551 /* Prefer the one specified at command line. */
10554 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10555 if -mstackrealign is used, it isn't used for sibcall check and
10556 estimated stack alignment is 128bit. */
10558 && !TARGET_64BIT
10559 && ix86_force_align_arg_pointer
10562 else
10565 /* Incoming stack alignment can be changed on individual functions
10566 via force_align_arg_pointer attribute. We use the smallest
10567 incoming stack boundary. */
10573 /* The incoming stack frame has to be aligned at least at
10574 parm_stack_boundary. */
10578 /* Stack at entrance of main is aligned by runtime. We use the
10579 smallest incoming stack boundary. */
10587 }
10589 /* Update incoming stack boundary and estimated stack alignment. */
10591 static void
10593 {
10594 ix86_incoming_stack_boundary
10597 /* x86_64 vararg needs 16byte stack alignment for register save
10598 area. */
10603 }
10605 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10606 needed or an rtx for DRAP otherwise. */
10608 static rtx
10610 {
10615 {
10616 /* Assign DRAP to vDRAP and returns vDRAP */
10618 rtx drap_vreg;
10619 rtx arg_ptr;
10632 {
10635 }
10637 }
10638 else
10640 }
10642 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10644 static rtx
10646 {
10648 }
10651 rtx reg;
10653 };
10655 /* Return a short-lived scratch register for use on function entry.
10656 In 32-bit mode, it is valid only after the registers are saved
10657 in the prologue. This register must be released by means of
10658 release_scratch_register_on_entry once it is dead. */
10660 static void
10662 {
10668 {
10669 /* We always use R11 in 64-bit mode. */
10671 }
10672 else
10673 {
10675 bool fastcall_p
10677 bool thiscall_p
10681 int drap_regno
10684 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10685 for the static chain register. */
10689 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10690 for the static chain register. */
10695 /* ecx is the static chain register. */
10697 && !static_chain_p
10702 /* esi is the static chain register. */
10708 else
10709 {
10712 }
10713 }
10717 {
10720 }
10721 }
10723 /* Release a scratch register obtained from the preceding function. */
10725 static void
10727 {
10729 {
10733 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10739 }
10740 }
10742 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10744 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10746 static void
10748 {
10749 /* We skip the probe for the first interval + a small dope of 4 words and
10750 probe that many bytes past the specified size to maintain a protection
10751 area at the botton of the stack. */
10755 /* See if we have a constant small number of probes to generate. If so,
10756 that's the easy case. The run-time loop is made up of 11 insns in the
10757 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10758 for n # of intervals. */
10760 {
10764 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10765 values of N from 1 until it exceeds SIZE. If only one probe is
10766 needed, this will not generate any code. Then adjust and probe
10767 to PROBE_INTERVAL + SIZE. */
10769 {
10771 {
10774 }
10775 else
10782 }
10786 else
10794 /* Adjust back to account for the additional first interval. */
10798 }
10800 /* Otherwise, do the same as above, but in a loop. Note that we must be
10801 extra careful with variables wrapping around because we might be at
10802 the very top (or the very bottom) of the address space and we have
10803 to be able to handle this case properly; in particular, we use an
10804 equality test for the loop condition. */
10805 else
10806 {
10807 HOST_WIDE_INT rounded_size;
10813 /* Step 1: round SIZE to the previous multiple of the interval. */
10818 /* Step 2: compute initial and final value of the loop counter. */
10820 /* SP = SP_0 + PROBE_INTERVAL. */
10825 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10829 stack_pointer_rtx)));
10832 /* Step 3: the loop
10834 while (SP != LAST_ADDR)
10835 {
10836 SP = SP + PROBE_INTERVAL
10837 probe at SP
10838 }
10840 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10841 values of N from 1 until it is equal to ROUNDED_SIZE. */
10846 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10847 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10850 {
10855 }
10857 /* Adjust back to account for the additional first interval. */
10863 }
10867 /* Even if the stack pointer isn't the CFA register, we need to correctly
10868 describe the adjustments made to it, in particular differentiate the
10869 frame-related ones from the frame-unrelated ones. */
10871 {
10884 }
10886 /* Make sure nothing is scheduled before we are done. */
10888 }
10890 /* Adjust the stack pointer up to REG while probing it. */
10894 {
10904 /* Jump to END_LAB if SP == LAST_ADDR. */
10912 /* SP = SP + PROBE_INTERVAL. */
10916 /* Probe at SP. */
10927 }
10929 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10930 inclusive. These are offsets from the current stack pointer. */
10932 static void
10934 {
10935 /* See if we have a constant small number of probes to generate. If so,
10936 that's the easy case. The run-time loop is made up of 7 insns in the
10937 generic case while the compile-time loop is made up of n insns for n #
10938 of intervals. */
10940 {
10941 HOST_WIDE_INT i;
10943 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10944 it exceeds SIZE. If only one probe is needed, this will not
10945 generate any code. Then probe at FIRST + SIZE. */
10952 }
10954 /* Otherwise, do the same as above, but in a loop. Note that we must be
10955 extra careful with variables wrapping around because we might be at
10956 the very top (or the very bottom) of the address space and we have
10957 to be able to handle this case properly; in particular, we use an
10958 equality test for the loop condition. */
10959 else
10960 {
10967 /* Step 1: round SIZE to the previous multiple of the interval. */
10972 /* Step 2: compute initial and final value of the loop counter. */
10974 /* TEST_OFFSET = FIRST. */
10977 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10981 /* Step 3: the loop
10983 while (TEST_ADDR != LAST_ADDR)
10984 {
10985 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10986 probe at TEST_ADDR
10987 }
10989 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10990 until it is equal to ROUNDED_SIZE. */
10995 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10996 that SIZE is equal to ROUNDED_SIZE. */
11001 stack_pointer_rtx,
11006 }
11008 /* Make sure nothing is scheduled before we are done. */
11010 }
11012 /* Probe a range of stack addresses from REG to END, inclusive. These are
11013 offsets from the current stack pointer. */
11017 {
11027 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11035 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11039 /* Probe at TEST_ADDR. */
11052 }
11054 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11055 to be generated in correct form. */
11056 static void
11058 {
11059 /* Check if stack realign is really needed after reload, and
11060 stores result in cfun */
11061 unsigned int incoming_stack_boundary
11070 {
11071 /* After stack_realign_needed is finalized, we can't no longer
11072 change it. */
11075 }
11077 /* If the only reason for frame_pointer_needed is that we conservatively
11078 assumed stack realignment might be needed, but in the end nothing that
11079 needed the stack alignment had been spilled, clear frame_pointer_needed
11080 and say we don't need stack realignment. */
11082 && frame_pointer_needed
11084 && flag_omit_frame_pointer
11086 && !ix86_current_function_calls_tls_descriptor
11095 {
11097 basic_block bb;
11104 HARD_FRAME_POINTER_REGNUM);
11106 {
11111 set_up_by_prologue))
11112 {
11116 }
11117 }
11119 /* If drap has been set, but it actually isn't live at the start
11120 of the function, there is no reason to set it up. */
11122 {
11125 {
11128 }
11129 }
11130 else
11145 }
11149 }
11151 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11153 static void
11155 {
11161 {
11164 {
11170 }
11171 }
11172 }
11174 /* Expand the prologue into a bunch of separate insns. */
11176 void
11178 {
11182 HOST_WIDE_INT allocate;
11188 /* DRAP should not coexist with stack_realign_fp */
11193 /* Initialize CFA state for before the prologue. */
11197 /* Track SP offset to the CFA. We continue tracking this after we've
11198 swapped the CFA register away from SP. In the case of re-alignment
11199 this is fudged; we're interested to offsets within the local frame. */
11206 {
11207 /* We should have already generated an error for any use of
11208 ms_hook on a nested function. */
11211 /* Check if profiling is active and we shall use profiling before
11212 prologue variant. If so sorry. */
11217 /* In ix86_asm_output_function_label we emitted:
11218 8b ff movl.s %edi,%edi
11219 55 push %ebp
11220 8b ec movl.s %esp,%ebp
11222 This matches the hookable function prologue in Win32 API
11223 functions in Microsoft Windows XP Service Pack 2 and newer.
11224 Wine uses this to enable Windows apps to hook the Win32 API
11225 functions provided by Wine.
11227 What that means is that we've already set up the frame pointer. */
11231 {
11234 /* We've decided to use the frame pointer already set up.
11235 Describe this to the unwinder by pretending that both
11236 push and mov insns happen right here.
11238 Putting the unwind info here at the end of the ms_hook
11239 is done so that we can make absolutely certain we get
11240 the required byte sequence at the start of the function,
11241 rather than relying on an assembler that can produce
11242 the exact encoding required.
11244 However it does mean (in the unpatched case) that we have
11245 a 1 insn window where the asynchronous unwind info is
11246 incorrect. However, if we placed the unwind info at
11247 its correct location we would have incorrect unwind info
11248 in the patched case. Which is probably all moot since
11249 I don't expect Wine generates dwarf2 unwind info for the
11250 system libraries that use this feature. */
11256 stack_pointer_rtx);
11264 /* Note that gen_push incremented m->fs.cfa_offset, even
11265 though we didn't emit the push insn here. */
11269 }
11270 else
11271 {
11272 /* The frame pointer is not needed so pop %ebp again.
11273 This leaves us with a pristine state. */
11275 }
11276 }
11278 /* The first insn of a function that accepts its static chain on the
11279 stack is to push the register that would be filled in by a direct
11280 call. This insn will be skipped by the trampoline. */
11282 {
11286 /* We don't want to interpret this push insn as a register save,
11287 only as a stack adjustment. The real copy of the register as
11288 a save will be done later, if needed. */
11293 }
11295 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11296 of DRAP is needed and stack realignment is really needed after reload */
11298 {
11301 /* Only need to push parameter pointer reg if it is caller saved. */
11303 {
11304 /* Push arg pointer reg */
11307 }
11309 /* Grab the argument pointer. */
11316 /* Align the stack. */
11318 stack_pointer_rtx,
11322 /* Replicate the return address on the stack so that return
11323 address can be reached via (argp - 1) slot. This is needed
11324 to implement macro RETURN_ADDR_RTX and intrinsic function
11325 expand_builtin_return_addr etc. */
11331 /* For the purposes of frame and register save area addressing,
11332 we've started over with a new frame. */
11335 }
11341 {
11342 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11343 slower on all targets. Also sdb doesn't like it. */
11347 /* Push registers now, before setting the frame pointer
11348 on SEH target. */
11350 && TARGET_SEH
11352 {
11356 }
11359 {
11367 }
11368 }
11371 {
11372 /* If saving registers via PUSH, do so now. */
11374 {
11378 }
11380 /* When using red zone we may start register saving before allocating
11381 the stack frame saving one cycle of the prologue. However, avoid
11382 doing this if we have to probe the stack; at least on x86_64 the
11383 stack probe can turn into a call that clobbers a red zone location. */
11385 && (! TARGET_STACK_PROBE
11387 {
11390 }
11391 }
11394 {
11398 /* The computation of the size of the re-aligned stack frame means
11399 that we must allocate the size of the register save area before
11400 performing the actual alignment. Otherwise we cannot guarantee
11401 that there's enough storage above the realignment point. */
11408 /* Align the stack. */
11410 stack_pointer_rtx,
11413 /* For the purposes of register save area addressing, the stack
11414 pointer is no longer valid. As for the value of sp_offset,
11415 see ix86_compute_frame_layout, which we need to match in order
11416 to pass verification of stack_pointer_offset at the end. */
11419 }
11424 {
11425 /* We start to count from ARG_POINTER. */
11428 /* If it was realigned, take into account the fake frame. */
11430 {
11437 /* This over-estimates by 1 minimal-stack-alignment-unit but
11438 mitigates that by counting in the new return address slot. */
11439 current_function_dynamic_stack_size
11441 }
11444 }
11446 /* On SEH target with very large frame size, allocate an area to save
11447 SSE registers (as the very large allocation won't be described). */
11451 {
11452 HOST_WIDE_INT sse_size =
11457 /* No need to do stack checking as the area will be immediately
11458 written. */
11465 }
11467 /* The stack has already been decremented by the instruction calling us
11468 so probe if the size is non-negative to preserve the protection area. */
11470 {
11471 /* We expect the registers to be saved when probes are used. */
11475 {
11478 {
11481 }
11482 }
11483 else
11484 {
11491 {
11493 {
11496 }
11497 else
11499 }
11500 else
11501 {
11503 {
11507 }
11508 else
11510 }
11511 }
11512 }
11515 ;
11518 {
11522 }
11523 else
11524 {
11536 {
11539 /* Note that SEH directives need to continue tracking the stack
11540 pointer even after the frame pointer has been set up. */
11542 {
11546 }
11547 }
11550 {
11555 {
11559 }
11560 }
11565 /* Use the fact that AX still contains ALLOCATE. */
11567 ? gen_pro_epilogue_adjust_stack_di_sub
11574 {
11582 }
11585 /* Use stack_pointer_rtx for relative addressing so that code
11586 works for realigned stack, too. */
11588 {
11595 }
11597 {
11602 }
11603 }
11606 /* If we havn't already set up the frame pointer, do so now. */
11608 {
11620 }
11627 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11628 in PROLOGUE. */
11630 {
11636 /* Deleting already emmitted SET_GOT if exist and allocated to
11637 REAL_PIC_OFFSET_TABLE_REGNUM. */
11639 }
11642 {
11643 /* vDRAP is setup but after reload it turns out stack realign
11644 isn't necessary, here we will emit prologue to setup DRAP
11645 without stack realign adjustment */
11648 }
11650 /* Prevent instructions from being scheduled into register save push
11651 sequence when access to the redzone area is done through frame pointer.
11652 The offset between the frame pointer and the stack pointer is calculated
11653 relative to the value of the stack pointer at the end of the function
11654 prologue, and moving instructions that access redzone area via frame
11655 pointer inside push sequence violates this assumption. */
11659 /* Emit cld instruction if stringops are used in the function. */
11663 /* SEH requires that the prologue end within 256 bytes of the start of
11664 the function. Prevent instruction schedules that would extend that.
11665 Further, prevent alloca modifications to the stack pointer from being
11666 combined with prologue modifications. */
11669 }
11671 /* Emit code to restore REG using a POP insn. */
11673 static void
11675 {
11684 {
11685 /* Previously we'd represented the CFA as an expression
11686 like *(%ebp - 8). We've just popped that value from
11687 the stack, which means we need to reset the CFA to
11688 the drap register. This will remain until we restore
11689 the stack pointer. */
11693 /* This means that the DRAP register is valid for addressing too. */
11696 }
11699 {
11706 }
11708 /* When the frame pointer is the CFA, and we pop it, we are
11709 swapping back to the stack pointer as the CFA. This happens
11710 for stack frames that don't allocate other data, so we assume
11711 the stack pointer is now pointing at the return address, i.e.
11712 the function entry state, which makes the offset be 1 word. */
11714 {
11717 {
11725 }
11726 }
11727 }
11729 /* Emit code to restore saved registers using POP insns. */
11731 static void
11733 {
11739 }
11741 /* Emit code and notes for the LEAVE instruction. */
11743 static void
11745 {
11757 {
11765 }
11768 }
11770 /* Emit code to restore saved registers using MOV insns.
11771 First register is restored from CFA - CFA_OFFSET. */
11772 static void
11775 {
11781 {
11790 {
11791 /* Previously we'd represented the CFA as an expression
11792 like *(%ebp - 8). We've just popped that value from
11793 the stack, which means we need to reset the CFA to
11794 the drap register. This will remain until we restore
11795 the stack pointer. */
11799 /* This means that the DRAP register is valid for addressing. */
11801 }
11802 else
11806 }
11807 }
11809 /* Emit code to restore saved registers using MOV insns.
11810 First register is restored from CFA - CFA_OFFSET. */
11811 static void
11814 {
11819 {
11821 rtx mem;
11831 }
11832 }
11834 /* Restore function stack, frame, and registers. */
11836 void
11838 {
11854 /* The FP must be valid if the frame pointer is present. */
11859 /* We must have *some* valid pointer to the stack frame. */
11862 /* The DRAP is never valid at this point. */
11865 /* See the comment about red zone and frame
11866 pointer usage in ix86_expand_prologue. */
11873 /* Determine the CFA offset of the end of the red-zone. */
11876 {
11877 /* The red-zone begins below the return address. */
11880 /* When the register save area is in the aligned portion of
11881 the stack, determine the maximum runtime displacement that
11882 matches up with the aligned frame. */
11886 }
11888 /* Special care must be taken for the normal return case of a function
11889 using eh_return: the eax and edx registers are marked as saved, but
11890 not restored along this path. Adjust the save location to match. */
11894 /* EH_RETURN requires the use of moves to function properly. */
11897 /* SEH requires the use of pops to identify the epilogue. */
11900 /* If we're only restoring one register and sp is not valid then
11901 using a move instruction to restore the register since it's
11902 less work than reloading sp and popping the register. */
11915 && TARGET_USE_LEAVE
11919 else
11923 {
11924 /* Ensure that the entire register save area is addressable via
11925 the stack pointer, if we will restore via sp. */
11930 {
11934 style,
11936 }
11937 }
11939 /* If there are any SSE registers to restore, then we have to do it
11940 via moves, since there's obviously no pop for SSE regs. */
11946 {
11947 rtx t;
11952 /* eh_return epilogues need %ecx added to the stack pointer. */
11954 {
11957 /* Stack align doesn't work with eh_return. */
11959 /* Neither does regparm nested functions. */
11963 {
11971 /* Note that we use SA as a temporary CFA, as the return
11972 address is at the proper place relative to it. We
11973 pretend this happens at the FP restore insn because
11974 prior to this insn the FP would be stored at the wrong
11975 offset relative to SA, and after this insn we have no
11976 other reasonable register to use for the CFA. We don't
11977 bother resetting the CFA to the SP for the duration of
11978 the return insn. */
11991 }
11992 else
11993 {
12001 {
12005 UNITS_PER_WORD));
12007 }
12008 }
12011 }
12012 }
12013 else
12014 {
12015 /* SEH requires that the function end with (1) a stack adjustment
12016 if necessary, (2) a sequence of pops, and (3) a return or
12017 jump instruction. Prevent insns from the function body from
12018 being scheduled into this sequence. */
12020 {
12021 /* Prevent a catch region from being adjacent to the standard
12022 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12023 several other flags that would be interesting to test are
12024 not yet set up. */
12027 else
12029 }
12031 /* First step is to deallocate the stack frame so that we can
12032 pop the registers. Also do it on SEH target for very large
12033 frame as the emitted instructions aren't allowed by the ABI in
12034 epilogues. */
12036 || (TARGET_SEH
12039 {
12044 }
12046 {
12050 style,
12052 }
12055 }
12057 /* If we used a stack pointer and haven't already got rid of it,
12058 then do so now. */
12060 {
12061 /* If the stack pointer is valid and pointing at the frame
12062 pointer store address, then we only need a pop. */
12065 /* Leave results in shorter dependency chains on CPUs that are
12066 able to grok it fast. */
12071 else
12072 {
12074 hard_frame_pointer_rtx,
12077 }
12078 }
12081 {
12083 rtx insn;
12109 }
12111 /* At this point the stack pointer must be valid, and we must have
12112 restored all of the registers. We may not have deallocated the
12113 entire stack frame. We've delayed this until now because it may
12114 be possible to merge the local stack deallocation with the
12115 deallocation forced by ix86_static_chain_on_stack. */
12120 {
12124 }
12125 else
12128 /* Sibcall epilogues don't want a return instruction. */
12130 {
12133 }
12136 {
12139 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12140 address, do explicit add, and jump indirectly to the caller. */
12143 {
12145 rtx insn;
12147 /* There is no "pascal" calling convention in any 64bit ABI. */
12164 }
12165 else
12167 }
12168 else
12171 /* Restore the state back to the state from the prologue,
12172 so that it's correct for the next epilogue. */
12174 }
12176 /* Reset from the function's potential modifications. */
12178 static void
12180 {
12184 #if TARGET_MACHO
12185 /* Mach-O doesn't support labels at the end of objects, so if
12186 it looks like we might want one, insert a NOP. */
12187 {
12193 {
12194 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12195 notes only, instead set their CODE_LABEL_NUMBER to -1,
12196 otherwise there would be code generation differences
12197 in between -g and -g0. */
12201 }
12211 }
12212 #endif
12214 }
12216 /* Return a scratch register to use in the split stack prologue. The
12217 split stack prologue is used for -fsplit-stack. It is the first
12218 instructions in the function, even before the regular prologue.
12219 The scratch register can be any caller-saved register which is not
12220 used for parameters or for the static chain. */
12222 static unsigned int
12224 {
12227 else
12228 {
12241 {
12243 {
12247 }
12249 }
12251 {
12255 }
12257 {
12260 else
12261 {
12263 {
12267 }
12269 }
12270 }
12271 else
12272 {
12273 /* FIXME: We could make this work by pushing a register
12274 around the addition and comparison. */
12277 }
12278 }
12279 }
12281 /* A SYMBOL_REF for the function which allocates new stackspace for
12282 -fsplit-stack. */
12286 /* A SYMBOL_REF for the more stack function when using the large
12287 model. */
12291 /* Handle -fsplit-stack. These are the first instructions in the
12292 function, even before the regular prologue. */
12294 void
12296 {
12298 HOST_WIDE_INT allocate;
12304 rtx fn;
12312 /* This is the label we will branch to if we have enough stack
12313 space. We expect the basic block reordering pass to reverse this
12314 branch if optimizing, so that we branch in the unlikely case. */
12317 /* We need to compare the stack pointer minus the frame size with
12318 the stack boundary in the TCB. The stack boundary always gives
12319 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12320 can compare directly. Otherwise we need to do an addition. */
12323 UNSPEC_STACK_CHECK);
12328 else
12329 {
12331 rtx offset;
12333 /* We need a scratch register to hold the stack pointer minus
12334 the required frame size. Since this is the very start of the
12335 function, the scratch register can be any caller-saved
12336 register which is not used for parameters. */
12343 {
12344 /* We don't use ix86_gen_add3 in this case because it will
12345 want to split to lea, but when not optimizing the insn
12346 will not be split after this point. */
12349 offset)));
12350 }
12351 else
12352 {
12355 stack_pointer_rtx));
12356 }
12358 }
12364 /* Mark the jump as very likely to be taken. */
12369 {
12372 }
12375 /* Get more stack space. We pass in the desired stack space and the
12376 size of the arguments to copy to the new stack. In 32-bit mode
12377 we push the parameters; __morestack will return on a new stack
12378 anyhow. In 64-bit mode we pass the parameters in r10 and
12379 r11. */
12384 {
12390 /* If this function uses a static chain, it will be in %r10.
12391 Preserve it across the call to __morestack. */
12393 {
12394 rtx rax;
12399 }
12403 {
12404 HOST_WIDE_INT argval;
12407 /* When using the large model we need to load the address
12408 into a register, and we've run out of registers. So we
12409 switch to a different calling convention, and we call a
12410 different function: __morestack_large. We pass the
12411 argument size in the upper 32 bits of r10 and pass the
12412 frame size in the lower 32 bits. */
12417 {
12418 split_stack_fn_large =
12421 }
12423 {
12425 rtx x;
12434 UNSPEC_GOT);
12440 }
12441 else
12448 }
12449 else
12450 {
12454 }
12457 }
12458 else
12459 {
12462 }
12468 /* In order to make call/return prediction work right, we now need
12469 to execute a return instruction. See
12470 libgcc/config/i386/morestack.S for the details on how this works.
12472 For flow purposes gcc must not see this as a return
12473 instruction--we need control flow to continue at the subsequent
12474 label. Therefore, we use an unspec. */
12478 /* If we are in 64-bit mode and this function uses a static chain,
12479 we saved %r10 in %rax before calling _morestack. */
12484 /* If this function calls va_start, we need to store a pointer to
12485 the arguments on the old stack, because they may not have been
12486 all copied to the new stack. At this point the old stack can be
12487 found at the frame pointer value used by __morestack, because
12488 __morestack has set that up before calling back to us. Here we
12489 store that pointer in a scratch register, and in
12490 ix86_expand_prologue we store the scratch register in a stack
12491 slot. */
12493 {
12495 rtx frame_reg;
12502 /* 64-bit:
12503 fp -> old fp value
12504 return address within this function
12505 return address of caller of this function
12506 stack arguments
12507 So we add three words to get to the stack arguments.
12509 32-bit:
12510 fp -> old fp value
12511 return address within this function
12512 first argument to __morestack
12513 second argument to __morestack
12514 return address of caller of this function
12515 stack arguments
12516 So we add five words to get to the stack arguments.
12517 */
12528 }
12533 /* If this function calls va_start, we now have to set the scratch
12534 register for the case where we do not call __morestack. In this
12535 case we need to set it based on the stack pointer. */
12537 {
12544 }
12545 }
12547 /* We may have to tell the dataflow pass that the split stack prologue
12548 is initializing a scratch register. */
12550 static void
12552 {
12554 {
12557 }
12558 }
12559 \f
12560 /* Extract the parts of an RTL expression that is a valid memory address
12561 for an instruction. Return 0 if the structure of the address is
12562 grossly off. Return -1 if the address contains ASHIFT, so it is not
12563 strictly valid, but still used for computing length of lea instruction. */
12565 int
12567 {
12572 rtx tmp;
12576 /* Allow zero-extended SImode addresses,
12577 they will be emitted with addr32 prefix. */
12579 {
12582 {
12586 }
12589 {
12596 }
12597 }
12599 /* Allow SImode subregs of DImode addresses,
12600 they will be emitted with addr32 prefix. */
12602 {
12605 {
12609 }
12610 }
12615 {
12618 else
12620 }
12622 {
12627 do
12628 {
12633 }
12640 {
12643 {
12668 /* FALLTHRU */
12672 && TARGET_TLS_DIRECT_SEG_REFS
12675 else
12682 /* FALLTHRU */
12689 else
12704 }
12705 }
12706 }
12708 {
12711 }
12713 {
12714 /* We're called for lea too, which implements ashift on occasion. */
12724 }
12725 else
12729 {
12731 ;
12734 ;
12735 else
12737 }
12739 /* Extract the integral value of scale. */
12741 {
12745 }
12750 /* Avoid useless 0 displacement. */
12754 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12759 {
12762 }
12764 /* Special case: %ebp cannot be encoded as a base without a displacement.
12765 Similarly %r13. */
12767 && base_reg
12776 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12777 Avoid this by transforming to [%esi+0].
12778 Reload calls address legitimization without cfun defined, so we need
12779 to test cfun for being non-NULL. */
12785 /* Special case: encode reg+reg instead of reg*2. */
12789 /* Special case: scaling cannot be encoded without base or displacement. */
12800 }
12801 \f
12802 /* Return cost of the memory address x.
12803 For i386, it is better to use a complex address than let gcc copy
12804 the address into a reg and make a new pseudo. But not if the address
12805 requires to two regs - that would mean more pseudos with longer
12806 lifetimes. */
12807 static int
12809 {
12821 /* Attempt to minimize number of registers in the address. */
12827 cost++;
12829 /* When address base or index is "pic_offset_table_rtx" we don't increase
12830 address cost. When a memopt with "pic_offset_table_rtx" is not invariant
12831 itself it most likely means that base or index is not invariant.
12832 Therefore only "pic_offset_table_rtx" could be hoisted out, which is not
12833 profitable for x86. */
12836 || (!pic_offset_table_rtx
12841 || (!pic_offset_table_rtx
12845 cost++;
12847 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12848 since it's predecode logic can't detect the length of instructions
12849 and it degenerates to vector decoded. Increase cost of such
12850 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12851 to split such addresses or even refuse such addresses at all.
12853 Following addressing modes are affected:
12854 [base+scale*index]
12855 [scale*index+disp]
12856 [base+index]
12858 The first and last case may be avoidable by explicitly coding the zero in
12859 memory address, but I don't have AMD-K6 machine handy to check this
12860 theory. */
12869 }
12870 \f
12871 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12872 this is used for to form addresses to local data when -fPIC is in
12873 use. */
12875 static bool
12877 {
12880 }
12882 /* Determine if a given RTX is a valid constant. We already know this
12883 satisfies CONSTANT_P. */
12885 static bool
12887 {
12888 /* Pointer bounds constants are not valid. */
12893 {
12898 {
12902 }
12907 /* Only some unspecs are valid as "constants". */
12910 {
12926 }
12928 /* We must have drilled down to a symbol. */
12933 /* FALLTHRU */
12936 /* TLS symbols are never valid. */
12940 /* DLLIMPORT symbols are never valid. */
12945 #if TARGET_MACHO
12946 /* mdynamic-no-pic */
12949 #endif
12965 }
12967 /* Otherwise we handle everything else in the move patterns. */
12969 }
12971 /* Determine if it's legal to put X into the constant pool. This
12972 is not possible for the address of thread-local symbols, which
12973 is checked above. */
12975 static bool
12977 {
12978 /* We can always put integral constants and vectors in memory. */
12980 {
12988 }
12990 }
12992 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12993 otherwise zero. */
12995 static bool
12997 {
13003 }
13006 /* Nonzero if the constant value X is a legitimate general operand
13007 when generating PIC code. It is given that flag_pic is on and
13008 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
13010 bool
13012 {
13013 rtx inner;
13016 {
13023 /* Only some unspecs are valid as "constants". */
13026 {
13039 }
13040 /* FALLTHRU */
13048 }
13049 }
13051 /* Determine if a given CONST RTX is a valid memory displacement
13052 in PIC mode. */
13054 bool
13056 {
13059 /* In 64bit mode we can allow direct addresses of symbols and labels
13060 when they are not dynamic symbols. */
13062 {
13066 {
13090 /* FALLTHRU */
13093 /* TLS references should always be enclosed in UNSPEC.
13094 The dllimported symbol needs always to be resolved. */
13100 {
13108 /* Function-symbols need to be resolved only for
13109 large-model.
13110 For the small-model we don't need to resolve anything
13111 here. */
13116 /* Non-external symbols don't need to be resolved for
13117 large, and medium-model. */
13122 }
13125 || (HAVE_LD_PIE_COPYRELOC
13126 && flag_pie
13135 }
13136 }
13142 {
13143 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13144 of GOT tables. We should not need these anyway. */
13156 }
13160 {
13165 }
13174 {
13178 /* We need to check for both symbols and labels because VxWorks loads
13179 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13180 details. */
13184 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13185 While ABI specify also 32bit relocation but we don't produce it in
13186 small PIC model at all. */
13208 }
13211 }
13213 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13214 replace the input X, or the original X if no replacement is called for.
13215 The output parameter *WIN is 1 if the calling macro should goto WIN,
13216 0 if it should not. */
13218 bool
13221 {
13222 /* Reload can generate:
13224 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13225 (reg:DI 97))
13226 (reg:DI 2 cx))
13228 This RTX is rejected from ix86_legitimate_address_p due to
13229 non-strictness of base register 97. Following this rejection,
13230 reload pushes all three components into separate registers,
13231 creating invalid memory address RTX.
13233 Following code reloads only the invalid part of the
13234 memory address RTX. */
13240 {
13246 {
13251 }
13255 {
13260 }
13264 }
13267 }
13269 /* Determine if op is suitable RTX for an address register.
13270 Return naked register if a register or a register subreg is
13271 found, otherwise return NULL_RTX. */
13273 static rtx
13275 {
13278 /* Only SImode or DImode registers can form the address. */
13285 {
13293 /* Don't allow SUBREGs that span more than a word. It can
13294 lead to spill failures when the register is one word out
13295 of a two word structure. */
13299 /* Allow only SUBREGs of non-eliminable hard registers. */
13302 }
13304 /* Op is not a register. */
13306 }
13308 /* Recognizes RTL expressions that are valid memory addresses for an
13309 instruction. The MODE argument is the machine mode for the MEM
13310 expression that wants to use this address.
13312 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13313 convert common non-canonical forms to canonical form so that they will
13314 be recognized. */
13316 static bool
13318 {
13321 HOST_WIDE_INT scale;
13325 /* Decomposition failed. */
13334 /* Validate base register. */
13336 {
13344 /* Base is not valid. */
13346 }
13348 /* Validate index register. */
13350 {
13358 /* Index is not valid. */
13360 }
13362 /* Index and base should have the same mode. */
13367 /* Address override works only on the (%reg) part of %fs:(%reg). */
13373 /* Validate scale factor. */
13375 {
13377 /* Scale without index. */
13381 /* Scale is not a valid multiplier. */
13383 }
13385 /* Validate displacement. */
13387 {
13392 {
13393 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13394 used. While ABI specify also 32bit relocations, we don't produce
13395 them at all and use IP relative instead. */
13402 /* 64bit address unspec. */
13422 /* Invalid address unspec. */
13424 }
13427 && (flag_pic
13428 || (TARGET_MACHO
13429 #if TARGET_MACHO
13430 && MACHOPIC_INDIRECT
13432 #endif
13433 )))
13434 {
13436 is_legitimate_pic:
13438 {
13439 /* foo@dtpoff(%rX) is ok. */
13446 /* Non-constant pic memory reference. */
13448 }
13451 /* Displacement is an invalid pic construct. */
13453 #if TARGET_MACHO
13456 /* displacment must be referenced via non_lazy_pointer */
13458 #endif
13460 /* This code used to verify that a symbolic pic displacement
13461 includes the pic_offset_table_rtx register.
13463 While this is good idea, unfortunately these constructs may
13464 be created by "adds using lea" optimization for incorrect
13465 code like:
13467 int a;
13468 int foo(int i)
13469 {
13470 return *(&a+i);
13471 }
13473 This code is nonsensical, but results in addressing
13474 GOT table with pic_offset_table_rtx base. We can't
13475 just refuse it easily, since it gets matched by
13476 "addsi3" pattern, that later gets split to lea in the
13477 case output register differs from input. While this
13478 can be handled by separate addsi pattern for this case
13479 that never results in lea, this seems to be easier and
13480 correct fix for crash to disable this test. */
13481 }
13488 /* Displacement is not constant. */
13492 /* Displacement is out of range. */
13494 /* In x32 mode, constant addresses are sign extended to 64bit, so
13495 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13500 }
13502 /* Everything looks valid. */
13504 }
13506 /* Determine if a given RTX is a valid constant address. */
13508 bool
13510 {
13512 }
13513 \f
13514 /* Return a unique alias set for the GOT. */
13516 static alias_set_type
13518 {
13523 }
13525 /* Set regs_ever_live for PIC base address register
13526 to true if required. */
13527 static void
13529 {
13532 }
13534 /* Return a legitimate reference for ORIG (an address) using the
13535 register REG. If REG is 0, a new pseudo is generated.
13537 There are two types of references that must be handled:
13539 1. Global data references must load the address from the GOT, via
13540 the PIC reg. An insn is emitted to do this load, and the reg is
13541 returned.
13543 2. Static data references, constant pool addresses, and code labels
13544 compute the address as an offset from the GOT, whose base is in
13545 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13546 differentiate them from global data objects. The returned
13547 address is the PIC reg + an unspec constant.
13549 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13550 reg also appears in the address. */
13552 static rtx
13554 {
13558 #if TARGET_MACHO
13560 {
13563 /* Use the generic Mach-O PIC machinery. */
13565 }
13566 #endif
13569 {
13573 }
13579 {
13580 rtx tmpreg;
13581 /* This symbol may be referenced via a displacement from the PIC
13582 base address (@GOTOFF). */
13588 {
13590 UNSPEC_GOTOFF);
13592 }
13593 else
13598 else
13603 {
13607 }
13608 else
13610 }
13612 {
13613 /* This symbol may be referenced via a displacement from the PIC
13614 base address (@GOTOFF). */
13620 {
13622 UNSPEC_GOTOFF);
13624 }
13625 else
13631 {
13634 }
13635 }
13637 /* We can't use @GOTOFF for text labels on VxWorks;
13638 see gotoff_operand. */
13640 {
13645 /* For x64 PE-COFF there is no GOT table. So we use address
13646 directly. */
13648 {
13656 }
13658 {
13666 /* Use directly gen_movsi, otherwise the address is loaded
13667 into register for CSE. We don't want to CSE this addresses,
13668 instead we CSE addresses from the GOT table, so skip this. */
13671 }
13672 else
13673 {
13674 /* This symbol must be referenced via a load from the
13675 Global Offset Table (@GOT). */
13690 }
13691 }
13692 else
13693 {
13696 {
13698 {
13701 }
13702 else
13704 }
13706 {
13709 /* We must match stuff we generate before. Assume the only
13710 unspecs that can get here are ours. Not that we could do
13711 anything with them anyway.... */
13717 }
13719 {
13722 /* Check first to see if this is a constant offset from a @GOTOFF
13723 symbol reference. */
13726 {
13728 {
13731 UNSPEC_GOTOFF);
13737 {
13740 }
13741 }
13742 else
13743 {
13746 {
13750 }
13751 }
13752 }
13753 else
13754 {
13757 new_rtx
13761 {
13764 {
13767 new_rtx
13769 }
13770 else
13772 }
13773 else
13774 {
13777 {
13780 }
13782 }
13783 }
13784 }
13785 }
13787 }
13788 \f
13789 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13791 static rtx
13793 {
13797 {
13802 }
13808 }
13810 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13814 static rtx
13816 {
13818 {
13824 }
13827 {
13829 UNSPEC_PLTOFF);
13832 }
13835 }
13837 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13841 rtx
13843 {
13845 {
13846 ix86_tls_module_base_symbol
13851 }
13854 }
13856 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13857 false if we expect this to be used for a memory address and true if
13858 we expect to load the address into a register. */
13860 static rtx
13862 {
13868 /* Fall back to global dynamic model if tool chain cannot support local
13869 dynamic. */
13876 {
13881 {
13884 else
13885 {
13888 }
13889 }
13892 {
13895 else
13905 }
13906 else
13907 {
13911 {
13916 emit_call_insn
13926 }
13927 else
13929 }
13936 {
13939 else
13940 {
13943 }
13944 }
13947 {
13952 else
13958 }
13959 else
13960 {
13964 {
13967 rtx eqv;
13970 emit_call_insn
13975 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13976 share the LD_BASE result with other LD model accesses. */
13978 UNSPEC_TLS_LD_BASE);
13982 }
13983 else
13985 }
13993 {
14000 }
14005 {
14007 {
14008 /* The Sun linker took the AMD64 TLS spec literally
14009 and can only handle %rax as destination of the
14010 initial executable code sequence. */
14015 }
14017 /* Generate DImode references to avoid %fs:(%reg32)
14018 problems and linker IE->LE relaxation bug. */
14022 }
14024 {
14028 }
14030 {
14034 }
14035 else
14036 {
14039 }
14049 {
14054 }
14055 else
14056 {
14060 }
14070 {
14074 }
14075 else
14076 {
14080 }
14085 }
14088 }
14090 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14091 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14092 unique refptr-DECL symbol corresponding to symbol DECL. */
14095 {
14099 {
14101 }
14103 static void
14105 {
14111 else
14113 }
14114 };
14118 static tree
14120 {
14126 tree to;
14127 rtx rtl;
14154 else
14167 {
14169 #ifdef SUB_TARGET_RECORD_STUB
14171 #endif
14172 }
14181 }
14183 /* Expand SYMBOL into its corresponding far-addresse symbol.
14184 WANT_REG is true if we require the result be a register. */
14186 static rtx
14188 {
14189 tree imp_decl;
14190 rtx x;
14199 }
14201 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14202 true if we require the result be a register. */
14204 static rtx
14206 {
14207 tree imp_decl;
14208 rtx x;
14217 }
14219 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14220 is true if we require the result be a register. */
14222 static rtx
14224 {
14229 {
14236 {
14239 }
14240 }
14256 {
14259 }
14261 }
14263 /* Try machine-dependent ways of modifying an illegitimate address
14264 to be legitimate. If we find one, return the new, valid address.
14265 This macro is used in only one place: `memory_address' in explow.c.
14267 OLDX is the address as it was before break_out_memory_refs was called.
14268 In some cases it is useful to look at this to decide what needs to be done.
14270 It is always safe for this macro to do nothing. It exists to recognize
14271 opportunities to optimize the output.
14273 For the 80386, we handle X+REG by loading X into a register R and
14274 using R+REG. R will go in a general reg and indexing will be used.
14275 However, if REG is a broken-out memory address or multiplication,
14276 nothing needs to be done because REG can certainly go in a general reg.
14278 When -fpic is used, special handling is needed for symbolic references.
14279 See comments by legitimize_pic_address in i386.c for details. */
14281 static rtx
14283 {
14294 {
14298 }
14301 {
14305 }
14310 #if TARGET_MACHO
14313 #endif
14315 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14319 {
14324 }
14327 {
14328 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14333 {
14339 }
14344 {
14350 }
14352 /* Put multiply first if it isn't already. */
14354 {
14359 }
14361 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14362 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14363 created by virtual register instantiation, register elimination, and
14364 similar optimizations. */
14366 {
14372 }
14374 /* Canonicalize
14375 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14376 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14381 {
14382 rtx constant;
14386 {
14389 }
14391 {
14394 }
14395 else
14399 {
14406 }
14407 }
14413 {
14416 }
14419 {
14422 }
14430 {
14433 }
14439 {
14443 {
14446 }
14450 }
14453 {
14457 {
14460 }
14464 }
14465 }
14468 }
14469 \f
14470 /* Print an integer constant expression in assembler syntax. Addition
14471 and subtraction are the only arithmetic that may appear in these
14472 expressions. FILE is the stdio stream to write to, X is the rtx, and
14473 CODE is the operand print code from the output string. */
14475 static void
14477 {
14481 {
14490 else
14491 {
14494 /* Mark the decl as referenced so that cgraph will
14495 output the function. */
14499 #if TARGET_MACHO
14503 #endif
14505 }
14513 /* FALLTHRU */
14524 /* This used to output parentheses around the expression,
14525 but that does not work on the 386 (either ATT or BSD assembler). */
14531 {
14532 /* We can use %d if the number is <32 bits and positive. */
14537 else
14539 }
14540 else
14541 /* We can't handle floating point constants;
14542 TARGET_PRINT_OPERAND must handle them. */
14547 /* Some assemblers need integer constants to appear first. */
14549 {
14553 }
14554 else
14555 {
14560 }
14575 {
14579 }
14584 {
14603 /* FIXME: This might be @TPOFF in Sun ld too. */
14612 else
14622 else
14628 #if TARGET_MACHO
14633 #endif
14637 }
14642 }
14643 }
14645 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14646 We need to emit DTP-relative relocations. */
14648 static void ATTRIBUTE_UNUSED
14650 {
14655 {
14663 }
14664 }
14666 /* Return true if X is a representation of the PIC register. This copes
14667 with calls from ix86_find_base_term, where the register might have
14668 been replaced by a cselib value. */
14670 static bool
14672 {
14679 {
14687 }
14688 else
14690 }
14692 /* Helper function for ix86_delegitimize_address.
14693 Attempt to delegitimize TLS local-exec accesses. */
14695 static rtx
14697 {
14722 {
14727 }
14733 }
14735 /* In the name of slightly smaller debug output, and to cater to
14736 general assembler lossage, recognize PIC+GOTOFF and turn it back
14737 into a direct symbol reference.
14739 On Darwin, this is necessary to avoid a crash, because Darwin
14740 has a different PIC label for each routine but the DWARF debugging
14741 information is not associated with any particular routine, so it's
14742 necessary to remove references to the PIC label from RTL stored by
14743 the DWARF output code. */
14745 static rtx
14747 {
14749 /* addend is NULL or some rtx if x is something+GOTOFF where
14750 something doesn't include the PIC register. */
14752 /* reg_addend is NULL or a multiple of some register. */
14754 /* const_addend is NULL or a const_int. */
14756 /* This is the result, or NULL. */
14765 {
14772 {
14778 }
14785 {
14788 {
14793 }
14795 }
14800 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14801 and -mcmodel=medium -fpic. */
14802 }
14809 /* %ebx + GOT/GOTOFF */
14810 ;
14812 {
14813 /* %ebx + %reg * scale + GOT/GOTOFF */
14819 else
14820 {
14823 }
14824 }
14825 else
14831 {
14834 }
14855 {
14856 /* If the rest of original X doesn't involve the PIC register, add
14857 addend and subtract pic_offset_table_rtx. This can happen e.g.
14858 for code like:
14859 leal (%ebx, %ecx, 4), %ecx
14860 ...
14861 movl foo@GOTOFF(%ecx), %edx
14862 in which case we return (%ecx - %ebx) + foo
14863 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14864 and reload has completed. */
14868 pic_offset_table_rtx),
14869 result);
14871 {
14875 }
14876 else
14878 }
14880 {
14884 }
14886 }
14888 /* If X is a machine specific address (i.e. a symbol or label being
14889 referenced as a displacement from the GOT implemented using an
14890 UNSPEC), then return the base term. Otherwise return X. */
14892 rtx
14894 {
14895 rtx term;
14898 {
14912 }
14915 }
14916 \f
14917 static void
14920 {
14924 {
14927 }
14932 {
14935 {
14954 }
14958 {
14977 }
14984 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14985 Those same assemblers have the same but opposite lossage on cmov. */
14988 else
14993 {
15006 }
15013 else
15018 {
15031 }
15038 else
15048 else
15059 }
15061 }
15063 /* Print the name of register X to FILE based on its machine mode and number.
15064 If CODE is 'w', pretend the mode is HImode.
15065 If CODE is 'b', pretend the mode is QImode.
15066 If CODE is 'k', pretend the mode is SImode.
15067 If CODE is 'q', pretend the mode is DImode.
15068 If CODE is 'x', pretend the mode is V4SFmode.
15069 If CODE is 't', pretend the mode is V8SFmode.
15070 If CODE is 'g', pretend the mode is V16SFmode.
15071 If CODE is 'h', pretend the reg is the 'high' byte register.
15072 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15073 If CODE is 'd', duplicate the operand for AVX instruction.
15074 */
15076 void
15078 {
15087 {
15091 }
15118 else
15121 /* Irritatingly, AMD extended registers use different naming convention
15122 from the normal registers: "r%d[bwd]" */
15124 {
15129 {
15143 /* no suffix */
15148 }
15150 }
15154 {
15157 {
15160 }
15161 /* FALLTHRU */
15167 /* FALLTHRU */
15170 normal:
15185 {
15190 }
15193 {
15198 }
15202 }
15206 {
15209 else
15211 }
15212 }
15214 /* Meaning of CODE:
15215 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15216 C -- print opcode suffix for set/cmov insn.
15217 c -- like C, but print reversed condition
15218 F,f -- likewise, but for floating-point.
15219 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15220 otherwise nothing
15221 R -- print embeded rounding and sae.
15222 r -- print only sae.
15223 z -- print the opcode suffix for the size of the current operand.
15224 Z -- likewise, with special suffixes for x87 instructions.
15225 * -- print a star (in certain assembler syntax)
15226 A -- print an absolute memory reference.
15227 E -- print address with DImode register names if TARGET_64BIT.
15228 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15229 s -- print a shift double count, followed by the assemblers argument
15230 delimiter.
15231 b -- print the QImode name of the register for the indicated operand.
15232 %b0 would print %al if operands[0] is reg 0.
15233 w -- likewise, print the HImode name of the register.
15234 k -- likewise, print the SImode name of the register.
15235 q -- likewise, print the DImode name of the register.
15236 x -- likewise, print the V4SFmode name of the register.
15237 t -- likewise, print the V8SFmode name of the register.
15238 g -- likewise, print the V16SFmode name of the register.
15239 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15240 y -- print "st(0)" instead of "st" as a register.
15241 d -- print duplicated register operand for AVX instruction.
15242 D -- print condition for SSE cmp instruction.
15243 P -- if PIC, print an @PLT suffix.
15244 p -- print raw symbol name.
15245 X -- don't print any sort of PIC '@' suffix for a symbol.
15246 & -- print some in-use local-dynamic symbol name.
15247 H -- print a memory address offset by 8; used for sse high-parts
15248 Y -- print condition for XOP pcom* instruction.
15249 + -- print a branch hint as 'cs' or 'ds' prefix
15250 ; -- print a semicolon (after prefixes due to bug in older gas).
15251 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15252 @ -- print a segment register of thread base pointer load
15253 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15254 ! -- print MPX prefix for jxx/call/ret instructions if required.
15255 */
15257 void
15259 {
15261 {
15263 {
15266 {
15272 /* Intel syntax. For absolute addresses, registers should not
15273 be surrounded by braces. */
15275 {
15280 }
15285 }
15291 /* Wrap address in an UNSPEC to declare special handling. */
15329 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15334 {
15348 output_operand_lossage
15351 }
15354 #endif
15359 {
15360 /* Opcodes don't get size suffixes if using Intel opcodes. */
15365 {
15383 output_operand_lossage
15386 }
15387 }
15390 warning
15392 /* FALLTHRU */
15395 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15400 {
15402 {
15404 #ifdef HAVE_AS_IX86_FILDS
15406 #endif
15414 #ifdef HAVE_AS_IX86_FILDQ
15416 #else
15418 #endif
15423 }
15424 }
15426 {
15427 /* 387 opcodes don't get size suffixes
15428 if the operands are registers. */
15433 {
15449 }
15450 }
15451 else
15452 {
15453 output_operand_lossage
15456 }
15458 output_operand_lossage
15479 {
15482 }
15487 {
15538 }
15542 /* Little bit of braindamage here. The SSE compare instructions
15543 does use completely different names for the comparisons that the
15544 fp conditional moves. */
15546 {
15549 {
15552 }
15558 {
15561 }
15567 {
15570 }
15579 {
15582 }
15588 {
15591 }
15597 {
15600 }
15611 }
15616 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15619 #endif
15624 {
15628 }
15632 file);
15637 {
15641 }
15642 /* It doesn't actually matter what mode we use here, as we're
15643 only going to use this for printing. */
15645 /* Output 'qword ptr' for intel assembler dialect. */
15654 #ifdef HAVE_AS_IX86_HLE
15656 #else
15658 #endif
15660 #ifdef HAVE_AS_IX86_HLE
15662 #else
15664 #endif
15665 /* We do not want to print value of the operand. */
15694 {
15709 }
15722 {
15727 else
15730 }
15733 {
15734 rtx x;
15743 {
15748 {
15750 bool cputaken
15753 /* Emit hints only in the case default branch prediction
15754 heuristics would fail. */
15756 {
15757 /* We use 3e (DS) prefix for taken branches and
15758 2e (CS) prefix for not taken branches. */
15761 else
15763 }
15764 }
15765 }
15767 }
15770 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15772 #endif
15779 /* The kernel uses a different segment register for performance
15780 reasons; a system call would not have to trash the userspace
15781 segment register, which would be expensive. */
15784 else
15804 }
15805 }
15811 {
15812 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15815 {
15818 {
15827 else
15834 }
15836 /* Check for explicit size override (codes 'b', 'w', 'k',
15837 'q' and 'x') */
15851 }
15854 /* Avoid (%rip) for call operands. */
15860 else
15862 }
15865 {
15866 REAL_VALUE_TYPE r;
15874 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15878 else
15880 }
15883 {
15884 REAL_VALUE_TYPE r;
15893 }
15895 /* These float cases don't actually occur as immediate operands. */
15897 {
15902 }
15904 else
15905 {
15906 /* We have patterns that allow zero sets of memory, for instance.
15907 In 64-bit mode, we should probably support all 8-byte vectors,
15908 since we can in fact encode that into an immediate. */
15910 {
15913 }
15916 {
15918 {
15921 }
15924 {
15927 else
15929 }
15930 }
15935 else
15937 }
15938 }
15940 static bool
15942 {
15945 }
15946 \f
15947 /* Print a memory operand whose address is ADDR. */
15949 static void
15951 {
15960 {
15967 }
15969 {
15973 }
15975 {
15979 {
15982 }
15985 }
15987 {
15992 }
15993 else
16004 {
16015 }
16017 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16019 {
16031 }
16033 {
16034 /* Displacement only requires special attention. */
16037 {
16041 }
16044 else
16046 }
16047 else
16048 {
16049 /* Print SImode register names to force addr32 prefix. */
16051 {
16052 #ifdef ENABLE_CHECKING
16055 {
16066 }
16067 #endif
16070 }
16072 && TARGET_X32
16073 && disp
16076 {
16077 /* X32 runs in 64-bit mode, where displacement, DISP, in
16078 address DISP(%r64), is encoded as 32-bit immediate sign-
16079 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16080 address is %r64 + 0xffffffffbffffd00. When %r64 <
16081 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16082 which is invalid for x32. The correct address is %r64
16083 - 0x40000300 == 0xf7ffdd64. To properly encode
16084 -0x40000300(%r64) for x32, we zero-extend negative
16085 displacement by forcing addr32 prefix which truncates
16086 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16087 zero-extend all negative displacements, including -1(%rsp).
16088 However, for small negative displacements, sign-extension
16089 won't cause overflow. We only zero-extend negative
16090 displacements if they < -16*1024*1024, which is also used
16091 to check legitimate address displacements for PIC. */
16093 }
16096 {
16098 {
16103 else
16105 }
16111 {
16116 }
16118 }
16119 else
16120 {
16124 {
16125 /* Pull out the offset of a symbol; print any symbol itself. */
16129 {
16133 }
16141 else
16143 }
16147 {
16150 {
16154 }
16155 }
16158 else
16162 {
16167 }
16169 }
16170 }
16171 }
16173 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16175 static bool
16177 {
16178 rtx op;
16185 {
16188 /* FIXME: This might be @TPOFF in Sun ld. */
16199 else
16211 else
16218 #if TARGET_MACHO
16224 #endif
16227 {
16232 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16234 #else
16236 #endif
16239 }
16244 }
16247 }
16248 \f
16249 /* Split one or more double-mode RTL references into pairs of half-mode
16250 references. The RTL can be REG, offsettable MEM, integer constant, or
16251 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16252 split and "num" is its length. lo_half and hi_half are output arrays
16253 that parallel "operands". */
16255 void
16258 {
16259 machine_mode half_mode;
16263 {
16272 }
16277 {
16280 /* simplify_subreg refuse to split volatile memory addresses,
16281 but we still have to handle it. */
16283 {
16286 }
16287 else
16288 {
16295 }
16296 }
16297 }
16298 \f
16299 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16300 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16301 is the expression of the binary operation. The output may either be
16302 emitted here, or returned to the caller, like all output_* functions.
16304 There is no guarantee that the operands are the same mode, as they
16305 might be within FLOAT or FLOAT_EXTEND expressions. */
16307 #ifndef SYSV386_COMPAT
16308 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16309 wants to fix the assemblers because that causes incompatibility
16310 with gcc. No-one wants to fix gcc because that causes
16311 incompatibility with assemblers... You can use the option of
16312 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16313 #define SYSV386_COMPAT 1
16314 #endif
16318 {
16324 #ifdef ENABLE_CHECKING
16325 /* Even if we do not want to check the inputs, this documents input
16326 constraints. Which helps in understanding the following code. */
16336 else
16338 #endif
16341 {
16346 else
16355 else
16364 else
16373 else
16380 }
16383 {
16385 {
16389 else
16391 }
16392 else
16393 {
16397 else
16399 }
16401 }
16405 {
16409 {
16413 }
16415 /* know operands[0] == operands[1]. */
16418 {
16421 }
16424 {
16426 /* How is it that we are storing to a dead operand[2]?
16427 Well, presumably operands[1] is dead too. We can't
16428 store the result to st(0) as st(0) gets popped on this
16429 instruction. Instead store to operands[2] (which I
16430 think has to be st(1)). st(1) will be popped later.
16431 gcc <= 2.8.1 didn't have this check and generated
16432 assembly code that the Unixware assembler rejected. */
16434 else
16437 }
16441 else
16448 {
16451 }
16454 {
16457 }
16460 {
16461 #if SYSV386_COMPAT
16462 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16463 derived assemblers, confusingly reverse the direction of
16464 the operation for fsub{r} and fdiv{r} when the
16465 destination register is not st(0). The Intel assembler
16466 doesn't have this brain damage. Read !SYSV386_COMPAT to
16467 figure out what the hardware really does. */
16470 else
16472 #else
16474 /* As above for fmul/fadd, we can't store to st(0). */
16476 else
16478 #endif
16480 }
16483 {
16484 #if SYSV386_COMPAT
16487 else
16489 #else
16492 else
16494 #endif
16496 }
16499 {
16502 else
16505 }
16507 {
16508 #if SYSV386_COMPAT
16510 #else
16512 #endif
16513 }
16514 else
16515 {
16516 #if SYSV386_COMPAT
16518 #else
16520 #endif
16521 }
16526 }
16530 }
16532 /* Check if a 256bit AVX register is referenced inside of EXP. */
16534 static bool
16536 {
16542 }
16544 /* Return needed mode for entity in optimize_mode_switching pass. */
16546 static int
16548 {
16550 {
16551 rtx link;
16553 /* Needed mode is set to AVX_U128_CLEAN if there are
16554 no 256bit modes used in function arguments. */
16556 link;
16558 {
16560 {
16565 }
16566 }
16569 }
16571 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16572 changes state only when a 256bit register is written to, but we need
16573 to prevent the compiler from moving optimal insertion point above
16574 eventual read from 256bit register. */
16581 }
16583 /* Return mode that i387 must be switched into
16584 prior to the execution of insn. */
16586 static int
16588 {
16591 /* The mode UNINITIALIZED is used to store control word after a
16592 function call or ASM pattern. The mode ANY specify that function
16593 has no requirements on the control word and make no changes in the
16594 bits we are interested in. */
16608 {
16631 }
16634 }
16636 /* Return mode that entity must be switched into
16637 prior to the execution of insn. */
16639 static int
16641 {
16643 {
16653 }
16655 }
16657 /* Check if a 256bit AVX register is referenced in stores. */
16659 static void
16661 {
16663 {
16666 }
16667 }
16669 /* Calculate mode of upper 128bit AVX registers after the insn. */
16671 static int
16673 {
16680 /* We know that state is clean after CALL insn if there are no
16681 256bit registers used in the function return register. */
16683 {
16688 }
16690 /* Otherwise, return current mode. Remember that if insn
16691 references AVX 256bit registers, the mode was already changed
16692 to DIRTY from MODE_NEEDED. */
16694 }
16696 /* Return the mode that an insn results in. */
16698 int
16700 {
16702 {
16712 }
16713 }
16715 static int
16717 {
16718 tree arg;
16720 /* Entry mode is set to AVX_U128_DIRTY if there are
16721 256bit modes used in function arguments. */
16724 {
16729 }
16732 }
16734 /* Return a mode that ENTITY is assumed to be
16735 switched to at function entry. */
16737 static int
16739 {
16741 {
16751 }
16752 }
16754 static int
16756 {
16759 /* Exit mode is set to AVX_U128_DIRTY if there are
16760 256bit modes used in the function return register. */
16765 }
16767 /* Return a mode that ENTITY is assumed to be
16768 switched to at function exit. */
16770 static int
16772 {
16774 {
16784 }
16785 }
16787 static int
16789 {
16791 }
16793 /* Output code to initialize control word copies used by trunc?f?i and
16794 rounding patterns. CURRENT_MODE is set to current control word,
16795 while NEW_MODE is set to new control word. */
16797 static void
16799 {
16801 rtx new_mode;
16812 {
16814 {
16816 /* round toward zero (truncate) */
16822 /* round down toward -oo */
16829 /* round up toward +oo */
16836 /* mask precision exception for nearbyint() */
16843 }
16844 }
16845 else
16846 {
16848 {
16850 /* round toward zero (truncate) */
16856 /* round down toward -oo */
16862 /* round up toward +oo */
16868 /* mask precision exception for nearbyint() */
16875 }
16876 }
16882 }
16884 /* Emit vzeroupper. */
16886 void
16888 {
16891 /* Cancel automatic vzeroupper insertion if there are
16892 live call-saved SSE registers at the insertion point. */
16904 }
16906 /* Generate one or more insns to set ENTITY to MODE. */
16908 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16909 is the set of hard registers live at the point where the insn(s)
16910 are to be inserted. */
16912 static void
16914 HARD_REG_SET regs_live)
16915 {
16917 {
16932 }
16933 }
16935 /* Output code for INSN to convert a float to a signed int. OPERANDS
16936 are the insn operands. The output may be [HSD]Imode and the input
16937 operand may be [SDX]Fmode. */
16941 {
16946 /* Jump through a hoop or two for DImode, since the hardware has no
16947 non-popping instruction. We used to do this a different way, but
16948 that was somewhat fragile and broke with post-reload splitters. */
16958 else
16959 {
16964 else
16968 }
16971 }
16973 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16974 have the values zero or one, indicates the ffreep insn's operand
16975 from the OPERANDS array. */
16979 {
16981 #ifdef HAVE_AS_IX86_FFREEP
16983 #else
16984 {
16994 }
16995 #endif
16998 }
17001 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17002 should be used. UNORDERED_P is true when fucom should be used. */
17006 {
17012 {
17015 }
17016 else
17017 {
17020 }
17023 {
17027 else
17029 else
17032 else
17034 }
17041 {
17043 {
17046 }
17047 else
17049 }
17052 && stack_top_dies
17055 {
17056 /* If both the top of the 387 stack dies, and the other operand
17057 is also a stack register that dies, then this must be a
17058 `fcompp' float compare */
17061 {
17062 /* There is no double popping fcomi variant. Fortunately,
17063 eflags is immune from the fstp's cc clobbering. */
17066 else
17069 }
17070 else
17071 {
17074 else
17076 }
17077 }
17078 else
17079 {
17080 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17083 {
17091 NULL,
17092 NULL,
17099 NULL,
17100 NULL,
17101 NULL,
17102 NULL
17103 };
17118 }
17119 }
17121 void
17123 {
17126 #ifdef ASM_QUAD
17129 #else
17131 #endif
17134 }
17136 void
17138 {
17141 #ifdef ASM_QUAD
17144 #else
17146 #endif
17147 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17153 #if TARGET_MACHO
17155 {
17159 }
17160 #endif
17161 else
17164 }
17165 \f
17166 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17167 for the target. */
17169 void
17171 {
17172 rtx tmp;
17174 /* We play register width games, which are only valid after reload. */
17177 /* Avoid HImode and its attendant prefix byte. */
17183 {
17186 }
17189 }
17191 /* X is an unchanging MEM. If it is a constant pool reference, return
17192 the constant pool rtx, else NULL. */
17194 rtx
17196 {
17203 }
17205 void
17207 {
17215 {
17216 rtx tmp;
17220 {
17226 }
17229 }
17233 {
17236 rtx tmp;
17241 else
17245 {
17252 }
17253 }
17257 {
17259 {
17260 #if TARGET_MACHO
17261 /* dynamic-no-pic */
17263 {
17264 rtx temp = ((reload_in_progress
17272 }
17274 {
17278 }
17281 else
17282 {
17290 }
17291 /* dynamic-no-pic */
17292 #endif
17293 }
17294 else
17295 {
17299 {
17305 }
17306 }
17307 }
17308 else
17309 {
17320 /* Force large constants in 64bit compilation into register
17321 to get them CSEed. */
17333 {
17334 /* If we are loading a floating point constant to a register,
17335 force the value to memory now, since we'll get better code
17336 out the back end. */
17340 {
17345 }
17346 }
17347 }
17350 }
17352 void
17354 {
17361 /* Force constants other than zero into memory. We do not know how
17362 the instructions used to build constants modify the upper 64 bits
17363 of the register, once we have that information we may be able
17364 to handle some of them more efficiently. */
17373 /* We need to check memory alignment for SSE mode since attribute
17374 can make operands unaligned. */
17379 {
17382 /* ix86_expand_vector_move_misalign() does not like constants ... */
17388 /* ... nor both arguments in memory. */
17396 }
17398 /* Make operand1 a register if it isn't already. */
17402 {
17405 }
17408 }
17410 /* Split 32-byte AVX unaligned load and store if needed. */
17412 static void
17414 {
17415 rtx m;
17419 machine_mode mode;
17422 {
17443 }
17446 {
17448 {
17455 }
17456 /* Normal *mov<mode>_internal pattern will handle
17457 unaligned loads just fine if misaligned_operand
17458 is true, and without the UNSPEC it can be combined
17459 with arithmetic instructions. */
17462 else
17464 }
17466 {
17468 {
17473 }
17474 else
17476 }
17477 else
17479 }
17481 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17482 straight to ix86_expand_vector_move. */
17483 /* Code generation for scalar reg-reg moves of single and double precision data:
17484 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17485 movaps reg, reg
17486 else
17487 movss reg, reg
17488 if (x86_sse_partial_reg_dependency == true)
17489 movapd reg, reg
17490 else
17491 movsd reg, reg
17493 Code generation for scalar loads of double precision data:
17494 if (x86_sse_split_regs == true)
17495 movlpd mem, reg (gas syntax)
17496 else
17497 movsd mem, reg
17499 Code generation for unaligned packed loads of single precision data
17500 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17501 if (x86_sse_unaligned_move_optimal)
17502 movups mem, reg
17504 if (x86_sse_partial_reg_dependency == true)
17505 {
17506 xorps reg, reg
17507 movlps mem, reg
17508 movhps mem+8, reg
17509 }
17510 else
17511 {
17512 movlps mem, reg
17513 movhps mem+8, reg
17514 }
17516 Code generation for unaligned packed loads of double precision data
17517 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17518 if (x86_sse_unaligned_move_optimal)
17519 movupd mem, reg
17521 if (x86_sse_split_regs == true)
17522 {
17523 movlpd mem, reg
17524 movhpd mem+8, reg
17525 }
17526 else
17527 {
17528 movsd mem, reg
17529 movhpd mem+8, reg
17530 }
17531 */
17533 void
17535 {
17544 {
17546 {
17550 {
17552 {
17555 }
17556 else
17558 }
17560 /* FALLTHRU */
17564 {
17579 }
17585 else
17593 }
17596 }
17600 {
17602 {
17606 {
17608 {
17611 }
17612 else
17614 }
17616 /* FALLTHRU */
17626 }
17629 }
17632 {
17633 /* Normal *mov<mode>_internal pattern will handle
17634 unaligned loads just fine if misaligned_operand
17635 is true, and without the UNSPEC it can be combined
17636 with arithmetic instructions. */
17642 /* ??? If we have typed data, then it would appear that using
17643 movdqu is the only way to get unaligned data loaded with
17644 integer type. */
17646 {
17648 {
17651 }
17653 /* We will eventually emit movups based on insn attributes. */
17657 }
17659 {
17660 rtx zero;
17663 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17664 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17666 {
17667 /* We will eventually emit movups based on insn attributes. */
17670 }
17672 /* When SSE registers are split into halves, we can avoid
17673 writing to the top half twice. */
17675 {
17678 }
17679 else
17680 {
17681 /* ??? Not sure about the best option for the Intel chips.
17682 The following would seem to satisfy; the register is
17683 entirely cleared, breaking the dependency chain. We
17684 then store to the upper half, with a dependency depth
17685 of one. A rumor has it that Intel recommends two movsd
17686 followed by an unpacklpd, but this is unconfirmed. And
17687 given that the dependency depth of the unpacklpd would
17688 still be one, I'm not sure why this would be better. */
17690 }
17696 }
17697 else
17698 {
17699 rtx t;
17702 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17703 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17705 {
17707 {
17710 }
17717 }
17721 else
17726 else
17735 }
17736 }
17738 {
17740 {
17743 /* We will eventually emit movups based on insn attributes. */
17745 }
17747 {
17749 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17750 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17752 /* We will eventually emit movups based on insn attributes. */
17754 else
17755 {
17760 }
17761 }
17762 else
17763 {
17768 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17769 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17771 {
17774 }
17775 else
17776 {
17781 }
17782 }
17783 }
17784 else
17786 }
17788 /* Helper function of ix86_fixup_binary_operands to canonicalize
17789 operand order. Returns true if the operands should be swapped. */
17791 static bool
17793 rtx operands[])
17794 {
17799 /* If the operation is not commutative, we can't do anything. */
17803 /* Highest priority is that src1 should match dst. */
17809 /* Next highest priority is that immediate constants come second. */
17815 /* Lowest priority is that memory references should come second. */
17822 }
17825 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17826 destination to use for the operation. If different from the true
17827 destination in operands[0], a copy operation will be required. */
17829 rtx
17831 rtx operands[])
17832 {
17837 /* Canonicalize operand order. */
17839 {
17840 /* It is invalid to swap operands of different modes. */
17844 }
17846 /* Both source operands cannot be in memory. */
17848 {
17849 /* Optimization: Only read from memory once. */
17851 {
17854 }
17857 else
17859 }
17861 /* If the destination is memory, and we do not have matching source
17862 operands, do things in registers. */
17866 /* Source 1 cannot be a constant. */
17870 /* Source 1 cannot be a non-matching memory. */
17874 /* Improve address combine. */
17883 }
17885 /* Similarly, but assume that the destination has already been
17886 set up properly. */
17888 void
17891 {
17894 }
17896 /* Attempt to expand a binary operator. Make the expansion closer to the
17897 actual machine, then just general_operand, which will allow 3 separate
17898 memory references (one output, two input) in a single insn. */
17900 void
17902 rtx operands[])
17903 {
17910 /* Emit the instruction. */
17914 {
17915 /* Reload doesn't know about the flags register, and doesn't know that
17916 it doesn't want to clobber it. We can only do this with PLUS. */
17919 }
17923 {
17924 /* This is going to be an LEA; avoid splitting it later. */
17926 }
17927 else
17928 {
17931 }
17933 /* Fix up the destination if needed. */
17936 }
17938 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17939 the given OPERANDS. */
17941 void
17943 rtx operands[])
17944 {
17947 {
17950 }
17952 {
17955 }
17956 /* Optimize (__m128i) d | (__m128i) e and similar code
17957 when d and e are float vectors into float vector logical
17958 insn. In C/C++ without using intrinsics there is no other way
17959 to express vector logical operation on float vectors than
17960 to cast them temporarily to integer vectors. */
17962 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17971 {
17972 rtx dst;
17974 {
17983 {
17986 }
17987 else
17988 {
17993 }
18004 }
18005 }
18014 }
18016 /* Return TRUE or FALSE depending on whether the binary operator meets the
18017 appropriate constraints. */
18019 bool
18022 {
18027 /* Both source operands cannot be in memory. */
18031 /* Canonicalize operand order for commutative operators. */
18035 /* If the destination is memory, we must have a matching source operand. */
18039 /* Source 1 cannot be a constant. */
18043 /* Source 1 cannot be a non-matching memory. */
18045 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18053 }
18055 /* Attempt to expand a unary operator. Make the expansion closer to the
18056 actual machine, then just general_operand, which will allow 2 separate
18057 memory references (one output, one input) in a single insn. */
18059 void
18061 rtx operands[])
18062 {
18069 /* If the destination is memory, and we do not have matching source
18070 operands, do things in registers. */
18073 {
18076 else
18078 }
18080 /* When source operand is memory, destination must match. */
18084 /* Emit the instruction. */
18088 {
18089 /* Reload doesn't know about the flags register, and doesn't know that
18090 it doesn't want to clobber it. */
18093 }
18094 else
18095 {
18098 }
18100 /* Fix up the destination if needed. */
18103 }
18105 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18106 divisor are within the range [0-255]. */
18108 void
18111 {
18120 {
18133 }
18140 /* Use 8bit unsigned divimod if dividend and divisor are within
18141 the range [0-255]. */
18150 pc_rtx);
18155 /* Generate original signed/unsigned divimod. */
18160 /* Branch to the end. */
18164 /* Generate 8bit unsigned divide. */
18166 /* Don't use operands[0] for result of 8bit divide since not all
18167 registers support QImode ZERO_EXTRACT. */
18174 {
18177 }
18178 else
18179 {
18182 }
18184 /* Extract remainder from AH. */
18188 else
18189 {
18190 /* Need a new scratch register since the old one has result
18191 of 8bit divide. */
18195 }
18198 /* Zero extend quotient from AL. */
18204 }
18206 #define LEA_MAX_STALL (3)
18207 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18209 /* Increase given DISTANCE in half-cycles according to
18210 dependencies between PREV and NEXT instructions.
18211 Add 1 half-cycle if there is no dependency and
18212 go to next cycle if there is some dependecy. */
18214 static unsigned int
18216 {
18232 }
18234 /* Function checks if instruction INSN defines register number
18235 REGNO1 or REGNO2. */
18237 static bool
18239 rtx insn)
18240 {
18241 df_ref def;
18251 }
18253 /* Function checks if instruction INSN uses register number
18254 REGNO as a part of address expression. */
18256 static bool
18258 {
18259 df_ref use;
18266 }
18268 /* Search backward for non-agu definition of register number REGNO1
18269 or register number REGNO2 in basic block starting from instruction
18270 START up to head of basic block or instruction INSN.
18272 Function puts true value into *FOUND var if definition was found
18273 and false otherwise.
18275 Distance in half-cycles between START and found instruction or head
18276 of BB is added to DISTANCE and returned. */
18278 static int
18282 {
18292 {
18294 {
18297 {
18300 {
18303 }
18304 }
18307 }
18312 }
18315 }
18317 /* Search backward for non-agu definition of register number REGNO1
18318 or register number REGNO2 in INSN's basic block until
18319 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18320 2. Reach neighbour BBs boundary, or
18321 3. Reach agu definition.
18322 Returns the distance between the non-agu definition point and INSN.
18323 If no definition point, returns -1. */
18325 static int
18328 {
18339 {
18340 edge e;
18341 edge_iterator ei;
18346 {
18349 }
18355 else
18356 {
18361 {
18362 int bb_dist
18368 {
18375 }
18376 }
18379 }
18380 }
18382 /* get_attr_type may modify recog data. We want to make sure
18383 that recog data is valid for instruction INSN, on which
18384 distance_non_agu_define is called. INSN is unchanged here. */
18391 }
18393 /* Return the distance in half-cycles between INSN and the next
18394 insn that uses register number REGNO in memory address added
18395 to DISTANCE. Return -1 if REGNO0 is set.
18397 Put true value into *FOUND if register usage was found and
18398 false otherwise.
18399 Put true value into *REDEFINED if register redefinition was
18400 found and false otherwise. */
18402 static int
18406 {
18415 {
18418 /* If insn and start belong to the same bb, set prev to insn,
18419 so the call to increase_distance will increase the distance
18420 between insns by 1. */
18422 }
18427 {
18429 {
18432 {
18433 /* Return DISTANCE if OP0 is used in memory
18434 address in NEXT. */
18437 }
18440 {
18441 /* Return -1 if OP0 is set in NEXT. */
18444 }
18447 }
18453 }
18456 }
18458 /* Return the distance between INSN and the next insn that uses
18459 register number REGNO0 in memory address. Return -1 if no such
18460 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18462 static int
18464 {
18476 {
18477 edge e;
18478 edge_iterator ei;
18483 {
18486 }
18492 else
18493 {
18499 {
18500 int bb_dist
18505 {
18512 }
18513 }
18516 }
18517 }
18523 }
18525 /* Define this macro to tune LEA priority vs ADD, it take effect when
18526 there is a dilemma of choicing LEA or ADD
18527 Negative value: ADD is more preferred than LEA
18528 Zero: Netrual
18529 Positive value: LEA is more preferred than ADD*/
18530 #define IX86_LEA_PRIORITY 0
18532 /* Return true if usage of lea INSN has performance advantage
18533 over a sequence of instructions. Instructions sequence has
18534 SPLIT_COST cycles higher latency than lea latency. */
18536 static bool
18539 {
18542 /* For Silvermont if using a 2-source or 3-source LEA for
18543 non-destructive destination purposes, or due to wanting
18544 ability to use SCALE, the use of LEA is justified. */
18546 {
18554 }
18560 {
18561 /* If there is no non AGU operand definition, no AGU
18562 operand usage and split cost is 0 then both lea
18563 and non lea variants have same priority. Currently
18564 we prefer lea for 64 bit code and non lea on 32 bit
18565 code. */
18568 else
18570 }
18572 /* With longer definitions distance lea is more preferable.
18573 Here we change it to take into account splitting cost and
18574 lea priority. */
18577 /* If there is no use in memory addess then we just check
18578 that split cost exceeds AGU stall. */
18582 /* If this insn has both backward non-agu dependence and forward
18583 agu dependence, the one with short distance takes effect. */
18585 }
18587 /* Return true if it is legal to clobber flags by INSN and
18588 false otherwise. */
18590 static bool
18592 {
18594 df_ref use;
18595 bitmap live;
18598 {
18600 {
18607 }
18613 }
18617 }
18619 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18620 move and add to avoid AGU stalls. */
18622 bool
18624 {
18627 /* Check if we need to optimize. */
18631 /* Check it is correct to split here. */
18639 /* We need to split only adds with non destructive
18640 destination operand. */
18643 else
18645 }
18647 /* Return true if we should emit lea instruction instead of mov
18648 instruction. */
18650 bool
18652 {
18655 /* Check if we need to optimize. */
18659 /* Use lea for reg to reg moves only. */
18667 }
18669 /* Return true if we need to split lea into a sequence of
18670 instructions to avoid AGU stalls. */
18672 bool
18674 {
18680 /* Check we need to optimize. */
18684 /* The "at least two components" test below might not catch simple
18685 move or zero extension insns if parts.base is non-NULL and parts.disp
18686 is const0_rtx as the only components in the address, e.g. if the
18687 register is %rbp or %r13. As this test is much cheaper and moves or
18688 zero extensions are the common case, do this check first. */
18694 /* Check if it is OK to split here. */
18701 /* There should be at least two components in the address. */
18706 /* We should not split into add if non legitimate pic
18707 operand is used as displacement. */
18722 /* Compute how many cycles we will add to execution time
18723 if split lea into a sequence of instructions. */
18725 {
18726 /* Have to use mov instruction if non desctructive
18727 destination form is used. */
18731 /* Have to add index to base if both exist. */
18735 /* Have to use shift and adds if scale is 2 or greater. */
18737 {
18742 else
18744 }
18746 /* Have to use add instruction with immediate if
18747 disp is non zero. */
18751 /* Subtract the price of lea. */
18753 }
18757 }
18759 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18760 matches destination. RTX includes clobber of FLAGS_REG. */
18762 static void
18765 {
18772 }
18774 /* Return true if regno1 def is nearest to the insn. */
18776 static bool
18778 {
18785 {
18787 {
18790 }
18796 }
18798 /* None of the regs is defined in the bb. */
18800 }
18802 /* Split lea instructions into a sequence of instructions
18803 which are executed on ALU to avoid AGU stalls.
18804 It is assumed that it is allowed to clobber flags register
18805 at lea position. */
18807 void
18809 {
18825 {
18828 }
18831 {
18834 }
18840 {
18841 /* Case r1 = r1 + ... */
18843 {
18844 /* If we have a case r1 = r1 + C * r2 then we
18845 should use multiplication which is very
18846 expensive. Assume cost model is wrong if we
18847 have such case here. */
18852 }
18853 else
18854 {
18855 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18859 /* Use shift for scaling. */
18868 }
18869 }
18871 {
18874 }
18875 else
18876 {
18878 {
18881 }
18883 {
18886 }
18887 else
18888 {
18893 else
18894 {
18895 rtx tmp1;
18897 /* Find better operand for SET instruction, depending
18898 on which definition is farther from the insn. */
18901 else
18911 }
18914 }
18918 }
18919 }
18921 /* Return true if it is ok to optimize an ADD operation to LEA
18922 operation to avoid flag register consumation. For most processors,
18923 ADD is faster than LEA. For the processors like BONNELL, if the
18924 destination register of LEA holds an actual address which will be
18925 used soon, LEA is better and otherwise ADD is better. */
18927 bool
18929 {
18934 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18942 }
18944 /* Return true if destination reg of SET_BODY is shift count of
18945 USE_BODY. */
18947 static bool
18949 {
18950 rtx set_dest;
18951 rtx shift_rtx;
18954 /* Retrieve destination of SET_BODY. */
18956 {
18965 use_body))
18970 }
18972 /* Retrieve shift count of USE_BODY. */
18974 {
18986 }
18994 {
18997 /* Return true if shift count is dest of SET_BODY. */
18999 {
19000 /* Add check since it can be invoked before register
19001 allocation in pre-reload schedule. */
19007 }
19008 }
19011 }
19013 /* Return true if destination reg of SET_INSN is shift count of
19014 USE_INSN. */
19016 bool
19018 {
19021 }
19023 /* Return TRUE or FALSE depending on whether the unary operator meets the
19024 appropriate constraints. */
19026 bool
19028 machine_mode,
19030 {
19031 /* If one of operands is memory, source and destination must match. */
19037 }
19039 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19040 are ok, keeping in mind the possible movddup alternative. */
19042 bool
19044 {
19050 }
19052 /* Post-reload splitter for converting an SF or DFmode value in an
19053 SSE register into an unsigned SImode. */
19055 void
19057 {
19058 machine_mode vecmode;
19068 /* Load up the value into the low element. We must ensure that the other
19069 elements are valid floats -- zero is the easiest such value. */
19071 {
19074 else
19076 }
19077 else
19078 {
19083 else
19085 }
19105 else
19110 }
19112 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19113 Expects the 64-bit DImode to be supplied in a pair of integral
19114 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19115 -mfpmath=sse, !optimize_size only. */
19117 void
19119 {
19123 rtx x;
19129 {
19132 }
19133 else
19134 {
19138 }
19146 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19149 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19150 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19151 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19152 (0x1.0p84 + double(fp_value_hi_xmm)).
19153 Note these exponents differ by 32. */
19157 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19158 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19167 /* Add the upper and lower DFmode values together. */
19170 else
19171 {
19175 }
19178 }
19180 /* Not used, but eases macroization of patterns. */
19181 void
19183 {
19185 }
19187 /* Convert an unsigned SImode value into a DFmode. Only currently used
19188 for SSE, but applicable anywhere. */
19190 void
19192 {
19193 REAL_VALUE_TYPE TWO31r;
19208 }
19210 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19211 32-bit mode; otherwise we have a direct convert instruction. */
19213 void
19215 {
19216 REAL_VALUE_TYPE TWO32r;
19234 }
19236 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19237 For x86_32, -mfpmath=sse, !optimize_size only. */
19238 void
19240 {
19241 REAL_VALUE_TYPE ONE16r;
19260 }
19262 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19263 a vector of unsigned ints VAL to vector of floats TARGET. */
19265 void
19267 {
19269 REAL_VALUE_TYPE TWO16r;
19276 else
19281 OPTAB_DIRECT);
19292 OPTAB_DIRECT);
19294 OPTAB_DIRECT);
19297 }
19299 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19300 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19301 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19302 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19304 rtx
19306 {
19307 REAL_VALUE_TYPE TWO31r;
19322 {
19328 }
19337 OPTAB_DIRECT);
19338 else
19339 {
19345 OPTAB_DIRECT);
19346 }
19349 }
19351 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19352 then replicate the value for all elements of the vector
19353 register. */
19355 rtx
19357 {
19359 rtvec v;
19360 machine_mode scalar_mode;
19363 {
19396 }
19397 }
19399 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19400 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19401 for an SSE register. If VECT is true, then replicate the mask for
19402 all elements of the vector register. If INVERT is true, then create
19403 a mask excluding the sign bit. */
19405 rtx
19407 {
19411 rtx v;
19412 rtx mask;
19414 /* Find the sign bit, sign extended to 2*HWI. */
19416 {
19440 else
19448 {
19451 }
19452 else
19453 {
19454 rtvec vec;
19460 {
19463 }
19464 else
19474 }
19479 }
19484 /* Force this value into the low part of a fp vector constant. */
19493 }
19495 /* Generate code for floating point ABS or NEG. */
19497 void
19499 rtx operands[])
19500 {
19511 {
19517 }
19519 /* NEG and ABS performed with SSE use bitwise mask operations.
19520 Create the appropriate mask now. */
19523 else
19533 {
19535 rtvec par;
19540 else
19541 {
19544 }
19546 }
19547 else
19549 }
19551 /* Expand a copysign operation. Special case operand 0 being a constant. */
19553 void
19555 {
19569 else
19573 {
19580 {
19583 else
19584 {
19588 }
19589 }
19599 else
19603 }
19604 else
19605 {
19615 else
19619 }
19620 }
19622 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19623 be a constant, and so has already been expanded into a vector constant. */
19625 void
19627 {
19643 {
19646 }
19647 }
19649 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19650 so we have to do two masks. */
19652 void
19654 {
19669 {
19670 /* Shouldn't happen often (it's useless, obviously), but when it does
19671 we'd generate incorrect code if we continue below. */
19674 }
19677 {
19688 }
19689 else
19690 {
19692 {
19694 }
19696 {
19700 }
19704 {
19707 }
19709 {
19714 }
19716 }
19720 }
19722 /* Return TRUE or FALSE depending on whether the first SET in INSN
19723 has source and destination with matching CC modes, and that the
19724 CC mode is at least as constrained as REQ_MODE. */
19726 bool
19728 {
19729 rtx set;
19730 machine_mode set_mode;
19740 {
19750 /* FALLTHRU */
19754 /* FALLTHRU */
19758 /* FALLTHRU */
19772 }
19775 }
19777 /* Generate insn patterns to do an integer compare of OPERANDS. */
19779 static rtx
19781 {
19782 machine_mode cmpmode;
19788 /* This is very simple, but making the interface the same as in the
19789 FP case makes the rest of the code easier. */
19793 /* Return the test that should be put into the flags user, i.e.
19794 the bcc, scc, or cmov instruction. */
19796 }
19798 /* Figure out whether to use ordered or unordered fp comparisons.
19799 Return the appropriate mode to use. */
19801 machine_mode
19803 {
19804 /* ??? In order to make all comparisons reversible, we do all comparisons
19805 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19806 all forms trapping and nontrapping comparisons, we can make inequality
19807 comparisons trapping again, since it results in better code when using
19808 FCOM based compares. */
19810 }
19812 machine_mode
19814 {
19818 {
19821 }
19824 {
19825 /* Only zero flag is needed. */
19829 /* Codes needing carry flag. */
19832 /* Detect overflow checks. They need just the carry flag. */
19836 else
19841 /* Codes possibly doable only with sign flag when
19842 comparing against zero. */
19847 else
19848 /* For other cases Carry flag is not required. */
19850 /* Codes doable only with sign flag when comparing
19851 against zero, but we miss jump instruction for it
19852 so we need to use relational tests against overflow
19853 that thus needs to be zero. */
19858 else
19860 /* strcmp pattern do (use flags) and combine may ask us for proper
19861 mode. */
19866 }
19867 }
19869 /* Return the fixed registers used for condition codes. */
19871 static bool
19873 {
19877 }
19879 /* If two condition code modes are compatible, return a condition code
19880 mode which is compatible with both. Otherwise, return
19881 VOIDmode. */
19883 static machine_mode
19885 {
19902 {
19916 {
19930 }
19934 /* These are only compatible with themselves, which we already
19935 checked above. */
19937 }
19938 }
19941 /* Return a comparison we can do and that it is equivalent to
19942 swap_condition (code) apart possibly from orderedness.
19943 But, never change orderedness if TARGET_IEEE_FP, returning
19944 UNKNOWN in that case if necessary. */
19946 static enum rtx_code
19948 {
19950 {
19961 }
19962 }
19964 /* Return cost of comparison CODE using the best strategy for performance.
19965 All following functions do use number of instructions as a cost metrics.
19966 In future this should be tweaked to compute bytes for optimize_size and
19967 take into account performance of various instructions on various CPUs. */
19969 static int
19971 {
19974 /* The cost of code using bit-twiddling on %ah. */
19976 {
19999 }
20002 {
20009 }
20010 }
20012 /* Return strategy to use for floating-point. We assume that fcomi is always
20013 preferrable where available, since that is also true when looking at size
20014 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20016 enum ix86_fpcmp_strategy
20018 {
20019 /* Do fcomi/sahf based test when profitable. */
20028 }
20030 /* Swap, force into registers, or otherwise massage the two operands
20031 to a fp comparison. The operands are updated in place; the new
20032 comparison code is returned. */
20034 static enum rtx_code
20036 {
20042 /* All of the unordered compare instructions only work on registers.
20043 The same is true of the fcomi compare instructions. The XFmode
20044 compare instructions require registers except when comparing
20045 against zero or when converting operand 1 from fixed point to
20046 floating point. */
20055 {
20058 }
20059 else
20060 {
20061 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20062 things around if they appear profitable, otherwise force op0
20063 into a register. */
20069 {
20072 {
20075 }
20076 }
20082 {
20087 {
20090 }
20091 else
20093 }
20094 }
20096 /* Try to rearrange the comparison to make it cheaper. */
20100 {
20105 }
20110 }
20112 /* Convert comparison codes we use to represent FP comparison to integer
20113 code that will result in proper branch. Return UNKNOWN if no such code
20114 is available. */
20116 enum rtx_code
20118 {
20120 {
20143 }
20144 }
20146 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20148 static rtx
20150 {
20157 /* Do fcomi/sahf based test when profitable. */
20159 {
20164 tmp);
20172 tmp);
20181 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20188 /* In the unordered case, we have to check C2 for NaN's, which
20189 doesn't happen to work out to anything nice combination-wise.
20190 So do some bit twiddling on the value we've got in AH to come
20191 up with an appropriate set of condition codes. */
20195 {
20199 {
20202 }
20203 else
20204 {
20210 }
20215 {
20220 }
20221 else
20222 {
20225 }
20230 {
20233 }
20234 else
20235 {
20239 }
20244 {
20250 }
20251 else
20252 {
20255 }
20260 {
20265 }
20266 else
20267 {
20270 }
20275 {
20280 }
20281 else
20282 {
20285 }
20299 }
20304 }
20306 /* Return the test that should be put into the flags user, i.e.
20307 the bcc, scc, or cmov instruction. */
20310 const0_rtx);
20311 }
20313 static rtx
20315 {
20316 rtx ret;
20322 {
20325 }
20326 else
20330 }
20332 void
20334 {
20336 rtx tmp;
20339 {
20346 simple:
20350 pc_rtx);
20358 /* Expand DImode branch into multiple compare+branch. */
20359 {
20363 machine_mode submode;
20366 {
20369 }
20376 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20377 avoid two branches. This costs one extra insn, so disable when
20378 optimizing for size. */
20383 {
20401 }
20403 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20404 op1 is a constant and the low word is zero, then we can just
20405 examine the high word. Similarly for low word -1 and
20406 less-or-equal-than or greater-than. */
20410 {
20413 {
20416 }
20420 {
20423 }
20427 }
20429 /* Otherwise, we need two or three jumps. */
20438 {
20452 }
20454 /*
20455 * a < b =>
20456 * if (hi(a) < hi(b)) goto true;
20457 * if (hi(a) > hi(b)) goto false;
20458 * if (lo(a) < lo(b)) goto true;
20459 * false:
20460 */
20472 }
20477 }
20478 }
20480 /* Split branch based on floating point condition. */
20481 void
20484 {
20485 rtx condition;
20486 rtx i;
20489 {
20494 }
20497 tmp);
20505 }
20507 void
20509 {
20510 rtx ret;
20517 }
20519 /* Expand comparison setting or clearing carry flag. Return true when
20520 successful and set pop for the operation. */
20521 static bool
20523 {
20524 machine_mode mode =
20527 /* Do not handle double-mode compares that go through special path. */
20532 {
20533 rtx compare_op;
20538 /* Shortcut: following common codes never translate
20539 into carry flag compares. */
20544 /* These comparisons require zero flag; swap operands so they won't. */
20547 {
20550 }
20552 /* Try to expand the comparison and verify that we end up with
20553 carry flag based comparison. This fails to be true only when
20554 we decide to expand comparison using arithmetic that is not
20555 too common scenario. */
20564 else
20573 }
20579 {
20584 /* Convert a==0 into (unsigned)a<1. */
20593 /* Convert a>b into b<a or a>=b-1. */
20597 {
20599 /* Bail out on overflow. We still can swap operands but that
20600 would force loading of the constant into register. */
20605 }
20606 else
20607 {
20610 }
20613 /* Convert a>=0 into (unsigned)a<0x80000000. */
20631 }
20632 /* Swapping operands may cause constant to appear as first operand. */
20634 {
20638 }
20642 }
20644 bool
20646 {
20649 rtx compare_op;
20671 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20672 HImode insns, we'd be swallowed in word prefix ops. */
20678 {
20682 HOST_WIDE_INT diff;
20685 /* Sign bit compares are better done using shifts than we do by using
20686 sbb. */
20689 {
20690 /* Detect overlap between destination and compare sources. */
20694 {
20695 rtx flags;
20704 {
20706 compare_code
20708 }
20710 /* To simplify rest of code, restrict to the GEU case. */
20712 {
20718 }
20719 else
20720 {
20723 reverse_condition_maybe_unordered
20725 else
20728 }
20737 else
20740 }
20741 else
20742 {
20745 else
20746 {
20751 }
20753 }
20756 {
20757 /*
20758 * cmpl op0,op1
20759 * sbbl dest,dest
20760 * [addl dest, ct]
20761 *
20762 * Size 5 - 8.
20763 */
20768 }
20770 {
20771 /*
20772 * cmpl op0,op1
20773 * sbbl dest,dest
20774 * orl $ct, dest
20775 *
20776 * Size 8.
20777 */
20781 }
20783 {
20784 /*
20785 * cmpl op0,op1
20786 * sbbl dest,dest
20787 * notl dest
20788 * [addl dest, cf]
20789 *
20790 * Size 8 - 11.
20791 */
20797 }
20798 else
20799 {
20800 /*
20801 * cmpl op0,op1
20802 * sbbl dest,dest
20803 * [notl dest]
20804 * andl cf - ct, dest
20805 * [addl dest, ct]
20806 *
20807 * Size 8 - 11.
20808 */
20811 {
20815 }
20825 }
20831 }
20834 {
20841 {
20844 /* We may be reversing unordered compare to normal compare, that
20845 is not valid in general (we may convert non-trapping condition
20846 to trapping one), however on i386 we currently emit all
20847 comparisons unordered. */
20850 }
20851 else
20852 {
20855 }
20856 }
20861 {
20866 {
20871 }
20872 }
20874 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20878 {
20879 /* If lea code below could be used, only optimize
20880 if it results in a 2 insn sequence. */
20886 {
20887 /*
20888 * notl op1 (if necessary)
20889 * sarl $31, op1
20890 * orl cf, op1
20891 */
20893 {
20897 }
20908 }
20909 }
20917 {
20918 /*
20919 * xorl dest,dest
20920 * cmpl op1,op2
20921 * setcc dest
20922 * lea cf(dest*(ct-cf)),dest
20923 *
20924 * Size 14.
20925 *
20926 * This also catches the degenerate setcc-only case.
20927 */
20929 rtx tmp;
20935 /* On x86_64 the lea instruction operates on Pmode, so we need
20936 to get arithmetics done in proper mode to match. */
20939 else
20940 {
20941 rtx out1;
20944 nops++;
20946 {
20948 nops++;
20949 }
20950 }
20952 {
20954 nops++;
20955 }
20957 {
20960 else
20962 }
20967 }
20969 /*
20970 * General case: Jumpful:
20971 * xorl dest,dest cmpl op1, op2
20972 * cmpl op1, op2 movl ct, dest
20973 * setcc dest jcc 1f
20974 * decl dest movl cf, dest
20975 * andl (cf-ct),dest 1:
20976 * addl ct,dest
20977 *
20978 * Size 20. Size 14.
20979 *
20980 * This is reasonably steep, but branch mispredict costs are
20981 * high on modern cpus, so consider failing only if optimizing
20982 * for space.
20983 */
20988 {
20990 {
20997 {
21000 /* We may be reversing unordered compare to normal compare,
21001 that is not valid in general (we may convert non-trapping
21002 condition to trapping one), however on i386 we currently
21003 emit all comparisons unordered. */
21005 }
21006 else
21007 {
21011 }
21012 }
21015 {
21016 /* notl op1 (if needed)
21017 sarl $31, op1
21018 andl (cf-ct), op1
21019 addl ct, op1
21021 For x < 0 (resp. x <= -1) there will be no notl,
21022 so if possible swap the constants to get rid of the
21023 complement.
21024 True/false will be -1/0 while code below (store flag
21025 followed by decrement) is 0/-1, so the constants need
21026 to be exchanged once more. */
21029 {
21032 }
21033 else
21037 }
21038 else
21039 {
21043 constm1_rtx,
21045 }
21057 }
21058 }
21061 {
21062 /* Try a few things more with specific constants and a variable. */
21064 optab op;
21070 /* If one of the two operands is an interesting constant, load a
21071 constant with the above and mask it in with a logical operation. */
21074 {
21080 else
21082 }
21084 {
21090 else
21092 }
21093 else
21100 /* Recurse to get the constant loaded. */
21104 /* Mask in the interesting variable. */
21106 OPTAB_WIDEN);
21111 }
21113 /*
21114 * For comparison with above,
21115 *
21116 * movl cf,dest
21117 * movl ct,tmp
21118 * cmpl op1,op2
21119 * cmovcc tmp,dest
21120 *
21121 * Size 15.
21122 */
21144 }
21146 /* Swap, force into registers, or otherwise massage the two operands
21147 to an sse comparison with a mask result. Thus we differ a bit from
21148 ix86_prepare_fp_compare_args which expects to produce a flags result.
21150 The DEST operand exists to help determine whether to commute commutative
21151 operators. The POP0/POP1 operands are updated in place. The new
21152 comparison code is returned, or UNKNOWN if not implementable. */
21154 static enum rtx_code
21157 {
21159 {
21162 /* AVX supports all the needed comparisons. */
21165 /* We have no LTGT as an operator. We could implement it with
21166 NE & ORDERED, but this requires an extra temporary. It's
21167 not clear that it's worth it. */
21174 /* These are supported directly. */
21181 /* AVX has 3 operand comparisons, no need to swap anything. */
21184 /* For commutative operators, try to canonicalize the destination
21185 operand to be first in the comparison - this helps reload to
21186 avoid extra moves. */
21189 /* FALLTHRU */
21195 /* These are not supported directly before AVX, and furthermore
21196 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21197 comparison operands to transform into something that is
21198 supported. */
21205 }
21208 }
21210 /* Detect conditional moves that exactly match min/max operational
21211 semantics. Note that this is IEEE safe, as long as we don't
21212 interchange the operands.
21214 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21215 and TRUE if the operation is successful and instructions are emitted. */
21217 static bool
21220 {
21221 machine_mode mode;
21223 rtx tmp;
21226 ;
21229 else
21236 else
21241 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21242 but MODE may be a vector mode and thus not appropriate. */
21244 {
21246 rtvec v;
21251 }
21252 else
21253 {
21256 }
21260 }
21262 /* Expand an sse vector comparison. Return the register with the result. */
21264 static rtx
21267 {
21271 /* In general case result of comparison can differ from operands' type. */
21272 machine_mode cmp_mode;
21274 /* In AVX512F the result of comparison is an integer mask. */
21276 rtx x;
21279 {
21284 }
21285 else
21298 /* Compare patterns for int modes are unspec in AVX512F only. */
21300 {
21304 {
21313 }
21316 {
21319 }
21320 }
21324 {
21327 }
21328 else
21332 }
21334 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21335 operations. This is used for both scalar and vector conditional moves. */
21337 static void
21339 {
21343 /* In AVX512F the result of comparison is an integer mask. */
21351 {
21353 }
21356 {
21360 }
21363 {
21368 }
21371 {
21375 }
21378 {
21386 op_true,
21387 op_false)));
21388 }
21389 else
21390 {
21400 {
21414 {
21421 }
21436 {
21443 }
21467 }
21470 {
21474 }
21475 else
21476 {
21482 else
21494 }
21495 }
21496 }
21498 /* Expand a floating-point conditional move. Return true if successful. */
21500 bool
21502 {
21510 {
21511 machine_mode cmode;
21513 /* Since we've no cmove for sse registers, don't force bad register
21514 allocation just to gain access to it. Deny movcc when the
21515 comparison mode doesn't match the move mode. */
21534 }
21541 /* The floating point conditional move instructions don't directly
21542 support conditions resulting from a signed integer comparison. */
21546 {
21551 }
21558 }
21560 /* Expand a floating-point vector conditional move; a vcond operation
21561 rather than a movcc operation. */
21563 bool
21565 {
21567 rtx cmp;
21572 {
21573 rtx temp;
21575 {
21592 }
21594 OPTAB_DIRECT);
21597 }
21607 }
21609 /* Expand a signed/unsigned integral vector conditional move. */
21611 bool
21613 {
21623 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21624 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21633 {
21637 {
21643 }
21646 {
21652 }
21653 }
21662 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21666 ;
21667 else
21668 {
21669 /* Canonicalize the comparison to EQ, GT, GTU. */
21671 {
21688 /* FALLTHRU */
21698 }
21700 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21702 {
21704 {
21706 /* SSE4.1 supports EQ. */
21713 /* SSE4.2 supports GT/GTU. */
21720 }
21721 }
21723 /* Unsigned parallel compare is not supported by the hardware.
21724 Play some tricks to turn this into a signed comparison
21725 against 0. */
21727 {
21731 {
21738 {
21743 {
21752 }
21753 /* Subtract (-(INT MAX) - 1) from both operands to make
21754 them signed. */
21765 }
21774 /* Perform a parallel unsigned saturating subtraction. */
21787 }
21788 }
21789 }
21791 /* Allow the comparison to be done in one mode, but the movcc to
21792 happen in another mode. */
21794 {
21797 }
21798 else
21799 {
21805 }
21810 }
21812 /* AVX512F does support 64-byte integer vector operations,
21813 thus the longest vector we are faced with is V64QImode. */
21814 #define MAX_VECT_LEN 64
21816 struct expand_vec_perm_d
21817 {
21820 machine_mode vmode;
21824 };
21826 static bool
21829 {
21830 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21831 expander, so args are either in d, or in op0, op1 etc. */
21837 {
21868 {
21871 }
21875 {
21878 }
21882 {
21885 }
21901 {
21904 }
21908 {
21911 }
21915 {
21918 }
21922 }
21927 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21928 expander, so args are either in d, or in op0, op1 etc. */
21930 {
21938 }
21942 }
21944 /* Expand a variable vector permutation. */
21946 void
21948 {
21959 /* Number of elements in the vector. */
21968 {
21970 {
21971 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21972 an constant shuffle operand. With a tiny bit of effort we can
21973 use VPERMD instead. A re-interpretation stall for V4DFmode is
21974 unfortunate but there's no avoiding it.
21975 Similarly for V16HImode we don't have instructions for variable
21976 shuffling, while for V32QImode we can use after preparing suitable
21977 masks vpshufb; vpshufb; vpermq; vpor. */
21980 {
21984 }
21985 else
21986 {
21990 }
21993 /* Replicate the low bits of the V4DImode mask into V8SImode:
21994 mask = { A B C D }
21995 t1 = { A A B B C C D D }. */
22003 else
22006 /* Multiply the shuffle indicies by two. */
22008 OPTAB_DIRECT);
22010 /* Add one to the odd shuffle indicies:
22011 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22013 {
22016 }
22020 OPTAB_DIRECT);
22022 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22027 }
22030 {
22032 /* The VPERMD and VPERMPS instructions already properly ignore
22033 the high bits of the shuffle elements. No need for us to
22034 perform an AND ourselves. */
22036 {
22041 }
22042 else
22043 {
22049 }
22056 else
22057 {
22063 }
22067 /* By combining the two 128-bit input vectors into one 256-bit
22068 input vector, we can use VPERMD and VPERMPS for the full
22069 two-operand shuffle. */
22101 /* From mask create two adjusted masks, which contain the same
22102 bits as mask in the low 7 bits of each vector element.
22103 The first mask will have the most significant bit clear
22104 if it requests element from the same 128-bit lane
22105 and MSB set if it requests element from the other 128-bit lane.
22106 The second mask will have the opposite values of the MSB,
22107 and additionally will have its 128-bit lanes swapped.
22108 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22109 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22110 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22111 stands for other 12 bytes. */
22112 /* The bit whether element is from the same lane or the other
22113 lane is bit 4, so shift it up by 3 to the MSB position. */
22117 /* Clear MSB bits from the mask just in case it had them set. */
22119 /* After this t1 will have MSB set for elements from other lane. */
22121 /* Clear bits other than MSB. */
22123 /* Or in the lower bits from mask into t3. */
22125 /* And invert MSB bits in t1, so MSB is set for elements from the same
22126 lane. */
22128 /* Swap 128-bit lanes in t3. */
22133 /* And or in the lower bits from mask into t1. */
22136 {
22137 /* Each of these shuffles will put 0s in places where
22138 element from the other 128-bit lane is needed, otherwise
22139 will shuffle in the requested value. */
22143 /* For t3 the 128-bit lanes are swapped again. */
22148 /* And oring both together leads to the result. */
22155 }
22158 /* Similarly to the above one_operand_shuffle code,
22159 just for repeated twice for each operand. merge_two:
22160 code will merge the two results together. */
22184 }
22185 }
22188 {
22189 /* The XOP VPPERM insn supports three inputs. By ignoring the
22190 one_operand_shuffle special case, we avoid creating another
22191 set of constant vectors in memory. */
22194 /* mask = mask & {2*w-1, ...} */
22196 }
22197 else
22198 {
22199 /* mask = mask & {w-1, ...} */
22201 }
22209 /* For non-QImode operations, convert the word permutation control
22210 into a byte permutation control. */
22212 {
22217 /* Convert mask to vector of chars. */
22220 /* Replicate each of the input bytes into byte positions:
22221 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22222 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22223 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22230 else
22233 /* Convert it into the byte positions by doing
22234 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22240 }
22242 /* The actual shuffle operations all operate on V16QImode. */
22247 {
22254 }
22256 {
22263 }
22264 else
22265 {
22269 /* Shuffle the two input vectors independently. */
22275 merge_two:
22276 /* Then merge them together. The key is whether any given control
22277 element contained a bit set that indicates the second word. */
22281 {
22282 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22283 more shuffle to convert the V2DI input mask into a V4SI
22284 input mask. At which point the masking that expand_int_vcond
22285 will work as desired. */
22293 }
22315 }
22316 }
22318 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22319 true if we should do zero extension, else sign extension. HIGH_P is
22320 true if we want the N/2 high elements, else the low elements. */
22322 void
22324 {
22326 rtx tmp;
22329 {
22335 {
22339 else
22342 extract
22348 else
22351 extract
22357 else
22360 extract
22366 else
22369 extract
22375 else
22378 extract
22384 else
22387 extract
22393 else
22399 else
22405 else
22410 }
22413 {
22416 }
22418 {
22419 /* Shift higher 8 bytes to lower 8 bytes. */
22424 }
22425 else
22429 }
22430 else
22431 {
22435 {
22439 else
22445 else
22451 else
22456 }
22460 else
22467 }
22468 }
22470 /* Expand conditional increment or decrement using adb/sbb instructions.
22471 The default case using setcc followed by the conditional move can be
22472 done by generic code. */
22473 bool
22475 {
22477 rtx flags;
22479 rtx compare_op;
22482 machine_mode mode;
22497 {
22500 }
22503 {
22507 reverse_condition_maybe_unordered
22509 else
22511 }
22515 /* Construct either adc or sbb insn. */
22517 {
22519 {
22534 }
22535 }
22536 else
22537 {
22539 {
22554 }
22555 }
22559 }
22562 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22563 but works for floating pointer parameters and nonoffsetable memories.
22564 For pushes, it returns just stack offsets; the values will be saved
22565 in the right order. Maximally three parts are generated. */
22567 static int
22569 {
22574 else
22580 /* Optimize constant pool reference to immediates. This is used by fp
22581 moves, that force all constants to memory to allow combining. */
22583 {
22587 }
22590 {
22591 /* The only non-offsetable memories we handle are pushes. */
22600 }
22603 {
22605 /* Caution: if we looked through a constant pool memory above,
22606 the operand may actually have a different mode now. That's
22607 ok, since we want to pun this all the way back to an integer. */
22611 }
22614 {
22617 else
22618 {
22622 {
22626 }
22628 {
22633 }
22635 {
22636 REAL_VALUE_TYPE r;
22641 {
22648 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22649 long double may not be 80-bit. */
22658 }
22661 }
22662 else
22664 }
22665 }
22666 else
22667 {
22671 {
22674 {
22678 }
22680 {
22684 }
22686 {
22687 REAL_VALUE_TYPE r;
22693 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22696 = gen_int_mode
22699 DImode);
22700 else
22707 = gen_int_mode
22710 DImode);
22711 else
22713 }
22714 else
22716 }
22717 }
22720 }
22722 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22723 Return false when normal moves are needed; true when all required
22724 insns have been emitted. Operands 2-4 contain the input values
22725 int the correct order; operands 5-7 contain the output values. */
22727 void
22729 {
22737 /* The DFmode expanders may ask us to move double.
22738 For 64bit target this is single move. By hiding the fact
22739 here we simplify i386.md splitters. */
22741 {
22742 /* Optimize constant pool reference to immediates. This is used by
22743 fp moves, that force all constants to memory to allow combining. */
22750 {
22753 }
22754 else
22759 }
22761 /* The only non-offsettable memory we handle is push. */
22764 else
22771 /* When emitting push, take care for source operands on the stack. */
22774 {
22777 /* Compensate for the stack decrement by 4. */
22782 /* src_base refers to the stack pointer and is
22783 automatically decreased by emitted push. */
22787 }
22789 /* We need to do copy in the right order in case an address register
22790 of the source overlaps the destination. */
22792 {
22793 rtx tmp;
22796 {
22800 collisions++;
22801 }
22803 /* Collision in the middle part can be handled by reordering. */
22805 {
22808 }
22812 {
22814 {
22817 }
22818 else
22819 {
22822 }
22823 }
22825 /* If there are more collisions, we can't handle it by reordering.
22826 Do an lea to the last part and use only one colliding move. */
22828 {
22829 rtx base;
22835 /* Handle the case when the last part isn't valid for lea.
22836 Happens in 64-bit mode storing the 12-byte XFmode. */
22843 {
22846 }
22847 }
22848 }
22851 {
22853 {
22855 {
22860 }
22862 {
22865 }
22866 }
22867 else
22868 {
22869 /* In 64bit mode we don't have 32bit push available. In case this is
22870 register, it is OK - we will just use larger counterpart. We also
22871 retype memory - these comes from attempt to avoid REX prefix on
22872 moving of second half of TFmode value. */
22874 {
22876 {
22887 }
22891 }
22892 }
22896 }
22898 /* Choose correct order to not overwrite the source before it is copied. */
22908 {
22910 {
22913 }
22914 }
22915 else
22916 {
22918 {
22921 }
22922 }
22924 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22926 {
22935 }
22941 }
22943 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22944 left shift by a constant, either using a single shift or
22945 a sequence of add instructions. */
22947 static void
22949 {
22955 {
22959 }
22960 else
22961 {
22964 }
22965 }
22967 void
22969 {
22978 {
22983 {
22989 }
22990 else
22991 {
22999 }
23001 }
23008 {
23009 /* Assuming we've chosen a QImode capable registers, then 1 << N
23010 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23012 {
23028 }
23030 /* Otherwise, we can get the same results by manually performing
23031 a bit extract operation on bit 5/6, and then performing the two
23032 shifts. The two methods of getting 0/1 into low/high are exactly
23033 the same size. Avoiding the shift in the bit extract case helps
23034 pentium4 a bit; no one else seems to care much either way. */
23035 else
23036 {
23037 machine_mode half_mode;
23041 HOST_WIDE_INT bits;
23042 rtx x;
23045 {
23051 }
23052 else
23053 {
23059 }
23063 else
23071 }
23076 }
23079 {
23080 /* For -1 << N, we can avoid the shld instruction, because we
23081 know that we're shifting 0...31/63 ones into a -1. */
23085 else
23087 }
23088 else
23089 {
23097 }
23102 {
23108 }
23109 else
23110 {
23115 }
23116 }
23118 void
23120 {
23130 {
23135 {
23141 }
23143 {
23152 }
23153 else
23154 {
23162 }
23163 }
23164 else
23165 {
23177 {
23185 scratch));
23186 }
23187 else
23188 {
23193 }
23194 }
23195 }
23197 void
23199 {
23209 {
23214 {
23221 }
23222 else
23223 {
23231 }
23232 }
23233 else
23234 {
23246 {
23252 scratch));
23253 }
23254 else
23255 {
23260 }
23261 }
23262 }
23264 /* Predict just emitted jump instruction to be taken with probability PROB. */
23265 static void
23267 {
23271 }
23273 /* Helper function for the string operations below. Dest VARIABLE whether
23274 it is aligned to VALUE bytes. If true, jump to the label. */
23277 {
23282 else
23288 else
23291 }
23293 /* Adjust COUNTER by the VALUE. */
23294 static void
23296 {
23301 }
23303 /* Zero extend possibly SImode EXP to Pmode register. */
23304 rtx
23306 {
23308 }
23310 /* Divide COUNTREG by SCALE. */
23311 static rtx
23313 {
23314 rtx sc;
23326 }
23328 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23329 DImode for constant loop counts. */
23331 static machine_mode
23333 {
23341 }
23343 /* Copy the address to a Pmode register. This is used for x32 to
23344 truncate DImode TLS address to a SImode register. */
23346 static rtx
23348 {
23351 else
23352 {
23355 }
23356 }
23358 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23359 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23360 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23361 memory by VALUE (supposed to be in MODE).
23363 The size is rounded down to whole number of chunk size moved at once.
23364 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23367 static void
23372 {
23379 rtx size;
23388 /* Those two should combine. */
23390 {
23394 }
23401 /* This assert could be relaxed - in this case we'll need to compute
23402 smallest power of two, containing in PIECE_SIZE_N and pass it to
23403 offset_address. */
23409 {
23413 /* When unrolling for chips that reorder memory reads and writes,
23414 we can save registers by using single temporary.
23415 Also using 4 temporaries is overkill in 32bit mode. */
23417 {
23419 {
23421 {
23422 destmem =
23424 srcmem =
23426 }
23428 }
23429 }
23430 else
23431 {
23435 {
23438 {
23439 srcmem =
23441 }
23443 }
23445 {
23447 {
23448 destmem =
23450 }
23452 }
23453 }
23454 }
23455 else
23457 {
23459 destmem =
23462 }
23472 {
23478 else
23480 }
23481 else
23489 {
23494 }
23496 }
23498 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23499 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23500 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23501 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23502 ORIG_VALUE is the original value passed to memset to fill the memory with.
23503 Other arguments have same meaning as for previous function. */
23505 static void
23508 rtx count,
23510 {
23511 rtx destexp;
23512 rtx srcexp;
23513 rtx countreg;
23514 HOST_WIDE_INT rounded_count;
23516 /* If possible, it is shorter to use rep movs.
23517 TODO: Maybe it is better to move this logic to decide_alg. */
23528 {
23532 }
23533 else
23536 {
23541 }
23546 {
23549 }
23550 else
23551 {
23555 {
23559 }
23560 else
23563 {
23568 }
23569 else
23570 {
23573 }
23576 }
23577 }
23579 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23580 DESTMEM.
23581 SRC is passed by pointer to be updated on return.
23582 Return value is updated DST. */
23583 static rtx
23585 HOST_WIDE_INT size_to_move)
23586 {
23589 machine_mode move_mode;
23592 /* Find the widest mode in which we could perform moves.
23593 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23594 it until move of such size is supported. */
23599 {
23603 }
23605 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23606 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23608 {
23613 {
23617 }
23618 }
23624 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23628 {
23629 /* We move from memory to memory, so we'll need to do it via
23630 a temporary register. */
23641 piece_size);
23643 piece_size);
23644 }
23646 /* Update DST and SRC rtx. */
23649 }
23651 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23652 static void
23655 {
23658 {
23663 /* For now MAX_SIZE should be a power of 2. This assert could be
23664 relaxed, but it'll require a bit more complicated epilogue
23665 expanding. */
23668 {
23671 }
23673 }
23675 {
23681 }
23683 /* When there are stringops, we can cheaply increase dest and src pointers.
23684 Otherwise we save code size by maintaining offset (zero is readily
23685 available from preceding rep operation) and using x86 addressing modes.
23686 */
23688 {
23690 {
23697 }
23699 {
23706 }
23708 {
23715 }
23716 }
23717 else
23718 {
23720 rtx tmp;
23723 {
23734 }
23736 {
23749 }
23751 {
23760 }
23761 }
23762 }
23764 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23765 with value PROMOTED_VAL.
23766 SRC is passed by pointer to be updated on return.
23767 Return value is updated DST. */
23768 static rtx
23770 HOST_WIDE_INT size_to_move)
23771 {
23774 machine_mode move_mode;
23777 /* Find the widest mode in which we could perform moves.
23778 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23779 it until move of such size is supported. */
23784 {
23787 }
23794 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23798 {
23800 {
23803 piece_size);
23805 }
23813 piece_size);
23814 }
23816 /* Update DST rtx. */
23818 }
23819 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23820 static void
23823 {
23824 count =
23830 }
23832 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23833 static void
23836 {
23837 rtx dest;
23840 {
23845 /* For now MAX_SIZE should be a power of 2. This assert could be
23846 relaxed, but it'll require a bit more complicated epilogue
23847 expanding. */
23850 {
23852 {
23855 else
23857 }
23858 }
23860 }
23862 {
23865 }
23867 {
23870 {
23875 }
23876 else
23877 {
23886 }
23889 }
23891 {
23894 {
23897 }
23898 else
23899 {
23904 }
23907 }
23909 {
23915 }
23917 {
23923 }
23925 {
23931 }
23932 }
23934 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23935 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23936 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23937 ignored.
23938 Return value is updated DESTMEM. */
23939 static rtx
23944 {
23947 {
23949 {
23952 {
23955 else
23957 }
23958 else
23964 }
23965 }
23967 }
23969 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23970 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23971 and jump to DONE_LABEL. */
23972 static void
23978 {
23981 rtx modesize;
23984 /* If we do not have vector value to copy, we must reduce size. */
23986 {
23988 {
23993 }
23994 else
23996 }
23997 else
23998 {
23999 /* Choose appropriate vector mode. */
24005 }
24010 {
24013 else
24014 {
24017 }
24019 }
24025 {
24029 }
24031 {
24034 else
24035 {
24038 }
24040 }
24046 }
24048 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24049 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24050 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24051 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24052 DONE_LABEL is a label after the whole copying sequence. The label is created
24053 on demand if *DONE_LABEL is NULL.
24054 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24055 bounds after the initial copies.
24057 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24058 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24059 we will dispatch to a library call for large blocks.
24061 In pseudocode we do:
24063 if (COUNT < SIZE)
24064 {
24065 Assume that SIZE is 4. Bigger sizes are handled analogously
24066 if (COUNT & 4)
24067 {
24068 copy 4 bytes from SRCPTR to DESTPTR
24069 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24070 goto done_label
24071 }
24072 if (!COUNT)
24073 goto done_label;
24074 copy 1 byte from SRCPTR to DESTPTR
24075 if (COUNT & 2)
24076 {
24077 copy 2 bytes from SRCPTR to DESTPTR
24078 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24079 }
24080 }
24081 else
24082 {
24083 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24084 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24086 OLD_DESPTR = DESTPTR;
24087 Align DESTPTR up to DESIRED_ALIGN
24088 SRCPTR += DESTPTR - OLD_DESTPTR
24089 COUNT -= DEST_PTR - OLD_DESTPTR
24090 if (DYNAMIC_CHECK)
24091 Round COUNT down to multiple of SIZE
24092 << optional caller supplied zero size guard is here >>
24093 << optional caller suppplied dynamic check is here >>
24094 << caller supplied main copy loop is here >>
24095 }
24096 done_label:
24097 */
24098 static void
24101 machine_mode mode,
24111 {
24114 rtx modesize;
24116 rtx mode_value;
24118 /* Chose proper value to copy. */
24121 else
24125 /* See if block is big or small, handle small blocks. */
24127 {
24138 /* Handle sizes > 3. */
24145 /* Nothing to copy? Jump to DONE_LABEL if so */
24149 /* Do a byte copy. */
24153 else
24154 {
24157 }
24159 /* Handle sizes 2 and 3. */
24166 else
24167 {
24172 }
24178 }
24179 else
24183 /* Start memcpy for COUNT >= SIZE. */
24185 {
24188 }
24190 /* Copy first desired_align bytes. */
24196 {
24199 else
24200 {
24203 }
24206 }
24209 /* Copy last SIZE bytes. */
24216 else
24217 {
24223 }
24225 {
24229 else
24230 {
24233 }
24234 }
24236 /* Align destination. */
24238 {
24242 /* Align destptr up, place it to new register. */
24249 /* See how many bytes we skipped. */
24253 /* Adjust srcptr and count. */
24259 /* We copied at most size + prolog_size. */
24262 else
24265 /* Our loops always round down the bock size, but for dispatch to library
24266 we need precise value. */
24270 }
24271 else
24272 {
24274 /* Decrease count, so we won't end up copying last word twice. */
24278 else
24282 }
24283 }
24286 /* This function is like the previous one, except here we know how many bytes
24287 need to be copied. That allows us to update alignment not only of DST, which
24288 is returned, but also of SRC, which is passed as a pointer for that
24289 reason. */
24290 static rtx
24295 {
24303 {
24307 }
24312 {
24314 {
24316 {
24319 else
24321 }
24322 else
24325 }
24326 }
24333 {
24339 {
24342 {
24346 }
24351 }
24355 }
24358 }
24360 /* Return true if ALG can be used in current context.
24361 Assume we expand memset if MEMSET is true. */
24362 static bool
24364 {
24369 /* Algorithms using the rep prefix want at least edi and ecx;
24370 additionally, memset wants eax and memcpy wants esi. Don't
24371 consider such algorithms if the user has appropriated those
24372 registers for their own purposes. */
24379 }
24381 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24382 static enum stringop_alg
24386 {
24397 /* Even if the string operation call is cold, we still might spend a lot
24398 of time processing large blocks. */
24404 else
24410 else
24413 /* See maximal size for user defined algorithm. */
24415 {
24422 }
24424 /* If expected size is not known but max size is small enough
24425 so inline version is a win, set expected size into
24426 the range. */
24431 /* If user specified the algorithm, honnor it if possible. */
24435 /* rep; movq or rep; movl is the smallest variant. */
24437 {
24442 else
24445 }
24446 /* Very tiny blocks are best handled via the loop, REP is expensive to
24447 setup. */
24451 {
24455 {
24456 /* We get here if the algorithms that were not libcall-based
24457 were rep-prefix based and we are unable to use rep prefixes
24458 based on global register usage. Break out of the loop and
24459 use the heuristic below. */
24463 {
24467 {
24470 }
24471 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24472 last non-libcall inline algorithm. */
24474 {
24475 /* When the current size is best to be copied by a libcall,
24476 but we are still forced to inline, run the heuristic below
24477 that will pick code for medium sized blocks. */
24479 {
24482 }
24485 }
24487 {
24490 }
24491 }
24492 }
24493 }
24494 /* When asked to inline the call anyway, try to pick meaningful choice.
24495 We look for maximal size of block that is faster to copy by hand and
24496 take blocks of at most of that size guessing that average size will
24497 be roughly half of the block.
24499 If this turns out to be bad, we might simply specify the preferred
24500 choice in ix86_costs. */
24504 {
24507 /* If there aren't any usable algorithms, then recursing on
24508 smaller sizes isn't going to find anything. Just return the
24509 simple byte-at-a-time copy loop. */
24511 {
24512 /* Pick something reasonable. */
24516 }
24524 else
24527 }
24530 }
24532 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24533 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24534 static int
24538 machine_mode move_mode)
24539 {
24550 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24551 copying whole cacheline at once. */
24564 }
24567 /* Helper function for memcpy. For QImode value 0xXY produce
24568 0xXYXYXYXY of wide specified by MODE. This is essentially
24569 a * 0x10101010, but we can do slightly better than
24570 synth_mult by unwinding the sequence by hand on CPUs with
24571 slow multiply. */
24572 static rtx
24574 {
24576 rtx tmp;
24583 {
24591 }
24600 nops--;
24605 {
24609 OPTAB_DIRECT);
24610 }
24611 else
24612 {
24618 else
24620 else
24621 {
24624 reg =
24626 }
24636 }
24637 }
24639 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24640 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24641 alignment from ALIGN to DESIRED_ALIGN. */
24642 static rtx
24645 {
24646 rtx promoted_val;
24655 else
24659 }
24661 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24662 operations when profitable. The code depends upon architecture, block size
24663 and alignment, but always has one of the following overall structures:
24665 Aligned move sequence:
24667 1) Prologue guard: Conditional that jumps up to epilogues for small
24668 blocks that can be handled by epilogue alone. This is faster
24669 but also needed for correctness, since prologue assume the block
24670 is larger than the desired alignment.
24672 Optional dynamic check for size and libcall for large
24673 blocks is emitted here too, with -minline-stringops-dynamically.
24675 2) Prologue: copy first few bytes in order to get destination
24676 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24677 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24678 copied. We emit either a jump tree on power of two sized
24679 blocks, or a byte loop.
24681 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24682 with specified algorithm.
24684 4) Epilogue: code copying tail of the block that is too small to be
24685 handled by main body (or up to size guarded by prologue guard).
24687 Misaligned move sequence
24689 1) missaligned move prologue/epilogue containing:
24690 a) Prologue handling small memory blocks and jumping to done_label
24691 (skipped if blocks are known to be large enough)
24692 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24693 needed by single possibly misaligned move
24694 (skipped if alignment is not needed)
24695 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24697 2) Zero size guard dispatching to done_label, if needed
24699 3) dispatch to library call, if needed,
24701 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24702 with specified algorithm. */
24703 bool
24709 {
24710 rtx destreg;
24713 rtx tmp;
24729 /* TODO: Once value ranges are available, fill in proper data. */
24737 /* i386 can do misaligned access on reasonably increased cost. */
24741 /* ALIGN is the minimum of destination and source alignment, but we care here
24742 just about destination alignment. */
24748 {
24751 /* When COUNT is 0, there is nothing to do. */
24754 }
24755 else
24756 {
24765 }
24767 /* Make sure we don't need to care about overflow later on. */
24771 /* Step 0: Decide on preferred algorithm, desired alignment and
24772 size of chunks to be copied by main loop. */
24774 issetmem,
24781 /* For now vector-version of memset is generated only for memory zeroing, as
24782 creating of promoted vector value is very cheap in this case. */
24795 {
24814 /* Find the widest supported mode. */
24820 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24821 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24823 {
24828 }
24840 }
24848 /* Step 1: Prologue guard. */
24850 /* Alignment code needs count to be in register. */
24852 {
24855 {
24856 align_bytes
24860 else
24862 }
24865 }
24868 /* Misaligned move sequences handle both prologue and epilogue at once.
24869 Default code generation results in a smaller code for large alignments
24870 and also avoids redundant job when sizes are known precisely. */
24871 misaligned_prologue_used
24872 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24878 /* Do the cheap promotion to allow better CSE across the
24879 main loop and epilogue (ie one load of the big constant in the
24880 front of all code.
24881 For now the misaligned move sequences do not have fast path
24882 without broadcasting. */
24884 {
24886 {
24892 }
24893 else
24894 {
24897 }
24898 }
24899 /* Misaligned move sequences handles both prologues and epilogues at once.
24900 Default code generation results in smaller code for large alignments and
24901 also avoids redundant job when sizes are known precisely. */
24903 {
24904 /* Misaligned move prologue handled small blocks by itself. */
24905 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24910 desired_align < align
24919 {
24920 /* It is possible that we copied enough so the main loop will not
24921 execute. */
24931 else
24933 }
24934 }
24935 /* Ensure that alignment prologue won't copy past end of block. */
24937 {
24939 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24940 Make sure it is power of 2. */
24943 /* To improve performance of small blocks, we jump around the VAL
24944 promoting mode. This mean that if the promoted VAL is not constant,
24945 we might not use it in the epilogue and have to use byte
24946 loop variant. */
24951 {
24952 /* If main algorithm works on QImode, no epilogue is needed.
24953 For small sizes just don't align anything. */
24956 else
24958 }
24961 {
24968 else
24970 }
24971 }
24973 /* Emit code to decide on runtime whether library call or inline should be
24974 used. */
24976 {
24978 {
24980 {
24984 }
24985 }
24986 else
24987 {
24997 else
25001 }
25002 }
25004 /* Step 2: Alignment prologue. */
25005 /* Do the expensive promotion once we branched off the small blocks. */
25011 {
25013 {
25014 /* Except for the first move in prologue, we no longer know
25015 constant offset in aliasing info. It don't seems to worth
25016 the pain to maintain it for the first move, so throw away
25017 the info early. */
25024 issetmem);
25025 /* At most desired_align - align bytes are copied. */
25028 else
25030 }
25031 else
25032 {
25033 /* If we know how many bytes need to be stored before dst is
25034 sufficiently aligned, maintain aliasing info accurately. */
25036 srcreg,
25037 promoted_val,
25038 vec_promoted_val,
25039 desired_align,
25040 align_bytes,
25041 issetmem);
25048 }
25050 && !min_size
25055 {
25056 /* It is possible that we copied enough so the main loop will not
25057 execute. */
25067 else
25069 }
25070 }
25072 {
25079 }
25083 /* Step 3: Main loop. */
25086 {
25109 }
25110 /* Adjust properly the offset of src and dest memory for aliasing. */
25112 {
25118 }
25119 else
25120 {
25124 }
25126 /* Step 4: Epilogue to copy the remaining bytes. */
25127 epilogue:
25129 {
25130 /* When the main loop is done, COUNT_EXP might hold original count,
25131 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25132 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25133 bytes. Compensate if needed. */
25136 {
25137 tmp =
25140 OPTAB_DIRECT);
25143 }
25146 }
25149 {
25152 epilogue_size_needed);
25153 else
25154 {
25158 epilogue_size_needed);
25159 else
25161 epilogue_size_needed);
25162 }
25163 }
25167 }
25170 /* Expand the appropriate insns for doing strlen if not just doing
25171 repnz; scasb
25173 out = result, initialized with the start address
25174 align_rtx = alignment of the address.
25175 scratch = scratch register, initialized with the startaddress when
25176 not aligned, otherwise undefined
25178 This is just the body. It needs the initializations mentioned above and
25179 some address computing at the end. These things are done in i386.md. */
25181 static void
25183 {
25185 rtx tmp;
25190 rtx mem;
25193 rtx cmp;
25199 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25201 /* Is there a known alignment and is it less than 4? */
25203 {
25206 /* Is there a known alignment and is it not 2? */
25208 {
25212 /* Leave just the 3 lower bits. */
25222 }
25223 else
25224 {
25225 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25226 check if is aligned to 4 - byte. */
25233 }
25237 /* Now compare the bytes. */
25239 /* Compare the first n unaligned byte on a byte per byte basis. */
25243 /* Increment the address. */
25246 /* Not needed with an alignment of 2 */
25248 {
25252 end_0_label);
25257 }
25260 end_0_label);
25263 }
25265 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25266 align this loop. It gives only huge programs, but does not help to
25267 speed up. */
25274 /* This formula yields a nonzero result iff one of the bytes is zero.
25275 This saves three branches inside loop and many cycles. */
25283 align_4_label);
25286 {
25292 /* If zero is not in the first two bytes, move two bytes forward. */
25298 reg,
25299 tmpreg)));
25300 /* Emit lea manually to avoid clobbering of flags. */
25308 reg2,
25309 out)));
25310 }
25311 else
25312 {
25314 /* Is zero in the first two bytes? */
25321 pc_rtx);
25325 /* Not in the first two. Move two bytes forward. */
25331 }
25333 /* Avoid branch in fixing the byte. */
25341 }
25343 /* Expand strlen. */
25345 bool
25347 {
25350 /* The generic case of strlen expander is long. Avoid it's
25351 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25354 && !TARGET_INLINE_ALL_STRINGOPS
25364 {
25365 /* Well it seems that some optimizer does not combine a call like
25366 foo(strlen(bar), strlen(bar));
25367 when the move and the subtraction is done here. It does calculate
25368 the length just once when these instructions are done inside of
25369 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25370 often used and I use one fewer register for the lifetime of
25371 output_strlen_unroll() this is better. */
25377 /* strlensi_unroll_1 returns the address of the zero at the end of
25378 the string, like memchr(), so compute the length by subtracting
25379 the start address. */
25381 }
25382 else
25383 {
25384 rtx unspec;
25386 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25399 /* If .md starts supporting :P, this can be done in .md. */
25405 }
25407 }
25409 /* For given symbol (function) construct code to compute address of it's PLT
25410 entry in large x86-64 PIC model. */
25411 static rtx
25413 {
25426 }
25428 rtx
25430 rtx callarg2,
25432 {
25442 {
25443 #if TARGET_MACHO
25446 #endif
25447 }
25448 else
25449 {
25450 /* Static functions and indirect calls don't need the pic register. */
25452 && (!TARGET_64BIT
25457 {
25461 pic_offset_table_rtx);
25462 }
25463 }
25465 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25466 parameters passed in vector registers. */
25471 {
25475 }
25478 && !TARGET_PECOFF
25486 {
25489 }
25494 {
25495 /* We should add bounds as destination register in case
25496 pointer with bounds may be returned. */
25498 {
25503 }
25506 }
25510 {
25514 }
25518 {
25519 int const cregs_size
25524 {
25529 }
25530 }
25539 }
25541 /* Output the assembly for a call instruction. */
25545 {
25551 {
25554 /* SEH epilogue detection requires the indirect branch case
25555 to include REX.W. */
25558 else
25563 }
25565 /* SEH unwinding can require an extra nop to be emitted in several
25566 circumstances. Determine if we have one of those. */
25568 {
25572 {
25573 /* If we get to another real insn, we don't need the nop. */
25577 /* If we get to the epilogue note, prevent a catch region from
25578 being adjacent to the standard epilogue sequence. If non-
25579 call-exceptions, we'll have done this during epilogue emission. */
25581 && !flag_non_call_exceptions
25583 {
25586 }
25587 }
25589 /* If we didn't find a real insn following the call, prevent the
25590 unwinder from looking into the next function. */
25593 }
25597 else
25606 }
25607 \f
25608 /* Clear stack slot assignments remembered from previous functions.
25609 This is called from INIT_EXPANDERS once before RTL is emitted for each
25610 function. */
25614 {
25622 }
25624 /* Return a MEM corresponding to a stack slot with mode MODE.
25625 Allocate a new slot if necessary.
25627 The RTL for a function can have several slots available: N is
25628 which slot to use. */
25630 rtx
25632 {
25649 }
25651 static void
25653 {
25659 }
25660 \f
25661 /* Check whether x86 address PARTS is a pc-relative address. */
25663 static bool
25665 {
25673 {
25675 {
25692 }
25693 }
25695 }
25697 /* Calculate the length of the memory address in the instruction encoding.
25698 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25699 or other prefixes. We never generate addr32 prefix for LEA insn. */
25701 int
25703 {
25720 /* If this is not LEA instruction, add the length of addr32 prefix. */
25725 len++;
25739 /* Rule of thumb:
25740 - esp as the base always wants an index,
25741 - ebp as the base always wants a displacement,
25742 - r12 as the base always wants an index,
25743 - r13 as the base always wants a displacement. */
25745 /* Register Indirect. */
25747 {
25748 /* esp (for its index) and ebp (for its displacement) need
25749 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25750 code. */
25757 len++;
25758 }
25760 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25761 is not disp32, but disp32(%rip), so for disp32
25762 SIB byte is needed, unless print_operand_address
25763 optimizes it into disp32(%rip) or (%rip) is implied
25764 by UNSPEC. */
25766 {
25769 len++;
25770 }
25771 else
25772 {
25773 /* Find the length of the displacement constant. */
25775 {
25778 else
25780 }
25781 /* ebp always wants a displacement. Similarly r13. */
25783 len++;
25785 /* An index requires the two-byte modrm form.... */
25787 /* ...like esp (or r12), which always wants an index. */
25791 len++;
25792 }
25795 }
25797 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25798 is set, expect that insn have 8bit immediate alternative. */
25799 int
25801 {
25807 {
25812 {
25815 {
25827 }
25829 {
25832 }
25833 }
25835 {
25845 /* Immediates for DImode instructions are encoded
25846 as 32bit sign extended values. */
25852 }
25853 }
25855 }
25857 /* Compute default value for "length_address" attribute. */
25858 int
25860 {
25864 {
25875 }
25880 {
25883 {
25888 constraints++;
25891 ;
25892 /* Skip ignored operands. */
25895 }
25897 }
25899 }
25901 /* Compute default value for "length_vex" attribute. It includes
25902 2 or 3 byte VEX prefix and 1 opcode byte. */
25904 int
25907 {
25910 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25911 byte VEX prefix. */
25915 /* We can always use 2 byte VEX prefix in 32bit. */
25923 {
25924 /* REX.W bit uses 3 byte VEX prefix. */
25928 }
25929 else
25930 {
25931 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25935 }
25938 }
25939 \f
25940 /* Return the maximum number of instructions a cpu can issue. */
25942 static int
25944 {
25946 {
25978 }
25979 }
25981 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25982 by DEP_INSN and nothing set by DEP_INSN. */
25984 static bool
25986 {
25989 /* Simplify the test for uninteresting insns. */
25997 {
26000 }
26005 {
26008 }
26009 else
26015 /* This test is true if the dependent insn reads the flags but
26016 not any other potentially set register. */
26024 }
26026 /* Return true iff USE_INSN has a memory address with operands set by
26027 SET_INSN. */
26029 bool
26031 {
26036 {
26039 }
26041 }
26043 /* Helper function for exact_store_load_dependency.
26044 Return true if addr is found in insn. */
26045 static bool
26047 {
26054 {
26060 CASE_CONST_ANY:
26069 }
26073 {
26075 {
26085 }
26086 }
26088 }
26090 /* Return true if there exists exact dependency for store & load, i.e.
26091 the same memory address is used in them. */
26092 static bool
26094 {
26108 }
26110 static int
26112 {
26118 /* Anti and output dependencies have zero cost on all CPUs. */
26124 /* If we can't recognize the insns, we can't really do anything. */
26132 {
26134 /* Address Generation Interlock adds a cycle of latency. */
26136 {
26147 }
26151 /* ??? Compares pair with jump/setcc. */
26155 /* Floating point stores require value to be ready one cycle earlier. */
26163 /* INT->FP conversion is expensive. */
26167 /* There is one cycle extra latency between an FP op and a store. */
26177 /* Show ability of reorder buffer to hide latency of load by executing
26178 in parallel with previous instruction in case
26179 previous instruction is not needed to compute the address. */
26182 {
26183 /* Claim moves to take one cycle, as core can issue one load
26184 at time and the next load can start cycle later. */
26189 cost--;
26190 }
26194 /* The esp dependency is resolved before
26195 the instruction is really finished. */
26200 /* INT->FP conversion is expensive. */
26206 /* Show ability of reorder buffer to hide latency of load by executing
26207 in parallel with previous instruction in case
26208 previous instruction is not needed to compute the address. */
26211 {
26212 /* Claim moves to take one cycle, as core can issue one load
26213 at time and the next load can start cycle later. */
26219 else
26221 }
26232 /* Stack engine allows to execute push&pop instructions in parall. */
26236 /* FALLTHRU */
26242 /* Show ability of reorder buffer to hide latency of load by executing
26243 in parallel with previous instruction in case
26244 previous instruction is not needed to compute the address. */
26247 {
26251 /* Because of the difference between the length of integer and
26252 floating unit pipeline preparation stages, the memory operands
26253 for floating point are cheaper.
26255 ??? For Athlon it the difference is most probably 2. */
26258 else
26263 else
26265 }
26272 /* Stack engine allows to execute push&pop instructions in parall. */
26279 /* Show ability of reorder buffer to hide latency of load by executing
26280 in parallel with previous instruction in case
26281 previous instruction is not needed to compute the address. */
26284 {
26287 else
26289 }
26298 /* Increase cost of integer loads. */
26301 {
26304 {
26307 else
26308 {
26309 /* Increase cost of ld/st for short int types only
26310 because of store forwarding issue. */
26314 {
26315 /* Increase cost of store/load insn if exact
26316 dependence exists and it is load insn. */
26321 }
26322 }
26323 }
26324 }
26328 }
26331 }
26333 /* How many alternative schedules to try. This should be as wide as the
26334 scheduling freedom in the DFA, but no wider. Making this value too
26335 large results extra work for the scheduler. */
26337 static int
26339 {
26341 {
26353 /* We use lookahead value 4 for BD both before and after reload
26354 schedules. Plan is to have value 8 included for O3. */
26365 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26366 as many instructions can be executed on a cycle, i.e.,
26367 issue_rate. I wonder why tuning for many CPUs does not do this. */
26370 /* Don't use lookahead for pre-reload schedule to save compile time. */
26375 }
26376 }
26378 /* Return true if target platform supports macro-fusion. */
26380 static bool
26382 {
26384 }
26386 /* Check whether current microarchitecture support macro fusion
26387 for insn pair "CONDGEN + CONDJMP". Refer to
26388 "Intel Architectures Optimization Reference Manual". */
26390 static bool
26392 {
26413 {
26418 {
26422 else
26424 }
26425 }
26432 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26433 supported. */
26440 /* No fusion for RIP-relative address. */
26447 ix86_address parts;
26453 }
26458 /* Check whether conditional jump use Sign or Overflow Flags. */
26466 /* Return true for TYPE_TEST and TYPE_ICMP. */
26471 /* The following is the case that macro-fusion for alu + jmp. */
26475 /* No fusion for alu op with memory destination operand. */
26480 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26481 supported. */
26490 }
26492 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26493 execution. It is applied if
26494 (1) IMUL instruction is on the top of list;
26495 (2) There exists the only producer of independent IMUL instruction in
26496 ready list.
26497 Return index of IMUL producer if it was found and -1 otherwise. */
26498 static int
26500 {
26503 sd_iterator_def sd_it;
26504 dep_t dep;
26511 /* Check that IMUL instruction is on the top of ready list. */
26520 /* Search for producer of independent IMUL instruction. */
26522 {
26526 /* Skip IMUL instruction. */
26536 {
26537 rtx con;
26548 {
26549 sd_iterator_def sd_it1;
26550 dep_t dep1;
26551 /* Check if there is no other dependee for IMUL. */
26554 {
26555 rtx pro;
26561 }
26564 }
26565 }
26568 }
26570 }
26572 /* Try to find the best candidate on the top of ready list if two insns
26573 have the same priority - candidate is best if its dependees were
26574 scheduled earlier. Applied for Silvermont only.
26575 Return true if top 2 insns must be interchanged. */
26576 static bool
26578 {
26581 rtx set;
26582 sd_iterator_def sd_it;
26583 dep_t dep;
26586 #define INSN_TICK(INSN) (HID (INSN)->tick)
26607 {
26610 /* Determine winner more precise. */
26612 {
26613 rtx pro;
26619 }
26621 {
26622 rtx pro;
26628 }
26631 {
26632 /* Determine winner - load must win. */
26638 }
26640 }
26642 #undef INSN_TICK
26643 }
26645 /* Perform possible reodering of ready list for Atom/Silvermont only.
26646 Return issue rate. */
26647 static int
26650 {
26657 /* Set up issue rate. */
26660 /* Do reodering for BONNELL/SILVERMONT only. */
26664 /* Nothing to do if ready list contains only 1 instruction. */
26668 /* Do reodering for post-reload scheduler only. */
26673 {
26678 /* Put IMUL producer (ready[index]) at the top of ready list. */
26684 }
26686 {
26690 /* Swap 2 top elements of ready list. */
26694 }
26696 }
26698 static bool
26701 /* Returns true if lhs of insn is HW function argument register and set up
26702 is_spilled to true if it is likely spilled HW register. */
26703 static bool
26705 {
26706 rtx dst;
26710 /* Call instructions are not movable, ignore it. */
26721 {
26722 /* Is it likely spilled HW register? */
26727 }
26729 }
26731 /* Add output dependencies for chain of function adjacent arguments if only
26732 there is a move to likely spilled HW register. Return first argument
26733 if at least one dependence was added or NULL otherwise. */
26736 {
26744 /* Find nearest to call argument passing instruction. */
26746 {
26755 }
26759 {
26766 {
26769 }
26771 {
26772 /* Add output depdendence between two function arguments if chain
26773 of output arguments contains likely spilled HW registers. */
26777 }
26778 else
26780 }
26784 }
26786 /* Add output or anti dependency from insn to first_arg to restrict its code
26787 motion. */
26788 static void
26790 {
26791 rtx set;
26792 rtx tmp;
26799 {
26800 /* Add output dependency to the first function argument. */
26803 }
26804 /* Add anti dependency. */
26806 }
26808 /* Avoid cross block motion of function argument through adding dependency
26809 from the first non-jump instruction in bb. */
26810 static void
26812 {
26816 {
26818 {
26821 {
26824 }
26825 }
26829 }
26830 }
26832 /* Hook for pre-reload schedule - avoid motion of function arguments
26833 passed in likely spilled HW registers. */
26834 static void
26836 {
26845 {
26848 {
26849 /* Add dependee for first argument to predecessors if only
26850 region contains more than one block. */
26854 /* Skip trivial regions and region head blocks that can have
26855 predecessors outside of region. */
26857 {
26858 edge e;
26859 edge_iterator ei;
26861 /* Regions are SCCs with the exception of selective
26862 scheduling with pipelining of outer blocks enabled.
26863 So also check that immediate predecessors of a non-head
26864 block are in the same region. */
26866 {
26867 /* Avoid creating of loop-carried dependencies through
26868 using topological ordering in the region. */
26872 }
26873 }
26877 }
26878 }
26881 }
26883 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26884 HW registers to maximum, to schedule them at soon as possible. These are
26885 moves from function argument registers at the top of the function entry
26886 and moves from function return value registers after call. */
26887 static int
26889 {
26890 rtx set;
26900 {
26907 }
26910 }
26912 /* Model decoder of Core 2/i7.
26913 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26914 track the instruction fetch block boundaries and make sure that long
26915 (9+ bytes) instructions are assigned to D0. */
26917 /* Maximum length of an insn that can be handled by
26918 a secondary decoder unit. '8' for Core 2/i7. */
26921 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26922 '16' for Core 2/i7. */
26925 /* Maximum number of instructions decoder can handle per cycle.
26926 '6' for Core 2/i7. */
26930 ix86_first_cycle_multipass_data_t;
26932 const_ix86_first_cycle_multipass_data_t;
26934 /* A variable to store target state across calls to max_issue within
26935 one cycle. */
26939 /* Initialize DATA. */
26940 static void
26942 {
26943 ix86_first_cycle_multipass_data_t data
26950 }
26952 /* Advancing the cycle; reset ifetch block counts. */
26953 static void
26955 {
26962 }
26966 /* Filter out insns from ready_try that the core will not be able to issue
26967 on current cycle due to decoder. */
26968 static void
26969 core2i7_first_cycle_multipass_filter_ready_try
26972 {
26974 {
26985 (!first_cycle_insn_p
26987 /* ... or it would not fit into the ifetch block ... */
26989 /* ... or the decoder is full already ... */
26991 /* ... mask the insn out. */
26992 {
26997 }
26998 }
26999 }
27001 /* Prepare for a new round of multipass lookahead scheduling. */
27002 static void
27006 {
27007 ix86_first_cycle_multipass_data_t data
27009 const_ix86_first_cycle_multipass_data_t prev_data
27012 /* Restore the state from the end of the previous round. */
27016 /* Filter instructions that cannot be issued on current cycle due to
27017 decoder restrictions. */
27019 first_cycle_insn_p);
27020 }
27022 /* INSN is being issued in current solution. Account for its impact on
27023 the decoder model. */
27024 static void
27028 {
27029 ix86_first_cycle_multipass_data_t data
27031 const_ix86_first_cycle_multipass_data_t prev_data
27041 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27043 {
27046 }
27048 {
27052 }
27055 /* Filter out insns from ready_try that the core will not be able to issue
27056 on current cycle due to decoder. */
27059 }
27061 /* Revert the effect on ready_try. */
27062 static void
27066 {
27067 const_ix86_first_cycle_multipass_data_t data
27070 sbitmap_iterator sbi;
27074 {
27076 }
27077 }
27079 /* Save the result of multipass lookahead scheduling for the next round. */
27080 static void
27082 {
27083 const_ix86_first_cycle_multipass_data_t data
27085 ix86_first_cycle_multipass_data_t next_data
27089 {
27092 }
27093 }
27095 /* Deallocate target data. */
27096 static void
27098 {
27099 ix86_first_cycle_multipass_data_t data
27103 {
27107 }
27108 }
27110 /* Prepare for scheduling pass. */
27111 static void
27113 {
27114 /* Install scheduling hooks for current CPU. Some of these hooks are used
27115 in time-critical parts of the scheduler, so we only set them up when
27116 they are actually used. */
27118 {
27123 /* Do not perform multipass scheduling for pre-reload schedule
27124 to save compile time. */
27126 {
27142 /* Set decoder parameters. */
27147 }
27148 /* ... Fall through ... */
27158 }
27159 }
27161 \f
27162 /* Compute the alignment given to a constant that is being placed in memory.
27163 EXP is the constant and ALIGN is the alignment that the object would
27164 ordinarily have.
27165 The value of this function is used instead of that alignment to align
27166 the object. */
27168 int
27170 {
27173 {
27178 }
27184 }
27186 /* Compute the alignment for a static variable.
27187 TYPE is the data type, and ALIGN is the alignment that
27188 the object would ordinarily have. The value of this function is used
27189 instead of that alignment to align the object. */
27191 int
27193 {
27194 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27195 for symbols from other compilation units or symbols that don't need
27196 to bind locally. In order to preserve some ABI compatibility with
27197 those compilers, ensure we don't decrease alignment from what we
27198 used to assume. */
27202 /* A data structure, equal or greater than the size of a cache line
27203 (64 bytes in the Pentium 4 and other recent Intel processors, including
27204 processors based on Intel Core microarchitecture) should be aligned
27205 so that its base address is a multiple of a cache line size. */
27207 int max_align
27214 {
27218 }
27224 {
27231 }
27233 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27234 to 16byte boundary. */
27236 {
27243 }
27249 {
27254 }
27256 {
27263 }
27268 {
27273 }
27276 {
27281 }
27284 }
27286 /* Compute the alignment for a local variable or a stack slot. EXP is
27287 the data type or decl itself, MODE is the widest mode available and
27288 ALIGN is the alignment that the object would ordinarily have. The
27289 value of this macro is used instead of that alignment to align the
27290 object. */
27292 unsigned int
27295 {
27299 {
27302 }
27303 else
27304 {
27307 }
27309 /* Don't do dynamic stack realignment for long long objects with
27310 -mpreferred-stack-boundary=2. */
27319 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27320 register in MODE. We will return the largest alignment of XF
27321 and DF. */
27323 {
27327 }
27329 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27330 to 16byte boundary. Exact wording is:
27332 An array uses the same alignment as its elements, except that a local or
27333 global array variable of length at least 16 bytes or
27334 a C99 variable-length array variable always has alignment of at least 16 bytes.
27336 This was added to allow use of aligned SSE instructions at arrays. This
27337 rule is meant for static storage (where compiler can not do the analysis
27338 by itself). We follow it for automatic variables only when convenient.
27339 We fully control everything in the function compiled and functions from
27340 other unit can not rely on the alignment.
27342 Exclude va_list type. It is the common case of local array where
27343 we can not benefit from the alignment.
27345 TODO: Probably one should optimize for size only when var is not escaping. */
27348 {
27358 }
27360 {
27365 }
27367 {
27373 }
27378 {
27383 }
27386 {
27392 }
27394 }
27396 /* Compute the minimum required alignment for dynamic stack realignment
27397 purposes for a local variable, parameter or a stack slot. EXP is
27398 the data type or decl itself, MODE is its mode and ALIGN is the
27399 alignment that the object would ordinarily have. */
27401 unsigned int
27404 {
27408 {
27411 }
27412 else
27413 {
27416 }
27421 /* Don't do dynamic stack realignment for long long objects with
27422 -mpreferred-stack-boundary=2. */
27429 }
27430 \f
27431 /* Find a location for the static chain incoming to a nested function.
27432 This is a register, unless all free registers are used by arguments. */
27434 static rtx
27436 {
27439 /* While this function won't be called by the middle-end when a static
27440 chain isn't needed, it's also used throughout the backend so it's
27441 easiest to keep this check centralized. */
27446 {
27447 /* We always use R10 in 64-bit mode. */
27449 }
27450 else
27451 {
27455 /* By default in 32-bit mode we use ECX to pass the static chain. */
27459 {
27462 }
27463 else
27464 {
27467 }
27471 {
27472 /* Fastcall functions use ecx/edx for arguments, which leaves
27473 us with EAX for the static chain.
27474 Thiscall functions use ecx for arguments, which also
27475 leaves us with EAX for the static chain. */
27477 }
27479 {
27480 /* Thiscall functions use ecx for arguments, which leaves
27481 us with EAX and EDX for the static chain.
27482 We are using for abi-compatibility EAX. */
27484 }
27486 {
27487 /* For regparm 3, we have no free call-clobbered registers in
27488 which to store the static chain. In order to implement this,
27489 we have the trampoline push the static chain to the stack.
27490 However, we can't push a value below the return address when
27491 we call the nested function directly, so we have to use an
27492 alternate entry point. For this we use ESI, and have the
27493 alternate entry point push ESI, so that things appear the
27494 same once we're executing the nested function. */
27496 {
27502 }
27504 }
27505 }
27508 }
27510 /* Emit RTL insns to initialize the variable parts of a trampoline.
27511 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27512 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27513 to be passed to the target function. */
27515 static void
27517 {
27525 {
27528 /* Load the function address to r11. Try to load address using
27529 the shorter movl instead of movabs. We may want to support
27530 movq for kernel mode, but kernel does not use trampolines at
27531 the moment. FNADDR is a 32bit address and may not be in
27532 DImode when ptr_mode == SImode. Always use movl in this
27533 case. */
27536 {
27545 }
27546 else
27547 {
27554 }
27556 /* Load static chain using movabs to r10. Use the shorter movl
27557 instead of movabs when ptr_mode == SImode. */
27559 {
27562 }
27563 else
27564 {
27567 }
27576 /* Jump to r11; the last (unused) byte is a nop, only there to
27577 pad the write out to a single 32-bit store. */
27581 }
27582 else
27583 {
27586 /* Depending on the static chain location, either load a register
27587 with a constant, or push the constant to the stack. All of the
27588 instructions are the same size. */
27591 {
27593 {
27600 }
27601 }
27602 else
27617 /* Compute offset from the end of the jmp to the target function.
27618 In the case in which the trampoline stores the static chain on
27619 the stack, we need to skip the first insn which pushes the
27620 (call-saved) register static chain; this push is 1 byte. */
27627 }
27631 #ifdef HAVE_ENABLE_EXECUTE_STACK
27632 #ifdef CHECK_EXECUTE_STACK_ENABLED
27634 #endif
27637 #endif
27638 }
27639 \f
27640 /* The following file contains several enumerations and data structures
27641 built from the definitions in i386-builtin-types.def. */
27645 /* Table for the ix86 builtin non-function types. */
27648 /* Retrieve an element from the above table, building some of
27649 the types lazily. */
27651 static tree
27653 {
27665 {
27666 machine_mode mode;
27673 }
27674 else
27675 {
27681 else
27689 }
27693 }
27695 /* Table for the ix86 builtin function types. */
27698 /* Retrieve an element from the above table, building some of
27699 the types lazily. */
27701 static tree
27703 {
27704 tree type;
27713 {
27721 {
27724 }
27727 }
27728 else
27729 {
27735 }
27739 }
27742 /* Codes for all the SSE/MMX builtins. */
27743 enum ix86_builtins
27744 {
27745 IX86_BUILTIN_ADDPS,
27746 IX86_BUILTIN_ADDSS,
27747 IX86_BUILTIN_DIVPS,
27748 IX86_BUILTIN_DIVSS,
27749 IX86_BUILTIN_MULPS,
27750 IX86_BUILTIN_MULSS,
27751 IX86_BUILTIN_SUBPS,
27752 IX86_BUILTIN_SUBSS,
27754 IX86_BUILTIN_CMPEQPS,
27755 IX86_BUILTIN_CMPLTPS,
27756 IX86_BUILTIN_CMPLEPS,
27757 IX86_BUILTIN_CMPGTPS,
27758 IX86_BUILTIN_CMPGEPS,
27759 IX86_BUILTIN_CMPNEQPS,
27760 IX86_BUILTIN_CMPNLTPS,
27761 IX86_BUILTIN_CMPNLEPS,
27762 IX86_BUILTIN_CMPNGTPS,
27763 IX86_BUILTIN_CMPNGEPS,
27764 IX86_BUILTIN_CMPORDPS,
27765 IX86_BUILTIN_CMPUNORDPS,
27766 IX86_BUILTIN_CMPEQSS,
27767 IX86_BUILTIN_CMPLTSS,
27768 IX86_BUILTIN_CMPLESS,
27769 IX86_BUILTIN_CMPNEQSS,
27770 IX86_BUILTIN_CMPNLTSS,
27771 IX86_BUILTIN_CMPNLESS,
27772 IX86_BUILTIN_CMPORDSS,
27773 IX86_BUILTIN_CMPUNORDSS,
27775 IX86_BUILTIN_COMIEQSS,
27776 IX86_BUILTIN_COMILTSS,
27777 IX86_BUILTIN_COMILESS,
27778 IX86_BUILTIN_COMIGTSS,
27779 IX86_BUILTIN_COMIGESS,
27780 IX86_BUILTIN_COMINEQSS,
27781 IX86_BUILTIN_UCOMIEQSS,
27782 IX86_BUILTIN_UCOMILTSS,
27783 IX86_BUILTIN_UCOMILESS,
27784 IX86_BUILTIN_UCOMIGTSS,
27785 IX86_BUILTIN_UCOMIGESS,
27786 IX86_BUILTIN_UCOMINEQSS,
27788 IX86_BUILTIN_CVTPI2PS,
27789 IX86_BUILTIN_CVTPS2PI,
27790 IX86_BUILTIN_CVTSI2SS,
27791 IX86_BUILTIN_CVTSI642SS,
27792 IX86_BUILTIN_CVTSS2SI,
27793 IX86_BUILTIN_CVTSS2SI64,
27794 IX86_BUILTIN_CVTTPS2PI,
27795 IX86_BUILTIN_CVTTSS2SI,
27796 IX86_BUILTIN_CVTTSS2SI64,
27798 IX86_BUILTIN_MAXPS,
27799 IX86_BUILTIN_MAXSS,
27800 IX86_BUILTIN_MINPS,
27801 IX86_BUILTIN_MINSS,
27803 IX86_BUILTIN_LOADUPS,
27804 IX86_BUILTIN_STOREUPS,
27805 IX86_BUILTIN_MOVSS,
27807 IX86_BUILTIN_MOVHLPS,
27808 IX86_BUILTIN_MOVLHPS,
27809 IX86_BUILTIN_LOADHPS,
27810 IX86_BUILTIN_LOADLPS,
27811 IX86_BUILTIN_STOREHPS,
27812 IX86_BUILTIN_STORELPS,
27814 IX86_BUILTIN_MASKMOVQ,
27815 IX86_BUILTIN_MOVMSKPS,
27816 IX86_BUILTIN_PMOVMSKB,
27818 IX86_BUILTIN_MOVNTPS,
27819 IX86_BUILTIN_MOVNTQ,
27821 IX86_BUILTIN_LOADDQU,
27822 IX86_BUILTIN_STOREDQU,
27824 IX86_BUILTIN_PACKSSWB,
27825 IX86_BUILTIN_PACKSSDW,
27826 IX86_BUILTIN_PACKUSWB,
27828 IX86_BUILTIN_PADDB,
27829 IX86_BUILTIN_PADDW,
27830 IX86_BUILTIN_PADDD,
27831 IX86_BUILTIN_PADDQ,
27832 IX86_BUILTIN_PADDSB,
27833 IX86_BUILTIN_PADDSW,
27834 IX86_BUILTIN_PADDUSB,
27835 IX86_BUILTIN_PADDUSW,
27836 IX86_BUILTIN_PSUBB,
27837 IX86_BUILTIN_PSUBW,
27838 IX86_BUILTIN_PSUBD,
27839 IX86_BUILTIN_PSUBQ,
27840 IX86_BUILTIN_PSUBSB,
27841 IX86_BUILTIN_PSUBSW,
27842 IX86_BUILTIN_PSUBUSB,
27843 IX86_BUILTIN_PSUBUSW,
27845 IX86_BUILTIN_PAND,
27846 IX86_BUILTIN_PANDN,
27847 IX86_BUILTIN_POR,
27848 IX86_BUILTIN_PXOR,
27850 IX86_BUILTIN_PAVGB,
27851 IX86_BUILTIN_PAVGW,
27853 IX86_BUILTIN_PCMPEQB,
27854 IX86_BUILTIN_PCMPEQW,
27855 IX86_BUILTIN_PCMPEQD,
27856 IX86_BUILTIN_PCMPGTB,
27857 IX86_BUILTIN_PCMPGTW,
27858 IX86_BUILTIN_PCMPGTD,
27860 IX86_BUILTIN_PMADDWD,
27862 IX86_BUILTIN_PMAXSW,
27863 IX86_BUILTIN_PMAXUB,
27864 IX86_BUILTIN_PMINSW,
27865 IX86_BUILTIN_PMINUB,
27867 IX86_BUILTIN_PMULHUW,
27868 IX86_BUILTIN_PMULHW,
27869 IX86_BUILTIN_PMULLW,
27871 IX86_BUILTIN_PSADBW,
27872 IX86_BUILTIN_PSHUFW,
27874 IX86_BUILTIN_PSLLW,
27875 IX86_BUILTIN_PSLLD,
27876 IX86_BUILTIN_PSLLQ,
27877 IX86_BUILTIN_PSRAW,
27878 IX86_BUILTIN_PSRAD,
27879 IX86_BUILTIN_PSRLW,
27880 IX86_BUILTIN_PSRLD,
27881 IX86_BUILTIN_PSRLQ,
27882 IX86_BUILTIN_PSLLWI,
27883 IX86_BUILTIN_PSLLDI,
27884 IX86_BUILTIN_PSLLQI,
27885 IX86_BUILTIN_PSRAWI,
27886 IX86_BUILTIN_PSRADI,
27887 IX86_BUILTIN_PSRLWI,
27888 IX86_BUILTIN_PSRLDI,
27889 IX86_BUILTIN_PSRLQI,
27891 IX86_BUILTIN_PUNPCKHBW,
27892 IX86_BUILTIN_PUNPCKHWD,
27893 IX86_BUILTIN_PUNPCKHDQ,
27894 IX86_BUILTIN_PUNPCKLBW,
27895 IX86_BUILTIN_PUNPCKLWD,
27896 IX86_BUILTIN_PUNPCKLDQ,
27898 IX86_BUILTIN_SHUFPS,
27900 IX86_BUILTIN_RCPPS,
27901 IX86_BUILTIN_RCPSS,
27902 IX86_BUILTIN_RSQRTPS,
27903 IX86_BUILTIN_RSQRTPS_NR,
27904 IX86_BUILTIN_RSQRTSS,
27905 IX86_BUILTIN_RSQRTF,
27906 IX86_BUILTIN_SQRTPS,
27907 IX86_BUILTIN_SQRTPS_NR,
27908 IX86_BUILTIN_SQRTSS,
27910 IX86_BUILTIN_UNPCKHPS,
27911 IX86_BUILTIN_UNPCKLPS,
27913 IX86_BUILTIN_ANDPS,
27914 IX86_BUILTIN_ANDNPS,
27915 IX86_BUILTIN_ORPS,
27916 IX86_BUILTIN_XORPS,
27918 IX86_BUILTIN_EMMS,
27919 IX86_BUILTIN_LDMXCSR,
27920 IX86_BUILTIN_STMXCSR,
27921 IX86_BUILTIN_SFENCE,
27923 IX86_BUILTIN_FXSAVE,
27924 IX86_BUILTIN_FXRSTOR,
27925 IX86_BUILTIN_FXSAVE64,
27926 IX86_BUILTIN_FXRSTOR64,
27928 IX86_BUILTIN_XSAVE,
27929 IX86_BUILTIN_XRSTOR,
27930 IX86_BUILTIN_XSAVE64,
27931 IX86_BUILTIN_XRSTOR64,
27933 IX86_BUILTIN_XSAVEOPT,
27934 IX86_BUILTIN_XSAVEOPT64,
27936 IX86_BUILTIN_XSAVEC,
27937 IX86_BUILTIN_XSAVEC64,
27939 IX86_BUILTIN_XSAVES,
27940 IX86_BUILTIN_XRSTORS,
27941 IX86_BUILTIN_XSAVES64,
27942 IX86_BUILTIN_XRSTORS64,
27944 /* 3DNow! Original */
27945 IX86_BUILTIN_FEMMS,
27946 IX86_BUILTIN_PAVGUSB,
27947 IX86_BUILTIN_PF2ID,
27948 IX86_BUILTIN_PFACC,
27949 IX86_BUILTIN_PFADD,
27950 IX86_BUILTIN_PFCMPEQ,
27951 IX86_BUILTIN_PFCMPGE,
27952 IX86_BUILTIN_PFCMPGT,
27953 IX86_BUILTIN_PFMAX,
27954 IX86_BUILTIN_PFMIN,
27955 IX86_BUILTIN_PFMUL,
27956 IX86_BUILTIN_PFRCP,
27957 IX86_BUILTIN_PFRCPIT1,
27958 IX86_BUILTIN_PFRCPIT2,
27959 IX86_BUILTIN_PFRSQIT1,
27960 IX86_BUILTIN_PFRSQRT,
27961 IX86_BUILTIN_PFSUB,
27962 IX86_BUILTIN_PFSUBR,
27963 IX86_BUILTIN_PI2FD,
27964 IX86_BUILTIN_PMULHRW,
27966 /* 3DNow! Athlon Extensions */
27967 IX86_BUILTIN_PF2IW,
27968 IX86_BUILTIN_PFNACC,
27969 IX86_BUILTIN_PFPNACC,
27970 IX86_BUILTIN_PI2FW,
27971 IX86_BUILTIN_PSWAPDSI,
27972 IX86_BUILTIN_PSWAPDSF,
27974 /* SSE2 */
27975 IX86_BUILTIN_ADDPD,
27976 IX86_BUILTIN_ADDSD,
27977 IX86_BUILTIN_DIVPD,
27978 IX86_BUILTIN_DIVSD,
27979 IX86_BUILTIN_MULPD,
27980 IX86_BUILTIN_MULSD,
27981 IX86_BUILTIN_SUBPD,
27982 IX86_BUILTIN_SUBSD,
27984 IX86_BUILTIN_CMPEQPD,
27985 IX86_BUILTIN_CMPLTPD,
27986 IX86_BUILTIN_CMPLEPD,
27987 IX86_BUILTIN_CMPGTPD,
27988 IX86_BUILTIN_CMPGEPD,
27989 IX86_BUILTIN_CMPNEQPD,
27990 IX86_BUILTIN_CMPNLTPD,
27991 IX86_BUILTIN_CMPNLEPD,
27992 IX86_BUILTIN_CMPNGTPD,
27993 IX86_BUILTIN_CMPNGEPD,
27994 IX86_BUILTIN_CMPORDPD,
27995 IX86_BUILTIN_CMPUNORDPD,
27996 IX86_BUILTIN_CMPEQSD,
27997 IX86_BUILTIN_CMPLTSD,
27998 IX86_BUILTIN_CMPLESD,
27999 IX86_BUILTIN_CMPNEQSD,
28000 IX86_BUILTIN_CMPNLTSD,
28001 IX86_BUILTIN_CMPNLESD,
28002 IX86_BUILTIN_CMPORDSD,
28003 IX86_BUILTIN_CMPUNORDSD,
28005 IX86_BUILTIN_COMIEQSD,
28006 IX86_BUILTIN_COMILTSD,
28007 IX86_BUILTIN_COMILESD,
28008 IX86_BUILTIN_COMIGTSD,
28009 IX86_BUILTIN_COMIGESD,
28010 IX86_BUILTIN_COMINEQSD,
28011 IX86_BUILTIN_UCOMIEQSD,
28012 IX86_BUILTIN_UCOMILTSD,
28013 IX86_BUILTIN_UCOMILESD,
28014 IX86_BUILTIN_UCOMIGTSD,
28015 IX86_BUILTIN_UCOMIGESD,
28016 IX86_BUILTIN_UCOMINEQSD,
28018 IX86_BUILTIN_MAXPD,
28019 IX86_BUILTIN_MAXSD,
28020 IX86_BUILTIN_MINPD,
28021 IX86_BUILTIN_MINSD,
28023 IX86_BUILTIN_ANDPD,
28024 IX86_BUILTIN_ANDNPD,
28025 IX86_BUILTIN_ORPD,
28026 IX86_BUILTIN_XORPD,
28028 IX86_BUILTIN_SQRTPD,
28029 IX86_BUILTIN_SQRTSD,
28031 IX86_BUILTIN_UNPCKHPD,
28032 IX86_BUILTIN_UNPCKLPD,
28034 IX86_BUILTIN_SHUFPD,
28036 IX86_BUILTIN_LOADUPD,
28037 IX86_BUILTIN_STOREUPD,
28038 IX86_BUILTIN_MOVSD,
28040 IX86_BUILTIN_LOADHPD,
28041 IX86_BUILTIN_LOADLPD,
28043 IX86_BUILTIN_CVTDQ2PD,
28044 IX86_BUILTIN_CVTDQ2PS,
28046 IX86_BUILTIN_CVTPD2DQ,
28047 IX86_BUILTIN_CVTPD2PI,
28048 IX86_BUILTIN_CVTPD2PS,
28049 IX86_BUILTIN_CVTTPD2DQ,
28050 IX86_BUILTIN_CVTTPD2PI,
28052 IX86_BUILTIN_CVTPI2PD,
28053 IX86_BUILTIN_CVTSI2SD,
28054 IX86_BUILTIN_CVTSI642SD,
28056 IX86_BUILTIN_CVTSD2SI,
28057 IX86_BUILTIN_CVTSD2SI64,
28058 IX86_BUILTIN_CVTSD2SS,
28059 IX86_BUILTIN_CVTSS2SD,
28060 IX86_BUILTIN_CVTTSD2SI,
28061 IX86_BUILTIN_CVTTSD2SI64,
28063 IX86_BUILTIN_CVTPS2DQ,
28064 IX86_BUILTIN_CVTPS2PD,
28065 IX86_BUILTIN_CVTTPS2DQ,
28067 IX86_BUILTIN_MOVNTI,
28068 IX86_BUILTIN_MOVNTI64,
28069 IX86_BUILTIN_MOVNTPD,
28070 IX86_BUILTIN_MOVNTDQ,
28072 IX86_BUILTIN_MOVQ128,
28074 /* SSE2 MMX */
28075 IX86_BUILTIN_MASKMOVDQU,
28076 IX86_BUILTIN_MOVMSKPD,
28077 IX86_BUILTIN_PMOVMSKB128,
28079 IX86_BUILTIN_PACKSSWB128,
28080 IX86_BUILTIN_PACKSSDW128,
28081 IX86_BUILTIN_PACKUSWB128,
28083 IX86_BUILTIN_PADDB128,
28084 IX86_BUILTIN_PADDW128,
28085 IX86_BUILTIN_PADDD128,
28086 IX86_BUILTIN_PADDQ128,
28087 IX86_BUILTIN_PADDSB128,
28088 IX86_BUILTIN_PADDSW128,
28089 IX86_BUILTIN_PADDUSB128,
28090 IX86_BUILTIN_PADDUSW128,
28091 IX86_BUILTIN_PSUBB128,
28092 IX86_BUILTIN_PSUBW128,
28093 IX86_BUILTIN_PSUBD128,
28094 IX86_BUILTIN_PSUBQ128,
28095 IX86_BUILTIN_PSUBSB128,
28096 IX86_BUILTIN_PSUBSW128,
28097 IX86_BUILTIN_PSUBUSB128,
28098 IX86_BUILTIN_PSUBUSW128,
28100 IX86_BUILTIN_PAND128,
28101 IX86_BUILTIN_PANDN128,
28102 IX86_BUILTIN_POR128,
28103 IX86_BUILTIN_PXOR128,
28105 IX86_BUILTIN_PAVGB128,
28106 IX86_BUILTIN_PAVGW128,
28108 IX86_BUILTIN_PCMPEQB128,
28109 IX86_BUILTIN_PCMPEQW128,
28110 IX86_BUILTIN_PCMPEQD128,
28111 IX86_BUILTIN_PCMPGTB128,
28112 IX86_BUILTIN_PCMPGTW128,
28113 IX86_BUILTIN_PCMPGTD128,
28115 IX86_BUILTIN_PMADDWD128,
28117 IX86_BUILTIN_PMAXSW128,
28118 IX86_BUILTIN_PMAXUB128,
28119 IX86_BUILTIN_PMINSW128,
28120 IX86_BUILTIN_PMINUB128,
28122 IX86_BUILTIN_PMULUDQ,
28123 IX86_BUILTIN_PMULUDQ128,
28124 IX86_BUILTIN_PMULHUW128,
28125 IX86_BUILTIN_PMULHW128,
28126 IX86_BUILTIN_PMULLW128,
28128 IX86_BUILTIN_PSADBW128,
28129 IX86_BUILTIN_PSHUFHW,
28130 IX86_BUILTIN_PSHUFLW,
28131 IX86_BUILTIN_PSHUFD,
28133 IX86_BUILTIN_PSLLDQI128,
28134 IX86_BUILTIN_PSLLWI128,
28135 IX86_BUILTIN_PSLLDI128,
28136 IX86_BUILTIN_PSLLQI128,
28137 IX86_BUILTIN_PSRAWI128,
28138 IX86_BUILTIN_PSRADI128,
28139 IX86_BUILTIN_PSRLDQI128,
28140 IX86_BUILTIN_PSRLWI128,
28141 IX86_BUILTIN_PSRLDI128,
28142 IX86_BUILTIN_PSRLQI128,
28144 IX86_BUILTIN_PSLLDQ128,
28145 IX86_BUILTIN_PSLLW128,
28146 IX86_BUILTIN_PSLLD128,
28147 IX86_BUILTIN_PSLLQ128,
28148 IX86_BUILTIN_PSRAW128,
28149 IX86_BUILTIN_PSRAD128,
28150 IX86_BUILTIN_PSRLW128,
28151 IX86_BUILTIN_PSRLD128,
28152 IX86_BUILTIN_PSRLQ128,
28154 IX86_BUILTIN_PUNPCKHBW128,
28155 IX86_BUILTIN_PUNPCKHWD128,
28156 IX86_BUILTIN_PUNPCKHDQ128,
28157 IX86_BUILTIN_PUNPCKHQDQ128,
28158 IX86_BUILTIN_PUNPCKLBW128,
28159 IX86_BUILTIN_PUNPCKLWD128,
28160 IX86_BUILTIN_PUNPCKLDQ128,
28161 IX86_BUILTIN_PUNPCKLQDQ128,
28163 IX86_BUILTIN_CLFLUSH,
28164 IX86_BUILTIN_MFENCE,
28165 IX86_BUILTIN_LFENCE,
28166 IX86_BUILTIN_PAUSE,
28168 IX86_BUILTIN_FNSTENV,
28169 IX86_BUILTIN_FLDENV,
28170 IX86_BUILTIN_FNSTSW,
28171 IX86_BUILTIN_FNCLEX,
28173 IX86_BUILTIN_BSRSI,
28174 IX86_BUILTIN_BSRDI,
28175 IX86_BUILTIN_RDPMC,
28176 IX86_BUILTIN_RDTSC,
28177 IX86_BUILTIN_RDTSCP,
28178 IX86_BUILTIN_ROLQI,
28179 IX86_BUILTIN_ROLHI,
28180 IX86_BUILTIN_RORQI,
28181 IX86_BUILTIN_RORHI,
28183 /* SSE3. */
28184 IX86_BUILTIN_ADDSUBPS,
28185 IX86_BUILTIN_HADDPS,
28186 IX86_BUILTIN_HSUBPS,
28187 IX86_BUILTIN_MOVSHDUP,
28188 IX86_BUILTIN_MOVSLDUP,
28189 IX86_BUILTIN_ADDSUBPD,
28190 IX86_BUILTIN_HADDPD,
28191 IX86_BUILTIN_HSUBPD,
28192 IX86_BUILTIN_LDDQU,
28194 IX86_BUILTIN_MONITOR,
28195 IX86_BUILTIN_MWAIT,
28197 /* SSSE3. */
28198 IX86_BUILTIN_PHADDW,
28199 IX86_BUILTIN_PHADDD,
28200 IX86_BUILTIN_PHADDSW,
28201 IX86_BUILTIN_PHSUBW,
28202 IX86_BUILTIN_PHSUBD,
28203 IX86_BUILTIN_PHSUBSW,
28204 IX86_BUILTIN_PMADDUBSW,
28205 IX86_BUILTIN_PMULHRSW,
28206 IX86_BUILTIN_PSHUFB,
28207 IX86_BUILTIN_PSIGNB,
28208 IX86_BUILTIN_PSIGNW,
28209 IX86_BUILTIN_PSIGND,
28210 IX86_BUILTIN_PALIGNR,
28211 IX86_BUILTIN_PABSB,
28212 IX86_BUILTIN_PABSW,
28213 IX86_BUILTIN_PABSD,
28215 IX86_BUILTIN_PHADDW128,
28216 IX86_BUILTIN_PHADDD128,
28217 IX86_BUILTIN_PHADDSW128,
28218 IX86_BUILTIN_PHSUBW128,
28219 IX86_BUILTIN_PHSUBD128,
28220 IX86_BUILTIN_PHSUBSW128,
28221 IX86_BUILTIN_PMADDUBSW128,
28222 IX86_BUILTIN_PMULHRSW128,
28223 IX86_BUILTIN_PSHUFB128,
28224 IX86_BUILTIN_PSIGNB128,
28225 IX86_BUILTIN_PSIGNW128,
28226 IX86_BUILTIN_PSIGND128,
28227 IX86_BUILTIN_PALIGNR128,
28228 IX86_BUILTIN_PABSB128,
28229 IX86_BUILTIN_PABSW128,
28230 IX86_BUILTIN_PABSD128,
28232 /* AMDFAM10 - SSE4A New Instructions. */
28233 IX86_BUILTIN_MOVNTSD,
28234 IX86_BUILTIN_MOVNTSS,
28235 IX86_BUILTIN_EXTRQI,
28236 IX86_BUILTIN_EXTRQ,
28237 IX86_BUILTIN_INSERTQI,
28238 IX86_BUILTIN_INSERTQ,
28240 /* SSE4.1. */
28241 IX86_BUILTIN_BLENDPD,
28242 IX86_BUILTIN_BLENDPS,
28243 IX86_BUILTIN_BLENDVPD,
28244 IX86_BUILTIN_BLENDVPS,
28245 IX86_BUILTIN_PBLENDVB128,
28246 IX86_BUILTIN_PBLENDW128,
28248 IX86_BUILTIN_DPPD,
28249 IX86_BUILTIN_DPPS,
28251 IX86_BUILTIN_INSERTPS128,
28253 IX86_BUILTIN_MOVNTDQA,
28254 IX86_BUILTIN_MPSADBW128,
28255 IX86_BUILTIN_PACKUSDW128,
28256 IX86_BUILTIN_PCMPEQQ,
28257 IX86_BUILTIN_PHMINPOSUW128,
28259 IX86_BUILTIN_PMAXSB128,
28260 IX86_BUILTIN_PMAXSD128,
28261 IX86_BUILTIN_PMAXUD128,
28262 IX86_BUILTIN_PMAXUW128,
28264 IX86_BUILTIN_PMINSB128,
28265 IX86_BUILTIN_PMINSD128,
28266 IX86_BUILTIN_PMINUD128,
28267 IX86_BUILTIN_PMINUW128,
28269 IX86_BUILTIN_PMOVSXBW128,
28270 IX86_BUILTIN_PMOVSXBD128,
28271 IX86_BUILTIN_PMOVSXBQ128,
28272 IX86_BUILTIN_PMOVSXWD128,
28273 IX86_BUILTIN_PMOVSXWQ128,
28274 IX86_BUILTIN_PMOVSXDQ128,
28276 IX86_BUILTIN_PMOVZXBW128,
28277 IX86_BUILTIN_PMOVZXBD128,
28278 IX86_BUILTIN_PMOVZXBQ128,
28279 IX86_BUILTIN_PMOVZXWD128,
28280 IX86_BUILTIN_PMOVZXWQ128,
28281 IX86_BUILTIN_PMOVZXDQ128,
28283 IX86_BUILTIN_PMULDQ128,
28284 IX86_BUILTIN_PMULLD128,
28286 IX86_BUILTIN_ROUNDSD,
28287 IX86_BUILTIN_ROUNDSS,
28289 IX86_BUILTIN_ROUNDPD,
28290 IX86_BUILTIN_ROUNDPS,
28292 IX86_BUILTIN_FLOORPD,
28293 IX86_BUILTIN_CEILPD,
28294 IX86_BUILTIN_TRUNCPD,
28295 IX86_BUILTIN_RINTPD,
28296 IX86_BUILTIN_ROUNDPD_AZ,
28298 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28299 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28300 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28302 IX86_BUILTIN_FLOORPS,
28303 IX86_BUILTIN_CEILPS,
28304 IX86_BUILTIN_TRUNCPS,
28305 IX86_BUILTIN_RINTPS,
28306 IX86_BUILTIN_ROUNDPS_AZ,
28308 IX86_BUILTIN_FLOORPS_SFIX,
28309 IX86_BUILTIN_CEILPS_SFIX,
28310 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28312 IX86_BUILTIN_PTESTZ,
28313 IX86_BUILTIN_PTESTC,
28314 IX86_BUILTIN_PTESTNZC,
28316 IX86_BUILTIN_VEC_INIT_V2SI,
28317 IX86_BUILTIN_VEC_INIT_V4HI,
28318 IX86_BUILTIN_VEC_INIT_V8QI,
28319 IX86_BUILTIN_VEC_EXT_V2DF,
28320 IX86_BUILTIN_VEC_EXT_V2DI,
28321 IX86_BUILTIN_VEC_EXT_V4SF,
28322 IX86_BUILTIN_VEC_EXT_V4SI,
28323 IX86_BUILTIN_VEC_EXT_V8HI,
28324 IX86_BUILTIN_VEC_EXT_V2SI,
28325 IX86_BUILTIN_VEC_EXT_V4HI,
28326 IX86_BUILTIN_VEC_EXT_V16QI,
28327 IX86_BUILTIN_VEC_SET_V2DI,
28328 IX86_BUILTIN_VEC_SET_V4SF,
28329 IX86_BUILTIN_VEC_SET_V4SI,
28330 IX86_BUILTIN_VEC_SET_V8HI,
28331 IX86_BUILTIN_VEC_SET_V4HI,
28332 IX86_BUILTIN_VEC_SET_V16QI,
28334 IX86_BUILTIN_VEC_PACK_SFIX,
28335 IX86_BUILTIN_VEC_PACK_SFIX256,
28337 /* SSE4.2. */
28338 IX86_BUILTIN_CRC32QI,
28339 IX86_BUILTIN_CRC32HI,
28340 IX86_BUILTIN_CRC32SI,
28341 IX86_BUILTIN_CRC32DI,
28343 IX86_BUILTIN_PCMPESTRI128,
28344 IX86_BUILTIN_PCMPESTRM128,
28345 IX86_BUILTIN_PCMPESTRA128,
28346 IX86_BUILTIN_PCMPESTRC128,
28347 IX86_BUILTIN_PCMPESTRO128,
28348 IX86_BUILTIN_PCMPESTRS128,
28349 IX86_BUILTIN_PCMPESTRZ128,
28350 IX86_BUILTIN_PCMPISTRI128,
28351 IX86_BUILTIN_PCMPISTRM128,
28352 IX86_BUILTIN_PCMPISTRA128,
28353 IX86_BUILTIN_PCMPISTRC128,
28354 IX86_BUILTIN_PCMPISTRO128,
28355 IX86_BUILTIN_PCMPISTRS128,
28356 IX86_BUILTIN_PCMPISTRZ128,
28358 IX86_BUILTIN_PCMPGTQ,
28360 /* AES instructions */
28361 IX86_BUILTIN_AESENC128,
28362 IX86_BUILTIN_AESENCLAST128,
28363 IX86_BUILTIN_AESDEC128,
28364 IX86_BUILTIN_AESDECLAST128,
28365 IX86_BUILTIN_AESIMC128,
28366 IX86_BUILTIN_AESKEYGENASSIST128,
28368 /* PCLMUL instruction */
28369 IX86_BUILTIN_PCLMULQDQ128,
28371 /* AVX */
28372 IX86_BUILTIN_ADDPD256,
28373 IX86_BUILTIN_ADDPS256,
28374 IX86_BUILTIN_ADDSUBPD256,
28375 IX86_BUILTIN_ADDSUBPS256,
28376 IX86_BUILTIN_ANDPD256,
28377 IX86_BUILTIN_ANDPS256,
28378 IX86_BUILTIN_ANDNPD256,
28379 IX86_BUILTIN_ANDNPS256,
28380 IX86_BUILTIN_BLENDPD256,
28381 IX86_BUILTIN_BLENDPS256,
28382 IX86_BUILTIN_BLENDVPD256,
28383 IX86_BUILTIN_BLENDVPS256,
28384 IX86_BUILTIN_DIVPD256,
28385 IX86_BUILTIN_DIVPS256,
28386 IX86_BUILTIN_DPPS256,
28387 IX86_BUILTIN_HADDPD256,
28388 IX86_BUILTIN_HADDPS256,
28389 IX86_BUILTIN_HSUBPD256,
28390 IX86_BUILTIN_HSUBPS256,
28391 IX86_BUILTIN_MAXPD256,
28392 IX86_BUILTIN_MAXPS256,
28393 IX86_BUILTIN_MINPD256,
28394 IX86_BUILTIN_MINPS256,
28395 IX86_BUILTIN_MULPD256,
28396 IX86_BUILTIN_MULPS256,
28397 IX86_BUILTIN_ORPD256,
28398 IX86_BUILTIN_ORPS256,
28399 IX86_BUILTIN_SHUFPD256,
28400 IX86_BUILTIN_SHUFPS256,
28401 IX86_BUILTIN_SUBPD256,
28402 IX86_BUILTIN_SUBPS256,
28403 IX86_BUILTIN_XORPD256,
28404 IX86_BUILTIN_XORPS256,
28405 IX86_BUILTIN_CMPSD,
28406 IX86_BUILTIN_CMPSS,
28407 IX86_BUILTIN_CMPPD,
28408 IX86_BUILTIN_CMPPS,
28409 IX86_BUILTIN_CMPPD256,
28410 IX86_BUILTIN_CMPPS256,
28411 IX86_BUILTIN_CVTDQ2PD256,
28412 IX86_BUILTIN_CVTDQ2PS256,
28413 IX86_BUILTIN_CVTPD2PS256,
28414 IX86_BUILTIN_CVTPS2DQ256,
28415 IX86_BUILTIN_CVTPS2PD256,
28416 IX86_BUILTIN_CVTTPD2DQ256,
28417 IX86_BUILTIN_CVTPD2DQ256,
28418 IX86_BUILTIN_CVTTPS2DQ256,
28419 IX86_BUILTIN_EXTRACTF128PD256,
28420 IX86_BUILTIN_EXTRACTF128PS256,
28421 IX86_BUILTIN_EXTRACTF128SI256,
28422 IX86_BUILTIN_VZEROALL,
28423 IX86_BUILTIN_VZEROUPPER,
28424 IX86_BUILTIN_VPERMILVARPD,
28425 IX86_BUILTIN_VPERMILVARPS,
28426 IX86_BUILTIN_VPERMILVARPD256,
28427 IX86_BUILTIN_VPERMILVARPS256,
28428 IX86_BUILTIN_VPERMILPD,
28429 IX86_BUILTIN_VPERMILPS,
28430 IX86_BUILTIN_VPERMILPD256,
28431 IX86_BUILTIN_VPERMILPS256,
28432 IX86_BUILTIN_VPERMIL2PD,
28433 IX86_BUILTIN_VPERMIL2PS,
28434 IX86_BUILTIN_VPERMIL2PD256,
28435 IX86_BUILTIN_VPERMIL2PS256,
28436 IX86_BUILTIN_VPERM2F128PD256,
28437 IX86_BUILTIN_VPERM2F128PS256,
28438 IX86_BUILTIN_VPERM2F128SI256,
28439 IX86_BUILTIN_VBROADCASTSS,
28440 IX86_BUILTIN_VBROADCASTSD256,
28441 IX86_BUILTIN_VBROADCASTSS256,
28442 IX86_BUILTIN_VBROADCASTPD256,
28443 IX86_BUILTIN_VBROADCASTPS256,
28444 IX86_BUILTIN_VINSERTF128PD256,
28445 IX86_BUILTIN_VINSERTF128PS256,
28446 IX86_BUILTIN_VINSERTF128SI256,
28447 IX86_BUILTIN_LOADUPD256,
28448 IX86_BUILTIN_LOADUPS256,
28449 IX86_BUILTIN_STOREUPD256,
28450 IX86_BUILTIN_STOREUPS256,
28451 IX86_BUILTIN_LDDQU256,
28452 IX86_BUILTIN_MOVNTDQ256,
28453 IX86_BUILTIN_MOVNTPD256,
28454 IX86_BUILTIN_MOVNTPS256,
28455 IX86_BUILTIN_LOADDQU256,
28456 IX86_BUILTIN_STOREDQU256,
28457 IX86_BUILTIN_MASKLOADPD,
28458 IX86_BUILTIN_MASKLOADPS,
28459 IX86_BUILTIN_MASKSTOREPD,
28460 IX86_BUILTIN_MASKSTOREPS,
28461 IX86_BUILTIN_MASKLOADPD256,
28462 IX86_BUILTIN_MASKLOADPS256,
28463 IX86_BUILTIN_MASKSTOREPD256,
28464 IX86_BUILTIN_MASKSTOREPS256,
28465 IX86_BUILTIN_MOVSHDUP256,
28466 IX86_BUILTIN_MOVSLDUP256,
28467 IX86_BUILTIN_MOVDDUP256,
28469 IX86_BUILTIN_SQRTPD256,
28470 IX86_BUILTIN_SQRTPS256,
28471 IX86_BUILTIN_SQRTPS_NR256,
28472 IX86_BUILTIN_RSQRTPS256,
28473 IX86_BUILTIN_RSQRTPS_NR256,
28475 IX86_BUILTIN_RCPPS256,
28477 IX86_BUILTIN_ROUNDPD256,
28478 IX86_BUILTIN_ROUNDPS256,
28480 IX86_BUILTIN_FLOORPD256,
28481 IX86_BUILTIN_CEILPD256,
28482 IX86_BUILTIN_TRUNCPD256,
28483 IX86_BUILTIN_RINTPD256,
28484 IX86_BUILTIN_ROUNDPD_AZ256,
28486 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28487 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28488 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28490 IX86_BUILTIN_FLOORPS256,
28491 IX86_BUILTIN_CEILPS256,
28492 IX86_BUILTIN_TRUNCPS256,
28493 IX86_BUILTIN_RINTPS256,
28494 IX86_BUILTIN_ROUNDPS_AZ256,
28496 IX86_BUILTIN_FLOORPS_SFIX256,
28497 IX86_BUILTIN_CEILPS_SFIX256,
28498 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28500 IX86_BUILTIN_UNPCKHPD256,
28501 IX86_BUILTIN_UNPCKLPD256,
28502 IX86_BUILTIN_UNPCKHPS256,
28503 IX86_BUILTIN_UNPCKLPS256,
28505 IX86_BUILTIN_SI256_SI,
28506 IX86_BUILTIN_PS256_PS,
28507 IX86_BUILTIN_PD256_PD,
28508 IX86_BUILTIN_SI_SI256,
28509 IX86_BUILTIN_PS_PS256,
28510 IX86_BUILTIN_PD_PD256,
28512 IX86_BUILTIN_VTESTZPD,
28513 IX86_BUILTIN_VTESTCPD,
28514 IX86_BUILTIN_VTESTNZCPD,
28515 IX86_BUILTIN_VTESTZPS,
28516 IX86_BUILTIN_VTESTCPS,
28517 IX86_BUILTIN_VTESTNZCPS,
28518 IX86_BUILTIN_VTESTZPD256,
28519 IX86_BUILTIN_VTESTCPD256,
28520 IX86_BUILTIN_VTESTNZCPD256,
28521 IX86_BUILTIN_VTESTZPS256,
28522 IX86_BUILTIN_VTESTCPS256,
28523 IX86_BUILTIN_VTESTNZCPS256,
28524 IX86_BUILTIN_PTESTZ256,
28525 IX86_BUILTIN_PTESTC256,
28526 IX86_BUILTIN_PTESTNZC256,
28528 IX86_BUILTIN_MOVMSKPD256,
28529 IX86_BUILTIN_MOVMSKPS256,
28531 /* AVX2 */
28532 IX86_BUILTIN_MPSADBW256,
28533 IX86_BUILTIN_PABSB256,
28534 IX86_BUILTIN_PABSW256,
28535 IX86_BUILTIN_PABSD256,
28536 IX86_BUILTIN_PACKSSDW256,
28537 IX86_BUILTIN_PACKSSWB256,
28538 IX86_BUILTIN_PACKUSDW256,
28539 IX86_BUILTIN_PACKUSWB256,
28540 IX86_BUILTIN_PADDB256,
28541 IX86_BUILTIN_PADDW256,
28542 IX86_BUILTIN_PADDD256,
28543 IX86_BUILTIN_PADDQ256,
28544 IX86_BUILTIN_PADDSB256,
28545 IX86_BUILTIN_PADDSW256,
28546 IX86_BUILTIN_PADDUSB256,
28547 IX86_BUILTIN_PADDUSW256,
28548 IX86_BUILTIN_PALIGNR256,
28549 IX86_BUILTIN_AND256I,
28550 IX86_BUILTIN_ANDNOT256I,
28551 IX86_BUILTIN_PAVGB256,
28552 IX86_BUILTIN_PAVGW256,
28553 IX86_BUILTIN_PBLENDVB256,
28554 IX86_BUILTIN_PBLENDVW256,
28555 IX86_BUILTIN_PCMPEQB256,
28556 IX86_BUILTIN_PCMPEQW256,
28557 IX86_BUILTIN_PCMPEQD256,
28558 IX86_BUILTIN_PCMPEQQ256,
28559 IX86_BUILTIN_PCMPGTB256,
28560 IX86_BUILTIN_PCMPGTW256,
28561 IX86_BUILTIN_PCMPGTD256,
28562 IX86_BUILTIN_PCMPGTQ256,
28563 IX86_BUILTIN_PHADDW256,
28564 IX86_BUILTIN_PHADDD256,
28565 IX86_BUILTIN_PHADDSW256,
28566 IX86_BUILTIN_PHSUBW256,
28567 IX86_BUILTIN_PHSUBD256,
28568 IX86_BUILTIN_PHSUBSW256,
28569 IX86_BUILTIN_PMADDUBSW256,
28570 IX86_BUILTIN_PMADDWD256,
28571 IX86_BUILTIN_PMAXSB256,
28572 IX86_BUILTIN_PMAXSW256,
28573 IX86_BUILTIN_PMAXSD256,
28574 IX86_BUILTIN_PMAXUB256,
28575 IX86_BUILTIN_PMAXUW256,
28576 IX86_BUILTIN_PMAXUD256,
28577 IX86_BUILTIN_PMINSB256,
28578 IX86_BUILTIN_PMINSW256,
28579 IX86_BUILTIN_PMINSD256,
28580 IX86_BUILTIN_PMINUB256,
28581 IX86_BUILTIN_PMINUW256,
28582 IX86_BUILTIN_PMINUD256,
28583 IX86_BUILTIN_PMOVMSKB256,
28584 IX86_BUILTIN_PMOVSXBW256,
28585 IX86_BUILTIN_PMOVSXBD256,
28586 IX86_BUILTIN_PMOVSXBQ256,
28587 IX86_BUILTIN_PMOVSXWD256,
28588 IX86_BUILTIN_PMOVSXWQ256,
28589 IX86_BUILTIN_PMOVSXDQ256,
28590 IX86_BUILTIN_PMOVZXBW256,
28591 IX86_BUILTIN_PMOVZXBD256,
28592 IX86_BUILTIN_PMOVZXBQ256,
28593 IX86_BUILTIN_PMOVZXWD256,
28594 IX86_BUILTIN_PMOVZXWQ256,
28595 IX86_BUILTIN_PMOVZXDQ256,
28596 IX86_BUILTIN_PMULDQ256,
28597 IX86_BUILTIN_PMULHRSW256,
28598 IX86_BUILTIN_PMULHUW256,
28599 IX86_BUILTIN_PMULHW256,
28600 IX86_BUILTIN_PMULLW256,
28601 IX86_BUILTIN_PMULLD256,
28602 IX86_BUILTIN_PMULUDQ256,
28603 IX86_BUILTIN_POR256,
28604 IX86_BUILTIN_PSADBW256,
28605 IX86_BUILTIN_PSHUFB256,
28606 IX86_BUILTIN_PSHUFD256,
28607 IX86_BUILTIN_PSHUFHW256,
28608 IX86_BUILTIN_PSHUFLW256,
28609 IX86_BUILTIN_PSIGNB256,
28610 IX86_BUILTIN_PSIGNW256,
28611 IX86_BUILTIN_PSIGND256,
28612 IX86_BUILTIN_PSLLDQI256,
28613 IX86_BUILTIN_PSLLWI256,
28614 IX86_BUILTIN_PSLLW256,
28615 IX86_BUILTIN_PSLLDI256,
28616 IX86_BUILTIN_PSLLD256,
28617 IX86_BUILTIN_PSLLQI256,
28618 IX86_BUILTIN_PSLLQ256,
28619 IX86_BUILTIN_PSRAWI256,
28620 IX86_BUILTIN_PSRAW256,
28621 IX86_BUILTIN_PSRADI256,
28622 IX86_BUILTIN_PSRAD256,
28623 IX86_BUILTIN_PSRLDQI256,
28624 IX86_BUILTIN_PSRLWI256,
28625 IX86_BUILTIN_PSRLW256,
28626 IX86_BUILTIN_PSRLDI256,
28627 IX86_BUILTIN_PSRLD256,
28628 IX86_BUILTIN_PSRLQI256,
28629 IX86_BUILTIN_PSRLQ256,
28630 IX86_BUILTIN_PSUBB256,
28631 IX86_BUILTIN_PSUBW256,
28632 IX86_BUILTIN_PSUBD256,
28633 IX86_BUILTIN_PSUBQ256,
28634 IX86_BUILTIN_PSUBSB256,
28635 IX86_BUILTIN_PSUBSW256,
28636 IX86_BUILTIN_PSUBUSB256,
28637 IX86_BUILTIN_PSUBUSW256,
28638 IX86_BUILTIN_PUNPCKHBW256,
28639 IX86_BUILTIN_PUNPCKHWD256,
28640 IX86_BUILTIN_PUNPCKHDQ256,
28641 IX86_BUILTIN_PUNPCKHQDQ256,
28642 IX86_BUILTIN_PUNPCKLBW256,
28643 IX86_BUILTIN_PUNPCKLWD256,
28644 IX86_BUILTIN_PUNPCKLDQ256,
28645 IX86_BUILTIN_PUNPCKLQDQ256,
28646 IX86_BUILTIN_PXOR256,
28647 IX86_BUILTIN_MOVNTDQA256,
28648 IX86_BUILTIN_VBROADCASTSS_PS,
28649 IX86_BUILTIN_VBROADCASTSS_PS256,
28650 IX86_BUILTIN_VBROADCASTSD_PD256,
28651 IX86_BUILTIN_VBROADCASTSI256,
28652 IX86_BUILTIN_PBLENDD256,
28653 IX86_BUILTIN_PBLENDD128,
28654 IX86_BUILTIN_PBROADCASTB256,
28655 IX86_BUILTIN_PBROADCASTW256,
28656 IX86_BUILTIN_PBROADCASTD256,
28657 IX86_BUILTIN_PBROADCASTQ256,
28658 IX86_BUILTIN_PBROADCASTB128,
28659 IX86_BUILTIN_PBROADCASTW128,
28660 IX86_BUILTIN_PBROADCASTD128,
28661 IX86_BUILTIN_PBROADCASTQ128,
28662 IX86_BUILTIN_VPERMVARSI256,
28663 IX86_BUILTIN_VPERMDF256,
28664 IX86_BUILTIN_VPERMVARSF256,
28665 IX86_BUILTIN_VPERMDI256,
28666 IX86_BUILTIN_VPERMTI256,
28667 IX86_BUILTIN_VEXTRACT128I256,
28668 IX86_BUILTIN_VINSERT128I256,
28669 IX86_BUILTIN_MASKLOADD,
28670 IX86_BUILTIN_MASKLOADQ,
28671 IX86_BUILTIN_MASKLOADD256,
28672 IX86_BUILTIN_MASKLOADQ256,
28673 IX86_BUILTIN_MASKSTORED,
28674 IX86_BUILTIN_MASKSTOREQ,
28675 IX86_BUILTIN_MASKSTORED256,
28676 IX86_BUILTIN_MASKSTOREQ256,
28677 IX86_BUILTIN_PSLLVV4DI,
28678 IX86_BUILTIN_PSLLVV2DI,
28679 IX86_BUILTIN_PSLLVV8SI,
28680 IX86_BUILTIN_PSLLVV4SI,
28681 IX86_BUILTIN_PSRAVV8SI,
28682 IX86_BUILTIN_PSRAVV4SI,
28683 IX86_BUILTIN_PSRLVV4DI,
28684 IX86_BUILTIN_PSRLVV2DI,
28685 IX86_BUILTIN_PSRLVV8SI,
28686 IX86_BUILTIN_PSRLVV4SI,
28688 IX86_BUILTIN_GATHERSIV2DF,
28689 IX86_BUILTIN_GATHERSIV4DF,
28690 IX86_BUILTIN_GATHERDIV2DF,
28691 IX86_BUILTIN_GATHERDIV4DF,
28692 IX86_BUILTIN_GATHERSIV4SF,
28693 IX86_BUILTIN_GATHERSIV8SF,
28694 IX86_BUILTIN_GATHERDIV4SF,
28695 IX86_BUILTIN_GATHERDIV8SF,
28696 IX86_BUILTIN_GATHERSIV2DI,
28697 IX86_BUILTIN_GATHERSIV4DI,
28698 IX86_BUILTIN_GATHERDIV2DI,
28699 IX86_BUILTIN_GATHERDIV4DI,
28700 IX86_BUILTIN_GATHERSIV4SI,
28701 IX86_BUILTIN_GATHERSIV8SI,
28702 IX86_BUILTIN_GATHERDIV4SI,
28703 IX86_BUILTIN_GATHERDIV8SI,
28705 /* AVX512F */
28706 IX86_BUILTIN_SI512_SI256,
28707 IX86_BUILTIN_PD512_PD256,
28708 IX86_BUILTIN_PS512_PS256,
28709 IX86_BUILTIN_SI512_SI,
28710 IX86_BUILTIN_PD512_PD,
28711 IX86_BUILTIN_PS512_PS,
28712 IX86_BUILTIN_ADDPD512,
28713 IX86_BUILTIN_ADDPS512,
28714 IX86_BUILTIN_ADDSD_ROUND,
28715 IX86_BUILTIN_ADDSS_ROUND,
28716 IX86_BUILTIN_ALIGND512,
28717 IX86_BUILTIN_ALIGNQ512,
28718 IX86_BUILTIN_BLENDMD512,
28719 IX86_BUILTIN_BLENDMPD512,
28720 IX86_BUILTIN_BLENDMPS512,
28721 IX86_BUILTIN_BLENDMQ512,
28722 IX86_BUILTIN_BROADCASTF32X4_512,
28723 IX86_BUILTIN_BROADCASTF64X4_512,
28724 IX86_BUILTIN_BROADCASTI32X4_512,
28725 IX86_BUILTIN_BROADCASTI64X4_512,
28726 IX86_BUILTIN_BROADCASTSD512,
28727 IX86_BUILTIN_BROADCASTSS512,
28728 IX86_BUILTIN_CMPD512,
28729 IX86_BUILTIN_CMPPD512,
28730 IX86_BUILTIN_CMPPS512,
28731 IX86_BUILTIN_CMPQ512,
28732 IX86_BUILTIN_CMPSD_MASK,
28733 IX86_BUILTIN_CMPSS_MASK,
28734 IX86_BUILTIN_COMIDF,
28735 IX86_BUILTIN_COMISF,
28736 IX86_BUILTIN_COMPRESSPD512,
28737 IX86_BUILTIN_COMPRESSPDSTORE512,
28738 IX86_BUILTIN_COMPRESSPS512,
28739 IX86_BUILTIN_COMPRESSPSSTORE512,
28740 IX86_BUILTIN_CVTDQ2PD512,
28741 IX86_BUILTIN_CVTDQ2PS512,
28742 IX86_BUILTIN_CVTPD2DQ512,
28743 IX86_BUILTIN_CVTPD2PS512,
28744 IX86_BUILTIN_CVTPD2UDQ512,
28745 IX86_BUILTIN_CVTPH2PS512,
28746 IX86_BUILTIN_CVTPS2DQ512,
28747 IX86_BUILTIN_CVTPS2PD512,
28748 IX86_BUILTIN_CVTPS2PH512,
28749 IX86_BUILTIN_CVTPS2UDQ512,
28750 IX86_BUILTIN_CVTSD2SS_ROUND,
28751 IX86_BUILTIN_CVTSI2SD64,
28752 IX86_BUILTIN_CVTSI2SS32,
28753 IX86_BUILTIN_CVTSI2SS64,
28754 IX86_BUILTIN_CVTSS2SD_ROUND,
28755 IX86_BUILTIN_CVTTPD2DQ512,
28756 IX86_BUILTIN_CVTTPD2UDQ512,
28757 IX86_BUILTIN_CVTTPS2DQ512,
28758 IX86_BUILTIN_CVTTPS2UDQ512,
28759 IX86_BUILTIN_CVTUDQ2PD512,
28760 IX86_BUILTIN_CVTUDQ2PS512,
28761 IX86_BUILTIN_CVTUSI2SD32,
28762 IX86_BUILTIN_CVTUSI2SD64,
28763 IX86_BUILTIN_CVTUSI2SS32,
28764 IX86_BUILTIN_CVTUSI2SS64,
28765 IX86_BUILTIN_DIVPD512,
28766 IX86_BUILTIN_DIVPS512,
28767 IX86_BUILTIN_DIVSD_ROUND,
28768 IX86_BUILTIN_DIVSS_ROUND,
28769 IX86_BUILTIN_EXPANDPD512,
28770 IX86_BUILTIN_EXPANDPD512Z,
28771 IX86_BUILTIN_EXPANDPDLOAD512,
28772 IX86_BUILTIN_EXPANDPDLOAD512Z,
28773 IX86_BUILTIN_EXPANDPS512,
28774 IX86_BUILTIN_EXPANDPS512Z,
28775 IX86_BUILTIN_EXPANDPSLOAD512,
28776 IX86_BUILTIN_EXPANDPSLOAD512Z,
28777 IX86_BUILTIN_EXTRACTF32X4,
28778 IX86_BUILTIN_EXTRACTF64X4,
28779 IX86_BUILTIN_EXTRACTI32X4,
28780 IX86_BUILTIN_EXTRACTI64X4,
28781 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28782 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28783 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28784 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28785 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28786 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28787 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28788 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28789 IX86_BUILTIN_GETEXPPD512,
28790 IX86_BUILTIN_GETEXPPS512,
28791 IX86_BUILTIN_GETEXPSD128,
28792 IX86_BUILTIN_GETEXPSS128,
28793 IX86_BUILTIN_GETMANTPD512,
28794 IX86_BUILTIN_GETMANTPS512,
28795 IX86_BUILTIN_GETMANTSD128,
28796 IX86_BUILTIN_GETMANTSS128,
28797 IX86_BUILTIN_INSERTF32X4,
28798 IX86_BUILTIN_INSERTF64X4,
28799 IX86_BUILTIN_INSERTI32X4,
28800 IX86_BUILTIN_INSERTI64X4,
28801 IX86_BUILTIN_LOADAPD512,
28802 IX86_BUILTIN_LOADAPS512,
28803 IX86_BUILTIN_LOADDQUDI512,
28804 IX86_BUILTIN_LOADDQUSI512,
28805 IX86_BUILTIN_LOADUPD512,
28806 IX86_BUILTIN_LOADUPS512,
28807 IX86_BUILTIN_MAXPD512,
28808 IX86_BUILTIN_MAXPS512,
28809 IX86_BUILTIN_MAXSD_ROUND,
28810 IX86_BUILTIN_MAXSS_ROUND,
28811 IX86_BUILTIN_MINPD512,
28812 IX86_BUILTIN_MINPS512,
28813 IX86_BUILTIN_MINSD_ROUND,
28814 IX86_BUILTIN_MINSS_ROUND,
28815 IX86_BUILTIN_MOVAPD512,
28816 IX86_BUILTIN_MOVAPS512,
28817 IX86_BUILTIN_MOVDDUP512,
28818 IX86_BUILTIN_MOVDQA32LOAD512,
28819 IX86_BUILTIN_MOVDQA32STORE512,
28820 IX86_BUILTIN_MOVDQA32_512,
28821 IX86_BUILTIN_MOVDQA64LOAD512,
28822 IX86_BUILTIN_MOVDQA64STORE512,
28823 IX86_BUILTIN_MOVDQA64_512,
28824 IX86_BUILTIN_MOVNTDQ512,
28825 IX86_BUILTIN_MOVNTDQA512,
28826 IX86_BUILTIN_MOVNTPD512,
28827 IX86_BUILTIN_MOVNTPS512,
28828 IX86_BUILTIN_MOVSHDUP512,
28829 IX86_BUILTIN_MOVSLDUP512,
28830 IX86_BUILTIN_MULPD512,
28831 IX86_BUILTIN_MULPS512,
28832 IX86_BUILTIN_MULSD_ROUND,
28833 IX86_BUILTIN_MULSS_ROUND,
28834 IX86_BUILTIN_PABSD512,
28835 IX86_BUILTIN_PABSQ512,
28836 IX86_BUILTIN_PADDD512,
28837 IX86_BUILTIN_PADDQ512,
28838 IX86_BUILTIN_PANDD512,
28839 IX86_BUILTIN_PANDND512,
28840 IX86_BUILTIN_PANDNQ512,
28841 IX86_BUILTIN_PANDQ512,
28842 IX86_BUILTIN_PBROADCASTD512,
28843 IX86_BUILTIN_PBROADCASTD512_GPR,
28844 IX86_BUILTIN_PBROADCASTMB512,
28845 IX86_BUILTIN_PBROADCASTMW512,
28846 IX86_BUILTIN_PBROADCASTQ512,
28847 IX86_BUILTIN_PBROADCASTQ512_GPR,
28848 IX86_BUILTIN_PCMPEQD512_MASK,
28849 IX86_BUILTIN_PCMPEQQ512_MASK,
28850 IX86_BUILTIN_PCMPGTD512_MASK,
28851 IX86_BUILTIN_PCMPGTQ512_MASK,
28852 IX86_BUILTIN_PCOMPRESSD512,
28853 IX86_BUILTIN_PCOMPRESSDSTORE512,
28854 IX86_BUILTIN_PCOMPRESSQ512,
28855 IX86_BUILTIN_PCOMPRESSQSTORE512,
28856 IX86_BUILTIN_PEXPANDD512,
28857 IX86_BUILTIN_PEXPANDD512Z,
28858 IX86_BUILTIN_PEXPANDDLOAD512,
28859 IX86_BUILTIN_PEXPANDDLOAD512Z,
28860 IX86_BUILTIN_PEXPANDQ512,
28861 IX86_BUILTIN_PEXPANDQ512Z,
28862 IX86_BUILTIN_PEXPANDQLOAD512,
28863 IX86_BUILTIN_PEXPANDQLOAD512Z,
28864 IX86_BUILTIN_PMAXSD512,
28865 IX86_BUILTIN_PMAXSQ512,
28866 IX86_BUILTIN_PMAXUD512,
28867 IX86_BUILTIN_PMAXUQ512,
28868 IX86_BUILTIN_PMINSD512,
28869 IX86_BUILTIN_PMINSQ512,
28870 IX86_BUILTIN_PMINUD512,
28871 IX86_BUILTIN_PMINUQ512,
28872 IX86_BUILTIN_PMOVDB512,
28873 IX86_BUILTIN_PMOVDB512_MEM,
28874 IX86_BUILTIN_PMOVDW512,
28875 IX86_BUILTIN_PMOVDW512_MEM,
28876 IX86_BUILTIN_PMOVQB512,
28877 IX86_BUILTIN_PMOVQB512_MEM,
28878 IX86_BUILTIN_PMOVQD512,
28879 IX86_BUILTIN_PMOVQD512_MEM,
28880 IX86_BUILTIN_PMOVQW512,
28881 IX86_BUILTIN_PMOVQW512_MEM,
28882 IX86_BUILTIN_PMOVSDB512,
28883 IX86_BUILTIN_PMOVSDB512_MEM,
28884 IX86_BUILTIN_PMOVSDW512,
28885 IX86_BUILTIN_PMOVSDW512_MEM,
28886 IX86_BUILTIN_PMOVSQB512,
28887 IX86_BUILTIN_PMOVSQB512_MEM,
28888 IX86_BUILTIN_PMOVSQD512,
28889 IX86_BUILTIN_PMOVSQD512_MEM,
28890 IX86_BUILTIN_PMOVSQW512,
28891 IX86_BUILTIN_PMOVSQW512_MEM,
28892 IX86_BUILTIN_PMOVSXBD512,
28893 IX86_BUILTIN_PMOVSXBQ512,
28894 IX86_BUILTIN_PMOVSXDQ512,
28895 IX86_BUILTIN_PMOVSXWD512,
28896 IX86_BUILTIN_PMOVSXWQ512,
28897 IX86_BUILTIN_PMOVUSDB512,
28898 IX86_BUILTIN_PMOVUSDB512_MEM,
28899 IX86_BUILTIN_PMOVUSDW512,
28900 IX86_BUILTIN_PMOVUSDW512_MEM,
28901 IX86_BUILTIN_PMOVUSQB512,
28902 IX86_BUILTIN_PMOVUSQB512_MEM,
28903 IX86_BUILTIN_PMOVUSQD512,
28904 IX86_BUILTIN_PMOVUSQD512_MEM,
28905 IX86_BUILTIN_PMOVUSQW512,
28906 IX86_BUILTIN_PMOVUSQW512_MEM,
28907 IX86_BUILTIN_PMOVZXBD512,
28908 IX86_BUILTIN_PMOVZXBQ512,
28909 IX86_BUILTIN_PMOVZXDQ512,
28910 IX86_BUILTIN_PMOVZXWD512,
28911 IX86_BUILTIN_PMOVZXWQ512,
28912 IX86_BUILTIN_PMULDQ512,
28913 IX86_BUILTIN_PMULLD512,
28914 IX86_BUILTIN_PMULUDQ512,
28915 IX86_BUILTIN_PORD512,
28916 IX86_BUILTIN_PORQ512,
28917 IX86_BUILTIN_PROLD512,
28918 IX86_BUILTIN_PROLQ512,
28919 IX86_BUILTIN_PROLVD512,
28920 IX86_BUILTIN_PROLVQ512,
28921 IX86_BUILTIN_PRORD512,
28922 IX86_BUILTIN_PRORQ512,
28923 IX86_BUILTIN_PRORVD512,
28924 IX86_BUILTIN_PRORVQ512,
28925 IX86_BUILTIN_PSHUFD512,
28926 IX86_BUILTIN_PSLLD512,
28927 IX86_BUILTIN_PSLLDI512,
28928 IX86_BUILTIN_PSLLQ512,
28929 IX86_BUILTIN_PSLLQI512,
28930 IX86_BUILTIN_PSLLVV16SI,
28931 IX86_BUILTIN_PSLLVV8DI,
28932 IX86_BUILTIN_PSRAD512,
28933 IX86_BUILTIN_PSRADI512,
28934 IX86_BUILTIN_PSRAQ512,
28935 IX86_BUILTIN_PSRAQI512,
28936 IX86_BUILTIN_PSRAVV16SI,
28937 IX86_BUILTIN_PSRAVV8DI,
28938 IX86_BUILTIN_PSRLD512,
28939 IX86_BUILTIN_PSRLDI512,
28940 IX86_BUILTIN_PSRLQ512,
28941 IX86_BUILTIN_PSRLQI512,
28942 IX86_BUILTIN_PSRLVV16SI,
28943 IX86_BUILTIN_PSRLVV8DI,
28944 IX86_BUILTIN_PSUBD512,
28945 IX86_BUILTIN_PSUBQ512,
28946 IX86_BUILTIN_PTESTMD512,
28947 IX86_BUILTIN_PTESTMQ512,
28948 IX86_BUILTIN_PTESTNMD512,
28949 IX86_BUILTIN_PTESTNMQ512,
28950 IX86_BUILTIN_PUNPCKHDQ512,
28951 IX86_BUILTIN_PUNPCKHQDQ512,
28952 IX86_BUILTIN_PUNPCKLDQ512,
28953 IX86_BUILTIN_PUNPCKLQDQ512,
28954 IX86_BUILTIN_PXORD512,
28955 IX86_BUILTIN_PXORQ512,
28956 IX86_BUILTIN_RCP14PD512,
28957 IX86_BUILTIN_RCP14PS512,
28958 IX86_BUILTIN_RCP14SD,
28959 IX86_BUILTIN_RCP14SS,
28960 IX86_BUILTIN_RNDSCALEPD,
28961 IX86_BUILTIN_RNDSCALEPS,
28962 IX86_BUILTIN_RNDSCALESD,
28963 IX86_BUILTIN_RNDSCALESS,
28964 IX86_BUILTIN_RSQRT14PD512,
28965 IX86_BUILTIN_RSQRT14PS512,
28966 IX86_BUILTIN_RSQRT14SD,
28967 IX86_BUILTIN_RSQRT14SS,
28968 IX86_BUILTIN_SCALEFPD512,
28969 IX86_BUILTIN_SCALEFPS512,
28970 IX86_BUILTIN_SCALEFSD,
28971 IX86_BUILTIN_SCALEFSS,
28972 IX86_BUILTIN_SHUFPD512,
28973 IX86_BUILTIN_SHUFPS512,
28974 IX86_BUILTIN_SHUF_F32x4,
28975 IX86_BUILTIN_SHUF_F64x2,
28976 IX86_BUILTIN_SHUF_I32x4,
28977 IX86_BUILTIN_SHUF_I64x2,
28978 IX86_BUILTIN_SQRTPD512,
28979 IX86_BUILTIN_SQRTPD512_MASK,
28980 IX86_BUILTIN_SQRTPS512_MASK,
28981 IX86_BUILTIN_SQRTPS_NR512,
28982 IX86_BUILTIN_SQRTSD_ROUND,
28983 IX86_BUILTIN_SQRTSS_ROUND,
28984 IX86_BUILTIN_STOREAPD512,
28985 IX86_BUILTIN_STOREAPS512,
28986 IX86_BUILTIN_STOREDQUDI512,
28987 IX86_BUILTIN_STOREDQUSI512,
28988 IX86_BUILTIN_STOREUPD512,
28989 IX86_BUILTIN_STOREUPS512,
28990 IX86_BUILTIN_SUBPD512,
28991 IX86_BUILTIN_SUBPS512,
28992 IX86_BUILTIN_SUBSD_ROUND,
28993 IX86_BUILTIN_SUBSS_ROUND,
28994 IX86_BUILTIN_UCMPD512,
28995 IX86_BUILTIN_UCMPQ512,
28996 IX86_BUILTIN_UNPCKHPD512,
28997 IX86_BUILTIN_UNPCKHPS512,
28998 IX86_BUILTIN_UNPCKLPD512,
28999 IX86_BUILTIN_UNPCKLPS512,
29000 IX86_BUILTIN_VCVTSD2SI32,
29001 IX86_BUILTIN_VCVTSD2SI64,
29002 IX86_BUILTIN_VCVTSD2USI32,
29003 IX86_BUILTIN_VCVTSD2USI64,
29004 IX86_BUILTIN_VCVTSS2SI32,
29005 IX86_BUILTIN_VCVTSS2SI64,
29006 IX86_BUILTIN_VCVTSS2USI32,
29007 IX86_BUILTIN_VCVTSS2USI64,
29008 IX86_BUILTIN_VCVTTSD2SI32,
29009 IX86_BUILTIN_VCVTTSD2SI64,
29010 IX86_BUILTIN_VCVTTSD2USI32,
29011 IX86_BUILTIN_VCVTTSD2USI64,
29012 IX86_BUILTIN_VCVTTSS2SI32,
29013 IX86_BUILTIN_VCVTTSS2SI64,
29014 IX86_BUILTIN_VCVTTSS2USI32,
29015 IX86_BUILTIN_VCVTTSS2USI64,
29016 IX86_BUILTIN_VFMADDPD512_MASK,
29017 IX86_BUILTIN_VFMADDPD512_MASK3,
29018 IX86_BUILTIN_VFMADDPD512_MASKZ,
29019 IX86_BUILTIN_VFMADDPS512_MASK,
29020 IX86_BUILTIN_VFMADDPS512_MASK3,
29021 IX86_BUILTIN_VFMADDPS512_MASKZ,
29022 IX86_BUILTIN_VFMADDSD3_ROUND,
29023 IX86_BUILTIN_VFMADDSS3_ROUND,
29024 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29025 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29026 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29027 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29028 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29029 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29030 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29031 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29032 IX86_BUILTIN_VFMSUBPD512_MASK3,
29033 IX86_BUILTIN_VFMSUBPS512_MASK3,
29034 IX86_BUILTIN_VFMSUBSD3_MASK3,
29035 IX86_BUILTIN_VFMSUBSS3_MASK3,
29036 IX86_BUILTIN_VFNMADDPD512_MASK,
29037 IX86_BUILTIN_VFNMADDPS512_MASK,
29038 IX86_BUILTIN_VFNMSUBPD512_MASK,
29039 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29040 IX86_BUILTIN_VFNMSUBPS512_MASK,
29041 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29042 IX86_BUILTIN_VPCLZCNTD512,
29043 IX86_BUILTIN_VPCLZCNTQ512,
29044 IX86_BUILTIN_VPCONFLICTD512,
29045 IX86_BUILTIN_VPCONFLICTQ512,
29046 IX86_BUILTIN_VPERMDF512,
29047 IX86_BUILTIN_VPERMDI512,
29048 IX86_BUILTIN_VPERMI2VARD512,
29049 IX86_BUILTIN_VPERMI2VARPD512,
29050 IX86_BUILTIN_VPERMI2VARPS512,
29051 IX86_BUILTIN_VPERMI2VARQ512,
29052 IX86_BUILTIN_VPERMILPD512,
29053 IX86_BUILTIN_VPERMILPS512,
29054 IX86_BUILTIN_VPERMILVARPD512,
29055 IX86_BUILTIN_VPERMILVARPS512,
29056 IX86_BUILTIN_VPERMT2VARD512,
29057 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29058 IX86_BUILTIN_VPERMT2VARPD512,
29059 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29060 IX86_BUILTIN_VPERMT2VARPS512,
29061 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29062 IX86_BUILTIN_VPERMT2VARQ512,
29063 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29064 IX86_BUILTIN_VPERMVARDF512,
29065 IX86_BUILTIN_VPERMVARDI512,
29066 IX86_BUILTIN_VPERMVARSF512,
29067 IX86_BUILTIN_VPERMVARSI512,
29068 IX86_BUILTIN_VTERNLOGD512_MASK,
29069 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29070 IX86_BUILTIN_VTERNLOGQ512_MASK,
29071 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29073 /* Mask arithmetic operations */
29074 IX86_BUILTIN_KAND16,
29075 IX86_BUILTIN_KANDN16,
29076 IX86_BUILTIN_KNOT16,
29077 IX86_BUILTIN_KOR16,
29078 IX86_BUILTIN_KORTESTC16,
29079 IX86_BUILTIN_KORTESTZ16,
29080 IX86_BUILTIN_KUNPCKBW,
29081 IX86_BUILTIN_KXNOR16,
29082 IX86_BUILTIN_KXOR16,
29083 IX86_BUILTIN_KMOV16,
29085 /* AVX512VL. */
29086 IX86_BUILTIN_PMOVUSQD256_MEM,
29087 IX86_BUILTIN_PMOVUSQD128_MEM,
29088 IX86_BUILTIN_PMOVSQD256_MEM,
29089 IX86_BUILTIN_PMOVSQD128_MEM,
29090 IX86_BUILTIN_PMOVQD256_MEM,
29091 IX86_BUILTIN_PMOVQD128_MEM,
29092 IX86_BUILTIN_PMOVUSQW256_MEM,
29093 IX86_BUILTIN_PMOVUSQW128_MEM,
29094 IX86_BUILTIN_PMOVSQW256_MEM,
29095 IX86_BUILTIN_PMOVSQW128_MEM,
29096 IX86_BUILTIN_PMOVQW256_MEM,
29097 IX86_BUILTIN_PMOVQW128_MEM,
29098 IX86_BUILTIN_PMOVUSQB256_MEM,
29099 IX86_BUILTIN_PMOVUSQB128_MEM,
29100 IX86_BUILTIN_PMOVSQB256_MEM,
29101 IX86_BUILTIN_PMOVSQB128_MEM,
29102 IX86_BUILTIN_PMOVQB256_MEM,
29103 IX86_BUILTIN_PMOVQB128_MEM,
29104 IX86_BUILTIN_PMOVUSDW256_MEM,
29105 IX86_BUILTIN_PMOVUSDW128_MEM,
29106 IX86_BUILTIN_PMOVSDW256_MEM,
29107 IX86_BUILTIN_PMOVSDW128_MEM,
29108 IX86_BUILTIN_PMOVDW256_MEM,
29109 IX86_BUILTIN_PMOVDW128_MEM,
29110 IX86_BUILTIN_PMOVUSDB256_MEM,
29111 IX86_BUILTIN_PMOVUSDB128_MEM,
29112 IX86_BUILTIN_PMOVSDB256_MEM,
29113 IX86_BUILTIN_PMOVSDB128_MEM,
29114 IX86_BUILTIN_PMOVDB256_MEM,
29115 IX86_BUILTIN_PMOVDB128_MEM,
29116 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29117 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29118 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29119 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29120 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29121 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29122 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29123 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29124 IX86_BUILTIN_LOADAPD256_MASK,
29125 IX86_BUILTIN_LOADAPD128_MASK,
29126 IX86_BUILTIN_LOADAPS256_MASK,
29127 IX86_BUILTIN_LOADAPS128_MASK,
29128 IX86_BUILTIN_STOREAPD256_MASK,
29129 IX86_BUILTIN_STOREAPD128_MASK,
29130 IX86_BUILTIN_STOREAPS256_MASK,
29131 IX86_BUILTIN_STOREAPS128_MASK,
29132 IX86_BUILTIN_LOADUPD256_MASK,
29133 IX86_BUILTIN_LOADUPD128_MASK,
29134 IX86_BUILTIN_LOADUPS256_MASK,
29135 IX86_BUILTIN_LOADUPS128_MASK,
29136 IX86_BUILTIN_STOREUPD256_MASK,
29137 IX86_BUILTIN_STOREUPD128_MASK,
29138 IX86_BUILTIN_STOREUPS256_MASK,
29139 IX86_BUILTIN_STOREUPS128_MASK,
29140 IX86_BUILTIN_LOADDQUDI256_MASK,
29141 IX86_BUILTIN_LOADDQUDI128_MASK,
29142 IX86_BUILTIN_LOADDQUSI256_MASK,
29143 IX86_BUILTIN_LOADDQUSI128_MASK,
29144 IX86_BUILTIN_LOADDQUHI256_MASK,
29145 IX86_BUILTIN_LOADDQUHI128_MASK,
29146 IX86_BUILTIN_LOADDQUQI256_MASK,
29147 IX86_BUILTIN_LOADDQUQI128_MASK,
29148 IX86_BUILTIN_STOREDQUDI256_MASK,
29149 IX86_BUILTIN_STOREDQUDI128_MASK,
29150 IX86_BUILTIN_STOREDQUSI256_MASK,
29151 IX86_BUILTIN_STOREDQUSI128_MASK,
29152 IX86_BUILTIN_STOREDQUHI256_MASK,
29153 IX86_BUILTIN_STOREDQUHI128_MASK,
29154 IX86_BUILTIN_STOREDQUQI256_MASK,
29155 IX86_BUILTIN_STOREDQUQI128_MASK,
29156 IX86_BUILTIN_COMPRESSPDSTORE256,
29157 IX86_BUILTIN_COMPRESSPDSTORE128,
29158 IX86_BUILTIN_COMPRESSPSSTORE256,
29159 IX86_BUILTIN_COMPRESSPSSTORE128,
29160 IX86_BUILTIN_PCOMPRESSQSTORE256,
29161 IX86_BUILTIN_PCOMPRESSQSTORE128,
29162 IX86_BUILTIN_PCOMPRESSDSTORE256,
29163 IX86_BUILTIN_PCOMPRESSDSTORE128,
29164 IX86_BUILTIN_EXPANDPDLOAD256,
29165 IX86_BUILTIN_EXPANDPDLOAD128,
29166 IX86_BUILTIN_EXPANDPSLOAD256,
29167 IX86_BUILTIN_EXPANDPSLOAD128,
29168 IX86_BUILTIN_PEXPANDQLOAD256,
29169 IX86_BUILTIN_PEXPANDQLOAD128,
29170 IX86_BUILTIN_PEXPANDDLOAD256,
29171 IX86_BUILTIN_PEXPANDDLOAD128,
29172 IX86_BUILTIN_EXPANDPDLOAD256Z,
29173 IX86_BUILTIN_EXPANDPDLOAD128Z,
29174 IX86_BUILTIN_EXPANDPSLOAD256Z,
29175 IX86_BUILTIN_EXPANDPSLOAD128Z,
29176 IX86_BUILTIN_PEXPANDQLOAD256Z,
29177 IX86_BUILTIN_PEXPANDQLOAD128Z,
29178 IX86_BUILTIN_PEXPANDDLOAD256Z,
29179 IX86_BUILTIN_PEXPANDDLOAD128Z,
29180 IX86_BUILTIN_PALIGNR256_MASK,
29181 IX86_BUILTIN_PALIGNR128_MASK,
29182 IX86_BUILTIN_MOVDQA64_256_MASK,
29183 IX86_BUILTIN_MOVDQA64_128_MASK,
29184 IX86_BUILTIN_MOVDQA32_256_MASK,
29185 IX86_BUILTIN_MOVDQA32_128_MASK,
29186 IX86_BUILTIN_MOVAPD256_MASK,
29187 IX86_BUILTIN_MOVAPD128_MASK,
29188 IX86_BUILTIN_MOVAPS256_MASK,
29189 IX86_BUILTIN_MOVAPS128_MASK,
29190 IX86_BUILTIN_MOVDQUHI256_MASK,
29191 IX86_BUILTIN_MOVDQUHI128_MASK,
29192 IX86_BUILTIN_MOVDQUQI256_MASK,
29193 IX86_BUILTIN_MOVDQUQI128_MASK,
29194 IX86_BUILTIN_MINPS128_MASK,
29195 IX86_BUILTIN_MAXPS128_MASK,
29196 IX86_BUILTIN_MINPD128_MASK,
29197 IX86_BUILTIN_MAXPD128_MASK,
29198 IX86_BUILTIN_MAXPD256_MASK,
29199 IX86_BUILTIN_MAXPS256_MASK,
29200 IX86_BUILTIN_MINPD256_MASK,
29201 IX86_BUILTIN_MINPS256_MASK,
29202 IX86_BUILTIN_MULPS128_MASK,
29203 IX86_BUILTIN_DIVPS128_MASK,
29204 IX86_BUILTIN_MULPD128_MASK,
29205 IX86_BUILTIN_DIVPD128_MASK,
29206 IX86_BUILTIN_DIVPD256_MASK,
29207 IX86_BUILTIN_DIVPS256_MASK,
29208 IX86_BUILTIN_MULPD256_MASK,
29209 IX86_BUILTIN_MULPS256_MASK,
29210 IX86_BUILTIN_ADDPD128_MASK,
29211 IX86_BUILTIN_ADDPD256_MASK,
29212 IX86_BUILTIN_ADDPS128_MASK,
29213 IX86_BUILTIN_ADDPS256_MASK,
29214 IX86_BUILTIN_SUBPD128_MASK,
29215 IX86_BUILTIN_SUBPD256_MASK,
29216 IX86_BUILTIN_SUBPS128_MASK,
29217 IX86_BUILTIN_SUBPS256_MASK,
29218 IX86_BUILTIN_XORPD256_MASK,
29219 IX86_BUILTIN_XORPD128_MASK,
29220 IX86_BUILTIN_XORPS256_MASK,
29221 IX86_BUILTIN_XORPS128_MASK,
29222 IX86_BUILTIN_ORPD256_MASK,
29223 IX86_BUILTIN_ORPD128_MASK,
29224 IX86_BUILTIN_ORPS256_MASK,
29225 IX86_BUILTIN_ORPS128_MASK,
29226 IX86_BUILTIN_BROADCASTF32x2_256,
29227 IX86_BUILTIN_BROADCASTI32x2_256,
29228 IX86_BUILTIN_BROADCASTI32x2_128,
29229 IX86_BUILTIN_BROADCASTF64X2_256,
29230 IX86_BUILTIN_BROADCASTI64X2_256,
29231 IX86_BUILTIN_BROADCASTF32X4_256,
29232 IX86_BUILTIN_BROADCASTI32X4_256,
29233 IX86_BUILTIN_EXTRACTF32X4_256,
29234 IX86_BUILTIN_EXTRACTI32X4_256,
29235 IX86_BUILTIN_DBPSADBW256,
29236 IX86_BUILTIN_DBPSADBW128,
29237 IX86_BUILTIN_CVTTPD2QQ256,
29238 IX86_BUILTIN_CVTTPD2QQ128,
29239 IX86_BUILTIN_CVTTPD2UQQ256,
29240 IX86_BUILTIN_CVTTPD2UQQ128,
29241 IX86_BUILTIN_CVTPD2QQ256,
29242 IX86_BUILTIN_CVTPD2QQ128,
29243 IX86_BUILTIN_CVTPD2UQQ256,
29244 IX86_BUILTIN_CVTPD2UQQ128,
29245 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29246 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29247 IX86_BUILTIN_CVTTPS2QQ256,
29248 IX86_BUILTIN_CVTTPS2QQ128,
29249 IX86_BUILTIN_CVTTPS2UQQ256,
29250 IX86_BUILTIN_CVTTPS2UQQ128,
29251 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29252 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29253 IX86_BUILTIN_CVTTPS2UDQ256,
29254 IX86_BUILTIN_CVTTPS2UDQ128,
29255 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29256 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29257 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29258 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29259 IX86_BUILTIN_CVTPD2DQ256_MASK,
29260 IX86_BUILTIN_CVTPD2DQ128_MASK,
29261 IX86_BUILTIN_CVTDQ2PD256_MASK,
29262 IX86_BUILTIN_CVTDQ2PD128_MASK,
29263 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29264 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29265 IX86_BUILTIN_CVTDQ2PS256_MASK,
29266 IX86_BUILTIN_CVTDQ2PS128_MASK,
29267 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29268 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29269 IX86_BUILTIN_CVTPS2PD256_MASK,
29270 IX86_BUILTIN_CVTPS2PD128_MASK,
29271 IX86_BUILTIN_PBROADCASTB256_MASK,
29272 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29273 IX86_BUILTIN_PBROADCASTB128_MASK,
29274 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29275 IX86_BUILTIN_PBROADCASTW256_MASK,
29276 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29277 IX86_BUILTIN_PBROADCASTW128_MASK,
29278 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29279 IX86_BUILTIN_PBROADCASTD256_MASK,
29280 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29281 IX86_BUILTIN_PBROADCASTD128_MASK,
29282 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29283 IX86_BUILTIN_PBROADCASTQ256_MASK,
29284 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29285 IX86_BUILTIN_PBROADCASTQ128_MASK,
29286 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29287 IX86_BUILTIN_BROADCASTSS256,
29288 IX86_BUILTIN_BROADCASTSS128,
29289 IX86_BUILTIN_BROADCASTSD256,
29290 IX86_BUILTIN_EXTRACTF64X2_256,
29291 IX86_BUILTIN_EXTRACTI64X2_256,
29292 IX86_BUILTIN_INSERTF32X4_256,
29293 IX86_BUILTIN_INSERTI32X4_256,
29294 IX86_BUILTIN_PMOVSXBW256_MASK,
29295 IX86_BUILTIN_PMOVSXBW128_MASK,
29296 IX86_BUILTIN_PMOVSXBD256_MASK,
29297 IX86_BUILTIN_PMOVSXBD128_MASK,
29298 IX86_BUILTIN_PMOVSXBQ256_MASK,
29299 IX86_BUILTIN_PMOVSXBQ128_MASK,
29300 IX86_BUILTIN_PMOVSXWD256_MASK,
29301 IX86_BUILTIN_PMOVSXWD128_MASK,
29302 IX86_BUILTIN_PMOVSXWQ256_MASK,
29303 IX86_BUILTIN_PMOVSXWQ128_MASK,
29304 IX86_BUILTIN_PMOVSXDQ256_MASK,
29305 IX86_BUILTIN_PMOVSXDQ128_MASK,
29306 IX86_BUILTIN_PMOVZXBW256_MASK,
29307 IX86_BUILTIN_PMOVZXBW128_MASK,
29308 IX86_BUILTIN_PMOVZXBD256_MASK,
29309 IX86_BUILTIN_PMOVZXBD128_MASK,
29310 IX86_BUILTIN_PMOVZXBQ256_MASK,
29311 IX86_BUILTIN_PMOVZXBQ128_MASK,
29312 IX86_BUILTIN_PMOVZXWD256_MASK,
29313 IX86_BUILTIN_PMOVZXWD128_MASK,
29314 IX86_BUILTIN_PMOVZXWQ256_MASK,
29315 IX86_BUILTIN_PMOVZXWQ128_MASK,
29316 IX86_BUILTIN_PMOVZXDQ256_MASK,
29317 IX86_BUILTIN_PMOVZXDQ128_MASK,
29318 IX86_BUILTIN_REDUCEPD256_MASK,
29319 IX86_BUILTIN_REDUCEPD128_MASK,
29320 IX86_BUILTIN_REDUCEPS256_MASK,
29321 IX86_BUILTIN_REDUCEPS128_MASK,
29322 IX86_BUILTIN_REDUCESD_MASK,
29323 IX86_BUILTIN_REDUCESS_MASK,
29324 IX86_BUILTIN_VPERMVARHI256_MASK,
29325 IX86_BUILTIN_VPERMVARHI128_MASK,
29326 IX86_BUILTIN_VPERMT2VARHI256,
29327 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29328 IX86_BUILTIN_VPERMT2VARHI128,
29329 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29330 IX86_BUILTIN_VPERMI2VARHI256,
29331 IX86_BUILTIN_VPERMI2VARHI128,
29332 IX86_BUILTIN_RCP14PD256,
29333 IX86_BUILTIN_RCP14PD128,
29334 IX86_BUILTIN_RCP14PS256,
29335 IX86_BUILTIN_RCP14PS128,
29336 IX86_BUILTIN_RSQRT14PD256_MASK,
29337 IX86_BUILTIN_RSQRT14PD128_MASK,
29338 IX86_BUILTIN_RSQRT14PS256_MASK,
29339 IX86_BUILTIN_RSQRT14PS128_MASK,
29340 IX86_BUILTIN_SQRTPD256_MASK,
29341 IX86_BUILTIN_SQRTPD128_MASK,
29342 IX86_BUILTIN_SQRTPS256_MASK,
29343 IX86_BUILTIN_SQRTPS128_MASK,
29344 IX86_BUILTIN_PADDB128_MASK,
29345 IX86_BUILTIN_PADDW128_MASK,
29346 IX86_BUILTIN_PADDD128_MASK,
29347 IX86_BUILTIN_PADDQ128_MASK,
29348 IX86_BUILTIN_PSUBB128_MASK,
29349 IX86_BUILTIN_PSUBW128_MASK,
29350 IX86_BUILTIN_PSUBD128_MASK,
29351 IX86_BUILTIN_PSUBQ128_MASK,
29352 IX86_BUILTIN_PADDSB128_MASK,
29353 IX86_BUILTIN_PADDSW128_MASK,
29354 IX86_BUILTIN_PSUBSB128_MASK,
29355 IX86_BUILTIN_PSUBSW128_MASK,
29356 IX86_BUILTIN_PADDUSB128_MASK,
29357 IX86_BUILTIN_PADDUSW128_MASK,
29358 IX86_BUILTIN_PSUBUSB128_MASK,
29359 IX86_BUILTIN_PSUBUSW128_MASK,
29360 IX86_BUILTIN_PADDB256_MASK,
29361 IX86_BUILTIN_PADDW256_MASK,
29362 IX86_BUILTIN_PADDD256_MASK,
29363 IX86_BUILTIN_PADDQ256_MASK,
29364 IX86_BUILTIN_PADDSB256_MASK,
29365 IX86_BUILTIN_PADDSW256_MASK,
29366 IX86_BUILTIN_PADDUSB256_MASK,
29367 IX86_BUILTIN_PADDUSW256_MASK,
29368 IX86_BUILTIN_PSUBB256_MASK,
29369 IX86_BUILTIN_PSUBW256_MASK,
29370 IX86_BUILTIN_PSUBD256_MASK,
29371 IX86_BUILTIN_PSUBQ256_MASK,
29372 IX86_BUILTIN_PSUBSB256_MASK,
29373 IX86_BUILTIN_PSUBSW256_MASK,
29374 IX86_BUILTIN_PSUBUSB256_MASK,
29375 IX86_BUILTIN_PSUBUSW256_MASK,
29376 IX86_BUILTIN_SHUF_F64x2_256,
29377 IX86_BUILTIN_SHUF_I64x2_256,
29378 IX86_BUILTIN_SHUF_I32x4_256,
29379 IX86_BUILTIN_SHUF_F32x4_256,
29380 IX86_BUILTIN_PMOVWB128,
29381 IX86_BUILTIN_PMOVWB256,
29382 IX86_BUILTIN_PMOVSWB128,
29383 IX86_BUILTIN_PMOVSWB256,
29384 IX86_BUILTIN_PMOVUSWB128,
29385 IX86_BUILTIN_PMOVUSWB256,
29386 IX86_BUILTIN_PMOVDB128,
29387 IX86_BUILTIN_PMOVDB256,
29388 IX86_BUILTIN_PMOVSDB128,
29389 IX86_BUILTIN_PMOVSDB256,
29390 IX86_BUILTIN_PMOVUSDB128,
29391 IX86_BUILTIN_PMOVUSDB256,
29392 IX86_BUILTIN_PMOVDW128,
29393 IX86_BUILTIN_PMOVDW256,
29394 IX86_BUILTIN_PMOVSDW128,
29395 IX86_BUILTIN_PMOVSDW256,
29396 IX86_BUILTIN_PMOVUSDW128,
29397 IX86_BUILTIN_PMOVUSDW256,
29398 IX86_BUILTIN_PMOVQB128,
29399 IX86_BUILTIN_PMOVQB256,
29400 IX86_BUILTIN_PMOVSQB128,
29401 IX86_BUILTIN_PMOVSQB256,
29402 IX86_BUILTIN_PMOVUSQB128,
29403 IX86_BUILTIN_PMOVUSQB256,
29404 IX86_BUILTIN_PMOVQW128,
29405 IX86_BUILTIN_PMOVQW256,
29406 IX86_BUILTIN_PMOVSQW128,
29407 IX86_BUILTIN_PMOVSQW256,
29408 IX86_BUILTIN_PMOVUSQW128,
29409 IX86_BUILTIN_PMOVUSQW256,
29410 IX86_BUILTIN_PMOVQD128,
29411 IX86_BUILTIN_PMOVQD256,
29412 IX86_BUILTIN_PMOVSQD128,
29413 IX86_BUILTIN_PMOVSQD256,
29414 IX86_BUILTIN_PMOVUSQD128,
29415 IX86_BUILTIN_PMOVUSQD256,
29416 IX86_BUILTIN_RANGEPD256,
29417 IX86_BUILTIN_RANGEPD128,
29418 IX86_BUILTIN_RANGEPS256,
29419 IX86_BUILTIN_RANGEPS128,
29420 IX86_BUILTIN_GETEXPPS256,
29421 IX86_BUILTIN_GETEXPPD256,
29422 IX86_BUILTIN_GETEXPPS128,
29423 IX86_BUILTIN_GETEXPPD128,
29424 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29425 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29426 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29427 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29428 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29429 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29430 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29431 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29432 IX86_BUILTIN_PABSQ256,
29433 IX86_BUILTIN_PABSQ128,
29434 IX86_BUILTIN_PABSD256_MASK,
29435 IX86_BUILTIN_PABSD128_MASK,
29436 IX86_BUILTIN_PMULHRSW256_MASK,
29437 IX86_BUILTIN_PMULHRSW128_MASK,
29438 IX86_BUILTIN_PMULHUW128_MASK,
29439 IX86_BUILTIN_PMULHUW256_MASK,
29440 IX86_BUILTIN_PMULHW256_MASK,
29441 IX86_BUILTIN_PMULHW128_MASK,
29442 IX86_BUILTIN_PMULLW256_MASK,
29443 IX86_BUILTIN_PMULLW128_MASK,
29444 IX86_BUILTIN_PMULLQ256,
29445 IX86_BUILTIN_PMULLQ128,
29446 IX86_BUILTIN_ANDPD256_MASK,
29447 IX86_BUILTIN_ANDPD128_MASK,
29448 IX86_BUILTIN_ANDPS256_MASK,
29449 IX86_BUILTIN_ANDPS128_MASK,
29450 IX86_BUILTIN_ANDNPD256_MASK,
29451 IX86_BUILTIN_ANDNPD128_MASK,
29452 IX86_BUILTIN_ANDNPS256_MASK,
29453 IX86_BUILTIN_ANDNPS128_MASK,
29454 IX86_BUILTIN_PSLLWI128_MASK,
29455 IX86_BUILTIN_PSLLDI128_MASK,
29456 IX86_BUILTIN_PSLLQI128_MASK,
29457 IX86_BUILTIN_PSLLW128_MASK,
29458 IX86_BUILTIN_PSLLD128_MASK,
29459 IX86_BUILTIN_PSLLQ128_MASK,
29460 IX86_BUILTIN_PSLLWI256_MASK ,
29461 IX86_BUILTIN_PSLLW256_MASK,
29462 IX86_BUILTIN_PSLLDI256_MASK,
29463 IX86_BUILTIN_PSLLD256_MASK,
29464 IX86_BUILTIN_PSLLQI256_MASK,
29465 IX86_BUILTIN_PSLLQ256_MASK,
29466 IX86_BUILTIN_PSRADI128_MASK,
29467 IX86_BUILTIN_PSRAD128_MASK,
29468 IX86_BUILTIN_PSRADI256_MASK,
29469 IX86_BUILTIN_PSRAD256_MASK,
29470 IX86_BUILTIN_PSRAQI128_MASK,
29471 IX86_BUILTIN_PSRAQ128_MASK,
29472 IX86_BUILTIN_PSRAQI256_MASK,
29473 IX86_BUILTIN_PSRAQ256_MASK,
29474 IX86_BUILTIN_PANDD256,
29475 IX86_BUILTIN_PANDD128,
29476 IX86_BUILTIN_PSRLDI128_MASK,
29477 IX86_BUILTIN_PSRLD128_MASK,
29478 IX86_BUILTIN_PSRLDI256_MASK,
29479 IX86_BUILTIN_PSRLD256_MASK,
29480 IX86_BUILTIN_PSRLQI128_MASK,
29481 IX86_BUILTIN_PSRLQ128_MASK,
29482 IX86_BUILTIN_PSRLQI256_MASK,
29483 IX86_BUILTIN_PSRLQ256_MASK,
29484 IX86_BUILTIN_PANDQ256,
29485 IX86_BUILTIN_PANDQ128,
29486 IX86_BUILTIN_PANDND256,
29487 IX86_BUILTIN_PANDND128,
29488 IX86_BUILTIN_PANDNQ256,
29489 IX86_BUILTIN_PANDNQ128,
29490 IX86_BUILTIN_PORD256,
29491 IX86_BUILTIN_PORD128,
29492 IX86_BUILTIN_PORQ256,
29493 IX86_BUILTIN_PORQ128,
29494 IX86_BUILTIN_PXORD256,
29495 IX86_BUILTIN_PXORD128,
29496 IX86_BUILTIN_PXORQ256,
29497 IX86_BUILTIN_PXORQ128,
29498 IX86_BUILTIN_PACKSSWB256_MASK,
29499 IX86_BUILTIN_PACKSSWB128_MASK,
29500 IX86_BUILTIN_PACKUSWB256_MASK,
29501 IX86_BUILTIN_PACKUSWB128_MASK,
29502 IX86_BUILTIN_RNDSCALEPS256,
29503 IX86_BUILTIN_RNDSCALEPD256,
29504 IX86_BUILTIN_RNDSCALEPS128,
29505 IX86_BUILTIN_RNDSCALEPD128,
29506 IX86_BUILTIN_VTERNLOGQ256_MASK,
29507 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29508 IX86_BUILTIN_VTERNLOGD256_MASK,
29509 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29510 IX86_BUILTIN_VTERNLOGQ128_MASK,
29511 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29512 IX86_BUILTIN_VTERNLOGD128_MASK,
29513 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29514 IX86_BUILTIN_SCALEFPD256,
29515 IX86_BUILTIN_SCALEFPS256,
29516 IX86_BUILTIN_SCALEFPD128,
29517 IX86_BUILTIN_SCALEFPS128,
29518 IX86_BUILTIN_VFMADDPD256_MASK,
29519 IX86_BUILTIN_VFMADDPD256_MASK3,
29520 IX86_BUILTIN_VFMADDPD256_MASKZ,
29521 IX86_BUILTIN_VFMADDPD128_MASK,
29522 IX86_BUILTIN_VFMADDPD128_MASK3,
29523 IX86_BUILTIN_VFMADDPD128_MASKZ,
29524 IX86_BUILTIN_VFMADDPS256_MASK,
29525 IX86_BUILTIN_VFMADDPS256_MASK3,
29526 IX86_BUILTIN_VFMADDPS256_MASKZ,
29527 IX86_BUILTIN_VFMADDPS128_MASK,
29528 IX86_BUILTIN_VFMADDPS128_MASK3,
29529 IX86_BUILTIN_VFMADDPS128_MASKZ,
29530 IX86_BUILTIN_VFMSUBPD256_MASK3,
29531 IX86_BUILTIN_VFMSUBPD128_MASK3,
29532 IX86_BUILTIN_VFMSUBPS256_MASK3,
29533 IX86_BUILTIN_VFMSUBPS128_MASK3,
29534 IX86_BUILTIN_VFNMADDPD256_MASK,
29535 IX86_BUILTIN_VFNMADDPD128_MASK,
29536 IX86_BUILTIN_VFNMADDPS256_MASK,
29537 IX86_BUILTIN_VFNMADDPS128_MASK,
29538 IX86_BUILTIN_VFNMSUBPD256_MASK,
29539 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29540 IX86_BUILTIN_VFNMSUBPD128_MASK,
29541 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29542 IX86_BUILTIN_VFNMSUBPS256_MASK,
29543 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29544 IX86_BUILTIN_VFNMSUBPS128_MASK,
29545 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29546 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29547 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29548 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29549 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29550 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29551 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29552 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29553 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29554 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29555 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29556 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29557 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29558 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29559 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29560 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29561 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29562 IX86_BUILTIN_INSERTF64X2_256,
29563 IX86_BUILTIN_INSERTI64X2_256,
29564 IX86_BUILTIN_PSRAVV16HI,
29565 IX86_BUILTIN_PSRAVV8HI,
29566 IX86_BUILTIN_PMADDUBSW256_MASK,
29567 IX86_BUILTIN_PMADDUBSW128_MASK,
29568 IX86_BUILTIN_PMADDWD256_MASK,
29569 IX86_BUILTIN_PMADDWD128_MASK,
29570 IX86_BUILTIN_PSRLVV16HI,
29571 IX86_BUILTIN_PSRLVV8HI,
29572 IX86_BUILTIN_CVTPS2DQ256_MASK,
29573 IX86_BUILTIN_CVTPS2DQ128_MASK,
29574 IX86_BUILTIN_CVTPS2UDQ256,
29575 IX86_BUILTIN_CVTPS2UDQ128,
29576 IX86_BUILTIN_CVTPS2QQ256,
29577 IX86_BUILTIN_CVTPS2QQ128,
29578 IX86_BUILTIN_CVTPS2UQQ256,
29579 IX86_BUILTIN_CVTPS2UQQ128,
29580 IX86_BUILTIN_GETMANTPS256,
29581 IX86_BUILTIN_GETMANTPS128,
29582 IX86_BUILTIN_GETMANTPD256,
29583 IX86_BUILTIN_GETMANTPD128,
29584 IX86_BUILTIN_MOVDDUP256_MASK,
29585 IX86_BUILTIN_MOVDDUP128_MASK,
29586 IX86_BUILTIN_MOVSHDUP256_MASK,
29587 IX86_BUILTIN_MOVSHDUP128_MASK,
29588 IX86_BUILTIN_MOVSLDUP256_MASK,
29589 IX86_BUILTIN_MOVSLDUP128_MASK,
29590 IX86_BUILTIN_CVTQQ2PS256,
29591 IX86_BUILTIN_CVTQQ2PS128,
29592 IX86_BUILTIN_CVTUQQ2PS256,
29593 IX86_BUILTIN_CVTUQQ2PS128,
29594 IX86_BUILTIN_CVTQQ2PD256,
29595 IX86_BUILTIN_CVTQQ2PD128,
29596 IX86_BUILTIN_CVTUQQ2PD256,
29597 IX86_BUILTIN_CVTUQQ2PD128,
29598 IX86_BUILTIN_VPERMT2VARQ256,
29599 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29600 IX86_BUILTIN_VPERMT2VARD256,
29601 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29602 IX86_BUILTIN_VPERMI2VARQ256,
29603 IX86_BUILTIN_VPERMI2VARD256,
29604 IX86_BUILTIN_VPERMT2VARPD256,
29605 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29606 IX86_BUILTIN_VPERMT2VARPS256,
29607 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29608 IX86_BUILTIN_VPERMI2VARPD256,
29609 IX86_BUILTIN_VPERMI2VARPS256,
29610 IX86_BUILTIN_VPERMT2VARQ128,
29611 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29612 IX86_BUILTIN_VPERMT2VARD128,
29613 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29614 IX86_BUILTIN_VPERMI2VARQ128,
29615 IX86_BUILTIN_VPERMI2VARD128,
29616 IX86_BUILTIN_VPERMT2VARPD128,
29617 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29618 IX86_BUILTIN_VPERMT2VARPS128,
29619 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29620 IX86_BUILTIN_VPERMI2VARPD128,
29621 IX86_BUILTIN_VPERMI2VARPS128,
29622 IX86_BUILTIN_PSHUFB256_MASK,
29623 IX86_BUILTIN_PSHUFB128_MASK,
29624 IX86_BUILTIN_PSHUFHW256_MASK,
29625 IX86_BUILTIN_PSHUFHW128_MASK,
29626 IX86_BUILTIN_PSHUFLW256_MASK,
29627 IX86_BUILTIN_PSHUFLW128_MASK,
29628 IX86_BUILTIN_PSHUFD256_MASK,
29629 IX86_BUILTIN_PSHUFD128_MASK,
29630 IX86_BUILTIN_SHUFPD256_MASK,
29631 IX86_BUILTIN_SHUFPD128_MASK,
29632 IX86_BUILTIN_SHUFPS256_MASK,
29633 IX86_BUILTIN_SHUFPS128_MASK,
29634 IX86_BUILTIN_PROLVQ256,
29635 IX86_BUILTIN_PROLVQ128,
29636 IX86_BUILTIN_PROLQ256,
29637 IX86_BUILTIN_PROLQ128,
29638 IX86_BUILTIN_PRORVQ256,
29639 IX86_BUILTIN_PRORVQ128,
29640 IX86_BUILTIN_PRORQ256,
29641 IX86_BUILTIN_PRORQ128,
29642 IX86_BUILTIN_PSRAVQ128,
29643 IX86_BUILTIN_PSRAVQ256,
29644 IX86_BUILTIN_PSLLVV4DI_MASK,
29645 IX86_BUILTIN_PSLLVV2DI_MASK,
29646 IX86_BUILTIN_PSLLVV8SI_MASK,
29647 IX86_BUILTIN_PSLLVV4SI_MASK,
29648 IX86_BUILTIN_PSRAVV8SI_MASK,
29649 IX86_BUILTIN_PSRAVV4SI_MASK,
29650 IX86_BUILTIN_PSRLVV4DI_MASK,
29651 IX86_BUILTIN_PSRLVV2DI_MASK,
29652 IX86_BUILTIN_PSRLVV8SI_MASK,
29653 IX86_BUILTIN_PSRLVV4SI_MASK,
29654 IX86_BUILTIN_PSRAWI256_MASK,
29655 IX86_BUILTIN_PSRAW256_MASK,
29656 IX86_BUILTIN_PSRAWI128_MASK,
29657 IX86_BUILTIN_PSRAW128_MASK,
29658 IX86_BUILTIN_PSRLWI256_MASK,
29659 IX86_BUILTIN_PSRLW256_MASK,
29660 IX86_BUILTIN_PSRLWI128_MASK,
29661 IX86_BUILTIN_PSRLW128_MASK,
29662 IX86_BUILTIN_PRORVD256,
29663 IX86_BUILTIN_PROLVD256,
29664 IX86_BUILTIN_PRORD256,
29665 IX86_BUILTIN_PROLD256,
29666 IX86_BUILTIN_PRORVD128,
29667 IX86_BUILTIN_PROLVD128,
29668 IX86_BUILTIN_PRORD128,
29669 IX86_BUILTIN_PROLD128,
29670 IX86_BUILTIN_FPCLASSPD256,
29671 IX86_BUILTIN_FPCLASSPD128,
29672 IX86_BUILTIN_FPCLASSSD,
29673 IX86_BUILTIN_FPCLASSPS256,
29674 IX86_BUILTIN_FPCLASSPS128,
29675 IX86_BUILTIN_FPCLASSSS,
29676 IX86_BUILTIN_CVTB2MASK128,
29677 IX86_BUILTIN_CVTB2MASK256,
29678 IX86_BUILTIN_CVTW2MASK128,
29679 IX86_BUILTIN_CVTW2MASK256,
29680 IX86_BUILTIN_CVTD2MASK128,
29681 IX86_BUILTIN_CVTD2MASK256,
29682 IX86_BUILTIN_CVTQ2MASK128,
29683 IX86_BUILTIN_CVTQ2MASK256,
29684 IX86_BUILTIN_CVTMASK2B128,
29685 IX86_BUILTIN_CVTMASK2B256,
29686 IX86_BUILTIN_CVTMASK2W128,
29687 IX86_BUILTIN_CVTMASK2W256,
29688 IX86_BUILTIN_CVTMASK2D128,
29689 IX86_BUILTIN_CVTMASK2D256,
29690 IX86_BUILTIN_CVTMASK2Q128,
29691 IX86_BUILTIN_CVTMASK2Q256,
29692 IX86_BUILTIN_PCMPEQB128_MASK,
29693 IX86_BUILTIN_PCMPEQB256_MASK,
29694 IX86_BUILTIN_PCMPEQW128_MASK,
29695 IX86_BUILTIN_PCMPEQW256_MASK,
29696 IX86_BUILTIN_PCMPEQD128_MASK,
29697 IX86_BUILTIN_PCMPEQD256_MASK,
29698 IX86_BUILTIN_PCMPEQQ128_MASK,
29699 IX86_BUILTIN_PCMPEQQ256_MASK,
29700 IX86_BUILTIN_PCMPGTB128_MASK,
29701 IX86_BUILTIN_PCMPGTB256_MASK,
29702 IX86_BUILTIN_PCMPGTW128_MASK,
29703 IX86_BUILTIN_PCMPGTW256_MASK,
29704 IX86_BUILTIN_PCMPGTD128_MASK,
29705 IX86_BUILTIN_PCMPGTD256_MASK,
29706 IX86_BUILTIN_PCMPGTQ128_MASK,
29707 IX86_BUILTIN_PCMPGTQ256_MASK,
29708 IX86_BUILTIN_PTESTMB128,
29709 IX86_BUILTIN_PTESTMB256,
29710 IX86_BUILTIN_PTESTMW128,
29711 IX86_BUILTIN_PTESTMW256,
29712 IX86_BUILTIN_PTESTMD128,
29713 IX86_BUILTIN_PTESTMD256,
29714 IX86_BUILTIN_PTESTMQ128,
29715 IX86_BUILTIN_PTESTMQ256,
29716 IX86_BUILTIN_PTESTNMB128,
29717 IX86_BUILTIN_PTESTNMB256,
29718 IX86_BUILTIN_PTESTNMW128,
29719 IX86_BUILTIN_PTESTNMW256,
29720 IX86_BUILTIN_PTESTNMD128,
29721 IX86_BUILTIN_PTESTNMD256,
29722 IX86_BUILTIN_PTESTNMQ128,
29723 IX86_BUILTIN_PTESTNMQ256,
29724 IX86_BUILTIN_PBROADCASTMB128,
29725 IX86_BUILTIN_PBROADCASTMB256,
29726 IX86_BUILTIN_PBROADCASTMW128,
29727 IX86_BUILTIN_PBROADCASTMW256,
29728 IX86_BUILTIN_COMPRESSPD256,
29729 IX86_BUILTIN_COMPRESSPD128,
29730 IX86_BUILTIN_COMPRESSPS256,
29731 IX86_BUILTIN_COMPRESSPS128,
29732 IX86_BUILTIN_PCOMPRESSQ256,
29733 IX86_BUILTIN_PCOMPRESSQ128,
29734 IX86_BUILTIN_PCOMPRESSD256,
29735 IX86_BUILTIN_PCOMPRESSD128,
29736 IX86_BUILTIN_EXPANDPD256,
29737 IX86_BUILTIN_EXPANDPD128,
29738 IX86_BUILTIN_EXPANDPS256,
29739 IX86_BUILTIN_EXPANDPS128,
29740 IX86_BUILTIN_PEXPANDQ256,
29741 IX86_BUILTIN_PEXPANDQ128,
29742 IX86_BUILTIN_PEXPANDD256,
29743 IX86_BUILTIN_PEXPANDD128,
29744 IX86_BUILTIN_EXPANDPD256Z,
29745 IX86_BUILTIN_EXPANDPD128Z,
29746 IX86_BUILTIN_EXPANDPS256Z,
29747 IX86_BUILTIN_EXPANDPS128Z,
29748 IX86_BUILTIN_PEXPANDQ256Z,
29749 IX86_BUILTIN_PEXPANDQ128Z,
29750 IX86_BUILTIN_PEXPANDD256Z,
29751 IX86_BUILTIN_PEXPANDD128Z,
29752 IX86_BUILTIN_PMAXSD256_MASK,
29753 IX86_BUILTIN_PMINSD256_MASK,
29754 IX86_BUILTIN_PMAXUD256_MASK,
29755 IX86_BUILTIN_PMINUD256_MASK,
29756 IX86_BUILTIN_PMAXSD128_MASK,
29757 IX86_BUILTIN_PMINSD128_MASK,
29758 IX86_BUILTIN_PMAXUD128_MASK,
29759 IX86_BUILTIN_PMINUD128_MASK,
29760 IX86_BUILTIN_PMAXSQ256_MASK,
29761 IX86_BUILTIN_PMINSQ256_MASK,
29762 IX86_BUILTIN_PMAXUQ256_MASK,
29763 IX86_BUILTIN_PMINUQ256_MASK,
29764 IX86_BUILTIN_PMAXSQ128_MASK,
29765 IX86_BUILTIN_PMINSQ128_MASK,
29766 IX86_BUILTIN_PMAXUQ128_MASK,
29767 IX86_BUILTIN_PMINUQ128_MASK,
29768 IX86_BUILTIN_PMINSB256_MASK,
29769 IX86_BUILTIN_PMINUB256_MASK,
29770 IX86_BUILTIN_PMAXSB256_MASK,
29771 IX86_BUILTIN_PMAXUB256_MASK,
29772 IX86_BUILTIN_PMINSB128_MASK,
29773 IX86_BUILTIN_PMINUB128_MASK,
29774 IX86_BUILTIN_PMAXSB128_MASK,
29775 IX86_BUILTIN_PMAXUB128_MASK,
29776 IX86_BUILTIN_PMINSW256_MASK,
29777 IX86_BUILTIN_PMINUW256_MASK,
29778 IX86_BUILTIN_PMAXSW256_MASK,
29779 IX86_BUILTIN_PMAXUW256_MASK,
29780 IX86_BUILTIN_PMINSW128_MASK,
29781 IX86_BUILTIN_PMINUW128_MASK,
29782 IX86_BUILTIN_PMAXSW128_MASK,
29783 IX86_BUILTIN_PMAXUW128_MASK,
29784 IX86_BUILTIN_VPCONFLICTQ256,
29785 IX86_BUILTIN_VPCONFLICTD256,
29786 IX86_BUILTIN_VPCLZCNTQ256,
29787 IX86_BUILTIN_VPCLZCNTD256,
29788 IX86_BUILTIN_UNPCKHPD256_MASK,
29789 IX86_BUILTIN_UNPCKHPD128_MASK,
29790 IX86_BUILTIN_UNPCKHPS256_MASK,
29791 IX86_BUILTIN_UNPCKHPS128_MASK,
29792 IX86_BUILTIN_UNPCKLPD256_MASK,
29793 IX86_BUILTIN_UNPCKLPD128_MASK,
29794 IX86_BUILTIN_UNPCKLPS256_MASK,
29795 IX86_BUILTIN_VPCONFLICTQ128,
29796 IX86_BUILTIN_VPCONFLICTD128,
29797 IX86_BUILTIN_VPCLZCNTQ128,
29798 IX86_BUILTIN_VPCLZCNTD128,
29799 IX86_BUILTIN_UNPCKLPS128_MASK,
29800 IX86_BUILTIN_ALIGND256,
29801 IX86_BUILTIN_ALIGNQ256,
29802 IX86_BUILTIN_ALIGND128,
29803 IX86_BUILTIN_ALIGNQ128,
29804 IX86_BUILTIN_CVTPS2PH256_MASK,
29805 IX86_BUILTIN_CVTPS2PH_MASK,
29806 IX86_BUILTIN_CVTPH2PS_MASK,
29807 IX86_BUILTIN_CVTPH2PS256_MASK,
29808 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29809 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29810 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29811 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29812 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29813 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29814 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29815 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29816 IX86_BUILTIN_PUNPCKHBW128_MASK,
29817 IX86_BUILTIN_PUNPCKHBW256_MASK,
29818 IX86_BUILTIN_PUNPCKHWD128_MASK,
29819 IX86_BUILTIN_PUNPCKHWD256_MASK,
29820 IX86_BUILTIN_PUNPCKLBW128_MASK,
29821 IX86_BUILTIN_PUNPCKLBW256_MASK,
29822 IX86_BUILTIN_PUNPCKLWD128_MASK,
29823 IX86_BUILTIN_PUNPCKLWD256_MASK,
29824 IX86_BUILTIN_PSLLVV16HI,
29825 IX86_BUILTIN_PSLLVV8HI,
29826 IX86_BUILTIN_PACKSSDW256_MASK,
29827 IX86_BUILTIN_PACKSSDW128_MASK,
29828 IX86_BUILTIN_PACKUSDW256_MASK,
29829 IX86_BUILTIN_PACKUSDW128_MASK,
29830 IX86_BUILTIN_PAVGB256_MASK,
29831 IX86_BUILTIN_PAVGW256_MASK,
29832 IX86_BUILTIN_PAVGB128_MASK,
29833 IX86_BUILTIN_PAVGW128_MASK,
29834 IX86_BUILTIN_VPERMVARSF256_MASK,
29835 IX86_BUILTIN_VPERMVARDF256_MASK,
29836 IX86_BUILTIN_VPERMDF256_MASK,
29837 IX86_BUILTIN_PABSB256_MASK,
29838 IX86_BUILTIN_PABSB128_MASK,
29839 IX86_BUILTIN_PABSW256_MASK,
29840 IX86_BUILTIN_PABSW128_MASK,
29841 IX86_BUILTIN_VPERMILVARPD_MASK,
29842 IX86_BUILTIN_VPERMILVARPS_MASK,
29843 IX86_BUILTIN_VPERMILVARPD256_MASK,
29844 IX86_BUILTIN_VPERMILVARPS256_MASK,
29845 IX86_BUILTIN_VPERMILPD_MASK,
29846 IX86_BUILTIN_VPERMILPS_MASK,
29847 IX86_BUILTIN_VPERMILPD256_MASK,
29848 IX86_BUILTIN_VPERMILPS256_MASK,
29849 IX86_BUILTIN_BLENDMQ256,
29850 IX86_BUILTIN_BLENDMD256,
29851 IX86_BUILTIN_BLENDMPD256,
29852 IX86_BUILTIN_BLENDMPS256,
29853 IX86_BUILTIN_BLENDMQ128,
29854 IX86_BUILTIN_BLENDMD128,
29855 IX86_BUILTIN_BLENDMPD128,
29856 IX86_BUILTIN_BLENDMPS128,
29857 IX86_BUILTIN_BLENDMW256,
29858 IX86_BUILTIN_BLENDMB256,
29859 IX86_BUILTIN_BLENDMW128,
29860 IX86_BUILTIN_BLENDMB128,
29861 IX86_BUILTIN_PMULLD256_MASK,
29862 IX86_BUILTIN_PMULLD128_MASK,
29863 IX86_BUILTIN_PMULUDQ256_MASK,
29864 IX86_BUILTIN_PMULDQ256_MASK,
29865 IX86_BUILTIN_PMULDQ128_MASK,
29866 IX86_BUILTIN_PMULUDQ128_MASK,
29867 IX86_BUILTIN_CVTPD2PS256_MASK,
29868 IX86_BUILTIN_CVTPD2PS_MASK,
29869 IX86_BUILTIN_VPERMVARSI256_MASK,
29870 IX86_BUILTIN_VPERMVARDI256_MASK,
29871 IX86_BUILTIN_VPERMDI256_MASK,
29872 IX86_BUILTIN_CMPQ256,
29873 IX86_BUILTIN_CMPD256,
29874 IX86_BUILTIN_UCMPQ256,
29875 IX86_BUILTIN_UCMPD256,
29876 IX86_BUILTIN_CMPB256,
29877 IX86_BUILTIN_CMPW256,
29878 IX86_BUILTIN_UCMPB256,
29879 IX86_BUILTIN_UCMPW256,
29880 IX86_BUILTIN_CMPPD256_MASK,
29881 IX86_BUILTIN_CMPPS256_MASK,
29882 IX86_BUILTIN_CMPQ128,
29883 IX86_BUILTIN_CMPD128,
29884 IX86_BUILTIN_UCMPQ128,
29885 IX86_BUILTIN_UCMPD128,
29886 IX86_BUILTIN_CMPB128,
29887 IX86_BUILTIN_CMPW128,
29888 IX86_BUILTIN_UCMPB128,
29889 IX86_BUILTIN_UCMPW128,
29890 IX86_BUILTIN_CMPPD128_MASK,
29891 IX86_BUILTIN_CMPPS128_MASK,
29893 IX86_BUILTIN_GATHER3SIV8SF,
29894 IX86_BUILTIN_GATHER3SIV4SF,
29895 IX86_BUILTIN_GATHER3SIV4DF,
29896 IX86_BUILTIN_GATHER3SIV2DF,
29897 IX86_BUILTIN_GATHER3DIV8SF,
29898 IX86_BUILTIN_GATHER3DIV4SF,
29899 IX86_BUILTIN_GATHER3DIV4DF,
29900 IX86_BUILTIN_GATHER3DIV2DF,
29901 IX86_BUILTIN_GATHER3SIV8SI,
29902 IX86_BUILTIN_GATHER3SIV4SI,
29903 IX86_BUILTIN_GATHER3SIV4DI,
29904 IX86_BUILTIN_GATHER3SIV2DI,
29905 IX86_BUILTIN_GATHER3DIV8SI,
29906 IX86_BUILTIN_GATHER3DIV4SI,
29907 IX86_BUILTIN_GATHER3DIV4DI,
29908 IX86_BUILTIN_GATHER3DIV2DI,
29909 IX86_BUILTIN_SCATTERSIV8SF,
29910 IX86_BUILTIN_SCATTERSIV4SF,
29911 IX86_BUILTIN_SCATTERSIV4DF,
29912 IX86_BUILTIN_SCATTERSIV2DF,
29913 IX86_BUILTIN_SCATTERDIV8SF,
29914 IX86_BUILTIN_SCATTERDIV4SF,
29915 IX86_BUILTIN_SCATTERDIV4DF,
29916 IX86_BUILTIN_SCATTERDIV2DF,
29917 IX86_BUILTIN_SCATTERSIV8SI,
29918 IX86_BUILTIN_SCATTERSIV4SI,
29919 IX86_BUILTIN_SCATTERSIV4DI,
29920 IX86_BUILTIN_SCATTERSIV2DI,
29921 IX86_BUILTIN_SCATTERDIV8SI,
29922 IX86_BUILTIN_SCATTERDIV4SI,
29923 IX86_BUILTIN_SCATTERDIV4DI,
29924 IX86_BUILTIN_SCATTERDIV2DI,
29926 /* AVX512DQ. */
29927 IX86_BUILTIN_RANGESD128,
29928 IX86_BUILTIN_RANGESS128,
29929 IX86_BUILTIN_KUNPCKWD,
29930 IX86_BUILTIN_KUNPCKDQ,
29931 IX86_BUILTIN_BROADCASTF32x2_512,
29932 IX86_BUILTIN_BROADCASTI32x2_512,
29933 IX86_BUILTIN_BROADCASTF64X2_512,
29934 IX86_BUILTIN_BROADCASTI64X2_512,
29935 IX86_BUILTIN_BROADCASTF32X8_512,
29936 IX86_BUILTIN_BROADCASTI32X8_512,
29937 IX86_BUILTIN_EXTRACTF64X2_512,
29938 IX86_BUILTIN_EXTRACTF32X8,
29939 IX86_BUILTIN_EXTRACTI64X2_512,
29940 IX86_BUILTIN_EXTRACTI32X8,
29941 IX86_BUILTIN_REDUCEPD512_MASK,
29942 IX86_BUILTIN_REDUCEPS512_MASK,
29943 IX86_BUILTIN_PMULLQ512,
29944 IX86_BUILTIN_XORPD512,
29945 IX86_BUILTIN_XORPS512,
29946 IX86_BUILTIN_ORPD512,
29947 IX86_BUILTIN_ORPS512,
29948 IX86_BUILTIN_ANDPD512,
29949 IX86_BUILTIN_ANDPS512,
29950 IX86_BUILTIN_ANDNPD512,
29951 IX86_BUILTIN_ANDNPS512,
29952 IX86_BUILTIN_INSERTF32X8,
29953 IX86_BUILTIN_INSERTI32X8,
29954 IX86_BUILTIN_INSERTF64X2_512,
29955 IX86_BUILTIN_INSERTI64X2_512,
29956 IX86_BUILTIN_FPCLASSPD512,
29957 IX86_BUILTIN_FPCLASSPS512,
29958 IX86_BUILTIN_CVTD2MASK512,
29959 IX86_BUILTIN_CVTQ2MASK512,
29960 IX86_BUILTIN_CVTMASK2D512,
29961 IX86_BUILTIN_CVTMASK2Q512,
29962 IX86_BUILTIN_CVTPD2QQ512,
29963 IX86_BUILTIN_CVTPS2QQ512,
29964 IX86_BUILTIN_CVTPD2UQQ512,
29965 IX86_BUILTIN_CVTPS2UQQ512,
29966 IX86_BUILTIN_CVTQQ2PS512,
29967 IX86_BUILTIN_CVTUQQ2PS512,
29968 IX86_BUILTIN_CVTQQ2PD512,
29969 IX86_BUILTIN_CVTUQQ2PD512,
29970 IX86_BUILTIN_CVTTPS2QQ512,
29971 IX86_BUILTIN_CVTTPS2UQQ512,
29972 IX86_BUILTIN_CVTTPD2QQ512,
29973 IX86_BUILTIN_CVTTPD2UQQ512,
29974 IX86_BUILTIN_RANGEPS512,
29975 IX86_BUILTIN_RANGEPD512,
29977 /* AVX512BW. */
29978 IX86_BUILTIN_PACKUSDW512,
29979 IX86_BUILTIN_PACKSSDW512,
29980 IX86_BUILTIN_LOADDQUHI512_MASK,
29981 IX86_BUILTIN_LOADDQUQI512_MASK,
29982 IX86_BUILTIN_PSLLDQ512,
29983 IX86_BUILTIN_PSRLDQ512,
29984 IX86_BUILTIN_STOREDQUHI512_MASK,
29985 IX86_BUILTIN_STOREDQUQI512_MASK,
29986 IX86_BUILTIN_PALIGNR512,
29987 IX86_BUILTIN_PALIGNR512_MASK,
29988 IX86_BUILTIN_MOVDQUHI512_MASK,
29989 IX86_BUILTIN_MOVDQUQI512_MASK,
29990 IX86_BUILTIN_PSADBW512,
29991 IX86_BUILTIN_DBPSADBW512,
29992 IX86_BUILTIN_PBROADCASTB512,
29993 IX86_BUILTIN_PBROADCASTB512_GPR,
29994 IX86_BUILTIN_PBROADCASTW512,
29995 IX86_BUILTIN_PBROADCASTW512_GPR,
29996 IX86_BUILTIN_PMOVSXBW512_MASK,
29997 IX86_BUILTIN_PMOVZXBW512_MASK,
29998 IX86_BUILTIN_VPERMVARHI512_MASK,
29999 IX86_BUILTIN_VPERMT2VARHI512,
30000 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30001 IX86_BUILTIN_VPERMI2VARHI512,
30002 IX86_BUILTIN_PAVGB512,
30003 IX86_BUILTIN_PAVGW512,
30004 IX86_BUILTIN_PADDB512,
30005 IX86_BUILTIN_PSUBB512,
30006 IX86_BUILTIN_PSUBSB512,
30007 IX86_BUILTIN_PADDSB512,
30008 IX86_BUILTIN_PSUBUSB512,
30009 IX86_BUILTIN_PADDUSB512,
30010 IX86_BUILTIN_PSUBW512,
30011 IX86_BUILTIN_PADDW512,
30012 IX86_BUILTIN_PSUBSW512,
30013 IX86_BUILTIN_PADDSW512,
30014 IX86_BUILTIN_PSUBUSW512,
30015 IX86_BUILTIN_PADDUSW512,
30016 IX86_BUILTIN_PMAXUW512,
30017 IX86_BUILTIN_PMAXSW512,
30018 IX86_BUILTIN_PMINUW512,
30019 IX86_BUILTIN_PMINSW512,
30020 IX86_BUILTIN_PMAXUB512,
30021 IX86_BUILTIN_PMAXSB512,
30022 IX86_BUILTIN_PMINUB512,
30023 IX86_BUILTIN_PMINSB512,
30024 IX86_BUILTIN_PMOVWB512,
30025 IX86_BUILTIN_PMOVSWB512,
30026 IX86_BUILTIN_PMOVUSWB512,
30027 IX86_BUILTIN_PMULHRSW512_MASK,
30028 IX86_BUILTIN_PMULHUW512_MASK,
30029 IX86_BUILTIN_PMULHW512_MASK,
30030 IX86_BUILTIN_PMULLW512_MASK,
30031 IX86_BUILTIN_PSLLWI512_MASK,
30032 IX86_BUILTIN_PSLLW512_MASK,
30033 IX86_BUILTIN_PACKSSWB512,
30034 IX86_BUILTIN_PACKUSWB512,
30035 IX86_BUILTIN_PSRAVV32HI,
30036 IX86_BUILTIN_PMADDUBSW512_MASK,
30037 IX86_BUILTIN_PMADDWD512_MASK,
30038 IX86_BUILTIN_PSRLVV32HI,
30039 IX86_BUILTIN_PUNPCKHBW512,
30040 IX86_BUILTIN_PUNPCKHWD512,
30041 IX86_BUILTIN_PUNPCKLBW512,
30042 IX86_BUILTIN_PUNPCKLWD512,
30043 IX86_BUILTIN_PSHUFB512,
30044 IX86_BUILTIN_PSHUFHW512,
30045 IX86_BUILTIN_PSHUFLW512,
30046 IX86_BUILTIN_PSRAWI512,
30047 IX86_BUILTIN_PSRAW512,
30048 IX86_BUILTIN_PSRLWI512,
30049 IX86_BUILTIN_PSRLW512,
30050 IX86_BUILTIN_CVTB2MASK512,
30051 IX86_BUILTIN_CVTW2MASK512,
30052 IX86_BUILTIN_CVTMASK2B512,
30053 IX86_BUILTIN_CVTMASK2W512,
30054 IX86_BUILTIN_PCMPEQB512_MASK,
30055 IX86_BUILTIN_PCMPEQW512_MASK,
30056 IX86_BUILTIN_PCMPGTB512_MASK,
30057 IX86_BUILTIN_PCMPGTW512_MASK,
30058 IX86_BUILTIN_PTESTMB512,
30059 IX86_BUILTIN_PTESTMW512,
30060 IX86_BUILTIN_PTESTNMB512,
30061 IX86_BUILTIN_PTESTNMW512,
30062 IX86_BUILTIN_PSLLVV32HI,
30063 IX86_BUILTIN_PABSB512,
30064 IX86_BUILTIN_PABSW512,
30065 IX86_BUILTIN_BLENDMW512,
30066 IX86_BUILTIN_BLENDMB512,
30067 IX86_BUILTIN_CMPB512,
30068 IX86_BUILTIN_CMPW512,
30069 IX86_BUILTIN_UCMPB512,
30070 IX86_BUILTIN_UCMPW512,
30072 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30073 where all operands are 32-byte or 64-byte wide respectively. */
30074 IX86_BUILTIN_GATHERALTSIV4DF,
30075 IX86_BUILTIN_GATHERALTDIV8SF,
30076 IX86_BUILTIN_GATHERALTSIV4DI,
30077 IX86_BUILTIN_GATHERALTDIV8SI,
30078 IX86_BUILTIN_GATHER3ALTDIV16SF,
30079 IX86_BUILTIN_GATHER3ALTDIV16SI,
30080 IX86_BUILTIN_GATHER3ALTSIV4DF,
30081 IX86_BUILTIN_GATHER3ALTDIV8SF,
30082 IX86_BUILTIN_GATHER3ALTSIV4DI,
30083 IX86_BUILTIN_GATHER3ALTDIV8SI,
30084 IX86_BUILTIN_GATHER3ALTSIV8DF,
30085 IX86_BUILTIN_GATHER3ALTSIV8DI,
30086 IX86_BUILTIN_GATHER3DIV16SF,
30087 IX86_BUILTIN_GATHER3DIV16SI,
30088 IX86_BUILTIN_GATHER3DIV8DF,
30089 IX86_BUILTIN_GATHER3DIV8DI,
30090 IX86_BUILTIN_GATHER3SIV16SF,
30091 IX86_BUILTIN_GATHER3SIV16SI,
30092 IX86_BUILTIN_GATHER3SIV8DF,
30093 IX86_BUILTIN_GATHER3SIV8DI,
30094 IX86_BUILTIN_SCATTERDIV16SF,
30095 IX86_BUILTIN_SCATTERDIV16SI,
30096 IX86_BUILTIN_SCATTERDIV8DF,
30097 IX86_BUILTIN_SCATTERDIV8DI,
30098 IX86_BUILTIN_SCATTERSIV16SF,
30099 IX86_BUILTIN_SCATTERSIV16SI,
30100 IX86_BUILTIN_SCATTERSIV8DF,
30101 IX86_BUILTIN_SCATTERSIV8DI,
30103 /* AVX512PF */
30104 IX86_BUILTIN_GATHERPFQPD,
30105 IX86_BUILTIN_GATHERPFDPS,
30106 IX86_BUILTIN_GATHERPFDPD,
30107 IX86_BUILTIN_GATHERPFQPS,
30108 IX86_BUILTIN_SCATTERPFDPD,
30109 IX86_BUILTIN_SCATTERPFDPS,
30110 IX86_BUILTIN_SCATTERPFQPD,
30111 IX86_BUILTIN_SCATTERPFQPS,
30113 /* AVX-512ER */
30114 IX86_BUILTIN_EXP2PD_MASK,
30115 IX86_BUILTIN_EXP2PS_MASK,
30116 IX86_BUILTIN_EXP2PS,
30117 IX86_BUILTIN_RCP28PD,
30118 IX86_BUILTIN_RCP28PS,
30119 IX86_BUILTIN_RCP28SD,
30120 IX86_BUILTIN_RCP28SS,
30121 IX86_BUILTIN_RSQRT28PD,
30122 IX86_BUILTIN_RSQRT28PS,
30123 IX86_BUILTIN_RSQRT28SD,
30124 IX86_BUILTIN_RSQRT28SS,
30126 /* AVX-512IFMA */
30127 IX86_BUILTIN_VPMADD52LUQ512,
30128 IX86_BUILTIN_VPMADD52HUQ512,
30129 IX86_BUILTIN_VPMADD52LUQ256,
30130 IX86_BUILTIN_VPMADD52HUQ256,
30131 IX86_BUILTIN_VPMADD52LUQ128,
30132 IX86_BUILTIN_VPMADD52HUQ128,
30133 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30134 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30135 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30136 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30137 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30138 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30140 /* AVX-512VBMI */
30141 IX86_BUILTIN_VPMULTISHIFTQB512,
30142 IX86_BUILTIN_VPMULTISHIFTQB256,
30143 IX86_BUILTIN_VPMULTISHIFTQB128,
30144 IX86_BUILTIN_VPERMVARQI512_MASK,
30145 IX86_BUILTIN_VPERMT2VARQI512,
30146 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30147 IX86_BUILTIN_VPERMI2VARQI512,
30148 IX86_BUILTIN_VPERMVARQI256_MASK,
30149 IX86_BUILTIN_VPERMVARQI128_MASK,
30150 IX86_BUILTIN_VPERMT2VARQI256,
30151 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30152 IX86_BUILTIN_VPERMT2VARQI128,
30153 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30154 IX86_BUILTIN_VPERMI2VARQI256,
30155 IX86_BUILTIN_VPERMI2VARQI128,
30157 /* SHA builtins. */
30158 IX86_BUILTIN_SHA1MSG1,
30159 IX86_BUILTIN_SHA1MSG2,
30160 IX86_BUILTIN_SHA1NEXTE,
30161 IX86_BUILTIN_SHA1RNDS4,
30162 IX86_BUILTIN_SHA256MSG1,
30163 IX86_BUILTIN_SHA256MSG2,
30164 IX86_BUILTIN_SHA256RNDS2,
30166 /* CLWB instructions. */
30167 IX86_BUILTIN_CLWB,
30169 /* PCOMMIT instructions. */
30170 IX86_BUILTIN_PCOMMIT,
30172 /* CLFLUSHOPT instructions. */
30173 IX86_BUILTIN_CLFLUSHOPT,
30175 /* TFmode support builtins. */
30176 IX86_BUILTIN_INFQ,
30177 IX86_BUILTIN_HUGE_VALQ,
30178 IX86_BUILTIN_FABSQ,
30179 IX86_BUILTIN_COPYSIGNQ,
30181 /* Vectorizer support builtins. */
30182 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30183 IX86_BUILTIN_CPYSGNPS,
30184 IX86_BUILTIN_CPYSGNPD,
30185 IX86_BUILTIN_CPYSGNPS256,
30186 IX86_BUILTIN_CPYSGNPS512,
30187 IX86_BUILTIN_CPYSGNPD256,
30188 IX86_BUILTIN_CPYSGNPD512,
30189 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30190 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30193 /* FMA4 instructions. */
30194 IX86_BUILTIN_VFMADDSS,
30195 IX86_BUILTIN_VFMADDSD,
30196 IX86_BUILTIN_VFMADDPS,
30197 IX86_BUILTIN_VFMADDPD,
30198 IX86_BUILTIN_VFMADDPS256,
30199 IX86_BUILTIN_VFMADDPD256,
30200 IX86_BUILTIN_VFMADDSUBPS,
30201 IX86_BUILTIN_VFMADDSUBPD,
30202 IX86_BUILTIN_VFMADDSUBPS256,
30203 IX86_BUILTIN_VFMADDSUBPD256,
30205 /* FMA3 instructions. */
30206 IX86_BUILTIN_VFMADDSS3,
30207 IX86_BUILTIN_VFMADDSD3,
30209 /* XOP instructions. */
30210 IX86_BUILTIN_VPCMOV,
30211 IX86_BUILTIN_VPCMOV_V2DI,
30212 IX86_BUILTIN_VPCMOV_V4SI,
30213 IX86_BUILTIN_VPCMOV_V8HI,
30214 IX86_BUILTIN_VPCMOV_V16QI,
30215 IX86_BUILTIN_VPCMOV_V4SF,
30216 IX86_BUILTIN_VPCMOV_V2DF,
30217 IX86_BUILTIN_VPCMOV256,
30218 IX86_BUILTIN_VPCMOV_V4DI256,
30219 IX86_BUILTIN_VPCMOV_V8SI256,
30220 IX86_BUILTIN_VPCMOV_V16HI256,
30221 IX86_BUILTIN_VPCMOV_V32QI256,
30222 IX86_BUILTIN_VPCMOV_V8SF256,
30223 IX86_BUILTIN_VPCMOV_V4DF256,
30225 IX86_BUILTIN_VPPERM,
30227 IX86_BUILTIN_VPMACSSWW,
30228 IX86_BUILTIN_VPMACSWW,
30229 IX86_BUILTIN_VPMACSSWD,
30230 IX86_BUILTIN_VPMACSWD,
30231 IX86_BUILTIN_VPMACSSDD,
30232 IX86_BUILTIN_VPMACSDD,
30233 IX86_BUILTIN_VPMACSSDQL,
30234 IX86_BUILTIN_VPMACSSDQH,
30235 IX86_BUILTIN_VPMACSDQL,
30236 IX86_BUILTIN_VPMACSDQH,
30237 IX86_BUILTIN_VPMADCSSWD,
30238 IX86_BUILTIN_VPMADCSWD,
30240 IX86_BUILTIN_VPHADDBW,
30241 IX86_BUILTIN_VPHADDBD,
30242 IX86_BUILTIN_VPHADDBQ,
30243 IX86_BUILTIN_VPHADDWD,
30244 IX86_BUILTIN_VPHADDWQ,
30245 IX86_BUILTIN_VPHADDDQ,
30246 IX86_BUILTIN_VPHADDUBW,
30247 IX86_BUILTIN_VPHADDUBD,
30248 IX86_BUILTIN_VPHADDUBQ,
30249 IX86_BUILTIN_VPHADDUWD,
30250 IX86_BUILTIN_VPHADDUWQ,
30251 IX86_BUILTIN_VPHADDUDQ,
30252 IX86_BUILTIN_VPHSUBBW,
30253 IX86_BUILTIN_VPHSUBWD,
30254 IX86_BUILTIN_VPHSUBDQ,
30256 IX86_BUILTIN_VPROTB,
30257 IX86_BUILTIN_VPROTW,
30258 IX86_BUILTIN_VPROTD,
30259 IX86_BUILTIN_VPROTQ,
30260 IX86_BUILTIN_VPROTB_IMM,
30261 IX86_BUILTIN_VPROTW_IMM,
30262 IX86_BUILTIN_VPROTD_IMM,
30263 IX86_BUILTIN_VPROTQ_IMM,
30265 IX86_BUILTIN_VPSHLB,
30266 IX86_BUILTIN_VPSHLW,
30267 IX86_BUILTIN_VPSHLD,
30268 IX86_BUILTIN_VPSHLQ,
30269 IX86_BUILTIN_VPSHAB,
30270 IX86_BUILTIN_VPSHAW,
30271 IX86_BUILTIN_VPSHAD,
30272 IX86_BUILTIN_VPSHAQ,
30274 IX86_BUILTIN_VFRCZSS,
30275 IX86_BUILTIN_VFRCZSD,
30276 IX86_BUILTIN_VFRCZPS,
30277 IX86_BUILTIN_VFRCZPD,
30278 IX86_BUILTIN_VFRCZPS256,
30279 IX86_BUILTIN_VFRCZPD256,
30281 IX86_BUILTIN_VPCOMEQUB,
30282 IX86_BUILTIN_VPCOMNEUB,
30283 IX86_BUILTIN_VPCOMLTUB,
30284 IX86_BUILTIN_VPCOMLEUB,
30285 IX86_BUILTIN_VPCOMGTUB,
30286 IX86_BUILTIN_VPCOMGEUB,
30287 IX86_BUILTIN_VPCOMFALSEUB,
30288 IX86_BUILTIN_VPCOMTRUEUB,
30290 IX86_BUILTIN_VPCOMEQUW,
30291 IX86_BUILTIN_VPCOMNEUW,
30292 IX86_BUILTIN_VPCOMLTUW,
30293 IX86_BUILTIN_VPCOMLEUW,
30294 IX86_BUILTIN_VPCOMGTUW,
30295 IX86_BUILTIN_VPCOMGEUW,
30296 IX86_BUILTIN_VPCOMFALSEUW,
30297 IX86_BUILTIN_VPCOMTRUEUW,
30299 IX86_BUILTIN_VPCOMEQUD,
30300 IX86_BUILTIN_VPCOMNEUD,
30301 IX86_BUILTIN_VPCOMLTUD,
30302 IX86_BUILTIN_VPCOMLEUD,
30303 IX86_BUILTIN_VPCOMGTUD,
30304 IX86_BUILTIN_VPCOMGEUD,
30305 IX86_BUILTIN_VPCOMFALSEUD,
30306 IX86_BUILTIN_VPCOMTRUEUD,
30308 IX86_BUILTIN_VPCOMEQUQ,
30309 IX86_BUILTIN_VPCOMNEUQ,
30310 IX86_BUILTIN_VPCOMLTUQ,
30311 IX86_BUILTIN_VPCOMLEUQ,
30312 IX86_BUILTIN_VPCOMGTUQ,
30313 IX86_BUILTIN_VPCOMGEUQ,
30314 IX86_BUILTIN_VPCOMFALSEUQ,
30315 IX86_BUILTIN_VPCOMTRUEUQ,
30317 IX86_BUILTIN_VPCOMEQB,
30318 IX86_BUILTIN_VPCOMNEB,
30319 IX86_BUILTIN_VPCOMLTB,
30320 IX86_BUILTIN_VPCOMLEB,
30321 IX86_BUILTIN_VPCOMGTB,
30322 IX86_BUILTIN_VPCOMGEB,
30323 IX86_BUILTIN_VPCOMFALSEB,
30324 IX86_BUILTIN_VPCOMTRUEB,
30326 IX86_BUILTIN_VPCOMEQW,
30327 IX86_BUILTIN_VPCOMNEW,
30328 IX86_BUILTIN_VPCOMLTW,
30329 IX86_BUILTIN_VPCOMLEW,
30330 IX86_BUILTIN_VPCOMGTW,
30331 IX86_BUILTIN_VPCOMGEW,
30332 IX86_BUILTIN_VPCOMFALSEW,
30333 IX86_BUILTIN_VPCOMTRUEW,
30335 IX86_BUILTIN_VPCOMEQD,
30336 IX86_BUILTIN_VPCOMNED,
30337 IX86_BUILTIN_VPCOMLTD,
30338 IX86_BUILTIN_VPCOMLED,
30339 IX86_BUILTIN_VPCOMGTD,
30340 IX86_BUILTIN_VPCOMGED,
30341 IX86_BUILTIN_VPCOMFALSED,
30342 IX86_BUILTIN_VPCOMTRUED,
30344 IX86_BUILTIN_VPCOMEQQ,
30345 IX86_BUILTIN_VPCOMNEQ,
30346 IX86_BUILTIN_VPCOMLTQ,
30347 IX86_BUILTIN_VPCOMLEQ,
30348 IX86_BUILTIN_VPCOMGTQ,
30349 IX86_BUILTIN_VPCOMGEQ,
30350 IX86_BUILTIN_VPCOMFALSEQ,
30351 IX86_BUILTIN_VPCOMTRUEQ,
30353 /* LWP instructions. */
30354 IX86_BUILTIN_LLWPCB,
30355 IX86_BUILTIN_SLWPCB,
30356 IX86_BUILTIN_LWPVAL32,
30357 IX86_BUILTIN_LWPVAL64,
30358 IX86_BUILTIN_LWPINS32,
30359 IX86_BUILTIN_LWPINS64,
30361 IX86_BUILTIN_CLZS,
30363 /* RTM */
30364 IX86_BUILTIN_XBEGIN,
30365 IX86_BUILTIN_XEND,
30366 IX86_BUILTIN_XABORT,
30367 IX86_BUILTIN_XTEST,
30369 /* MPX */
30370 IX86_BUILTIN_BNDMK,
30371 IX86_BUILTIN_BNDSTX,
30372 IX86_BUILTIN_BNDLDX,
30373 IX86_BUILTIN_BNDCL,
30374 IX86_BUILTIN_BNDCU,
30375 IX86_BUILTIN_BNDRET,
30376 IX86_BUILTIN_BNDNARROW,
30377 IX86_BUILTIN_BNDINT,
30378 IX86_BUILTIN_SIZEOF,
30379 IX86_BUILTIN_BNDLOWER,
30380 IX86_BUILTIN_BNDUPPER,
30382 /* BMI instructions. */
30383 IX86_BUILTIN_BEXTR32,
30384 IX86_BUILTIN_BEXTR64,
30385 IX86_BUILTIN_CTZS,
30387 /* TBM instructions. */
30388 IX86_BUILTIN_BEXTRI32,
30389 IX86_BUILTIN_BEXTRI64,
30391 /* BMI2 instructions. */
30392 IX86_BUILTIN_BZHI32,
30393 IX86_BUILTIN_BZHI64,
30394 IX86_BUILTIN_PDEP32,
30395 IX86_BUILTIN_PDEP64,
30396 IX86_BUILTIN_PEXT32,
30397 IX86_BUILTIN_PEXT64,
30399 /* ADX instructions. */
30400 IX86_BUILTIN_ADDCARRYX32,
30401 IX86_BUILTIN_ADDCARRYX64,
30403 /* SBB instructions. */
30404 IX86_BUILTIN_SBB32,
30405 IX86_BUILTIN_SBB64,
30407 /* FSGSBASE instructions. */
30408 IX86_BUILTIN_RDFSBASE32,
30409 IX86_BUILTIN_RDFSBASE64,
30410 IX86_BUILTIN_RDGSBASE32,
30411 IX86_BUILTIN_RDGSBASE64,
30412 IX86_BUILTIN_WRFSBASE32,
30413 IX86_BUILTIN_WRFSBASE64,
30414 IX86_BUILTIN_WRGSBASE32,
30415 IX86_BUILTIN_WRGSBASE64,
30417 /* RDRND instructions. */
30418 IX86_BUILTIN_RDRAND16_STEP,
30419 IX86_BUILTIN_RDRAND32_STEP,
30420 IX86_BUILTIN_RDRAND64_STEP,
30422 /* RDSEED instructions. */
30423 IX86_BUILTIN_RDSEED16_STEP,
30424 IX86_BUILTIN_RDSEED32_STEP,
30425 IX86_BUILTIN_RDSEED64_STEP,
30427 /* F16C instructions. */
30428 IX86_BUILTIN_CVTPH2PS,
30429 IX86_BUILTIN_CVTPH2PS256,
30430 IX86_BUILTIN_CVTPS2PH,
30431 IX86_BUILTIN_CVTPS2PH256,
30433 /* CFString built-in for darwin */
30434 IX86_BUILTIN_CFSTRING,
30436 /* Builtins to get CPU type and supported features. */
30437 IX86_BUILTIN_CPU_INIT,
30438 IX86_BUILTIN_CPU_IS,
30439 IX86_BUILTIN_CPU_SUPPORTS,
30441 /* Read/write FLAGS register built-ins. */
30442 IX86_BUILTIN_READ_FLAGS,
30443 IX86_BUILTIN_WRITE_FLAGS,
30445 IX86_BUILTIN_MAX
30446 };
30448 /* Table for the ix86 builtin decls. */
30451 /* Table of all of the builtin functions that are possible with different ISA's
30452 but are waiting to be built until a function is declared to use that
30453 ISA. */
30462 };
30467 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30468 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30469 function decl in the ix86_builtins array. Returns the function decl or
30470 NULL_TREE, if the builtin was not added.
30472 If the front end has a special hook for builtin functions, delay adding
30473 builtin functions that aren't in the current ISA until the ISA is changed
30474 with function specific optimization. Doing so, can save about 300K for the
30475 default compiler. When the builtin is expanded, check at that time whether
30476 it is valid.
30478 If the front end doesn't have a special hook, record all builtins, even if
30479 it isn't an instruction set in the current ISA in case the user uses
30480 function specific options for a different ISA, so that we don't get scope
30481 errors if a builtin is added in the middle of a function scope. */
30487 {
30491 {
30500 {
30506 }
30507 else
30508 {
30516 }
30517 }
30520 }
30522 /* Like def_builtin, but also marks the function decl "const". */
30527 {
30531 else
30535 }
30537 /* Add any new builtin functions for a given ISA that may not have been
30538 declared. This saves a bit of space compared to adding all of the
30539 declarations to the tree, even if we didn't use them. */
30541 static void
30543 {
30547 {
30550 {
30553 /* Don't define the builtin again. */
30559 NULL_TREE);
30566 NULL_TREE);
30569 }
30570 }
30571 }
30573 /* Bits for builtin_description.flag. */
30575 /* Set when we don't support the comparison natively, and should
30576 swap_comparison in order to support it. */
30577 #define BUILTIN_DESC_SWAP_OPERANDS 1
30579 struct builtin_description
30580 {
30587 };
30590 {
30591 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30592 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30593 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30594 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30595 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30596 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30597 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30598 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30599 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30600 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30601 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30602 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30605 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30607 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30608 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30610 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30615 };
30618 {
30619 /* SSE4.2 */
30620 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30621 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30622 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30623 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30624 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30625 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30626 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30627 };
30630 {
30631 /* SSE4.2 */
30632 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30633 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30634 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30635 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30636 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30637 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30638 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30639 };
30641 /* Special builtins with variable number of arguments. */
30643 {
30644 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30645 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30646 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30648 /* 80387 (for use internally for atomic compound assignment). */
30649 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30650 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30651 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30652 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30654 /* MMX */
30655 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30657 /* 3DNow! */
30658 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30660 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30661 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30662 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30663 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30664 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30665 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30666 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30667 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30668 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30670 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30671 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30672 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30673 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30674 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30675 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30676 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30677 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30679 /* SSE */
30680 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30681 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30682 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30684 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30685 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30686 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30687 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30689 /* SSE or 3DNow!A */
30690 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30691 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30693 /* SSE2 */
30694 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30698 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30699 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30700 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30701 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30705 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30708 /* SSE3 */
30709 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30711 /* SSE4.1 */
30712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30714 /* SSE4A */
30715 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30716 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30718 /* AVX */
30719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30722 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30723 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30724 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30749 /* AVX2 */
30750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30760 /* AVX512F */
30761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30809 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30810 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30811 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30812 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30813 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30814 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30816 /* FSGSBASE */
30817 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30818 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30819 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30820 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30821 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30822 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30823 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30824 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30826 /* RTM */
30827 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30828 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30829 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30831 /* AVX512BW */
30832 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30833 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30834 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30835 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30837 /* AVX512VL */
30838 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30839 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30840 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30841 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30846 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30874 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30875 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30876 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30877 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30933 /* PCOMMIT. */
30934 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
30935 };
30937 /* Builtins with variable number of arguments. */
30939 {
30940 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30941 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30942 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30943 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30944 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30945 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30946 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30948 /* MMX */
30949 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30950 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30951 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30952 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30953 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30954 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30956 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30957 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30958 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30959 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30960 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30961 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30962 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30963 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30965 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30966 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30974 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30978 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30982 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30984 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
30985 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
30987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
30989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
30993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31012 /* 3DNow! */
31013 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31014 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31015 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31016 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31018 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31019 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31020 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31021 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31022 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31023 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31024 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31025 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31026 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31027 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31028 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31029 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31030 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31031 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31032 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31034 /* 3DNow!A */
31035 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31036 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31037 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31038 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31039 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31040 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31042 /* SSE */
31043 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31044 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31045 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31046 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31047 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31048 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31049 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31050 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31051 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31052 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31053 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31054 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31056 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31058 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31059 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31060 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31061 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31062 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31064 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31065 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31067 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31068 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31069 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31070 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31072 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31075 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31076 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31077 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31078 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31088 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31089 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31093 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31095 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31096 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31098 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31103 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31104 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31108 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31110 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31116 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31117 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31119 /* SSE MMX or 3Dnow!A */
31120 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31121 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31122 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31124 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31125 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31126 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31127 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31129 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31130 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31132 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31134 /* SSE2 */
31135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31139 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31140 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31141 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31152 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31153 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31154 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31158 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31160 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31161 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31162 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31163 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31169 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31171 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31191 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31195 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31197 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31200 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31203 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31204 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31206 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31208 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31209 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31210 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31211 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31212 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31213 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31214 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31215 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31226 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31227 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31229 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31231 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31232 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31244 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31245 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31246 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31247 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31249 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31250 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31251 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31252 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31253 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31254 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31255 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31256 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31262 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31266 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31271 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31276 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31277 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31278 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31279 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31280 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31281 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31284 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31285 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31286 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31288 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31291 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31292 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31293 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31294 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31302 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31304 /* SSE2 MMX */
31305 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31306 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31308 /* SSE3 */
31309 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31310 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31312 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31313 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31314 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31315 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31316 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31317 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31319 /* SSSE3 */
31320 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31321 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31322 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31323 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31324 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31325 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31327 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31328 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31329 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31330 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31331 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31332 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31333 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31334 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31335 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31336 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31337 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31338 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31339 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31340 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31341 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31342 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31343 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31344 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31345 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31346 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31347 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31348 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31349 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31350 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31352 /* SSSE3. */
31353 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31354 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31356 /* SSE4.1 */
31357 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31358 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31359 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31360 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31361 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31362 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31363 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31364 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31365 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31366 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31368 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31369 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31370 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31371 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31372 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31373 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31374 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31375 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31376 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31377 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31378 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31379 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31380 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31382 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31383 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31384 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31385 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31386 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31387 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31388 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31389 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31390 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31391 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31392 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31393 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31395 /* SSE4.1 */
31396 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31397 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31398 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31399 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31401 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31402 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31403 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31404 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31406 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31407 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31409 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31410 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31412 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31413 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31414 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31415 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31417 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31418 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31420 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31421 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31423 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31424 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31425 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31427 /* SSE4.2 */
31428 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31429 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31430 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31431 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31432 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31434 /* SSE4A */
31435 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31436 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31437 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31438 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31440 /* AES */
31441 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31442 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31444 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31445 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31446 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31447 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31449 /* PCLMUL */
31450 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31452 /* AVX */
31453 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31454 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31455 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31456 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31457 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31458 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31460 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31461 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31462 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31463 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31467 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31468 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31469 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31470 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31471 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31472 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31473 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31474 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31475 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31476 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31477 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31478 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31480 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31481 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31482 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31483 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31485 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31487 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31488 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31489 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31490 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31491 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31492 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31493 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31494 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31495 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31496 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31497 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31498 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31501 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31502 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31506 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31508 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31524 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31526 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31528 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31540 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31541 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31554 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31555 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31565 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31566 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31567 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31588 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31589 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31591 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31593 /* AVX2 */
31594 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31595 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31596 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31597 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31598 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31599 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31600 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31601 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31602 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31603 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31604 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31605 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31606 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31607 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31608 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31609 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31610 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31611 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31612 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31613 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31614 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31615 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31616 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31617 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31618 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31619 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31620 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31621 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31622 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31623 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31624 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31625 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31626 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31627 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31628 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31629 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31630 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31631 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31632 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31633 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31634 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31635 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31636 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31637 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31638 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31639 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31640 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31641 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31642 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31643 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31644 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31658 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31660 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31661 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31662 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31663 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31664 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31665 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31675 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31676 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31677 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31678 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31679 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31680 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31681 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31682 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31683 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31684 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31686 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31687 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31688 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31689 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31690 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31691 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31692 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31693 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31694 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31695 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31701 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31708 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31718 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31730 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31731 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31733 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31741 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31743 /* BMI */
31744 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31745 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31746 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31748 /* TBM */
31749 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31750 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31752 /* F16C */
31753 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31754 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31755 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31756 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31758 /* BMI2 */
31759 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31760 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31761 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31762 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31763 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31764 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31766 /* AVX512F */
31767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31822 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31823 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31933 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31934 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31935 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31936 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31968 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31973 /* Mask arithmetic operations */
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
31985 /* SHA */
31986 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31987 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31988 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31989 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
31994 /* AVX512VL. */
31995 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
31996 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
31997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
31998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32005 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32006 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32007 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32008 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32033 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32034 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32035 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32036 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32037 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32038 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32039 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32040 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32041 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32042 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32043 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32044 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32045 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32050 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32051 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32052 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32053 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32054 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32055 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32056 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32057 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32058 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32059 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32062 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32063 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32064 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32065 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32086 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32087 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32088 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32089 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32090 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32091 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32092 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32093 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32099 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32100 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32101 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32102 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32103 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32105 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32106 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32108 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32109 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32110 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32111 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32112 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32113 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32114 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32115 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32116 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32120 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32121 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32122 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32133 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32134 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32135 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32136 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32137 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32138 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32139 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32140 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32141 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32142 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32143 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32144 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32145 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32146 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32159 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32160 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32163 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32164 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32167 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32168 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32169 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32170 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32171 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32172 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32173 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32174 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32175 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32176 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32179 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32180 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32181 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32182 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32183 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32184 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32187 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32188 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32189 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32190 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32195 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32196 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32197 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32198 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32199 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32200 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32231 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32232 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32233 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32234 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32251 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32252 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32253 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32254 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32255 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32256 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32257 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32258 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32259 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32260 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32261 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32262 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32263 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32264 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32265 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32266 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32267 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32268 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32269 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32272 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32275 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32276 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32304 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32311 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32312 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32313 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32314 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32315 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32377 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32378 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32379 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32380 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32381 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32382 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32383 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32384 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32385 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32386 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32391 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32392 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32393 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32394 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32405 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32406 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32407 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32408 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32409 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32410 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32411 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32412 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32437 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32438 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32439 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32440 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32469 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32470 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32471 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32472 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32473 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32474 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32475 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32476 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32485 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32486 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32487 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32488 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32489 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32490 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32492 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32493 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32494 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32495 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32496 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32497 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32498 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32503 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32504 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32505 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32506 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32507 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32508 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32509 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32510 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32515 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32516 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32517 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32523 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32524 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32525 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32526 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32531 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32532 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32533 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32534 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32539 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32540 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32541 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32542 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32549 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32583 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32584 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32585 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32586 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32587 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32588 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32589 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32590 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32591 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32592 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32593 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32594 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32595 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32596 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32597 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32598 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32599 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32600 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32601 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32602 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32610 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32611 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32612 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32613 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32631 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32632 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32633 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32634 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32635 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32636 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32637 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32638 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32639 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32640 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32648 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32652 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32653 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32654 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32655 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32672 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32673 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32674 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32675 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32691 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32692 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32693 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32694 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32708 /* AVX512DQ. */
32709 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32710 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32711 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32712 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32713 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32714 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32715 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32716 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32717 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32718 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32719 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32720 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32721 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32722 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32723 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32724 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32725 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32726 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32727 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32728 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32729 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32730 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32731 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32732 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32733 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32734 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32735 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32736 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32737 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32738 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32739 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32741 /* AVX512BW. */
32742 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32743 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32744 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32745 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32746 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32747 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32748 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32749 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32750 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32751 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32752 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32753 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32754 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32755 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32756 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32757 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32758 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32759 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32760 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32761 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32762 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32763 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32764 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32765 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32766 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32767 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32768 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32769 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32770 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32771 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32772 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32773 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32774 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32775 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32776 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32777 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32778 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32779 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32780 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32781 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32782 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32783 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32784 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32785 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32786 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32787 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32788 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32789 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32790 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32791 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32792 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32793 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32794 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32795 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32796 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32797 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32798 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32799 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32800 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32801 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32802 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32803 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32808 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32809 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32810 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32811 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32812 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32813 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32814 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32815 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32816 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32817 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32818 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32819 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32820 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32821 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32822 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32823 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32824 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32825 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32826 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32827 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32828 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32829 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32830 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32831 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32832 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32834 /* AVX512IFMA */
32835 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32836 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32837 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32838 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32839 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32840 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32841 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32842 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32843 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32844 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32845 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32846 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32848 /* AVX512VBMI */
32849 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32850 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32851 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32852 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32853 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32854 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32855 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32856 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32857 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32858 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32859 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32860 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32861 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32862 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32863 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32864 };
32866 /* Builtins with rounding support. */
32868 {
32869 /* AVX512F */
32870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32889 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32891 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32898 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32900 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32950 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32952 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32954 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32956 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32958 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32960 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32962 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32964 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
32972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
32973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32990 /* AVX512ER */
32991 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32992 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32993 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32994 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32995 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32996 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32997 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32998 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32999 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33000 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33002 /* AVX512DQ. */
33003 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33004 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33005 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33006 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33007 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33008 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33009 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33010 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33011 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33012 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33013 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33014 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33015 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33016 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33017 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33018 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33019 };
33021 /* Bultins for MPX. */
33023 {
33024 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33025 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33026 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33027 };
33029 /* Const builtins for MPX. */
33031 {
33032 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33033 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33034 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33035 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33036 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33037 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33038 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33039 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33040 };
33042 /* FMA4 and XOP. */
33043 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33044 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33045 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33046 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33047 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33048 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33049 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33050 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33051 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33052 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33053 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33054 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33055 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33056 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33057 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33058 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33059 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33060 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33061 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33062 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33063 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33064 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33065 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33066 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33067 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33068 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33069 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33070 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33071 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33072 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33073 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33074 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33075 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33076 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33077 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33078 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33079 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33080 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33081 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33082 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33083 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33084 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33085 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33086 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33087 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33088 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33089 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33090 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33091 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33092 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33093 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33094 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33097 {
33138 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33139 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33140 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33141 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33142 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33143 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33144 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33146 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33147 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33148 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33149 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33150 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33151 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33152 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33154 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33156 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33157 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33158 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33159 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33160 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33161 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33162 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33163 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33164 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33165 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33166 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33167 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33169 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33170 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33171 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33172 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33173 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33174 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33175 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33176 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33177 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33178 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33179 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33180 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33181 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33182 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33183 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33184 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33186 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33187 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33188 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33189 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33190 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33191 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33193 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33194 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33195 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33197 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33199 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33200 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33202 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33203 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33204 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33207 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33211 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33212 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33213 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33215 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33217 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33218 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33223 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33226 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33229 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33231 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33234 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33236 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33239 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33241 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33242 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33243 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33247 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33250 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33252 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33265 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33266 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33271 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33273 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33274 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33276 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33279 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33282 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33284 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33289 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33296 };
33297 \f
33298 /* TM vector builtins. */
33300 /* Reuse the existing x86-specific `struct builtin_description' cause
33301 we're lazy. Add casts to make them fit. */
33303 {
33304 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33305 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33306 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33307 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33308 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33309 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33310 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33312 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33313 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33314 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33315 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33316 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33317 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33318 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33320 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33321 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33322 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33323 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33324 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33325 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33326 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33328 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33329 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33330 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33331 };
33333 /* TM callbacks. */
33335 /* Return the builtin decl needed to load a vector of TYPE. */
33337 static tree
33339 {
33341 {
33343 {
33350 }
33351 }
33353 }
33355 /* Return the builtin decl needed to store a vector of TYPE. */
33357 static tree
33359 {
33361 {
33363 {
33370 }
33371 }
33373 }
33374 \f
33375 /* Initialize the transactional memory vector load/store builtins. */
33377 static void
33379 {
33383 tree decl;
33390 /* If there are no builtins defined, we must be compiling in a
33391 language without trans-mem support. */
33395 /* Use whatever attributes a normal TM load has. */
33399 /* Use whatever attributes a normal TM store has. */
33403 /* Use whatever attributes a normal TM log has. */
33411 {
33415 {
33423 {
33426 }
33428 {
33431 }
33432 else
33433 {
33436 }
33438 /* The builtin without the prefix for
33439 calling it directly. */
33441 attrs);
33442 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33443 set the TYPE_ATTRIBUTES. */
33447 }
33448 }
33449 }
33451 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33452 in the current target ISA to allow the user to compile particular modules
33453 with different target specific options that differ from the command line
33454 options. */
33455 static void
33457 {
33462 /* Add all special builtins with variable number of operands. */
33466 {
33472 }
33474 /* Add all builtins with variable number of operands. */
33478 {
33484 }
33486 /* Add all builtins with rounding. */
33490 {
33496 }
33498 /* pcmpestr[im] insns. */
33502 {
33505 else
33508 }
33510 /* pcmpistr[im] insns. */
33514 {
33517 else
33520 }
33522 /* comi/ucomi insns. */
33524 {
33527 else
33530 }
33532 /* SSE */
33538 /* SSE or 3DNow!A */
33541 IX86_BUILTIN_MASKMOVQ);
33543 /* SSE2 */
33552 /* SSE3. */
33558 /* AES */
33572 /* PCLMUL */
33576 /* RDRND */
33583 IX86_BUILTIN_RDRAND64_STEP);
33585 /* AVX2 */
33587 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33588 IX86_BUILTIN_GATHERSIV2DF);
33591 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33592 IX86_BUILTIN_GATHERSIV4DF);
33595 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33596 IX86_BUILTIN_GATHERDIV2DF);
33599 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33600 IX86_BUILTIN_GATHERDIV4DF);
33603 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33604 IX86_BUILTIN_GATHERSIV4SF);
33607 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33608 IX86_BUILTIN_GATHERSIV8SF);
33611 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33612 IX86_BUILTIN_GATHERDIV4SF);
33615 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33616 IX86_BUILTIN_GATHERDIV8SF);
33619 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33620 IX86_BUILTIN_GATHERSIV2DI);
33623 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33624 IX86_BUILTIN_GATHERSIV4DI);
33627 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33628 IX86_BUILTIN_GATHERDIV2DI);
33631 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33632 IX86_BUILTIN_GATHERDIV4DI);
33635 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33636 IX86_BUILTIN_GATHERSIV4SI);
33639 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33640 IX86_BUILTIN_GATHERSIV8SI);
33643 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33644 IX86_BUILTIN_GATHERDIV4SI);
33647 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33648 IX86_BUILTIN_GATHERDIV8SI);
33651 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33652 IX86_BUILTIN_GATHERALTSIV4DF);
33655 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33656 IX86_BUILTIN_GATHERALTDIV8SF);
33659 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33660 IX86_BUILTIN_GATHERALTSIV4DI);
33663 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33664 IX86_BUILTIN_GATHERALTDIV8SI);
33666 /* AVX512F */
33668 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33669 IX86_BUILTIN_GATHER3SIV16SF);
33672 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33673 IX86_BUILTIN_GATHER3SIV8DF);
33676 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33677 IX86_BUILTIN_GATHER3DIV16SF);
33680 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33681 IX86_BUILTIN_GATHER3DIV8DF);
33684 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33685 IX86_BUILTIN_GATHER3SIV16SI);
33688 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33689 IX86_BUILTIN_GATHER3SIV8DI);
33692 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33693 IX86_BUILTIN_GATHER3DIV16SI);
33696 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33697 IX86_BUILTIN_GATHER3DIV8DI);
33700 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33701 IX86_BUILTIN_GATHER3ALTSIV8DF);
33704 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33705 IX86_BUILTIN_GATHER3ALTDIV16SF);
33708 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33709 IX86_BUILTIN_GATHER3ALTSIV8DI);
33712 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33713 IX86_BUILTIN_GATHER3ALTDIV16SI);
33716 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33717 IX86_BUILTIN_SCATTERSIV16SF);
33720 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33721 IX86_BUILTIN_SCATTERSIV8DF);
33724 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33725 IX86_BUILTIN_SCATTERDIV16SF);
33728 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33729 IX86_BUILTIN_SCATTERDIV8DF);
33732 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33733 IX86_BUILTIN_SCATTERSIV16SI);
33736 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33737 IX86_BUILTIN_SCATTERSIV8DI);
33740 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33741 IX86_BUILTIN_SCATTERDIV16SI);
33744 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33745 IX86_BUILTIN_SCATTERDIV8DI);
33747 /* AVX512VL */
33749 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33750 IX86_BUILTIN_GATHER3SIV2DF);
33753 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33754 IX86_BUILTIN_GATHER3SIV4DF);
33757 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33758 IX86_BUILTIN_GATHER3DIV2DF);
33761 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33762 IX86_BUILTIN_GATHER3DIV4DF);
33765 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33766 IX86_BUILTIN_GATHER3SIV4SF);
33769 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33770 IX86_BUILTIN_GATHER3SIV8SF);
33773 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33774 IX86_BUILTIN_GATHER3DIV4SF);
33777 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33778 IX86_BUILTIN_GATHER3DIV8SF);
33781 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33782 IX86_BUILTIN_GATHER3SIV2DI);
33785 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33786 IX86_BUILTIN_GATHER3SIV4DI);
33789 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33790 IX86_BUILTIN_GATHER3DIV2DI);
33793 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33794 IX86_BUILTIN_GATHER3DIV4DI);
33797 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33798 IX86_BUILTIN_GATHER3SIV4SI);
33801 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33802 IX86_BUILTIN_GATHER3SIV8SI);
33805 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33806 IX86_BUILTIN_GATHER3DIV4SI);
33809 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33810 IX86_BUILTIN_GATHER3DIV8SI);
33813 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33814 IX86_BUILTIN_GATHER3ALTSIV4DF);
33817 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33818 IX86_BUILTIN_GATHER3ALTDIV8SF);
33821 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33822 IX86_BUILTIN_GATHER3ALTSIV4DI);
33825 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33826 IX86_BUILTIN_GATHER3ALTDIV8SI);
33829 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33830 IX86_BUILTIN_SCATTERSIV8SF);
33833 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33834 IX86_BUILTIN_SCATTERSIV4SF);
33837 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33838 IX86_BUILTIN_SCATTERSIV4DF);
33841 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33842 IX86_BUILTIN_SCATTERSIV2DF);
33845 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33846 IX86_BUILTIN_SCATTERDIV8SF);
33849 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33850 IX86_BUILTIN_SCATTERDIV4SF);
33853 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33854 IX86_BUILTIN_SCATTERDIV4DF);
33857 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33858 IX86_BUILTIN_SCATTERDIV2DF);
33861 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33862 IX86_BUILTIN_SCATTERSIV8SI);
33865 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33866 IX86_BUILTIN_SCATTERSIV4SI);
33869 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33870 IX86_BUILTIN_SCATTERSIV4DI);
33873 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33874 IX86_BUILTIN_SCATTERSIV2DI);
33877 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33878 IX86_BUILTIN_SCATTERDIV8SI);
33881 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33882 IX86_BUILTIN_SCATTERDIV4SI);
33885 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33886 IX86_BUILTIN_SCATTERDIV4DI);
33889 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33890 IX86_BUILTIN_SCATTERDIV2DI);
33892 /* AVX512PF */
33894 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33895 IX86_BUILTIN_GATHERPFDPD);
33897 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33898 IX86_BUILTIN_GATHERPFDPS);
33900 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33901 IX86_BUILTIN_GATHERPFQPD);
33903 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33904 IX86_BUILTIN_GATHERPFQPS);
33906 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33907 IX86_BUILTIN_SCATTERPFDPD);
33909 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33910 IX86_BUILTIN_SCATTERPFDPS);
33912 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33913 IX86_BUILTIN_SCATTERPFQPD);
33915 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33916 IX86_BUILTIN_SCATTERPFQPS);
33918 /* SHA */
33934 /* RTM. */
33938 /* MMX access to the vec_init patterns. */
33943 V4HI_FTYPE_HI_HI_HI_HI,
33944 IX86_BUILTIN_VEC_INIT_V4HI);
33947 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33948 IX86_BUILTIN_VEC_INIT_V8QI);
33950 /* Access to the vec_extract patterns. */
33972 /* Access to the vec_set patterns. */
33993 /* RDSEED */
34002 /* ADCX */
34007 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34008 IX86_BUILTIN_ADDCARRYX64);
34010 /* SBB */
34015 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34016 IX86_BUILTIN_SBB64);
34018 /* Read/write FLAGS. */
34028 /* CLFLUSHOPT. */
34032 /* CLWB. */
34036 /* Add FMA4 multi-arg argument instructions */
34038 {
34044 }
34045 }
34047 static void
34049 {
34052 tree decl;
34058 {
34065 /* With no leaf and nothrow flags for MPX builtins
34066 abnormal edges may follow its call when setjmp
34067 presents in the function. Since we may have a lot
34068 of MPX builtins calls it causes lots of useless
34069 edges and enormous PHI nodes. To avoid this we mark
34070 MPX builtins as leaf and nothrow. */
34072 {
34074 NULL_TREE);
34076 }
34077 else
34078 {
34081 }
34082 }
34087 {
34095 {
34097 NULL_TREE);
34099 }
34100 else
34101 {
34104 }
34105 }
34106 }
34108 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34109 to return a pointer to VERSION_DECL if the outcome of the expression
34110 formed by PREDICATE_CHAIN is true. This function will be called during
34111 version dispatch to decide which function version to execute. It returns
34112 the basic block at the end, to which more conditions can be added. */
34114 static basic_block
34117 {
34118 gimple return_stmt;
34120 gimple convert_stmt;
34121 gimple call_cond_stmt;
34122 gimple if_else_stmt;
34128 gimple_seq gseq;
34145 {
34153 }
34156 {
34171 else
34172 {
34173 gimple assign_stmt;
34174 /* Use MIN_EXPR to check if any integer is zero?.
34175 and_expr_var = min_expr <cond_var, and_expr_var> */
34183 }
34184 }
34187 integer_zero_node,
34217 }
34219 /* This parses the attribute arguments to target in DECL and determines
34220 the right builtin to use to match the platform specification.
34221 It returns the priority value for this version decl. If PREDICATE_LIST
34222 is not NULL, it stores the list of cpu features that need to be checked
34223 before dispatching this function. */
34225 static unsigned int
34227 {
34228 tree attrs;
34230 tree target_node;
34237 /* Priority of i386 features, greater value is higher priority. This is
34238 used to decide the order in which function dispatch must happen. For
34239 instance, a version specialized for SSE4.2 should be checked for dispatch
34240 before a version for SSE3, as SSE4.2 implies SSE3. */
34241 enum feature_priority
34242 {
34244 P_MMX,
34245 P_SSE,
34246 P_SSE2,
34247 P_SSE3,
34248 P_SSSE3,
34249 P_PROC_SSSE3,
34250 P_SSE4_A,
34251 P_PROC_SSE4_A,
34252 P_SSE4_1,
34253 P_SSE4_2,
34254 P_PROC_SSE4_2,
34255 P_POPCNT,
34256 P_AVX,
34257 P_PROC_AVX,
34258 P_FMA4,
34259 P_XOP,
34260 P_PROC_XOP,
34261 P_FMA,
34262 P_PROC_FMA,
34263 P_AVX2,
34264 P_PROC_AVX2,
34265 P_AVX512F,
34266 P_PROC_AVX512F
34267 };
34271 /* These are the target attribute strings for which a dispatcher is
34272 available, from fold_builtin_cpu. */
34274 static struct _feature_list
34275 {
34278 }
34280 {
34296 };
34299 static unsigned int NUM_FEATURES
34315 /* Return priority zero for default function. */
34319 /* Handle arch= if specified. For priority, set it to be 1 more than
34320 the best instruction set the processor can handle. For instance, if
34321 there is a version for atom and a version for ssse3 (the highest ISA
34322 priority for atom), the atom version must be checked for dispatch
34323 before the ssse3 version. */
34325 {
34335 {
34337 {
34345 else
34346 /* We translate "arch=corei7" and "arch=nehalem" to
34347 "corei7" so that it will be mapped to M_INTEL_COREI7
34348 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34355 else
34362 else
34406 }
34407 }
34412 {
34416 }
34419 {
34421 /* For a C string literal the length includes the trailing NULL. */
34424 predicate_chain);
34425 }
34426 }
34428 /* Process feature name. */
34435 {
34436 /* Do not process "arch=" */
34438 {
34441 }
34443 {
34445 {
34447 {
34452 predicate_chain);
34453 }
34454 /* Find the maximum priority feature. */
34459 }
34460 }
34462 {
34466 }
34468 }
34472 {
34475 attrs_str);
34477 }
34479 {
34482 }
34485 }
34487 /* This compares the priority of target features in function DECL1
34488 and DECL2. It returns positive value if DECL1 is higher priority,
34489 negative value if DECL2 is higher priority and 0 if they are the
34490 same. */
34492 static int
34494 {
34499 }
34501 /* V1 and V2 point to function versions with different priorities
34502 based on the target ISA. This function compares their priorities. */
34504 static int
34506 {
34508 {
34509 tree version_decl;
34510 tree predicate_chain;
34517 }
34519 /* This function generates the dispatch function for
34520 multi-versioned functions. DISPATCH_DECL is the function which will
34521 contain the dispatch logic. FNDECLS are the function choices for
34522 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34523 in DISPATCH_DECL in which the dispatch code is generated. */
34525 static int
34529 {
34530 tree default_decl;
34531 gimple ifunc_cpu_init_stmt;
34532 gimple_seq gseq;
34534 tree ele;
34540 struct _function_version_info
34541 {
34542 tree version_decl;
34543 tree predicate_chain;
34551 /*fndecls_p is actually a vector. */
34554 /* At least one more version other than the default. */
34561 /* The first version in the vector is the default decl. */
34567 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34568 constructors, so explicity call __builtin_cpu_init here. */
34579 {
34583 /* Get attribute string, parse it and find the right predicate decl.
34584 The predicate function could be a lengthy combination of many
34585 features, like arch-type and various isa-variants. */
34596 actual_versions++;
34597 }
34599 /* Sort the versions according to descending order of dispatch priority. The
34600 priority is based on the ISA. This is not a perfect solution. There
34601 could still be ambiguity. If more than one function version is suitable
34602 to execute, which one should be dispatched? In future, allow the user
34603 to specify a dispatch priority next to the version. */
34613 /* dispatch default version at the end. */
34619 }
34621 /* Comparator function to be used in qsort routine to sort attribute
34622 specification strings to "target". */
34624 static int
34626 {
34630 }
34632 /* ARGLIST is the argument to target attribute. This function tokenizes
34633 the comma separated arguments, sorts them and returns a string which
34634 is a unique identifier for the comma separated arguments. It also
34635 replaces non-identifier characters "=,-" with "_". */
34639 {
34640 tree arg;
34649 {
34654 argnum++;
34657 argnum++;
34658 }
34663 {
34669 }
34671 /* Replace "=,-" with "_". */
34684 {
34686 i++;
34688 }
34695 {
34700 }
34705 }
34707 /* This function changes the assembler name for functions that are
34708 versions. If DECL is a function version and has a "target"
34709 attribute, it appends the attribute string to its assembler name. */
34711 static tree
34713 {
34714 tree version_attr;
34722 "Function versions cannot be marked as gnu_inline,"
34731 /* target attribute string cannot be NULL. */
34735 version_string
34746 /* Allow assembler name to be modified if already set. */
34754 }
34756 /* This function returns true if FN1 and FN2 are versions of the same function,
34757 that is, the target strings of the function decls are different. This assumes
34758 that FN1 and FN2 have the same signature. */
34760 static bool
34762 {
34774 /* At least one function decl should have the target attribute specified. */
34778 /* Diagnose missing target attribute if one of the decls is already
34779 multi-versioned. */
34781 {
34783 {
34785 {
34790 }
34793 fn2);
34796 /* Prevent diagnosing of the same error multiple times. */
34801 }
34803 }
34808 /* The sorted target strings must be different for fn1 and fn2
34809 to be versions. */
34812 else
34819 }
34821 static tree
34823 {
34824 /* For function version, add the target suffix to the assembler name. */
34828 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34830 #endif
34833 }
34835 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34836 is true, append the full path name of the source file. */
34840 {
34848 /* Get a unique name that can be used globally without any chances
34849 of collision at link time. */
34859 /* Use '.' to concatenate names as it is demangler friendly. */
34862 suffix);
34863 else
34867 }
34869 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34871 /* Make a dispatcher declaration for the multi-versioned function DECL.
34872 Calls to DECL function will be replaced with calls to the dispatcher
34873 by the front-end. Return the decl created. */
34875 static tree
34877 {
34878 tree func_decl;
34898 /* Mark this func as external, the resolver will flip it again if
34899 it gets generated. */
34901 /* This will be of type IFUNCs have to be externally visible. */
34905 }
34907 #endif
34909 /* Returns true if decl is multi-versioned and DECL is the default function,
34910 that is it is not tagged with target specific optimization. */
34912 static bool
34914 {
34923 }
34925 /* Make a dispatcher declaration for the multi-versioned function DECL.
34926 Calls to DECL function will be replaced with calls to the dispatcher
34927 by the front-end. Returns the decl of the dispatcher function. */
34929 static tree
34931 {
34953 /* Find the default version and make it the first node. */
34955 /* Go to the beginning of the chain. */
34960 {
34965 }
34967 /* If there is no default node, just return NULL. */
34971 /* Make default info the first node. */
34973 {
34980 }
34984 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34986 {
34991 /* Right now, the dispatching is done via ifunc. */
34997 dispatcher_version_info
35002 /* Set the dispatcher for all the versions. */
35005 {
35008 }
35009 }
35010 else
35011 #endif
35012 {
35014 "multiversioning needs ifunc which is not supported "
35016 }
35019 }
35021 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35022 it to CHAIN. */
35024 static tree
35026 {
35027 tree attr_name;
35028 tree attr_arg_name;
35029 tree attr_args;
35030 tree attr;
35037 }
35039 /* Make the resolver function decl to dispatch the versions of
35040 a multi-versioned function, DEFAULT_DECL. Create an
35041 empty basic block in the resolver and store the pointer in
35042 EMPTY_BB. Return the decl of the resolver function. */
35044 static tree
35048 {
35053 /* IFUNC's have to be globally visible. So, if the default_decl is
35054 not, then the name of the IFUNC should be made unique. */
35058 /* Append the filename to the resolver function if the versions are
35059 not externally visible. This is because the resolver function has
35060 to be externally visible for the loader to find it. So, appending
35061 the filename will prevent conflicts with a resolver function from
35062 another module which is based on the same version name. */
35065 /* The resolver function should return a (void *). */
35076 /* IFUNC resolvers have to be externally visible. */
35080 /* Resolver is not external, body is generated. */
35090 {
35091 /* In this case, each translation unit with a call to this
35092 versioned function will put out a resolver. Ensure it
35093 is comdat to keep just one copy. */
35096 }
35097 /* Build result decl and add to function_decl. */
35113 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35117 /* Create the alias for dispatch to resolver here. */
35118 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35122 }
35124 /* Generate the dispatching code body to dispatch multi-versioned function
35125 DECL. The target hook is called to process the "target" attributes and
35126 provide the code to dispatch the right function at run-time. NODE points
35127 to the dispatcher decl whose body will be created. */
35129 static tree
35131 {
35132 tree resolver_decl;
35133 basic_block empty_bb;
35134 tree default_ver_decl;
35150 /* The first version in the chain corresponds to the default version. */
35153 /* node is going to be an alias, so remove the finalized bit. */
35167 {
35169 /* Check for virtual functions here again, as by this time it should
35170 have been determined if this function needs a vtable index or
35171 not. This happens for methods in derived classes that override
35172 virtual methods in base classes but are not explicitly marked as
35173 virtual. */
35178 }
35184 }
35185 /* This builds the processor_model struct type defined in
35186 libgcc/config/i386/cpuinfo.c */
35188 static tree
35190 {
35197 /* The first 3 fields are unsigned int. */
35199 {
35205 }
35207 /* The last field is an array of unsigned integers of size one. */
35218 }
35220 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35222 static tree
35224 {
35225 tree new_decl;
35228 VAR_DECL,
35230 type);
35243 }
35245 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35246 into an integer defined in libgcc/config/i386/cpuinfo.c */
35248 static tree
35250 {
35256 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35257 enum processor_features
35258 {
35260 F_MMX,
35261 F_POPCNT,
35262 F_SSE,
35263 F_SSE2,
35264 F_SSE3,
35265 F_SSSE3,
35266 F_SSE4_1,
35267 F_SSE4_2,
35268 F_AVX,
35269 F_AVX2,
35270 F_SSE4_A,
35271 F_FMA4,
35272 F_XOP,
35273 F_FMA,
35274 F_AVX512F,
35275 F_MAX
35276 };
35278 /* These are the values for vendor types and cpu types and subtypes
35279 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35280 the corresponding start value. */
35281 enum processor_model
35282 {
35284 M_AMD,
35285 M_CPU_TYPE_START,
35286 M_INTEL_BONNELL,
35287 M_INTEL_CORE2,
35288 M_INTEL_COREI7,
35289 M_AMDFAM10H,
35290 M_AMDFAM15H,
35291 M_INTEL_SILVERMONT,
35292 M_INTEL_KNL,
35293 M_AMD_BTVER1,
35294 M_AMD_BTVER2,
35295 M_CPU_SUBTYPE_START,
35296 M_INTEL_COREI7_NEHALEM,
35297 M_INTEL_COREI7_WESTMERE,
35298 M_INTEL_COREI7_SANDYBRIDGE,
35299 M_AMDFAM10H_BARCELONA,
35300 M_AMDFAM10H_SHANGHAI,
35301 M_AMDFAM10H_ISTANBUL,
35302 M_AMDFAM15H_BDVER1,
35303 M_AMDFAM15H_BDVER2,
35304 M_AMDFAM15H_BDVER3,
35305 M_AMDFAM15H_BDVER4,
35306 M_INTEL_COREI7_IVYBRIDGE,
35307 M_INTEL_COREI7_HASWELL
35308 };
35310 static struct _arch_names_table
35311 {
35314 }
35316 {
35342 };
35344 static struct _isa_names_table
35345 {
35348 }
35350 {
35367 };
35381 {
35382 /* *args must be a expr that can contain other EXPRS leading to a
35383 STRING_CST. */
35385 {
35388 }
35390 }
35395 {
35396 tree ref;
35397 tree field;
35398 tree final;
35401 unsigned int NUM_ARCH_NAMES
35410 {
35414 }
35419 /* CPU types are stored in the next field. */
35422 {
35425 }
35427 /* CPU subtypes are stored in the next field. */
35429 {
35432 }
35434 /* Get the appropriate field in __cpu_model. */
35438 /* Check the value. */
35442 }
35444 {
35445 tree ref;
35446 tree array_elt;
35447 tree field;
35448 tree final;
35451 unsigned int NUM_ISA_NAMES
35460 {
35464 }
35467 /* Get the last field, which is __cpu_features. */
35471 /* Get the appropriate field: __cpu_model.__cpu_features */
35475 /* Access the 0th element of __cpu_features array. */
35480 /* Return __cpu_model.__cpu_features[0] & field_val */
35484 }
35486 }
35488 static tree
35491 {
35493 {
35498 {
35501 }
35502 }
35504 #ifdef SUBTARGET_FOLD_BUILTIN
35506 #endif
35509 }
35511 /* Make builtins to detect cpu type and features supported. NAME is
35512 the builtin name, CODE is the builtin code, and FTYPE is the function
35513 type of the builtin. */
35515 static void
35518 {
35519 tree decl;
35520 tree type;
35528 }
35530 /* Make builtins to get CPU type and features supported. The created
35531 builtins are :
35533 __builtin_cpu_init (), to detect cpu type and features,
35534 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35535 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35536 */
35538 static void
35540 {
35547 }
35549 /* Internal method for ix86_init_builtins. */
35551 static void
35553 {
35565 sysv_va_ref =
35568 fnvoid_va_end_ms =
35570 fnvoid_va_start_ms =
35572 fnvoid_va_end_sysv =
35574 fnvoid_va_start_sysv =
35576 NULL_TREE);
35577 fnvoid_va_copy_ms =
35579 NULL_TREE);
35580 fnvoid_va_copy_sysv =
35596 }
35598 static void
35600 {
35603 /* The __float80 type. */
35606 {
35607 /* The __float80 type. */
35612 }
35615 /* The __float128 type. */
35621 /* This macro is built by i386-builtin-types.awk. */
35622 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35623 }
35625 static void
35627 {
35628 tree t;
35632 /* Builtins to get CPU type and features. */
35635 /* TFmode support builtins. */
35641 /* We will expand them to normal call if SSE isn't available since
35642 they are used by libgcc. */
35662 #ifdef SUBTARGET_INIT_BUILTINS
35663 SUBTARGET_INIT_BUILTINS;
35664 #endif
35665 }
35667 /* Return the ix86 builtin for CODE. */
35669 static tree
35671 {
35676 }
35678 /* Errors in the source file can cause expand_expr to return const0_rtx
35679 where we expect a vector. To avoid crashing, use one of the vector
35680 clear instructions. */
35681 static rtx
35683 {
35687 }
35689 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35691 static rtx
35693 {
35694 rtx pat;
35714 {
35718 }
35732 }
35734 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35736 static rtx
35740 {
35741 rtx pat;
35749 rtx op;
35750 machine_mode mode;
35756 {
35836 }
35846 {
35853 {
35855 {
35858 {
35876 xop_rotl:
35878 {
35881 gcc_checking_assert
35883 }
35884 else
35885 {
35886 gcc_checking_assert
35897 }
35901 }
35902 }
35903 }
35904 else
35905 {
35906 non_constant:
35910 /* If we aren't optimizing, only allow one memory operand to be
35911 generated. */
35913 num_memory++;
35921 }
35925 }
35928 {
35939 else
35940 {
35946 }
35959 }
35966 }
35968 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
35969 insns with vec_merge. */
35971 static rtx
35973 rtx target)
35974 {
35975 rtx pat;
36002 }
36004 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36006 static rtx
36009 {
36010 rtx pat;
36015 rtx op2;
36026 /* Swap operands if we have a comparison that isn't available in
36027 hardware. */
36029 {
36034 }
36054 }
36056 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36058 static rtx
36060 rtx target)
36061 {
36062 rtx pat;
36076 /* Swap operands if we have a comparison that isn't available in
36077 hardware. */
36100 const0_rtx)));
36103 }
36105 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36107 static rtx
36109 rtx target)
36110 {
36111 rtx pat;
36136 }
36138 static rtx
36141 {
36142 rtx pat;
36147 rtx op2;
36174 }
36176 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36178 static rtx
36180 rtx target)
36181 {
36182 rtx pat;
36215 const0_rtx)));
36218 }
36220 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36222 static rtx
36225 {
36226 rtx pat;
36264 {
36267 }
36270 {
36279 }
36281 {
36290 }
36291 else
36292 {
36299 }
36307 {
36312 emit_insn
36316 FLAGS_REG),
36317 const0_rtx)));
36319 }
36320 else
36322 }
36325 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36327 static rtx
36330 {
36331 rtx pat;
36359 {
36362 }
36365 {
36374 }
36376 {
36385 }
36386 else
36387 {
36394 }
36402 {
36407 emit_insn
36411 FLAGS_REG),
36412 const0_rtx)));
36414 }
36415 else
36417 }
36419 /* Subroutine of ix86_expand_builtin to take care of insns with
36420 variable number of operands. */
36422 static rtx
36425 {
36431 struct
36432 {
36433 rtx op;
36434 machine_mode mode;
36445 {
37155 }
37160 {
37163 }
37166 {
37173 }
37174 else
37175 {
37178 }
37181 {
37188 {
37189 /* SIMD shift insns take either an 8-bit immediate or
37190 register as count. But builtin functions take int as
37191 count. If count doesn't match, we put it in register. */
37193 {
37197 }
37198 }
37201 {
37204 {
37313 {
37317 {
37320 }
37326 }
37328 }
37329 }
37330 else
37331 {
37335 /* If we aren't optimizing, only allow one memory operand to
37336 be generated. */
37338 num_memory++;
37341 {
37344 }
37345 else
37346 {
37349 }
37350 }
37354 }
37357 {
37382 }
37389 }
37391 /* Transform pattern of following layout:
37392 (parallel [
37393 set (A B)
37394 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37395 ])
37396 into:
37397 (set (A B))
37399 Or:
37400 (parallel [ A B
37401 ...
37402 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37403 ...
37404 ])
37405 into:
37406 (parallel [ A B ... ]) */
37408 static rtx
37410 {
37417 {
37426 }
37427 else
37428 {
37434 {
37439 }
37441 /* No more than 1 occurence was removed. */
37445 }
37446 }
37448 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37449 with rounding. */
37450 static rtx
37453 {
37470 /* See avxintrin.h for values. */
37472 {
37476 };
37478 {
37483 };
37486 {
37489 }
37491 {
37494 }
37497 {
37500 }
37523 ? CODE_FOR_sse_ucomi_round
37530 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37532 {
37538 }
37539 else
37540 {
37543 }
37549 set_dst,
37550 const0_rtx)));
37553 }
37555 static rtx
37558 {
37559 rtx pat;
37561 struct
37562 {
37563 rtx op;
37564 machine_mode mode;
37573 {
37656 }
37666 {
37673 {
37675 {
37677 {
37693 }
37694 }
37695 }
37697 {
37699 {
37702 }
37704 /* If there is no rounding use normal version of the pattern. */
37707 }
37708 else
37709 {
37714 {
37717 }
37718 else
37719 {
37722 }
37723 }
37727 }
37730 {
37755 }
37765 }
37767 /* Subroutine of ix86_expand_builtin to take care of special insns
37768 with variable number of operands. */
37770 static rtx
37773 {
37774 tree arg;
37778 struct
37779 {
37780 rtx op;
37781 machine_mode mode;
37790 {
37830 {
37838 }
37857 /* Reserve memory operand for target. */
37860 {
37861 /* These builtins and instructions require the memory
37862 to be properly aligned. */
37881 }
37910 {
37911 /* These builtins and instructions require the memory
37912 to be properly aligned. */
37929 }
37930 /* FALLTHRU */
37968 /* Reserve memory operand for target. */
37995 {
37996 /* These builtins and instructions require the memory
37997 to be properly aligned. */
38020 }
38033 }
38038 {
38043 {
38046 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38047 on it. Try to improve it using get_pointer_alignment,
38048 and if the special builtin is one that requires strict
38049 mode alignment, also from it's GET_MODE_ALIGNMENT.
38050 Failure to do so could lead to ix86_legitimate_combined_insn
38051 rejecting all changes to such insns. */
38057 }
38058 else
38061 }
38062 else
38063 {
38070 }
38073 {
38082 {
38084 {
38090 else
38093 }
38094 }
38095 else
38096 {
38098 {
38099 /* This must be the memory operand. */
38102 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38103 on it. Try to improve it using get_pointer_alignment,
38104 and if the special builtin is one that requires strict
38105 mode alignment, also from it's GET_MODE_ALIGNMENT.
38106 Failure to do so could lead to ix86_legitimate_combined_insn
38107 rejecting all changes to such insns. */
38113 }
38114 else
38115 {
38116 /* This must be register. */
38122 else
38123 {
38126 }
38127 }
38128 }
38132 }
38135 {
38150 }
38156 }
38158 /* Return the integer constant in ARG. Constrain it to be in the range
38159 of the subparts of VEC_TYPE; issue an error if not. */
38161 static int
38163 {
38168 {
38171 }
38174 }
38176 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38177 ix86_expand_vector_init. We DO have language-level syntax for this, in
38178 the form of (type){ init-list }. Except that since we can't place emms
38179 instructions from inside the compiler, we can't allow the use of MMX
38180 registers unless the user explicitly asks for it. So we do *not* define
38181 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38182 we have builtins invoked by mmintrin.h that gives us license to emit
38183 these sorts of instructions. */
38185 static rtx
38187 {
38197 {
38200 }
38207 }
38209 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38210 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38211 had a language-level syntax for referencing vector elements. */
38213 static rtx
38215 {
38219 rtx op0;
38239 }
38241 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38242 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38243 a language-level syntax for referencing vector elements. */
38245 static rtx
38247 {
38271 /* OP0 is the source of these builtin functions and shouldn't be
38272 modified. Create a copy, use it and return it as target. */
38278 }
38280 /* Emit conditional move of SRC to DST with condition
38281 OP1 CODE OP2. */
38282 static void
38284 {
38285 rtx t;
38288 {
38293 }
38294 else
38295 {
38301 }
38302 }
38304 /* Choose max of DST and SRC and put it to DST. */
38305 static void
38307 {
38309 }
38311 /* Expand an expression EXP that calls a built-in function,
38312 with result going to TARGET if that's convenient
38313 (and in mode MODE if that's convenient).
38314 SUBTARGET may be used as the target for computing one of EXP's operands.
38315 IGNORE is nonzero if the value is to be ignored. */
38317 static rtx
38320 {
38330 /* For CPU builtins that can be folded, fold first and expand the fold. */
38332 {
38334 {
38335 /* Make it call __cpu_indicator_init in libgcc. */
38341 }
38344 {
38349 }
38350 }
38352 /* Determine whether the builtin function is available under the current ISA.
38353 Originally the builtin was not created if it wasn't applicable to the
38354 current ISA based on the command line switches. With function specific
38355 options, we need to check in the context of the function making the call
38356 whether it is supported. */
38359 {
38365 else
38366 {
38370 }
38372 }
38375 {
38393 /* Builtin arg1 is size of block but instruction op1 should
38394 be (size - 1). */
38485 /* If no bounds were specified for returned value,
38486 then use INIT bounds. It usually happens when
38487 some built-in function is expanded. */
38489 {
38498 }
38504 {
38507 /* Return value and lb. */
38509 /* Bounds. */
38511 /* Size. */
38518 /* Size was passed but we need to use (size - 1) as for bndmk. */
38522 /* Add LB to size and inverse to get UB. */
38532 /* We need to move bounds to memory before any computations. */
38535 else
38536 {
38539 }
38541 /* Generate mem expression to be used for access to LB and UB. */
38547 /* Compute LB. */
38552 /* Compute UB. UB is stored in 1's complement form. Therefore
38553 we also use max here. */
38562 }
38565 {
38583 /* Put first bounds to temporaries. */
38587 {
38591 }
38592 else
38593 {
38597 }
38599 /* Put second bounds to temporaries. */
38603 {
38607 }
38608 else
38609 {
38613 }
38615 /* Compute LB. */
38619 /* Compute UB. UB is stored in 1's complement form. Therefore
38620 we also use max here. */
38627 }
38630 {
38631 tree name;
38632 rtx symbol;
38650 }
38653 {
38664 /* We need to move bounds to memory first. */
38667 else
38668 {
38671 }
38673 /* Generate mem expression to access LB and load it. */
38678 }
38681 {
38692 /* We need to move bounds to memory first. */
38695 else
38696 {
38699 }
38701 /* Generate mem expression to access UB. */
38704 /* We need to inverse all bits of UB. */
38711 }
38716 ? CODE_FOR_mmx_maskmovq
38718 /* Note the arg order is different from the operand order. */
38839 {
38840 REAL_VALUE_TYPE inf;
38841 rtx tmp;
38853 }
38863 {
38869 insn = (TARGET_64BIT
38873 }
38875 {
38876 insn = (TARGET_64BIT
38880 }
38881 else
38882 {
38885 insn = (TARGET_64BIT
38893 {
38896 }
38898 }
38901 {
38902 /* mode is VOIDmode if __builtin_rd* has been called
38903 without lhs. */
38907 }
38910 {
38915 }
38928 {
38949 }
38955 {
38958 }
38984 {
38987 }
38993 {
38997 {
39036 }
39041 }
39042 else
39043 {
39045 {
39066 }
39068 }
39098 ? CODE_FOR_tbm_bextri_si
39101 {
39104 }
39105 else
39106 {
39115 }
39131 rdrand_step:
39138 {
39141 }
39147 /* Emit SImode conditional move. */
39149 {
39152 }
39155 else
39163 const0_rtx);
39182 rdseed_step:
39189 {
39192 }
39198 const0_rtx);
39227 addcarryx:
39235 /* Generate CF from input operand. */
39240 /* Gen ADCX instruction to compute X+Y+CF. */
39255 /* Store the result. */
39258 {
39261 }
39264 /* Return current CF value. */
39306 kortest:
39320 /* Emit kortest. */
39322 /* And use setcc to return result from flags. */
39580 gather_gen:
39581 rtx half;
39594 /* Note the arg order is different from the operand order. */
39605 else
39609 {
39633 else
39640 {
39645 }
39654 else
39661 {
39666 }
39670 }
39672 /* Force memory operand only with base register here. But we
39673 don't want to do it on memory operand for other builtin
39674 functions. */
39684 {
39687 }
39688 else
39689 {
39692 }
39694 {
39697 }
39699 /* Optimize. If mask is known to have all high bits set,
39700 replace op0 with pc_rtx to signal that the instruction
39701 overwrites the whole destination and doesn't use its
39702 previous contents. */
39704 {
39706 {
39709 }
39711 {
39714 {
39718 negative++;
39721 negative++;
39722 }
39725 }
39728 {
39729 /* Recognize also when mask is like:
39730 __v2df src = _mm_setzero_pd ();
39731 __v2df mask = _mm_cmpeq_pd (src, src);
39732 or
39733 __v8sf src = _mm256_setzero_ps ();
39734 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39735 as that is a cheaper way to load all ones into
39736 a register than having to load a constant from
39737 memory. */
39740 {
39745 {
39752 /* FALLTHRU */
39762 }
39763 }
39764 }
39765 }
39773 {
39799 }
39802 scatter_gen:
39818 /* Force memory operand only with base register here. But we
39819 don't want to do it on memory operand for other builtin
39820 functions. */
39827 {
39830 }
39831 else
39832 {
39835 }
39844 {
39847 }
39856 vec_prefetch_gen:
39874 {
39877 }
39879 {
39882 }
39887 /* Force memory operand only with base register here. But we
39888 don't want to do it on memory operand for other builtin
39889 functions. */
39896 {
39899 }
39902 {
39905 }
39921 {
39924 }
39930 }
39943 {
39947 /* Emit a normal call if SSE isn't available. */
39951 }
39980 }
39982 /* This returns the target-specific builtin with code CODE if
39983 current_function_decl has visibility on this builtin, which is checked
39984 using isa flags. Returns NULL_TREE otherwise. */
39987 {
39991 /* Determine the isa flags of current_function_decl. */
40003 else
40005 }
40007 /* Return function decl for target specific builtin
40008 for given MPX builtin passed i FCODE. */
40009 static tree
40011 {
40013 {
40049 }
40052 }
40054 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40056 Return an address to be used to load/store bounds for pointer
40057 passed in SLOT.
40059 SLOT_NO is an integer constant holding number of a target
40060 dependent special slot to be used in case SLOT is not a memory.
40062 SPECIAL_BASE is a pointer to be used as a base of fake address
40063 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40064 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40066 static rtx
40068 {
40071 /* NULL slot means we pass bounds for pointer not passed to the
40072 function at all. Register slot means we pass pointer in a
40073 register. In both these cases bounds are passed via Bounds
40074 Table. Since we do not have actual pointer stored in memory,
40075 we have to use fake addresses to access Bounds Table. We
40076 start with (special_base - sizeof (void*)) and decrease this
40077 address by pointer size to get addresses for other slots. */
40079 {
40083 }
40084 /* If pointer is passed in a memory then its address is used to
40085 access Bounds Table. */
40087 {
40091 }
40092 else
40096 }
40098 /* Expand pass uses this hook to load bounds for function parameter
40099 PTR passed in SLOT in case its bounds are not passed in a register.
40101 If SLOT is a memory, then bounds are loaded as for regular pointer
40102 loaded from memory. PTR may be NULL in case SLOT is a memory.
40103 In such case value of PTR (if required) may be loaded from SLOT.
40105 If SLOT is NULL or a register then SLOT_NO is an integer constant
40106 holding number of the target dependent special slot which should be
40107 used to obtain bounds.
40109 Return loaded bounds. */
40111 static rtx
40113 {
40115 rtx addr;
40117 /* Get address to be used to access Bounds Table. Special slots start
40118 at the location of return address of the current function. */
40121 /* Load pointer value from a memory if we don't have it. */
40123 {
40126 }
40133 }
40135 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40136 passed in SLOT in case BOUNDS are not passed in a register.
40138 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40139 stored in memory. PTR may be NULL in case SLOT is a memory.
40140 In such case value of PTR (if required) may be loaded from SLOT.
40142 If SLOT is NULL or a register then SLOT_NO is an integer constant
40143 holding number of the target dependent special slot which should be
40144 used to store BOUNDS. */
40146 static void
40148 {
40149 rtx addr;
40151 /* Get address to be used to access Bounds Table. Special slots start
40152 at the location of return address of a called function. */
40155 /* Load pointer value from a memory if we don't have it. */
40157 {
40160 }
40169 }
40171 /* Load and return bounds returned by function in SLOT. */
40173 static rtx
40175 {
40176 rtx res;
40183 }
40185 /* Store BOUNDS returned by function into SLOT. */
40187 static void
40189 {
40192 }
40194 /* Returns a function decl for a vectorized version of the builtin function
40195 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40196 if it is not available. */
40198 static tree
40200 tree type_in)
40201 {
40217 {
40220 {
40227 }
40232 {
40235 }
40240 {
40247 }
40253 /* The round insn does not trap on denormals. */
40258 {
40265 }
40271 /* The round insn does not trap on denormals. */
40276 {
40281 }
40287 /* The round insn does not trap on denormals. */
40292 {
40299 }
40305 /* The round insn does not trap on denormals. */
40310 {
40315 }
40322 {
40327 }
40334 {
40339 }
40345 /* The round insn does not trap on denormals. */
40350 {
40357 }
40363 /* The round insn does not trap on denormals. */
40368 {
40373 }
40378 {
40385 }
40390 {
40397 }
40401 /* The round insn does not trap on denormals. */
40406 {
40411 }
40415 /* The round insn does not trap on denormals. */
40420 {
40425 }
40429 /* The round insn does not trap on denormals. */
40434 {
40439 }
40443 /* The round insn does not trap on denormals. */
40448 {
40453 }
40457 /* The round insn does not trap on denormals. */
40462 {
40467 }
40471 /* The round insn does not trap on denormals. */
40476 {
40481 }
40485 /* The round insn does not trap on denormals. */
40490 {
40495 }
40499 /* The round insn does not trap on denormals. */
40504 {
40509 }
40513 /* The round insn does not trap on denormals. */
40518 {
40523 }
40527 /* The round insn does not trap on denormals. */
40532 {
40537 }
40542 {
40547 }
40552 {
40557 }
40562 }
40564 /* Dispatch to a handler for a vectorization library. */
40567 type_in);
40570 }
40572 /* Handler for an SVML-style interface to
40573 a library with vectorized intrinsics. */
40575 static tree
40577 {
40585 /* The SVML is suitable for unsafe math only. */
40598 {
40645 }
40654 {
40657 }
40658 else
40661 /* Convert to uppercase. */
40666 args;
40668 arity++;
40672 else
40675 /* Build a function declaration for the vectorized function. */
40684 }
40686 /* Handler for an ACML-style interface to
40687 a library with vectorized intrinsics. */
40689 static tree
40691 {
40699 /* The ACML is 64bits only and suitable for unsafe math only as
40700 it does not correctly support parts of IEEE with the required
40701 precision such as denormals. */
40715 {
40745 }
40752 args;
40754 arity++;
40758 else
40761 /* Build a function declaration for the vectorized function. */
40770 }
40772 /* Returns a decl of a function that implements gather load with
40773 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40774 Return NULL_TREE if it is not available. */
40776 static tree
40779 {
40795 /* v*gather* insn sign extends index to pointer mode. */
40807 {
40811 else
40817 else
40823 else
40829 else
40835 else
40841 else
40847 else
40853 else
40859 else
40865 else
40871 else
40877 else
40882 }
40885 }
40887 /* Returns a code for a target-specific builtin that implements
40888 reciprocal of the function, or NULL_TREE if not available. */
40890 static tree
40892 {
40899 /* Machine dependent builtins. */
40901 {
40902 /* Vectorized version of sqrt to rsqrt conversion. */
40911 }
40912 else
40913 /* Normal builtins. */
40915 {
40916 /* Sqrt to rsqrt conversion. */
40922 }
40923 }
40924 \f
40925 /* Helper for avx_vpermilps256_operand et al. This is also used by
40926 the expansion functions to turn the parallel back into a mask.
40927 The return value is 0 for no match and the imm8+1 for a match. */
40929 int
40931 {
40939 /* Validate that all of the elements are constants, and not totally
40940 out of range. Copy the data into an integral array to make the
40941 subsequent checks easier. */
40943 {
40953 }
40956 {
40958 /* In the 512-bit DFmode case, we can only move elements within
40959 a 128-bit lane. First fill the second part of the mask,
40960 then fallthru. */
40962 {
40966 }
40968 {
40972 }
40973 /* FALLTHRU */
40976 /* In the 256-bit DFmode case, we can only move elements within
40977 a 128-bit lane. */
40979 {
40983 }
40985 {
40989 }
40993 /* In 512 bit SFmode case, permutation in the upper 256 bits
40994 must mirror the permutation in the lower 256-bits. */
40998 /* FALLTHRU */
41001 /* In 256 bit SFmode case, we have full freedom of
41002 movement within the low 128-bit lane, but the high 128-bit
41003 lane must mirror the exact same pattern. */
41008 /* FALLTHRU */
41012 /* In the 128-bit case, we've full freedom in the placement of
41013 the elements from the source operand. */
41020 }
41022 /* Make sure success has a non-zero value by adding one. */
41024 }
41026 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41027 the expansion functions to turn the parallel back into a mask.
41028 The return value is 0 for no match and the imm8+1 for a match. */
41030 int
41032 {
41040 /* Validate that all of the elements are constants, and not totally
41041 out of range. Copy the data into an integral array to make the
41042 subsequent checks easier. */
41044 {
41054 }
41056 /* Validate that the halves of the permute are halves. */
41064 /* Reconstruct the mask. */
41066 {
41072 }
41074 /* Make sure success has a non-zero value by adding one. */
41076 }
41077 \f
41078 /* Return a register priority for hard reg REGNO. */
41079 static int
41081 {
41082 /* ebp and r13 as the base always wants a displacement, r12 as the
41083 base always wants an index. So discourage their usage in an
41084 address. */
41089 /* New x86-64 int registers result in bigger code size. Discourage
41090 them. */
41093 /* New x86-64 SSE registers result in bigger code size. Discourage
41094 them. */
41097 /* Usage of AX register results in smaller code. Prefer it. */
41101 }
41103 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41105 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41106 QImode must go into class Q_REGS.
41107 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41108 movdf to do mem-to-mem moves through integer regs. */
41110 static reg_class_t
41112 {
41115 /* We're only allowed to return a subclass of CLASS. Many of the
41116 following checks fail for NO_REGS, so eliminate that early. */
41120 /* All classes can load zeros. */
41124 /* Force constants into memory if we are loading a (nonzero) constant into
41125 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41126 instructions to load from a constant. */
41133 /* Prefer SSE regs only, if we can use them for math. */
41137 /* Floating-point constants need more complex checks. */
41139 {
41140 /* General regs can load everything. */
41144 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41145 zero above. We only want to wind up preferring 80387 registers if
41146 we plan on doing computation with them. */
41149 {
41150 /* Limit class to non-sse. */
41159 }
41162 }
41164 /* Generally when we see PLUS here, it's the function invariant
41165 (plus soft-fp const_int). Which can only be computed into general
41166 regs. */
41170 /* QImode constants are easy to load, but non-constant QImode data
41171 must go into Q_REGS. */
41173 {
41179 }
41182 }
41184 /* Discourage putting floating-point values in SSE registers unless
41185 SSE math is being used, and likewise for the 387 registers. */
41186 static reg_class_t
41188 {
41191 /* Restrict the output reload class to the register bank that we are doing
41192 math on. If we would like not to return a subset of CLASS, reject this
41193 alternative: if reload cannot do this, it will still use its choice. */
41199 {
41204 else
41206 }
41209 }
41211 static reg_class_t
41214 {
41215 /* Double-word spills from general registers to non-offsettable memory
41216 references (zero-extended addresses) require special handling. */
41222 {
41224 ? CODE_FOR_reload_noff_load
41226 /* Add the cost of moving address to a temporary. */
41230 }
41232 /* QImode spills from non-QI registers require
41233 intermediate register on 32bit targets. */
41239 {
41244 else
41250 /* Return Q_REGS if the operand is in memory. */
41253 }
41255 /* This condition handles corner case where an expression involving
41256 pointers gets vectorized. We're trying to use the address of a
41257 stack slot as a vector initializer.
41259 (set (reg:V2DI 74 [ vect_cst_.2 ])
41260 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41262 Eventually frame gets turned into sp+offset like this:
41264 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41265 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41266 (const_int 392 [0x188]))))
41268 That later gets turned into:
41270 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41271 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41272 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41274 We'll have the following reload recorded:
41276 Reload 0: reload_in (DI) =
41277 (plus:DI (reg/f:DI 7 sp)
41278 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41279 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41280 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41281 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41282 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41283 reload_reg_rtx: (reg:V2DI 22 xmm1)
41285 Which isn't going to work since SSE instructions can't handle scalar
41286 additions. Returning GENERAL_REGS forces the addition into integer
41287 register and reload can handle subsequent reloads without problems. */
41295 }
41297 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41299 static bool
41301 {
41303 {
41319 }
41322 }
41324 /* If we are copying between general and FP registers, we need a memory
41325 location. The same is true for SSE and MMX registers.
41327 To optimize register_move_cost performance, allow inline variant.
41329 The macro can't work reliably when one of the CLASSES is class containing
41330 registers from multiple units (SSE, MMX, integer). We avoid this by never
41331 combining those units in single alternative in the machine description.
41332 Ensure that this constraint holds to avoid unexpected surprises.
41334 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41335 enforce these sanity checks. */
41340 {
41349 {
41352 }
41357 /* Between mask and general, we have moves no larger than word size. */
41362 /* ??? This is a lie. We do have moves between mmx/general, and for
41363 mmx/sse2. But by saying we need secondary memory we discourage the
41364 register allocator from using the mmx registers unless needed. */
41369 {
41370 /* SSE1 doesn't have any direct moves from other classes. */
41374 /* If the target says that inter-unit moves are more expensive
41375 than moving through memory, then don't generate them. */
41380 /* Between SSE and general, we have moves no larger than word size. */
41383 }
41386 }
41388 bool
41391 {
41393 }
41395 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41397 On the 80386, this is the size of MODE in words,
41398 except in the FP regs, where a single reg is always enough. */
41400 static unsigned char
41402 {
41404 {
41409 else
41411 }
41412 else
41413 {
41416 else
41418 }
41419 }
41421 /* Return true if the registers in CLASS cannot represent the change from
41422 modes FROM to TO. */
41424 bool
41427 {
41431 /* x87 registers can't do subreg at all, as all values are reformatted
41432 to extended precision. */
41437 {
41438 /* Vector registers do not support QI or HImode loads. If we don't
41439 disallow a change to these modes, reload will assume it's ok to
41440 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41441 the vec_dupv4hi pattern. */
41444 }
41447 }
41449 /* Return the cost of moving data of mode M between a
41450 register and memory. A value of 2 is the default; this cost is
41451 relative to those in `REGISTER_MOVE_COST'.
41453 This function is used extensively by register_move_cost that is used to
41454 build tables at startup. Make it inline in this case.
41455 When IN is 2, return maximum of in and out move cost.
41457 If moving between registers and memory is more expensive than
41458 between two registers, you should define this macro to express the
41459 relative cost.
41461 Model also increased moving costs of QImode registers in non
41462 Q_REGS classes.
41463 */
41467 {
41470 {
41473 {
41485 }
41489 }
41491 {
41494 {
41506 }
41510 }
41512 {
41515 {
41524 }
41528 }
41530 {
41533 {
41539 else
41544 }
41545 else
41546 {
41551 else
41553 }
41560 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41567 else
41571 }
41572 }
41574 static int
41577 {
41579 }
41582 /* Return the cost of moving data from a register in class CLASS1 to
41583 one in class CLASS2.
41585 It is not required that the cost always equal 2 when FROM is the same as TO;
41586 on some machines it is expensive to move between registers if they are not
41587 general registers. */
41589 static int
41591 reg_class_t class2_i)
41592 {
41596 /* In case we require secondary memory, compute cost of the store followed
41597 by load. In order to avoid bad register allocation choices, we need
41598 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41601 {
41607 /* In case of copying from general_purpose_register we may emit multiple
41608 stores followed by single load causing memory size mismatch stall.
41609 Count this as arbitrarily high cost of 20. */
41614 /* In the case of FP/MMX moves, the registers actually overlap, and we
41615 have to switch modes in order to treat them differently. */
41621 }
41623 /* Moves between SSE/MMX and integer unit are expensive. */
41627 /* ??? By keeping returned value relatively high, we limit the number
41628 of moves between integer and MMX/SSE registers for all targets.
41629 Additionally, high value prevents problem with x86_modes_tieable_p(),
41630 where integer modes in MMX/SSE registers are not tieable
41631 because of missing QImode and HImode moves to, from or between
41632 MMX/SSE registers. */
41642 }
41644 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41645 MODE. */
41647 bool
41649 {
41650 /* Flags and only flags can only hold CCmode values. */
41666 {
41667 /* We implement the move patterns for all vector modes into and
41668 out of SSE registers, even when no operation instructions
41669 are available. */
41671 /* For AVX-512 we allow, regardless of regno:
41672 - XI mode
41673 - any of 512-bit wide vector mode
41674 - any scalar mode. */
41681 /* TODO check for QI/HI scalars. */
41682 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41690 /* xmm16-xmm31 are only available for AVX-512. */
41694 /* OImode and AVX modes are available only when AVX is enabled. */
41701 }
41703 {
41704 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41705 so if the register is available at all, then we can move data of
41706 the given mode into or out of it. */
41709 }
41712 {
41713 /* Take care for QImode values - they can be in non-QI regs,
41714 but then they do cause partial register stalls. */
41719 /* LRA checks if the hard register is OK for the given mode.
41720 QImode values can live in non-QI regs, so we allow all
41721 registers here. */
41725 }
41726 /* We handle both integer and floats in the general purpose registers. */
41733 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41734 on to use that value in smaller contexts, this can easily force a
41735 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41736 supporting DImode, allow it. */
41741 }
41743 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41744 tieable integer mode. */
41746 static bool
41748 {
41750 {
41763 }
41764 }
41766 /* Return true if MODE1 is accessible in a register that can hold MODE2
41767 without copying. That is, all register classes that can hold MODE2
41768 can also hold MODE1. */
41770 bool
41772 {
41780 /* MODE2 being XFmode implies fp stack or general regs, which means we
41781 can tie any smaller floating point modes to it. Note that we do not
41782 tie this with TFmode. */
41786 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41787 that we can tie it with SFmode. */
41791 /* If MODE2 is only appropriate for an SSE register, then tie with
41792 any other mode acceptable to SSE registers. */
41802 /* If MODE2 is appropriate for an MMX register, then tie
41803 with any other mode acceptable to MMX registers. */
41810 }
41812 /* Return the cost of moving between two registers of mode MODE. */
41814 static int
41816 {
41820 {
41852 }
41854 /* Return the cost of moving between two registers of mode MODE,
41855 assuming that the move will be in pieces of at most UNITS bytes. */
41857 }
41859 /* Compute a (partial) cost for rtx X. Return true if the complete
41860 cost has been computed, and false if subexpressions should be
41861 scanned. In either case, *TOTAL contains the cost result. */
41863 static bool
41866 {
41867 rtx mask;
41874 {
41878 {
41881 }
41893 && !(TARGET_64BIT
41898 else
41904 {
41907 }
41909 {
41919 }
41921 {
41924 {
41933 }
41934 }
41935 /* Fall back to (MEM (SYMBOL_REF)), since that's where
41936 it'll probably end up. Add a penalty for size. */
41943 /* The zero extensions is often completely free on x86_64, so make
41944 it as cheap as possible. */
41950 else
41962 {
41965 {
41968 }
41971 {
41974 }
41975 }
41976 /* FALLTHRU */
41983 {
41984 /* ??? Should be SSE vector operation cost. */
41985 /* At least for published AMD latencies, this really is the same
41986 as the latency for a simple fpu operation like fabs. */
41987 /* V*QImode is emulated with 1-11 insns. */
41989 {
41992 {
41993 /* For XOP we use vpshab, which requires a broadcast of the
41994 value to the variable shift insn. For constants this
41995 means a V16Q const in mem; even when we can perform the
41996 shift with one insn set the cost to prefer paddb. */
41998 {
42003 }
42005 }
42009 }
42010 else
42012 }
42014 {
42016 {
42019 else
42021 }
42022 else
42023 {
42026 else
42028 }
42029 }
42030 else
42031 {
42036 {
42037 /* Return the cost after shift-and truncation. */
42040 }
42041 else
42043 }
42047 {
42048 rtx sub;
42053 /* ??? SSE scalar/vector cost should be used here. */
42054 /* ??? Bald assumption that fma has the same cost as fmul. */
42058 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42069 }
42073 {
42074 /* ??? SSE scalar cost should be used here. */
42077 }
42079 {
42082 }
42084 {
42085 /* ??? SSE vector cost should be used here. */
42088 }
42090 {
42091 /* V*QImode is emulated with 7-13 insns. */
42093 {
42100 }
42101 /* V*DImode is emulated with 5-8 insns. */
42103 {
42106 else
42108 }
42109 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42110 insns, including two PMULUDQ. */
42113 else
42116 }
42117 else
42118 {
42123 {
42126 nbits++;
42127 }
42128 else
42129 /* This is arbitrary. */
42132 /* Compute costs correctly for widening multiplication. */
42136 {
42143 {
42147 else
42149 }
42153 }
42161 }
42168 /* ??? SSE cost should be used here. */
42173 /* ??? SSE vector cost should be used here. */
42175 else
42182 {
42187 {
42190 {
42198 }
42199 }
42202 {
42205 {
42211 }
42212 }
42214 {
42222 }
42223 }
42224 /* FALLTHRU */
42228 {
42229 /* ??? SSE cost should be used here. */
42232 }
42234 {
42237 }
42239 {
42240 /* ??? SSE vector cost should be used here. */
42243 }
42244 /* FALLTHRU */
42251 {
42258 }
42259 /* FALLTHRU */
42263 {
42264 /* ??? SSE cost should be used here. */
42267 }
42269 {
42272 }
42274 {
42275 /* ??? SSE vector cost should be used here. */
42278 }
42279 /* FALLTHRU */
42283 {
42284 /* ??? Should be SSE vector operation cost. */
42285 /* At least for published AMD latencies, this really is the same
42286 as the latency for a simple fpu operation like fabs. */
42288 }
42291 else
42300 {
42301 /* This kind of construct is implemented using test[bwl].
42302 Treat it as if we had an AND. */
42307 }
42317 /* ??? SSE cost should be used here. */
42322 /* ??? SSE vector cost should be used here. */
42328 /* ??? SSE cost should be used here. */
42333 /* ??? SSE vector cost should be used here. */
42345 /* ??? Assume all of these vector manipulation patterns are
42346 recognizable. In which case they all pretty much have the
42347 same cost. */
42352 /* This is masked instruction, assume the same cost,
42353 as nonmasked variant. */
42356 else
42362 }
42363 }
42365 #if TARGET_MACHO
42369 /* Given a symbol name and its associated stub, write out the
42370 definition of the stub. */
42372 void
42374 {
42379 /* For 64-bit we shouldn't get here. */
42382 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42399 else
42406 {
42408 }
42410 {
42411 /* PIC stub. */
42412 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42418 }
42419 else
42422 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42423 it needs no stub-binding-helper. */
42430 {
42433 }
42434 else
42439 /* N.B. Keep the correspondence of these
42440 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42441 old-pic/new-pic/non-pic stubs; altering this will break
42442 compatibility with existing dylibs. */
42444 {
42445 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42447 }
42448 else
42449 /* 16-byte -mdynamic-no-pic stub. */
42455 }
42458 /* Order the registers for register allocator. */
42460 void
42462 {
42466 /* First allocate the local general purpose registers. */
42471 /* Global general purpose registers. */
42476 /* x87 registers come first in case we are doing FP math
42477 using them. */
42482 /* SSE registers. */
42488 /* Extended REX SSE registers. */
42492 /* Mask register. */
42496 /* MPX bound registers. */
42500 /* x87 registers. */
42508 /* Initialize the rest of array as we do not allocate some registers
42509 at all. */
42512 }
42514 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42515 in struct attribute_spec handler. */
42516 static tree
42518 tree args,
42521 {
42526 {
42528 name);
42531 }
42533 {
42535 name);
42538 }
42540 {
42541 tree cst;
42545 {
42548 name);
42550 }
42553 {
42556 name);
42558 }
42561 }
42564 }
42566 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42567 struct attribute_spec.handler. */
42568 static tree
42571 {
42576 {
42578 name);
42581 }
42583 /* Can combine regparm with all attributes but fastcall. */
42585 {
42587 {
42589 }
42592 }
42594 {
42596 {
42598 }
42601 }
42604 }
42606 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42607 struct attribute_spec.handler. */
42608 static tree
42611 {
42613 {
42616 }
42622 {
42624 name);
42626 }
42629 }
42631 static tree
42634 {
42643 }
42645 static tree
42648 {
42650 {
42652 name);
42654 }
42656 }
42658 static bool
42660 {
42664 }
42666 /* Returns an expression indicating where the this parameter is
42667 located on entry to the FUNCTION. */
42669 static rtx
42671 {
42677 {
42682 else
42685 }
42690 {
42697 {
42702 }
42703 else
42704 {
42707 {
42713 }
42714 }
42716 }
42720 }
42722 /* Determine whether x86_output_mi_thunk can succeed. */
42724 static bool
42726 const_tree function)
42727 {
42728 /* 64-bit can handle anything. */
42732 /* For 32-bit, everything's fine if we have one free register. */
42736 /* Need a free register for vcall_offset. */
42740 /* Need a free register for GOT references. */
42744 /* Otherwise ok. */
42746 }
42748 /* Output the assembler code for a thunk function. THUNK_DECL is the
42749 declaration for the thunk function itself, FUNCTION is the decl for
42750 the target function. DELTA is an immediate constant offset to be
42751 added to THIS. If VCALL_OFFSET is nonzero, the word at
42752 *(*this + vcall_offset) should be added to THIS. */
42754 static void
42757 {
42765 else
42766 {
42772 else
42774 }
42778 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42779 pull it in now and let DELTA benefit. */
42783 {
42784 /* Put the this parameter into %eax. */
42787 }
42788 else
42791 /* Adjust the this parameter by a fixed constant. */
42793 {
42798 {
42800 {
42804 }
42805 }
42808 }
42810 /* Adjust the this parameter by a value stored in the vtable. */
42812 {
42822 /* Adjust the this parameter. */
42826 {
42830 }
42837 vcall_mem));
42838 else
42840 }
42842 /* If necessary, drop THIS back to its stack slot. */
42848 {
42851 ;
42852 else
42853 {
42857 }
42858 }
42859 else
42860 {
42862 ;
42863 #if TARGET_MACHO
42865 {
42868 }
42870 else
42871 {
42879 }
42880 }
42882 /* Our sibling call patterns do not allow memories, because we have no
42883 predicate that can distinguish between frame and non-frame memory.
42884 For our purposes here, we can get away with (ab)using a jump pattern,
42885 because we're going to do no optimization. */
42887 {
42889 {
42895 }
42896 else
42898 }
42899 else
42900 {
42902 {
42903 // CM_LARGE_PIC always uses pseudo PIC register which is
42904 // uninitialized. Since FUNCTION is local and calling it
42905 // doesn't go through PLT, we use scratch register %r11 as
42906 // PIC register and initialize it here.
42911 }
42914 {
42920 }
42926 }
42929 /* Emit just enough of rest_of_compilation to get the insns emitted.
42930 Note that use_thunk calls assemble_start_function et al. */
42936 }
42938 static void
42940 {
42944 #if TARGET_MACHO
42946 #endif
42953 }
42955 int
42957 {
42958 machine_mode mode;
42969 }
42971 /* Print call to TARGET to FILE. */
42973 static void
42975 {
42978 else
42980 }
42982 /* Output assembler code to FILE to increment profiler label # LABELNO
42983 for profiling a function entry. */
42984 void
42986 {
42990 {
42991 #ifndef NO_PROFILE_COUNTERS
42993 #endif
42997 else
42999 }
43001 {
43002 #ifndef NO_PROFILE_COUNTERS
43005 #endif
43007 }
43008 else
43009 {
43010 #ifndef NO_PROFILE_COUNTERS
43013 #endif
43015 }
43018 {
43022 }
43023 }
43025 /* We don't have exact information about the insn sizes, but we may assume
43026 quite safely that we are informed about all 1 byte insns and memory
43027 address sizes. This is enough to eliminate unnecessary padding in
43028 99% of cases. */
43030 static int
43032 {
43038 /* Discard alignments we've emit and jump instructions. */
43043 /* Important case - calls are always 5 bytes.
43044 It is common to have many calls in the row. */
43053 /* For normal instructions we rely on get_attr_length being exact,
43054 with a few exceptions. */
43056 {
43060 {
43070 /* Otherwise trust get_attr_length. */
43072 }
43077 }
43080 else
43082 }
43084 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43086 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43087 window. */
43089 static void
43091 {
43096 /* Look for all minimal intervals of instructions containing 4 jumps.
43097 The intervals are bounded by START and INSN. NBYTES is the total
43098 size of instructions in the interval including INSN and not including
43099 START. When the NBYTES is smaller than 16 bytes, it is possible
43100 that the end of START and INSN ends up in the same 16byte page.
43102 The smallest offset in the page INSN can start is the case where START
43103 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43104 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43106 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43107 have to, control transfer to label(s) can be performed through other
43108 means, and also we estimate minimum length of all asm stmts as 0. */
43110 {
43114 {
43120 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43121 already in the current 16 byte page, because otherwise
43122 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43123 bytes to reach 16 byte boundary. */
43131 {
43133 {
43138 else
43141 }
43142 }
43144 }
43153 njumps++;
43154 else
43158 {
43163 else
43166 }
43173 {
43180 }
43181 }
43182 }
43183 #endif
43185 /* AMD Athlon works faster
43186 when RET is not destination of conditional jump or directly preceded
43187 by other jump instruction. We avoid the penalty by inserting NOP just
43188 before the RET instructions in such cases. */
43189 static void
43191 {
43192 edge e;
43193 edge_iterator ei;
43196 {
43209 {
43210 edge e;
43211 edge_iterator ei;
43216 {
43219 }
43220 }
43222 {
43228 /* Empty functions get branch mispredict even when
43229 the jump destination is not visible to us. */
43232 }
43234 {
43237 }
43238 }
43239 }
43241 /* Count the minimum number of instructions in BB. Return 4 if the
43242 number of instructions >= 4. */
43244 static int
43246 {
43250 /* Count number of instructions in this block. Return 4 if the number
43251 of instructions >= 4. */
43253 {
43254 /* Only happen in exit blocks. */
43262 {
43263 insn_count++;
43266 }
43267 }
43270 }
43273 /* Count the minimum number of instructions in code path in BB.
43274 Return 4 if the number of instructions >= 4. */
43276 static int
43278 {
43279 edge e;
43280 edge_iterator ei;
43283 /* Only bother counting instructions along paths with no
43284 more than 2 basic blocks between entry and exit. Given
43285 that BB has an edge to exit, determine if a predecessor
43286 of BB has an edge from entry. If so, compute the number
43287 of instructions in the predecessor block. If there
43288 happen to be multiple such blocks, compute the minimum. */
43291 {
43292 edge prev_e;
43293 edge_iterator prev_ei;
43296 {
43299 }
43301 {
43303 {
43308 }
43309 }
43310 }
43316 }
43318 /* Pad short function to 4 instructions. */
43320 static void
43322 {
43323 edge e;
43324 edge_iterator ei;
43327 {
43330 {
43333 /* Pad short function. */
43335 {
43338 /* Find epilogue. */
43347 /* Two NOPs count as one instruction. */
43350 }
43351 }
43352 }
43353 }
43355 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43356 the epilogue, the Windows system unwinder will apply epilogue logic and
43357 produce incorrect offsets. This can be avoided by adding a nop between
43358 the last insn that can throw and the first insn of the epilogue. */
43360 static void
43362 {
43363 edge e;
43364 edge_iterator ei;
43367 {
43370 /* Find the beginning of the epilogue. */
43377 /* We only care about preceding insns that can throw. */
43382 /* Do not separate calls from their debug information. */
43388 else
43392 }
43393 }
43395 /* Implement machine specific optimizations. We implement padding of returns
43396 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43397 static void
43399 {
43400 /* We are freeing block_for_insn in the toplev to keep compatibility
43401 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43408 {
43413 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43416 #endif
43417 }
43418 }
43420 /* Return nonzero when QImode register that must be represented via REX prefix
43421 is used. */
43422 bool
43424 {
43432 }
43434 /* Return true when INSN mentions register that must be encoded using REX
43435 prefix. */
43436 bool
43438 {
43441 {
43446 }
43448 }
43450 /* If profitable, negate (without causing overflow) integer constant
43451 of mode MODE at location LOC. Return true in this case. */
43452 bool
43454 {
43455 HOST_WIDE_INT val;
43461 {
43463 /* DImode x86_64 constants must fit in 32 bits. */
43476 }
43478 /* Avoid overflows. */
43484 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43485 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43488 {
43491 }
43494 }
43496 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43497 optabs would emit if we didn't have TFmode patterns. */
43499 void
43501 {
43536 }
43537 \f
43543 /* Get a vector mode of the same size as the original but with elements
43544 twice as wide. This is only guaranteed to apply to integral vectors. */
43548 {
43549 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43554 }
43556 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43557 fill target with val via vec_duplicate. */
43559 static bool
43561 {
43564 rtx dup;
43566 /* First attempt to recognize VAL as-is. */
43570 {
43572 /* If that fails, force VAL into a register. */
43583 }
43585 }
43587 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43588 with all elements equal to VAR. Return true if successful. */
43590 static bool
43593 {
43597 {
43602 /* FALLTHRU */
43622 {
43623 rtx x;
43630 }
43643 {
43647 permute:
43655 /* Extend to SImode using a paradoxical SUBREG. */
43659 /* Insert the SImode value as low element of a V4SImode vector. */
43668 }
43679 widen:
43680 /* Replicate the value once into the next wider mode and recurse. */
43681 {
43683 rtx x;
43700 }
43706 else
43707 {
43716 }
43723 else
43724 {
43733 }
43738 }
43739 }
43741 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43742 whose ONE_VAR element is VAR, and other elements are zero. Return true
43743 if successful. */
43745 static bool
43748 {
43749 machine_mode vsimode;
43750 rtx new_target;
43755 {
43757 /* For SSE4.1, we normally use vector set. But if the second
43758 element is zero and inter-unit moves are OK, we use movq
43759 instead. */
43761 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43783 /* Use ix86_expand_vector_set in 64bit mode only. */
43788 }
43791 {
43796 }
43799 {
43804 /* FALLTHRU */
43819 else
43826 {
43827 /* We need to shuffle the value to the correct position, so
43828 create a new pseudo to store the intermediate result. */
43830 /* With SSE2, we can use the integer shuffle insns. */
43832 {
43834 const1_rtx,
43841 }
43843 /* Otherwise convert the intermediate result to V4SFmode and
43844 use the SSE1 shuffle instructions. */
43846 {
43849 }
43850 else
43854 const1_rtx,
43863 }
43878 widen:
43882 /* Zero extend the variable element to SImode and recurse. */
43895 }
43896 }
43898 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43899 consisting of the values in VALS. It is known that all elements
43900 except ONE_VAR are constants. Return true if successful. */
43902 static bool
43905 {
43907 machine_mode wmode;
43915 {
43920 /* For the two element vectors, it's just as easy to use
43921 the general case. */
43925 /* Use ix86_expand_vector_set in 64bit mode only. */
43947 widen:
43948 /* There's no way to set one QImode entry easily. Combine
43949 the variable value with its adjacent constant value, and
43950 promote to an HImode set. */
43953 {
43958 }
43959 else
43960 {
43963 }
43977 }
43982 }
43984 /* A subroutine of ix86_expand_vector_init_general. Use vector
43985 concatenate to handle the most general case: all values variable,
43986 and none identical. */
43988 static void
43991 {
43994 rtvec v;
43998 {
44001 {
44046 }
44059 {
44074 }
44079 {
44098 }
44103 {
44116 }
44119 half:
44120 /* FIXME: We process inputs backward to help RA. PR 36222. */
44124 {
44129 }
44133 {
44137 {
44141 }
44144 {
44148 }
44151 }
44153 {
44156 {
44160 }
44163 }
44164 else
44170 }
44171 }
44173 /* A subroutine of ix86_expand_vector_init_general. Use vector
44174 interleave to handle the most general case: all values variable,
44175 and none identical. */
44177 static void
44180 {
44189 {
44210 }
44213 {
44214 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44218 /* Insert the SImode value as low element of V4SImode vector. */
44222 op0),
44224 const1_rtx);
44227 /* Cast the V4SImode vector back to a vector in orignal mode. */
44231 /* Load even elements into the second position. */
44235 const1_rtx));
44237 /* Cast vector to FIRST_IMODE vector. */
44240 }
44242 /* Interleave low FIRST_IMODE vectors. */
44244 {
44248 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44251 }
44253 /* Interleave low SECOND_IMODE vectors. */
44255 {
44258 {
44263 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44264 vector. */
44267 }
44270 /* FALLTHRU */
44277 /* Cast the SECOND_IMODE vector back to a vector on original
44278 mode. */
44285 }
44286 }
44288 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44289 all values variable, and none identical. */
44291 static void
44294 {
44301 {
44306 /* FALLTHRU */
44334 half:
44358 quarter:
44387 /* FALLTHRU */
44393 /* Don't use ix86_expand_vector_init_interleave if we can't
44394 move from GPR to SSE register directly. */
44410 }
44412 {
44414 machine_mode inner_mode;
44424 {
44428 {
44434 else
44435 {
44440 }
44441 }
44444 }
44449 {
44455 }
44457 {
44463 }
44464 else
44466 }
44467 }
44469 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44470 instructions unless MMX_OK is true. */
44472 void
44474 {
44481 rtx x;
44484 {
44494 }
44496 /* Constants are best loaded from the constant pool. */
44498 {
44501 }
44503 /* If all values are identical, broadcast the value. */
44509 /* Values where only one field is non-constant are best loaded from
44510 the pool and overwritten via move later. */
44512 {
44516 one_var))
44521 }
44524 }
44526 void
44528 {
44531 machine_mode half_mode;
44533 rtx tmp;
44535 = {
44542 };
44544 = {
44551 };
44555 {
44559 {
44564 else
44568 }
44580 else
44586 {
44589 /* For the two element vectors, we implement a VEC_CONCAT with
44590 the extraction of the other element. */
44597 else
44602 }
44611 {
44617 /* tmp = target = A B C D */
44619 /* target = A A B B */
44621 /* target = X A B B */
44623 /* target = A X C D */
44630 /* tmp = target = A B C D */
44632 /* tmp = X B C D */
44634 /* target = A B X D */
44641 /* tmp = target = A B C D */
44643 /* tmp = X B C D */
44645 /* target = A B X D */
44653 }
44661 /* Element 0 handled by vec_merge below. */
44663 {
44666 }
44669 {
44670 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44671 store into element 0, then shuffle them back. */
44688 }
44689 else
44690 {
44691 /* For SSE1, we have to reuse the V4SF code. */
44695 }
44748 half:
44749 /* Compute offset. */
44755 /* Extract the half. */
44759 /* Put val in tmp at elt. */
44762 /* Put it back. */
44768 {
44775 }
44776 else
44780 {
44787 }
44788 else
44792 {
44799 }
44800 else
44804 {
44811 }
44812 else
44816 {
44823 }
44824 else
44828 {
44835 }
44836 else
44841 }
44844 {
44848 }
44849 else
44850 {
44859 }
44860 }
44862 void
44864 {
44868 rtx tmp;
44871 {
44876 /* FALLTHRU */
44889 {
44909 }
44921 {
44923 {
44943 }
44947 }
44948 else
44949 {
44950 /* For SSE1, we have to reuse the V4SF code. */
44954 }
44970 {
44974 else
44978 }
44983 {
44987 else
44991 }
44996 {
45000 else
45004 }
45009 {
45013 else
45017 }
45022 {
45026 else
45030 }
45035 {
45039 else
45043 }
45048 {
45052 else
45056 }
45061 {
45065 else
45069 }
45076 else
45085 else
45094 else
45103 else
45109 /* ??? Could extract the appropriate HImode element and shift. */
45112 }
45115 {
45119 /* Let the rtl optimizers know about the zero extension performed. */
45121 {
45124 }
45127 }
45128 else
45129 {
45136 }
45137 }
45139 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45140 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45141 The upper bits of DEST are undefined, though they shouldn't cause
45142 exceptions (some bits from src or all zeros are ok). */
45144 static void
45146 {
45149 {
45153 else
45171 else
45178 else
45186 {
45191 const1_rtx);
45192 }
45193 else
45194 {
45198 }
45220 else
45242 }
45246 }
45248 /* Expand a vector reduction. FN is the binary pattern to reduce;
45249 DEST is the destination; IN is the input vector. */
45251 void
45253 {
45258 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45262 {
45265 }
45270 {
45275 else
45279 }
45280 }
45281 \f
45282 /* Target hook for scalar_mode_supported_p. */
45283 static bool
45285 {
45290 else
45292 }
45294 /* Implements target hook vector_mode_supported_p. */
45295 static bool
45297 {
45311 }
45313 /* Implement target hook libgcc_floating_mode_supported_p. */
45314 static bool
45316 {
45318 {
45325 #ifdef IX86_NO_LIBGCC_TFMODE
45327 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45329 #else
45331 #endif
45335 }
45336 }
45338 /* Target hook for c_mode_for_suffix. */
45339 static machine_mode
45341 {
45348 }
45350 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45352 We do this in the new i386 backend to maintain source compatibility
45353 with the old cc0-based compiler. */
45355 static tree
45357 {
45359 clobbers);
45361 clobbers);
45363 }
45365 /* Implements target vector targetm.asm.encode_section_info. */
45367 static void ATTRIBUTE_UNUSED
45369 {
45374 }
45376 /* Worker function for REVERSE_CONDITION. */
45378 enum rtx_code
45380 {
45384 }
45386 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45387 to OPERANDS[0]. */
45391 {
45393 {
45396 {
45400 }
45404 }
45406 {
45410 else
45411 {
45412 /* There is no non-popping store to memory for XFmode.
45413 So if we need one, follow the store with a load. */
45416 else
45418 }
45419 }
45420 else
45422 }
45424 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45425 FP status register is set. */
45427 void
45429 {
45431 rtx temp;
45436 {
45441 }
45442 else
45443 {
45448 }
45452 pc_rtx);
45457 }
45459 /* Output code to perform a log1p XFmode calculation. */
45462 {
45468 rtx test;
45474 XFmode));
45488 }
45490 /* Emit code for round calculation. */
45492 {
45499 rtx insn;
45504 {
45516 }
45519 {
45540 }
45548 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45550 /* scratch = fxam(op1) */
45553 UNSPEC_FXAM)));
45554 /* e1 = fabs(op1) */
45557 /* e2 = e1 + 0.5 */
45562 /* res = floor(e2) */
45564 {
45569 }
45570 else
45574 {
45577 {
45584 UNSPEC_TRUNC_NOOP)));
45585 }
45601 }
45603 /* flags = signbit(a) */
45606 /* if (flags) then res = -res */
45610 pc_rtx);
45621 }
45623 /* Output code to perform a Newton-Rhapson approximation of a single precision
45624 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45627 {
45635 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45639 /* x0 = rcp(b) estimate */
45643 UNSPEC_RCP14)));
45644 else
45647 UNSPEC_RCP)));
45649 /* e0 = x0 * b */
45653 /* e0 = x0 * e0 */
45657 /* e1 = x0 + x0 */
45661 /* x1 = e1 - e0 */
45665 /* res = a * x1 */
45668 }
45670 /* Output code to perform a Newton-Rhapson approximation of a
45671 single precision floating point [reciprocal] square root. */
45675 {
45677 REAL_VALUE_TYPE r;
45694 {
45697 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45700 }
45702 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45703 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45707 /* x0 = rsqrt(a) estimate */
45710 unspec)));
45712 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45714 {
45722 /* Handle masked compare. */
45724 {
45726 /* Imm value 0x4 corresponds to not-equal comparison. */
45729 }
45730 else
45731 {
45737 }
45738 }
45740 /* e0 = x0 * a */
45743 /* e1 = e0 * x0 */
45747 /* e2 = e1 - 3. */
45754 /* e3 = -.5 * x0 */
45757 else
45758 /* e3 = -.5 * e0 */
45761 /* ret = e2 * e3 */
45764 }
45766 #ifdef TARGET_SOLARIS
45767 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45769 static void
45771 tree decl)
45772 {
45773 /* With Binutils 2.15, the "@unwind" marker must be specified on
45774 every occurrence of the ".eh_frame" section, not just the first
45775 one. */
45778 {
45782 }
45784 #ifndef USE_GAS
45786 {
45789 }
45790 #endif
45793 }
45796 /* Return the mangling of TYPE if it is an extended fundamental type. */
45800 {
45808 {
45810 /* __float128 is "g". */
45813 /* "long double" or __float80 is "e". */
45817 }
45818 }
45820 /* For 32-bit code we can save PIC register setup by using
45821 __stack_chk_fail_local hidden function instead of calling
45822 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45823 register, so it is better to call __stack_chk_fail directly. */
45825 static tree ATTRIBUTE_UNUSED
45827 {
45828 return TARGET_64BIT
45831 }
45833 /* Select a format to encode pointers in exception handling data. CODE
45834 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45835 true if the symbol may be affected by dynamic relocations.
45837 ??? All x86 object file formats are capable of representing this.
45838 After all, the relocation needed is the same as for the call insn.
45839 Whether or not a particular assembler allows us to enter such, I
45840 guess we'll have to see. */
45841 int
45843 {
45845 {
45852 }
45857 }
45858 \f
45859 /* Expand copysign from SIGN to the positive value ABS_VALUE
45860 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45861 the sign-bit. */
45862 static void
45864 {
45868 {
45869 machine_mode vmode;
45875 else
45880 {
45881 /* We need to generate a scalar mode mask in this case. */
45886 }
45887 }
45888 else
45894 }
45896 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45897 mask for masking out the sign-bit is stored in *SMASK, if that is
45898 non-null. */
45899 static rtx
45901 {
45910 else
45914 {
45915 /* We need to generate a scalar mode mask in this case. */
45920 }
45928 }
45930 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
45931 swapping the operands if SWAP_OPERANDS is true. The expanded
45932 code is a forward jump to a newly created label in case the
45933 comparison is true. The generated label rtx is returned. */
45937 {
45940 rtx tmp;
45956 }
45958 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
45959 using comparison code CODE. Operands are swapped for the comparison if
45960 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
45961 static rtx
45964 {
45977 }
45979 /* Generate and return a rtx of mode MODE for 2**n where n is the number
45980 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
45981 static rtx
45983 {
45984 REAL_VALUE_TYPE TWO52r;
45985 rtx TWO52;
45992 }
45994 /* Expand SSE sequence for computing lround from OP1 storing
45995 into OP0. */
45996 void
45998 {
45999 /* C code for the stuff we're doing below:
46000 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46001 return (long)tmp;
46002 */
46006 rtx adj;
46008 /* load nextafter (0.5, 0.0) */
46013 /* adj = copysign (0.5, op1) */
46017 /* adj = op1 + adj */
46020 /* op0 = (imode)adj */
46022 }
46024 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46025 into OPERAND0. */
46026 void
46028 {
46029 /* C code for the stuff we're doing below (for do_floor):
46030 xi = (long)op1;
46031 xi -= (double)xi > op1 ? 1 : 0;
46032 return xi;
46033 */
46039 /* reg = (long)op1 */
46043 /* freg = (double)reg */
46047 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46058 }
46060 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46061 result in OPERAND0. */
46062 void
46064 {
46065 /* C code for the stuff we're doing below:
46066 xa = fabs (operand1);
46067 if (!isless (xa, 2**52))
46068 return operand1;
46069 xa = xa + 2**52 - 2**52;
46070 return copysign (xa, operand1);
46071 */
46079 /* xa = abs (operand1) */
46082 /* if (!isless (xa, TWO52)) goto label; */
46095 }
46097 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46098 into OPERAND0. */
46099 void
46101 {
46102 /* C code for the stuff we expand below.
46103 double xa = fabs (x), x2;
46104 if (!isless (xa, TWO52))
46105 return x;
46106 xa = xa + TWO52 - TWO52;
46107 x2 = copysign (xa, x);
46108 Compensate. Floor:
46109 if (x2 > x)
46110 x2 -= 1;
46111 Compensate. Ceil:
46112 if (x2 < x)
46113 x2 -= -1;
46114 return x2;
46115 */
46122 /* Temporary for holding the result, initialized to the input
46123 operand to ease control flow. */
46127 /* xa = abs (operand1) */
46130 /* if (!isless (xa, TWO52)) goto label; */
46133 /* xa = xa + TWO52 - TWO52; */
46137 /* xa = copysign (xa, operand1) */
46140 /* generate 1.0 or -1.0 */
46145 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46149 /* We always need to subtract here to preserve signed zero. */
46158 }
46160 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46161 into OPERAND0. */
46162 void
46164 {
46165 /* C code for the stuff we expand below.
46166 double xa = fabs (x), x2;
46167 if (!isless (xa, TWO52))
46168 return x;
46169 x2 = (double)(long)x;
46170 Compensate. Floor:
46171 if (x2 > x)
46172 x2 -= 1;
46173 Compensate. Ceil:
46174 if (x2 < x)
46175 x2 += 1;
46176 if (HONOR_SIGNED_ZEROS (mode))
46177 return copysign (x2, x);
46178 return x2;
46179 */
46186 /* Temporary for holding the result, initialized to the input
46187 operand to ease control flow. */
46191 /* xa = abs (operand1) */
46194 /* if (!isless (xa, TWO52)) goto label; */
46197 /* xa = (double)(long)x */
46202 /* generate 1.0 */
46205 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46220 }
46222 /* Expand SSE sequence for computing round from OPERAND1 storing
46223 into OPERAND0. Sequence that works without relying on DImode truncation
46224 via cvttsd2siq that is only available on 64bit targets. */
46225 void
46227 {
46228 /* C code for the stuff we expand below.
46229 double xa = fabs (x), xa2, x2;
46230 if (!isless (xa, TWO52))
46231 return x;
46232 Using the absolute value and copying back sign makes
46233 -0.0 -> -0.0 correct.
46234 xa2 = xa + TWO52 - TWO52;
46235 Compensate.
46236 dxa = xa2 - xa;
46237 if (dxa <= -0.5)
46238 xa2 += 1;
46239 else if (dxa > 0.5)
46240 xa2 -= 1;
46241 x2 = copysign (xa2, x);
46242 return x2;
46243 */
46250 /* Temporary for holding the result, initialized to the input
46251 operand to ease control flow. */
46255 /* xa = abs (operand1) */
46258 /* if (!isless (xa, TWO52)) goto label; */
46261 /* xa2 = xa + TWO52 - TWO52; */
46265 /* dxa = xa2 - xa; */
46268 /* generate 0.5, 1.0 and -0.5 */
46274 /* Compensate. */
46276 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46281 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46287 /* res = copysign (xa2, operand1) */
46294 }
46296 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46297 into OPERAND0. */
46298 void
46300 {
46301 /* C code for SSE variant we expand below.
46302 double xa = fabs (x), x2;
46303 if (!isless (xa, TWO52))
46304 return x;
46305 x2 = (double)(long)x;
46306 if (HONOR_SIGNED_ZEROS (mode))
46307 return copysign (x2, x);
46308 return x2;
46309 */
46316 /* Temporary for holding the result, initialized to the input
46317 operand to ease control flow. */
46321 /* xa = abs (operand1) */
46324 /* if (!isless (xa, TWO52)) goto label; */
46327 /* x = (double)(long)x */
46339 }
46341 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46342 into OPERAND0. */
46343 void
46345 {
46350 /* C code for SSE variant we expand below.
46351 double xa = fabs (x), x2;
46352 if (!isless (xa, TWO52))
46353 return x;
46354 xa2 = xa + TWO52 - TWO52;
46355 Compensate:
46356 if (xa2 > xa)
46357 xa2 -= 1.0;
46358 x2 = copysign (xa2, x);
46359 return x2;
46360 */
46364 /* Temporary for holding the result, initialized to the input
46365 operand to ease control flow. */
46369 /* xa = abs (operand1) */
46372 /* if (!isless (xa, TWO52)) goto label; */
46375 /* res = xa + TWO52 - TWO52; */
46380 /* generate 1.0 */
46383 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46391 /* res = copysign (res, operand1) */
46398 }
46400 /* Expand SSE sequence for computing round from OPERAND1 storing
46401 into OPERAND0. */
46402 void
46404 {
46405 /* C code for the stuff we're doing below:
46406 double xa = fabs (x);
46407 if (!isless (xa, TWO52))
46408 return x;
46409 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46410 return copysign (xa, x);
46411 */
46418 /* Temporary for holding the result, initialized to the input
46419 operand to ease control flow. */
46427 /* load nextafter (0.5, 0.0) */
46432 /* xa = xa + 0.5 */
46436 /* xa = (double)(int64_t)xa */
46441 /* res = copysign (xa, operand1) */
46448 }
46450 /* Expand SSE sequence for computing round
46451 from OP1 storing into OP0 using sse4 round insn. */
46452 void
46454 {
46463 {
46474 }
46476 /* round (a) = trunc (a + copysign (0.5, a)) */
46478 /* load nextafter (0.5, 0.0) */
46484 /* e1 = copysign (0.5, op1) */
46488 /* e2 = op1 + e1 */
46491 /* res = trunc (e2) */
46496 }
46497 \f
46499 /* Table of valid machine attributes. */
46501 {
46502 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, decl_handler,
46503 type_handler, affects_type_identity } */
46504 /* Stdcall attribute says callee is responsible for popping arguments
46505 if they are not variable. */
46508 /* Fastcall attribute says callee is responsible for popping arguments
46509 if they are not variable. */
46512 /* Thiscall attribute says callee is responsible for popping arguments
46513 if they are not variable. */
46516 /* Cdecl attribute says the callee is a normal C declaration */
46519 /* Regparm attribute specifies how many integer arguments are to be
46520 passed in registers. */
46523 /* Sseregparm attribute says we are using x86_64 calling conventions
46524 for FP arguments. */
46527 /* The transactional memory builtins are implicitly regparm or fastcall
46528 depending on the ABI. Override the generic do-nothing attribute that
46529 these builtins were declared with. */
46532 /* force_align_arg_pointer says this function realigns the stack at entry. */
46535 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46542 #endif
46547 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46548 SUBTARGET_ATTRIBUTE_TABLE,
46549 #endif
46550 /* ms_abi and sysv_abi calling convention function attributes. */
46558 /* End element. */
46560 };
46562 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46563 static int
46566 {
46570 {
46615 }
46616 }
46618 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46619 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46620 insn every time. */
46624 /* Initialize vselect_insn. */
46626 static void
46628 {
46630 rtx x;
46641 }
46643 /* Construct (set target (vec_select op0 (parallel perm))) and
46644 return true if that's a valid instruction in the active ISA. */
46646 static bool
46649 {
46675 }
46677 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46679 static bool
46683 {
46684 machine_mode v2mode;
46685 rtx x;
46700 }
46702 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46703 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46705 static bool
46707 {
46717 ;
46719 ;
46721 ;
46723 ;
46724 else
46727 /* This is a blend, not a permute. Elements must stay in their
46728 respective lanes. */
46730 {
46734 }
46739 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46740 decision should be extracted elsewhere, so that we only try that
46741 sequence once all budget==3 options have been tried. */
46748 {
46778 /* See if bytes move in pairs so we can use pblendw with
46779 an immediate argument, rather than pblendvb with a vector
46780 argument. */
46783 {
46784 use_pblendvb:
46788 finish_pblendvb:
46794 else
46799 }
46804 /* FALLTHRU */
46806 do_subreg:
46813 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46817 /* See if bytes move in quadruplets. If yes, vpblendd
46818 with immediate can be used. */
46823 {
46824 /* See if bytes move the same in both lanes. If yes,
46825 vpblendw with immediate can be used. */
46830 /* Use vpblendw. */
46835 }
46837 /* Use vpblendd. */
46844 /* See if words move in pairs. If yes, vpblendd can be used. */
46849 {
46850 /* See if words move the same in both lanes. If not,
46851 vpblendvb must be used. */
46854 {
46855 /* Use vpblendvb. */
46865 }
46867 /* Use vpblendw. */
46871 }
46873 /* Use vpblendd. */
46880 /* Use vpblendd. */
46888 }
46890 /* This matches five different patterns with the different modes. */
46898 }
46900 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46901 in terms of the variable form of vpermilps.
46903 Note that we will have already failed the immediate input vpermilps,
46904 which requires that the high and low part shuffle be identical; the
46905 variable form doesn't require that. */
46907 static bool
46909 {
46916 /* We can only permute within the 128-bit lane. */
46918 {
46922 }
46928 {
46931 /* Within each 128-bit lane, the elements of op0 are numbered
46932 from 0 and the elements of op1 are numbered from 4. */
46939 }
46946 }
46948 /* Return true if permutation D can be performed as VMODE permutation
46949 instead. */
46951 static bool
46953 {
46968 else
46974 }
46976 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46977 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
46979 static bool
46981 {
46990 {
46992 {
46995 {
46999 /* Use vperm2i128 insn. The pattern uses
47000 V4DImode instead of V2TImode. */
47013 }
47015 }
47016 }
47017 else
47018 {
47020 {
47023 }
47025 {
47029 /* V4DImode should be already handled through
47030 expand_vselect by vpermq instruction. */
47037 {
47038 /* First see if vpermq can be used for
47039 V8SImode/V16HImode/V32QImode. */
47041 {
47049 {
47053 }
47055 }
47057 /* Next see if vpermd can be used. */
47060 }
47061 /* Or if vpermps can be used. */
47066 {
47067 /* vpshufb only works intra lanes, it is not
47068 possible to shuffle bytes in between the lanes. */
47072 }
47073 }
47075 {
47079 /* If vpermq didn't work, vpshufb won't work either. */
47087 {
47088 /* First see if vpermq can be used for
47089 V16SImode/V32HImode/V64QImode. */
47091 {
47099 {
47103 }
47105 }
47107 /* Next see if vpermd can be used. */
47110 }
47111 /* Or if vpermps can be used. */
47115 {
47116 /* vpshufb only works intra lanes, it is not
47117 possible to shuffle bytes in between the lanes. */
47121 }
47122 }
47123 else
47125 }
47136 else
47137 {
47145 else
47149 {
47153 }
47154 }
47165 {
47180 else
47182 }
47183 else
47184 {
47187 }
47192 }
47194 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47195 in a single instruction. */
47197 static bool
47199 {
47203 /* Check plain VEC_SELECT first, because AVX has instructions that could
47204 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47205 input where SEL+CONCAT may not. */
47207 {
47213 {
47219 }
47222 {
47226 }
47228 {
47229 /* Use vpbroadcast{b,w,d}. */
47232 {
47275 /* For other modes prefer other shuffles this function creates. */
47277 }
47279 {
47283 }
47284 }
47289 /* There are plenty of patterns in sse.md that are written for
47290 SEL+CONCAT and are not replicated for a single op. Perhaps
47291 that should be changed, to avoid the nastiness here. */
47293 /* Recognize interleave style patterns, which means incrementing
47294 every other permutation operand. */
47296 {
47299 }
47304 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47306 {
47308 {
47313 }
47318 }
47319 }
47321 /* Finally, try the fully general two operand permute. */
47326 /* Recognize interleave style patterns with reversed operands. */
47328 {
47330 {
47334 else
47337 }
47342 }
47344 /* Try the SSE4.1 blend variable merge instructions. */
47348 /* Try one of the AVX vpermil variable permutations. */
47352 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47353 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47357 /* Try the AVX2 vpalignr instruction. */
47361 /* Try the AVX512F vpermi2 instructions. */
47366 }
47368 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47369 in terms of a pair of pshuflw + pshufhw instructions. */
47371 static bool
47373 {
47381 /* The two permutations only operate in 64-bit lanes. */
47392 /* Emit the pshuflw. */
47399 /* Emit the pshufhw. */
47407 }
47409 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47410 the permutation using the SSSE3 palignr instruction. This succeeds
47411 when all of the elements in PERM fit within one vector and we merely
47412 need to shift them down so that a single vector permutation has a
47413 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47414 the vpalignr instruction itself can perform the requested permutation. */
47416 static bool
47418 {
47425 /* Even with AVX, palignr only operates on 128-bit vectors,
47426 in AVX2 palignr operates on both 128-bit lanes. */
47436 {
47440 {
47443 }
47452 }
47455 {
47464 }
47466 /* Given that we have SSSE3, we know we'll be able to implement the
47467 single operand permutation after the palignr with pshufb for
47468 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47469 first. */
47475 {
47480 }
47484 {
47490 else
47495 }
47501 /* For AVX2, test whether we can permute the result in one instruction. */
47503 {
47508 }
47512 {
47516 }
47517 else
47518 {
47523 shift));
47524 }
47528 /* Test for the degenerate case where the alignment by itself
47529 produces the desired permutation. */
47531 {
47534 }
47540 }
47542 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47543 the permutation using the SSE4_1 pblendv instruction. Potentially
47544 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47546 static bool
47548 {
47554 /* Use the same checks as in expand_vec_perm_blend. */
47558 ;
47560 ;
47562 ;
47563 else
47566 /* Figure out where permutation elements stay not in their
47567 respective lanes. */
47569 {
47573 }
47574 /* We can pblend the part where elements stay not in their
47575 respective lanes only when these elements are all in one
47576 half of a permutation.
47577 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47578 lanes, but both 8 and 9 >= 8
47579 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47580 respective lanes and 8 >= 8, but 2 not. */
47586 /* First we apply one operand permutation to the part where
47587 elements stay not in their respective lanes. */
47591 else
47603 else
47608 /* Next we put permuted elements into their positions. */
47612 else
47622 }
47626 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47627 a two vector permutation into a single vector permutation by using
47628 an interleave operation to merge the vectors. */
47630 static bool
47632 {
47641 {
47644 }
47646 {
47649 /* For 32-byte modes allow even d->one_operand_p.
47650 The lack of cross-lane shuffling in some instructions
47651 might prevent a single insn shuffle. */
47654 /* If expand_vec_perm_interleave3 can expand this into
47655 a 3 insn sequence, give up and let it be expanded as
47656 3 insn sequence. While that is one insn longer,
47657 it doesn't need a memory operand and in the common
47658 case that both interleave low and high permutations
47659 with the same operands are adjacent needs 4 insns
47660 for both after CSE. */
47663 }
47664 else
47667 /* Examine from whence the elements come. */
47676 {
47679 /* Split the two input vectors into 4 halves. */
47685 /* If the elements from the low halves use interleave low, and similarly
47686 for interleave high. If the elements are from mis-matched halves, we
47687 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47689 {
47690 /* punpckl* */
47692 {
47697 }
47700 }
47702 {
47703 /* punpckh* */
47705 {
47710 }
47713 }
47715 {
47716 /* shufps */
47718 {
47723 }
47725 {
47726 /* shufpd */
47731 }
47732 }
47734 {
47735 /* shufps */
47737 {
47742 }
47744 {
47745 /* shufpd */
47750 }
47751 }
47752 else
47754 }
47755 else
47756 {
47761 /* Split the two input vectors into 8 quarters. */
47767 {
47770 }
47773 {
47777 }
47779 {
47782 }
47785 {
47787 {
47788 /* Attempt to increase the likelihood that dfinal
47789 shuffle will be intra-lane. */
47793 }
47795 /* vperm2f128 or vperm2i128. */
47797 {
47802 }
47807 {
47811 {
47814 }
47815 }
47816 }
47821 {
47822 /* vpunpckl* */
47824 {
47833 }
47834 }
47837 {
47838 /* vpunpckh* */
47840 {
47849 }
47850 }
47851 else
47853 }
47855 /* Use the remapping array set up above to move the elements from their
47856 swizzled locations into their final destinations. */
47859 {
47862 /* If same_halves is true, both halves of the remapped vector are the
47863 same. Avoid cross-lane accesses if possible. */
47865 {
47868 }
47869 else
47871 }
47873 {
47876 }
47880 /* Test if the final remap can be done with a single insn. For V4SFmode or
47881 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47894 {
47897 }
47904 }
47906 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47907 a single vector cross-lane permutation into vpermq followed
47908 by any of the single insn permutations. */
47910 static bool
47912 {
47926 {
47929 }
47932 {
47937 }
47950 {
47957 }
47964 {
47969 ;
47972 else
47974 }
47983 }
47985 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
47986 a vector permutation using two instructions, vperm2f128 resp.
47987 vperm2i128 followed by any single in-lane permutation. */
47989 static bool
47991 {
48005 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48006 immediate. For perm < 16 the second permutation uses
48007 d->op0 as first operand, for perm >= 16 it uses d->op1
48008 as first operand. The second operand is the result of
48009 vperm2[fi]128. */
48011 {
48012 /* Ignore permutations which do not move anything cross-lane. */
48014 {
48015 /* The second shuffle for e.g. V4DFmode has
48016 0123 and ABCD operands.
48017 Ignore AB23, as 23 is already in the second lane
48018 of the first operand. */
48020 /* And 01CD, as 01 is in the first lane of the first
48021 operand. */
48023 /* And 4567, as then the vperm2[fi]128 doesn't change
48024 anything on the original 4567 second operand. */
48026 }
48027 else
48028 {
48029 /* The second shuffle for e.g. V4DFmode has
48030 4567 and ABCD operands.
48031 Ignore AB67, as 67 is already in the second lane
48032 of the first operand. */
48034 /* And 45CD, as 45 is in the first lane of the first
48035 operand. */
48037 /* And 0123, as then the vperm2[fi]128 doesn't change
48038 anything on the original 0123 first operand. */
48040 }
48043 {
48049 else
48051 }
48054 {
48058 }
48059 else
48063 {
48067 /* Found a usable second shuffle. dfirst will be
48068 vperm2f128 on d->op0 and d->op1. */
48080 /* And dsecond is some single insn shuffle, taking
48081 d->op0 and result of vperm2f128 (if perm < 16) or
48082 d->op1 and result of vperm2f128 (otherwise). */
48091 }
48093 /* For one operand, the only useful vperm2f128 permutation is 0x01
48094 aka lanes swap. */
48097 }
48100 }
48102 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48103 a two vector permutation using 2 intra-lane interleave insns
48104 and cross-lane shuffle for 32-byte vectors. */
48106 static bool
48108 {
48115 ;
48117 ;
48118 else
48133 {
48137 else
48143 else
48149 else
48155 else
48161 else
48167 else
48172 }
48176 }
48178 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48179 a single vector permutation using a single intra-lane vector
48180 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48181 the non-swapped and swapped vectors together. */
48183 static bool
48185 {
48193 || TARGET_AVX2
48202 {
48209 }
48244 }
48246 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48247 permutation using two vperm2f128, followed by a vshufpd insn blending
48248 the two vectors together. */
48250 static bool
48252 {
48295 }
48297 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48298 permutation with two pshufb insns and an ior. We should have already
48299 failed all two instruction sequences. */
48301 static bool
48303 {
48317 /* Generate two permutation masks. If the required element is within
48318 the given vector it is shuffled into the proper lane. If the required
48319 element is in the other vector, force a zero into the lane by setting
48320 bit 7 in the permutation mask. */
48323 {
48330 {
48333 }
48334 }
48358 }
48360 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48361 with two vpshufb insns, vpermq and vpor. We should have already failed
48362 all two or three instruction sequences. */
48364 static bool
48366 {
48381 /* Generate two permutation masks. If the required element is within
48382 the same lane, it is shuffled in. If the required element from the
48383 other lane, force a zero by setting bit 7 in the permutation mask.
48384 In the other mask the mask has non-negative elements if element
48385 is requested from the other lane, but also moved to the other lane,
48386 so that the result of vpshufb can have the two V2TImode halves
48387 swapped. */
48390 {
48395 {
48398 }
48399 }
48408 /* Swap the 128-byte lanes of h into hp. */
48412 const1_rtx));
48429 }
48431 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48432 and extract-odd permutations of two V32QImode and V16QImode operand
48433 with two vpshufb insns, vpor and vpermq. We should have already
48434 failed all two or three instruction sequences. */
48436 static bool
48438 {
48457 /* Generate two permutation masks. In the first permutation mask
48458 the first quarter will contain indexes for the first half
48459 of the op0, the second quarter will contain bit 7 set, third quarter
48460 will contain indexes for the second half of the op0 and the
48461 last quarter bit 7 set. In the second permutation mask
48462 the first quarter will contain bit 7 set, the second quarter
48463 indexes for the first half of the op1, the third quarter bit 7 set
48464 and last quarter indexes for the second half of the op1.
48465 I.e. the first mask e.g. for V32QImode extract even will be:
48466 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48467 (all values masked with 0xf except for -128) and second mask
48468 for extract even will be
48469 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48472 {
48478 {
48481 }
48482 }
48501 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48509 }
48511 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48512 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48513 with two "and" and "pack" or two "shift" and "pack" insns. We should
48514 have already failed all two instruction sequences. */
48516 static bool
48518 {
48522 machine_mode half_mode;
48531 {
48533 /* Required for "pack". */
48544 /* No check as all instructions are SSE2. */
48575 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48576 general shuffles. */
48578 }
48580 /* Check that permutation is even or odd. */
48595 {
48602 }
48603 else
48604 {
48611 }
48612 /* In AVX2 for 256 bit case we need to permute pack result. */
48614 {
48620 const0_rtx,
48621 const2_rtx,
48622 const1_rtx,
48625 }
48626 else
48630 }
48632 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48633 and extract-odd permutations. */
48635 static bool
48637 {
48641 {
48648 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48652 /* Now an unpck[lh]pd will produce the result required. */
48655 else
48661 {
48670 /* Shuffle within the 128-bit lanes to produce:
48671 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48675 /* Shuffle the lanes around to produce:
48676 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48680 /* Shuffle within the 128-bit lanes to produce:
48681 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48684 /* Shuffle within the 128-bit lanes to produce:
48685 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48688 /* Shuffle the lanes around to produce:
48689 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48692 }
48699 /* These are always directly implementable by expand_vec_perm_1. */
48707 else
48708 {
48711 /* We need 2*log2(N)-1 operations to achieve odd/even
48712 with interleave. */
48721 else
48724 }
48736 {
48741 else
48746 {
48751 }
48753 }
48761 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48765 /* Now an vpunpck[lh]qdq will produce the result required. */
48768 else
48775 {
48780 else
48785 {
48790 }
48792 }
48803 /* Shuffle the lanes around into
48804 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48812 /* Swap the 2nd and 3rd position in each lane into
48813 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48819 /* Now an vpunpck[lh]qdq will produce
48820 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48824 else
48833 }
48836 }
48838 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48839 extract-even and extract-odd permutations. */
48841 static bool
48843 {
48855 }
48857 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48858 permutations. We assume that expand_vec_perm_1 has already failed. */
48860 static bool
48862 {
48870 {
48873 /* These are special-cased in sse.md so that we can optionally
48874 use the vbroadcast instruction. They expand to two insns
48875 if the input happens to be in a register. */
48882 /* These are always implementable using standard shuffle patterns. */
48887 /* These can be implemented via interleave. We save one insn by
48888 stopping once we have promoted to V4SImode and then use pshufd. */
48891 do
48892 {
48893 rtx dest;
48899 {
48903 }
48910 }
48926 /* For AVX2 broadcasts of the first element vpbroadcast* or
48927 vpermq should be used by expand_vec_perm_1. */
48933 }
48934 }
48936 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48937 broadcast permutations. */
48939 static bool
48941 {
48953 }
48955 /* Implement arbitrary permutations of two V64QImode operands
48956 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
48957 static bool
48959 {
48969 machine_mode vmode;
48975 {
48982 }
48984 /* Prepare permutations such that the first one takes care of
48985 putting the even bytes into the right positions or one higher
48986 positions (ds[0]) and the second one takes care of
48987 putting the odd bytes into the right positions or one below
48988 (ds[1]). */
48991 {
48994 {
48997 }
48998 else
48999 {
49002 }
49003 }
49025 }
49027 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49028 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49029 all the shorter instruction sequences. */
49031 static bool
49033 {
49049 /* Generate 4 permutation masks. If the required element is within
49050 the same lane, it is shuffled in. If the required element from the
49051 other lane, force a zero by setting bit 7 in the permutation mask.
49052 In the other mask the mask has non-negative elements if element
49053 is requested from the other lane, but also moved to the other lane,
49054 so that the result of vpshufb can have the two V2TImode halves
49055 swapped. */
49058 {
49063 }
49069 {
49077 }
49080 {
49082 {
49085 }
49092 }
49094 /* Swap the 128-byte lanes of h[X]. */
49096 {
49102 const1_rtx));
49104 }
49107 {
49109 {
49112 }
49118 }
49121 {
49123 {
49127 }
49130 }
49140 }
49142 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49143 With all of the interface bits taken care of, perform the expansion
49144 in D and return true on success. */
49146 static bool
49148 {
49149 /* Try a single instruction expansion. */
49153 /* Try sequences of two instructions. */
49176 /* Try sequences of three instructions. */
49193 /* Try sequences of four instructions. */
49204 /* ??? Look for narrow permutations whose element orderings would
49205 allow the promotion to a wider mode. */
49207 /* ??? Look for sequences of interleave or a wider permute that place
49208 the data into the correct lanes for a half-vector shuffle like
49209 pshuf[lh]w or vpermilps. */
49211 /* ??? Look for sequences of interleave that produce the desired results.
49212 The combinatorics of punpck[lh] get pretty ugly... */
49217 /* Even longer sequences. */
49222 }
49224 /* If a permutation only uses one operand, make it clear. Returns true
49225 if the permutation references both operands. */
49227 static bool
49229 {
49237 {
49243 {
49246 }
49247 /* The elements of PERM do not suggest that only the first operand
49248 is used, but both operands are identical. Allow easier matching
49249 of the permutation by folding the permutation into the single
49250 input vector. */
49251 /* FALLTHRU */
49262 }
49265 }
49267 bool
49269 {
49274 rtx sel;
49291 {
49296 }
49303 /* If the selector says both arguments are needed, but the operands are the
49304 same, the above tried to expand with one_operand_p and flattened selector.
49305 If that didn't work, retry without one_operand_p; we succeeded with that
49306 during testing. */
49308 {
49312 }
49315 }
49317 /* Implement targetm.vectorize.vec_perm_const_ok. */
49319 static bool
49322 {
49331 /* Given sufficient ISA support we can just return true here
49332 for selected vector modes. */
49334 {
49340 /* All implementable with a single vpermi2 insn. */
49345 /* All implementable with a single vpermi2 insn. */
49350 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49358 /* All implementable with a single vpermi2 insn. */
49363 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49368 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49375 /* All implementable with a single vpperm insn. */
49378 /* All implementable with 2 pshufb + 1 ior. */
49384 /* All implementable with shufpd or unpck[lh]pd. */
49388 }
49390 /* Extract the values from the vector CST into the permutation
49391 array in D. */
49394 {
49398 }
49400 /* For all elements from second vector, fold the elements to first. */
49405 /* Check whether the mask can be applied to the vector type. */
49408 /* Implementable with shufps or pshufd. */
49412 /* Otherwise we have to go through the motions and see if we can
49413 figure out how to generate the requested permutation. */
49424 }
49426 void
49428 {
49443 /* We'll either be able to implement the permutation directly... */
49447 /* ... or we use the special-case patterns. */
49449 }
49451 static void
49453 {
49468 {
49471 }
49473 /* Note that for AVX this isn't one instruction. */
49476 }
49479 /* Expand a vector operation CODE for a V*QImode in terms of the
49480 same operation on V*HImode. */
49482 void
49484 {
49486 machine_mode himode;
49496 {
49514 }
49518 {
49520 /* Unpack data such that we've got a source byte in each low byte of
49521 each word. We don't care what goes into the high byte of each word.
49522 Rather than trying to get zero in there, most convenient is to let
49523 it be a copy of the low byte. */
49528 /* FALLTHRU */
49540 /* FALLTHRU */
49550 }
49552 /* Perform the operation. */
49559 /* Merge the data back into the right place. */
49569 {
49570 /* For SSE2, we used an full interleave, so the desired
49571 results are in the even elements. */
49574 }
49575 else
49576 {
49577 /* For AVX, the interleave used above was not cross-lane. So the
49578 extraction is evens but with the second and third quarter swapped.
49579 Happily, that is even one insn shorter than even extraction. */
49582 }
49589 }
49591 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49592 if op is CONST_VECTOR with all odd elements equal to their
49593 preceding element. */
49595 static bool
49597 {
49607 }
49609 void
49612 {
49615 rtx x;
49623 /* We only play even/odd games with vectors of SImode. */
49626 /* If we're looking for the odd results, shift those members down to
49627 the even slots. For some cpus this is faster than a PSHUFD. */
49629 {
49630 /* For XOP use vpmacsdqh, but only for smult, as it is only
49631 signed. */
49633 {
49637 }
49648 }
49651 {
49654 else
49656 }
49658 {
49661 else
49663 }
49668 else
49669 {
49672 /* The easiest way to implement this without PMULDQ is to go through
49673 the motions as if we are performing a full 64-bit multiply. With
49674 the exception that we need to do less shuffling of the elements. */
49676 /* Compute the sign-extension, aka highparts, of the two operands. */
49682 /* Multiply LO(A) * HI(B), and vice-versa. */
49688 /* Multiply LO(A) * LO(B). */
49692 /* Combine and shift the highparts into place. */
49697 /* Combine high and low parts. */
49700 }
49702 }
49704 void
49707 {
49713 {
49718 {
49719 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49720 shuffle the elements once so that all elements are in the right
49721 place for immediate use: { A C B D }. */
49726 }
49727 else
49728 {
49729 /* Put the elements into place for the multiply. */
49733 }
49738 /* Shuffle the elements between the lanes. After this we
49739 have { A B E F | C D G H } for each operand. */
49749 /* Shuffle the elements within the lanes. After this we
49750 have { A A B B | C C D D } or { E E F F | G G H H }. */
49791 }
49792 }
49794 void
49796 {
49806 /* Move the results in element 2 down to element 1; we don't care
49807 what goes in elements 2 and 3. Then we can merge the parts
49808 back together with an interleave.
49810 Note that two other sequences were tried:
49811 (1) Use interleaves at the start instead of psrldq, which allows
49812 us to use a single shufps to merge things back at the end.
49813 (2) Use shufps here to combine the two vectors, then pshufd to
49814 put the elements in the correct order.
49815 In both cases the cost of the reformatting stall was too high
49816 and the overall sequence slower. */
49827 }
49829 void
49831 {
49842 {
49843 /* op1: A,B,C,D, op2: E,F,G,H */
49852 /* t1: B,A,D,C */
49859 /* t2: (B*E),(A*F),(D*G),(C*H) */
49862 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49865 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49868 /* Multiply lower parts and add all */
49875 }
49876 else
49877 {
49878 machine_mode nmode;
49882 {
49885 }
49887 {
49890 }
49892 {
49895 }
49896 else
49900 /* Multiply low parts. */
49904 /* Shift input vectors right 32 bits so we can multiply high parts. */
49909 /* Multiply high parts by low parts. */
49915 /* Combine and shift the highparts back. */
49919 /* Combine high and low parts. */
49921 }
49925 }
49927 /* Return 1 if control tansfer instruction INSN
49928 should be encoded with bnd prefix.
49929 If insn is NULL then return 1 when control
49930 transfer instructions should be prefixed with
49931 bnd by default for current function. */
49933 bool
49935 {
49936 /* For call insns check special flag. */
49938 {
49942 }
49944 /* All other insns are prefixed only if function is instrumented. */
49946 }
49948 /* Calculate integer abs() using only SSE2 instructions. */
49950 void
49952 {
49957 {
49958 /* For 32-bit signed integer X, the best way to calculate the absolute
49959 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
49971 /* For 16-bit signed integer X, the best way to calculate the absolute
49972 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
49980 /* For 8-bit signed integer X, the best way to calculate the absolute
49981 value of X is min ((unsigned char) X, (unsigned char) (-X)),
49982 as SSE2 provides the PMINUB insn. */
49992 }
49996 }
49998 /* Expand an insert into a vector register through pinsr insn.
49999 Return true if successful. */
50001 bool
50003 {
50011 {
50014 }
50020 {
50025 {
50032 {
50064 }
50078 }
50082 }
50083 }
50084 \f
50085 /* This function returns the calling abi specific va_list type node.
50086 It returns the FNDECL specific va_list type. */
50088 static tree
50090 {
50097 else
50099 }
50101 /* Returns the canonical va_list type specified by TYPE. If there
50102 is no valid TYPE provided, it return NULL_TREE. */
50104 static tree
50106 {
50109 /* Resolve references and pointers to va_list type. */
50118 {
50123 {
50124 /* If va_list is an array type, the argument may have decayed
50125 to a pointer type, e.g. by being passed to another function.
50126 In that case, unwrap both types so that we can compare the
50127 underlying records. */
50130 {
50133 }
50134 }
50141 {
50142 /* If va_list is an array type, the argument may have decayed
50143 to a pointer type, e.g. by being passed to another function.
50144 In that case, unwrap both types so that we can compare the
50145 underlying records. */
50148 {
50151 }
50152 }
50159 {
50160 /* If va_list is an array type, the argument may have decayed
50161 to a pointer type, e.g. by being passed to another function.
50162 In that case, unwrap both types so that we can compare the
50163 underlying records. */
50166 {
50169 }
50170 }
50174 }
50176 }
50178 /* Iterate through the target-specific builtin types for va_list.
50179 IDX denotes the iterator, *PTREE is set to the result type of
50180 the va_list builtin, and *PNAME to its internal type.
50181 Returns zero if there is no element for this index, otherwise
50182 IDX should be increased upon the next call.
50183 Note, do not iterate a base builtin's name like __builtin_va_list.
50184 Used from c_common_nodes_and_builtins. */
50186 static int
50188 {
50190 {
50192 {
50205 }
50206 }
50209 }
50211 #undef TARGET_SCHED_DISPATCH
50212 #define TARGET_SCHED_DISPATCH has_dispatch
50213 #undef TARGET_SCHED_DISPATCH_DO
50214 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50215 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50216 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50217 #undef TARGET_SCHED_REORDER
50218 #define TARGET_SCHED_REORDER ix86_sched_reorder
50219 #undef TARGET_SCHED_ADJUST_PRIORITY
50220 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50221 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50222 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50223 ix86_dependencies_evaluation_hook
50225 /* The size of the dispatch window is the total number of bytes of
50226 object code allowed in a window. */
50227 #define DISPATCH_WINDOW_SIZE 16
50229 /* Number of dispatch windows considered for scheduling. */
50230 #define MAX_DISPATCH_WINDOWS 3
50232 /* Maximum number of instructions in a window. */
50233 #define MAX_INSN 4
50235 /* Maximum number of immediate operands in a window. */
50236 #define MAX_IMM 4
50238 /* Maximum number of immediate bits allowed in a window. */
50239 #define MAX_IMM_SIZE 128
50241 /* Maximum number of 32 bit immediates allowed in a window. */
50242 #define MAX_IMM_32 4
50244 /* Maximum number of 64 bit immediates allowed in a window. */
50245 #define MAX_IMM_64 2
50247 /* Maximum total of loads or prefetches allowed in a window. */
50248 #define MAX_LOAD 2
50250 /* Maximum total of stores allowed in a window. */
50251 #define MAX_STORE 1
50253 #undef BIG
50254 #define BIG 100
50257 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50260 disp_load,
50261 disp_store,
50262 disp_load_store,
50263 disp_prefetch,
50264 disp_imm,
50265 disp_imm_32,
50266 disp_imm_64,
50267 disp_branch,
50268 disp_cmp,
50269 disp_jcc,
50270 disp_last
50271 };
50273 /* Number of allowable groups in a dispatch window. It is an array
50274 indexed by dispatch_group enum. 100 is used as a big number,
50275 because the number of these kind of operations does not have any
50276 effect in dispatch window, but we need them for other reasons in
50277 the table. */
50280 };
50286 };
50288 /* Instruction path. */
50294 last_path
50295 };
50297 /* sched_insn_info defines a window to the instructions scheduled in
50298 the basic block. It contains a pointer to the insn_info table and
50299 the instruction scheduled.
50301 Windows are allocated for each basic block and are linked
50302 together. */
50304 rtx insn;
50311 /* Linked list of dispatch windows. This is a two way list of
50312 dispatch windows of a basic block. It contains information about
50313 the number of uops in the window and the total number of
50314 instructions and of bytes in the object code for this dispatch
50315 window. */
50333 /* Immediate valuse used in an insn. */
50335 {
50344 /* Get dispatch group of insn. */
50346 static enum dispatch_group
50348 {
50364 }
50366 /* Return true if insn is a compare instruction. */
50368 static bool
50370 {
50378 }
50380 /* Return true if a dispatch violation encountered. */
50382 static bool
50384 {
50388 }
50390 /* Return true if insn is a branch instruction. */
50392 static bool
50394 {
50396 }
50398 /* Return true if insn is a prefetch instruction. */
50400 static bool
50402 {
50404 }
50406 /* This function initializes a dispatch window and the list container holding a
50407 pointer to the window. */
50409 static void
50411 {
50417 else
50435 {
50441 }
50443 }
50445 /* This function allocates and initializes a dispatch window and the
50446 list container holding a pointer to the window. */
50450 {
50455 }
50457 /* This routine initializes the dispatch scheduling information. It
50458 initiates building dispatch scheduler tables and constructs the
50459 first dispatch window. */
50461 static void
50463 {
50464 /* Allocate a dispatch list and a window. */
50469 }
50471 /* This function returns true if a branch is detected. End of a basic block
50472 does not have to be a branch, but here we assume only branches end a
50473 window. */
50475 static bool
50477 {
50479 }
50481 /* This function is called when the end of a window processing is reached. */
50483 static void
50485 {
50488 {
50493 }
50495 }
50497 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50498 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50499 for 48 bytes of instructions. Note that these windows are not dispatch
50500 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50504 {
50506 {
50511 }
50517 }
50519 /* Compute number of immediate operands of an instruction. */
50521 static void
50523 {
50530 {
50537 else
50548 {
50551 }
50556 }
50557 }
50559 /* Return total size of immediate operands of an instruction along with number
50560 of corresponding immediate-operands. It initializes its parameters to zero
50561 befor calling FIND_CONSTANT.
50562 INSN is the input instruction. IMM is the total of immediates.
50563 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50564 bit immediates. */
50566 static int
50568 {
50576 }
50578 /* This function indicates if an operand of an instruction is an
50579 immediate. */
50581 static bool
50583 {
50592 }
50594 /* Return single or double path for instructions. */
50596 static enum insn_path
50598 {
50608 }
50610 /* Return insn dispatch group. */
50612 static enum dispatch_group
50614 {
50632 }
50634 /* Count number of GROUP restricted instructions in a dispatch
50635 window WINDOW_LIST. */
50637 static int
50639 {
50650 {
50669 }
50682 }
50684 /* This function returns true if insn satisfies dispatch rules on the
50685 last window scheduled. */
50687 static bool
50689 {
50697 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50698 instructions should be given the lowest priority in the
50699 scheduling process in Haifa scheduler to make sure they will be
50700 scheduled in the same dispatch window as the reference to them. */
50704 /* Check nonrestricted. */
50708 /* Get last dispatch window. */
50713 {
50718 /* Window 1 is full. Go for next window. */
50720 }
50727 /* See if it fits in the first window. */
50729 {
50730 /* The first widow should have only single and double path
50731 uops. */
50737 }
50739 }
50741 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50742 dispatch window WINDOW_LIST. */
50744 static void
50746 {
50764 /* Initialize window with new instruction. */
50785 {
50788 }
50789 }
50791 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50792 If the total bytes of instructions or the number of instructions in
50793 the window exceed allowable, it allocates a new window. */
50795 static void
50797 {
50820 /* Get the last dispatch window. */
50828 else
50831 /* If current window is full, get a new window.
50832 Window number zero is full, if MAX_INSN uops are scheduled in it.
50833 Window number one is full, if window zero's bytes plus window
50834 one's bytes is 32, or if the bytes of the new instruction added
50835 to the total makes it greater than 48, or it has already MAX_INSN
50836 instructions in it. */
50845 {
50848 }
50851 {
50855 {
50858 }
50859 }
50861 {
50866 {
50869 }
50872 }
50873 else
50877 {
50878 /* End of basic block is reached do end-basic-block process. */
50881 }
50882 }
50884 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50886 DEBUG_FUNCTION static void
50888 {
50894 else
50908 {
50911 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50917 }
50918 }
50920 /* Print to stdout a dispatch window. */
50922 DEBUG_FUNCTION void
50924 {
50926 }
50928 /* Print INSN dispatch information to FILE. */
50930 DEBUG_FUNCTION static void
50932 {
50955 }
50957 /* Print to STDERR the status of the ready list with respect to
50958 dispatch windows. */
50960 DEBUG_FUNCTION void
50962 {
50970 }
50972 /* This routine is the driver of the dispatch scheduler. */
50974 static void
50976 {
50981 }
50983 /* Return TRUE if Dispatch Scheduling is supported. */
50985 static bool
50987 {
50991 {
51007 }
51010 }
51012 /* Implementation of reassociation_width target hook used by
51013 reassoc phase to identify parallelism level in reassociated
51014 tree. Statements tree_code is passed in OPC. Arguments type
51015 is passed in MODE.
51017 Currently parallel reassociation is enabled for Atom
51018 processors only and we set reassociation width to be 2
51019 because Atom may issue up to 2 instructions per cycle.
51021 Return value should be fixed if parallel reassociation is
51022 enabled for other processors. */
51024 static int
51026 {
51029 /* Vector part. */
51031 {
51034 else
51036 }
51038 /* Scalar part. */
51045 }
51047 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51048 place emms and femms instructions. */
51050 static machine_mode
51052 {
51057 {
51076 else
51088 /* FALLTHRU */
51092 }
51093 }
51095 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51096 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51097 256bit and 128bit vectors. */
51099 static unsigned int
51101 {
51104 }
51106 \f
51108 /* Return class of registers which could be used for pseudo of MODE
51109 and of class RCLASS for spilling instead of memory. Return NO_REGS
51110 if it is not possible or non-profitable. */
51111 static reg_class_t
51113 {
51119 }
51121 /* Implement targetm.vectorize.init_cost. */
51125 {
51129 }
51131 /* Implement targetm.vectorize.add_stmt_cost. */
51133 static unsigned
51137 {
51144 /* Statements in an inner loop relative to the loop being
51145 vectorized are weighted more heavily. The value here is
51146 arbitrary and could potentially be improved with analysis. */
51152 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51153 for Silvermont as it has out of order integer pipeline and can execute
51154 2 scalar instruction per tick, but has in order SIMD pipeline. */
51157 {
51161 }
51166 }
51168 /* Implement targetm.vectorize.finish_cost. */
51170 static void
51173 {
51178 }
51180 /* Implement targetm.vectorize.destroy_cost_data. */
51182 static void
51184 {
51186 }
51188 /* Validate target specific memory model bits in VAL. */
51190 static unsigned HOST_WIDE_INT
51192 {
51199 {
51203 }
51206 {
51210 }
51212 {
51216 }
51218 }
51220 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51221 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51222 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51223 or number of vecsize_mangle variants that should be emitted. */
51225 static int
51229 {
51236 {
51240 }
51245 {
51252 /* case SCmode: */
51253 /* case DCmode: */
51259 }
51261 tree t;
51265 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51267 {
51274 /* case SCmode: */
51275 /* case DCmode: */
51281 }
51284 {
51285 /* Parse here processor clause. If not present, default to 'b'. */
51287 }
51289 {
51290 /* If the function isn't exported, we can pick up just one ISA
51291 for the clones. */
51296 else
51299 }
51300 else
51301 {
51304 }
51306 {
51319 }
51321 {
51324 else
51329 }
51331 }
51333 /* Add target attribute to SIMD clone NODE if needed. */
51335 static void
51337 {
51341 {
51356 }
51366 }
51368 /* If SIMD clone NODE can't be used in a vectorized loop
51369 in current function, return -1, otherwise return a badness of using it
51370 (0 if it is most desirable from vecsize_mangle point of view, 1
51371 slightly less desirable, etc.). */
51373 static int
51375 {
51377 {
51395 }
51396 }
51398 /* This function adjusts the unroll factor based on
51399 the hardware capabilities. For ex, bdver3 has
51400 a loop buffer which makes unrolling of smaller
51401 loops less important. This function decides the
51402 unroll factor using number of memory references
51403 (value 32 is used) as a heuristic. */
51405 static unsigned
51407 {
51416 /* Count the number of memory references within the loop body.
51417 This value determines the unrolling factor for bdver3 and bdver4
51418 architectures. */
51427 {
51432 else
51434 }
51441 }
51444 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51446 static bool
51448 {
51449 /* For x87 floating point with standard excess precision handling,
51450 there is no adddf3 pattern (since x87 floating point only has
51451 XFmode operations) so the default hook implementation gets this
51452 wrong. */
51454 }
51456 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51458 static void
51460 {
51465 {
51480 hold_fnclex);
51493 }
51495 {
51504 mxcsr_orig_var,
51514 ldmxcsr_hold_call);
51517 else
51522 ldmxcsr_clear_call);
51523 else
51527 stxmcsr_update_call);
51529 {
51535 exceptions_assign);
51536 }
51537 else
51542 ldmxcsr_update_call);
51543 }
51544 tree atomic_feraiseexcept
51549 atomic_feraiseexcept_call);
51550 }
51552 /* Return mode to be used for bounds or VOIDmode
51553 if bounds are not supported. */
51555 static enum machine_mode
51557 {
51558 /* Do not support pointer checker if MPX
51559 is not enabled. */
51561 {
51566 }
51569 }
51571 /* Return constant used to statically initialize constant bounds.
51573 This function is used to create special bound values. For now
51574 only INIT bounds and NONE bounds are expected. More special
51575 values may be added later. */
51577 static tree
51579 {
51585 /* This function is supposed to be used to create INIT and
51586 NONE bounds only. */
51591 }
51593 /* Generate a list of statements STMTS to initialize pointer bounds
51594 variable VAR with bounds LB and UB. Return the number of generated
51595 statements. */
51597 static int
51599 {
51617 }
51619 /* Initialize the GCC target structure. */
51620 #undef TARGET_RETURN_IN_MEMORY
51621 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51623 #undef TARGET_LEGITIMIZE_ADDRESS
51624 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51626 #undef TARGET_ATTRIBUTE_TABLE
51627 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51628 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51629 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51630 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51631 # undef TARGET_MERGE_DECL_ATTRIBUTES
51632 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51633 #endif
51635 #undef TARGET_COMP_TYPE_ATTRIBUTES
51636 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51638 #undef TARGET_INIT_BUILTINS
51639 #define TARGET_INIT_BUILTINS ix86_init_builtins
51640 #undef TARGET_BUILTIN_DECL
51641 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51642 #undef TARGET_EXPAND_BUILTIN
51643 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51645 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51646 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51647 ix86_builtin_vectorized_function
51649 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51650 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51652 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51653 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51655 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51656 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51658 #undef TARGET_BUILTIN_RECIPROCAL
51659 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51661 #undef TARGET_ASM_FUNCTION_EPILOGUE
51662 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51664 #undef TARGET_ENCODE_SECTION_INFO
51665 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51666 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51667 #else
51668 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51669 #endif
51671 #undef TARGET_ASM_OPEN_PAREN
51673 #undef TARGET_ASM_CLOSE_PAREN
51676 #undef TARGET_ASM_BYTE_OP
51677 #define TARGET_ASM_BYTE_OP ASM_BYTE
51679 #undef TARGET_ASM_ALIGNED_HI_OP
51680 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51681 #undef TARGET_ASM_ALIGNED_SI_OP
51682 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51683 #ifdef ASM_QUAD
51684 #undef TARGET_ASM_ALIGNED_DI_OP
51685 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51686 #endif
51688 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51689 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51691 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51692 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51694 #undef TARGET_ASM_UNALIGNED_HI_OP
51695 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51696 #undef TARGET_ASM_UNALIGNED_SI_OP
51697 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51698 #undef TARGET_ASM_UNALIGNED_DI_OP
51699 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51701 #undef TARGET_PRINT_OPERAND
51702 #define TARGET_PRINT_OPERAND ix86_print_operand
51703 #undef TARGET_PRINT_OPERAND_ADDRESS
51704 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51705 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51706 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51707 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51708 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51710 #undef TARGET_SCHED_INIT_GLOBAL
51711 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51712 #undef TARGET_SCHED_ADJUST_COST
51713 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51714 #undef TARGET_SCHED_ISSUE_RATE
51715 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51716 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51717 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51718 ia32_multipass_dfa_lookahead
51719 #undef TARGET_SCHED_MACRO_FUSION_P
51720 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51721 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51722 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51724 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51725 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51727 #undef TARGET_MEMMODEL_CHECK
51728 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51730 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51731 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51733 #ifdef HAVE_AS_TLS
51734 #undef TARGET_HAVE_TLS
51735 #define TARGET_HAVE_TLS true
51736 #endif
51737 #undef TARGET_CANNOT_FORCE_CONST_MEM
51738 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51739 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51740 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51742 #undef TARGET_DELEGITIMIZE_ADDRESS
51743 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51745 #undef TARGET_MS_BITFIELD_LAYOUT_P
51746 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51748 #if TARGET_MACHO
51749 #undef TARGET_BINDS_LOCAL_P
51750 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51751 #endif
51752 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51753 #undef TARGET_BINDS_LOCAL_P
51754 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51755 #endif
51757 #undef TARGET_ASM_OUTPUT_MI_THUNK
51758 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51759 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51760 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51762 #undef TARGET_ASM_FILE_START
51763 #define TARGET_ASM_FILE_START x86_file_start
51765 #undef TARGET_OPTION_OVERRIDE
51766 #define TARGET_OPTION_OVERRIDE ix86_option_override
51768 #undef TARGET_REGISTER_MOVE_COST
51769 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51770 #undef TARGET_MEMORY_MOVE_COST
51771 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51772 #undef TARGET_RTX_COSTS
51773 #define TARGET_RTX_COSTS ix86_rtx_costs
51774 #undef TARGET_ADDRESS_COST
51775 #define TARGET_ADDRESS_COST ix86_address_cost
51777 #undef TARGET_FIXED_CONDITION_CODE_REGS
51778 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51779 #undef TARGET_CC_MODES_COMPATIBLE
51780 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51782 #undef TARGET_MACHINE_DEPENDENT_REORG
51783 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51785 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51786 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51788 #undef TARGET_BUILD_BUILTIN_VA_LIST
51789 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51791 #undef TARGET_FOLD_BUILTIN
51792 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51794 #undef TARGET_COMPARE_VERSION_PRIORITY
51795 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51797 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51798 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51799 ix86_generate_version_dispatcher_body
51801 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51802 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51803 ix86_get_function_versions_dispatcher
51805 #undef TARGET_ENUM_VA_LIST_P
51806 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51808 #undef TARGET_FN_ABI_VA_LIST
51809 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51811 #undef TARGET_CANONICAL_VA_LIST_TYPE
51812 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51814 #undef TARGET_EXPAND_BUILTIN_VA_START
51815 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51817 #undef TARGET_MD_ASM_CLOBBERS
51818 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51820 #undef TARGET_PROMOTE_PROTOTYPES
51821 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51822 #undef TARGET_SETUP_INCOMING_VARARGS
51823 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51824 #undef TARGET_MUST_PASS_IN_STACK
51825 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51826 #undef TARGET_FUNCTION_ARG_ADVANCE
51827 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51828 #undef TARGET_FUNCTION_ARG
51829 #define TARGET_FUNCTION_ARG ix86_function_arg
51830 #undef TARGET_INIT_PIC_REG
51831 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51832 #undef TARGET_USE_PSEUDO_PIC_REG
51833 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51834 #undef TARGET_FUNCTION_ARG_BOUNDARY
51835 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51836 #undef TARGET_PASS_BY_REFERENCE
51837 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51838 #undef TARGET_INTERNAL_ARG_POINTER
51839 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51840 #undef TARGET_UPDATE_STACK_BOUNDARY
51841 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51842 #undef TARGET_GET_DRAP_RTX
51843 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51844 #undef TARGET_STRICT_ARGUMENT_NAMING
51845 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51846 #undef TARGET_STATIC_CHAIN
51847 #define TARGET_STATIC_CHAIN ix86_static_chain
51848 #undef TARGET_TRAMPOLINE_INIT
51849 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51850 #undef TARGET_RETURN_POPS_ARGS
51851 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51853 #undef TARGET_LEGITIMATE_COMBINED_INSN
51854 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51856 #undef TARGET_ASAN_SHADOW_OFFSET
51857 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
51859 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
51860 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
51862 #undef TARGET_SCALAR_MODE_SUPPORTED_P
51863 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
51865 #undef TARGET_VECTOR_MODE_SUPPORTED_P
51866 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
51868 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
51869 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
51870 ix86_libgcc_floating_mode_supported_p
51872 #undef TARGET_C_MODE_FOR_SUFFIX
51873 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
51875 #ifdef HAVE_AS_TLS
51876 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
51877 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
51878 #endif
51880 #ifdef SUBTARGET_INSERT_ATTRIBUTES
51881 #undef TARGET_INSERT_ATTRIBUTES
51882 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
51883 #endif
51885 #undef TARGET_MANGLE_TYPE
51886 #define TARGET_MANGLE_TYPE ix86_mangle_type
51888 #if !TARGET_MACHO
51889 #undef TARGET_STACK_PROTECT_FAIL
51890 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
51891 #endif
51893 #undef TARGET_FUNCTION_VALUE
51894 #define TARGET_FUNCTION_VALUE ix86_function_value
51896 #undef TARGET_FUNCTION_VALUE_REGNO_P
51897 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
51899 #undef TARGET_PROMOTE_FUNCTION_MODE
51900 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
51902 #undef TARGET_MEMBER_TYPE_FORCES_BLK
51903 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
51905 #undef TARGET_INSTANTIATE_DECLS
51906 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
51908 #undef TARGET_SECONDARY_RELOAD
51909 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
51911 #undef TARGET_CLASS_MAX_NREGS
51912 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
51914 #undef TARGET_PREFERRED_RELOAD_CLASS
51915 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
51916 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
51917 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
51918 #undef TARGET_CLASS_LIKELY_SPILLED_P
51919 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
51921 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
51922 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
51923 ix86_builtin_vectorization_cost
51924 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
51925 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
51926 ix86_vectorize_vec_perm_const_ok
51927 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
51928 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
51929 ix86_preferred_simd_mode
51930 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
51931 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
51932 ix86_autovectorize_vector_sizes
51933 #undef TARGET_VECTORIZE_INIT_COST
51934 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
51935 #undef TARGET_VECTORIZE_ADD_STMT_COST
51936 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
51937 #undef TARGET_VECTORIZE_FINISH_COST
51938 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
51939 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
51940 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
51942 #undef TARGET_SET_CURRENT_FUNCTION
51943 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
51945 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
51946 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
51948 #undef TARGET_OPTION_SAVE
51949 #define TARGET_OPTION_SAVE ix86_function_specific_save
51951 #undef TARGET_OPTION_RESTORE
51952 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
51954 #undef TARGET_OPTION_PRINT
51955 #define TARGET_OPTION_PRINT ix86_function_specific_print
51957 #undef TARGET_OPTION_FUNCTION_VERSIONS
51958 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
51960 #undef TARGET_CAN_INLINE_P
51961 #define TARGET_CAN_INLINE_P ix86_can_inline_p
51963 #undef TARGET_EXPAND_TO_RTL_HOOK
51964 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
51966 #undef TARGET_LEGITIMATE_ADDRESS_P
51967 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
51969 #undef TARGET_LRA_P
51970 #define TARGET_LRA_P hook_bool_void_true
51972 #undef TARGET_REGISTER_PRIORITY
51973 #define TARGET_REGISTER_PRIORITY ix86_register_priority
51975 #undef TARGET_REGISTER_USAGE_LEVELING_P
51976 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
51978 #undef TARGET_LEGITIMATE_CONSTANT_P
51979 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
51981 #undef TARGET_FRAME_POINTER_REQUIRED
51982 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
51984 #undef TARGET_CAN_ELIMINATE
51985 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
51987 #undef TARGET_EXTRA_LIVE_ON_ENTRY
51988 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
51990 #undef TARGET_ASM_CODE_END
51991 #define TARGET_ASM_CODE_END ix86_code_end
51993 #undef TARGET_CONDITIONAL_REGISTER_USAGE
51994 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
51996 #if TARGET_MACHO
51997 #undef TARGET_INIT_LIBFUNCS
51998 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
51999 #endif
52001 #undef TARGET_LOOP_UNROLL_ADJUST
52002 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52004 #undef TARGET_SPILL_CLASS
52005 #define TARGET_SPILL_CLASS ix86_spill_class
52007 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52008 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52009 ix86_simd_clone_compute_vecsize_and_simdlen
52011 #undef TARGET_SIMD_CLONE_ADJUST
52012 #define TARGET_SIMD_CLONE_ADJUST \
52013 ix86_simd_clone_adjust
52015 #undef TARGET_SIMD_CLONE_USABLE
52016 #define TARGET_SIMD_CLONE_USABLE \
52017 ix86_simd_clone_usable
52019 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52020 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52021 ix86_float_exceptions_rounding_supported_p
52023 #undef TARGET_MODE_EMIT
52024 #define TARGET_MODE_EMIT ix86_emit_mode_set
52026 #undef TARGET_MODE_NEEDED
52027 #define TARGET_MODE_NEEDED ix86_mode_needed
52029 #undef TARGET_MODE_AFTER
52030 #define TARGET_MODE_AFTER ix86_mode_after
52032 #undef TARGET_MODE_ENTRY
52033 #define TARGET_MODE_ENTRY ix86_mode_entry
52035 #undef TARGET_MODE_EXIT
52036 #define TARGET_MODE_EXIT ix86_mode_exit
52038 #undef TARGET_MODE_PRIORITY
52039 #define TARGET_MODE_PRIORITY ix86_mode_priority
52041 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52042 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52044 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52045 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52047 #undef TARGET_STORE_BOUNDS_FOR_ARG
52048 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52050 #undef TARGET_LOAD_RETURNED_BOUNDS
52051 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52053 #undef TARGET_STORE_RETURNED_BOUNDS
52054 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52056 #undef TARGET_CHKP_BOUND_MODE
52057 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52059 #undef TARGET_BUILTIN_CHKP_FUNCTION
52060 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52062 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52063 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52065 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52066 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52068 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52069 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52071 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52072 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52074 #undef TARGET_OFFLOAD_OPTIONS
52075 #define TARGET_OFFLOAD_OPTIONS \
52076 ix86_offload_options
52079 \f