gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2" } */
   3
   4 typedef long long v2di __attribute__ ((vector_size (16)));
   5 typedef double v2df __attribute__ ((vector_size (16)));
   6
   7 void
   8 construct_lane_1 (double *y, v2df *z)
   9 {
  10   double y0 = y[0] + 1;
  11   double y1 = y[1] + 2;
  12   v2df x = {y0, y1};
  13   z[2] = x;
  14 }
  15
  16 void
  17 construct_lane_2 (long long *y, v2di *z)
  18 {
  19   long long y0 = y[0] + 1;
  20   long long y1 = y[1] + 2;
  21   v2di x = {y0, y1};
  22   z[2] = x;
  23 }
  24
  25 /* We can use the load_pair_lanes<mode> pattern to vec_concat two DI/DF
  26    values from consecutive memory into a 2-element vector by using
  27    a Q-reg LDR.  */
  28
  29 /* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 1 } } */
  30 /* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 1 } } */
  31 /* { dg-final { scan-assembler-not "ins\t" } } */