1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_register_constraint "k" "STACK_REG"
22 "@internal The stack register.")
24 (define_register_constraint "Ucs" "CALLER_SAVE_REGS"
25 "@internal The caller save registers.")
27 (define_register_constraint "w" "FP_REGS"
28 "Floating point and SIMD vector registers.")
30 (define_register_constraint "x" "FP_LO_REGS"
31 "Floating point and SIMD vector registers V0 - V15.")
33 (define_constraint "I"
34 "A constant that can be used with an ADD operation."
35 (and (match_code "const_int")
36 (match_test "aarch64_uimm12_shift (ival)")))
38 (define_constraint "Uaa"
39 "@internal A constant that matches two uses of add instructions."
40 (and (match_code "const_int")
41 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
43 (define_constraint "J"
44 "A constant that can be used with a SUB operation (once negated)."
45 (and (match_code "const_int")
46 (match_test "aarch64_uimm12_shift (-ival)")))
48 ;; We can't use the mode of a CONST_INT to determine the context in
49 ;; which it is being used, so we must have a separate constraint for
52 (define_constraint "K"
53 "A constant that can be used with a 32-bit logical operation."
54 (and (match_code "const_int")
55 (match_test "aarch64_bitmask_imm (ival, SImode)")))
57 (define_constraint "L"
58 "A constant that can be used with a 64-bit logical operation."
59 (and (match_code "const_int")
60 (match_test "aarch64_bitmask_imm (ival, DImode)")))
62 (define_constraint "M"
63 "A constant that can be used with a 32-bit MOV immediate operation."
64 (and (match_code "const_int")
65 (match_test "aarch64_move_imm (ival, SImode)")))
67 (define_constraint "N"
68 "A constant that can be used with a 64-bit MOV immediate operation."
69 (and (match_code "const_int")
70 (match_test "aarch64_move_imm (ival, DImode)")))
72 (define_constraint "UsO"
73 "A constant that can be used with a 32-bit and operation."
74 (and (match_code "const_int")
75 (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
77 (define_constraint "UsP"
78 "A constant that can be used with a 64-bit and operation."
79 (and (match_code "const_int")
80 (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
82 (define_constraint "S"
83 "A constraint that matches an absolute symbolic address."
84 (and (match_code "const,symbol_ref,label_ref")
85 (match_test "aarch64_symbolic_address_p (op)")))
87 (define_constraint "Y"
88 "Floating point constant zero."
89 (and (match_code "const_double")
90 (match_test "aarch64_float_const_zero_rtx_p (op)")))
92 (define_constraint "Z"
93 "Integer constant zero."
94 (match_test "op == const0_rtx"))
96 (define_constraint "Ush"
97 "A constraint that matches an absolute symbolic address high part."
98 (and (match_code "high")
99 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
101 (define_constraint "Usa"
103 A constraint that matches an absolute symbolic address that can be
104 loaded by a single ADR."
105 (and (match_code "const,symbol_ref,label_ref")
106 (match_test "aarch64_symbolic_address_p (op)")
107 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
109 (define_constraint "Uss"
111 A constraint that matches an immediate shift constant in SImode."
112 (and (match_code "const_int")
113 (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
115 (define_constraint "Usn"
116 "A constant that can be used with a CCMN operation (once negated)."
117 (and (match_code "const_int")
118 (match_test "IN_RANGE (ival, -31, 0)")))
120 (define_constraint "Usd"
122 A constraint that matches an immediate shift constant in DImode."
123 (and (match_code "const_int")
124 (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
126 (define_constraint "Usf"
127 "@internal Usf is a symbol reference under the context where plt stub allowed."
128 (and (match_code "symbol_ref")
129 (match_test "!(aarch64_is_noplt_call_p (op)
130 || aarch64_is_long_call_p (op))")))
132 (define_constraint "UsM"
134 A constraint that matches the immediate constant -1."
135 (match_test "op == constm1_rtx"))
137 (define_constraint "Ui1"
139 A constraint that matches the immediate constant +1."
140 (match_test "op == const1_rtx"))
142 (define_constraint "Ui3"
144 A constraint that matches the integers 0...4."
145 (and (match_code "const_int")
146 (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
148 (define_constraint "Up3"
150 A constraint that matches the integers 2^(0...4)."
151 (and (match_code "const_int")
152 (match_test "(unsigned) exact_log2 (ival) <= 4")))
154 (define_memory_constraint "Q"
155 "A memory address which uses a single base register with no offset."
156 (and (match_code "mem")
157 (match_test "REG_P (XEXP (op, 0))")))
159 (define_memory_constraint "Umq"
161 A memory address which uses a base register with an offset small enough for
162 a load/store pair operation in DI mode."
163 (and (match_code "mem")
164 (match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0),
167 (define_memory_constraint "Ump"
169 A memory address suitable for a load/store pair operation."
170 (and (match_code "mem")
171 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
174 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
175 ;; as a 128-bit vec_concat.
176 (define_memory_constraint "Uml"
178 A memory address suitable for a load/store pair operation."
179 (and (match_code "mem")
180 (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0),
183 (define_memory_constraint "Utv"
185 An address valid for loading/storing opaque structure
186 types wider than TImode."
187 (and (match_code "mem")
188 (match_test "aarch64_simd_mem_operand_p (op)")))
190 (define_memory_constraint "Utq"
192 An address valid for loading or storing a 128-bit AdvSIMD register"
193 (and (match_code "mem")
194 (match_test "aarch64_legitimate_address_p (V2DImode, XEXP (op, 0),
197 (define_constraint "Ufc"
198 "A floating point constant which can be used with an\
199 FMOV immediate operation."
200 (and (match_code "const_double")
201 (match_test "aarch64_float_const_representable_p (op)")))
203 (define_constraint "Uvi"
204 "A floating point constant which can be used with a\
205 MOVI immediate operation."
206 (and (match_code "const_double")
207 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
209 (define_constraint "Do"
211 A constraint that matches vector of immediates for orr."
212 (and (match_code "const_vector")
213 (match_test "aarch64_simd_valid_immediate (op, mode, false,
214 NULL, AARCH64_CHECK_ORR)")))
216 (define_constraint "Db"
218 A constraint that matches vector of immediates for bic."
219 (and (match_code "const_vector")
220 (match_test "aarch64_simd_valid_immediate (op, mode, false,
221 NULL, AARCH64_CHECK_BIC)")))
223 (define_constraint "Dn"
225 A constraint that matches vector of immediates."
226 (and (match_code "const_vector")
227 (match_test "aarch64_simd_valid_immediate (op, GET_MODE (op),
230 (define_constraint "Dh"
232 A constraint that matches an immediate operand valid for\
233 AdvSIMD scalar move in HImode."
234 (and (match_code "const_int")
235 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
238 (define_constraint "Dq"
240 A constraint that matches an immediate operand valid for\
241 AdvSIMD scalar move in QImode."
242 (and (match_code "const_int")
243 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
246 (define_constraint "Dl"
248 A constraint that matches vector of immediates for left shifts."
249 (and (match_code "const_vector")
250 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
253 (define_constraint "Dr"
255 A constraint that matches vector of immediates for right shifts."
256 (and (match_code "const_vector")
257 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
259 (define_constraint "Dz"
261 A constraint that matches vector of immediate zero."
262 (and (match_code "const_vector")
263 (match_test "aarch64_simd_imm_zero_p (op, GET_MODE (op))")))
265 (define_constraint "Dd"
267 A constraint that matches an integer immediate operand valid\
268 for AdvSIMD scalar operations in DImode."
269 (and (match_code "const_int")
270 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
272 (define_constraint "Ds"
274 A constraint that matches an integer immediate operand valid\
275 for AdvSIMD scalar operations in SImode."
276 (and (match_code "const_int")
277 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
279 (define_address_constraint "Dp"
281 An address valid for a prefetch instruction."
282 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))