| blob | 6be05a4f0f722c91cdeec179a1beec09ba8f9181 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2013 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
57 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
58 (TOC_SAVE_OFFSET_32BIT 20)
59 (TOC_SAVE_OFFSET_64BIT 40)
61 ; Function TOC offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_TOC_32BIT 4)
63 (AIX_FUNC_DESC_TOC_64BIT 8)
65 ; Static chain offset in the AIX function descriptor.
66 (AIX_FUNC_DESC_SC_32BIT 8)
67 (AIX_FUNC_DESC_SC_64BIT 16)
68 ])
70 ;;
71 ;; UNSPEC usage
72 ;;
74 (define_c_enum "unspec"
75 [UNSPEC_FRSP ; frsp for POWER machines
76 UNSPEC_PROBE_STACK ; probe stack memory reference
77 UNSPEC_TOCPTR ; address of a word pointing to the TOC
78 UNSPEC_TOC ; address of the TOC (more-or-less)
79 UNSPEC_MOVSI_GOT
80 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
81 UNSPEC_FCTIWZ
82 UNSPEC_FRIM
83 UNSPEC_FRIN
84 UNSPEC_FRIP
85 UNSPEC_FRIZ
86 UNSPEC_LD_MPIC ; load_macho_picbase
87 UNSPEC_MPIC_CORRECT ; macho_correct_pic
88 UNSPEC_TLSGD
89 UNSPEC_TLSLD
90 UNSPEC_MOVESI_FROM_CR
91 UNSPEC_MOVESI_TO_CR
92 UNSPEC_TLSDTPREL
93 UNSPEC_TLSDTPRELHA
94 UNSPEC_TLSDTPRELLO
95 UNSPEC_TLSGOTDTPREL
96 UNSPEC_TLSTPREL
97 UNSPEC_TLSTPRELHA
98 UNSPEC_TLSTPRELLO
99 UNSPEC_TLSGOTTPREL
100 UNSPEC_TLSTLS
101 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
102 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
103 UNSPEC_STFIWX
104 UNSPEC_POPCNTB
105 UNSPEC_FRES
106 UNSPEC_SP_SET
107 UNSPEC_SP_TEST
108 UNSPEC_SYNC
109 UNSPEC_LWSYNC
110 UNSPEC_SYNC_OP
111 UNSPEC_ATOMIC
112 UNSPEC_CMPXCHG
113 UNSPEC_XCHG
114 UNSPEC_AND
115 UNSPEC_DLMZB
116 UNSPEC_DLMZB_CR
117 UNSPEC_DLMZB_STRLEN
118 UNSPEC_RSQRT
119 UNSPEC_TOCREL
120 UNSPEC_MACHOPIC_OFFSET
121 UNSPEC_BPERM
122 UNSPEC_COPYSIGN
123 UNSPEC_PARITY
124 UNSPEC_FCTIW
125 UNSPEC_FCTID
126 UNSPEC_LFIWAX
127 UNSPEC_LFIWZX
128 UNSPEC_FCTIWUZ
129 UNSPEC_GRP_END_NOP
130 ])
132 ;;
133 ;; UNSPEC_VOLATILE usage
134 ;;
136 (define_c_enum "unspecv"
137 [UNSPECV_BLOCK
138 UNSPECV_LL ; load-locked
139 UNSPECV_SC ; store-conditional
140 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
141 UNSPECV_EH_RR ; eh_reg_restore
142 UNSPECV_ISYNC ; isync instruction
143 UNSPECV_MFTB ; move from time base
144 ])
146 \f
147 ;; Define an insn type attribute. This is used in function unit delay
148 ;; computations.
149 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto"
150 (const_string "integer"))
152 ;; Define floating point instruction sub-types for use with Xfpu.md
153 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
155 ;; Length (in bytes).
156 ; '(pc)' in the following doesn't include the instruction itself; it is
157 ; calculated as if the instruction had zero size.
158 (define_attr "length" ""
159 (if_then_else (eq_attr "type" "branch")
160 (if_then_else (and (ge (minus (match_dup 0) (pc))
161 (const_int -32768))
162 (lt (minus (match_dup 0) (pc))
163 (const_int 32764)))
164 (const_int 4)
165 (const_int 8))
166 (const_int 4)))
168 ;; Processor type -- this attribute must exactly match the processor_type
169 ;; enumeration in rs6000-opts.h.
170 (define_attr "cpu"
171 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
172 ppc750,ppc7400,ppc7450,
173 ppc403,ppc405,ppc440,ppc476,
174 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
175 power4,power5,power6,power7,power8,
176 rs64a,mpccore,cell,ppca2,titan"
177 (const (symbol_ref "rs6000_cpu_attr")))
180 ;; If this instruction is microcoded on the CELL processor
181 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
182 (define_attr "cell_micro" "not,conditional,always"
183 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
184 (const_string "always")
185 (const_string "not")))
187 (automata_option "ndfa")
189 (include "rs64.md")
190 (include "mpc.md")
191 (include "40x.md")
192 (include "440.md")
193 (include "476.md")
194 (include "601.md")
195 (include "603.md")
196 (include "6xx.md")
197 (include "7xx.md")
198 (include "7450.md")
199 (include "8540.md")
200 (include "e300c2c3.md")
201 (include "e500mc.md")
202 (include "e500mc64.md")
203 (include "e5500.md")
204 (include "e6500.md")
205 (include "power4.md")
206 (include "power5.md")
207 (include "power6.md")
208 (include "power7.md")
209 (include "cell.md")
210 (include "xfpu.md")
211 (include "a2.md")
212 (include "titan.md")
214 (include "predicates.md")
215 (include "constraints.md")
217 (include "darwin.md")
219 \f
220 ;; Mode iterators
222 ; This mode iterator allows :GPR to be used to indicate the allowable size
223 ; of whole values in GPRs.
224 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
226 ; Any supported integer mode.
227 (define_mode_iterator INT [QI HI SI DI TI PTI])
229 ; Any supported integer mode that fits in one register.
230 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
232 ; extend modes for DImode
233 (define_mode_iterator QHSI [QI HI SI])
235 ; SImode or DImode, even if DImode doesn't fit in GPRs.
236 (define_mode_iterator SDI [SI DI])
238 ; The size of a pointer. Also, the size of the value that a record-condition
239 ; (one with a '.') will compare; and the size used for arithmetic carries.
240 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
242 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
243 ; PTImode is GPR only)
244 (define_mode_iterator TI2 [TI PTI])
246 ; Any hardware-supported floating-point mode
247 (define_mode_iterator FP [
248 (SF "TARGET_HARD_FLOAT
249 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
250 (DF "TARGET_HARD_FLOAT
251 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
252 (TF "!TARGET_IEEEQUAD
253 && TARGET_HARD_FLOAT
254 && (TARGET_FPRS || TARGET_E500_DOUBLE)
255 && TARGET_LONG_DOUBLE_128")
256 (DD "TARGET_DFP")
257 (TD "TARGET_DFP")])
259 ; Any fma capable floating-point mode.
260 (define_mode_iterator FMA_F [
261 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
262 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
263 || VECTOR_UNIT_VSX_P (DFmode)")
264 (V2SF "TARGET_PAIRED_FLOAT")
265 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
266 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
267 ])
269 ; Floating point move iterators to combine binary and decimal moves
270 (define_mode_iterator FMOVE32 [SF SD])
271 (define_mode_iterator FMOVE64 [DF DD])
272 (define_mode_iterator FMOVE64X [DI DF DD])
273 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
274 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
276 ; Whether a floating point move is ok, don't allow SD without hardware FP
277 (define_mode_attr fmove_ok [(SF "")
278 (DF "")
279 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
280 (DD "")])
282 ; Convert REAL_VALUE to the appropriate bits
283 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
284 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
285 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
286 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
288 ; Definitions for load to 32-bit fpr register
289 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
290 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
291 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
293 ; Definitions for store from 32-bit fpr register
294 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
295 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
296 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
298 ; These modes do not fit in integer registers in 32-bit mode.
299 ; but on e500v2, the gpr are 64 bit registers
300 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
302 ; Iterator for reciprocal estimate instructions
303 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
305 ; Iterator for just SF/DF
306 (define_mode_iterator SFDF [SF DF])
308 ; Conditional returns.
309 (define_code_iterator any_return [return simple_return])
310 (define_code_attr return_pred [(return "direct_return ()")
311 (simple_return "1")])
312 (define_code_attr return_str [(return "") (simple_return "simple_")])
314 ; Various instructions that come in SI and DI forms.
315 ; A generic w/d attribute, for things like cmpw/cmpd.
316 (define_mode_attr wd [(QI "b")
317 (HI "h")
318 (SI "w")
319 (DI "d")
320 (V16QI "b")
321 (V8HI "h")
322 (V4SI "w")
323 (V2DI "d")])
325 ; DImode bits
326 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
328 ;; ISEL/ISEL64 target selection
329 (define_mode_attr sel [(SI "") (DI "64")])
331 ;; Suffix for reload patterns
332 (define_mode_attr ptrsize [(SI "32bit")
333 (DI "64bit")])
335 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
336 (DI "TARGET_64BIT")])
338 (define_mode_attr mptrsize [(SI "si")
339 (DI "di")])
341 (define_mode_attr ptrload [(SI "lwz")
342 (DI "ld")])
344 (define_mode_attr ptrm [(SI "m")
345 (DI "Y")])
347 (define_mode_attr rreg [(SF "f")
348 (DF "ws")
349 (V4SF "wf")
350 (V2DF "wd")])
352 (define_mode_attr rreg2 [(SF "f")
353 (DF "d")])
355 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
356 (DF "TARGET_FCFID")])
358 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
359 (DF "TARGET_E500_DOUBLE")])
361 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
362 (DF "TARGET_DOUBLE_FLOAT")])
363 \f
364 ;; Start with fixed-point load and store insns. Here we put only the more
365 ;; complex forms. Basic data transfer is done later.
367 (define_expand "zero_extend<mode>di2"
368 [(set (match_operand:DI 0 "gpc_reg_operand" "")
369 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
370 "TARGET_POWERPC64"
371 "")
373 (define_insn "*zero_extend<mode>di2_internal1"
374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
375 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
376 "TARGET_POWERPC64"
377 "@
378 l<wd>z%U1%X1 %0,%1
379 rldicl %0,%1,0,<dbits>"
380 [(set_attr_alternative "type"
381 [(if_then_else
382 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
383 (const_string "load_ux")
384 (if_then_else
385 (match_test "update_address_mem (operands[1], VOIDmode)")
386 (const_string "load_u")
387 (const_string "load")))
388 (const_string "*")])])
390 (define_insn "*zero_extend<mode>di2_internal2"
391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
392 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
393 (const_int 0)))
394 (clobber (match_scratch:DI 2 "=r,r"))]
395 "TARGET_64BIT"
396 "@
397 rldicl. %2,%1,0,<dbits>
398 #"
399 [(set_attr "type" "compare")
400 (set_attr "length" "4,8")])
402 (define_split
403 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
404 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
405 (const_int 0)))
406 (clobber (match_scratch:DI 2 ""))]
407 "TARGET_POWERPC64 && reload_completed"
408 [(set (match_dup 2)
409 (zero_extend:DI (match_dup 1)))
410 (set (match_dup 0)
411 (compare:CC (match_dup 2)
412 (const_int 0)))]
413 "")
415 (define_insn "*zero_extend<mode>di2_internal3"
416 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
417 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
418 (const_int 0)))
419 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
420 (zero_extend:DI (match_dup 1)))]
421 "TARGET_64BIT"
422 "@
423 rldicl. %0,%1,0,<dbits>
424 #"
425 [(set_attr "type" "compare")
426 (set_attr "length" "4,8")])
428 (define_split
429 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
430 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
431 (const_int 0)))
432 (set (match_operand:DI 0 "gpc_reg_operand" "")
433 (zero_extend:DI (match_dup 1)))]
434 "TARGET_POWERPC64 && reload_completed"
435 [(set (match_dup 0)
436 (zero_extend:DI (match_dup 1)))
437 (set (match_dup 2)
438 (compare:CC (match_dup 0)
439 (const_int 0)))]
440 "")
442 (define_insn "extendqidi2"
443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
444 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
445 "TARGET_POWERPC64"
446 "extsb %0,%1"
447 [(set_attr "type" "exts")])
449 (define_insn ""
450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
451 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
452 (const_int 0)))
453 (clobber (match_scratch:DI 2 "=r,r"))]
454 "TARGET_64BIT"
455 "@
456 extsb. %2,%1
457 #"
458 [(set_attr "type" "compare")
459 (set_attr "length" "4,8")])
461 (define_split
462 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
463 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
464 (const_int 0)))
465 (clobber (match_scratch:DI 2 ""))]
466 "TARGET_POWERPC64 && reload_completed"
467 [(set (match_dup 2)
468 (sign_extend:DI (match_dup 1)))
469 (set (match_dup 0)
470 (compare:CC (match_dup 2)
471 (const_int 0)))]
472 "")
474 (define_insn ""
475 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
476 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
477 (const_int 0)))
478 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
479 (sign_extend:DI (match_dup 1)))]
480 "TARGET_64BIT"
481 "@
482 extsb. %0,%1
483 #"
484 [(set_attr "type" "compare")
485 (set_attr "length" "4,8")])
487 (define_split
488 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
489 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
490 (const_int 0)))
491 (set (match_operand:DI 0 "gpc_reg_operand" "")
492 (sign_extend:DI (match_dup 1)))]
493 "TARGET_POWERPC64 && reload_completed"
494 [(set (match_dup 0)
495 (sign_extend:DI (match_dup 1)))
496 (set (match_dup 2)
497 (compare:CC (match_dup 0)
498 (const_int 0)))]
499 "")
501 (define_expand "extendhidi2"
502 [(set (match_operand:DI 0 "gpc_reg_operand" "")
503 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
504 "TARGET_POWERPC64"
505 "")
507 (define_insn ""
508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
509 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
510 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
511 "@
512 lha%U1%X1 %0,%1
513 extsh %0,%1"
514 [(set_attr_alternative "type"
515 [(if_then_else
516 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
517 (const_string "load_ext_ux")
518 (if_then_else
519 (match_test "update_address_mem (operands[1], VOIDmode)")
520 (const_string "load_ext_u")
521 (const_string "load_ext")))
522 (const_string "exts")])])
524 (define_insn ""
525 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
526 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
527 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
528 "extsh %0,%1"
529 [(set_attr "type" "exts")])
531 (define_insn ""
532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
533 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
534 (const_int 0)))
535 (clobber (match_scratch:DI 2 "=r,r"))]
536 "TARGET_64BIT"
537 "@
538 extsh. %2,%1
539 #"
540 [(set_attr "type" "compare")
541 (set_attr "length" "4,8")])
543 (define_split
544 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
545 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
546 (const_int 0)))
547 (clobber (match_scratch:DI 2 ""))]
548 "TARGET_POWERPC64 && reload_completed"
549 [(set (match_dup 2)
550 (sign_extend:DI (match_dup 1)))
551 (set (match_dup 0)
552 (compare:CC (match_dup 2)
553 (const_int 0)))]
554 "")
556 (define_insn ""
557 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
558 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
559 (const_int 0)))
560 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
561 (sign_extend:DI (match_dup 1)))]
562 "TARGET_64BIT"
563 "@
564 extsh. %0,%1
565 #"
566 [(set_attr "type" "compare")
567 (set_attr "length" "4,8")])
569 (define_split
570 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
571 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
572 (const_int 0)))
573 (set (match_operand:DI 0 "gpc_reg_operand" "")
574 (sign_extend:DI (match_dup 1)))]
575 "TARGET_POWERPC64 && reload_completed"
576 [(set (match_dup 0)
577 (sign_extend:DI (match_dup 1)))
578 (set (match_dup 2)
579 (compare:CC (match_dup 0)
580 (const_int 0)))]
581 "")
583 (define_expand "extendsidi2"
584 [(set (match_operand:DI 0 "gpc_reg_operand" "")
585 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
586 "TARGET_POWERPC64"
587 "")
589 (define_insn ""
590 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
591 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
592 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
593 "@
594 lwa%U1%X1 %0,%1
595 extsw %0,%1"
596 [(set_attr_alternative "type"
597 [(if_then_else
598 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
599 (const_string "load_ext_ux")
600 (if_then_else
601 (match_test "update_address_mem (operands[1], VOIDmode)")
602 (const_string "load_ext_u")
603 (const_string "load_ext")))
604 (const_string "exts")])])
606 (define_insn ""
607 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
608 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
609 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
610 "extsw %0,%1"
611 [(set_attr "type" "exts")])
613 (define_insn ""
614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
616 (const_int 0)))
617 (clobber (match_scratch:DI 2 "=r,r"))]
618 "TARGET_64BIT"
619 "@
620 extsw. %2,%1
621 #"
622 [(set_attr "type" "compare")
623 (set_attr "length" "4,8")])
625 (define_split
626 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
627 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
628 (const_int 0)))
629 (clobber (match_scratch:DI 2 ""))]
630 "TARGET_POWERPC64 && reload_completed"
631 [(set (match_dup 2)
632 (sign_extend:DI (match_dup 1)))
633 (set (match_dup 0)
634 (compare:CC (match_dup 2)
635 (const_int 0)))]
636 "")
638 (define_insn ""
639 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
640 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
641 (const_int 0)))
642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
643 (sign_extend:DI (match_dup 1)))]
644 "TARGET_64BIT"
645 "@
646 extsw. %0,%1
647 #"
648 [(set_attr "type" "compare")
649 (set_attr "length" "4,8")])
651 (define_split
652 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
653 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
654 (const_int 0)))
655 (set (match_operand:DI 0 "gpc_reg_operand" "")
656 (sign_extend:DI (match_dup 1)))]
657 "TARGET_POWERPC64 && reload_completed"
658 [(set (match_dup 0)
659 (sign_extend:DI (match_dup 1)))
660 (set (match_dup 2)
661 (compare:CC (match_dup 0)
662 (const_int 0)))]
663 "")
665 (define_expand "zero_extendqisi2"
666 [(set (match_operand:SI 0 "gpc_reg_operand" "")
667 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
668 ""
669 "")
671 (define_insn ""
672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
673 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
674 ""
675 "@
676 lbz%U1%X1 %0,%1
677 rlwinm %0,%1,0,0xff"
678 [(set_attr_alternative "type"
679 [(if_then_else
680 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
681 (const_string "load_ux")
682 (if_then_else
683 (match_test "update_address_mem (operands[1], VOIDmode)")
684 (const_string "load_u")
685 (const_string "load")))
686 (const_string "*")])])
688 (define_insn ""
689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
690 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (clobber (match_scratch:SI 2 "=r,r"))]
693 ""
694 "@
695 andi. %2,%1,0xff
696 #"
697 [(set_attr "type" "fast_compare,compare")
698 (set_attr "length" "4,8")])
700 (define_split
701 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
702 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
703 (const_int 0)))
704 (clobber (match_scratch:SI 2 ""))]
705 "reload_completed"
706 [(set (match_dup 2)
707 (zero_extend:SI (match_dup 1)))
708 (set (match_dup 0)
709 (compare:CC (match_dup 2)
710 (const_int 0)))]
711 "")
713 (define_insn ""
714 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
715 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
716 (const_int 0)))
717 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
718 (zero_extend:SI (match_dup 1)))]
719 ""
720 "@
721 andi. %0,%1,0xff
722 #"
723 [(set_attr "type" "fast_compare,compare")
724 (set_attr "length" "4,8")])
726 (define_split
727 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
728 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
729 (const_int 0)))
730 (set (match_operand:SI 0 "gpc_reg_operand" "")
731 (zero_extend:SI (match_dup 1)))]
732 "reload_completed"
733 [(set (match_dup 0)
734 (zero_extend:SI (match_dup 1)))
735 (set (match_dup 2)
736 (compare:CC (match_dup 0)
737 (const_int 0)))]
738 "")
740 (define_insn "extendqisi2"
741 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
742 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
743 ""
744 "extsb %0,%1"
745 [(set_attr "type" "exts")])
747 (define_insn ""
748 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
749 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
750 (const_int 0)))
751 (clobber (match_scratch:SI 2 "=r,r"))]
752 ""
753 "@
754 extsb. %2,%1
755 #"
756 [(set_attr "type" "compare")
757 (set_attr "length" "4,8")])
759 (define_split
760 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
761 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
762 (const_int 0)))
763 (clobber (match_scratch:SI 2 ""))]
764 "reload_completed"
765 [(set (match_dup 2)
766 (sign_extend:SI (match_dup 1)))
767 (set (match_dup 0)
768 (compare:CC (match_dup 2)
769 (const_int 0)))]
770 "")
772 (define_insn ""
773 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
774 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
775 (const_int 0)))
776 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
777 (sign_extend:SI (match_dup 1)))]
778 ""
779 "@
780 extsb. %0,%1
781 #"
782 [(set_attr "type" "compare")
783 (set_attr "length" "4,8")])
785 (define_split
786 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
787 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
788 (const_int 0)))
789 (set (match_operand:SI 0 "gpc_reg_operand" "")
790 (sign_extend:SI (match_dup 1)))]
791 "reload_completed"
792 [(set (match_dup 0)
793 (sign_extend:SI (match_dup 1)))
794 (set (match_dup 2)
795 (compare:CC (match_dup 0)
796 (const_int 0)))]
797 "")
799 (define_insn ""
800 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
801 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
802 ""
803 "@
804 lbz%U1%X1 %0,%1
805 rlwinm %0,%1,0,0xff"
806 [(set_attr_alternative "type"
807 [(if_then_else
808 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
809 (const_string "load_ux")
810 (if_then_else
811 (match_test "update_address_mem (operands[1], VOIDmode)")
812 (const_string "load_u")
813 (const_string "load")))
814 (const_string "*")])])
816 (define_insn ""
817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
818 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
819 (const_int 0)))
820 (clobber (match_scratch:HI 2 "=r,r"))]
821 ""
822 "@
823 andi. %2,%1,0xff
824 #"
825 [(set_attr "type" "fast_compare,compare")
826 (set_attr "length" "4,8")])
828 (define_split
829 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
830 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
831 (const_int 0)))
832 (clobber (match_scratch:HI 2 ""))]
833 "reload_completed"
834 [(set (match_dup 2)
835 (zero_extend:HI (match_dup 1)))
836 (set (match_dup 0)
837 (compare:CC (match_dup 2)
838 (const_int 0)))]
839 "")
841 (define_insn ""
842 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
843 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
844 (const_int 0)))
845 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
846 (zero_extend:HI (match_dup 1)))]
847 ""
848 "@
849 andi. %0,%1,0xff
850 #"
851 [(set_attr "type" "fast_compare,compare")
852 (set_attr "length" "4,8")])
854 (define_split
855 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
856 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
857 (const_int 0)))
858 (set (match_operand:HI 0 "gpc_reg_operand" "")
859 (zero_extend:HI (match_dup 1)))]
860 "reload_completed"
861 [(set (match_dup 0)
862 (zero_extend:HI (match_dup 1)))
863 (set (match_dup 2)
864 (compare:CC (match_dup 0)
865 (const_int 0)))]
866 "")
868 (define_insn "extendqihi2"
869 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
870 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
871 ""
872 "extsb %0,%1"
873 [(set_attr "type" "exts")])
875 (define_insn ""
876 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
877 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (clobber (match_scratch:HI 2 "=r,r"))]
880 ""
881 "@
882 extsb. %2,%1
883 #"
884 [(set_attr "type" "compare")
885 (set_attr "length" "4,8")])
887 (define_split
888 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
889 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
890 (const_int 0)))
891 (clobber (match_scratch:HI 2 ""))]
892 "reload_completed"
893 [(set (match_dup 2)
894 (sign_extend:HI (match_dup 1)))
895 (set (match_dup 0)
896 (compare:CC (match_dup 2)
897 (const_int 0)))]
898 "")
900 (define_insn ""
901 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
902 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
903 (const_int 0)))
904 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
905 (sign_extend:HI (match_dup 1)))]
906 ""
907 "@
908 extsb. %0,%1
909 #"
910 [(set_attr "type" "compare")
911 (set_attr "length" "4,8")])
913 (define_split
914 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
915 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
916 (const_int 0)))
917 (set (match_operand:HI 0 "gpc_reg_operand" "")
918 (sign_extend:HI (match_dup 1)))]
919 "reload_completed"
920 [(set (match_dup 0)
921 (sign_extend:HI (match_dup 1)))
922 (set (match_dup 2)
923 (compare:CC (match_dup 0)
924 (const_int 0)))]
925 "")
927 (define_expand "zero_extendhisi2"
928 [(set (match_operand:SI 0 "gpc_reg_operand" "")
929 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
930 ""
931 "")
933 (define_insn ""
934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
935 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
936 ""
937 "@
938 lhz%U1%X1 %0,%1
939 rlwinm %0,%1,0,0xffff"
940 [(set_attr_alternative "type"
941 [(if_then_else
942 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
943 (const_string "load_ux")
944 (if_then_else
945 (match_test "update_address_mem (operands[1], VOIDmode)")
946 (const_string "load_u")
947 (const_string "load")))
948 (const_string "*")])])
950 (define_insn ""
951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
952 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
953 (const_int 0)))
954 (clobber (match_scratch:SI 2 "=r,r"))]
955 ""
956 "@
957 andi. %2,%1,0xffff
958 #"
959 [(set_attr "type" "fast_compare,compare")
960 (set_attr "length" "4,8")])
962 (define_split
963 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
965 (const_int 0)))
966 (clobber (match_scratch:SI 2 ""))]
967 "reload_completed"
968 [(set (match_dup 2)
969 (zero_extend:SI (match_dup 1)))
970 (set (match_dup 0)
971 (compare:CC (match_dup 2)
972 (const_int 0)))]
973 "")
975 (define_insn ""
976 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
977 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
978 (const_int 0)))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
980 (zero_extend:SI (match_dup 1)))]
981 ""
982 "@
983 andi. %0,%1,0xffff
984 #"
985 [(set_attr "type" "fast_compare,compare")
986 (set_attr "length" "4,8")])
988 (define_split
989 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
990 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
991 (const_int 0)))
992 (set (match_operand:SI 0 "gpc_reg_operand" "")
993 (zero_extend:SI (match_dup 1)))]
994 "reload_completed"
995 [(set (match_dup 0)
996 (zero_extend:SI (match_dup 1)))
997 (set (match_dup 2)
998 (compare:CC (match_dup 0)
999 (const_int 0)))]
1000 "")
1002 (define_expand "extendhisi2"
1003 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1004 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1005 ""
1006 "")
1008 (define_insn ""
1009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1010 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1011 "rs6000_gen_cell_microcode"
1012 "@
1013 lha%U1%X1 %0,%1
1014 extsh %0,%1"
1015 [(set_attr_alternative "type"
1016 [(if_then_else
1017 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1018 (const_string "load_ext_ux")
1019 (if_then_else
1020 (match_test "update_address_mem (operands[1], VOIDmode)")
1021 (const_string "load_ext_u")
1022 (const_string "load_ext")))
1023 (const_string "exts")])])
1025 (define_insn ""
1026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1027 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1028 "!rs6000_gen_cell_microcode"
1029 "extsh %0,%1"
1030 [(set_attr "type" "exts")])
1032 (define_insn ""
1033 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1034 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1035 (const_int 0)))
1036 (clobber (match_scratch:SI 2 "=r,r"))]
1037 ""
1038 "@
1039 extsh. %2,%1
1040 #"
1041 [(set_attr "type" "compare")
1042 (set_attr "length" "4,8")])
1044 (define_split
1045 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1046 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1047 (const_int 0)))
1048 (clobber (match_scratch:SI 2 ""))]
1049 "reload_completed"
1050 [(set (match_dup 2)
1051 (sign_extend:SI (match_dup 1)))
1052 (set (match_dup 0)
1053 (compare:CC (match_dup 2)
1054 (const_int 0)))]
1055 "")
1057 (define_insn ""
1058 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1059 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1060 (const_int 0)))
1061 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1062 (sign_extend:SI (match_dup 1)))]
1063 ""
1064 "@
1065 extsh. %0,%1
1066 #"
1067 [(set_attr "type" "compare")
1068 (set_attr "length" "4,8")])
1070 (define_split
1071 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1072 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1073 (const_int 0)))
1074 (set (match_operand:SI 0 "gpc_reg_operand" "")
1075 (sign_extend:SI (match_dup 1)))]
1076 "reload_completed"
1077 [(set (match_dup 0)
1078 (sign_extend:SI (match_dup 1)))
1079 (set (match_dup 2)
1080 (compare:CC (match_dup 0)
1081 (const_int 0)))]
1082 "")
1083 \f
1084 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1086 (define_insn "*macchwc"
1087 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1088 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1089 (match_operand:SI 2 "gpc_reg_operand" "r")
1090 (const_int 16))
1091 (sign_extend:SI
1092 (match_operand:HI 1 "gpc_reg_operand" "r")))
1093 (match_operand:SI 4 "gpc_reg_operand" "0"))
1094 (const_int 0)))
1095 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (plus:SI (mult:SI (ashiftrt:SI
1097 (match_dup 2)
1098 (const_int 16))
1099 (sign_extend:SI
1100 (match_dup 1)))
1101 (match_dup 4)))]
1102 "TARGET_MULHW"
1103 "macchw. %0,%1,%2"
1104 [(set_attr "type" "imul3")])
1106 (define_insn "*macchw"
1107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1108 (plus:SI (mult:SI (ashiftrt:SI
1109 (match_operand:SI 2 "gpc_reg_operand" "r")
1110 (const_int 16))
1111 (sign_extend:SI
1112 (match_operand:HI 1 "gpc_reg_operand" "r")))
1113 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1114 "TARGET_MULHW"
1115 "macchw %0,%1,%2"
1116 [(set_attr "type" "imul3")])
1118 (define_insn "*macchwuc"
1119 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1120 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1121 (match_operand:SI 2 "gpc_reg_operand" "r")
1122 (const_int 16))
1123 (zero_extend:SI
1124 (match_operand:HI 1 "gpc_reg_operand" "r")))
1125 (match_operand:SI 4 "gpc_reg_operand" "0"))
1126 (const_int 0)))
1127 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1128 (plus:SI (mult:SI (lshiftrt:SI
1129 (match_dup 2)
1130 (const_int 16))
1131 (zero_extend:SI
1132 (match_dup 1)))
1133 (match_dup 4)))]
1134 "TARGET_MULHW"
1135 "macchwu. %0,%1,%2"
1136 [(set_attr "type" "imul3")])
1138 (define_insn "*macchwu"
1139 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (plus:SI (mult:SI (lshiftrt:SI
1141 (match_operand:SI 2 "gpc_reg_operand" "r")
1142 (const_int 16))
1143 (zero_extend:SI
1144 (match_operand:HI 1 "gpc_reg_operand" "r")))
1145 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1146 "TARGET_MULHW"
1147 "macchwu %0,%1,%2"
1148 [(set_attr "type" "imul3")])
1150 (define_insn "*machhwc"
1151 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1152 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1153 (match_operand:SI 1 "gpc_reg_operand" "%r")
1154 (const_int 16))
1155 (ashiftrt:SI
1156 (match_operand:SI 2 "gpc_reg_operand" "r")
1157 (const_int 16)))
1158 (match_operand:SI 4 "gpc_reg_operand" "0"))
1159 (const_int 0)))
1160 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (plus:SI (mult:SI (ashiftrt:SI
1162 (match_dup 1)
1163 (const_int 16))
1164 (ashiftrt:SI
1165 (match_dup 2)
1166 (const_int 16)))
1167 (match_dup 4)))]
1168 "TARGET_MULHW"
1169 "machhw. %0,%1,%2"
1170 [(set_attr "type" "imul3")])
1172 (define_insn "*machhw"
1173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1174 (plus:SI (mult:SI (ashiftrt:SI
1175 (match_operand:SI 1 "gpc_reg_operand" "%r")
1176 (const_int 16))
1177 (ashiftrt:SI
1178 (match_operand:SI 2 "gpc_reg_operand" "r")
1179 (const_int 16)))
1180 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1181 "TARGET_MULHW"
1182 "machhw %0,%1,%2"
1183 [(set_attr "type" "imul3")])
1185 (define_insn "*machhwuc"
1186 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1187 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1188 (match_operand:SI 1 "gpc_reg_operand" "%r")
1189 (const_int 16))
1190 (lshiftrt:SI
1191 (match_operand:SI 2 "gpc_reg_operand" "r")
1192 (const_int 16)))
1193 (match_operand:SI 4 "gpc_reg_operand" "0"))
1194 (const_int 0)))
1195 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (plus:SI (mult:SI (lshiftrt:SI
1197 (match_dup 1)
1198 (const_int 16))
1199 (lshiftrt:SI
1200 (match_dup 2)
1201 (const_int 16)))
1202 (match_dup 4)))]
1203 "TARGET_MULHW"
1204 "machhwu. %0,%1,%2"
1205 [(set_attr "type" "imul3")])
1207 (define_insn "*machhwu"
1208 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (plus:SI (mult:SI (lshiftrt:SI
1210 (match_operand:SI 1 "gpc_reg_operand" "%r")
1211 (const_int 16))
1212 (lshiftrt:SI
1213 (match_operand:SI 2 "gpc_reg_operand" "r")
1214 (const_int 16)))
1215 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1216 "TARGET_MULHW"
1217 "machhwu %0,%1,%2"
1218 [(set_attr "type" "imul3")])
1220 (define_insn "*maclhwc"
1221 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1222 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1223 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1224 (sign_extend:SI
1225 (match_operand:HI 2 "gpc_reg_operand" "r")))
1226 (match_operand:SI 4 "gpc_reg_operand" "0"))
1227 (const_int 0)))
1228 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1229 (plus:SI (mult:SI (sign_extend:SI
1230 (match_dup 1))
1231 (sign_extend:SI
1232 (match_dup 2)))
1233 (match_dup 4)))]
1234 "TARGET_MULHW"
1235 "maclhw. %0,%1,%2"
1236 [(set_attr "type" "imul3")])
1238 (define_insn "*maclhw"
1239 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1240 (plus:SI (mult:SI (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1242 (sign_extend:SI
1243 (match_operand:HI 2 "gpc_reg_operand" "r")))
1244 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1245 "TARGET_MULHW"
1246 "maclhw %0,%1,%2"
1247 [(set_attr "type" "imul3")])
1249 (define_insn "*maclhwuc"
1250 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1251 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1252 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1253 (zero_extend:SI
1254 (match_operand:HI 2 "gpc_reg_operand" "r")))
1255 (match_operand:SI 4 "gpc_reg_operand" "0"))
1256 (const_int 0)))
1257 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1258 (plus:SI (mult:SI (zero_extend:SI
1259 (match_dup 1))
1260 (zero_extend:SI
1261 (match_dup 2)))
1262 (match_dup 4)))]
1263 "TARGET_MULHW"
1264 "maclhwu. %0,%1,%2"
1265 [(set_attr "type" "imul3")])
1267 (define_insn "*maclhwu"
1268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1269 (plus:SI (mult:SI (zero_extend:SI
1270 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1271 (zero_extend:SI
1272 (match_operand:HI 2 "gpc_reg_operand" "r")))
1273 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1274 "TARGET_MULHW"
1275 "maclhwu %0,%1,%2"
1276 [(set_attr "type" "imul3")])
1278 (define_insn "*nmacchwc"
1279 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1280 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1281 (mult:SI (ashiftrt:SI
1282 (match_operand:SI 2 "gpc_reg_operand" "r")
1283 (const_int 16))
1284 (sign_extend:SI
1285 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1286 (const_int 0)))
1287 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1288 (minus:SI (match_dup 4)
1289 (mult:SI (ashiftrt:SI
1290 (match_dup 2)
1291 (const_int 16))
1292 (sign_extend:SI
1293 (match_dup 1)))))]
1294 "TARGET_MULHW"
1295 "nmacchw. %0,%1,%2"
1296 [(set_attr "type" "imul3")])
1298 (define_insn "*nmacchw"
1299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1301 (mult:SI (ashiftrt:SI
1302 (match_operand:SI 2 "gpc_reg_operand" "r")
1303 (const_int 16))
1304 (sign_extend:SI
1305 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1306 "TARGET_MULHW"
1307 "nmacchw %0,%1,%2"
1308 [(set_attr "type" "imul3")])
1310 (define_insn "*nmachhwc"
1311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1312 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1313 (mult:SI (ashiftrt:SI
1314 (match_operand:SI 1 "gpc_reg_operand" "%r")
1315 (const_int 16))
1316 (ashiftrt:SI
1317 (match_operand:SI 2 "gpc_reg_operand" "r")
1318 (const_int 16))))
1319 (const_int 0)))
1320 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1321 (minus:SI (match_dup 4)
1322 (mult:SI (ashiftrt:SI
1323 (match_dup 1)
1324 (const_int 16))
1325 (ashiftrt:SI
1326 (match_dup 2)
1327 (const_int 16)))))]
1328 "TARGET_MULHW"
1329 "nmachhw. %0,%1,%2"
1330 [(set_attr "type" "imul3")])
1332 (define_insn "*nmachhw"
1333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1335 (mult:SI (ashiftrt:SI
1336 (match_operand:SI 1 "gpc_reg_operand" "%r")
1337 (const_int 16))
1338 (ashiftrt:SI
1339 (match_operand:SI 2 "gpc_reg_operand" "r")
1340 (const_int 16)))))]
1341 "TARGET_MULHW"
1342 "nmachhw %0,%1,%2"
1343 [(set_attr "type" "imul3")])
1345 (define_insn "*nmaclhwc"
1346 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1347 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1348 (mult:SI (sign_extend:SI
1349 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1350 (sign_extend:SI
1351 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1352 (const_int 0)))
1353 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1354 (minus:SI (match_dup 4)
1355 (mult:SI (sign_extend:SI
1356 (match_dup 1))
1357 (sign_extend:SI
1358 (match_dup 2)))))]
1359 "TARGET_MULHW"
1360 "nmaclhw. %0,%1,%2"
1361 [(set_attr "type" "imul3")])
1363 (define_insn "*nmaclhw"
1364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1366 (mult:SI (sign_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (sign_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1370 "TARGET_MULHW"
1371 "nmaclhw %0,%1,%2"
1372 [(set_attr "type" "imul3")])
1374 (define_insn "*mulchwc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (ashiftrt:SI
1377 (match_operand:SI 2 "gpc_reg_operand" "r")
1378 (const_int 16))
1379 (sign_extend:SI
1380 (match_operand:HI 1 "gpc_reg_operand" "r")))
1381 (const_int 0)))
1382 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1383 (mult:SI (ashiftrt:SI
1384 (match_dup 2)
1385 (const_int 16))
1386 (sign_extend:SI
1387 (match_dup 1))))]
1388 "TARGET_MULHW"
1389 "mulchw. %0,%1,%2"
1390 [(set_attr "type" "imul3")])
1392 (define_insn "*mulchw"
1393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1394 (mult:SI (ashiftrt:SI
1395 (match_operand:SI 2 "gpc_reg_operand" "r")
1396 (const_int 16))
1397 (sign_extend:SI
1398 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1399 "TARGET_MULHW"
1400 "mulchw %0,%1,%2"
1401 [(set_attr "type" "imul3")])
1403 (define_insn "*mulchwuc"
1404 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1405 (compare:CC (mult:SI (lshiftrt:SI
1406 (match_operand:SI 2 "gpc_reg_operand" "r")
1407 (const_int 16))
1408 (zero_extend:SI
1409 (match_operand:HI 1 "gpc_reg_operand" "r")))
1410 (const_int 0)))
1411 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1412 (mult:SI (lshiftrt:SI
1413 (match_dup 2)
1414 (const_int 16))
1415 (zero_extend:SI
1416 (match_dup 1))))]
1417 "TARGET_MULHW"
1418 "mulchwu. %0,%1,%2"
1419 [(set_attr "type" "imul3")])
1421 (define_insn "*mulchwu"
1422 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1423 (mult:SI (lshiftrt:SI
1424 (match_operand:SI 2 "gpc_reg_operand" "r")
1425 (const_int 16))
1426 (zero_extend:SI
1427 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1428 "TARGET_MULHW"
1429 "mulchwu %0,%1,%2"
1430 [(set_attr "type" "imul3")])
1432 (define_insn "*mulhhwc"
1433 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1434 (compare:CC (mult:SI (ashiftrt:SI
1435 (match_operand:SI 1 "gpc_reg_operand" "%r")
1436 (const_int 16))
1437 (ashiftrt:SI
1438 (match_operand:SI 2 "gpc_reg_operand" "r")
1439 (const_int 16)))
1440 (const_int 0)))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1442 (mult:SI (ashiftrt:SI
1443 (match_dup 1)
1444 (const_int 16))
1445 (ashiftrt:SI
1446 (match_dup 2)
1447 (const_int 16))))]
1448 "TARGET_MULHW"
1449 "mulhhw. %0,%1,%2"
1450 [(set_attr "type" "imul3")])
1452 (define_insn "*mulhhw"
1453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1454 (mult:SI (ashiftrt:SI
1455 (match_operand:SI 1 "gpc_reg_operand" "%r")
1456 (const_int 16))
1457 (ashiftrt:SI
1458 (match_operand:SI 2 "gpc_reg_operand" "r")
1459 (const_int 16))))]
1460 "TARGET_MULHW"
1461 "mulhhw %0,%1,%2"
1462 [(set_attr "type" "imul3")])
1464 (define_insn "*mulhhwuc"
1465 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1466 (compare:CC (mult:SI (lshiftrt:SI
1467 (match_operand:SI 1 "gpc_reg_operand" "%r")
1468 (const_int 16))
1469 (lshiftrt:SI
1470 (match_operand:SI 2 "gpc_reg_operand" "r")
1471 (const_int 16)))
1472 (const_int 0)))
1473 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1474 (mult:SI (lshiftrt:SI
1475 (match_dup 1)
1476 (const_int 16))
1477 (lshiftrt:SI
1478 (match_dup 2)
1479 (const_int 16))))]
1480 "TARGET_MULHW"
1481 "mulhhwu. %0,%1,%2"
1482 [(set_attr "type" "imul3")])
1484 (define_insn "*mulhhwu"
1485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1486 (mult:SI (lshiftrt:SI
1487 (match_operand:SI 1 "gpc_reg_operand" "%r")
1488 (const_int 16))
1489 (lshiftrt:SI
1490 (match_operand:SI 2 "gpc_reg_operand" "r")
1491 (const_int 16))))]
1492 "TARGET_MULHW"
1493 "mulhhwu %0,%1,%2"
1494 [(set_attr "type" "imul3")])
1496 (define_insn "*mullhwc"
1497 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1498 (compare:CC (mult:SI (sign_extend:SI
1499 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1500 (sign_extend:SI
1501 (match_operand:HI 2 "gpc_reg_operand" "r")))
1502 (const_int 0)))
1503 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1504 (mult:SI (sign_extend:SI
1505 (match_dup 1))
1506 (sign_extend:SI
1507 (match_dup 2))))]
1508 "TARGET_MULHW"
1509 "mullhw. %0,%1,%2"
1510 [(set_attr "type" "imul3")])
1512 (define_insn "*mullhw"
1513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1514 (mult:SI (sign_extend:SI
1515 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1516 (sign_extend:SI
1517 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1518 "TARGET_MULHW"
1519 "mullhw %0,%1,%2"
1520 [(set_attr "type" "imul3")])
1522 (define_insn "*mullhwuc"
1523 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1524 (compare:CC (mult:SI (zero_extend:SI
1525 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1526 (zero_extend:SI
1527 (match_operand:HI 2 "gpc_reg_operand" "r")))
1528 (const_int 0)))
1529 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1530 (mult:SI (zero_extend:SI
1531 (match_dup 1))
1532 (zero_extend:SI
1533 (match_dup 2))))]
1534 "TARGET_MULHW"
1535 "mullhwu. %0,%1,%2"
1536 [(set_attr "type" "imul3")])
1538 (define_insn "*mullhwu"
1539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1540 (mult:SI (zero_extend:SI
1541 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1542 (zero_extend:SI
1543 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1544 "TARGET_MULHW"
1545 "mullhwu %0,%1,%2"
1546 [(set_attr "type" "imul3")])
1547 \f
1548 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1549 (define_insn "dlmzb"
1550 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1551 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1552 (match_operand:SI 2 "gpc_reg_operand" "r")]
1553 UNSPEC_DLMZB_CR))
1554 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1555 (unspec:SI [(match_dup 1)
1556 (match_dup 2)]
1557 UNSPEC_DLMZB))]
1558 "TARGET_DLMZB"
1559 "dlmzb. %0,%1,%2")
1561 (define_expand "strlensi"
1562 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1563 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1564 (match_operand:QI 2 "const_int_operand" "")
1565 (match_operand 3 "const_int_operand" "")]
1566 UNSPEC_DLMZB_STRLEN))
1567 (clobber (match_scratch:CC 4 "=x"))]
1568 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1569 {
1570 rtx result = operands[0];
1571 rtx src = operands[1];
1572 rtx search_char = operands[2];
1573 rtx align = operands[3];
1574 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1575 rtx loop_label, end_label, mem, cr0, cond;
1576 if (search_char != const0_rtx
1577 || GET_CODE (align) != CONST_INT
1578 || INTVAL (align) < 8)
1579 FAIL;
1580 word1 = gen_reg_rtx (SImode);
1581 word2 = gen_reg_rtx (SImode);
1582 scratch_dlmzb = gen_reg_rtx (SImode);
1583 scratch_string = gen_reg_rtx (Pmode);
1584 loop_label = gen_label_rtx ();
1585 end_label = gen_label_rtx ();
1586 addr = force_reg (Pmode, XEXP (src, 0));
1587 emit_move_insn (scratch_string, addr);
1588 emit_label (loop_label);
1589 mem = change_address (src, SImode, scratch_string);
1590 emit_move_insn (word1, mem);
1591 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1592 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1593 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1594 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1595 emit_jump_insn (gen_rtx_SET (VOIDmode,
1596 pc_rtx,
1597 gen_rtx_IF_THEN_ELSE (VOIDmode,
1598 cond,
1599 gen_rtx_LABEL_REF
1600 (VOIDmode,
1601 end_label),
1602 pc_rtx)));
1603 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1604 emit_jump_insn (gen_rtx_SET (VOIDmode,
1605 pc_rtx,
1606 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1607 emit_barrier ();
1608 emit_label (end_label);
1609 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1610 emit_insn (gen_subsi3 (result, scratch_string, addr));
1611 emit_insn (gen_subsi3 (result, result, const1_rtx));
1612 DONE;
1613 })
1614 \f
1615 ;; Fixed-point arithmetic insns.
1617 (define_expand "add<mode>3"
1618 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1619 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1620 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1621 ""
1622 {
1623 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1624 {
1625 if (non_short_cint_operand (operands[2], DImode))
1626 FAIL;
1627 }
1628 else if (GET_CODE (operands[2]) == CONST_INT
1629 && ! add_operand (operands[2], <MODE>mode))
1630 {
1631 rtx tmp = ((!can_create_pseudo_p ()
1632 || rtx_equal_p (operands[0], operands[1]))
1633 ? operands[0] : gen_reg_rtx (<MODE>mode));
1635 HOST_WIDE_INT val = INTVAL (operands[2]);
1636 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1637 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1639 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1640 FAIL;
1642 /* The ordering here is important for the prolog expander.
1643 When space is allocated from the stack, adding 'low' first may
1644 produce a temporary deallocation (which would be bad). */
1645 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1646 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1647 DONE;
1648 }
1649 })
1651 ;; Discourage ai/addic because of carry but provide it in an alternative
1652 ;; allowing register zero as source.
1653 (define_insn "*add<mode>3_internal1"
1654 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1655 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1656 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1657 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1658 "@
1659 add %0,%1,%2
1660 addi %0,%1,%2
1661 addic %0,%1,%2
1662 addis %0,%1,%v2"
1663 [(set_attr "length" "4,4,4,4")])
1665 (define_insn "addsi3_high"
1666 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1667 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1668 (high:SI (match_operand 2 "" ""))))]
1669 "TARGET_MACHO && !TARGET_64BIT"
1670 "addis %0,%1,ha16(%2)"
1671 [(set_attr "length" "4")])
1673 (define_insn "*add<mode>3_internal2"
1674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1675 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1676 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1677 (const_int 0)))
1678 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1679 ""
1680 "@
1681 add. %3,%1,%2
1682 addic. %3,%1,%2
1683 #
1684 #"
1685 [(set_attr "type" "fast_compare,compare,compare,compare")
1686 (set_attr "length" "4,4,8,8")])
1688 (define_split
1689 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1690 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1691 (match_operand:GPR 2 "reg_or_short_operand" ""))
1692 (const_int 0)))
1693 (clobber (match_scratch:GPR 3 ""))]
1694 "reload_completed"
1695 [(set (match_dup 3)
1696 (plus:GPR (match_dup 1)
1697 (match_dup 2)))
1698 (set (match_dup 0)
1699 (compare:CC (match_dup 3)
1700 (const_int 0)))]
1701 "")
1703 (define_insn "*add<mode>3_internal3"
1704 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1705 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1706 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1707 (const_int 0)))
1708 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1709 (plus:P (match_dup 1)
1710 (match_dup 2)))]
1711 ""
1712 "@
1713 add. %0,%1,%2
1714 addic. %0,%1,%2
1715 #
1716 #"
1717 [(set_attr "type" "fast_compare,compare,compare,compare")
1718 (set_attr "length" "4,4,8,8")])
1720 (define_split
1721 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1722 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1723 (match_operand:P 2 "reg_or_short_operand" ""))
1724 (const_int 0)))
1725 (set (match_operand:P 0 "gpc_reg_operand" "")
1726 (plus:P (match_dup 1) (match_dup 2)))]
1727 "reload_completed"
1728 [(set (match_dup 0)
1729 (plus:P (match_dup 1)
1730 (match_dup 2)))
1731 (set (match_dup 3)
1732 (compare:CC (match_dup 0)
1733 (const_int 0)))]
1734 "")
1736 ;; Split an add that we can't do in one insn into two insns, each of which
1737 ;; does one 16-bit part. This is used by combine. Note that the low-order
1738 ;; add should be last in case the result gets used in an address.
1740 (define_split
1741 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1742 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1743 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1744 ""
1745 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1746 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1747 {
1748 HOST_WIDE_INT val = INTVAL (operands[2]);
1749 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1750 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1752 operands[4] = GEN_INT (low);
1753 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1754 operands[3] = GEN_INT (rest);
1755 else if (can_create_pseudo_p ())
1756 {
1757 operands[3] = gen_reg_rtx (DImode);
1758 emit_move_insn (operands[3], operands[2]);
1759 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1760 DONE;
1761 }
1762 else
1763 FAIL;
1764 })
1766 (define_insn "one_cmpl<mode>2"
1767 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1768 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1769 ""
1770 "nor %0,%1,%1")
1772 (define_insn ""
1773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1774 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1775 (const_int 0)))
1776 (clobber (match_scratch:P 2 "=r,r"))]
1777 ""
1778 "@
1779 nor. %2,%1,%1
1780 #"
1781 [(set_attr "type" "fast_compare,compare")
1782 (set_attr "length" "4,8")])
1784 (define_split
1785 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1786 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1787 (const_int 0)))
1788 (clobber (match_scratch:P 2 ""))]
1789 "reload_completed"
1790 [(set (match_dup 2)
1791 (not:P (match_dup 1)))
1792 (set (match_dup 0)
1793 (compare:CC (match_dup 2)
1794 (const_int 0)))]
1795 "")
1797 (define_insn ""
1798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1799 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1800 (const_int 0)))
1801 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1802 (not:P (match_dup 1)))]
1803 ""
1804 "@
1805 nor. %0,%1,%1
1806 #"
1807 [(set_attr "type" "fast_compare,compare")
1808 (set_attr "length" "4,8")])
1810 (define_split
1811 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1812 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1813 (const_int 0)))
1814 (set (match_operand:P 0 "gpc_reg_operand" "")
1815 (not:P (match_dup 1)))]
1816 "reload_completed"
1817 [(set (match_dup 0)
1818 (not:P (match_dup 1)))
1819 (set (match_dup 2)
1820 (compare:CC (match_dup 0)
1821 (const_int 0)))]
1822 "")
1824 (define_insn ""
1825 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1826 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1827 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1828 ""
1829 "@
1830 subf %0,%2,%1
1831 subfic %0,%2,%1")
1833 (define_insn ""
1834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1835 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1836 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1837 (const_int 0)))
1838 (clobber (match_scratch:P 3 "=r,r"))]
1839 ""
1840 "@
1841 subf. %3,%2,%1
1842 #"
1843 [(set_attr "type" "fast_compare")
1844 (set_attr "length" "4,8")])
1846 (define_split
1847 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1848 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1849 (match_operand:P 2 "gpc_reg_operand" ""))
1850 (const_int 0)))
1851 (clobber (match_scratch:P 3 ""))]
1852 "reload_completed"
1853 [(set (match_dup 3)
1854 (minus:P (match_dup 1)
1855 (match_dup 2)))
1856 (set (match_dup 0)
1857 (compare:CC (match_dup 3)
1858 (const_int 0)))]
1859 "")
1861 (define_insn ""
1862 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1863 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1864 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1865 (const_int 0)))
1866 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1867 (minus:P (match_dup 1)
1868 (match_dup 2)))]
1869 ""
1870 "@
1871 subf. %0,%2,%1
1872 #"
1873 [(set_attr "type" "fast_compare")
1874 (set_attr "length" "4,8")])
1876 (define_split
1877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1878 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1879 (match_operand:P 2 "gpc_reg_operand" ""))
1880 (const_int 0)))
1881 (set (match_operand:P 0 "gpc_reg_operand" "")
1882 (minus:P (match_dup 1)
1883 (match_dup 2)))]
1884 "reload_completed"
1885 [(set (match_dup 0)
1886 (minus:P (match_dup 1)
1887 (match_dup 2)))
1888 (set (match_dup 3)
1889 (compare:CC (match_dup 0)
1890 (const_int 0)))]
1891 "")
1893 (define_expand "sub<mode>3"
1894 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1895 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1896 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1897 ""
1898 "
1899 {
1900 if (GET_CODE (operands[2]) == CONST_INT)
1901 {
1902 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1903 negate_rtx (<MODE>mode, operands[2])));
1904 DONE;
1905 }
1906 }")
1908 (define_expand "neg<mode>2"
1909 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1910 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1911 ""
1912 "")
1914 (define_insn "*neg<mode>2_internal"
1915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1916 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1917 ""
1918 "neg %0,%1")
1920 (define_insn ""
1921 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1922 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1923 (const_int 0)))
1924 (clobber (match_scratch:P 2 "=r,r"))]
1925 ""
1926 "@
1927 neg. %2,%1
1928 #"
1929 [(set_attr "type" "fast_compare")
1930 (set_attr "length" "4,8")])
1932 (define_split
1933 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1934 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1935 (const_int 0)))
1936 (clobber (match_scratch:P 2 ""))]
1937 "reload_completed"
1938 [(set (match_dup 2)
1939 (neg:P (match_dup 1)))
1940 (set (match_dup 0)
1941 (compare:CC (match_dup 2)
1942 (const_int 0)))]
1943 "")
1945 (define_insn ""
1946 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1947 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1948 (const_int 0)))
1949 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1950 (neg:P (match_dup 1)))]
1951 ""
1952 "@
1953 neg. %0,%1
1954 #"
1955 [(set_attr "type" "fast_compare")
1956 (set_attr "length" "4,8")])
1958 (define_split
1959 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1960 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1961 (const_int 0)))
1962 (set (match_operand:P 0 "gpc_reg_operand" "")
1963 (neg:P (match_dup 1)))]
1964 "reload_completed"
1965 [(set (match_dup 0)
1966 (neg:P (match_dup 1)))
1967 (set (match_dup 2)
1968 (compare:CC (match_dup 0)
1969 (const_int 0)))]
1970 "")
1972 (define_insn "clz<mode>2"
1973 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1974 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1975 ""
1976 "cntlz<wd> %0,%1"
1977 [(set_attr "type" "cntlz")])
1979 (define_expand "ctz<mode>2"
1980 [(set (match_dup 2)
1981 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1982 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1983 (match_dup 2)))
1984 (clobber (scratch:CC))])
1985 (set (match_dup 4) (clz:GPR (match_dup 3)))
1986 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1987 (minus:GPR (match_dup 5) (match_dup 4)))]
1988 ""
1989 {
1990 operands[2] = gen_reg_rtx (<MODE>mode);
1991 operands[3] = gen_reg_rtx (<MODE>mode);
1992 operands[4] = gen_reg_rtx (<MODE>mode);
1993 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1994 })
1996 (define_expand "ffs<mode>2"
1997 [(set (match_dup 2)
1998 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1999 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2000 (match_dup 2)))
2001 (clobber (scratch:CC))])
2002 (set (match_dup 4) (clz:GPR (match_dup 3)))
2003 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2004 (minus:GPR (match_dup 5) (match_dup 4)))]
2005 ""
2006 {
2007 operands[2] = gen_reg_rtx (<MODE>mode);
2008 operands[3] = gen_reg_rtx (<MODE>mode);
2009 operands[4] = gen_reg_rtx (<MODE>mode);
2010 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2011 })
2013 (define_insn "popcntb<mode>2"
2014 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2015 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2016 UNSPEC_POPCNTB))]
2017 "TARGET_POPCNTB"
2018 "popcntb %0,%1"
2019 [(set_attr "length" "4")
2020 (set_attr "type" "popcnt")])
2022 (define_insn "popcntd<mode>2"
2023 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2024 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2025 "TARGET_POPCNTD"
2026 "popcnt<wd> %0,%1"
2027 [(set_attr "length" "4")
2028 (set_attr "type" "popcnt")])
2030 (define_expand "popcount<mode>2"
2031 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2032 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2033 "TARGET_POPCNTB || TARGET_POPCNTD"
2034 {
2035 rs6000_emit_popcount (operands[0], operands[1]);
2036 DONE;
2037 })
2039 (define_insn "parity<mode>2_cmpb"
2040 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2041 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2042 "TARGET_CMPB && TARGET_POPCNTB"
2043 "prty<wd> %0,%1")
2045 (define_expand "parity<mode>2"
2046 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2047 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2048 "TARGET_POPCNTB"
2049 {
2050 rs6000_emit_parity (operands[0], operands[1]);
2051 DONE;
2052 })
2054 ;; Since the hardware zeros the upper part of the register, save generating the
2055 ;; AND immediate if we are converting to unsigned
2056 (define_insn "*bswaphi2_extenddi"
2057 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2058 (zero_extend:DI
2059 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2060 "TARGET_POWERPC64"
2061 "lhbrx %0,%y1"
2062 [(set_attr "length" "4")
2063 (set_attr "type" "load")])
2065 (define_insn "*bswaphi2_extendsi"
2066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2067 (zero_extend:SI
2068 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2069 ""
2070 "lhbrx %0,%y1"
2071 [(set_attr "length" "4")
2072 (set_attr "type" "load")])
2074 (define_expand "bswaphi2"
2075 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2076 (bswap:HI
2077 (match_operand:HI 1 "reg_or_mem_operand" "")))
2078 (clobber (match_scratch:SI 2 ""))])]
2079 ""
2080 {
2081 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2082 operands[1] = force_reg (HImode, operands[1]);
2083 })
2085 (define_insn "bswaphi2_internal"
2086 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2087 (bswap:HI
2088 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2089 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2090 ""
2091 "@
2092 lhbrx %0,%y1
2093 sthbrx %1,%y0
2094 #"
2095 [(set_attr "length" "4,4,12")
2096 (set_attr "type" "load,store,*")])
2098 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2099 ;; correct for -mlittle as well as -mbig.
2100 (define_split
2101 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2102 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2103 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2104 "reload_completed"
2105 [(set (match_dup 3)
2106 (zero_extract:SI (match_dup 4)
2107 (const_int 8)
2108 (const_int 16)))
2109 (set (match_dup 2)
2110 (and:SI (ashift:SI (match_dup 4)
2111 (const_int 8))
2112 (const_int 65280))) ;; 0xff00
2113 (set (match_dup 3)
2114 (ior:SI (match_dup 3)
2115 (match_dup 2)))]
2116 "
2117 {
2118 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2119 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2120 }")
2122 (define_insn "*bswapsi2_extenddi"
2123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2124 (zero_extend:DI
2125 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2126 "TARGET_POWERPC64"
2127 "lwbrx %0,%y1"
2128 [(set_attr "length" "4")
2129 (set_attr "type" "load")])
2131 (define_expand "bswapsi2"
2132 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2133 (bswap:SI
2134 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2135 ""
2136 {
2137 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2138 operands[1] = force_reg (SImode, operands[1]);
2139 })
2141 (define_insn "*bswapsi2_internal"
2142 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2143 (bswap:SI
2144 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2145 ""
2146 "@
2147 lwbrx %0,%y1
2148 stwbrx %1,%y0
2149 #"
2150 [(set_attr "length" "4,4,12")
2151 (set_attr "type" "load,store,*")])
2153 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2154 ;; zero_extract insns do not change for -mlittle.
2155 (define_split
2156 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2157 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2158 "reload_completed"
2159 [(set (match_dup 0)
2160 (rotate:SI (match_dup 1) (const_int 8)))
2161 (set (zero_extract:SI (match_dup 0)
2162 (const_int 8)
2163 (const_int 0))
2164 (match_dup 1))
2165 (set (zero_extract:SI (match_dup 0)
2166 (const_int 8)
2167 (const_int 16))
2168 (rotate:SI (match_dup 1)
2169 (const_int 16)))]
2170 "")
2172 (define_expand "bswapdi2"
2173 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2174 (bswap:DI
2175 (match_operand:DI 1 "reg_or_mem_operand" "")))
2176 (clobber (match_scratch:DI 2 ""))
2177 (clobber (match_scratch:DI 3 ""))
2178 (clobber (match_scratch:DI 4 ""))])]
2179 ""
2180 {
2181 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2182 operands[1] = force_reg (DImode, operands[1]);
2184 if (!TARGET_POWERPC64)
2185 {
2186 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2187 that uses 64-bit registers needs the same scratch registers as 64-bit
2188 mode. */
2189 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2190 DONE;
2191 }
2192 })
2194 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2195 (define_insn "*bswapdi2_ldbrx"
2196 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2197 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2198 (clobber (match_scratch:DI 2 "=X,X,&r"))
2199 (clobber (match_scratch:DI 3 "=X,X,&r"))
2200 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2201 "TARGET_POWERPC64 && TARGET_LDBRX
2202 && (REG_P (operands[0]) || REG_P (operands[1]))"
2203 "@
2204 ldbrx %0,%y1
2205 stdbrx %1,%y0
2206 #"
2207 [(set_attr "length" "4,4,36")
2208 (set_attr "type" "load,store,*")])
2210 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2211 (define_insn "*bswapdi2_64bit"
2212 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2213 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2214 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2215 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2216 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2217 "TARGET_POWERPC64 && !TARGET_LDBRX
2218 && (REG_P (operands[0]) || REG_P (operands[1]))"
2219 "#"
2220 [(set_attr "length" "16,12,36")])
2222 (define_split
2223 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2224 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2225 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2226 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2227 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2228 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2229 [(const_int 0)]
2230 "
2231 {
2232 rtx dest = operands[0];
2233 rtx src = operands[1];
2234 rtx op2 = operands[2];
2235 rtx op3 = operands[3];
2236 rtx op4 = operands[4];
2237 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2238 BYTES_BIG_ENDIAN ? 4 : 0);
2239 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2240 BYTES_BIG_ENDIAN ? 4 : 0);
2241 rtx addr1;
2242 rtx addr2;
2243 rtx word_high;
2244 rtx word_low;
2246 addr1 = XEXP (src, 0);
2247 if (GET_CODE (addr1) == PLUS)
2248 {
2249 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2250 if (TARGET_AVOID_XFORM)
2251 {
2252 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2253 addr2 = op2;
2254 }
2255 else
2256 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2257 }
2258 else if (TARGET_AVOID_XFORM)
2259 {
2260 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2261 addr2 = op2;
2262 }
2263 else
2264 {
2265 emit_move_insn (op2, GEN_INT (4));
2266 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2267 }
2269 if (BYTES_BIG_ENDIAN)
2270 {
2271 word_high = change_address (src, SImode, addr1);
2272 word_low = change_address (src, SImode, addr2);
2273 }
2274 else
2275 {
2276 word_high = change_address (src, SImode, addr2);
2277 word_low = change_address (src, SImode, addr1);
2278 }
2280 emit_insn (gen_bswapsi2 (op3_32, word_low));
2281 emit_insn (gen_bswapsi2 (op4_32, word_high));
2282 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2283 emit_insn (gen_iordi3 (dest, dest, op4));
2284 }")
2286 (define_split
2287 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2288 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2289 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2290 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2291 (clobber (match_operand:DI 4 "" ""))]
2292 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2293 [(const_int 0)]
2294 "
2295 {
2296 rtx dest = operands[0];
2297 rtx src = operands[1];
2298 rtx op2 = operands[2];
2299 rtx op3 = operands[3];
2300 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2301 BYTES_BIG_ENDIAN ? 4 : 0);
2302 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2303 BYTES_BIG_ENDIAN ? 4 : 0);
2304 rtx addr1;
2305 rtx addr2;
2306 rtx word_high;
2307 rtx word_low;
2309 addr1 = XEXP (dest, 0);
2310 if (GET_CODE (addr1) == PLUS)
2311 {
2312 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2313 if (TARGET_AVOID_XFORM)
2314 {
2315 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2316 addr2 = op2;
2317 }
2318 else
2319 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2320 }
2321 else if (TARGET_AVOID_XFORM)
2322 {
2323 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2324 addr2 = op2;
2325 }
2326 else
2327 {
2328 emit_move_insn (op2, GEN_INT (4));
2329 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2330 }
2332 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2333 if (BYTES_BIG_ENDIAN)
2334 {
2335 word_high = change_address (dest, SImode, addr1);
2336 word_low = change_address (dest, SImode, addr2);
2337 }
2338 else
2339 {
2340 word_high = change_address (dest, SImode, addr2);
2341 word_low = change_address (dest, SImode, addr1);
2342 }
2343 emit_insn (gen_bswapsi2 (word_high, src_si));
2344 emit_insn (gen_bswapsi2 (word_low, op3_si));
2345 }")
2347 (define_split
2348 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2349 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2350 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2351 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2352 (clobber (match_operand:DI 4 "" ""))]
2353 "TARGET_POWERPC64 && reload_completed"
2354 [(const_int 0)]
2355 "
2356 {
2357 rtx dest = operands[0];
2358 rtx src = operands[1];
2359 rtx op2 = operands[2];
2360 rtx op3 = operands[3];
2361 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2362 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2363 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2364 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2365 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2367 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2368 emit_insn (gen_bswapsi2 (dest_si, src_si));
2369 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2370 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2371 emit_insn (gen_iordi3 (dest, dest, op3));
2372 }")
2374 (define_insn "bswapdi2_32bit"
2375 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2376 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2377 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2378 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2379 "#"
2380 [(set_attr "length" "16,12,36")])
2382 (define_split
2383 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2384 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2385 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2386 "!TARGET_POWERPC64 && reload_completed"
2387 [(const_int 0)]
2388 "
2389 {
2390 rtx dest = operands[0];
2391 rtx src = operands[1];
2392 rtx op2 = operands[2];
2393 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2394 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2395 rtx addr1;
2396 rtx addr2;
2397 rtx word1;
2398 rtx word2;
2400 addr1 = XEXP (src, 0);
2401 if (GET_CODE (addr1) == PLUS)
2402 {
2403 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2404 if (TARGET_AVOID_XFORM)
2405 {
2406 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2407 addr2 = op2;
2408 }
2409 else
2410 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2411 }
2412 else if (TARGET_AVOID_XFORM)
2413 {
2414 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2415 addr2 = op2;
2416 }
2417 else
2418 {
2419 emit_move_insn (op2, GEN_INT (4));
2420 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2421 }
2423 word1 = change_address (src, SImode, addr1);
2424 word2 = change_address (src, SImode, addr2);
2426 emit_insn (gen_bswapsi2 (dest2, word1));
2427 emit_insn (gen_bswapsi2 (dest1, word2));
2428 }")
2430 (define_split
2431 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2432 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2433 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2434 "!TARGET_POWERPC64 && reload_completed"
2435 [(const_int 0)]
2436 "
2437 {
2438 rtx dest = operands[0];
2439 rtx src = operands[1];
2440 rtx op2 = operands[2];
2441 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2442 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2443 rtx addr1;
2444 rtx addr2;
2445 rtx word1;
2446 rtx word2;
2448 addr1 = XEXP (dest, 0);
2449 if (GET_CODE (addr1) == PLUS)
2450 {
2451 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2452 if (TARGET_AVOID_XFORM)
2453 {
2454 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2455 addr2 = op2;
2456 }
2457 else
2458 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2459 }
2460 else if (TARGET_AVOID_XFORM)
2461 {
2462 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2463 addr2 = op2;
2464 }
2465 else
2466 {
2467 emit_move_insn (op2, GEN_INT (4));
2468 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2469 }
2471 word1 = change_address (dest, SImode, addr1);
2472 word2 = change_address (dest, SImode, addr2);
2474 emit_insn (gen_bswapsi2 (word2, src1));
2475 emit_insn (gen_bswapsi2 (word1, src2));
2476 }")
2478 (define_split
2479 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2480 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2481 (clobber (match_operand:SI 2 "" ""))]
2482 "!TARGET_POWERPC64 && reload_completed"
2483 [(const_int 0)]
2484 "
2485 {
2486 rtx dest = operands[0];
2487 rtx src = operands[1];
2488 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2489 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2490 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2491 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2493 emit_insn (gen_bswapsi2 (dest1, src2));
2494 emit_insn (gen_bswapsi2 (dest2, src1));
2495 }")
2497 (define_insn "mulsi3"
2498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2499 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2500 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2501 ""
2502 "@
2503 mullw %0,%1,%2
2504 mulli %0,%1,%2"
2505 [(set (attr "type")
2506 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2507 (const_string "imul3")
2508 (match_operand:SI 2 "short_cint_operand" "")
2509 (const_string "imul2")]
2510 (const_string "imul")))])
2512 (define_insn "*mulsi3_internal1"
2513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2514 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2515 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2516 (const_int 0)))
2517 (clobber (match_scratch:SI 3 "=r,r"))]
2518 ""
2519 "@
2520 mullw. %3,%1,%2
2521 #"
2522 [(set_attr "type" "imul_compare")
2523 (set_attr "length" "4,8")])
2525 (define_split
2526 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2527 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2528 (match_operand:SI 2 "gpc_reg_operand" ""))
2529 (const_int 0)))
2530 (clobber (match_scratch:SI 3 ""))]
2531 "reload_completed"
2532 [(set (match_dup 3)
2533 (mult:SI (match_dup 1) (match_dup 2)))
2534 (set (match_dup 0)
2535 (compare:CC (match_dup 3)
2536 (const_int 0)))]
2537 "")
2539 (define_insn "*mulsi3_internal2"
2540 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2541 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2542 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2543 (const_int 0)))
2544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2545 (mult:SI (match_dup 1) (match_dup 2)))]
2546 ""
2547 "@
2548 mullw. %0,%1,%2
2549 #"
2550 [(set_attr "type" "imul_compare")
2551 (set_attr "length" "4,8")])
2553 (define_split
2554 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2555 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2556 (match_operand:SI 2 "gpc_reg_operand" ""))
2557 (const_int 0)))
2558 (set (match_operand:SI 0 "gpc_reg_operand" "")
2559 (mult:SI (match_dup 1) (match_dup 2)))]
2560 "reload_completed"
2561 [(set (match_dup 0)
2562 (mult:SI (match_dup 1) (match_dup 2)))
2563 (set (match_dup 3)
2564 (compare:CC (match_dup 0)
2565 (const_int 0)))]
2566 "")
2569 (define_insn "udiv<mode>3"
2570 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2571 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2572 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2573 ""
2574 "div<wd>u %0,%1,%2"
2575 [(set (attr "type")
2576 (cond [(match_operand:SI 0 "" "")
2577 (const_string "idiv")]
2578 (const_string "ldiv")))])
2581 ;; For powers of two we can do srai/aze for divide and then adjust for
2582 ;; modulus. If it isn't a power of two, force operands into register and do
2583 ;; a normal divide.
2584 (define_expand "div<mode>3"
2585 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2586 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2587 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2588 ""
2589 {
2590 if (GET_CODE (operands[2]) != CONST_INT
2591 || INTVAL (operands[2]) <= 0
2592 || exact_log2 (INTVAL (operands[2])) < 0)
2593 operands[2] = force_reg (<MODE>mode, operands[2]);
2594 })
2596 (define_insn "*div<mode>3"
2597 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2598 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2599 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2600 ""
2601 "div<wd> %0,%1,%2"
2602 [(set (attr "type")
2603 (cond [(match_operand:SI 0 "" "")
2604 (const_string "idiv")]
2605 (const_string "ldiv")))])
2607 (define_expand "mod<mode>3"
2608 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2609 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2610 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2611 ""
2612 "
2613 {
2614 int i;
2615 rtx temp1;
2616 rtx temp2;
2618 if (GET_CODE (operands[2]) != CONST_INT
2619 || INTVAL (operands[2]) <= 0
2620 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2621 FAIL;
2623 temp1 = gen_reg_rtx (<MODE>mode);
2624 temp2 = gen_reg_rtx (<MODE>mode);
2626 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2627 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2628 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2629 DONE;
2630 }")
2632 (define_insn ""
2633 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2634 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2635 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2636 ""
2637 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2638 [(set_attr "type" "two")
2639 (set_attr "length" "8")])
2641 (define_insn ""
2642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2643 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2644 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2645 (const_int 0)))
2646 (clobber (match_scratch:P 3 "=r,r"))]
2647 ""
2648 "@
2649 sra<wd>i %3,%1,%p2\;addze. %3,%3
2650 #"
2651 [(set_attr "type" "compare")
2652 (set_attr "length" "8,12")
2653 (set_attr "cell_micro" "not")])
2655 (define_split
2656 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2657 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2658 (match_operand:GPR 2 "exact_log2_cint_operand"
2659 ""))
2660 (const_int 0)))
2661 (clobber (match_scratch:GPR 3 ""))]
2662 "reload_completed"
2663 [(set (match_dup 3)
2664 (div:<MODE> (match_dup 1) (match_dup 2)))
2665 (set (match_dup 0)
2666 (compare:CC (match_dup 3)
2667 (const_int 0)))]
2668 "")
2670 (define_insn ""
2671 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2672 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2673 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2674 (const_int 0)))
2675 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2676 (div:P (match_dup 1) (match_dup 2)))]
2677 ""
2678 "@
2679 sra<wd>i %0,%1,%p2\;addze. %0,%0
2680 #"
2681 [(set_attr "type" "compare")
2682 (set_attr "length" "8,12")
2683 (set_attr "cell_micro" "not")])
2685 (define_split
2686 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2687 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2688 (match_operand:GPR 2 "exact_log2_cint_operand"
2689 ""))
2690 (const_int 0)))
2691 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2692 (div:GPR (match_dup 1) (match_dup 2)))]
2693 "reload_completed"
2694 [(set (match_dup 0)
2695 (div:<MODE> (match_dup 1) (match_dup 2)))
2696 (set (match_dup 3)
2697 (compare:CC (match_dup 0)
2698 (const_int 0)))]
2699 "")
2700 \f
2701 ;; Logical instructions
2702 ;; The logical instructions are mostly combined by using match_operator,
2703 ;; but the plain AND insns are somewhat different because there is no
2704 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2705 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2707 (define_expand "andsi3"
2708 [(parallel
2709 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2710 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2711 (match_operand:SI 2 "and_operand" "")))
2712 (clobber (match_scratch:CC 3 ""))])]
2713 ""
2714 "")
2716 (define_insn "andsi3_mc"
2717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2718 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2719 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2720 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2721 "rs6000_gen_cell_microcode"
2722 "@
2723 and %0,%1,%2
2724 rlwinm %0,%1,0,%m2,%M2
2725 andi. %0,%1,%b2
2726 andis. %0,%1,%u2"
2727 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2729 (define_insn "andsi3_nomc"
2730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2731 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2732 (match_operand:SI 2 "and_operand" "?r,T")))
2733 (clobber (match_scratch:CC 3 "=X,X"))]
2734 "!rs6000_gen_cell_microcode"
2735 "@
2736 and %0,%1,%2
2737 rlwinm %0,%1,0,%m2,%M2")
2739 (define_insn "andsi3_internal0_nomc"
2740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2741 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2742 (match_operand:SI 2 "and_operand" "?r,T")))]
2743 "!rs6000_gen_cell_microcode"
2744 "@
2745 and %0,%1,%2
2746 rlwinm %0,%1,0,%m2,%M2")
2749 ;; Note to set cr's other than cr0 we do the and immediate and then
2750 ;; the test again -- this avoids a mfcr which on the higher end
2751 ;; machines causes an execution serialization
2753 (define_insn "*andsi3_internal2_mc"
2754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2755 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2756 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2757 (const_int 0)))
2758 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2759 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2760 "TARGET_32BIT && rs6000_gen_cell_microcode"
2761 "@
2762 and. %3,%1,%2
2763 andi. %3,%1,%b2
2764 andis. %3,%1,%u2
2765 rlwinm. %3,%1,0,%m2,%M2
2766 #
2767 #
2768 #
2769 #"
2770 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2771 compare,compare,compare,compare")
2772 (set_attr "length" "4,4,4,4,8,8,8,8")])
2774 (define_insn "*andsi3_internal3_mc"
2775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2776 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2777 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2778 (const_int 0)))
2779 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2780 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2781 "TARGET_64BIT && rs6000_gen_cell_microcode"
2782 "@
2783 #
2784 andi. %3,%1,%b2
2785 andis. %3,%1,%u2
2786 rlwinm. %3,%1,0,%m2,%M2
2787 #
2788 #
2789 #
2790 #"
2791 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2792 compare,compare,compare")
2793 (set_attr "length" "8,4,4,4,8,8,8,8")])
2795 (define_split
2796 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2797 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2798 (match_operand:GPR 2 "and_operand" ""))
2799 (const_int 0)))
2800 (clobber (match_scratch:GPR 3 ""))
2801 (clobber (match_scratch:CC 4 ""))]
2802 "reload_completed"
2803 [(parallel [(set (match_dup 3)
2804 (and:<MODE> (match_dup 1)
2805 (match_dup 2)))
2806 (clobber (match_dup 4))])
2807 (set (match_dup 0)
2808 (compare:CC (match_dup 3)
2809 (const_int 0)))]
2810 "")
2812 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2813 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2815 (define_split
2816 [(set (match_operand:CC 0 "cc_reg_operand" "")
2817 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2818 (match_operand:SI 2 "gpc_reg_operand" ""))
2819 (const_int 0)))
2820 (clobber (match_scratch:SI 3 ""))
2821 (clobber (match_scratch:CC 4 ""))]
2822 "TARGET_POWERPC64 && reload_completed"
2823 [(parallel [(set (match_dup 3)
2824 (and:SI (match_dup 1)
2825 (match_dup 2)))
2826 (clobber (match_dup 4))])
2827 (set (match_dup 0)
2828 (compare:CC (match_dup 3)
2829 (const_int 0)))]
2830 "")
2832 (define_insn "*andsi3_internal4"
2833 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2834 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2835 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2836 (const_int 0)))
2837 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2838 (and:SI (match_dup 1)
2839 (match_dup 2)))
2840 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2841 "TARGET_32BIT && rs6000_gen_cell_microcode"
2842 "@
2843 and. %0,%1,%2
2844 andi. %0,%1,%b2
2845 andis. %0,%1,%u2
2846 rlwinm. %0,%1,0,%m2,%M2
2847 #
2848 #
2849 #
2850 #"
2851 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2852 compare,compare,compare,compare")
2853 (set_attr "length" "4,4,4,4,8,8,8,8")])
2855 (define_insn "*andsi3_internal5_mc"
2856 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2857 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2858 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2859 (const_int 0)))
2860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2861 (and:SI (match_dup 1)
2862 (match_dup 2)))
2863 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2864 "TARGET_64BIT && rs6000_gen_cell_microcode"
2865 "@
2866 #
2867 andi. %0,%1,%b2
2868 andis. %0,%1,%u2
2869 rlwinm. %0,%1,0,%m2,%M2
2870 #
2871 #
2872 #
2873 #"
2874 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2875 compare,compare,compare")
2876 (set_attr "length" "8,4,4,4,8,8,8,8")])
2878 (define_split
2879 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2880 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2881 (match_operand:SI 2 "and_operand" ""))
2882 (const_int 0)))
2883 (set (match_operand:SI 0 "gpc_reg_operand" "")
2884 (and:SI (match_dup 1)
2885 (match_dup 2)))
2886 (clobber (match_scratch:CC 4 ""))]
2887 "reload_completed"
2888 [(parallel [(set (match_dup 0)
2889 (and:SI (match_dup 1)
2890 (match_dup 2)))
2891 (clobber (match_dup 4))])
2892 (set (match_dup 3)
2893 (compare:CC (match_dup 0)
2894 (const_int 0)))]
2895 "")
2897 (define_split
2898 [(set (match_operand:CC 3 "cc_reg_operand" "")
2899 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2900 (match_operand:SI 2 "gpc_reg_operand" ""))
2901 (const_int 0)))
2902 (set (match_operand:SI 0 "gpc_reg_operand" "")
2903 (and:SI (match_dup 1)
2904 (match_dup 2)))
2905 (clobber (match_scratch:CC 4 ""))]
2906 "TARGET_POWERPC64 && reload_completed"
2907 [(parallel [(set (match_dup 0)
2908 (and:SI (match_dup 1)
2909 (match_dup 2)))
2910 (clobber (match_dup 4))])
2911 (set (match_dup 3)
2912 (compare:CC (match_dup 0)
2913 (const_int 0)))]
2914 "")
2916 ;; Handle the PowerPC64 rlwinm corner case
2918 (define_insn_and_split "*andsi3_internal6"
2919 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2920 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2921 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2922 "TARGET_POWERPC64"
2923 "#"
2924 "TARGET_POWERPC64"
2925 [(set (match_dup 0)
2926 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2927 (match_dup 4)))
2928 (set (match_dup 0)
2929 (rotate:SI (match_dup 0) (match_dup 5)))]
2930 "
2931 {
2932 int mb = extract_MB (operands[2]);
2933 int me = extract_ME (operands[2]);
2934 operands[3] = GEN_INT (me + 1);
2935 operands[5] = GEN_INT (32 - (me + 1));
2936 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2937 }"
2938 [(set_attr "length" "8")])
2940 (define_expand "iorsi3"
2941 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2942 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2943 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2944 ""
2945 "
2946 {
2947 if (GET_CODE (operands[2]) == CONST_INT
2948 && ! logical_operand (operands[2], SImode))
2949 {
2950 HOST_WIDE_INT value = INTVAL (operands[2]);
2951 rtx tmp = ((!can_create_pseudo_p ()
2952 || rtx_equal_p (operands[0], operands[1]))
2953 ? operands[0] : gen_reg_rtx (SImode));
2955 emit_insn (gen_iorsi3 (tmp, operands[1],
2956 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2957 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2958 DONE;
2959 }
2960 }")
2962 (define_expand "xorsi3"
2963 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2964 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2965 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2966 ""
2967 "
2968 {
2969 if (GET_CODE (operands[2]) == CONST_INT
2970 && ! logical_operand (operands[2], SImode))
2971 {
2972 HOST_WIDE_INT value = INTVAL (operands[2]);
2973 rtx tmp = ((!can_create_pseudo_p ()
2974 || rtx_equal_p (operands[0], operands[1]))
2975 ? operands[0] : gen_reg_rtx (SImode));
2977 emit_insn (gen_xorsi3 (tmp, operands[1],
2978 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2979 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2980 DONE;
2981 }
2982 }")
2984 (define_insn "*boolsi3_internal1"
2985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2986 (match_operator:SI 3 "boolean_or_operator"
2987 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2988 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2989 ""
2990 "@
2991 %q3 %0,%1,%2
2992 %q3i %0,%1,%b2
2993 %q3is %0,%1,%u2")
2995 (define_insn "*boolsi3_internal2"
2996 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2997 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2998 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2999 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3000 (const_int 0)))
3001 (clobber (match_scratch:SI 3 "=r,r"))]
3002 "TARGET_32BIT"
3003 "@
3004 %q4. %3,%1,%2
3005 #"
3006 [(set_attr "type" "fast_compare,compare")
3007 (set_attr "length" "4,8")])
3009 (define_split
3010 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3011 (compare:CC (match_operator:SI 4 "boolean_operator"
3012 [(match_operand:SI 1 "gpc_reg_operand" "")
3013 (match_operand:SI 2 "gpc_reg_operand" "")])
3014 (const_int 0)))
3015 (clobber (match_scratch:SI 3 ""))]
3016 "TARGET_32BIT && reload_completed"
3017 [(set (match_dup 3) (match_dup 4))
3018 (set (match_dup 0)
3019 (compare:CC (match_dup 3)
3020 (const_int 0)))]
3021 "")
3023 (define_insn "*boolsi3_internal3"
3024 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3025 (compare:CC (match_operator:SI 4 "boolean_operator"
3026 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3027 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3028 (const_int 0)))
3029 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3030 (match_dup 4))]
3031 "TARGET_32BIT"
3032 "@
3033 %q4. %0,%1,%2
3034 #"
3035 [(set_attr "type" "fast_compare,compare")
3036 (set_attr "length" "4,8")])
3038 (define_split
3039 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3040 (compare:CC (match_operator:SI 4 "boolean_operator"
3041 [(match_operand:SI 1 "gpc_reg_operand" "")
3042 (match_operand:SI 2 "gpc_reg_operand" "")])
3043 (const_int 0)))
3044 (set (match_operand:SI 0 "gpc_reg_operand" "")
3045 (match_dup 4))]
3046 "TARGET_32BIT && reload_completed"
3047 [(set (match_dup 0) (match_dup 4))
3048 (set (match_dup 3)
3049 (compare:CC (match_dup 0)
3050 (const_int 0)))]
3051 "")
3053 ;; Split a logical operation that we can't do in one insn into two insns,
3054 ;; each of which does one 16-bit part. This is used by combine.
3056 (define_split
3057 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3058 (match_operator:SI 3 "boolean_or_operator"
3059 [(match_operand:SI 1 "gpc_reg_operand" "")
3060 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3061 ""
3062 [(set (match_dup 0) (match_dup 4))
3063 (set (match_dup 0) (match_dup 5))]
3064 "
3065 {
3066 rtx i;
3067 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3068 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3069 operands[1], i);
3070 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3071 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3072 operands[0], i);
3073 }")
3075 (define_insn "*boolcsi3_internal1"
3076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3077 (match_operator:SI 3 "boolean_operator"
3078 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3079 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3080 ""
3081 "%q3 %0,%2,%1")
3083 (define_insn "*boolcsi3_internal2"
3084 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3085 (compare:CC (match_operator:SI 4 "boolean_operator"
3086 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3087 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3088 (const_int 0)))
3089 (clobber (match_scratch:SI 3 "=r,r"))]
3090 "TARGET_32BIT"
3091 "@
3092 %q4. %3,%2,%1
3093 #"
3094 [(set_attr "type" "compare")
3095 (set_attr "length" "4,8")])
3097 (define_split
3098 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3099 (compare:CC (match_operator:SI 4 "boolean_operator"
3100 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3101 (match_operand:SI 2 "gpc_reg_operand" "")])
3102 (const_int 0)))
3103 (clobber (match_scratch:SI 3 ""))]
3104 "TARGET_32BIT && reload_completed"
3105 [(set (match_dup 3) (match_dup 4))
3106 (set (match_dup 0)
3107 (compare:CC (match_dup 3)
3108 (const_int 0)))]
3109 "")
3111 (define_insn "*boolcsi3_internal3"
3112 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3113 (compare:CC (match_operator:SI 4 "boolean_operator"
3114 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3115 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3116 (const_int 0)))
3117 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3118 (match_dup 4))]
3119 "TARGET_32BIT"
3120 "@
3121 %q4. %0,%2,%1
3122 #"
3123 [(set_attr "type" "compare")
3124 (set_attr "length" "4,8")])
3126 (define_split
3127 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3128 (compare:CC (match_operator:SI 4 "boolean_operator"
3129 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3130 (match_operand:SI 2 "gpc_reg_operand" "")])
3131 (const_int 0)))
3132 (set (match_operand:SI 0 "gpc_reg_operand" "")
3133 (match_dup 4))]
3134 "TARGET_32BIT && reload_completed"
3135 [(set (match_dup 0) (match_dup 4))
3136 (set (match_dup 3)
3137 (compare:CC (match_dup 0)
3138 (const_int 0)))]
3139 "")
3141 (define_insn "*boolccsi3_internal1"
3142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3143 (match_operator:SI 3 "boolean_operator"
3144 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3145 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3146 ""
3147 "%q3 %0,%1,%2")
3149 (define_insn "*boolccsi3_internal2"
3150 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3151 (compare:CC (match_operator:SI 4 "boolean_operator"
3152 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3153 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3154 (const_int 0)))
3155 (clobber (match_scratch:SI 3 "=r,r"))]
3156 "TARGET_32BIT"
3157 "@
3158 %q4. %3,%1,%2
3159 #"
3160 [(set_attr "type" "fast_compare,compare")
3161 (set_attr "length" "4,8")])
3163 (define_split
3164 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3165 (compare:CC (match_operator:SI 4 "boolean_operator"
3166 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3167 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3168 (const_int 0)))
3169 (clobber (match_scratch:SI 3 ""))]
3170 "TARGET_32BIT && reload_completed"
3171 [(set (match_dup 3) (match_dup 4))
3172 (set (match_dup 0)
3173 (compare:CC (match_dup 3)
3174 (const_int 0)))]
3175 "")
3177 (define_insn "*boolccsi3_internal3"
3178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3179 (compare:CC (match_operator:SI 4 "boolean_operator"
3180 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3181 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3182 (const_int 0)))
3183 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3184 (match_dup 4))]
3185 "TARGET_32BIT"
3186 "@
3187 %q4. %0,%1,%2
3188 #"
3189 [(set_attr "type" "fast_compare,compare")
3190 (set_attr "length" "4,8")])
3192 (define_split
3193 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3194 (compare:CC (match_operator:SI 4 "boolean_operator"
3195 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3196 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3197 (const_int 0)))
3198 (set (match_operand:SI 0 "gpc_reg_operand" "")
3199 (match_dup 4))]
3200 "TARGET_32BIT && reload_completed"
3201 [(set (match_dup 0) (match_dup 4))
3202 (set (match_dup 3)
3203 (compare:CC (match_dup 0)
3204 (const_int 0)))]
3205 "")
3206 \f
3207 ;; Rotate and shift insns, in all their variants. These support shifts,
3208 ;; field inserts and extracts, and various combinations thereof.
3209 (define_expand "insv"
3210 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3211 (match_operand:SI 1 "const_int_operand" "")
3212 (match_operand:SI 2 "const_int_operand" ""))
3213 (match_operand 3 "gpc_reg_operand" ""))]
3214 ""
3215 "
3216 {
3217 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3218 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3219 compiler if the address of the structure is taken later. Likewise, do
3220 not handle invalid E500 subregs. */
3221 if (GET_CODE (operands[0]) == SUBREG
3222 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3223 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3224 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3225 FAIL;
3227 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3228 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3229 operands[3]));
3230 else
3231 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3232 operands[3]));
3233 DONE;
3234 }")
3236 (define_insn "insvsi_internal"
3237 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3238 (match_operand:SI 1 "const_int_operand" "i")
3239 (match_operand:SI 2 "const_int_operand" "i"))
3240 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3241 ""
3242 "*
3243 {
3244 int start = INTVAL (operands[2]) & 31;
3245 int size = INTVAL (operands[1]) & 31;
3247 operands[4] = GEN_INT (32 - start - size);
3248 operands[1] = GEN_INT (start + size - 1);
3249 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3250 }"
3251 [(set_attr "type" "insert_word")])
3253 (define_insn "*insvsi_internal1"
3254 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3255 (match_operand:SI 1 "const_int_operand" "i")
3256 (match_operand:SI 2 "const_int_operand" "i"))
3257 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3258 (match_operand:SI 4 "const_int_operand" "i")))]
3259 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3260 "*
3261 {
3262 int shift = INTVAL (operands[4]) & 31;
3263 int start = INTVAL (operands[2]) & 31;
3264 int size = INTVAL (operands[1]) & 31;
3266 operands[4] = GEN_INT (shift - start - size);
3267 operands[1] = GEN_INT (start + size - 1);
3268 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3269 }"
3270 [(set_attr "type" "insert_word")])
3272 (define_insn "*insvsi_internal2"
3273 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3274 (match_operand:SI 1 "const_int_operand" "i")
3275 (match_operand:SI 2 "const_int_operand" "i"))
3276 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3277 (match_operand:SI 4 "const_int_operand" "i")))]
3278 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3279 "*
3280 {
3281 int shift = INTVAL (operands[4]) & 31;
3282 int start = INTVAL (operands[2]) & 31;
3283 int size = INTVAL (operands[1]) & 31;
3285 operands[4] = GEN_INT (32 - shift - start - size);
3286 operands[1] = GEN_INT (start + size - 1);
3287 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3288 }"
3289 [(set_attr "type" "insert_word")])
3291 (define_insn "*insvsi_internal3"
3292 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3293 (match_operand:SI 1 "const_int_operand" "i")
3294 (match_operand:SI 2 "const_int_operand" "i"))
3295 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3296 (match_operand:SI 4 "const_int_operand" "i")))]
3297 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3298 "*
3299 {
3300 int shift = INTVAL (operands[4]) & 31;
3301 int start = INTVAL (operands[2]) & 31;
3302 int size = INTVAL (operands[1]) & 31;
3304 operands[4] = GEN_INT (32 - shift - start - size);
3305 operands[1] = GEN_INT (start + size - 1);
3306 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3307 }"
3308 [(set_attr "type" "insert_word")])
3310 (define_insn "*insvsi_internal4"
3311 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3312 (match_operand:SI 1 "const_int_operand" "i")
3313 (match_operand:SI 2 "const_int_operand" "i"))
3314 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3315 (match_operand:SI 4 "const_int_operand" "i")
3316 (match_operand:SI 5 "const_int_operand" "i")))]
3317 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3318 "*
3319 {
3320 int extract_start = INTVAL (operands[5]) & 31;
3321 int extract_size = INTVAL (operands[4]) & 31;
3322 int insert_start = INTVAL (operands[2]) & 31;
3323 int insert_size = INTVAL (operands[1]) & 31;
3325 /* Align extract field with insert field */
3326 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3327 operands[1] = GEN_INT (insert_start + insert_size - 1);
3328 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3329 }"
3330 [(set_attr "type" "insert_word")])
3332 ;; combine patterns for rlwimi
3333 (define_insn "*insvsi_internal5"
3334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3335 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3336 (match_operand:SI 1 "mask_operand" "i"))
3337 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3338 (match_operand:SI 2 "const_int_operand" "i"))
3339 (match_operand:SI 5 "mask_operand" "i"))))]
3340 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3341 "*
3342 {
3343 int me = extract_ME(operands[5]);
3344 int mb = extract_MB(operands[5]);
3345 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3346 operands[2] = GEN_INT(mb);
3347 operands[1] = GEN_INT(me);
3348 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3349 }"
3350 [(set_attr "type" "insert_word")])
3352 (define_insn "*insvsi_internal6"
3353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3354 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3355 (match_operand:SI 2 "const_int_operand" "i"))
3356 (match_operand:SI 5 "mask_operand" "i"))
3357 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3358 (match_operand:SI 1 "mask_operand" "i"))))]
3359 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3360 "*
3361 {
3362 int me = extract_ME(operands[5]);
3363 int mb = extract_MB(operands[5]);
3364 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3365 operands[2] = GEN_INT(mb);
3366 operands[1] = GEN_INT(me);
3367 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3368 }"
3369 [(set_attr "type" "insert_word")])
3371 (define_insn "insvdi_internal"
3372 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3373 (match_operand:SI 1 "const_int_operand" "i")
3374 (match_operand:SI 2 "const_int_operand" "i"))
3375 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3376 "TARGET_POWERPC64"
3377 "*
3378 {
3379 int start = INTVAL (operands[2]) & 63;
3380 int size = INTVAL (operands[1]) & 63;
3382 operands[1] = GEN_INT (64 - start - size);
3383 return \"rldimi %0,%3,%H1,%H2\";
3384 }"
3385 [(set_attr "type" "insert_dword")])
3387 (define_insn "*insvdi_internal2"
3388 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3389 (match_operand:SI 1 "const_int_operand" "i")
3390 (match_operand:SI 2 "const_int_operand" "i"))
3391 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3392 (match_operand:SI 4 "const_int_operand" "i")))]
3393 "TARGET_POWERPC64
3394 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3395 "*
3396 {
3397 int shift = INTVAL (operands[4]) & 63;
3398 int start = (INTVAL (operands[2]) & 63) - 32;
3399 int size = INTVAL (operands[1]) & 63;
3401 operands[4] = GEN_INT (64 - shift - start - size);
3402 operands[2] = GEN_INT (start);
3403 operands[1] = GEN_INT (start + size - 1);
3404 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3405 }")
3407 (define_insn "*insvdi_internal3"
3408 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3409 (match_operand:SI 1 "const_int_operand" "i")
3410 (match_operand:SI 2 "const_int_operand" "i"))
3411 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3412 (match_operand:SI 4 "const_int_operand" "i")))]
3413 "TARGET_POWERPC64
3414 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3415 "*
3416 {
3417 int shift = INTVAL (operands[4]) & 63;
3418 int start = (INTVAL (operands[2]) & 63) - 32;
3419 int size = INTVAL (operands[1]) & 63;
3421 operands[4] = GEN_INT (64 - shift - start - size);
3422 operands[2] = GEN_INT (start);
3423 operands[1] = GEN_INT (start + size - 1);
3424 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3425 }")
3427 (define_expand "extzv"
3428 [(set (match_operand 0 "gpc_reg_operand" "")
3429 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3430 (match_operand:SI 2 "const_int_operand" "")
3431 (match_operand:SI 3 "const_int_operand" "")))]
3432 ""
3433 "
3434 {
3435 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3436 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3437 compiler if the address of the structure is taken later. */
3438 if (GET_CODE (operands[0]) == SUBREG
3439 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3440 FAIL;
3442 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3443 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3444 operands[3]));
3445 else
3446 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3447 operands[3]));
3448 DONE;
3449 }")
3451 (define_insn "extzvsi_internal"
3452 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3453 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3454 (match_operand:SI 2 "const_int_operand" "i")
3455 (match_operand:SI 3 "const_int_operand" "i")))]
3456 ""
3457 "*
3458 {
3459 int start = INTVAL (operands[3]) & 31;
3460 int size = INTVAL (operands[2]) & 31;
3462 if (start + size >= 32)
3463 operands[3] = const0_rtx;
3464 else
3465 operands[3] = GEN_INT (start + size);
3466 return \"rlwinm %0,%1,%3,%s2,31\";
3467 }")
3469 (define_insn "*extzvsi_internal1"
3470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3471 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3472 (match_operand:SI 2 "const_int_operand" "i,i")
3473 (match_operand:SI 3 "const_int_operand" "i,i"))
3474 (const_int 0)))
3475 (clobber (match_scratch:SI 4 "=r,r"))]
3476 ""
3477 "*
3478 {
3479 int start = INTVAL (operands[3]) & 31;
3480 int size = INTVAL (operands[2]) & 31;
3482 /* Force split for non-cc0 compare. */
3483 if (which_alternative == 1)
3484 return \"#\";
3486 /* If the bit-field being tested fits in the upper or lower half of a
3487 word, it is possible to use andiu. or andil. to test it. This is
3488 useful because the condition register set-use delay is smaller for
3489 andi[ul]. than for rlinm. This doesn't work when the starting bit
3490 position is 0 because the LT and GT bits may be set wrong. */
3492 if ((start > 0 && start + size <= 16) || start >= 16)
3493 {
3494 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3495 - (1 << (16 - (start & 15) - size))));
3496 if (start < 16)
3497 return \"andis. %4,%1,%3\";
3498 else
3499 return \"andi. %4,%1,%3\";
3500 }
3502 if (start + size >= 32)
3503 operands[3] = const0_rtx;
3504 else
3505 operands[3] = GEN_INT (start + size);
3506 return \"rlwinm. %4,%1,%3,%s2,31\";
3507 }"
3508 [(set_attr "type" "delayed_compare")
3509 (set_attr "length" "4,8")])
3511 (define_split
3512 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3513 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3514 (match_operand:SI 2 "const_int_operand" "")
3515 (match_operand:SI 3 "const_int_operand" ""))
3516 (const_int 0)))
3517 (clobber (match_scratch:SI 4 ""))]
3518 "reload_completed"
3519 [(set (match_dup 4)
3520 (zero_extract:SI (match_dup 1) (match_dup 2)
3521 (match_dup 3)))
3522 (set (match_dup 0)
3523 (compare:CC (match_dup 4)
3524 (const_int 0)))]
3525 "")
3527 (define_insn "*extzvsi_internal2"
3528 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3529 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3530 (match_operand:SI 2 "const_int_operand" "i,i")
3531 (match_operand:SI 3 "const_int_operand" "i,i"))
3532 (const_int 0)))
3533 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3534 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3535 ""
3536 "*
3537 {
3538 int start = INTVAL (operands[3]) & 31;
3539 int size = INTVAL (operands[2]) & 31;
3541 /* Force split for non-cc0 compare. */
3542 if (which_alternative == 1)
3543 return \"#\";
3545 /* Since we are using the output value, we can't ignore any need for
3546 a shift. The bit-field must end at the LSB. */
3547 if (start >= 16 && start + size == 32)
3548 {
3549 operands[3] = GEN_INT ((1 << size) - 1);
3550 return \"andi. %0,%1,%3\";
3551 }
3553 if (start + size >= 32)
3554 operands[3] = const0_rtx;
3555 else
3556 operands[3] = GEN_INT (start + size);
3557 return \"rlwinm. %0,%1,%3,%s2,31\";
3558 }"
3559 [(set_attr "type" "delayed_compare")
3560 (set_attr "length" "4,8")])
3562 (define_split
3563 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3564 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3565 (match_operand:SI 2 "const_int_operand" "")
3566 (match_operand:SI 3 "const_int_operand" ""))
3567 (const_int 0)))
3568 (set (match_operand:SI 0 "gpc_reg_operand" "")
3569 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3570 "reload_completed"
3571 [(set (match_dup 0)
3572 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3573 (set (match_dup 4)
3574 (compare:CC (match_dup 0)
3575 (const_int 0)))]
3576 "")
3578 (define_insn "extzvdi_internal"
3579 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3580 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3581 (match_operand:SI 2 "const_int_operand" "i")
3582 (match_operand:SI 3 "const_int_operand" "i")))]
3583 "TARGET_POWERPC64"
3584 "*
3585 {
3586 int start = INTVAL (operands[3]) & 63;
3587 int size = INTVAL (operands[2]) & 63;
3589 if (start + size >= 64)
3590 operands[3] = const0_rtx;
3591 else
3592 operands[3] = GEN_INT (start + size);
3593 operands[2] = GEN_INT (64 - size);
3594 return \"rldicl %0,%1,%3,%2\";
3595 }")
3597 (define_insn "*extzvdi_internal1"
3598 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3599 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3600 (match_operand:SI 2 "const_int_operand" "i")
3601 (match_operand:SI 3 "const_int_operand" "i"))
3602 (const_int 0)))
3603 (clobber (match_scratch:DI 4 "=r"))]
3604 "TARGET_64BIT && rs6000_gen_cell_microcode"
3605 "*
3606 {
3607 int start = INTVAL (operands[3]) & 63;
3608 int size = INTVAL (operands[2]) & 63;
3610 if (start + size >= 64)
3611 operands[3] = const0_rtx;
3612 else
3613 operands[3] = GEN_INT (start + size);
3614 operands[2] = GEN_INT (64 - size);
3615 return \"rldicl. %4,%1,%3,%2\";
3616 }"
3617 [(set_attr "type" "compare")])
3619 (define_insn "*extzvdi_internal2"
3620 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3621 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3622 (match_operand:SI 2 "const_int_operand" "i")
3623 (match_operand:SI 3 "const_int_operand" "i"))
3624 (const_int 0)))
3625 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3626 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3627 "TARGET_64BIT && rs6000_gen_cell_microcode"
3628 "*
3629 {
3630 int start = INTVAL (operands[3]) & 63;
3631 int size = INTVAL (operands[2]) & 63;
3633 if (start + size >= 64)
3634 operands[3] = const0_rtx;
3635 else
3636 operands[3] = GEN_INT (start + size);
3637 operands[2] = GEN_INT (64 - size);
3638 return \"rldicl. %0,%1,%3,%2\";
3639 }"
3640 [(set_attr "type" "compare")])
3642 (define_insn "rotlsi3"
3643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3644 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3645 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3646 ""
3647 "@
3648 rlwnm %0,%1,%2,0xffffffff
3649 rlwinm %0,%1,%h2,0xffffffff"
3650 [(set_attr "type" "var_shift_rotate,integer")])
3652 (define_insn "*rotlsi3_64"
3653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3654 (zero_extend:DI
3655 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3656 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3657 "TARGET_64BIT"
3658 "@
3659 rlwnm %0,%1,%2,0xffffffff
3660 rlwinm %0,%1,%h2,0xffffffff"
3661 [(set_attr "type" "var_shift_rotate,integer")])
3663 (define_insn "*rotlsi3_internal2"
3664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3665 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3666 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3667 (const_int 0)))
3668 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3669 ""
3670 "@
3671 rlwnm. %3,%1,%2,0xffffffff
3672 rlwinm. %3,%1,%h2,0xffffffff
3673 #
3674 #"
3675 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3676 (set_attr "length" "4,4,8,8")])
3678 (define_split
3679 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3680 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3681 (match_operand:SI 2 "reg_or_cint_operand" ""))
3682 (const_int 0)))
3683 (clobber (match_scratch:SI 3 ""))]
3684 "reload_completed"
3685 [(set (match_dup 3)
3686 (rotate:SI (match_dup 1) (match_dup 2)))
3687 (set (match_dup 0)
3688 (compare:CC (match_dup 3)
3689 (const_int 0)))]
3690 "")
3692 (define_insn "*rotlsi3_internal3"
3693 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3694 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3695 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3696 (const_int 0)))
3697 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3698 (rotate:SI (match_dup 1) (match_dup 2)))]
3699 ""
3700 "@
3701 rlwnm. %0,%1,%2,0xffffffff
3702 rlwinm. %0,%1,%h2,0xffffffff
3703 #
3704 #"
3705 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3706 (set_attr "length" "4,4,8,8")])
3708 (define_split
3709 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3710 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3711 (match_operand:SI 2 "reg_or_cint_operand" ""))
3712 (const_int 0)))
3713 (set (match_operand:SI 0 "gpc_reg_operand" "")
3714 (rotate:SI (match_dup 1) (match_dup 2)))]
3715 "reload_completed"
3716 [(set (match_dup 0)
3717 (rotate:SI (match_dup 1) (match_dup 2)))
3718 (set (match_dup 3)
3719 (compare:CC (match_dup 0)
3720 (const_int 0)))]
3721 "")
3723 (define_insn "*rotlsi3_internal4"
3724 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3725 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3726 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3727 (match_operand:SI 3 "mask_operand" "n,n")))]
3728 ""
3729 "@
3730 rlwnm %0,%1,%2,%m3,%M3
3731 rlwinm %0,%1,%h2,%m3,%M3"
3732 [(set_attr "type" "var_shift_rotate,integer")])
3734 (define_insn "*rotlsi3_internal5"
3735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3736 (compare:CC (and:SI
3737 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3738 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3739 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3740 (const_int 0)))
3741 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3742 ""
3743 "@
3744 rlwnm. %4,%1,%2,%m3,%M3
3745 rlwinm. %4,%1,%h2,%m3,%M3
3746 #
3747 #"
3748 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3749 (set_attr "length" "4,4,8,8")])
3751 (define_split
3752 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3753 (compare:CC (and:SI
3754 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3755 (match_operand:SI 2 "reg_or_cint_operand" ""))
3756 (match_operand:SI 3 "mask_operand" ""))
3757 (const_int 0)))
3758 (clobber (match_scratch:SI 4 ""))]
3759 "reload_completed"
3760 [(set (match_dup 4)
3761 (and:SI (rotate:SI (match_dup 1)
3762 (match_dup 2))
3763 (match_dup 3)))
3764 (set (match_dup 0)
3765 (compare:CC (match_dup 4)
3766 (const_int 0)))]
3767 "")
3769 (define_insn "*rotlsi3_internal6"
3770 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3771 (compare:CC (and:SI
3772 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3773 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3774 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3775 (const_int 0)))
3776 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3777 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3778 ""
3779 "@
3780 rlwnm. %0,%1,%2,%m3,%M3
3781 rlwinm. %0,%1,%h2,%m3,%M3
3782 #
3783 #"
3784 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3785 (set_attr "length" "4,4,8,8")])
3787 (define_split
3788 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3789 (compare:CC (and:SI
3790 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3791 (match_operand:SI 2 "reg_or_cint_operand" ""))
3792 (match_operand:SI 3 "mask_operand" ""))
3793 (const_int 0)))
3794 (set (match_operand:SI 0 "gpc_reg_operand" "")
3795 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3796 "reload_completed"
3797 [(set (match_dup 0)
3798 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3799 (set (match_dup 4)
3800 (compare:CC (match_dup 0)
3801 (const_int 0)))]
3802 "")
3804 (define_insn "*rotlsi3_internal7le"
3805 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3806 (zero_extend:SI
3807 (subreg:QI
3808 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3809 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3810 "!BYTES_BIG_ENDIAN"
3811 "rlw%I2nm %0,%1,%h2,0xff"
3812 [(set (attr "cell_micro")
3813 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3814 (const_string "not")
3815 (const_string "always")))])
3817 (define_insn "*rotlsi3_internal7be"
3818 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3819 (zero_extend:SI
3820 (subreg:QI
3821 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3822 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3823 "BYTES_BIG_ENDIAN"
3824 "rlw%I2nm %0,%1,%h2,0xff"
3825 [(set (attr "cell_micro")
3826 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3827 (const_string "not")
3828 (const_string "always")))])
3830 (define_insn "*rotlsi3_internal8le"
3831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3832 (compare:CC (zero_extend:SI
3833 (subreg:QI
3834 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3835 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3836 (const_int 0)))
3837 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3838 "!BYTES_BIG_ENDIAN"
3839 "@
3840 rlwnm. %3,%1,%2,0xff
3841 rlwinm. %3,%1,%h2,0xff
3842 #
3843 #"
3844 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3845 (set_attr "length" "4,4,8,8")])
3847 (define_insn "*rotlsi3_internal8be"
3848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3849 (compare:CC (zero_extend:SI
3850 (subreg:QI
3851 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3852 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3853 (const_int 0)))
3854 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3855 "BYTES_BIG_ENDIAN"
3856 "@
3857 rlwnm. %3,%1,%2,0xff
3858 rlwinm. %3,%1,%h2,0xff
3859 #
3860 #"
3861 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3862 (set_attr "length" "4,4,8,8")])
3864 (define_split
3865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3866 (compare:CC (zero_extend:SI
3867 (subreg:QI
3868 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3869 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3870 (const_int 0)))
3871 (clobber (match_scratch:SI 3 ""))]
3872 "!BYTES_BIG_ENDIAN && reload_completed"
3873 [(set (match_dup 3)
3874 (zero_extend:SI (subreg:QI
3875 (rotate:SI (match_dup 1)
3876 (match_dup 2)) 0)))
3877 (set (match_dup 0)
3878 (compare:CC (match_dup 3)
3879 (const_int 0)))]
3880 "")
3882 (define_split
3883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3884 (compare:CC (zero_extend:SI
3885 (subreg:QI
3886 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3887 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3888 (const_int 0)))
3889 (clobber (match_scratch:SI 3 ""))]
3890 "BYTES_BIG_ENDIAN && reload_completed"
3891 [(set (match_dup 3)
3892 (zero_extend:SI (subreg:QI
3893 (rotate:SI (match_dup 1)
3894 (match_dup 2)) 3)))
3895 (set (match_dup 0)
3896 (compare:CC (match_dup 3)
3897 (const_int 0)))]
3898 "")
3900 (define_insn "*rotlsi3_internal9le"
3901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3902 (compare:CC (zero_extend:SI
3903 (subreg:QI
3904 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3905 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3906 (const_int 0)))
3907 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3908 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3909 "!BYTES_BIG_ENDIAN"
3910 "@
3911 rlwnm. %0,%1,%2,0xff
3912 rlwinm. %0,%1,%h2,0xff
3913 #
3914 #"
3915 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3916 (set_attr "length" "4,4,8,8")])
3918 (define_insn "*rotlsi3_internal9be"
3919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3920 (compare:CC (zero_extend:SI
3921 (subreg:QI
3922 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3924 (const_int 0)))
3925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3926 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3927 "BYTES_BIG_ENDIAN"
3928 "@
3929 rlwnm. %0,%1,%2,0xff
3930 rlwinm. %0,%1,%h2,0xff
3931 #
3932 #"
3933 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3934 (set_attr "length" "4,4,8,8")])
3936 (define_split
3937 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3938 (compare:CC (zero_extend:SI
3939 (subreg:QI
3940 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3941 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3942 (const_int 0)))
3943 (set (match_operand:SI 0 "gpc_reg_operand" "")
3944 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3945 "!BYTES_BIG_ENDIAN && reload_completed"
3946 [(set (match_dup 0)
3947 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3948 (set (match_dup 3)
3949 (compare:CC (match_dup 0)
3950 (const_int 0)))]
3951 "")
3953 (define_split
3954 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3955 (compare:CC (zero_extend:SI
3956 (subreg:QI
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3959 (const_int 0)))
3960 (set (match_operand:SI 0 "gpc_reg_operand" "")
3961 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3962 "BYTES_BIG_ENDIAN && reload_completed"
3963 [(set (match_dup 0)
3964 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3965 (set (match_dup 3)
3966 (compare:CC (match_dup 0)
3967 (const_int 0)))]
3968 "")
3970 (define_insn "*rotlsi3_internal10le"
3971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3972 (zero_extend:SI
3973 (subreg:HI
3974 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3975 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
3976 "!BYTES_BIG_ENDIAN"
3977 "@
3978 rlwnm %0,%1,%2,0xffff
3979 rlwinm %0,%1,%h2,0xffff"
3980 [(set_attr "type" "var_shift_rotate,integer")])
3982 (define_insn "*rotlsi3_internal10be"
3983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3984 (zero_extend:SI
3985 (subreg:HI
3986 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3987 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
3988 "BYTES_BIG_ENDIAN"
3989 "@
3990 rlwnm %0,%1,%2,0xffff
3991 rlwinm %0,%1,%h2,0xffff"
3992 [(set_attr "type" "var_shift_rotate,integer")])
3994 (define_insn "*rotlsi3_internal11le"
3995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3996 (compare:CC (zero_extend:SI
3997 (subreg:HI
3998 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3999 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4000 (const_int 0)))
4001 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4002 "!BYTES_BIG_ENDIAN"
4003 "@
4004 rlwnm. %3,%1,%2,0xffff
4005 rlwinm. %3,%1,%h2,0xffff
4006 #
4007 #"
4008 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4009 (set_attr "length" "4,4,8,8")])
4011 (define_insn "*rotlsi3_internal11be"
4012 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4013 (compare:CC (zero_extend:SI
4014 (subreg:HI
4015 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4016 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4017 (const_int 0)))
4018 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4019 "BYTES_BIG_ENDIAN"
4020 "@
4021 rlwnm. %3,%1,%2,0xffff
4022 rlwinm. %3,%1,%h2,0xffff
4023 #
4024 #"
4025 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4026 (set_attr "length" "4,4,8,8")])
4028 (define_split
4029 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4030 (compare:CC (zero_extend:SI
4031 (subreg:HI
4032 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4033 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4034 (const_int 0)))
4035 (clobber (match_scratch:SI 3 ""))]
4036 "!BYTES_BIG_ENDIAN && reload_completed"
4037 [(set (match_dup 3)
4038 (zero_extend:SI (subreg:HI
4039 (rotate:SI (match_dup 1)
4040 (match_dup 2)) 0)))
4041 (set (match_dup 0)
4042 (compare:CC (match_dup 3)
4043 (const_int 0)))]
4044 "")
4046 (define_split
4047 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4048 (compare:CC (zero_extend:SI
4049 (subreg:HI
4050 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4051 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4052 (const_int 0)))
4053 (clobber (match_scratch:SI 3 ""))]
4054 "BYTES_BIG_ENDIAN && reload_completed"
4055 [(set (match_dup 3)
4056 (zero_extend:SI (subreg:HI
4057 (rotate:SI (match_dup 1)
4058 (match_dup 2)) 2)))
4059 (set (match_dup 0)
4060 (compare:CC (match_dup 3)
4061 (const_int 0)))]
4062 "")
4064 (define_insn "*rotlsi3_internal12le"
4065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4066 (compare:CC (zero_extend:SI
4067 (subreg:HI
4068 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4069 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4070 (const_int 0)))
4071 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4072 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4073 "!BYTES_BIG_ENDIAN"
4074 "@
4075 rlwnm. %0,%1,%2,0xffff
4076 rlwinm. %0,%1,%h2,0xffff
4077 #
4078 #"
4079 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4080 (set_attr "length" "4,4,8,8")])
4082 (define_insn "*rotlsi3_internal12be"
4083 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4084 (compare:CC (zero_extend:SI
4085 (subreg:HI
4086 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4087 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4088 (const_int 0)))
4089 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4090 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4091 "BYTES_BIG_ENDIAN"
4092 "@
4093 rlwnm. %0,%1,%2,0xffff
4094 rlwinm. %0,%1,%h2,0xffff
4095 #
4096 #"
4097 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4098 (set_attr "length" "4,4,8,8")])
4100 (define_split
4101 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4102 (compare:CC (zero_extend:SI
4103 (subreg:HI
4104 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4105 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4106 (const_int 0)))
4107 (set (match_operand:SI 0 "gpc_reg_operand" "")
4108 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4109 "!BYTES_BIG_ENDIAN && reload_completed"
4110 [(set (match_dup 0)
4111 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4112 (set (match_dup 3)
4113 (compare:CC (match_dup 0)
4114 (const_int 0)))]
4115 "")
4117 (define_split
4118 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4119 (compare:CC (zero_extend:SI
4120 (subreg:HI
4121 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4122 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4123 (const_int 0)))
4124 (set (match_operand:SI 0 "gpc_reg_operand" "")
4125 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4126 "BYTES_BIG_ENDIAN && reload_completed"
4127 [(set (match_dup 0)
4128 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4129 (set (match_dup 3)
4130 (compare:CC (match_dup 0)
4131 (const_int 0)))]
4132 "")
4134 (define_insn "ashlsi3"
4135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4136 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4137 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4138 ""
4139 "@
4140 slw %0,%1,%2
4141 slwi %0,%1,%h2"
4142 [(set_attr "type" "var_shift_rotate,shift")])
4144 (define_insn "*ashlsi3_64"
4145 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4146 (zero_extend:DI
4147 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4148 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4149 "TARGET_POWERPC64"
4150 "@
4151 slw %0,%1,%2
4152 slwi %0,%1,%h2"
4153 [(set_attr "type" "var_shift_rotate,shift")])
4155 (define_insn ""
4156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4157 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4158 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4159 (const_int 0)))
4160 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4161 "TARGET_32BIT"
4162 "@
4163 slw. %3,%1,%2
4164 slwi. %3,%1,%h2
4165 #
4166 #"
4167 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4168 (set_attr "length" "4,4,8,8")])
4170 (define_split
4171 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4172 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4173 (match_operand:SI 2 "reg_or_cint_operand" ""))
4174 (const_int 0)))
4175 (clobber (match_scratch:SI 3 ""))]
4176 "TARGET_32BIT && reload_completed"
4177 [(set (match_dup 3)
4178 (ashift:SI (match_dup 1) (match_dup 2)))
4179 (set (match_dup 0)
4180 (compare:CC (match_dup 3)
4181 (const_int 0)))]
4182 "")
4184 (define_insn ""
4185 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4186 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4187 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4188 (const_int 0)))
4189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4190 (ashift:SI (match_dup 1) (match_dup 2)))]
4191 "TARGET_32BIT"
4192 "@
4193 slw. %0,%1,%2
4194 slwi. %0,%1,%h2
4195 #
4196 #"
4197 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4198 (set_attr "length" "4,4,8,8")])
4200 (define_split
4201 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4202 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4203 (match_operand:SI 2 "reg_or_cint_operand" ""))
4204 (const_int 0)))
4205 (set (match_operand:SI 0 "gpc_reg_operand" "")
4206 (ashift:SI (match_dup 1) (match_dup 2)))]
4207 "TARGET_32BIT && reload_completed"
4208 [(set (match_dup 0)
4209 (ashift:SI (match_dup 1) (match_dup 2)))
4210 (set (match_dup 3)
4211 (compare:CC (match_dup 0)
4212 (const_int 0)))]
4213 "")
4215 (define_insn "rlwinm"
4216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4217 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4218 (match_operand:SI 2 "const_int_operand" "i"))
4219 (match_operand:SI 3 "mask_operand" "n")))]
4220 "includes_lshift_p (operands[2], operands[3])"
4221 "rlwinm %0,%1,%h2,%m3,%M3")
4223 (define_insn ""
4224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4225 (compare:CC
4226 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4227 (match_operand:SI 2 "const_int_operand" "i,i"))
4228 (match_operand:SI 3 "mask_operand" "n,n"))
4229 (const_int 0)))
4230 (clobber (match_scratch:SI 4 "=r,r"))]
4231 "includes_lshift_p (operands[2], operands[3])"
4232 "@
4233 rlwinm. %4,%1,%h2,%m3,%M3
4234 #"
4235 [(set_attr "type" "delayed_compare")
4236 (set_attr "length" "4,8")])
4238 (define_split
4239 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4240 (compare:CC
4241 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4242 (match_operand:SI 2 "const_int_operand" ""))
4243 (match_operand:SI 3 "mask_operand" ""))
4244 (const_int 0)))
4245 (clobber (match_scratch:SI 4 ""))]
4246 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4247 [(set (match_dup 4)
4248 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4249 (match_dup 3)))
4250 (set (match_dup 0)
4251 (compare:CC (match_dup 4)
4252 (const_int 0)))]
4253 "")
4255 (define_insn ""
4256 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4257 (compare:CC
4258 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4259 (match_operand:SI 2 "const_int_operand" "i,i"))
4260 (match_operand:SI 3 "mask_operand" "n,n"))
4261 (const_int 0)))
4262 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4263 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4264 "includes_lshift_p (operands[2], operands[3])"
4265 "@
4266 rlwinm. %0,%1,%h2,%m3,%M3
4267 #"
4268 [(set_attr "type" "delayed_compare")
4269 (set_attr "length" "4,8")])
4271 (define_split
4272 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4273 (compare:CC
4274 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4275 (match_operand:SI 2 "const_int_operand" ""))
4276 (match_operand:SI 3 "mask_operand" ""))
4277 (const_int 0)))
4278 (set (match_operand:SI 0 "gpc_reg_operand" "")
4279 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4280 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4281 [(set (match_dup 0)
4282 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4283 (set (match_dup 4)
4284 (compare:CC (match_dup 0)
4285 (const_int 0)))]
4286 "")
4288 (define_insn "lshrsi3"
4289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4290 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4291 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4292 ""
4293 "@
4294 mr %0,%1
4295 srw %0,%1,%2
4296 srwi %0,%1,%h2"
4297 [(set_attr "type" "integer,var_shift_rotate,shift")])
4299 (define_insn "*lshrsi3_64"
4300 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4301 (zero_extend:DI
4302 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4303 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4304 "TARGET_POWERPC64"
4305 "@
4306 srw %0,%1,%2
4307 srwi %0,%1,%h2"
4308 [(set_attr "type" "var_shift_rotate,shift")])
4310 (define_insn ""
4311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4312 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4313 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4314 (const_int 0)))
4315 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4316 "TARGET_32BIT"
4317 "@
4318 mr. %1,%1
4319 srw. %3,%1,%2
4320 srwi. %3,%1,%h2
4321 #
4322 #
4323 #"
4324 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4325 (set_attr "length" "4,4,4,8,8,8")])
4327 (define_split
4328 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4329 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4330 (match_operand:SI 2 "reg_or_cint_operand" ""))
4331 (const_int 0)))
4332 (clobber (match_scratch:SI 3 ""))]
4333 "TARGET_32BIT && reload_completed"
4334 [(set (match_dup 3)
4335 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4336 (set (match_dup 0)
4337 (compare:CC (match_dup 3)
4338 (const_int 0)))]
4339 "")
4341 (define_insn ""
4342 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4343 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4344 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4345 (const_int 0)))
4346 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4347 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4348 "TARGET_32BIT"
4349 "@
4350 mr. %0,%1
4351 srw. %0,%1,%2
4352 srwi. %0,%1,%h2
4353 #
4354 #
4355 #"
4356 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4357 (set_attr "length" "4,4,4,8,8,8")])
4359 (define_split
4360 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4361 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4362 (match_operand:SI 2 "reg_or_cint_operand" ""))
4363 (const_int 0)))
4364 (set (match_operand:SI 0 "gpc_reg_operand" "")
4365 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4366 "TARGET_32BIT && reload_completed"
4367 [(set (match_dup 0)
4368 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4369 (set (match_dup 3)
4370 (compare:CC (match_dup 0)
4371 (const_int 0)))]
4372 "")
4374 (define_insn ""
4375 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4376 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4377 (match_operand:SI 2 "const_int_operand" "i"))
4378 (match_operand:SI 3 "mask_operand" "n")))]
4379 "includes_rshift_p (operands[2], operands[3])"
4380 "rlwinm %0,%1,%s2,%m3,%M3")
4382 (define_insn ""
4383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4384 (compare:CC
4385 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4386 (match_operand:SI 2 "const_int_operand" "i,i"))
4387 (match_operand:SI 3 "mask_operand" "n,n"))
4388 (const_int 0)))
4389 (clobber (match_scratch:SI 4 "=r,r"))]
4390 "includes_rshift_p (operands[2], operands[3])"
4391 "@
4392 rlwinm. %4,%1,%s2,%m3,%M3
4393 #"
4394 [(set_attr "type" "delayed_compare")
4395 (set_attr "length" "4,8")])
4397 (define_split
4398 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4399 (compare:CC
4400 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4401 (match_operand:SI 2 "const_int_operand" ""))
4402 (match_operand:SI 3 "mask_operand" ""))
4403 (const_int 0)))
4404 (clobber (match_scratch:SI 4 ""))]
4405 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4406 [(set (match_dup 4)
4407 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4408 (match_dup 3)))
4409 (set (match_dup 0)
4410 (compare:CC (match_dup 4)
4411 (const_int 0)))]
4412 "")
4414 (define_insn ""
4415 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4416 (compare:CC
4417 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4418 (match_operand:SI 2 "const_int_operand" "i,i"))
4419 (match_operand:SI 3 "mask_operand" "n,n"))
4420 (const_int 0)))
4421 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4422 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4423 "includes_rshift_p (operands[2], operands[3])"
4424 "@
4425 rlwinm. %0,%1,%s2,%m3,%M3
4426 #"
4427 [(set_attr "type" "delayed_compare")
4428 (set_attr "length" "4,8")])
4430 (define_split
4431 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4432 (compare:CC
4433 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4434 (match_operand:SI 2 "const_int_operand" ""))
4435 (match_operand:SI 3 "mask_operand" ""))
4436 (const_int 0)))
4437 (set (match_operand:SI 0 "gpc_reg_operand" "")
4438 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4439 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4440 [(set (match_dup 0)
4441 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4442 (set (match_dup 4)
4443 (compare:CC (match_dup 0)
4444 (const_int 0)))]
4445 "")
4447 (define_insn "*lshiftrt_internal1le"
4448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4449 (zero_extend:SI
4450 (subreg:QI
4451 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4452 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4453 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4454 "rlwinm %0,%1,%s2,0xff")
4456 (define_insn "*lshiftrt_internal1be"
4457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4458 (zero_extend:SI
4459 (subreg:QI
4460 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4461 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4462 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4463 "rlwinm %0,%1,%s2,0xff")
4465 (define_insn "*lshiftrt_internal2le"
4466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4467 (compare:CC
4468 (zero_extend:SI
4469 (subreg:QI
4470 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4471 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4472 (const_int 0)))
4473 (clobber (match_scratch:SI 3 "=r,r"))]
4474 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4475 "@
4476 rlwinm. %3,%1,%s2,0xff
4477 #"
4478 [(set_attr "type" "delayed_compare")
4479 (set_attr "length" "4,8")])
4481 (define_insn "*lshiftrt_internal2be"
4482 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4483 (compare:CC
4484 (zero_extend:SI
4485 (subreg:QI
4486 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4487 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4488 (const_int 0)))
4489 (clobber (match_scratch:SI 3 "=r,r"))]
4490 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4491 "@
4492 rlwinm. %3,%1,%s2,0xff
4493 #"
4494 [(set_attr "type" "delayed_compare")
4495 (set_attr "length" "4,8")])
4497 (define_split
4498 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4499 (compare:CC
4500 (zero_extend:SI
4501 (subreg:QI
4502 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4503 (match_operand:SI 2 "const_int_operand" "")) 0))
4504 (const_int 0)))
4505 (clobber (match_scratch:SI 3 ""))]
4506 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4507 [(set (match_dup 3)
4508 (zero_extend:SI (subreg:QI
4509 (lshiftrt:SI (match_dup 1)
4510 (match_dup 2)) 0)))
4511 (set (match_dup 0)
4512 (compare:CC (match_dup 3)
4513 (const_int 0)))]
4514 "")
4516 (define_split
4517 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4518 (compare:CC
4519 (zero_extend:SI
4520 (subreg:QI
4521 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4522 (match_operand:SI 2 "const_int_operand" "")) 3))
4523 (const_int 0)))
4524 (clobber (match_scratch:SI 3 ""))]
4525 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4526 [(set (match_dup 3)
4527 (zero_extend:SI (subreg:QI
4528 (lshiftrt:SI (match_dup 1)
4529 (match_dup 2)) 3)))
4530 (set (match_dup 0)
4531 (compare:CC (match_dup 3)
4532 (const_int 0)))]
4533 "")
4535 (define_insn "*lshiftrt_internal3le"
4536 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4537 (compare:CC
4538 (zero_extend:SI
4539 (subreg:QI
4540 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4541 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4542 (const_int 0)))
4543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4544 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4545 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4546 "@
4547 rlwinm. %0,%1,%s2,0xff
4548 #"
4549 [(set_attr "type" "delayed_compare")
4550 (set_attr "length" "4,8")])
4552 (define_insn "*lshiftrt_internal3be"
4553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4554 (compare:CC
4555 (zero_extend:SI
4556 (subreg:QI
4557 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4558 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4559 (const_int 0)))
4560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4561 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4562 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4563 "@
4564 rlwinm. %0,%1,%s2,0xff
4565 #"
4566 [(set_attr "type" "delayed_compare")
4567 (set_attr "length" "4,8")])
4569 (define_split
4570 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4571 (compare:CC
4572 (zero_extend:SI
4573 (subreg:QI
4574 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4575 (match_operand:SI 2 "const_int_operand" "")) 0))
4576 (const_int 0)))
4577 (set (match_operand:SI 0 "gpc_reg_operand" "")
4578 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4579 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4580 [(set (match_dup 0)
4581 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4582 (set (match_dup 3)
4583 (compare:CC (match_dup 0)
4584 (const_int 0)))]
4585 "")
4587 (define_split
4588 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4589 (compare:CC
4590 (zero_extend:SI
4591 (subreg:QI
4592 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4593 (match_operand:SI 2 "const_int_operand" "")) 3))
4594 (const_int 0)))
4595 (set (match_operand:SI 0 "gpc_reg_operand" "")
4596 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4597 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4598 [(set (match_dup 0)
4599 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4600 (set (match_dup 3)
4601 (compare:CC (match_dup 0)
4602 (const_int 0)))]
4603 "")
4605 (define_insn "*lshiftrt_internal4le"
4606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4607 (zero_extend:SI
4608 (subreg:HI
4609 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4610 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4611 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4612 "rlwinm %0,%1,%s2,0xffff")
4614 (define_insn "*lshiftrt_internal4be"
4615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4616 (zero_extend:SI
4617 (subreg:HI
4618 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4619 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4620 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4621 "rlwinm %0,%1,%s2,0xffff")
4623 (define_insn "*lshiftrt_internal5le"
4624 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4625 (compare:CC
4626 (zero_extend:SI
4627 (subreg:HI
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4629 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4630 (const_int 0)))
4631 (clobber (match_scratch:SI 3 "=r,r"))]
4632 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4633 "@
4634 rlwinm. %3,%1,%s2,0xffff
4635 #"
4636 [(set_attr "type" "delayed_compare")
4637 (set_attr "length" "4,8")])
4639 (define_insn "*lshiftrt_internal5be"
4640 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4641 (compare:CC
4642 (zero_extend:SI
4643 (subreg:HI
4644 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4645 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4646 (const_int 0)))
4647 (clobber (match_scratch:SI 3 "=r,r"))]
4648 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4649 "@
4650 rlwinm. %3,%1,%s2,0xffff
4651 #"
4652 [(set_attr "type" "delayed_compare")
4653 (set_attr "length" "4,8")])
4655 (define_split
4656 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4657 (compare:CC
4658 (zero_extend:SI
4659 (subreg:HI
4660 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4661 (match_operand:SI 2 "const_int_operand" "")) 0))
4662 (const_int 0)))
4663 (clobber (match_scratch:SI 3 ""))]
4664 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4665 [(set (match_dup 3)
4666 (zero_extend:SI (subreg:HI
4667 (lshiftrt:SI (match_dup 1)
4668 (match_dup 2)) 0)))
4669 (set (match_dup 0)
4670 (compare:CC (match_dup 3)
4671 (const_int 0)))]
4672 "")
4674 (define_split
4675 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4676 (compare:CC
4677 (zero_extend:SI
4678 (subreg:HI
4679 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4680 (match_operand:SI 2 "const_int_operand" "")) 2))
4681 (const_int 0)))
4682 (clobber (match_scratch:SI 3 ""))]
4683 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4684 [(set (match_dup 3)
4685 (zero_extend:SI (subreg:HI
4686 (lshiftrt:SI (match_dup 1)
4687 (match_dup 2)) 2)))
4688 (set (match_dup 0)
4689 (compare:CC (match_dup 3)
4690 (const_int 0)))]
4691 "")
4693 (define_insn "*lshiftrt_internal5le"
4694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4695 (compare:CC
4696 (zero_extend:SI
4697 (subreg:HI
4698 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4699 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4700 (const_int 0)))
4701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4702 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4703 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4704 "@
4705 rlwinm. %0,%1,%s2,0xffff
4706 #"
4707 [(set_attr "type" "delayed_compare")
4708 (set_attr "length" "4,8")])
4710 (define_insn "*lshiftrt_internal5be"
4711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4712 (compare:CC
4713 (zero_extend:SI
4714 (subreg:HI
4715 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4716 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4717 (const_int 0)))
4718 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4719 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4720 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4721 "@
4722 rlwinm. %0,%1,%s2,0xffff
4723 #"
4724 [(set_attr "type" "delayed_compare")
4725 (set_attr "length" "4,8")])
4727 (define_split
4728 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4729 (compare:CC
4730 (zero_extend:SI
4731 (subreg:HI
4732 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4733 (match_operand:SI 2 "const_int_operand" "")) 0))
4734 (const_int 0)))
4735 (set (match_operand:SI 0 "gpc_reg_operand" "")
4736 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4737 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4738 [(set (match_dup 0)
4739 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4740 (set (match_dup 3)
4741 (compare:CC (match_dup 0)
4742 (const_int 0)))]
4743 "")
4745 (define_split
4746 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4747 (compare:CC
4748 (zero_extend:SI
4749 (subreg:HI
4750 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4751 (match_operand:SI 2 "const_int_operand" "")) 2))
4752 (const_int 0)))
4753 (set (match_operand:SI 0 "gpc_reg_operand" "")
4754 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4755 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4756 [(set (match_dup 0)
4757 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4758 (set (match_dup 3)
4759 (compare:CC (match_dup 0)
4760 (const_int 0)))]
4761 "")
4763 (define_insn "ashrsi3"
4764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4765 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4766 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4767 ""
4768 "@
4769 sraw %0,%1,%2
4770 srawi %0,%1,%h2"
4771 [(set_attr "type" "var_shift_rotate,shift")])
4773 (define_insn "*ashrsi3_64"
4774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4775 (sign_extend:DI
4776 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4777 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4778 "TARGET_POWERPC64"
4779 "@
4780 sraw %0,%1,%2
4781 srawi %0,%1,%h2"
4782 [(set_attr "type" "var_shift_rotate,shift")])
4784 (define_insn ""
4785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4786 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4787 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4788 (const_int 0)))
4789 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4790 ""
4791 "@
4792 sraw. %3,%1,%2
4793 srawi. %3,%1,%h2
4794 #
4795 #"
4796 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4797 (set_attr "length" "4,4,8,8")])
4799 (define_split
4800 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4801 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4802 (match_operand:SI 2 "reg_or_cint_operand" ""))
4803 (const_int 0)))
4804 (clobber (match_scratch:SI 3 ""))]
4805 "reload_completed"
4806 [(set (match_dup 3)
4807 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4808 (set (match_dup 0)
4809 (compare:CC (match_dup 3)
4810 (const_int 0)))]
4811 "")
4813 (define_insn ""
4814 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4815 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4816 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4817 (const_int 0)))
4818 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4819 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4820 ""
4821 "@
4822 sraw. %0,%1,%2
4823 srawi. %0,%1,%h2
4824 #
4825 #"
4826 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4827 (set_attr "length" "4,4,8,8")])
4828 \f
4829 ;; Builtins to replace a division to generate FRE reciprocal estimate
4830 ;; instructions and the necessary fixup instructions
4831 (define_expand "recip<mode>3"
4832 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4833 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4834 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4835 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4836 {
4837 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4838 DONE;
4839 })
4841 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4842 ;; hardware division. This is only done before register allocation and with
4843 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4844 (define_split
4845 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4846 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4847 (match_operand 2 "gpc_reg_operand" "")))]
4848 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4849 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4850 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4851 [(const_int 0)]
4852 {
4853 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4854 DONE;
4855 })
4857 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4858 ;; appropriate fixup.
4859 (define_expand "rsqrt<mode>2"
4860 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4861 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4862 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4863 {
4864 rs6000_emit_swrsqrt (operands[0], operands[1]);
4865 DONE;
4866 })
4867 \f
4868 (define_split
4869 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4870 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4871 (match_operand:SI 2 "reg_or_cint_operand" ""))
4872 (const_int 0)))
4873 (set (match_operand:SI 0 "gpc_reg_operand" "")
4874 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4875 "reload_completed"
4876 [(set (match_dup 0)
4877 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4878 (set (match_dup 3)
4879 (compare:CC (match_dup 0)
4880 (const_int 0)))]
4881 "")
4883 ;; Floating-point insns, excluding normal data motion.
4884 ;;
4885 ;; PowerPC has a full set of single-precision floating point instructions.
4886 ;;
4887 ;; For the POWER architecture, we pretend that we have both SFmode and
4888 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4889 ;; The only conversions we will do will be when storing to memory. In that
4890 ;; case, we will use the "frsp" instruction before storing.
4891 ;;
4892 ;; Note that when we store into a single-precision memory location, we need to
4893 ;; use the frsp insn first. If the register being stored isn't dead, we
4894 ;; need a scratch register for the frsp. But this is difficult when the store
4895 ;; is done by reload. It is not incorrect to do the frsp on the register in
4896 ;; this case, we just lose precision that we would have otherwise gotten but
4897 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4899 (define_expand "extendsfdf2"
4900 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4901 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4902 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4903 "")
4905 (define_insn_and_split "*extendsfdf2_fpr"
4906 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4907 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4908 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4909 "@
4910 #
4911 fmr %0,%1
4912 lfs%U1%X1 %0,%1"
4913 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4914 [(const_int 0)]
4915 {
4916 emit_note (NOTE_INSN_DELETED);
4917 DONE;
4918 }
4919 [(set_attr_alternative "type"
4920 [(const_string "fp")
4921 (const_string "fp")
4922 (if_then_else
4923 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
4924 (const_string "fpload_ux")
4925 (if_then_else
4926 (match_test "update_address_mem (operands[1], VOIDmode)")
4927 (const_string "fpload_u")
4928 (const_string "fpload")))])])
4930 (define_expand "truncdfsf2"
4931 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4932 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4933 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4934 "")
4936 (define_insn "*truncdfsf2_fpr"
4937 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4938 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4939 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4940 "frsp %0,%1"
4941 [(set_attr "type" "fp")])
4943 (define_expand "negsf2"
4944 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4945 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4946 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4947 "")
4949 (define_insn "*negsf2"
4950 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4951 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4952 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4953 "fneg %0,%1"
4954 [(set_attr "type" "fp")])
4956 (define_expand "abssf2"
4957 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4958 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4959 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4960 "")
4962 (define_insn "*abssf2"
4963 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4964 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4965 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4966 "fabs %0,%1"
4967 [(set_attr "type" "fp")])
4969 (define_insn ""
4970 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4971 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4972 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4973 "fnabs %0,%1"
4974 [(set_attr "type" "fp")])
4976 (define_expand "addsf3"
4977 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4978 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4979 (match_operand:SF 2 "gpc_reg_operand" "")))]
4980 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4981 "")
4983 (define_insn ""
4984 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4985 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4986 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4988 "fadds %0,%1,%2"
4989 [(set_attr "type" "fp")
4990 (set_attr "fp_type" "fp_addsub_s")])
4992 (define_expand "subsf3"
4993 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4994 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4995 (match_operand:SF 2 "gpc_reg_operand" "")))]
4996 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4997 "")
4999 (define_insn ""
5000 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5001 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5002 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5003 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5004 "fsubs %0,%1,%2"
5005 [(set_attr "type" "fp")
5006 (set_attr "fp_type" "fp_addsub_s")])
5008 (define_expand "mulsf3"
5009 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5010 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5011 (match_operand:SF 2 "gpc_reg_operand" "")))]
5012 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5013 "")
5015 (define_insn ""
5016 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5017 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5018 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5019 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5020 "fmuls %0,%1,%2"
5021 [(set_attr "type" "fp")
5022 (set_attr "fp_type" "fp_mul_s")])
5024 (define_expand "divsf3"
5025 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5026 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5027 (match_operand:SF 2 "gpc_reg_operand" "")))]
5028 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5029 "")
5031 (define_insn ""
5032 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5033 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5034 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5035 "TARGET_HARD_FLOAT && TARGET_FPRS
5036 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5037 "fdivs %0,%1,%2"
5038 [(set_attr "type" "sdiv")])
5040 (define_insn "fres"
5041 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5042 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5043 "TARGET_FRES"
5044 "fres %0,%1"
5045 [(set_attr "type" "fp")])
5047 ; builtin fmaf support
5048 (define_insn "*fmasf4_fpr"
5049 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5050 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5051 (match_operand:SF 2 "gpc_reg_operand" "f")
5052 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5053 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5054 "fmadds %0,%1,%2,%3"
5055 [(set_attr "type" "fp")
5056 (set_attr "fp_type" "fp_maddsub_s")])
5058 (define_insn "*fmssf4_fpr"
5059 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5060 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5061 (match_operand:SF 2 "gpc_reg_operand" "f")
5062 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5063 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5064 "fmsubs %0,%1,%2,%3"
5065 [(set_attr "type" "fp")
5066 (set_attr "fp_type" "fp_maddsub_s")])
5068 (define_insn "*nfmasf4_fpr"
5069 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5070 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5071 (match_operand:SF 2 "gpc_reg_operand" "f")
5072 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5073 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5074 "fnmadds %0,%1,%2,%3"
5075 [(set_attr "type" "fp")
5076 (set_attr "fp_type" "fp_maddsub_s")])
5078 (define_insn "*nfmssf4_fpr"
5079 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5080 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5081 (match_operand:SF 2 "gpc_reg_operand" "f")
5082 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5083 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5084 "fnmsubs %0,%1,%2,%3"
5085 [(set_attr "type" "fp")
5086 (set_attr "fp_type" "fp_maddsub_s")])
5088 (define_expand "sqrtsf2"
5089 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5090 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5091 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
5092 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5093 && !TARGET_SIMPLE_FPU"
5094 "")
5096 (define_insn ""
5097 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5098 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5099 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5100 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5101 "fsqrts %0,%1"
5102 [(set_attr "type" "ssqrt")])
5104 (define_insn "*rsqrtsf_internal1"
5105 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5106 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5107 UNSPEC_RSQRT))]
5108 "TARGET_FRSQRTES"
5109 "frsqrtes %0,%1"
5110 [(set_attr "type" "fp")])
5112 (define_expand "copysign<mode>3"
5113 [(set (match_dup 3)
5114 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5115 (set (match_dup 4)
5116 (neg:SFDF (abs:SFDF (match_dup 1))))
5117 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5118 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5119 (match_dup 5))
5120 (match_dup 3)
5121 (match_dup 4)))]
5122 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5123 && ((TARGET_PPC_GFXOPT
5124 && !HONOR_NANS (<MODE>mode)
5125 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5126 || TARGET_CMPB
5127 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5128 {
5129 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5130 {
5131 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5132 operands[2]));
5133 DONE;
5134 }
5136 operands[3] = gen_reg_rtx (<MODE>mode);
5137 operands[4] = gen_reg_rtx (<MODE>mode);
5138 operands[5] = CONST0_RTX (<MODE>mode);
5139 })
5141 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5142 ;; compiler from optimizing -0.0
5143 (define_insn "copysign<mode>3_fcpsgn"
5144 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5145 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5146 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5147 UNSPEC_COPYSIGN))]
5148 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5149 "fcpsgn %0,%2,%1"
5150 [(set_attr "type" "fp")])
5152 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5153 ;; fsel instruction and some auxiliary computations. Then we just have a
5154 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5155 ;; combine.
5156 (define_expand "smaxsf3"
5157 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5158 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5159 (match_operand:SF 2 "gpc_reg_operand" ""))
5160 (match_dup 1)
5161 (match_dup 2)))]
5162 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5163 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5164 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5166 (define_expand "sminsf3"
5167 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5168 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5169 (match_operand:SF 2 "gpc_reg_operand" ""))
5170 (match_dup 2)
5171 (match_dup 1)))]
5172 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5173 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5174 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5176 (define_split
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5178 (match_operator:SF 3 "min_max_operator"
5179 [(match_operand:SF 1 "gpc_reg_operand" "")
5180 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5181 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5182 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5183 [(const_int 0)]
5184 "
5185 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5186 operands[1], operands[2]);
5187 DONE;
5188 }")
5190 (define_expand "mov<mode>cc"
5191 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5192 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5193 (match_operand:GPR 2 "gpc_reg_operand" "")
5194 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5195 "TARGET_ISEL<sel>"
5196 "
5197 {
5198 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5199 DONE;
5200 else
5201 FAIL;
5202 }")
5204 ;; We use the BASE_REGS for the isel input operands because, if rA is
5205 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5206 ;; because we may switch the operands and rB may end up being rA.
5207 ;;
5208 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5209 ;; leave out the mode in operand 4 and use one pattern, but reload can
5210 ;; change the mode underneath our feet and then gets confused trying
5211 ;; to reload the value.
5212 (define_insn "isel_signed_<mode>"
5213 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5214 (if_then_else:GPR
5215 (match_operator 1 "scc_comparison_operator"
5216 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5217 (const_int 0)])
5218 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5219 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5220 "TARGET_ISEL<sel>"
5221 "*
5222 { return output_isel (operands); }"
5223 [(set_attr "type" "isel")
5224 (set_attr "length" "4")])
5226 (define_insn "isel_unsigned_<mode>"
5227 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5228 (if_then_else:GPR
5229 (match_operator 1 "scc_comparison_operator"
5230 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5231 (const_int 0)])
5232 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5233 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5234 "TARGET_ISEL<sel>"
5235 "*
5236 { return output_isel (operands); }"
5237 [(set_attr "type" "isel")
5238 (set_attr "length" "4")])
5240 ;; These patterns can be useful for combine; they let combine know that
5241 ;; isel can handle reversed comparisons so long as the operands are
5242 ;; registers.
5244 (define_insn "*isel_reversed_signed_<mode>"
5245 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5246 (if_then_else:GPR
5247 (match_operator 1 "scc_rev_comparison_operator"
5248 [(match_operand:CC 4 "cc_reg_operand" "y")
5249 (const_int 0)])
5250 (match_operand:GPR 2 "gpc_reg_operand" "b")
5251 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5252 "TARGET_ISEL<sel>"
5253 "*
5254 { return output_isel (operands); }"
5255 [(set_attr "type" "isel")
5256 (set_attr "length" "4")])
5258 (define_insn "*isel_reversed_unsigned_<mode>"
5259 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5260 (if_then_else:GPR
5261 (match_operator 1 "scc_rev_comparison_operator"
5262 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5263 (const_int 0)])
5264 (match_operand:GPR 2 "gpc_reg_operand" "b")
5265 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5266 "TARGET_ISEL<sel>"
5267 "*
5268 { return output_isel (operands); }"
5269 [(set_attr "type" "isel")
5270 (set_attr "length" "4")])
5272 (define_expand "movsfcc"
5273 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5274 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5275 (match_operand:SF 2 "gpc_reg_operand" "")
5276 (match_operand:SF 3 "gpc_reg_operand" "")))]
5277 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5278 "
5279 {
5280 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5281 DONE;
5282 else
5283 FAIL;
5284 }")
5286 (define_insn "*fselsfsf4"
5287 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5288 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5289 (match_operand:SF 4 "zero_fp_constant" "F"))
5290 (match_operand:SF 2 "gpc_reg_operand" "f")
5291 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5292 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5293 "fsel %0,%1,%2,%3"
5294 [(set_attr "type" "fp")])
5296 (define_insn "*fseldfsf4"
5297 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5298 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5299 (match_operand:DF 4 "zero_fp_constant" "F"))
5300 (match_operand:SF 2 "gpc_reg_operand" "f")
5301 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5302 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5303 "fsel %0,%1,%2,%3"
5304 [(set_attr "type" "fp")])
5306 (define_expand "negdf2"
5307 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5308 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5309 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5310 "")
5312 (define_insn "*negdf2_fpr"
5313 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5314 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5315 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5316 && !VECTOR_UNIT_VSX_P (DFmode)"
5317 "fneg %0,%1"
5318 [(set_attr "type" "fp")])
5320 (define_expand "absdf2"
5321 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5322 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5323 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5324 "")
5326 (define_insn "*absdf2_fpr"
5327 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5328 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5329 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5330 && !VECTOR_UNIT_VSX_P (DFmode)"
5331 "fabs %0,%1"
5332 [(set_attr "type" "fp")])
5334 (define_insn "*nabsdf2_fpr"
5335 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5336 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5337 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5338 && !VECTOR_UNIT_VSX_P (DFmode)"
5339 "fnabs %0,%1"
5340 [(set_attr "type" "fp")])
5342 (define_expand "adddf3"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5344 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5345 (match_operand:DF 2 "gpc_reg_operand" "")))]
5346 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5347 "")
5349 (define_insn "*adddf3_fpr"
5350 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5351 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5352 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5353 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5354 && !VECTOR_UNIT_VSX_P (DFmode)"
5355 "fadd %0,%1,%2"
5356 [(set_attr "type" "fp")
5357 (set_attr "fp_type" "fp_addsub_d")])
5359 (define_expand "subdf3"
5360 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5361 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5362 (match_operand:DF 2 "gpc_reg_operand" "")))]
5363 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5364 "")
5366 (define_insn "*subdf3_fpr"
5367 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5368 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5369 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5370 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5371 && !VECTOR_UNIT_VSX_P (DFmode)"
5372 "fsub %0,%1,%2"
5373 [(set_attr "type" "fp")
5374 (set_attr "fp_type" "fp_addsub_d")])
5376 (define_expand "muldf3"
5377 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5378 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5379 (match_operand:DF 2 "gpc_reg_operand" "")))]
5380 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5381 "")
5383 (define_insn "*muldf3_fpr"
5384 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5385 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5386 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5387 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5388 && !VECTOR_UNIT_VSX_P (DFmode)"
5389 "fmul %0,%1,%2"
5390 [(set_attr "type" "dmul")
5391 (set_attr "fp_type" "fp_mul_d")])
5393 (define_expand "divdf3"
5394 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5395 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5396 (match_operand:DF 2 "gpc_reg_operand" "")))]
5397 "TARGET_HARD_FLOAT
5398 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5399 && !TARGET_SIMPLE_FPU"
5400 "")
5402 (define_insn "*divdf3_fpr"
5403 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5404 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5405 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5406 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
5407 && !VECTOR_UNIT_VSX_P (DFmode)"
5408 "fdiv %0,%1,%2"
5409 [(set_attr "type" "ddiv")])
5411 (define_insn "*fred_fpr"
5412 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5413 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5414 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
5415 "fre %0,%1"
5416 [(set_attr "type" "fp")])
5418 (define_insn "*rsqrtdf_internal1"
5419 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5420 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
5421 UNSPEC_RSQRT))]
5422 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
5423 "frsqrte %0,%1"
5424 [(set_attr "type" "fp")])
5426 ; builtin fma support
5427 (define_insn "*fmadf4_fpr"
5428 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5429 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5430 (match_operand:DF 2 "gpc_reg_operand" "f")
5431 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5432 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5433 && VECTOR_UNIT_NONE_P (DFmode)"
5434 "fmadd %0,%1,%2,%3"
5435 [(set_attr "type" "fp")
5436 (set_attr "fp_type" "fp_maddsub_d")])
5438 (define_insn "*fmsdf4_fpr"
5439 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5440 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5441 (match_operand:DF 2 "gpc_reg_operand" "f")
5442 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5443 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5444 && VECTOR_UNIT_NONE_P (DFmode)"
5445 "fmsub %0,%1,%2,%3"
5446 [(set_attr "type" "fp")
5447 (set_attr "fp_type" "fp_maddsub_d")])
5449 (define_insn "*nfmadf4_fpr"
5450 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5451 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5452 (match_operand:DF 2 "gpc_reg_operand" "f")
5453 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5454 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5455 && VECTOR_UNIT_NONE_P (DFmode)"
5456 "fnmadd %0,%1,%2,%3"
5457 [(set_attr "type" "fp")
5458 (set_attr "fp_type" "fp_maddsub_d")])
5460 (define_insn "*nfmsdf4_fpr"
5461 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5462 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5463 (match_operand:DF 2 "gpc_reg_operand" "f")
5464 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5465 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5466 && VECTOR_UNIT_NONE_P (DFmode)"
5467 "fnmsub %0,%1,%2,%3"
5468 [(set_attr "type" "fp")
5469 (set_attr "fp_type" "fp_maddsub_d")])
5471 (define_expand "sqrtdf2"
5472 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5473 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5474 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5475 "")
5477 (define_insn "*sqrtdf2_fpr"
5478 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5479 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5480 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5481 && !VECTOR_UNIT_VSX_P (DFmode)"
5482 "fsqrt %0,%1"
5483 [(set_attr "type" "dsqrt")])
5485 ;; The conditional move instructions allow us to perform max and min
5486 ;; operations even when
5488 (define_expand "smaxdf3"
5489 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5490 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5491 (match_operand:DF 2 "gpc_reg_operand" ""))
5492 (match_dup 1)
5493 (match_dup 2)))]
5494 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5495 && !flag_trapping_math"
5496 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5498 (define_expand "smindf3"
5499 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5500 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5501 (match_operand:DF 2 "gpc_reg_operand" ""))
5502 (match_dup 2)
5503 (match_dup 1)))]
5504 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5505 && !flag_trapping_math"
5506 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5508 (define_split
5509 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5510 (match_operator:DF 3 "min_max_operator"
5511 [(match_operand:DF 1 "gpc_reg_operand" "")
5512 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5513 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5514 && !flag_trapping_math"
5515 [(const_int 0)]
5516 "
5517 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5518 operands[1], operands[2]);
5519 DONE;
5520 }")
5522 (define_expand "movdfcc"
5523 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5524 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5525 (match_operand:DF 2 "gpc_reg_operand" "")
5526 (match_operand:DF 3 "gpc_reg_operand" "")))]
5527 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5528 "
5529 {
5530 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5531 DONE;
5532 else
5533 FAIL;
5534 }")
5536 (define_insn "*fseldfdf4"
5537 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5538 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5539 (match_operand:DF 4 "zero_fp_constant" "F"))
5540 (match_operand:DF 2 "gpc_reg_operand" "d")
5541 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5542 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5543 "fsel %0,%1,%2,%3"
5544 [(set_attr "type" "fp")])
5546 (define_insn "*fselsfdf4"
5547 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5548 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5549 (match_operand:SF 4 "zero_fp_constant" "F"))
5550 (match_operand:DF 2 "gpc_reg_operand" "d")
5551 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5552 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5553 "fsel %0,%1,%2,%3"
5554 [(set_attr "type" "fp")])
5555 \f
5556 ;; Conversions to and from floating-point.
5558 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5559 ; don't want to support putting SImode in FPR registers.
5560 (define_insn "lfiwax"
5561 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5562 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5563 UNSPEC_LFIWAX))]
5564 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5565 "lfiwax %0,%y1"
5566 [(set_attr "type" "fpload")])
5568 ; This split must be run before register allocation because it allocates the
5569 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5570 ; it earlier to allow for the combiner to merge insns together where it might
5571 ; not be needed and also in case the insns are deleted as dead code.
5573 (define_insn_and_split "floatsi<mode>2_lfiwax"
5574 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5575 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5576 (clobber (match_scratch:DI 2 "=d"))]
5577 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5578 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5579 "#"
5580 ""
5581 [(pc)]
5582 "
5583 {
5584 rtx dest = operands[0];
5585 rtx src = operands[1];
5586 rtx tmp;
5588 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5589 tmp = convert_to_mode (DImode, src, false);
5590 else
5591 {
5592 tmp = operands[2];
5593 if (GET_CODE (tmp) == SCRATCH)
5594 tmp = gen_reg_rtx (DImode);
5595 if (MEM_P (src))
5596 {
5597 src = rs6000_address_for_fpconvert (src);
5598 emit_insn (gen_lfiwax (tmp, src));
5599 }
5600 else
5601 {
5602 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5603 emit_move_insn (stack, src);
5604 emit_insn (gen_lfiwax (tmp, stack));
5605 }
5606 }
5607 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5608 DONE;
5609 }"
5610 [(set_attr "length" "12")
5611 (set_attr "type" "fpload")])
5613 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5614 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5615 (float:SFDF
5616 (sign_extend:DI
5617 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5618 (clobber (match_scratch:DI 2 "=0,d"))]
5619 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5620 && <SI_CONVERT_FP>"
5621 "#"
5622 ""
5623 [(pc)]
5624 "
5625 {
5626 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5627 if (GET_CODE (operands[2]) == SCRATCH)
5628 operands[2] = gen_reg_rtx (DImode);
5629 emit_insn (gen_lfiwax (operands[2], operands[1]));
5630 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5631 DONE;
5632 }"
5633 [(set_attr "length" "8")
5634 (set_attr "type" "fpload")])
5636 (define_insn "lfiwzx"
5637 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5638 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5639 UNSPEC_LFIWZX))]
5640 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5641 "lfiwzx %0,%y1"
5642 [(set_attr "type" "fpload")])
5644 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5645 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5646 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5647 (clobber (match_scratch:DI 2 "=d"))]
5648 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5649 && <SI_CONVERT_FP>"
5650 "#"
5651 ""
5652 [(pc)]
5653 "
5654 {
5655 rtx dest = operands[0];
5656 rtx src = operands[1];
5657 rtx tmp;
5659 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5660 tmp = convert_to_mode (DImode, src, true);
5661 else
5662 {
5663 tmp = operands[2];
5664 if (GET_CODE (tmp) == SCRATCH)
5665 tmp = gen_reg_rtx (DImode);
5666 if (MEM_P (src))
5667 {
5668 src = rs6000_address_for_fpconvert (src);
5669 emit_insn (gen_lfiwzx (tmp, src));
5670 }
5671 else
5672 {
5673 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5674 emit_move_insn (stack, src);
5675 emit_insn (gen_lfiwzx (tmp, stack));
5676 }
5677 }
5678 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5679 DONE;
5680 }"
5681 [(set_attr "length" "12")
5682 (set_attr "type" "fpload")])
5684 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5685 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5686 (unsigned_float:SFDF
5687 (zero_extend:DI
5688 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5689 (clobber (match_scratch:DI 2 "=0,d"))]
5690 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5691 && <SI_CONVERT_FP>"
5692 "#"
5693 ""
5694 [(pc)]
5695 "
5696 {
5697 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5698 if (GET_CODE (operands[2]) == SCRATCH)
5699 operands[2] = gen_reg_rtx (DImode);
5700 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5701 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5702 DONE;
5703 }"
5704 [(set_attr "length" "8")
5705 (set_attr "type" "fpload")])
5707 ; For each of these conversions, there is a define_expand, a define_insn
5708 ; with a '#' template, and a define_split (with C code). The idea is
5709 ; to allow constant folding with the template of the define_insn,
5710 ; then to have the insns split later (between sched1 and final).
5712 (define_expand "floatsidf2"
5713 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5714 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5715 (use (match_dup 2))
5716 (use (match_dup 3))
5717 (clobber (match_dup 4))
5718 (clobber (match_dup 5))
5719 (clobber (match_dup 6))])]
5720 "TARGET_HARD_FLOAT
5721 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5722 "
5723 {
5724 if (TARGET_E500_DOUBLE)
5725 {
5726 if (!REG_P (operands[1]))
5727 operands[1] = force_reg (SImode, operands[1]);
5728 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5729 DONE;
5730 }
5731 else if (TARGET_LFIWAX && TARGET_FCFID)
5732 {
5733 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5734 DONE;
5735 }
5736 else if (TARGET_FCFID)
5737 {
5738 rtx dreg = operands[1];
5739 if (!REG_P (dreg))
5740 dreg = force_reg (SImode, dreg);
5741 dreg = convert_to_mode (DImode, dreg, false);
5742 emit_insn (gen_floatdidf2 (operands[0], dreg));
5743 DONE;
5744 }
5746 if (!REG_P (operands[1]))
5747 operands[1] = force_reg (SImode, operands[1]);
5748 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5749 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5750 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5751 operands[5] = gen_reg_rtx (DFmode);
5752 operands[6] = gen_reg_rtx (SImode);
5753 }")
5755 (define_insn_and_split "*floatsidf2_internal"
5756 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5757 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5758 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5759 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5760 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5761 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5762 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5763 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5764 "#"
5765 ""
5766 [(pc)]
5767 "
5768 {
5769 rtx lowword, highword;
5770 gcc_assert (MEM_P (operands[4]));
5771 highword = adjust_address (operands[4], SImode, 0);
5772 lowword = adjust_address (operands[4], SImode, 4);
5773 if (! WORDS_BIG_ENDIAN)
5774 {
5775 rtx tmp;
5776 tmp = highword; highword = lowword; lowword = tmp;
5777 }
5779 emit_insn (gen_xorsi3 (operands[6], operands[1],
5780 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5781 emit_move_insn (lowword, operands[6]);
5782 emit_move_insn (highword, operands[2]);
5783 emit_move_insn (operands[5], operands[4]);
5784 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5785 DONE;
5786 }"
5787 [(set_attr "length" "24")
5788 (set_attr "type" "fp")])
5790 ;; If we don't have a direct conversion to single precision, don't enable this
5791 ;; conversion for 32-bit without fast math, because we don't have the insn to
5792 ;; generate the fixup swizzle to avoid double rounding problems.
5793 (define_expand "floatunssisf2"
5794 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5795 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5796 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5797 && (!TARGET_FPRS
5798 || (TARGET_FPRS
5799 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5800 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5801 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5802 "
5803 {
5804 if (!TARGET_FPRS)
5805 {
5806 if (!REG_P (operands[1]))
5807 operands[1] = force_reg (SImode, operands[1]);
5808 }
5809 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5810 {
5811 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5812 DONE;
5813 }
5814 else
5815 {
5816 rtx dreg = operands[1];
5817 if (!REG_P (dreg))
5818 dreg = force_reg (SImode, dreg);
5819 dreg = convert_to_mode (DImode, dreg, true);
5820 emit_insn (gen_floatdisf2 (operands[0], dreg));
5821 DONE;
5822 }
5823 }")
5825 (define_expand "floatunssidf2"
5826 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5827 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5828 (use (match_dup 2))
5829 (use (match_dup 3))
5830 (clobber (match_dup 4))
5831 (clobber (match_dup 5))])]
5832 "TARGET_HARD_FLOAT
5833 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5834 "
5835 {
5836 if (TARGET_E500_DOUBLE)
5837 {
5838 if (!REG_P (operands[1]))
5839 operands[1] = force_reg (SImode, operands[1]);
5840 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5841 DONE;
5842 }
5843 else if (TARGET_LFIWZX && TARGET_FCFID)
5844 {
5845 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5846 DONE;
5847 }
5848 else if (TARGET_FCFID)
5849 {
5850 rtx dreg = operands[1];
5851 if (!REG_P (dreg))
5852 dreg = force_reg (SImode, dreg);
5853 dreg = convert_to_mode (DImode, dreg, true);
5854 emit_insn (gen_floatdidf2 (operands[0], dreg));
5855 DONE;
5856 }
5858 if (!REG_P (operands[1]))
5859 operands[1] = force_reg (SImode, operands[1]);
5860 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5861 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5862 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5863 operands[5] = gen_reg_rtx (DFmode);
5864 }")
5866 (define_insn_and_split "*floatunssidf2_internal"
5867 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5868 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5869 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5870 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5871 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5872 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5873 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5874 && !(TARGET_FCFID && TARGET_POWERPC64)"
5875 "#"
5876 ""
5877 [(pc)]
5878 "
5879 {
5880 rtx lowword, highword;
5881 gcc_assert (MEM_P (operands[4]));
5882 highword = adjust_address (operands[4], SImode, 0);
5883 lowword = adjust_address (operands[4], SImode, 4);
5884 if (! WORDS_BIG_ENDIAN)
5885 {
5886 rtx tmp;
5887 tmp = highword; highword = lowword; lowword = tmp;
5888 }
5890 emit_move_insn (lowword, operands[1]);
5891 emit_move_insn (highword, operands[2]);
5892 emit_move_insn (operands[5], operands[4]);
5893 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5894 DONE;
5895 }"
5896 [(set_attr "length" "20")
5897 (set_attr "type" "fp")])
5899 (define_expand "fix_trunc<mode>si2"
5900 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5901 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5902 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5903 "
5904 {
5905 if (!<E500_CONVERT>)
5906 {
5907 rtx tmp, stack;
5909 if (TARGET_STFIWX)
5910 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5911 else
5912 {
5913 tmp = gen_reg_rtx (DImode);
5914 stack = rs6000_allocate_stack_temp (DImode, true, false);
5915 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5916 tmp, stack));
5917 }
5918 DONE;
5919 }
5920 }")
5922 ; Like the convert to float patterns, this insn must be split before
5923 ; register allocation so that it can allocate the memory slot if it
5924 ; needed
5925 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5926 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5927 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5928 (clobber (match_scratch:DI 2 "=d"))]
5929 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5930 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5931 && TARGET_STFIWX && can_create_pseudo_p ()"
5932 "#"
5933 ""
5934 [(pc)]
5935 {
5936 rtx dest = operands[0];
5937 rtx src = operands[1];
5938 rtx tmp = operands[2];
5940 if (GET_CODE (tmp) == SCRATCH)
5941 tmp = gen_reg_rtx (DImode);
5943 emit_insn (gen_fctiwz_<mode> (tmp, src));
5944 if (MEM_P (dest))
5945 {
5946 dest = rs6000_address_for_fpconvert (dest);
5947 emit_insn (gen_stfiwx (dest, tmp));
5948 DONE;
5949 }
5950 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5951 {
5952 dest = gen_lowpart (DImode, dest);
5953 emit_move_insn (dest, tmp);
5954 DONE;
5955 }
5956 else
5957 {
5958 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5959 emit_insn (gen_stfiwx (stack, tmp));
5960 emit_move_insn (dest, stack);
5961 DONE;
5962 }
5963 }
5964 [(set_attr "length" "12")
5965 (set_attr "type" "fp")])
5967 (define_insn_and_split "fix_trunc<mode>si2_internal"
5968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5969 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5970 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5971 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5972 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5973 "#"
5974 ""
5975 [(pc)]
5976 "
5977 {
5978 rtx lowword;
5979 gcc_assert (MEM_P (operands[3]));
5980 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5982 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5983 emit_move_insn (operands[3], operands[2]);
5984 emit_move_insn (operands[0], lowword);
5985 DONE;
5986 }"
5987 [(set_attr "length" "16")
5988 (set_attr "type" "fp")])
5990 (define_expand "fix_trunc<mode>di2"
5991 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5992 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5993 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5994 && TARGET_FCFID"
5995 "")
5997 (define_insn "*fix_trunc<mode>di2_fctidz"
5998 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5999 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6000 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6001 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6002 "fctidz %0,%1"
6003 [(set_attr "type" "fp")])
6005 (define_expand "fixuns_trunc<mode>si2"
6006 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6007 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6008 "TARGET_HARD_FLOAT
6009 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6010 || <E500_CONVERT>)"
6011 "
6012 {
6013 if (!<E500_CONVERT>)
6014 {
6015 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6016 DONE;
6017 }
6018 }")
6020 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6021 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6022 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6023 (clobber (match_scratch:DI 2 "=d"))]
6024 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6025 && TARGET_STFIWX && can_create_pseudo_p ()"
6026 "#"
6027 ""
6028 [(pc)]
6029 {
6030 rtx dest = operands[0];
6031 rtx src = operands[1];
6032 rtx tmp = operands[2];
6034 if (GET_CODE (tmp) == SCRATCH)
6035 tmp = gen_reg_rtx (DImode);
6037 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6038 if (MEM_P (dest))
6039 {
6040 dest = rs6000_address_for_fpconvert (dest);
6041 emit_insn (gen_stfiwx (dest, tmp));
6042 DONE;
6043 }
6044 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6045 {
6046 dest = gen_lowpart (DImode, dest);
6047 emit_move_insn (dest, tmp);
6048 DONE;
6049 }
6050 else
6051 {
6052 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6053 emit_insn (gen_stfiwx (stack, tmp));
6054 emit_move_insn (dest, stack);
6055 DONE;
6056 }
6057 }
6058 [(set_attr "length" "12")
6059 (set_attr "type" "fp")])
6061 (define_expand "fixuns_trunc<mode>di2"
6062 [(set (match_operand:DI 0 "register_operand" "")
6063 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6064 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6065 "")
6067 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6068 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6069 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6070 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6071 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6072 "fctiduz %0,%1"
6073 [(set_attr "type" "fp")])
6075 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6076 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6077 ; because the first makes it clear that operand 0 is not live
6078 ; before the instruction.
6079 (define_insn "fctiwz_<mode>"
6080 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6081 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6082 UNSPEC_FCTIWZ))]
6083 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6084 "fctiwz %0,%1"
6085 [(set_attr "type" "fp")])
6087 (define_insn "fctiwuz_<mode>"
6088 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6089 (unspec:DI [(unsigned_fix:SI
6090 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6091 UNSPEC_FCTIWUZ))]
6092 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6093 "fctiwuz %0,%1"
6094 [(set_attr "type" "fp")])
6096 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6097 ;; since the friz instruction does not truncate the value if the floating
6098 ;; point value is < LONG_MIN or > LONG_MAX.
6099 (define_insn "*friz"
6100 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6101 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6102 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6103 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6104 && !flag_trapping_math && TARGET_FRIZ"
6105 "friz %0,%1"
6106 [(set_attr "type" "fp")])
6108 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6109 ;; load to properly sign extend the value, but at least doing a store, load
6110 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6111 ;; if we have 32-bit memory ops
6112 (define_insn_and_split "*round32<mode>2_fprs"
6113 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6114 (float:SFDF
6115 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6116 (clobber (match_scratch:DI 2 "=d"))
6117 (clobber (match_scratch:DI 3 "=d"))]
6118 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6119 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6120 && can_create_pseudo_p ()"
6121 "#"
6122 ""
6123 [(pc)]
6124 {
6125 rtx dest = operands[0];
6126 rtx src = operands[1];
6127 rtx tmp1 = operands[2];
6128 rtx tmp2 = operands[3];
6129 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6131 if (GET_CODE (tmp1) == SCRATCH)
6132 tmp1 = gen_reg_rtx (DImode);
6133 if (GET_CODE (tmp2) == SCRATCH)
6134 tmp2 = gen_reg_rtx (DImode);
6136 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6137 emit_insn (gen_stfiwx (stack, tmp1));
6138 emit_insn (gen_lfiwax (tmp2, stack));
6139 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6140 DONE;
6141 }
6142 [(set_attr "type" "fpload")
6143 (set_attr "length" "16")])
6145 (define_insn_and_split "*roundu32<mode>2_fprs"
6146 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6147 (unsigned_float:SFDF
6148 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6149 (clobber (match_scratch:DI 2 "=d"))
6150 (clobber (match_scratch:DI 3 "=d"))]
6151 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6152 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6153 && can_create_pseudo_p ()"
6154 "#"
6155 ""
6156 [(pc)]
6157 {
6158 rtx dest = operands[0];
6159 rtx src = operands[1];
6160 rtx tmp1 = operands[2];
6161 rtx tmp2 = operands[3];
6162 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6164 if (GET_CODE (tmp1) == SCRATCH)
6165 tmp1 = gen_reg_rtx (DImode);
6166 if (GET_CODE (tmp2) == SCRATCH)
6167 tmp2 = gen_reg_rtx (DImode);
6169 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6170 emit_insn (gen_stfiwx (stack, tmp1));
6171 emit_insn (gen_lfiwzx (tmp2, stack));
6172 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6173 DONE;
6174 }
6175 [(set_attr "type" "fpload")
6176 (set_attr "length" "16")])
6178 ;; No VSX equivalent to fctid
6179 (define_insn "lrint<mode>di2"
6180 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6181 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6182 UNSPEC_FCTID))]
6183 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6184 "fctid %0,%1"
6185 [(set_attr "type" "fp")])
6187 (define_expand "btrunc<mode>2"
6188 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6189 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6190 UNSPEC_FRIZ))]
6191 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6192 "")
6194 (define_insn "*btrunc<mode>2_fpr"
6195 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6196 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6197 UNSPEC_FRIZ))]
6198 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6199 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6200 "friz %0,%1"
6201 [(set_attr "type" "fp")])
6203 (define_expand "ceil<mode>2"
6204 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6205 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6206 UNSPEC_FRIP))]
6207 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6208 "")
6210 (define_insn "*ceil<mode>2_fpr"
6211 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6212 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6213 UNSPEC_FRIP))]
6214 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6215 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6216 "frip %0,%1"
6217 [(set_attr "type" "fp")])
6219 (define_expand "floor<mode>2"
6220 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6221 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6222 UNSPEC_FRIM))]
6223 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6224 "")
6226 (define_insn "*floor<mode>2_fpr"
6227 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6228 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6229 UNSPEC_FRIM))]
6230 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6231 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6232 "frim %0,%1"
6233 [(set_attr "type" "fp")])
6235 ;; No VSX equivalent to frin
6236 (define_insn "round<mode>2"
6237 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6238 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6239 UNSPEC_FRIN))]
6240 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6241 "frin %0,%1"
6242 [(set_attr "type" "fp")])
6244 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6245 (define_insn "stfiwx"
6246 [(set (match_operand:SI 0 "memory_operand" "=Z")
6247 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6248 UNSPEC_STFIWX))]
6249 "TARGET_PPC_GFXOPT"
6250 "stfiwx %1,%y0"
6251 [(set_attr "type" "fpstore")])
6253 ;; If we don't have a direct conversion to single precision, don't enable this
6254 ;; conversion for 32-bit without fast math, because we don't have the insn to
6255 ;; generate the fixup swizzle to avoid double rounding problems.
6256 (define_expand "floatsisf2"
6257 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6258 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6259 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6260 && (!TARGET_FPRS
6261 || (TARGET_FPRS
6262 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6263 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6264 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6265 "
6266 {
6267 if (!TARGET_FPRS)
6268 {
6269 if (!REG_P (operands[1]))
6270 operands[1] = force_reg (SImode, operands[1]);
6271 }
6272 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6273 {
6274 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6275 DONE;
6276 }
6277 else if (TARGET_FCFID && TARGET_LFIWAX)
6278 {
6279 rtx dfreg = gen_reg_rtx (DFmode);
6280 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6281 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6282 DONE;
6283 }
6284 else
6285 {
6286 rtx dreg = operands[1];
6287 if (!REG_P (dreg))
6288 dreg = force_reg (SImode, dreg);
6289 dreg = convert_to_mode (DImode, dreg, false);
6290 emit_insn (gen_floatdisf2 (operands[0], dreg));
6291 DONE;
6292 }
6293 }")
6295 (define_expand "floatdidf2"
6296 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6297 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6298 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6299 "")
6301 (define_insn "*floatdidf2_fpr"
6302 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6303 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6304 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6305 && !VECTOR_UNIT_VSX_P (DFmode)"
6306 "fcfid %0,%1"
6307 [(set_attr "type" "fp")])
6309 ; Allow the combiner to merge source memory operands to the conversion so that
6310 ; the optimizer/register allocator doesn't try to load the value too early in a
6311 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6312 ; hit. We will split after reload to avoid the trip through the GPRs
6314 (define_insn_and_split "*floatdidf2_mem"
6315 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6316 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6317 (clobber (match_scratch:DI 2 "=d"))]
6318 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6319 "#"
6320 "&& reload_completed"
6321 [(set (match_dup 2) (match_dup 1))
6322 (set (match_dup 0) (float:DF (match_dup 2)))]
6323 ""
6324 [(set_attr "length" "8")
6325 (set_attr "type" "fpload")])
6327 (define_expand "floatunsdidf2"
6328 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6329 (unsigned_float:DF
6330 (match_operand:DI 1 "gpc_reg_operand" "")))]
6331 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6332 "")
6334 (define_insn "*floatunsdidf2_fcfidu"
6335 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6336 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6337 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6338 "fcfidu %0,%1"
6339 [(set_attr "type" "fp")
6340 (set_attr "length" "4")])
6342 (define_insn_and_split "*floatunsdidf2_mem"
6343 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6344 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6345 (clobber (match_scratch:DI 2 "=d"))]
6346 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6347 "#"
6348 "&& reload_completed"
6349 [(set (match_dup 2) (match_dup 1))
6350 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6351 ""
6352 [(set_attr "length" "8")
6353 (set_attr "type" "fpload")])
6355 (define_expand "floatdisf2"
6356 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6357 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6358 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6359 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6360 "
6361 {
6362 if (!TARGET_FCFIDS)
6363 {
6364 rtx val = operands[1];
6365 if (!flag_unsafe_math_optimizations)
6366 {
6367 rtx label = gen_label_rtx ();
6368 val = gen_reg_rtx (DImode);
6369 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6370 emit_label (label);
6371 }
6372 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6373 DONE;
6374 }
6375 }")
6377 (define_insn "floatdisf2_fcfids"
6378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6379 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6380 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6381 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6382 "fcfids %0,%1"
6383 [(set_attr "type" "fp")])
6385 (define_insn_and_split "*floatdisf2_mem"
6386 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6387 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6388 (clobber (match_scratch:DI 2 "=f"))]
6389 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6390 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6391 "#"
6392 "&& reload_completed"
6393 [(pc)]
6394 "
6395 {
6396 emit_move_insn (operands[2], operands[1]);
6397 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6398 DONE;
6399 }"
6400 [(set_attr "length" "8")])
6402 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6403 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6404 ;; from double rounding.
6405 ;; Instead of creating a new cpu type for two FP operations, just use fp
6406 (define_insn_and_split "floatdisf2_internal1"
6407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6408 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6409 (clobber (match_scratch:DF 2 "=d"))]
6410 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6411 "#"
6412 "&& reload_completed"
6413 [(set (match_dup 2)
6414 (float:DF (match_dup 1)))
6415 (set (match_dup 0)
6416 (float_truncate:SF (match_dup 2)))]
6417 ""
6418 [(set_attr "length" "8")
6419 (set_attr "type" "fp")])
6421 ;; Twiddles bits to avoid double rounding.
6422 ;; Bits that might be truncated when converting to DFmode are replaced
6423 ;; by a bit that won't be lost at that stage, but is below the SFmode
6424 ;; rounding position.
6425 (define_expand "floatdisf2_internal2"
6426 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6427 (const_int 53)))
6428 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6429 (const_int 2047)))
6430 (clobber (scratch:CC))])
6431 (set (match_dup 3) (plus:DI (match_dup 3)
6432 (const_int 1)))
6433 (set (match_dup 0) (plus:DI (match_dup 0)
6434 (const_int 2047)))
6435 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6436 (const_int 2)))
6437 (set (match_dup 0) (ior:DI (match_dup 0)
6438 (match_dup 1)))
6439 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6440 (const_int -2048)))
6441 (clobber (scratch:CC))])
6442 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6443 (label_ref (match_operand:DI 2 "" ""))
6444 (pc)))
6445 (set (match_dup 0) (match_dup 1))]
6446 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6447 "
6448 {
6449 operands[3] = gen_reg_rtx (DImode);
6450 operands[4] = gen_reg_rtx (CCUNSmode);
6451 }")
6453 (define_expand "floatunsdisf2"
6454 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6455 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6456 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6457 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6458 "")
6460 (define_insn "floatunsdisf2_fcfidus"
6461 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6462 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6463 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6464 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6465 "fcfidus %0,%1"
6466 [(set_attr "type" "fp")])
6468 (define_insn_and_split "*floatunsdisf2_mem"
6469 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6470 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6471 (clobber (match_scratch:DI 2 "=f"))]
6472 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6473 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6474 "#"
6475 "&& reload_completed"
6476 [(pc)]
6477 "
6478 {
6479 emit_move_insn (operands[2], operands[1]);
6480 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6481 DONE;
6482 }"
6483 [(set_attr "length" "8")
6484 (set_attr "type" "fpload")])
6485 \f
6486 ;; Define the DImode operations that can be done in a small number
6487 ;; of instructions. The & constraints are to prevent the register
6488 ;; allocator from allocating registers that overlap with the inputs
6489 ;; (for example, having an input in 7,8 and an output in 6,7). We
6490 ;; also allow for the output being the same as one of the inputs.
6492 (define_insn "*adddi3_noppc64"
6493 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6494 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6495 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6496 "! TARGET_POWERPC64"
6497 "*
6498 {
6499 if (WORDS_BIG_ENDIAN)
6500 return (GET_CODE (operands[2])) != CONST_INT
6501 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6502 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6503 else
6504 return (GET_CODE (operands[2])) != CONST_INT
6505 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6506 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6507 }"
6508 [(set_attr "type" "two")
6509 (set_attr "length" "8")])
6511 (define_insn "*subdi3_noppc64"
6512 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6513 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6514 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6515 "! TARGET_POWERPC64"
6516 "*
6517 {
6518 if (WORDS_BIG_ENDIAN)
6519 return (GET_CODE (operands[1]) != CONST_INT)
6520 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6521 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6522 else
6523 return (GET_CODE (operands[1]) != CONST_INT)
6524 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6525 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6526 }"
6527 [(set_attr "type" "two")
6528 (set_attr "length" "8")])
6530 (define_insn "*negdi2_noppc64"
6531 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6532 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6533 "! TARGET_POWERPC64"
6534 "*
6535 {
6536 return (WORDS_BIG_ENDIAN)
6537 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6538 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6539 }"
6540 [(set_attr "type" "two")
6541 (set_attr "length" "8")])
6543 (define_insn "mulsidi3"
6544 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6545 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6546 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6547 "! TARGET_POWERPC64"
6548 {
6549 return (WORDS_BIG_ENDIAN)
6550 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6551 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6552 }
6553 [(set_attr "type" "imul")
6554 (set_attr "length" "8")])
6556 (define_split
6557 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6558 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6559 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6560 "! TARGET_POWERPC64 && reload_completed"
6561 [(set (match_dup 3)
6562 (truncate:SI
6563 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6564 (sign_extend:DI (match_dup 2)))
6565 (const_int 32))))
6566 (set (match_dup 4)
6567 (mult:SI (match_dup 1)
6568 (match_dup 2)))]
6569 "
6570 {
6571 int endian = (WORDS_BIG_ENDIAN == 0);
6572 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6573 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6574 }")
6576 (define_insn "umulsidi3"
6577 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6578 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6579 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6580 "! TARGET_POWERPC64"
6581 "*
6582 {
6583 return (WORDS_BIG_ENDIAN)
6584 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6585 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6586 }"
6587 [(set_attr "type" "imul")
6588 (set_attr "length" "8")])
6590 (define_split
6591 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6592 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6593 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6594 "! TARGET_POWERPC64 && reload_completed"
6595 [(set (match_dup 3)
6596 (truncate:SI
6597 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6598 (zero_extend:DI (match_dup 2)))
6599 (const_int 32))))
6600 (set (match_dup 4)
6601 (mult:SI (match_dup 1)
6602 (match_dup 2)))]
6603 "
6604 {
6605 int endian = (WORDS_BIG_ENDIAN == 0);
6606 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6607 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6608 }")
6610 (define_insn "smulsi3_highpart"
6611 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6612 (truncate:SI
6613 (lshiftrt:DI (mult:DI (sign_extend:DI
6614 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6615 (sign_extend:DI
6616 (match_operand:SI 2 "gpc_reg_operand" "r")))
6617 (const_int 32))))]
6618 ""
6619 "mulhw %0,%1,%2"
6620 [(set_attr "type" "imul")])
6622 (define_insn "umulsi3_highpart"
6623 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6624 (truncate:SI
6625 (lshiftrt:DI (mult:DI (zero_extend:DI
6626 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6627 (zero_extend:DI
6628 (match_operand:SI 2 "gpc_reg_operand" "r")))
6629 (const_int 32))))]
6630 ""
6631 "mulhwu %0,%1,%2"
6632 [(set_attr "type" "imul")])
6634 ;; Shift by a variable amount is too complex to be worth open-coding. We
6635 ;; just handle shifts by constants.
6636 (define_insn "ashrdi3_no_power"
6637 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6638 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6639 (match_operand:SI 2 "const_int_operand" "M,i")))]
6640 "!TARGET_POWERPC64"
6641 "*
6642 {
6643 switch (which_alternative)
6644 {
6645 default:
6646 gcc_unreachable ();
6647 case 0:
6648 if (WORDS_BIG_ENDIAN)
6649 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6650 else
6651 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6652 case 1:
6653 if (WORDS_BIG_ENDIAN)
6654 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6655 else
6656 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6657 }
6658 }"
6659 [(set_attr "type" "two,three")
6660 (set_attr "length" "8,12")])
6662 (define_insn "*ashrdisi3_noppc64be"
6663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6664 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6665 (const_int 32)) 4))]
6666 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6667 "*
6668 {
6669 if (REGNO (operands[0]) == REGNO (operands[1]))
6670 return \"\";
6671 else
6672 return \"mr %0,%1\";
6673 }"
6674 [(set_attr "length" "4")])
6676 \f
6677 ;; PowerPC64 DImode operations.
6679 (define_insn "muldi3"
6680 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6681 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6682 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6683 "TARGET_POWERPC64"
6684 "@
6685 mulld %0,%1,%2
6686 mulli %0,%1,%2"
6687 [(set (attr "type")
6688 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6689 (const_string "imul3")
6690 (match_operand:SI 2 "short_cint_operand" "")
6691 (const_string "imul2")]
6692 (const_string "lmul")))])
6694 (define_insn "*muldi3_internal1"
6695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6696 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6697 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6698 (const_int 0)))
6699 (clobber (match_scratch:DI 3 "=r,r"))]
6700 "TARGET_POWERPC64"
6701 "@
6702 mulld. %3,%1,%2
6703 #"
6704 [(set_attr "type" "lmul_compare")
6705 (set_attr "length" "4,8")])
6707 (define_split
6708 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6709 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6710 (match_operand:DI 2 "gpc_reg_operand" ""))
6711 (const_int 0)))
6712 (clobber (match_scratch:DI 3 ""))]
6713 "TARGET_POWERPC64 && reload_completed"
6714 [(set (match_dup 3)
6715 (mult:DI (match_dup 1) (match_dup 2)))
6716 (set (match_dup 0)
6717 (compare:CC (match_dup 3)
6718 (const_int 0)))]
6719 "")
6721 (define_insn "*muldi3_internal2"
6722 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6723 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6724 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6725 (const_int 0)))
6726 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6727 (mult:DI (match_dup 1) (match_dup 2)))]
6728 "TARGET_POWERPC64"
6729 "@
6730 mulld. %0,%1,%2
6731 #"
6732 [(set_attr "type" "lmul_compare")
6733 (set_attr "length" "4,8")])
6735 (define_split
6736 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6737 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6738 (match_operand:DI 2 "gpc_reg_operand" ""))
6739 (const_int 0)))
6740 (set (match_operand:DI 0 "gpc_reg_operand" "")
6741 (mult:DI (match_dup 1) (match_dup 2)))]
6742 "TARGET_POWERPC64 && reload_completed"
6743 [(set (match_dup 0)
6744 (mult:DI (match_dup 1) (match_dup 2)))
6745 (set (match_dup 3)
6746 (compare:CC (match_dup 0)
6747 (const_int 0)))]
6748 "")
6750 (define_insn "smuldi3_highpart"
6751 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6752 (truncate:DI
6753 (lshiftrt:TI (mult:TI (sign_extend:TI
6754 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6755 (sign_extend:TI
6756 (match_operand:DI 2 "gpc_reg_operand" "r")))
6757 (const_int 64))))]
6758 "TARGET_POWERPC64"
6759 "mulhd %0,%1,%2"
6760 [(set_attr "type" "lmul")])
6762 (define_insn "umuldi3_highpart"
6763 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6764 (truncate:DI
6765 (lshiftrt:TI (mult:TI (zero_extend:TI
6766 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6767 (zero_extend:TI
6768 (match_operand:DI 2 "gpc_reg_operand" "r")))
6769 (const_int 64))))]
6770 "TARGET_POWERPC64"
6771 "mulhdu %0,%1,%2"
6772 [(set_attr "type" "lmul")])
6774 (define_expand "mulditi3"
6775 [(set (match_operand:TI 0 "gpc_reg_operand")
6776 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6777 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6778 "TARGET_POWERPC64"
6779 {
6780 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6781 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6782 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6783 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6784 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6785 DONE;
6786 })
6788 (define_expand "umulditi3"
6789 [(set (match_operand:TI 0 "gpc_reg_operand")
6790 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6791 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6792 "TARGET_POWERPC64"
6793 {
6794 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6795 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6796 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6797 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6798 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6799 DONE;
6800 })
6802 (define_insn "rotldi3"
6803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6804 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6805 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6806 "TARGET_POWERPC64"
6807 "@
6808 rldcl %0,%1,%2,0
6809 rldicl %0,%1,%H2,0"
6810 [(set_attr "type" "var_shift_rotate,integer")])
6812 (define_insn "*rotldi3_internal2"
6813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6814 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6815 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6816 (const_int 0)))
6817 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6818 "TARGET_64BIT"
6819 "@
6820 rldcl. %3,%1,%2,0
6821 rldicl. %3,%1,%H2,0
6822 #
6823 #"
6824 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6825 (set_attr "length" "4,4,8,8")])
6827 (define_split
6828 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6829 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6830 (match_operand:DI 2 "reg_or_cint_operand" ""))
6831 (const_int 0)))
6832 (clobber (match_scratch:DI 3 ""))]
6833 "TARGET_POWERPC64 && reload_completed"
6834 [(set (match_dup 3)
6835 (rotate:DI (match_dup 1) (match_dup 2)))
6836 (set (match_dup 0)
6837 (compare:CC (match_dup 3)
6838 (const_int 0)))]
6839 "")
6841 (define_insn "*rotldi3_internal3"
6842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6843 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6844 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6845 (const_int 0)))
6846 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6847 (rotate:DI (match_dup 1) (match_dup 2)))]
6848 "TARGET_64BIT"
6849 "@
6850 rldcl. %0,%1,%2,0
6851 rldicl. %0,%1,%H2,0
6852 #
6853 #"
6854 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6855 (set_attr "length" "4,4,8,8")])
6857 (define_split
6858 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6859 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6860 (match_operand:DI 2 "reg_or_cint_operand" ""))
6861 (const_int 0)))
6862 (set (match_operand:DI 0 "gpc_reg_operand" "")
6863 (rotate:DI (match_dup 1) (match_dup 2)))]
6864 "TARGET_POWERPC64 && reload_completed"
6865 [(set (match_dup 0)
6866 (rotate:DI (match_dup 1) (match_dup 2)))
6867 (set (match_dup 3)
6868 (compare:CC (match_dup 0)
6869 (const_int 0)))]
6870 "")
6872 (define_insn "*rotldi3_internal4"
6873 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6874 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6875 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6876 (match_operand:DI 3 "mask64_operand" "n,n")))]
6877 "TARGET_POWERPC64"
6878 "@
6879 rldc%B3 %0,%1,%2,%S3
6880 rldic%B3 %0,%1,%H2,%S3"
6881 [(set_attr "type" "var_shift_rotate,integer")])
6883 (define_insn "*rotldi3_internal5"
6884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6885 (compare:CC (and:DI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6887 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6888 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6891 "TARGET_64BIT"
6892 "@
6893 rldc%B3. %4,%1,%2,%S3
6894 rldic%B3. %4,%1,%H2,%S3
6895 #
6896 #"
6897 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6898 (set_attr "length" "4,4,8,8")])
6900 (define_split
6901 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6902 (compare:CC (and:DI
6903 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6904 (match_operand:DI 2 "reg_or_cint_operand" ""))
6905 (match_operand:DI 3 "mask64_operand" ""))
6906 (const_int 0)))
6907 (clobber (match_scratch:DI 4 ""))]
6908 "TARGET_POWERPC64 && reload_completed"
6909 [(set (match_dup 4)
6910 (and:DI (rotate:DI (match_dup 1)
6911 (match_dup 2))
6912 (match_dup 3)))
6913 (set (match_dup 0)
6914 (compare:CC (match_dup 4)
6915 (const_int 0)))]
6916 "")
6918 (define_insn "*rotldi3_internal6"
6919 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6920 (compare:CC (and:DI
6921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6922 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6923 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6926 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6927 "TARGET_64BIT"
6928 "@
6929 rldc%B3. %0,%1,%2,%S3
6930 rldic%B3. %0,%1,%H2,%S3
6931 #
6932 #"
6933 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6934 (set_attr "length" "4,4,8,8")])
6936 (define_split
6937 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6938 (compare:CC (and:DI
6939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:DI 2 "reg_or_cint_operand" ""))
6941 (match_operand:DI 3 "mask64_operand" ""))
6942 (const_int 0)))
6943 (set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6945 "TARGET_POWERPC64 && reload_completed"
6946 [(set (match_dup 0)
6947 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6948 (set (match_dup 4)
6949 (compare:CC (match_dup 0)
6950 (const_int 0)))]
6951 "")
6953 (define_insn "*rotldi3_internal7le"
6954 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6955 (zero_extend:DI
6956 (subreg:QI
6957 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6958 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6959 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6960 "@
6961 rldcl %0,%1,%2,56
6962 rldicl %0,%1,%H2,56"
6963 [(set_attr "type" "var_shift_rotate,integer")])
6965 (define_insn "*rotldi3_internal7be"
6966 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6967 (zero_extend:DI
6968 (subreg:QI
6969 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6970 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
6971 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6972 "@
6973 rldcl %0,%1,%2,56
6974 rldicl %0,%1,%H2,56"
6975 [(set_attr "type" "var_shift_rotate,integer")])
6977 (define_insn "*rotldi3_internal8le"
6978 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6979 (compare:CC (zero_extend:DI
6980 (subreg:QI
6981 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6982 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6983 (const_int 0)))
6984 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6985 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6986 "@
6987 rldcl. %3,%1,%2,56
6988 rldicl. %3,%1,%H2,56
6989 #
6990 #"
6991 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6992 (set_attr "length" "4,4,8,8")])
6994 (define_insn "*rotldi3_internal8be"
6995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6996 (compare:CC (zero_extend:DI
6997 (subreg:QI
6998 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6999 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7000 (const_int 0)))
7001 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7002 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7003 "@
7004 rldcl. %3,%1,%2,56
7005 rldicl. %3,%1,%H2,56
7006 #
7007 #"
7008 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7009 (set_attr "length" "4,4,8,8")])
7011 (define_split
7012 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7013 (compare:CC (zero_extend:DI
7014 (subreg:QI
7015 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7016 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7017 (const_int 0)))
7018 (clobber (match_scratch:DI 3 ""))]
7019 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7020 [(set (match_dup 3)
7021 (zero_extend:DI (subreg:QI
7022 (rotate:DI (match_dup 1)
7023 (match_dup 2)) 0)))
7024 (set (match_dup 0)
7025 (compare:CC (match_dup 3)
7026 (const_int 0)))]
7027 "")
7029 (define_split
7030 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7031 (compare:CC (zero_extend:DI
7032 (subreg:QI
7033 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7034 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7035 (const_int 0)))
7036 (clobber (match_scratch:DI 3 ""))]
7037 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7038 [(set (match_dup 3)
7039 (zero_extend:DI (subreg:QI
7040 (rotate:DI (match_dup 1)
7041 (match_dup 2)) 7)))
7042 (set (match_dup 0)
7043 (compare:CC (match_dup 3)
7044 (const_int 0)))]
7045 "")
7047 (define_insn "*rotldi3_internal9le"
7048 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7049 (compare:CC (zero_extend:DI
7050 (subreg:QI
7051 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7052 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7053 (const_int 0)))
7054 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7055 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7056 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7057 "@
7058 rldcl. %0,%1,%2,56
7059 rldicl. %0,%1,%H2,56
7060 #
7061 #"
7062 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7063 (set_attr "length" "4,4,8,8")])
7065 (define_insn "*rotldi3_internal9be"
7066 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7067 (compare:CC (zero_extend:DI
7068 (subreg:QI
7069 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7070 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7071 (const_int 0)))
7072 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7073 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7074 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7075 "@
7076 rldcl. %0,%1,%2,56
7077 rldicl. %0,%1,%H2,56
7078 #
7079 #"
7080 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7081 (set_attr "length" "4,4,8,8")])
7083 (define_split
7084 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7085 (compare:CC (zero_extend:DI
7086 (subreg:QI
7087 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7088 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7089 (const_int 0)))
7090 (set (match_operand:DI 0 "gpc_reg_operand" "")
7091 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7092 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7093 [(set (match_dup 0)
7094 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7095 (set (match_dup 3)
7096 (compare:CC (match_dup 0)
7097 (const_int 0)))]
7098 "")
7100 (define_split
7101 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7102 (compare:CC (zero_extend:DI
7103 (subreg:QI
7104 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7105 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7106 (const_int 0)))
7107 (set (match_operand:DI 0 "gpc_reg_operand" "")
7108 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7109 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7110 [(set (match_dup 0)
7111 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7112 (set (match_dup 3)
7113 (compare:CC (match_dup 0)
7114 (const_int 0)))]
7115 "")
7117 (define_insn "*rotldi3_internal10le"
7118 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7119 (zero_extend:DI
7120 (subreg:HI
7121 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7122 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7123 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7124 "@
7125 rldcl %0,%1,%2,48
7126 rldicl %0,%1,%H2,48"
7127 [(set_attr "type" "var_shift_rotate,integer")])
7129 (define_insn "*rotldi3_internal10be"
7130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7131 (zero_extend:DI
7132 (subreg:HI
7133 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7134 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7135 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7136 "@
7137 rldcl %0,%1,%2,48
7138 rldicl %0,%1,%H2,48"
7139 [(set_attr "type" "var_shift_rotate,integer")])
7141 (define_insn "*rotldi3_internal11le"
7142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7143 (compare:CC (zero_extend:DI
7144 (subreg:HI
7145 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7146 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7147 (const_int 0)))
7148 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7149 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7150 "@
7151 rldcl. %3,%1,%2,48
7152 rldicl. %3,%1,%H2,48
7153 #
7154 #"
7155 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7156 (set_attr "length" "4,4,8,8")])
7158 (define_insn "*rotldi3_internal11be"
7159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7160 (compare:CC (zero_extend:DI
7161 (subreg:HI
7162 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7163 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7164 (const_int 0)))
7165 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7166 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7167 "@
7168 rldcl. %3,%1,%2,48
7169 rldicl. %3,%1,%H2,48
7170 #
7171 #"
7172 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7173 (set_attr "length" "4,4,8,8")])
7175 (define_split
7176 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7177 (compare:CC (zero_extend:DI
7178 (subreg:HI
7179 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7180 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7181 (const_int 0)))
7182 (clobber (match_scratch:DI 3 ""))]
7183 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7184 [(set (match_dup 3)
7185 (zero_extend:DI (subreg:HI
7186 (rotate:DI (match_dup 1)
7187 (match_dup 2)) 0)))
7188 (set (match_dup 0)
7189 (compare:CC (match_dup 3)
7190 (const_int 0)))]
7191 "")
7193 (define_split
7194 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7195 (compare:CC (zero_extend:DI
7196 (subreg:HI
7197 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7198 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7199 (const_int 0)))
7200 (clobber (match_scratch:DI 3 ""))]
7201 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7202 [(set (match_dup 3)
7203 (zero_extend:DI (subreg:HI
7204 (rotate:DI (match_dup 1)
7205 (match_dup 2)) 6)))
7206 (set (match_dup 0)
7207 (compare:CC (match_dup 3)
7208 (const_int 0)))]
7209 "")
7211 (define_insn "*rotldi3_internal12le"
7212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7213 (compare:CC (zero_extend:DI
7214 (subreg:HI
7215 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7216 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7217 (const_int 0)))
7218 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7219 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7220 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7221 "@
7222 rldcl. %0,%1,%2,48
7223 rldicl. %0,%1,%H2,48
7224 #
7225 #"
7226 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7227 (set_attr "length" "4,4,8,8")])
7229 (define_insn "*rotldi3_internal12be"
7230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7231 (compare:CC (zero_extend:DI
7232 (subreg:HI
7233 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7234 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7235 (const_int 0)))
7236 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7237 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7238 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7239 "@
7240 rldcl. %0,%1,%2,48
7241 rldicl. %0,%1,%H2,48
7242 #
7243 #"
7244 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7245 (set_attr "length" "4,4,8,8")])
7247 (define_split
7248 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7249 (compare:CC (zero_extend:DI
7250 (subreg:HI
7251 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7252 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7253 (const_int 0)))
7254 (set (match_operand:DI 0 "gpc_reg_operand" "")
7255 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7256 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7257 [(set (match_dup 0)
7258 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7259 (set (match_dup 3)
7260 (compare:CC (match_dup 0)
7261 (const_int 0)))]
7262 "")
7264 (define_split
7265 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7266 (compare:CC (zero_extend:DI
7267 (subreg:HI
7268 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7269 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7270 (const_int 0)))
7271 (set (match_operand:DI 0 "gpc_reg_operand" "")
7272 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7273 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7274 [(set (match_dup 0)
7275 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7276 (set (match_dup 3)
7277 (compare:CC (match_dup 0)
7278 (const_int 0)))]
7279 "")
7281 (define_insn "*rotldi3_internal13le"
7282 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7283 (zero_extend:DI
7284 (subreg:SI
7285 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7286 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7287 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7288 "@
7289 rldcl %0,%1,%2,32
7290 rldicl %0,%1,%H2,32"
7291 [(set_attr "type" "var_shift_rotate,integer")])
7293 (define_insn "*rotldi3_internal13be"
7294 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7295 (zero_extend:DI
7296 (subreg:SI
7297 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7298 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7299 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7300 "@
7301 rldcl %0,%1,%2,32
7302 rldicl %0,%1,%H2,32"
7303 [(set_attr "type" "var_shift_rotate,integer")])
7305 (define_insn "*rotldi3_internal14le"
7306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7307 (compare:CC (zero_extend:DI
7308 (subreg:SI
7309 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7310 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7311 (const_int 0)))
7312 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7313 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7314 "@
7315 rldcl. %3,%1,%2,32
7316 rldicl. %3,%1,%H2,32
7317 #
7318 #"
7319 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7320 (set_attr "length" "4,4,8,8")])
7322 (define_insn "*rotldi3_internal14be"
7323 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7324 (compare:CC (zero_extend:DI
7325 (subreg:SI
7326 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7327 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7328 (const_int 0)))
7329 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7330 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7331 "@
7332 rldcl. %3,%1,%2,32
7333 rldicl. %3,%1,%H2,32
7334 #
7335 #"
7336 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7337 (set_attr "length" "4,4,8,8")])
7339 (define_split
7340 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7341 (compare:CC (zero_extend:DI
7342 (subreg:SI
7343 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7344 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7345 (const_int 0)))
7346 (clobber (match_scratch:DI 3 ""))]
7347 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7348 [(set (match_dup 3)
7349 (zero_extend:DI (subreg:SI
7350 (rotate:DI (match_dup 1)
7351 (match_dup 2)) 0)))
7352 (set (match_dup 0)
7353 (compare:CC (match_dup 3)
7354 (const_int 0)))]
7355 "")
7357 (define_split
7358 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7359 (compare:CC (zero_extend:DI
7360 (subreg:SI
7361 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7362 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7363 (const_int 0)))
7364 (clobber (match_scratch:DI 3 ""))]
7365 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7366 [(set (match_dup 3)
7367 (zero_extend:DI (subreg:SI
7368 (rotate:DI (match_dup 1)
7369 (match_dup 2)) 4)))
7370 (set (match_dup 0)
7371 (compare:CC (match_dup 3)
7372 (const_int 0)))]
7373 "")
7375 (define_insn "*rotldi3_internal15le"
7376 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7377 (compare:CC (zero_extend:DI
7378 (subreg:SI
7379 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7380 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7381 (const_int 0)))
7382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7383 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7384 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7385 "@
7386 rldcl. %0,%1,%2,32
7387 rldicl. %0,%1,%H2,32
7388 #
7389 #"
7390 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7391 (set_attr "length" "4,4,8,8")])
7393 (define_insn "*rotldi3_internal15be"
7394 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7395 (compare:CC (zero_extend:DI
7396 (subreg:SI
7397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7398 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7399 (const_int 0)))
7400 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7401 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7402 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7403 "@
7404 rldcl. %0,%1,%2,32
7405 rldicl. %0,%1,%H2,32
7406 #
7407 #"
7408 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7409 (set_attr "length" "4,4,8,8")])
7411 (define_split
7412 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7413 (compare:CC (zero_extend:DI
7414 (subreg:SI
7415 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7416 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7417 (const_int 0)))
7418 (set (match_operand:DI 0 "gpc_reg_operand" "")
7419 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7420 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7421 [(set (match_dup 0)
7422 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7423 (set (match_dup 3)
7424 (compare:CC (match_dup 0)
7425 (const_int 0)))]
7426 "")
7428 (define_split
7429 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7430 (compare:CC (zero_extend:DI
7431 (subreg:SI
7432 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7433 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7434 (const_int 0)))
7435 (set (match_operand:DI 0 "gpc_reg_operand" "")
7436 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7437 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7438 [(set (match_dup 0)
7439 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7440 (set (match_dup 3)
7441 (compare:CC (match_dup 0)
7442 (const_int 0)))]
7443 "")
7445 (define_expand "ashldi3"
7446 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7447 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7448 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7449 "TARGET_POWERPC64"
7450 "")
7452 (define_insn "*ashldi3_internal1"
7453 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7454 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7455 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7456 "TARGET_POWERPC64"
7457 "@
7458 sld %0,%1,%2
7459 sldi %0,%1,%H2"
7460 [(set_attr "type" "var_shift_rotate,shift")])
7462 (define_insn "*ashldi3_internal2"
7463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7464 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7465 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7466 (const_int 0)))
7467 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7468 "TARGET_64BIT"
7469 "@
7470 sld. %3,%1,%2
7471 sldi. %3,%1,%H2
7472 #
7473 #"
7474 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7475 (set_attr "length" "4,4,8,8")])
7477 (define_split
7478 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7479 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7480 (match_operand:SI 2 "reg_or_cint_operand" ""))
7481 (const_int 0)))
7482 (clobber (match_scratch:DI 3 ""))]
7483 "TARGET_POWERPC64 && reload_completed"
7484 [(set (match_dup 3)
7485 (ashift:DI (match_dup 1) (match_dup 2)))
7486 (set (match_dup 0)
7487 (compare:CC (match_dup 3)
7488 (const_int 0)))]
7489 "")
7491 (define_insn "*ashldi3_internal3"
7492 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7493 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7494 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7495 (const_int 0)))
7496 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7497 (ashift:DI (match_dup 1) (match_dup 2)))]
7498 "TARGET_64BIT"
7499 "@
7500 sld. %0,%1,%2
7501 sldi. %0,%1,%H2
7502 #
7503 #"
7504 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7505 (set_attr "length" "4,4,8,8")])
7507 (define_split
7508 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7509 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7510 (match_operand:SI 2 "reg_or_cint_operand" ""))
7511 (const_int 0)))
7512 (set (match_operand:DI 0 "gpc_reg_operand" "")
7513 (ashift:DI (match_dup 1) (match_dup 2)))]
7514 "TARGET_POWERPC64 && reload_completed"
7515 [(set (match_dup 0)
7516 (ashift:DI (match_dup 1) (match_dup 2)))
7517 (set (match_dup 3)
7518 (compare:CC (match_dup 0)
7519 (const_int 0)))]
7520 "")
7522 (define_insn "*ashldi3_internal4"
7523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7524 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7525 (match_operand:SI 2 "const_int_operand" "i"))
7526 (match_operand:DI 3 "const_int_operand" "n")))]
7527 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7528 "rldic %0,%1,%H2,%W3")
7530 (define_insn "ashldi3_internal5"
7531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7532 (compare:CC
7533 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7534 (match_operand:SI 2 "const_int_operand" "i,i"))
7535 (match_operand:DI 3 "const_int_operand" "n,n"))
7536 (const_int 0)))
7537 (clobber (match_scratch:DI 4 "=r,r"))]
7538 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7539 "@
7540 rldic. %4,%1,%H2,%W3
7541 #"
7542 [(set_attr "type" "compare")
7543 (set_attr "length" "4,8")])
7545 (define_split
7546 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7547 (compare:CC
7548 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7549 (match_operand:SI 2 "const_int_operand" ""))
7550 (match_operand:DI 3 "const_int_operand" ""))
7551 (const_int 0)))
7552 (clobber (match_scratch:DI 4 ""))]
7553 "TARGET_POWERPC64 && reload_completed
7554 && includes_rldic_lshift_p (operands[2], operands[3])"
7555 [(set (match_dup 4)
7556 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7557 (match_dup 3)))
7558 (set (match_dup 0)
7559 (compare:CC (match_dup 4)
7560 (const_int 0)))]
7561 "")
7563 (define_insn "*ashldi3_internal6"
7564 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7565 (compare:CC
7566 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7567 (match_operand:SI 2 "const_int_operand" "i,i"))
7568 (match_operand:DI 3 "const_int_operand" "n,n"))
7569 (const_int 0)))
7570 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7571 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7572 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7573 "@
7574 rldic. %0,%1,%H2,%W3
7575 #"
7576 [(set_attr "type" "compare")
7577 (set_attr "length" "4,8")])
7579 (define_split
7580 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7581 (compare:CC
7582 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7583 (match_operand:SI 2 "const_int_operand" ""))
7584 (match_operand:DI 3 "const_int_operand" ""))
7585 (const_int 0)))
7586 (set (match_operand:DI 0 "gpc_reg_operand" "")
7587 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7588 "TARGET_POWERPC64 && reload_completed
7589 && includes_rldic_lshift_p (operands[2], operands[3])"
7590 [(set (match_dup 0)
7591 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7592 (match_dup 3)))
7593 (set (match_dup 4)
7594 (compare:CC (match_dup 0)
7595 (const_int 0)))]
7596 "")
7598 (define_insn "*ashldi3_internal7"
7599 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7600 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7601 (match_operand:SI 2 "const_int_operand" "i"))
7602 (match_operand:DI 3 "mask64_operand" "n")))]
7603 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7604 "rldicr %0,%1,%H2,%S3")
7606 (define_insn "ashldi3_internal8"
7607 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7608 (compare:CC
7609 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7610 (match_operand:SI 2 "const_int_operand" "i,i"))
7611 (match_operand:DI 3 "mask64_operand" "n,n"))
7612 (const_int 0)))
7613 (clobber (match_scratch:DI 4 "=r,r"))]
7614 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7615 "@
7616 rldicr. %4,%1,%H2,%S3
7617 #"
7618 [(set_attr "type" "compare")
7619 (set_attr "length" "4,8")])
7621 (define_split
7622 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7623 (compare:CC
7624 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7625 (match_operand:SI 2 "const_int_operand" ""))
7626 (match_operand:DI 3 "mask64_operand" ""))
7627 (const_int 0)))
7628 (clobber (match_scratch:DI 4 ""))]
7629 "TARGET_POWERPC64 && reload_completed
7630 && includes_rldicr_lshift_p (operands[2], operands[3])"
7631 [(set (match_dup 4)
7632 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7633 (match_dup 3)))
7634 (set (match_dup 0)
7635 (compare:CC (match_dup 4)
7636 (const_int 0)))]
7637 "")
7639 (define_insn "*ashldi3_internal9"
7640 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7641 (compare:CC
7642 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7643 (match_operand:SI 2 "const_int_operand" "i,i"))
7644 (match_operand:DI 3 "mask64_operand" "n,n"))
7645 (const_int 0)))
7646 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7647 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7648 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7649 "@
7650 rldicr. %0,%1,%H2,%S3
7651 #"
7652 [(set_attr "type" "compare")
7653 (set_attr "length" "4,8")])
7655 (define_split
7656 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7657 (compare:CC
7658 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7659 (match_operand:SI 2 "const_int_operand" ""))
7660 (match_operand:DI 3 "mask64_operand" ""))
7661 (const_int 0)))
7662 (set (match_operand:DI 0 "gpc_reg_operand" "")
7663 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7664 "TARGET_POWERPC64 && reload_completed
7665 && includes_rldicr_lshift_p (operands[2], operands[3])"
7666 [(set (match_dup 0)
7667 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7668 (match_dup 3)))
7669 (set (match_dup 4)
7670 (compare:CC (match_dup 0)
7671 (const_int 0)))]
7672 "")
7674 (define_expand "lshrdi3"
7675 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7676 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7677 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7678 "TARGET_POWERPC64"
7679 "")
7681 (define_insn "*lshrdi3_internal1"
7682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7683 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7684 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7685 "TARGET_POWERPC64"
7686 "@
7687 srd %0,%1,%2
7688 srdi %0,%1,%H2"
7689 [(set_attr "type" "var_shift_rotate,shift")])
7691 (define_insn "*lshrdi3_internal2"
7692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7693 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7694 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7695 (const_int 0)))
7696 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7697 "TARGET_64BIT "
7698 "@
7699 srd. %3,%1,%2
7700 srdi. %3,%1,%H2
7701 #
7702 #"
7703 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7704 (set_attr "length" "4,4,8,8")])
7706 (define_split
7707 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7708 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7709 (match_operand:SI 2 "reg_or_cint_operand" ""))
7710 (const_int 0)))
7711 (clobber (match_scratch:DI 3 ""))]
7712 "TARGET_POWERPC64 && reload_completed"
7713 [(set (match_dup 3)
7714 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7715 (set (match_dup 0)
7716 (compare:CC (match_dup 3)
7717 (const_int 0)))]
7718 "")
7720 (define_insn "*lshrdi3_internal3"
7721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7722 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7723 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7724 (const_int 0)))
7725 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7726 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7727 "TARGET_64BIT"
7728 "@
7729 srd. %0,%1,%2
7730 srdi. %0,%1,%H2
7731 #
7732 #"
7733 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7734 (set_attr "length" "4,4,8,8")])
7736 (define_split
7737 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7738 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7739 (match_operand:SI 2 "reg_or_cint_operand" ""))
7740 (const_int 0)))
7741 (set (match_operand:DI 0 "gpc_reg_operand" "")
7742 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7743 "TARGET_POWERPC64 && reload_completed"
7744 [(set (match_dup 0)
7745 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7746 (set (match_dup 3)
7747 (compare:CC (match_dup 0)
7748 (const_int 0)))]
7749 "")
7751 (define_expand "ashrdi3"
7752 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7753 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7754 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7755 ""
7756 "
7757 {
7758 if (TARGET_POWERPC64)
7759 ;
7760 else if (GET_CODE (operands[2]) == CONST_INT)
7761 {
7762 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7763 DONE;
7764 }
7765 else
7766 FAIL;
7767 }")
7769 (define_insn "*ashrdi3_internal1"
7770 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7771 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7772 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7773 "TARGET_POWERPC64"
7774 "@
7775 srad %0,%1,%2
7776 sradi %0,%1,%H2"
7777 [(set_attr "type" "var_shift_rotate,shift")])
7779 (define_insn "*ashrdi3_internal2"
7780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7781 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7782 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7783 (const_int 0)))
7784 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7785 "TARGET_64BIT"
7786 "@
7787 srad. %3,%1,%2
7788 sradi. %3,%1,%H2
7789 #
7790 #"
7791 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7792 (set_attr "length" "4,4,8,8")])
7794 (define_split
7795 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7796 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7797 (match_operand:SI 2 "reg_or_cint_operand" ""))
7798 (const_int 0)))
7799 (clobber (match_scratch:DI 3 ""))]
7800 "TARGET_POWERPC64 && reload_completed"
7801 [(set (match_dup 3)
7802 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7803 (set (match_dup 0)
7804 (compare:CC (match_dup 3)
7805 (const_int 0)))]
7806 "")
7808 (define_insn "*ashrdi3_internal3"
7809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7810 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7811 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7812 (const_int 0)))
7813 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7814 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7815 "TARGET_64BIT"
7816 "@
7817 srad. %0,%1,%2
7818 sradi. %0,%1,%H2
7819 #
7820 #"
7821 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7822 (set_attr "length" "4,4,8,8")])
7824 (define_split
7825 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7826 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7827 (match_operand:SI 2 "reg_or_cint_operand" ""))
7828 (const_int 0)))
7829 (set (match_operand:DI 0 "gpc_reg_operand" "")
7830 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7831 "TARGET_POWERPC64 && reload_completed"
7832 [(set (match_dup 0)
7833 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7834 (set (match_dup 3)
7835 (compare:CC (match_dup 0)
7836 (const_int 0)))]
7837 "")
7839 (define_expand "anddi3"
7840 [(parallel
7841 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7842 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7843 (match_operand:DI 2 "and64_2_operand" "")))
7844 (clobber (match_scratch:CC 3 ""))])]
7845 "TARGET_POWERPC64"
7846 "")
7848 (define_insn "anddi3_mc"
7849 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7850 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7851 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7852 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7853 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7854 "@
7855 and %0,%1,%2
7856 rldic%B2 %0,%1,0,%S2
7857 rlwinm %0,%1,0,%m2,%M2
7858 andi. %0,%1,%b2
7859 andis. %0,%1,%u2
7860 #"
7861 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7862 (set_attr "length" "4,4,4,4,4,8")])
7864 (define_insn "anddi3_nomc"
7865 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7866 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7867 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7868 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7869 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7870 "@
7871 and %0,%1,%2
7872 rldic%B2 %0,%1,0,%S2
7873 rlwinm %0,%1,0,%m2,%M2
7874 #"
7875 [(set_attr "length" "4,4,4,8")])
7877 (define_split
7878 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7879 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7880 (match_operand:DI 2 "mask64_2_operand" "")))
7881 (clobber (match_scratch:CC 3 ""))]
7882 "TARGET_POWERPC64
7883 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7884 && !mask_operand (operands[2], DImode)
7885 && !mask64_operand (operands[2], DImode)"
7886 [(set (match_dup 0)
7887 (and:DI (rotate:DI (match_dup 1)
7888 (match_dup 4))
7889 (match_dup 5)))
7890 (set (match_dup 0)
7891 (and:DI (rotate:DI (match_dup 0)
7892 (match_dup 6))
7893 (match_dup 7)))]
7894 {
7895 build_mask64_2_operands (operands[2], &operands[4]);
7896 })
7898 (define_insn "*anddi3_internal2_mc"
7899 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7900 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7901 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7902 (const_int 0)))
7903 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7904 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7905 "TARGET_64BIT && rs6000_gen_cell_microcode"
7906 "@
7907 and. %3,%1,%2
7908 rldic%B2. %3,%1,0,%S2
7909 rlwinm. %3,%1,0,%m2,%M2
7910 andi. %3,%1,%b2
7911 andis. %3,%1,%u2
7912 #
7913 #
7914 #
7915 #
7916 #
7917 #
7918 #"
7919 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7920 fast_compare,compare,compare,compare,compare,compare,\
7921 compare,compare")
7922 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7924 (define_split
7925 [(set (match_operand:CC 0 "cc_reg_operand" "")
7926 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7927 (match_operand:DI 2 "mask64_2_operand" ""))
7928 (const_int 0)))
7929 (clobber (match_scratch:DI 3 ""))
7930 (clobber (match_scratch:CC 4 ""))]
7931 "TARGET_64BIT && reload_completed
7932 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7933 && !mask_operand (operands[2], DImode)
7934 && !mask64_operand (operands[2], DImode)"
7935 [(set (match_dup 3)
7936 (and:DI (rotate:DI (match_dup 1)
7937 (match_dup 5))
7938 (match_dup 6)))
7939 (parallel [(set (match_dup 0)
7940 (compare:CC (and:DI (rotate:DI (match_dup 3)
7941 (match_dup 7))
7942 (match_dup 8))
7943 (const_int 0)))
7944 (clobber (match_dup 3))])]
7945 "
7946 {
7947 build_mask64_2_operands (operands[2], &operands[5]);
7948 }")
7950 (define_insn "*anddi3_internal3_mc"
7951 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7952 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7953 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7954 (const_int 0)))
7955 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7956 (and:DI (match_dup 1) (match_dup 2)))
7957 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7958 "TARGET_64BIT && rs6000_gen_cell_microcode"
7959 "@
7960 and. %0,%1,%2
7961 rldic%B2. %0,%1,0,%S2
7962 rlwinm. %0,%1,0,%m2,%M2
7963 andi. %0,%1,%b2
7964 andis. %0,%1,%u2
7965 #
7966 #
7967 #
7968 #
7969 #
7970 #
7971 #"
7972 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7973 fast_compare,compare,compare,compare,compare,compare,\
7974 compare,compare")
7975 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7977 (define_split
7978 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7979 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7980 (match_operand:DI 2 "and64_2_operand" ""))
7981 (const_int 0)))
7982 (set (match_operand:DI 0 "gpc_reg_operand" "")
7983 (and:DI (match_dup 1) (match_dup 2)))
7984 (clobber (match_scratch:CC 4 ""))]
7985 "TARGET_64BIT && reload_completed"
7986 [(parallel [(set (match_dup 0)
7987 (and:DI (match_dup 1) (match_dup 2)))
7988 (clobber (match_dup 4))])
7989 (set (match_dup 3)
7990 (compare:CC (match_dup 0)
7991 (const_int 0)))]
7992 "")
7994 (define_split
7995 [(set (match_operand:CC 3 "cc_reg_operand" "")
7996 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7997 (match_operand:DI 2 "mask64_2_operand" ""))
7998 (const_int 0)))
7999 (set (match_operand:DI 0 "gpc_reg_operand" "")
8000 (and:DI (match_dup 1) (match_dup 2)))
8001 (clobber (match_scratch:CC 4 ""))]
8002 "TARGET_64BIT && reload_completed
8003 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8004 && !mask_operand (operands[2], DImode)
8005 && !mask64_operand (operands[2], DImode)"
8006 [(set (match_dup 0)
8007 (and:DI (rotate:DI (match_dup 1)
8008 (match_dup 5))
8009 (match_dup 6)))
8010 (parallel [(set (match_dup 3)
8011 (compare:CC (and:DI (rotate:DI (match_dup 0)
8012 (match_dup 7))
8013 (match_dup 8))
8014 (const_int 0)))
8015 (set (match_dup 0)
8016 (and:DI (rotate:DI (match_dup 0)
8017 (match_dup 7))
8018 (match_dup 8)))])]
8019 "
8020 {
8021 build_mask64_2_operands (operands[2], &operands[5]);
8022 }")
8024 (define_expand "iordi3"
8025 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8026 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8027 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8028 "TARGET_POWERPC64"
8029 "
8030 {
8031 if (non_logical_cint_operand (operands[2], DImode))
8032 {
8033 HOST_WIDE_INT value;
8034 rtx tmp = ((!can_create_pseudo_p ()
8035 || rtx_equal_p (operands[0], operands[1]))
8036 ? operands[0] : gen_reg_rtx (DImode));
8038 value = INTVAL (operands[2]);
8039 emit_insn (gen_iordi3 (tmp, operands[1],
8040 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8042 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8043 DONE;
8044 }
8045 }")
8047 (define_expand "xordi3"
8048 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8049 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8050 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8051 "TARGET_POWERPC64"
8052 "
8053 {
8054 if (non_logical_cint_operand (operands[2], DImode))
8055 {
8056 HOST_WIDE_INT value;
8057 rtx tmp = ((!can_create_pseudo_p ()
8058 || rtx_equal_p (operands[0], operands[1]))
8059 ? operands[0] : gen_reg_rtx (DImode));
8061 value = INTVAL (operands[2]);
8062 emit_insn (gen_xordi3 (tmp, operands[1],
8063 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8065 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8066 DONE;
8067 }
8068 }")
8070 (define_insn "*booldi3_internal1"
8071 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8072 (match_operator:DI 3 "boolean_or_operator"
8073 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8074 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8075 "TARGET_POWERPC64"
8076 "@
8077 %q3 %0,%1,%2
8078 %q3i %0,%1,%b2
8079 %q3is %0,%1,%u2")
8081 (define_insn "*booldi3_internal2"
8082 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8083 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8084 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8085 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8086 (const_int 0)))
8087 (clobber (match_scratch:DI 3 "=r,r"))]
8088 "TARGET_64BIT"
8089 "@
8090 %q4. %3,%1,%2
8091 #"
8092 [(set_attr "type" "fast_compare,compare")
8093 (set_attr "length" "4,8")])
8095 (define_split
8096 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8097 (compare:CC (match_operator:DI 4 "boolean_operator"
8098 [(match_operand:DI 1 "gpc_reg_operand" "")
8099 (match_operand:DI 2 "gpc_reg_operand" "")])
8100 (const_int 0)))
8101 (clobber (match_scratch:DI 3 ""))]
8102 "TARGET_POWERPC64 && reload_completed"
8103 [(set (match_dup 3) (match_dup 4))
8104 (set (match_dup 0)
8105 (compare:CC (match_dup 3)
8106 (const_int 0)))]
8107 "")
8109 (define_insn "*booldi3_internal3"
8110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8111 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8112 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8113 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8114 (const_int 0)))
8115 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8116 (match_dup 4))]
8117 "TARGET_64BIT"
8118 "@
8119 %q4. %0,%1,%2
8120 #"
8121 [(set_attr "type" "fast_compare,compare")
8122 (set_attr "length" "4,8")])
8124 (define_split
8125 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8126 (compare:CC (match_operator:DI 4 "boolean_operator"
8127 [(match_operand:DI 1 "gpc_reg_operand" "")
8128 (match_operand:DI 2 "gpc_reg_operand" "")])
8129 (const_int 0)))
8130 (set (match_operand:DI 0 "gpc_reg_operand" "")
8131 (match_dup 4))]
8132 "TARGET_POWERPC64 && reload_completed"
8133 [(set (match_dup 0) (match_dup 4))
8134 (set (match_dup 3)
8135 (compare:CC (match_dup 0)
8136 (const_int 0)))]
8137 "")
8139 ;; Split a logical operation that we can't do in one insn into two insns,
8140 ;; each of which does one 16-bit part. This is used by combine.
8142 (define_split
8143 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8144 (match_operator:DI 3 "boolean_or_operator"
8145 [(match_operand:DI 1 "gpc_reg_operand" "")
8146 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8147 "TARGET_POWERPC64"
8148 [(set (match_dup 0) (match_dup 4))
8149 (set (match_dup 0) (match_dup 5))]
8150 "
8151 {
8152 rtx i3,i4;
8154 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8155 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8156 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8157 operands[1], i3);
8158 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8159 operands[0], i4);
8160 }")
8162 (define_insn "*boolcdi3_internal1"
8163 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8164 (match_operator:DI 3 "boolean_operator"
8165 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8166 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8167 "TARGET_POWERPC64"
8168 "%q3 %0,%2,%1")
8170 (define_insn "*boolcdi3_internal2"
8171 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8172 (compare:CC (match_operator:DI 4 "boolean_operator"
8173 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8174 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8175 (const_int 0)))
8176 (clobber (match_scratch:DI 3 "=r,r"))]
8177 "TARGET_64BIT"
8178 "@
8179 %q4. %3,%2,%1
8180 #"
8181 [(set_attr "type" "fast_compare,compare")
8182 (set_attr "length" "4,8")])
8184 (define_split
8185 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8186 (compare:CC (match_operator:DI 4 "boolean_operator"
8187 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8188 (match_operand:DI 2 "gpc_reg_operand" "")])
8189 (const_int 0)))
8190 (clobber (match_scratch:DI 3 ""))]
8191 "TARGET_POWERPC64 && reload_completed"
8192 [(set (match_dup 3) (match_dup 4))
8193 (set (match_dup 0)
8194 (compare:CC (match_dup 3)
8195 (const_int 0)))]
8196 "")
8198 (define_insn "*boolcdi3_internal3"
8199 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8200 (compare:CC (match_operator:DI 4 "boolean_operator"
8201 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8202 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8203 (const_int 0)))
8204 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8205 (match_dup 4))]
8206 "TARGET_64BIT"
8207 "@
8208 %q4. %0,%2,%1
8209 #"
8210 [(set_attr "type" "fast_compare,compare")
8211 (set_attr "length" "4,8")])
8213 (define_split
8214 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8215 (compare:CC (match_operator:DI 4 "boolean_operator"
8216 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8217 (match_operand:DI 2 "gpc_reg_operand" "")])
8218 (const_int 0)))
8219 (set (match_operand:DI 0 "gpc_reg_operand" "")
8220 (match_dup 4))]
8221 "TARGET_POWERPC64 && reload_completed"
8222 [(set (match_dup 0) (match_dup 4))
8223 (set (match_dup 3)
8224 (compare:CC (match_dup 0)
8225 (const_int 0)))]
8226 "")
8228 (define_insn "*boolccdi3_internal1"
8229 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8230 (match_operator:DI 3 "boolean_operator"
8231 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8232 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8233 "TARGET_POWERPC64"
8234 "%q3 %0,%1,%2")
8236 (define_insn "*boolccdi3_internal2"
8237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8238 (compare:CC (match_operator:DI 4 "boolean_operator"
8239 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8240 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8241 (const_int 0)))
8242 (clobber (match_scratch:DI 3 "=r,r"))]
8243 "TARGET_64BIT"
8244 "@
8245 %q4. %3,%1,%2
8246 #"
8247 [(set_attr "type" "fast_compare,compare")
8248 (set_attr "length" "4,8")])
8250 (define_split
8251 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8252 (compare:CC (match_operator:DI 4 "boolean_operator"
8253 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8254 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8255 (const_int 0)))
8256 (clobber (match_scratch:DI 3 ""))]
8257 "TARGET_POWERPC64 && reload_completed"
8258 [(set (match_dup 3) (match_dup 4))
8259 (set (match_dup 0)
8260 (compare:CC (match_dup 3)
8261 (const_int 0)))]
8262 "")
8264 (define_insn "*boolccdi3_internal3"
8265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8266 (compare:CC (match_operator:DI 4 "boolean_operator"
8267 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8268 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8269 (const_int 0)))
8270 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8271 (match_dup 4))]
8272 "TARGET_64BIT"
8273 "@
8274 %q4. %0,%1,%2
8275 #"
8276 [(set_attr "type" "fast_compare,compare")
8277 (set_attr "length" "4,8")])
8279 (define_split
8280 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8281 (compare:CC (match_operator:DI 4 "boolean_operator"
8282 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8283 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8284 (const_int 0)))
8285 (set (match_operand:DI 0 "gpc_reg_operand" "")
8286 (match_dup 4))]
8287 "TARGET_POWERPC64 && reload_completed"
8288 [(set (match_dup 0) (match_dup 4))
8289 (set (match_dup 3)
8290 (compare:CC (match_dup 0)
8291 (const_int 0)))]
8292 "")
8293 \f
8294 ;; Now define ways of moving data around.
8296 ;; Set up a register with a value from the GOT table
8298 (define_expand "movsi_got"
8299 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8300 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8301 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8302 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8303 "
8304 {
8305 if (GET_CODE (operands[1]) == CONST)
8306 {
8307 rtx offset = const0_rtx;
8308 HOST_WIDE_INT value;
8310 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8311 value = INTVAL (offset);
8312 if (value != 0)
8313 {
8314 rtx tmp = (!can_create_pseudo_p ()
8315 ? operands[0]
8316 : gen_reg_rtx (Pmode));
8317 emit_insn (gen_movsi_got (tmp, operands[1]));
8318 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8319 DONE;
8320 }
8321 }
8323 operands[2] = rs6000_got_register (operands[1]);
8324 }")
8326 (define_insn "*movsi_got_internal"
8327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8328 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8329 (match_operand:SI 2 "gpc_reg_operand" "b")]
8330 UNSPEC_MOVSI_GOT))]
8331 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8332 "lwz %0,%a1@got(%2)"
8333 [(set_attr "type" "load")])
8335 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8336 ;; didn't get allocated to a hard register.
8337 (define_split
8338 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8339 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8340 (match_operand:SI 2 "memory_operand" "")]
8341 UNSPEC_MOVSI_GOT))]
8342 "DEFAULT_ABI == ABI_V4
8343 && flag_pic == 1
8344 && (reload_in_progress || reload_completed)"
8345 [(set (match_dup 0) (match_dup 2))
8346 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8347 UNSPEC_MOVSI_GOT))]
8348 "")
8350 ;; For SI, we special-case integers that can't be loaded in one insn. We
8351 ;; do the load 16-bits at a time. We could do this by loading from memory,
8352 ;; and this is even supposed to be faster, but it is simpler not to get
8353 ;; integers in the TOC.
8354 (define_insn "movsi_low"
8355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8356 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8357 (match_operand 2 "" ""))))]
8358 "TARGET_MACHO && ! TARGET_64BIT"
8359 "lwz %0,lo16(%2)(%1)"
8360 [(set_attr "type" "load")
8361 (set_attr "length" "4")])
8363 (define_insn "*movsi_internal1"
8364 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8365 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8366 "!TARGET_SINGLE_FPU &&
8367 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8368 "@
8369 mr %0,%1
8370 la %0,%a1
8371 lwz%U1%X1 %0,%1
8372 stw%U0%X0 %1,%0
8373 li %0,%1
8374 lis %0,%v1
8375 #
8376 mf%1 %0
8377 mt%0 %1
8378 mt%0 %1
8379 nop"
8380 [(set_attr_alternative "type"
8381 [(const_string "*")
8382 (const_string "*")
8383 (if_then_else
8384 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8385 (const_string "load_ux")
8386 (if_then_else
8387 (match_test "update_address_mem (operands[1], VOIDmode)")
8388 (const_string "load_u")
8389 (const_string "load")))
8390 (if_then_else
8391 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8392 (const_string "store_ux")
8393 (if_then_else
8394 (match_test "update_address_mem (operands[0], VOIDmode)")
8395 (const_string "store_u")
8396 (const_string "store")))
8397 (const_string "*")
8398 (const_string "*")
8399 (const_string "*")
8400 (const_string "mfjmpr")
8401 (const_string "mtjmpr")
8402 (const_string "*")
8403 (const_string "*")])
8405 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8407 (define_insn "*movsi_internal1_single"
8408 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8409 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8410 "TARGET_SINGLE_FPU &&
8411 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8412 "@
8413 mr %0,%1
8414 la %0,%a1
8415 lwz%U1%X1 %0,%1
8416 stw%U0%X0 %1,%0
8417 li %0,%1
8418 lis %0,%v1
8419 #
8420 mf%1 %0
8421 mt%0 %1
8422 mt%0 %1
8423 nop
8424 stfs%U0%X0 %1,%0
8425 lfs%U1%X1 %0,%1"
8426 [(set_attr_alternative "type"
8427 [(const_string "*")
8428 (const_string "*")
8429 (if_then_else
8430 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8431 (const_string "load_ux")
8432 (if_then_else
8433 (match_test "update_address_mem (operands[1], VOIDmode)")
8434 (const_string "load_u")
8435 (const_string "load")))
8436 (if_then_else
8437 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8438 (const_string "store_ux")
8439 (if_then_else
8440 (match_test "update_address_mem (operands[0], VOIDmode)")
8441 (const_string "store_u")
8442 (const_string "store")))
8443 (const_string "*")
8444 (const_string "*")
8445 (const_string "*")
8446 (const_string "mfjmpr")
8447 (const_string "mtjmpr")
8448 (const_string "*")
8449 (const_string "*")
8450 (if_then_else
8451 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8452 (const_string "fpstore_ux")
8453 (if_then_else
8454 (match_test "update_address_mem (operands[0], VOIDmode)")
8455 (const_string "fpstore_u")
8456 (const_string "fpstore")))
8457 (if_then_else
8458 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8459 (const_string "fpload_ux")
8460 (if_then_else
8461 (match_test "update_address_mem (operands[1], VOIDmode)")
8462 (const_string "fpload_u")
8463 (const_string "fpload")))])
8464 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8466 ;; Split a load of a large constant into the appropriate two-insn
8467 ;; sequence.
8469 (define_split
8470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8471 (match_operand:SI 1 "const_int_operand" ""))]
8472 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8473 && (INTVAL (operands[1]) & 0xffff) != 0"
8474 [(set (match_dup 0)
8475 (match_dup 2))
8476 (set (match_dup 0)
8477 (ior:SI (match_dup 0)
8478 (match_dup 3)))]
8479 "
8480 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8482 if (tem == operands[0])
8483 DONE;
8484 else
8485 FAIL;
8486 }")
8488 (define_insn "*mov<mode>_internal2"
8489 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8490 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8491 (const_int 0)))
8492 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8493 ""
8494 "@
8495 cmp<wd>i %2,%0,0
8496 mr. %0,%1
8497 #"
8498 [(set_attr "type" "cmp,compare,cmp")
8499 (set_attr "length" "4,4,8")])
8501 (define_split
8502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8503 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8504 (const_int 0)))
8505 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8506 "reload_completed"
8507 [(set (match_dup 0) (match_dup 1))
8508 (set (match_dup 2)
8509 (compare:CC (match_dup 0)
8510 (const_int 0)))]
8511 "")
8512 \f
8513 (define_insn "*movhi_internal"
8514 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8515 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8516 "gpc_reg_operand (operands[0], HImode)
8517 || gpc_reg_operand (operands[1], HImode)"
8518 "@
8519 mr %0,%1
8520 lhz%U1%X1 %0,%1
8521 sth%U0%X0 %1,%0
8522 li %0,%w1
8523 mf%1 %0
8524 mt%0 %1
8525 nop"
8526 [(set_attr_alternative "type"
8527 [(const_string "*")
8528 (if_then_else
8529 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8530 (const_string "load_ux")
8531 (if_then_else
8532 (match_test "update_address_mem (operands[1], VOIDmode)")
8533 (const_string "load_u")
8534 (const_string "load")))
8535 (if_then_else
8536 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8537 (const_string "store_ux")
8538 (if_then_else
8539 (match_test "update_address_mem (operands[0], VOIDmode)")
8540 (const_string "store_u")
8541 (const_string "store")))
8542 (const_string "*")
8543 (const_string "mfjmpr")
8544 (const_string "mtjmpr")
8545 (const_string "*")])])
8547 (define_expand "mov<mode>"
8548 [(set (match_operand:INT 0 "general_operand" "")
8549 (match_operand:INT 1 "any_operand" ""))]
8550 ""
8551 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8553 (define_insn "*movqi_internal"
8554 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8555 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8556 "gpc_reg_operand (operands[0], QImode)
8557 || gpc_reg_operand (operands[1], QImode)"
8558 "@
8559 mr %0,%1
8560 lbz%U1%X1 %0,%1
8561 stb%U0%X0 %1,%0
8562 li %0,%1
8563 mf%1 %0
8564 mt%0 %1
8565 nop"
8566 [(set_attr_alternative "type"
8567 [(const_string "*")
8568 (if_then_else
8569 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8570 (const_string "load_ux")
8571 (if_then_else
8572 (match_test "update_address_mem (operands[1], VOIDmode)")
8573 (const_string "load_u")
8574 (const_string "load")))
8575 (if_then_else
8576 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8577 (const_string "store_ux")
8578 (if_then_else
8579 (match_test "update_address_mem (operands[0], VOIDmode)")
8580 (const_string "store_u")
8581 (const_string "store")))
8582 (const_string "*")
8583 (const_string "mfjmpr")
8584 (const_string "mtjmpr")
8585 (const_string "*")])])
8586 \f
8587 ;; Here is how to move condition codes around. When we store CC data in
8588 ;; an integer register or memory, we store just the high-order 4 bits.
8589 ;; This lets us not shift in the most common case of CR0.
8590 (define_expand "movcc"
8591 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8592 (match_operand:CC 1 "nonimmediate_operand" ""))]
8593 ""
8594 "")
8596 (define_insn "*movcc_internal1"
8597 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
8598 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
8599 "register_operand (operands[0], CCmode)
8600 || register_operand (operands[1], CCmode)"
8601 "@
8602 mcrf %0,%1
8603 mtcrf 128,%1
8604 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
8605 crxor %0,%0,%0
8606 mfcr %0%Q1
8607 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
8608 mr %0,%1
8609 li %0,%1
8610 mf%1 %0
8611 mt%0 %1
8612 lwz%U1%X1 %0,%1
8613 stw%U0%X0 %1,%0"
8614 [(set (attr "type")
8615 (cond [(eq_attr "alternative" "0,3")
8616 (const_string "cr_logical")
8617 (eq_attr "alternative" "1,2")
8618 (const_string "mtcr")
8619 (eq_attr "alternative" "6,7")
8620 (const_string "integer")
8621 (eq_attr "alternative" "8")
8622 (const_string "mfjmpr")
8623 (eq_attr "alternative" "9")
8624 (const_string "mtjmpr")
8625 (eq_attr "alternative" "10")
8626 (if_then_else
8627 (match_test "update_indexed_address_mem (operands[1],
8628 VOIDmode)")
8629 (const_string "load_ux")
8630 (if_then_else
8631 (match_test "update_address_mem (operands[1], VOIDmode)")
8632 (const_string "load_u")
8633 (const_string "load")))
8634 (eq_attr "alternative" "11")
8635 (if_then_else
8636 (match_test "update_indexed_address_mem (operands[0],
8637 VOIDmode)")
8638 (const_string "store_ux")
8639 (if_then_else
8640 (match_test "update_address_mem (operands[0], VOIDmode)")
8641 (const_string "store_u")
8642 (const_string "store")))
8643 (match_test "TARGET_MFCRF")
8644 (const_string "mfcrf")
8645 ]
8646 (const_string "mfcr")))
8647 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8648 \f
8649 ;; For floating-point, we normally deal with the floating-point registers
8650 ;; unless -msoft-float is used. The sole exception is that parameter passing
8651 ;; can produce floating-point values in fixed-point registers. Unless the
8652 ;; value is a simple constant or already in memory, we deal with this by
8653 ;; allocating memory and copying the value explicitly via that memory location.
8655 ;; Move 32-bit binary/decimal floating point
8656 (define_expand "mov<mode>"
8657 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8658 (match_operand:FMOVE32 1 "any_operand" ""))]
8659 "<fmove_ok>"
8660 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8662 (define_split
8663 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8664 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8665 "reload_completed
8666 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8667 || (GET_CODE (operands[0]) == SUBREG
8668 && GET_CODE (SUBREG_REG (operands[0])) == REG
8669 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8670 [(set (match_dup 2) (match_dup 3))]
8671 "
8672 {
8673 long l;
8674 REAL_VALUE_TYPE rv;
8676 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8677 <real_value_to_target> (rv, l);
8679 if (! TARGET_POWERPC64)
8680 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
8681 else
8682 operands[2] = gen_lowpart (SImode, operands[0]);
8684 operands[3] = gen_int_mode (l, SImode);
8685 }")
8687 (define_insn "mov<mode>_hardfloat"
8688 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,*c*l,!r,*h,!r,!r")
8689 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,r,h,0,G,Fn"))]
8690 "(gpc_reg_operand (operands[0], <MODE>mode)
8691 || gpc_reg_operand (operands[1], <MODE>mode))
8692 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8693 "@
8694 mr %0,%1
8695 lwz%U1%X1 %0,%1
8696 stw%U0%X0 %1,%0
8697 fmr %0,%1
8698 xxlor %x0,%x1,%x1
8699 xxlxor %x0,%x0,%x0
8700 <f32_li>
8701 <f32_si>
8702 mt%0 %1
8703 mf%1 %0
8704 nop
8705 #
8706 #"
8707 [(set_attr_alternative "type"
8708 [(const_string "*")
8709 (if_then_else
8710 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8711 (const_string "load_ux")
8712 (if_then_else
8713 (match_test "update_address_mem (operands[1], VOIDmode)")
8714 (const_string "load_u")
8715 (const_string "load")))
8716 (if_then_else
8717 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8718 (const_string "store_ux")
8719 (if_then_else
8720 (match_test "update_address_mem (operands[0], VOIDmode)")
8721 (const_string "store_u")
8722 (const_string "store")))
8723 (const_string "fp")
8724 (const_string "vecsimple")
8725 (const_string "vecsimple")
8726 (if_then_else
8727 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8728 (const_string "fpload_ux")
8729 (if_then_else
8730 (match_test "update_address_mem (operands[1], VOIDmode)")
8731 (const_string "fpload_u")
8732 (const_string "fpload")))
8733 (if_then_else
8734 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8735 (const_string "fpstore_ux")
8736 (if_then_else
8737 (match_test "update_address_mem (operands[0], VOIDmode)")
8738 (const_string "fpstore_u")
8739 (const_string "fpstore")))
8740 (const_string "mtjmpr")
8741 (const_string "mfjmpr")
8742 (const_string "*")
8743 (const_string "*")
8744 (const_string "*")])
8745 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8")])
8747 (define_insn "*mov<mode>_softfloat"
8748 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
8749 (match_operand:FMOVE32 1 "input_operand" "r, r,h,m,r,I,L,G,Fn,0"))]
8750 "(gpc_reg_operand (operands[0], <MODE>mode)
8751 || gpc_reg_operand (operands[1], <MODE>mode))
8752 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8753 "@
8754 mr %0,%1
8755 mt%0 %1
8756 mf%1 %0
8757 lwz%U1%X1 %0,%1
8758 stw%U0%X0 %1,%0
8759 li %0,%1
8760 lis %0,%v1
8761 #
8762 #
8763 nop"
8764 [(set_attr_alternative "type"
8765 [(const_string "*")
8766 (const_string "mtjmpr")
8767 (const_string "mfjmpr")
8768 (if_then_else
8769 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8770 (const_string "load_ux")
8771 (if_then_else
8772 (match_test "update_address_mem (operands[1], VOIDmode)")
8773 (const_string "load_u")
8774 (const_string "load")))
8775 (if_then_else
8776 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8777 (const_string "store_ux")
8778 (if_then_else
8779 (match_test "update_address_mem (operands[0], VOIDmode)")
8780 (const_string "store_u")
8781 (const_string "store")))
8782 (const_string "*")
8783 (const_string "*")
8784 (const_string "*")
8785 (const_string "*")
8786 (const_string "*")])
8787 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
8789 \f
8790 ;; Move 64-bit binary/decimal floating point
8791 (define_expand "mov<mode>"
8792 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
8793 (match_operand:FMOVE64 1 "any_operand" ""))]
8794 ""
8795 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8797 (define_split
8798 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8799 (match_operand:FMOVE64 1 "const_int_operand" ""))]
8800 "! TARGET_POWERPC64 && reload_completed
8801 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8802 || (GET_CODE (operands[0]) == SUBREG
8803 && GET_CODE (SUBREG_REG (operands[0])) == REG
8804 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8805 [(set (match_dup 2) (match_dup 4))
8806 (set (match_dup 3) (match_dup 1))]
8807 "
8808 {
8809 int endian = (WORDS_BIG_ENDIAN == 0);
8810 HOST_WIDE_INT value = INTVAL (operands[1]);
8812 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8813 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8814 operands[4] = GEN_INT (value >> 32);
8815 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8816 }")
8818 (define_split
8819 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8820 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8821 "! TARGET_POWERPC64 && reload_completed
8822 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8823 || (GET_CODE (operands[0]) == SUBREG
8824 && GET_CODE (SUBREG_REG (operands[0])) == REG
8825 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8826 [(set (match_dup 2) (match_dup 4))
8827 (set (match_dup 3) (match_dup 5))]
8828 "
8829 {
8830 int endian = (WORDS_BIG_ENDIAN == 0);
8831 long l[2];
8832 REAL_VALUE_TYPE rv;
8834 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8835 <real_value_to_target> (rv, l);
8837 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8838 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8839 operands[4] = gen_int_mode (l[endian], SImode);
8840 operands[5] = gen_int_mode (l[1 - endian], SImode);
8841 }")
8843 (define_split
8844 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8845 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8846 "TARGET_POWERPC64 && reload_completed
8847 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8848 || (GET_CODE (operands[0]) == SUBREG
8849 && GET_CODE (SUBREG_REG (operands[0])) == REG
8850 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8851 [(set (match_dup 2) (match_dup 3))]
8852 "
8853 {
8854 int endian = (WORDS_BIG_ENDIAN == 0);
8855 long l[2];
8856 REAL_VALUE_TYPE rv;
8857 HOST_WIDE_INT val;
8859 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8860 <real_value_to_target> (rv, l);
8862 operands[2] = gen_lowpart (DImode, operands[0]);
8863 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8864 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8865 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8867 operands[3] = gen_int_mode (val, DImode);
8868 }")
8870 ;; Don't have reload use general registers to load a constant. It is
8871 ;; less efficient than loading the constant into an FP register, since
8872 ;; it will probably be used there.
8874 ;; The move constraints are ordered to prefer floating point registers before
8875 ;; general purpose registers to avoid doing a store and a load to get the value
8876 ;; into a floating point register when it is needed for a floating point
8877 ;; operation. Prefer traditional floating point registers over VSX registers,
8878 ;; since the D-form version of the memory instructions does not need a GPR for
8879 ;; reloading.
8881 (define_insn "*mov<mode>_hardfloat32"
8882 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
8883 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
8884 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8885 && (gpc_reg_operand (operands[0], <MODE>mode)
8886 || gpc_reg_operand (operands[1], <MODE>mode))"
8887 "@
8888 stfd%U0%X0 %1,%0
8889 lfd%U1%X1 %0,%1
8890 fmr %0,%1
8891 lxsd%U1x %x0,%y1
8892 lxsd%U1x %x0,%y1
8893 stxsd%U0x %x1,%y0
8894 stxsd%U0x %x1,%y0
8895 xxlor %x0,%x1,%x1
8896 xxlor %x0,%x1,%x1
8897 xxlxor %x0,%x0,%x0
8898 #
8899 #
8900 #
8901 #
8902 #
8903 #"
8904 [(set_attr_alternative "type"
8905 [(if_then_else
8906 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8907 (const_string "fpstore_ux")
8908 (if_then_else
8909 (match_test "update_address_mem (operands[0], VOIDmode)")
8910 (const_string "fpstore_u")
8911 (const_string "fpstore")))
8912 (if_then_else
8913 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8914 (const_string "fpload_ux")
8915 (if_then_else
8916 (match_test "update_address_mem (operands[1], VOIDmode)")
8917 (const_string "fpload_u")
8918 (const_string "fpload")))
8919 (const_string "fp")
8920 (if_then_else
8921 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8922 (const_string "fpload_ux")
8923 (const_string "fpload"))
8924 (if_then_else
8925 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8926 (const_string "fpload_ux")
8927 (const_string "fpload"))
8928 (if_then_else
8929 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8930 (const_string "fpstore_ux")
8931 (const_string "fpstore"))
8932 (if_then_else
8933 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8934 (const_string "fpstore_ux")
8935 (const_string "fpstore"))
8936 (const_string "vecsimple")
8937 (const_string "vecsimple")
8938 (const_string "vecsimple")
8939 (const_string "store")
8940 (const_string "load")
8941 (const_string "two")
8942 (const_string "fp")
8943 (const_string "fp")
8944 (const_string "*")])
8945 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
8947 (define_insn "*mov<mode>_softfloat32"
8948 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8949 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8950 "! TARGET_POWERPC64
8951 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8952 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8953 && (gpc_reg_operand (operands[0], <MODE>mode)
8954 || gpc_reg_operand (operands[1], <MODE>mode))"
8955 "#"
8956 [(set_attr "type" "store,load,two,*,*,*")
8957 (set_attr "length" "8,8,8,8,12,16")])
8959 ; ld/std require word-aligned displacements -> 'Y' constraint.
8960 ; List Y->r and r->Y before r->r for reload.
8961 (define_insn "*mov<mode>_hardfloat64"
8962 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg")
8963 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,r,h,0,G,H,F,wg,r"))]
8964 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8965 && (gpc_reg_operand (operands[0], <MODE>mode)
8966 || gpc_reg_operand (operands[1], <MODE>mode))"
8967 "@
8968 stfd%U0%X0 %1,%0
8969 lfd%U1%X1 %0,%1
8970 fmr %0,%1
8971 lxsd%U1x %x0,%y1
8972 lxsd%U1x %x0,%y1
8973 stxsd%U0x %x1,%y0
8974 stxsd%U0x %x1,%y0
8975 xxlor %x0,%x1,%x1
8976 xxlor %x0,%x1,%x1
8977 xxlxor %x0,%x0,%x0
8978 std%U0%X0 %1,%0
8979 ld%U1%X1 %0,%1
8980 mr %0,%1
8981 mt%0 %1
8982 mf%1 %0
8983 nop
8984 #
8985 #
8986 #
8987 mftgpr %0,%1
8988 mffgpr %0,%1"
8989 [(set_attr_alternative "type"
8990 [(if_then_else
8991 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8992 (const_string "fpstore_ux")
8993 (if_then_else
8994 (match_test "update_address_mem (operands[0], VOIDmode)")
8995 (const_string "fpstore_u")
8996 (const_string "fpstore")))
8997 (if_then_else
8998 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8999 (const_string "fpload_ux")
9000 (if_then_else
9001 (match_test "update_address_mem (operands[1], VOIDmode)")
9002 (const_string "fpload_u")
9003 (const_string "fpload")))
9004 (const_string "fp")
9005 (if_then_else
9006 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9007 (const_string "fpload_ux")
9008 (const_string "fpload"))
9009 (if_then_else
9010 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9011 (const_string "fpload_ux")
9012 (const_string "fpload"))
9013 (if_then_else
9014 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9015 (const_string "fpstore_ux")
9016 (const_string "fpstore"))
9017 (if_then_else
9018 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9019 (const_string "fpstore_ux")
9020 (const_string "fpstore"))
9021 (const_string "vecsimple")
9022 (const_string "vecsimple")
9023 (const_string "vecsimple")
9024 (if_then_else
9025 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9026 (const_string "store_ux")
9027 (if_then_else
9028 (match_test "update_address_mem (operands[0], VOIDmode)")
9029 (const_string "store_u")
9030 (const_string "store")))
9031 (if_then_else
9032 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9033 (const_string "load_ux")
9034 (if_then_else
9035 (match_test "update_address_mem (operands[1], VOIDmode)")
9036 (const_string "load_u")
9037 (const_string "load")))
9038 (const_string "*")
9039 (const_string "mtjmpr")
9040 (const_string "mfjmpr")
9041 (const_string "*")
9042 (const_string "*")
9043 (const_string "*")
9044 (const_string "*")
9045 (const_string "mftgpr")
9046 (const_string "mffgpr")])
9047 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9049 (define_insn "*mov<mode>_softfloat64"
9050 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9051 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9052 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9053 && (gpc_reg_operand (operands[0], <MODE>mode)
9054 || gpc_reg_operand (operands[1], <MODE>mode))"
9055 "@
9056 std%U0%X0 %1,%0
9057 ld%U1%X1 %0,%1
9058 mr %0,%1
9059 mt%0 %1
9060 mf%1 %0
9061 #
9062 #
9063 #
9064 nop"
9065 [(set_attr_alternative "type"
9066 [(if_then_else
9067 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9068 (const_string "store_ux")
9069 (if_then_else
9070 (match_test "update_address_mem (operands[0], VOIDmode)")
9071 (const_string "store_u")
9072 (const_string "store")))
9073 (if_then_else
9074 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9075 (const_string "load_ux")
9076 (if_then_else
9077 (match_test "update_address_mem (operands[1], VOIDmode)")
9078 (const_string "load_u")
9079 (const_string "load")))
9080 (const_string "*")
9081 (const_string "mtjmpr")
9082 (const_string "mfjmpr")
9083 (const_string "*")
9084 (const_string "*")
9085 (const_string "*")
9086 (const_string "*")])
9087 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9088 \f
9089 (define_expand "mov<mode>"
9090 [(set (match_operand:FMOVE128 0 "general_operand" "")
9091 (match_operand:FMOVE128 1 "any_operand" ""))]
9092 ""
9093 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9095 ;; It's important to list Y->r and r->Y before r->r because otherwise
9096 ;; reload, given m->r, will try to pick r->r and reload it, which
9097 ;; doesn't make progress.
9098 (define_insn_and_split "*mov<mode>_internal"
9099 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9100 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9101 "TARGET_HARD_FLOAT && TARGET_FPRS
9102 && (gpc_reg_operand (operands[0], <MODE>mode)
9103 || gpc_reg_operand (operands[1], <MODE>mode))"
9104 "#"
9105 "&& reload_completed"
9106 [(pc)]
9107 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9108 [(set_attr "length" "8,8,8,20,20,16")])
9110 (define_insn_and_split "*mov<mode>_softfloat"
9111 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9112 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9113 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9114 && (gpc_reg_operand (operands[0], <MODE>mode)
9115 || gpc_reg_operand (operands[1], <MODE>mode))"
9116 "#"
9117 "&& reload_completed"
9118 [(pc)]
9119 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9120 [(set_attr "length" "20,20,16")])
9122 (define_expand "extenddftf2"
9123 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9124 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9125 "!TARGET_IEEEQUAD
9126 && TARGET_HARD_FLOAT
9127 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9128 && TARGET_LONG_DOUBLE_128"
9129 {
9130 if (TARGET_E500_DOUBLE)
9131 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9132 else
9133 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9134 DONE;
9135 })
9137 (define_expand "extenddftf2_fprs"
9138 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9139 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9140 (use (match_dup 2))])]
9141 "!TARGET_IEEEQUAD
9142 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9143 && TARGET_LONG_DOUBLE_128"
9144 {
9145 operands[2] = CONST0_RTX (DFmode);
9146 /* Generate GOT reference early for SVR4 PIC. */
9147 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9148 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9149 })
9151 (define_insn_and_split "*extenddftf2_internal"
9152 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9153 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9154 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9155 "!TARGET_IEEEQUAD
9156 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9157 && TARGET_LONG_DOUBLE_128"
9158 "#"
9159 "&& reload_completed"
9160 [(pc)]
9161 {
9162 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9163 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9164 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9165 operands[1]);
9166 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9167 operands[2]);
9168 DONE;
9169 })
9171 (define_expand "extendsftf2"
9172 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9173 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9174 "!TARGET_IEEEQUAD
9175 && TARGET_HARD_FLOAT
9176 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9177 && TARGET_LONG_DOUBLE_128"
9178 {
9179 rtx tmp = gen_reg_rtx (DFmode);
9180 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9181 emit_insn (gen_extenddftf2 (operands[0], tmp));
9182 DONE;
9183 })
9185 (define_expand "trunctfdf2"
9186 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9187 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9188 "!TARGET_IEEEQUAD
9189 && TARGET_HARD_FLOAT
9190 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9191 && TARGET_LONG_DOUBLE_128"
9192 "")
9194 (define_insn_and_split "trunctfdf2_internal1"
9195 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9196 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9197 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9198 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9199 "@
9200 #
9201 fmr %0,%1"
9202 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9203 [(const_int 0)]
9204 {
9205 emit_note (NOTE_INSN_DELETED);
9206 DONE;
9207 }
9208 [(set_attr "type" "fp")])
9210 (define_insn "trunctfdf2_internal2"
9211 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9212 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9213 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9214 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9215 && TARGET_LONG_DOUBLE_128"
9216 "fadd %0,%1,%L1"
9217 [(set_attr "type" "fp")
9218 (set_attr "fp_type" "fp_addsub_d")])
9220 (define_expand "trunctfsf2"
9221 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9222 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9223 "!TARGET_IEEEQUAD
9224 && TARGET_HARD_FLOAT
9225 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9226 && TARGET_LONG_DOUBLE_128"
9227 {
9228 if (TARGET_E500_DOUBLE)
9229 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9230 else
9231 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9232 DONE;
9233 })
9235 (define_insn_and_split "trunctfsf2_fprs"
9236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9237 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9238 (clobber (match_scratch:DF 2 "=d"))]
9239 "!TARGET_IEEEQUAD
9240 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9241 && TARGET_LONG_DOUBLE_128"
9242 "#"
9243 "&& reload_completed"
9244 [(set (match_dup 2)
9245 (float_truncate:DF (match_dup 1)))
9246 (set (match_dup 0)
9247 (float_truncate:SF (match_dup 2)))]
9248 "")
9250 (define_expand "floatsitf2"
9251 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9252 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9253 "!TARGET_IEEEQUAD
9254 && TARGET_HARD_FLOAT
9255 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9256 && TARGET_LONG_DOUBLE_128"
9257 {
9258 rtx tmp = gen_reg_rtx (DFmode);
9259 expand_float (tmp, operands[1], false);
9260 emit_insn (gen_extenddftf2 (operands[0], tmp));
9261 DONE;
9262 })
9264 ; fadd, but rounding towards zero.
9265 ; This is probably not the optimal code sequence.
9266 (define_insn "fix_trunc_helper"
9267 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9268 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9269 UNSPEC_FIX_TRUNC_TF))
9270 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9271 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9272 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9273 [(set_attr "type" "fp")
9274 (set_attr "length" "20")])
9276 (define_expand "fix_trunctfsi2"
9277 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9278 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9279 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9280 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9281 {
9282 if (TARGET_E500_DOUBLE)
9283 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9284 else
9285 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9286 DONE;
9287 })
9289 (define_expand "fix_trunctfsi2_fprs"
9290 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9291 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9292 (clobber (match_dup 2))
9293 (clobber (match_dup 3))
9294 (clobber (match_dup 4))
9295 (clobber (match_dup 5))])]
9296 "!TARGET_IEEEQUAD
9297 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9298 {
9299 operands[2] = gen_reg_rtx (DFmode);
9300 operands[3] = gen_reg_rtx (DFmode);
9301 operands[4] = gen_reg_rtx (DImode);
9302 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9303 })
9305 (define_insn_and_split "*fix_trunctfsi2_internal"
9306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9307 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9308 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9309 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9310 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9311 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9312 "!TARGET_IEEEQUAD
9313 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9314 "#"
9315 ""
9316 [(pc)]
9317 {
9318 rtx lowword;
9319 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9321 gcc_assert (MEM_P (operands[5]));
9322 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9324 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9325 emit_move_insn (operands[5], operands[4]);
9326 emit_move_insn (operands[0], lowword);
9327 DONE;
9328 })
9330 (define_expand "negtf2"
9331 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9332 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9333 "!TARGET_IEEEQUAD
9334 && TARGET_HARD_FLOAT
9335 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9336 && TARGET_LONG_DOUBLE_128"
9337 "")
9339 (define_insn "negtf2_internal"
9340 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9341 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9342 "!TARGET_IEEEQUAD
9343 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9344 "*
9345 {
9346 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9347 return \"fneg %L0,%L1\;fneg %0,%1\";
9348 else
9349 return \"fneg %0,%1\;fneg %L0,%L1\";
9350 }"
9351 [(set_attr "type" "fp")
9352 (set_attr "length" "8")])
9354 (define_expand "abstf2"
9355 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9356 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9357 "!TARGET_IEEEQUAD
9358 && TARGET_HARD_FLOAT
9359 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9360 && TARGET_LONG_DOUBLE_128"
9361 "
9362 {
9363 rtx label = gen_label_rtx ();
9364 if (TARGET_E500_DOUBLE)
9365 {
9366 if (flag_finite_math_only && !flag_trapping_math)
9367 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9368 else
9369 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9370 }
9371 else
9372 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9373 emit_label (label);
9374 DONE;
9375 }")
9377 (define_expand "abstf2_internal"
9378 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9379 (match_operand:TF 1 "gpc_reg_operand" ""))
9380 (set (match_dup 3) (match_dup 5))
9381 (set (match_dup 5) (abs:DF (match_dup 5)))
9382 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9383 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9384 (label_ref (match_operand 2 "" ""))
9385 (pc)))
9386 (set (match_dup 6) (neg:DF (match_dup 6)))]
9387 "!TARGET_IEEEQUAD
9388 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9389 && TARGET_LONG_DOUBLE_128"
9390 "
9391 {
9392 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9393 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9394 operands[3] = gen_reg_rtx (DFmode);
9395 operands[4] = gen_reg_rtx (CCFPmode);
9396 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9397 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9398 }")
9399 \f
9400 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9401 ;; must have 3 arguments, and scratch register constraint must be a single
9402 ;; constraint.
9404 ;; Reload patterns to support gpr load/store with misaligned mem.
9405 ;; and multiple gpr load/store at offset >= 0xfffc
9406 (define_expand "reload_<mode>_store"
9407 [(parallel [(match_operand 0 "memory_operand" "=m")
9408 (match_operand 1 "gpc_reg_operand" "r")
9409 (match_operand:GPR 2 "register_operand" "=&b")])]
9410 ""
9411 {
9412 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9413 DONE;
9414 })
9416 (define_expand "reload_<mode>_load"
9417 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9418 (match_operand 1 "memory_operand" "m")
9419 (match_operand:GPR 2 "register_operand" "=b")])]
9420 ""
9421 {
9422 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9423 DONE;
9424 })
9426 \f
9427 ;; Next come the multi-word integer load and store and the load and store
9428 ;; multiple insns.
9430 ;; List r->r after r->Y, otherwise reload will try to reload a
9431 ;; non-offsettable address by using r->r which won't make progress.
9432 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9433 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9434 (define_insn "*movdi_internal32"
9435 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
9436 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
9437 "! TARGET_POWERPC64
9438 && (gpc_reg_operand (operands[0], DImode)
9439 || gpc_reg_operand (operands[1], DImode))"
9440 "@
9441 #
9442 #
9443 #
9444 stfd%U0%X0 %1,%0
9445 lfd%U1%X1 %0,%1
9446 fmr %0,%1
9447 #
9448 xxlxor %x0,%x0,%x0"
9449 [(set_attr_alternative "type"
9450 [(const_string "store")
9451 (const_string "load")
9452 (const_string "*")
9453 (if_then_else
9454 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9455 (const_string "fpstore_ux")
9456 (if_then_else
9457 (match_test "update_address_mem (operands[0], VOIDmode)")
9458 (const_string "fpstore_u")
9459 (const_string "fpstore")))
9460 (if_then_else
9461 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9462 (const_string "fpload_ux")
9463 (if_then_else
9464 (match_test "update_address_mem (operands[1], VOIDmode)")
9465 (const_string "fpload_u")
9466 (const_string "fpload")))
9467 (const_string "fp")
9468 (const_string "*")
9469 (const_string "vecsimple")])])
9471 (define_split
9472 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9473 (match_operand:DI 1 "const_int_operand" ""))]
9474 "! TARGET_POWERPC64 && reload_completed
9475 && gpr_or_gpr_p (operands[0], operands[1])"
9476 [(set (match_dup 2) (match_dup 4))
9477 (set (match_dup 3) (match_dup 1))]
9478 "
9479 {
9480 HOST_WIDE_INT value = INTVAL (operands[1]);
9481 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9482 DImode);
9483 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9484 DImode);
9485 operands[4] = GEN_INT (value >> 32);
9486 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9487 }")
9489 (define_split
9490 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9491 (match_operand:DIFD 1 "input_operand" ""))]
9492 "reload_completed && !TARGET_POWERPC64
9493 && gpr_or_gpr_p (operands[0], operands[1])"
9494 [(pc)]
9495 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9497 (define_insn "*movdi_internal64"
9498 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wa,?wa,r,*h,*h,?wa,r,?*wg")
9499 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wa,Z,wa,*h,r,0,O,*wg,r"))]
9500 "TARGET_POWERPC64
9501 && (gpc_reg_operand (operands[0], DImode)
9502 || gpc_reg_operand (operands[1], DImode))"
9503 "@
9504 std%U0%X0 %1,%0
9505 ld%U1%X1 %0,%1
9506 mr %0,%1
9507 li %0,%1
9508 lis %0,%v1
9509 #
9510 stfd%U0%X0 %1,%0
9511 lfd%U1%X1 %0,%1
9512 fmr %0,%1
9513 stxsd%U0x %x1,%y0
9514 lxsd%U1x %x0,%y1
9515 xxlor %x0,%x1,%x1
9516 mf%1 %0
9517 mt%0 %1
9518 nop
9519 xxlxor %x0,%x0,%x0
9520 mftgpr %0,%1
9521 mffgpr %0,%1"
9522 [(set_attr_alternative "type"
9523 [(if_then_else
9524 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9525 (const_string "store_ux")
9526 (if_then_else
9527 (match_test "update_address_mem (operands[0], VOIDmode)")
9528 (const_string "store_u")
9529 (const_string "store")))
9530 (if_then_else
9531 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9532 (const_string "load_ux")
9533 (if_then_else
9534 (match_test "update_address_mem (operands[1], VOIDmode)")
9535 (const_string "load_u")
9536 (const_string "load")))
9537 (const_string "*")
9538 (const_string "*")
9539 (const_string "*")
9540 (const_string "*")
9541 (if_then_else
9542 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9543 (const_string "fpstore_ux")
9544 (if_then_else
9545 (match_test "update_address_mem (operands[0], VOIDmode)")
9546 (const_string "fpstore_u")
9547 (const_string "fpstore")))
9548 (if_then_else
9549 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9550 (const_string "fpload_ux")
9551 (if_then_else
9552 (match_test "update_address_mem (operands[1], VOIDmode)")
9553 (const_string "fpload_u")
9554 (const_string "fpload")))
9555 (const_string "fp")
9556 (if_then_else
9557 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9558 (const_string "fpstore_ux")
9559 (const_string "fpstore"))
9560 (if_then_else
9561 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9562 (const_string "fpload_ux")
9563 (const_string "fpload"))
9564 (const_string "vecsimple")
9565 (const_string "mfjmpr")
9566 (const_string "mtjmpr")
9567 (const_string "*")
9568 (const_string "vecsimple")
9569 (const_string "mftgpr")
9570 (const_string "mffgpr")])
9571 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4")])
9573 ;; Generate all one-bits and clear left or right.
9574 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9575 (define_split
9576 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9577 (match_operand:DI 1 "mask64_operand" ""))]
9578 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9579 [(set (match_dup 0) (const_int -1))
9580 (set (match_dup 0)
9581 (and:DI (rotate:DI (match_dup 0)
9582 (const_int 0))
9583 (match_dup 1)))]
9584 "")
9586 ;; Split a load of a large constant into the appropriate five-instruction
9587 ;; sequence. Handle anything in a constant number of insns.
9588 ;; When non-easy constants can go in the TOC, this should use
9589 ;; easy_fp_constant predicate.
9590 (define_split
9591 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9592 (match_operand:DI 1 "const_int_operand" ""))]
9593 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9594 [(set (match_dup 0) (match_dup 2))
9595 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9596 "
9597 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9599 if (tem == operands[0])
9600 DONE;
9601 else
9602 FAIL;
9603 }")
9605 (define_split
9606 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9607 (match_operand:DI 1 "const_double_operand" ""))]
9608 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9609 [(set (match_dup 0) (match_dup 2))
9610 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9611 "
9612 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9614 if (tem == operands[0])
9615 DONE;
9616 else
9617 FAIL;
9618 }")
9619 \f
9620 ;; TImode/PTImode is similar, except that we usually want to compute the
9621 ;; address into a register and use lsi/stsi (the exception is during reload).
9623 (define_insn "*mov<mode>_string"
9624 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9625 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9626 "! TARGET_POWERPC64
9627 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9628 && (gpc_reg_operand (operands[0], <MODE>mode)
9629 || gpc_reg_operand (operands[1], <MODE>mode))"
9630 "*
9631 {
9632 switch (which_alternative)
9633 {
9634 default:
9635 gcc_unreachable ();
9636 case 0:
9637 if (TARGET_STRING)
9638 return \"stswi %1,%P0,16\";
9639 case 1:
9640 return \"#\";
9641 case 2:
9642 /* If the address is not used in the output, we can use lsi. Otherwise,
9643 fall through to generating four loads. */
9644 if (TARGET_STRING
9645 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9646 return \"lswi %0,%P1,16\";
9647 /* ... fall through ... */
9648 case 3:
9649 case 4:
9650 case 5:
9651 return \"#\";
9652 }
9653 }"
9654 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
9655 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9656 (const_string "always")
9657 (const_string "conditional")))])
9659 (define_insn "*mov<mode>_ppc64"
9660 [(set (match_operand:TI2 0 "nonimmediate_operand" "=Y,r,r")
9661 (match_operand:TI2 1 "input_operand" "r,Y,r"))]
9662 "(TARGET_POWERPC64
9663 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9664 && (gpc_reg_operand (operands[0], <MODE>mode)
9665 || gpc_reg_operand (operands[1], <MODE>mode)))"
9666 "#"
9667 [(set_attr "type" "store,load,*")])
9669 (define_split
9670 [(set (match_operand:TI2 0 "gpc_reg_operand" "")
9671 (match_operand:TI2 1 "const_double_operand" ""))]
9672 "TARGET_POWERPC64"
9673 [(set (match_dup 2) (match_dup 4))
9674 (set (match_dup 3) (match_dup 5))]
9675 "
9676 {
9677 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9678 <MODE>mode);
9679 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9680 <MODE>mode);
9681 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9682 {
9683 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9684 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9685 }
9686 else if (GET_CODE (operands[1]) == CONST_INT)
9687 {
9688 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9689 operands[5] = operands[1];
9690 }
9691 else
9692 FAIL;
9693 }")
9695 (define_split
9696 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
9697 (match_operand:TI2 1 "input_operand" ""))]
9698 "reload_completed
9699 && gpr_or_gpr_p (operands[0], operands[1])"
9700 [(pc)]
9701 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9702 \f
9703 (define_expand "load_multiple"
9704 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9705 (match_operand:SI 1 "" ""))
9706 (use (match_operand:SI 2 "" ""))])]
9707 "TARGET_STRING && !TARGET_POWERPC64"
9708 "
9709 {
9710 int regno;
9711 int count;
9712 rtx op1;
9713 int i;
9715 /* Support only loading a constant number of fixed-point registers from
9716 memory and only bother with this if more than two; the machine
9717 doesn't support more than eight. */
9718 if (GET_CODE (operands[2]) != CONST_INT
9719 || INTVAL (operands[2]) <= 2
9720 || INTVAL (operands[2]) > 8
9721 || GET_CODE (operands[1]) != MEM
9722 || GET_CODE (operands[0]) != REG
9723 || REGNO (operands[0]) >= 32)
9724 FAIL;
9726 count = INTVAL (operands[2]);
9727 regno = REGNO (operands[0]);
9729 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9730 op1 = replace_equiv_address (operands[1],
9731 force_reg (SImode, XEXP (operands[1], 0)));
9733 for (i = 0; i < count; i++)
9734 XVECEXP (operands[3], 0, i)
9735 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9736 adjust_address_nv (op1, SImode, i * 4));
9737 }")
9739 (define_insn "*ldmsi8"
9740 [(match_parallel 0 "load_multiple_operation"
9741 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9742 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9743 (set (match_operand:SI 3 "gpc_reg_operand" "")
9744 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9745 (set (match_operand:SI 4 "gpc_reg_operand" "")
9746 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9747 (set (match_operand:SI 5 "gpc_reg_operand" "")
9748 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9749 (set (match_operand:SI 6 "gpc_reg_operand" "")
9750 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9751 (set (match_operand:SI 7 "gpc_reg_operand" "")
9752 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9753 (set (match_operand:SI 8 "gpc_reg_operand" "")
9754 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9755 (set (match_operand:SI 9 "gpc_reg_operand" "")
9756 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9757 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9758 "*
9759 { return rs6000_output_load_multiple (operands); }"
9760 [(set_attr "type" "load_ux")
9761 (set_attr "length" "32")])
9763 (define_insn "*ldmsi7"
9764 [(match_parallel 0 "load_multiple_operation"
9765 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9766 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9767 (set (match_operand:SI 3 "gpc_reg_operand" "")
9768 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9769 (set (match_operand:SI 4 "gpc_reg_operand" "")
9770 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9771 (set (match_operand:SI 5 "gpc_reg_operand" "")
9772 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9773 (set (match_operand:SI 6 "gpc_reg_operand" "")
9774 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9775 (set (match_operand:SI 7 "gpc_reg_operand" "")
9776 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9777 (set (match_operand:SI 8 "gpc_reg_operand" "")
9778 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9779 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9780 "*
9781 { return rs6000_output_load_multiple (operands); }"
9782 [(set_attr "type" "load_ux")
9783 (set_attr "length" "32")])
9785 (define_insn "*ldmsi6"
9786 [(match_parallel 0 "load_multiple_operation"
9787 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9788 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9789 (set (match_operand:SI 3 "gpc_reg_operand" "")
9790 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9791 (set (match_operand:SI 4 "gpc_reg_operand" "")
9792 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9793 (set (match_operand:SI 5 "gpc_reg_operand" "")
9794 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9795 (set (match_operand:SI 6 "gpc_reg_operand" "")
9796 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9797 (set (match_operand:SI 7 "gpc_reg_operand" "")
9798 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9799 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9800 "*
9801 { return rs6000_output_load_multiple (operands); }"
9802 [(set_attr "type" "load_ux")
9803 (set_attr "length" "32")])
9805 (define_insn "*ldmsi5"
9806 [(match_parallel 0 "load_multiple_operation"
9807 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9808 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9809 (set (match_operand:SI 3 "gpc_reg_operand" "")
9810 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9811 (set (match_operand:SI 4 "gpc_reg_operand" "")
9812 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9813 (set (match_operand:SI 5 "gpc_reg_operand" "")
9814 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9815 (set (match_operand:SI 6 "gpc_reg_operand" "")
9816 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9817 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9818 "*
9819 { return rs6000_output_load_multiple (operands); }"
9820 [(set_attr "type" "load_ux")
9821 (set_attr "length" "32")])
9823 (define_insn "*ldmsi4"
9824 [(match_parallel 0 "load_multiple_operation"
9825 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9826 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9827 (set (match_operand:SI 3 "gpc_reg_operand" "")
9828 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9829 (set (match_operand:SI 4 "gpc_reg_operand" "")
9830 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9831 (set (match_operand:SI 5 "gpc_reg_operand" "")
9832 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9833 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9834 "*
9835 { return rs6000_output_load_multiple (operands); }"
9836 [(set_attr "type" "load_ux")
9837 (set_attr "length" "32")])
9839 (define_insn "*ldmsi3"
9840 [(match_parallel 0 "load_multiple_operation"
9841 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9842 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9843 (set (match_operand:SI 3 "gpc_reg_operand" "")
9844 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9845 (set (match_operand:SI 4 "gpc_reg_operand" "")
9846 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9847 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9848 "*
9849 { return rs6000_output_load_multiple (operands); }"
9850 [(set_attr "type" "load_ux")
9851 (set_attr "length" "32")])
9853 (define_expand "store_multiple"
9854 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9855 (match_operand:SI 1 "" ""))
9856 (clobber (scratch:SI))
9857 (use (match_operand:SI 2 "" ""))])]
9858 "TARGET_STRING && !TARGET_POWERPC64"
9859 "
9860 {
9861 int regno;
9862 int count;
9863 rtx to;
9864 rtx op0;
9865 int i;
9867 /* Support only storing a constant number of fixed-point registers to
9868 memory and only bother with this if more than two; the machine
9869 doesn't support more than eight. */
9870 if (GET_CODE (operands[2]) != CONST_INT
9871 || INTVAL (operands[2]) <= 2
9872 || INTVAL (operands[2]) > 8
9873 || GET_CODE (operands[0]) != MEM
9874 || GET_CODE (operands[1]) != REG
9875 || REGNO (operands[1]) >= 32)
9876 FAIL;
9878 count = INTVAL (operands[2]);
9879 regno = REGNO (operands[1]);
9881 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9882 to = force_reg (SImode, XEXP (operands[0], 0));
9883 op0 = replace_equiv_address (operands[0], to);
9885 XVECEXP (operands[3], 0, 0)
9886 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9887 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9888 gen_rtx_SCRATCH (SImode));
9890 for (i = 1; i < count; i++)
9891 XVECEXP (operands[3], 0, i + 1)
9892 = gen_rtx_SET (VOIDmode,
9893 adjust_address_nv (op0, SImode, i * 4),
9894 gen_rtx_REG (SImode, regno + i));
9895 }")
9897 (define_insn "*stmsi8"
9898 [(match_parallel 0 "store_multiple_operation"
9899 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9900 (match_operand:SI 2 "gpc_reg_operand" "r"))
9901 (clobber (match_scratch:SI 3 "=X"))
9902 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9903 (match_operand:SI 4 "gpc_reg_operand" "r"))
9904 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9905 (match_operand:SI 5 "gpc_reg_operand" "r"))
9906 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9907 (match_operand:SI 6 "gpc_reg_operand" "r"))
9908 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9909 (match_operand:SI 7 "gpc_reg_operand" "r"))
9910 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9911 (match_operand:SI 8 "gpc_reg_operand" "r"))
9912 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9913 (match_operand:SI 9 "gpc_reg_operand" "r"))
9914 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9915 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9916 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9917 "stswi %2,%1,%O0"
9918 [(set_attr "type" "store_ux")
9919 (set_attr "cell_micro" "always")])
9921 (define_insn "*stmsi7"
9922 [(match_parallel 0 "store_multiple_operation"
9923 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9924 (match_operand:SI 2 "gpc_reg_operand" "r"))
9925 (clobber (match_scratch:SI 3 "=X"))
9926 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9927 (match_operand:SI 4 "gpc_reg_operand" "r"))
9928 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9929 (match_operand:SI 5 "gpc_reg_operand" "r"))
9930 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9931 (match_operand:SI 6 "gpc_reg_operand" "r"))
9932 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9933 (match_operand:SI 7 "gpc_reg_operand" "r"))
9934 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9935 (match_operand:SI 8 "gpc_reg_operand" "r"))
9936 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9937 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9938 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9939 "stswi %2,%1,%O0"
9940 [(set_attr "type" "store_ux")
9941 (set_attr "cell_micro" "always")])
9943 (define_insn "*stmsi6"
9944 [(match_parallel 0 "store_multiple_operation"
9945 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9946 (match_operand:SI 2 "gpc_reg_operand" "r"))
9947 (clobber (match_scratch:SI 3 "=X"))
9948 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9949 (match_operand:SI 4 "gpc_reg_operand" "r"))
9950 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9951 (match_operand:SI 5 "gpc_reg_operand" "r"))
9952 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9953 (match_operand:SI 6 "gpc_reg_operand" "r"))
9954 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9955 (match_operand:SI 7 "gpc_reg_operand" "r"))
9956 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9957 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9958 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9959 "stswi %2,%1,%O0"
9960 [(set_attr "type" "store_ux")
9961 (set_attr "cell_micro" "always")])
9963 (define_insn "*stmsi5"
9964 [(match_parallel 0 "store_multiple_operation"
9965 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9966 (match_operand:SI 2 "gpc_reg_operand" "r"))
9967 (clobber (match_scratch:SI 3 "=X"))
9968 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9969 (match_operand:SI 4 "gpc_reg_operand" "r"))
9970 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9971 (match_operand:SI 5 "gpc_reg_operand" "r"))
9972 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9973 (match_operand:SI 6 "gpc_reg_operand" "r"))
9974 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9975 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9976 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9977 "stswi %2,%1,%O0"
9978 [(set_attr "type" "store_ux")
9979 (set_attr "cell_micro" "always")])
9981 (define_insn "*stmsi4"
9982 [(match_parallel 0 "store_multiple_operation"
9983 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9984 (match_operand:SI 2 "gpc_reg_operand" "r"))
9985 (clobber (match_scratch:SI 3 "=X"))
9986 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9987 (match_operand:SI 4 "gpc_reg_operand" "r"))
9988 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9989 (match_operand:SI 5 "gpc_reg_operand" "r"))
9990 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9991 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9992 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9993 "stswi %2,%1,%O0"
9994 [(set_attr "type" "store_ux")
9995 (set_attr "cell_micro" "always")])
9997 (define_insn "*stmsi3"
9998 [(match_parallel 0 "store_multiple_operation"
9999 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10000 (match_operand:SI 2 "gpc_reg_operand" "r"))
10001 (clobber (match_scratch:SI 3 "=X"))
10002 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10003 (match_operand:SI 4 "gpc_reg_operand" "r"))
10004 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10005 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10006 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10007 "stswi %2,%1,%O0"
10008 [(set_attr "type" "store_ux")
10009 (set_attr "cell_micro" "always")])
10010 \f
10011 (define_expand "setmemsi"
10012 [(parallel [(set (match_operand:BLK 0 "" "")
10013 (match_operand 2 "const_int_operand" ""))
10014 (use (match_operand:SI 1 "" ""))
10015 (use (match_operand:SI 3 "" ""))])]
10016 ""
10017 "
10018 {
10019 /* If value to set is not zero, use the library routine. */
10020 if (operands[2] != const0_rtx)
10021 FAIL;
10023 if (expand_block_clear (operands))
10024 DONE;
10025 else
10026 FAIL;
10027 }")
10029 ;; String/block move insn.
10030 ;; Argument 0 is the destination
10031 ;; Argument 1 is the source
10032 ;; Argument 2 is the length
10033 ;; Argument 3 is the alignment
10035 (define_expand "movmemsi"
10036 [(parallel [(set (match_operand:BLK 0 "" "")
10037 (match_operand:BLK 1 "" ""))
10038 (use (match_operand:SI 2 "" ""))
10039 (use (match_operand:SI 3 "" ""))])]
10040 ""
10041 "
10042 {
10043 if (expand_block_move (operands))
10044 DONE;
10045 else
10046 FAIL;
10047 }")
10049 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10050 ;; register allocator doesn't have a clue about allocating 8 word registers.
10051 ;; rD/rS = r5 is preferred, efficient form.
10052 (define_expand "movmemsi_8reg"
10053 [(parallel [(set (match_operand 0 "" "")
10054 (match_operand 1 "" ""))
10055 (use (match_operand 2 "" ""))
10056 (use (match_operand 3 "" ""))
10057 (clobber (reg:SI 5))
10058 (clobber (reg:SI 6))
10059 (clobber (reg:SI 7))
10060 (clobber (reg:SI 8))
10061 (clobber (reg:SI 9))
10062 (clobber (reg:SI 10))
10063 (clobber (reg:SI 11))
10064 (clobber (reg:SI 12))
10065 (clobber (match_scratch:SI 4 ""))])]
10066 "TARGET_STRING"
10067 "")
10069 (define_insn ""
10070 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10071 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10072 (use (match_operand:SI 2 "immediate_operand" "i"))
10073 (use (match_operand:SI 3 "immediate_operand" "i"))
10074 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10075 (clobber (reg:SI 6))
10076 (clobber (reg:SI 7))
10077 (clobber (reg:SI 8))
10078 (clobber (reg:SI 9))
10079 (clobber (reg:SI 10))
10080 (clobber (reg:SI 11))
10081 (clobber (reg:SI 12))
10082 (clobber (match_scratch:SI 5 "=X"))]
10083 "TARGET_STRING
10084 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10085 || INTVAL (operands[2]) == 0)
10086 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10087 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10088 && REGNO (operands[4]) == 5"
10089 "lswi %4,%1,%2\;stswi %4,%0,%2"
10090 [(set_attr "type" "store_ux")
10091 (set_attr "cell_micro" "always")
10092 (set_attr "length" "8")])
10094 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10095 ;; register allocator doesn't have a clue about allocating 6 word registers.
10096 ;; rD/rS = r5 is preferred, efficient form.
10097 (define_expand "movmemsi_6reg"
10098 [(parallel [(set (match_operand 0 "" "")
10099 (match_operand 1 "" ""))
10100 (use (match_operand 2 "" ""))
10101 (use (match_operand 3 "" ""))
10102 (clobber (reg:SI 5))
10103 (clobber (reg:SI 6))
10104 (clobber (reg:SI 7))
10105 (clobber (reg:SI 8))
10106 (clobber (reg:SI 9))
10107 (clobber (reg:SI 10))
10108 (clobber (match_scratch:SI 4 ""))])]
10109 "TARGET_STRING"
10110 "")
10112 (define_insn ""
10113 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10114 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10115 (use (match_operand:SI 2 "immediate_operand" "i"))
10116 (use (match_operand:SI 3 "immediate_operand" "i"))
10117 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10118 (clobber (reg:SI 6))
10119 (clobber (reg:SI 7))
10120 (clobber (reg:SI 8))
10121 (clobber (reg:SI 9))
10122 (clobber (reg:SI 10))
10123 (clobber (match_scratch:SI 5 "=X"))]
10124 "TARGET_STRING
10125 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10126 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10127 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10128 && REGNO (operands[4]) == 5"
10129 "lswi %4,%1,%2\;stswi %4,%0,%2"
10130 [(set_attr "type" "store_ux")
10131 (set_attr "cell_micro" "always")
10132 (set_attr "length" "8")])
10134 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10135 ;; problems with TImode.
10136 ;; rD/rS = r5 is preferred, efficient form.
10137 (define_expand "movmemsi_4reg"
10138 [(parallel [(set (match_operand 0 "" "")
10139 (match_operand 1 "" ""))
10140 (use (match_operand 2 "" ""))
10141 (use (match_operand 3 "" ""))
10142 (clobber (reg:SI 5))
10143 (clobber (reg:SI 6))
10144 (clobber (reg:SI 7))
10145 (clobber (reg:SI 8))
10146 (clobber (match_scratch:SI 4 ""))])]
10147 "TARGET_STRING"
10148 "")
10150 (define_insn ""
10151 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10152 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10153 (use (match_operand:SI 2 "immediate_operand" "i"))
10154 (use (match_operand:SI 3 "immediate_operand" "i"))
10155 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10156 (clobber (reg:SI 6))
10157 (clobber (reg:SI 7))
10158 (clobber (reg:SI 8))
10159 (clobber (match_scratch:SI 5 "=X"))]
10160 "TARGET_STRING
10161 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10162 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10163 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10164 && REGNO (operands[4]) == 5"
10165 "lswi %4,%1,%2\;stswi %4,%0,%2"
10166 [(set_attr "type" "store_ux")
10167 (set_attr "cell_micro" "always")
10168 (set_attr "length" "8")])
10170 ;; Move up to 8 bytes at a time.
10171 (define_expand "movmemsi_2reg"
10172 [(parallel [(set (match_operand 0 "" "")
10173 (match_operand 1 "" ""))
10174 (use (match_operand 2 "" ""))
10175 (use (match_operand 3 "" ""))
10176 (clobber (match_scratch:DI 4 ""))
10177 (clobber (match_scratch:SI 5 ""))])]
10178 "TARGET_STRING && ! TARGET_POWERPC64"
10179 "")
10181 (define_insn ""
10182 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10183 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10184 (use (match_operand:SI 2 "immediate_operand" "i"))
10185 (use (match_operand:SI 3 "immediate_operand" "i"))
10186 (clobber (match_scratch:DI 4 "=&r"))
10187 (clobber (match_scratch:SI 5 "=X"))]
10188 "TARGET_STRING && ! TARGET_POWERPC64
10189 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10190 "lswi %4,%1,%2\;stswi %4,%0,%2"
10191 [(set_attr "type" "store_ux")
10192 (set_attr "cell_micro" "always")
10193 (set_attr "length" "8")])
10195 ;; Move up to 4 bytes at a time.
10196 (define_expand "movmemsi_1reg"
10197 [(parallel [(set (match_operand 0 "" "")
10198 (match_operand 1 "" ""))
10199 (use (match_operand 2 "" ""))
10200 (use (match_operand 3 "" ""))
10201 (clobber (match_scratch:SI 4 ""))
10202 (clobber (match_scratch:SI 5 ""))])]
10203 "TARGET_STRING"
10204 "")
10206 (define_insn ""
10207 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10208 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10209 (use (match_operand:SI 2 "immediate_operand" "i"))
10210 (use (match_operand:SI 3 "immediate_operand" "i"))
10211 (clobber (match_scratch:SI 4 "=&r"))
10212 (clobber (match_scratch:SI 5 "=X"))]
10213 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10214 "lswi %4,%1,%2\;stswi %4,%0,%2"
10215 [(set_attr "type" "store_ux")
10216 (set_attr "cell_micro" "always")
10217 (set_attr "length" "8")])
10218 \f
10219 ;; Define insns that do load or store with update. Some of these we can
10220 ;; get by using pre-decrement or pre-increment, but the hardware can also
10221 ;; do cases where the increment is not the size of the object.
10222 ;;
10223 ;; In all these cases, we use operands 0 and 1 for the register being
10224 ;; incremented because those are the operands that local-alloc will
10225 ;; tie and these are the pair most likely to be tieable (and the ones
10226 ;; that will benefit the most).
10228 (define_insn "*movdi_update1"
10229 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10230 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10231 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10232 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10233 (plus:DI (match_dup 1) (match_dup 2)))]
10234 "TARGET_POWERPC64 && TARGET_UPDATE
10235 && (!avoiding_indexed_address_p (DImode)
10236 || !gpc_reg_operand (operands[2], DImode))"
10237 "@
10238 ldux %3,%0,%2
10239 ldu %3,%2(%0)"
10240 [(set_attr "type" "load_ux,load_u")])
10242 (define_insn "movdi_<mode>_update"
10243 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10244 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10245 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10246 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10247 (plus:P (match_dup 1) (match_dup 2)))]
10248 "TARGET_POWERPC64 && TARGET_UPDATE
10249 && (!avoiding_indexed_address_p (Pmode)
10250 || !gpc_reg_operand (operands[2], Pmode)
10251 || (REG_P (operands[0])
10252 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10253 "@
10254 stdux %3,%0,%2
10255 stdu %3,%2(%0)"
10256 [(set_attr "type" "store_ux,store_u")])
10258 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10259 ;; needed for stack allocation, even if the user passes -mno-update.
10260 (define_insn "movdi_<mode>_update_stack"
10261 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10262 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10263 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10264 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10265 (plus:P (match_dup 1) (match_dup 2)))]
10266 "TARGET_POWERPC64"
10267 "@
10268 stdux %3,%0,%2
10269 stdu %3,%2(%0)"
10270 [(set_attr "type" "store_ux,store_u")])
10272 (define_insn "*movsi_update1"
10273 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10274 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10275 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10276 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10277 (plus:SI (match_dup 1) (match_dup 2)))]
10278 "TARGET_UPDATE
10279 && (!avoiding_indexed_address_p (SImode)
10280 || !gpc_reg_operand (operands[2], SImode))"
10281 "@
10282 lwzux %3,%0,%2
10283 lwzu %3,%2(%0)"
10284 [(set_attr "type" "load_ux,load_u")])
10286 (define_insn "*movsi_update2"
10287 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10288 (sign_extend:DI
10289 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10290 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10291 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10292 (plus:DI (match_dup 1) (match_dup 2)))]
10293 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10294 && !avoiding_indexed_address_p (DImode)"
10295 "lwaux %3,%0,%2"
10296 [(set_attr "type" "load_ext_ux")])
10298 (define_insn "movsi_update"
10299 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10300 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10301 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10302 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10303 (plus:SI (match_dup 1) (match_dup 2)))]
10304 "TARGET_UPDATE
10305 && (!avoiding_indexed_address_p (SImode)
10306 || !gpc_reg_operand (operands[2], SImode)
10307 || (REG_P (operands[0])
10308 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10309 "@
10310 stwux %3,%0,%2
10311 stwu %3,%2(%0)"
10312 [(set_attr "type" "store_ux,store_u")])
10314 ;; This is an unconditional pattern; needed for stack allocation, even
10315 ;; if the user passes -mno-update.
10316 (define_insn "movsi_update_stack"
10317 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10318 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10319 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10320 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10321 (plus:SI (match_dup 1) (match_dup 2)))]
10322 ""
10323 "@
10324 stwux %3,%0,%2
10325 stwu %3,%2(%0)"
10326 [(set_attr "type" "store_ux,store_u")])
10328 (define_insn "*movhi_update1"
10329 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10330 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10331 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10332 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10333 (plus:SI (match_dup 1) (match_dup 2)))]
10334 "TARGET_UPDATE
10335 && (!avoiding_indexed_address_p (SImode)
10336 || !gpc_reg_operand (operands[2], SImode))"
10337 "@
10338 lhzux %3,%0,%2
10339 lhzu %3,%2(%0)"
10340 [(set_attr "type" "load_ux,load_u")])
10342 (define_insn "*movhi_update2"
10343 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10344 (zero_extend:SI
10345 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10346 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10347 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10348 (plus:SI (match_dup 1) (match_dup 2)))]
10349 "TARGET_UPDATE
10350 && (!avoiding_indexed_address_p (SImode)
10351 || !gpc_reg_operand (operands[2], SImode))"
10352 "@
10353 lhzux %3,%0,%2
10354 lhzu %3,%2(%0)"
10355 [(set_attr "type" "load_ux,load_u")])
10357 (define_insn "*movhi_update3"
10358 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10359 (sign_extend:SI
10360 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10361 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10362 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10363 (plus:SI (match_dup 1) (match_dup 2)))]
10364 "TARGET_UPDATE && rs6000_gen_cell_microcode
10365 && (!avoiding_indexed_address_p (SImode)
10366 || !gpc_reg_operand (operands[2], SImode))"
10367 "@
10368 lhaux %3,%0,%2
10369 lhau %3,%2(%0)"
10370 [(set_attr "type" "load_ext_ux,load_ext_u")])
10372 (define_insn "*movhi_update4"
10373 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10374 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10375 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10376 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10377 (plus:SI (match_dup 1) (match_dup 2)))]
10378 "TARGET_UPDATE
10379 && (!avoiding_indexed_address_p (SImode)
10380 || !gpc_reg_operand (operands[2], SImode))"
10381 "@
10382 sthux %3,%0,%2
10383 sthu %3,%2(%0)"
10384 [(set_attr "type" "store_ux,store_u")])
10386 (define_insn "*movqi_update1"
10387 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10388 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10389 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10390 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10391 (plus:SI (match_dup 1) (match_dup 2)))]
10392 "TARGET_UPDATE
10393 && (!avoiding_indexed_address_p (SImode)
10394 || !gpc_reg_operand (operands[2], SImode))"
10395 "@
10396 lbzux %3,%0,%2
10397 lbzu %3,%2(%0)"
10398 [(set_attr "type" "load_ux,load_u")])
10400 (define_insn "*movqi_update2"
10401 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10402 (zero_extend:SI
10403 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10404 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10405 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10406 (plus:SI (match_dup 1) (match_dup 2)))]
10407 "TARGET_UPDATE
10408 && (!avoiding_indexed_address_p (SImode)
10409 || !gpc_reg_operand (operands[2], SImode))"
10410 "@
10411 lbzux %3,%0,%2
10412 lbzu %3,%2(%0)"
10413 [(set_attr "type" "load_ux,load_u")])
10415 (define_insn "*movqi_update3"
10416 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10417 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10418 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10419 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10420 (plus:SI (match_dup 1) (match_dup 2)))]
10421 "TARGET_UPDATE
10422 && (!avoiding_indexed_address_p (SImode)
10423 || !gpc_reg_operand (operands[2], SImode))"
10424 "@
10425 stbux %3,%0,%2
10426 stbu %3,%2(%0)"
10427 [(set_attr "type" "store_ux,store_u")])
10429 (define_insn "*movsf_update1"
10430 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10431 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10432 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10433 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10434 (plus:SI (match_dup 1) (match_dup 2)))]
10435 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10436 && (!avoiding_indexed_address_p (SImode)
10437 || !gpc_reg_operand (operands[2], SImode))"
10438 "@
10439 lfsux %3,%0,%2
10440 lfsu %3,%2(%0)"
10441 [(set_attr "type" "fpload_ux,fpload_u")])
10443 (define_insn "*movsf_update2"
10444 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10445 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10446 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10447 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10448 (plus:SI (match_dup 1) (match_dup 2)))]
10449 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10450 && (!avoiding_indexed_address_p (SImode)
10451 || !gpc_reg_operand (operands[2], SImode))"
10452 "@
10453 stfsux %3,%0,%2
10454 stfsu %3,%2(%0)"
10455 [(set_attr "type" "fpstore_ux,fpstore_u")])
10457 (define_insn "*movsf_update3"
10458 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10459 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10460 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10461 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10462 (plus:SI (match_dup 1) (match_dup 2)))]
10463 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10464 && (!avoiding_indexed_address_p (SImode)
10465 || !gpc_reg_operand (operands[2], SImode))"
10466 "@
10467 lwzux %3,%0,%2
10468 lwzu %3,%2(%0)"
10469 [(set_attr "type" "load_ux,load_u")])
10471 (define_insn "*movsf_update4"
10472 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10473 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10474 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10475 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10476 (plus:SI (match_dup 1) (match_dup 2)))]
10477 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10478 && (!avoiding_indexed_address_p (SImode)
10479 || !gpc_reg_operand (operands[2], SImode))"
10480 "@
10481 stwux %3,%0,%2
10482 stwu %3,%2(%0)"
10483 [(set_attr "type" "store_ux,store_u")])
10485 (define_insn "*movdf_update1"
10486 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10487 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10488 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10489 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10490 (plus:SI (match_dup 1) (match_dup 2)))]
10491 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10492 && (!avoiding_indexed_address_p (SImode)
10493 || !gpc_reg_operand (operands[2], SImode))"
10494 "@
10495 lfdux %3,%0,%2
10496 lfdu %3,%2(%0)"
10497 [(set_attr "type" "fpload_ux,fpload_u")])
10499 (define_insn "*movdf_update2"
10500 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10501 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10502 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10503 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10504 (plus:SI (match_dup 1) (match_dup 2)))]
10505 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10506 && (!avoiding_indexed_address_p (SImode)
10507 || !gpc_reg_operand (operands[2], SImode))"
10508 "@
10509 stfdux %3,%0,%2
10510 stfdu %3,%2(%0)"
10511 [(set_attr "type" "fpstore_ux,fpstore_u")])
10514 ;; After inserting conditional returns we can sometimes have
10515 ;; unnecessary register moves. Unfortunately we cannot have a
10516 ;; modeless peephole here, because some single SImode sets have early
10517 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10518 ;; sequences, using get_attr_length here will smash the operands
10519 ;; array. Neither is there an early_cobbler_p predicate.
10520 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10521 (define_peephole2
10522 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10523 (match_operand:DF 1 "any_operand" ""))
10524 (set (match_operand:DF 2 "gpc_reg_operand" "")
10525 (match_dup 0))]
10526 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10527 && peep2_reg_dead_p (2, operands[0])"
10528 [(set (match_dup 2) (match_dup 1))])
10530 (define_peephole2
10531 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10532 (match_operand:SF 1 "any_operand" ""))
10533 (set (match_operand:SF 2 "gpc_reg_operand" "")
10534 (match_dup 0))]
10535 "peep2_reg_dead_p (2, operands[0])"
10536 [(set (match_dup 2) (match_dup 1))])
10538 \f
10539 ;; TLS support.
10541 ;; Mode attributes for different ABIs.
10542 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10543 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10544 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10545 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10547 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10548 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10549 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10550 (match_operand 4 "" "g")))
10551 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10552 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10553 UNSPEC_TLSGD)
10554 (clobber (reg:SI LR_REGNO))]
10555 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10556 {
10557 if (TARGET_CMODEL != CMODEL_SMALL)
10558 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10559 "bl %z3\;nop";
10560 else
10561 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10562 }
10563 "&& TARGET_TLS_MARKERS"
10564 [(set (match_dup 0)
10565 (unspec:TLSmode [(match_dup 1)
10566 (match_dup 2)]
10567 UNSPEC_TLSGD))
10568 (parallel [(set (match_dup 0)
10569 (call (mem:TLSmode (match_dup 3))
10570 (match_dup 4)))
10571 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10572 (clobber (reg:SI LR_REGNO))])]
10573 ""
10574 [(set_attr "type" "two")
10575 (set (attr "length")
10576 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10577 (const_int 16)
10578 (const_int 12)))])
10580 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10581 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10582 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10583 (match_operand 4 "" "g")))
10584 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10585 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10586 UNSPEC_TLSGD)
10587 (clobber (reg:SI LR_REGNO))]
10588 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10589 {
10590 if (flag_pic)
10591 {
10592 if (TARGET_SECURE_PLT && flag_pic == 2)
10593 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10594 else
10595 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10596 }
10597 else
10598 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10599 }
10600 "&& TARGET_TLS_MARKERS"
10601 [(set (match_dup 0)
10602 (unspec:TLSmode [(match_dup 1)
10603 (match_dup 2)]
10604 UNSPEC_TLSGD))
10605 (parallel [(set (match_dup 0)
10606 (call (mem:TLSmode (match_dup 3))
10607 (match_dup 4)))
10608 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10609 (clobber (reg:SI LR_REGNO))])]
10610 ""
10611 [(set_attr "type" "two")
10612 (set_attr "length" "8")])
10614 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10615 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10616 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10617 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10618 UNSPEC_TLSGD))]
10619 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10620 "addi %0,%1,%2@got@tlsgd"
10621 "&& TARGET_CMODEL != CMODEL_SMALL"
10622 [(set (match_dup 3)
10623 (high:TLSmode
10624 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10625 (set (match_dup 0)
10626 (lo_sum:TLSmode (match_dup 3)
10627 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
10628 "
10629 {
10630 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10631 }"
10632 [(set (attr "length")
10633 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10634 (const_int 8)
10635 (const_int 4)))])
10637 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10638 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10639 (high:TLSmode
10640 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10641 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10642 UNSPEC_TLSGD)))]
10643 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10644 "addis %0,%1,%2@got@tlsgd@ha"
10645 [(set_attr "length" "4")])
10647 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10648 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10649 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10650 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10651 UNSPEC_TLSGD)))]
10652 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10653 "addi %0,%1,%2@got@tlsgd@l"
10654 [(set_attr "length" "4")])
10656 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10657 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10658 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10659 (match_operand 2 "" "g")))
10660 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10661 UNSPEC_TLSGD)
10662 (clobber (reg:SI LR_REGNO))]
10663 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10664 "bl %z1(%3@tlsgd)\;nop"
10665 [(set_attr "type" "branch")
10666 (set_attr "length" "8")])
10668 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10669 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10670 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10671 (match_operand 2 "" "g")))
10672 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10673 UNSPEC_TLSGD)
10674 (clobber (reg:SI LR_REGNO))]
10675 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10676 {
10677 if (flag_pic)
10678 {
10679 if (TARGET_SECURE_PLT && flag_pic == 2)
10680 return "bl %z1+32768(%3@tlsgd)@plt";
10681 return "bl %z1(%3@tlsgd)@plt";
10682 }
10683 return "bl %z1(%3@tlsgd)";
10684 }
10685 [(set_attr "type" "branch")
10686 (set_attr "length" "4")])
10688 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10689 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10690 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10691 (match_operand 3 "" "g")))
10692 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10693 UNSPEC_TLSLD)
10694 (clobber (reg:SI LR_REGNO))]
10695 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10696 {
10697 if (TARGET_CMODEL != CMODEL_SMALL)
10698 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10699 "bl %z2\;nop";
10700 else
10701 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10702 }
10703 "&& TARGET_TLS_MARKERS"
10704 [(set (match_dup 0)
10705 (unspec:TLSmode [(match_dup 1)]
10706 UNSPEC_TLSLD))
10707 (parallel [(set (match_dup 0)
10708 (call (mem:TLSmode (match_dup 2))
10709 (match_dup 3)))
10710 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10711 (clobber (reg:SI LR_REGNO))])]
10712 ""
10713 [(set_attr "type" "two")
10714 (set (attr "length")
10715 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10716 (const_int 16)
10717 (const_int 12)))])
10719 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10720 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10721 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10722 (match_operand 3 "" "g")))
10723 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10724 UNSPEC_TLSLD)
10725 (clobber (reg:SI LR_REGNO))]
10726 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10727 {
10728 if (flag_pic)
10729 {
10730 if (TARGET_SECURE_PLT && flag_pic == 2)
10731 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10732 else
10733 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10734 }
10735 else
10736 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10737 }
10738 "&& TARGET_TLS_MARKERS"
10739 [(set (match_dup 0)
10740 (unspec:TLSmode [(match_dup 1)]
10741 UNSPEC_TLSLD))
10742 (parallel [(set (match_dup 0)
10743 (call (mem:TLSmode (match_dup 2))
10744 (match_dup 3)))
10745 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10746 (clobber (reg:SI LR_REGNO))])]
10747 ""
10748 [(set_attr "length" "8")])
10750 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10751 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10752 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10753 UNSPEC_TLSLD))]
10754 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10755 "addi %0,%1,%&@got@tlsld"
10756 "&& TARGET_CMODEL != CMODEL_SMALL"
10757 [(set (match_dup 2)
10758 (high:TLSmode
10759 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10760 (set (match_dup 0)
10761 (lo_sum:TLSmode (match_dup 2)
10762 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
10763 "
10764 {
10765 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10766 }"
10767 [(set (attr "length")
10768 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10769 (const_int 8)
10770 (const_int 4)))])
10772 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10773 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10774 (high:TLSmode
10775 (unspec:TLSmode [(const_int 0)
10776 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10777 UNSPEC_TLSLD)))]
10778 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10779 "addis %0,%1,%&@got@tlsld@ha"
10780 [(set_attr "length" "4")])
10782 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10783 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10784 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10785 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
10786 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10787 "addi %0,%1,%&@got@tlsld@l"
10788 [(set_attr "length" "4")])
10790 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10791 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10792 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10793 (match_operand 2 "" "g")))
10794 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10795 (clobber (reg:SI LR_REGNO))]
10796 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10797 "bl %z1(%&@tlsld)\;nop"
10798 [(set_attr "type" "branch")
10799 (set_attr "length" "8")])
10801 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10802 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10803 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10804 (match_operand 2 "" "g")))
10805 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10806 (clobber (reg:SI LR_REGNO))]
10807 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10808 {
10809 if (flag_pic)
10810 {
10811 if (TARGET_SECURE_PLT && flag_pic == 2)
10812 return "bl %z1+32768(%&@tlsld)@plt";
10813 return "bl %z1(%&@tlsld)@plt";
10814 }
10815 return "bl %z1(%&@tlsld)";
10816 }
10817 [(set_attr "type" "branch")
10818 (set_attr "length" "4")])
10820 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10821 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10822 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10823 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10824 UNSPEC_TLSDTPREL))]
10825 "HAVE_AS_TLS"
10826 "addi %0,%1,%2@dtprel")
10828 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10829 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10830 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10831 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10832 UNSPEC_TLSDTPRELHA))]
10833 "HAVE_AS_TLS"
10834 "addis %0,%1,%2@dtprel@ha")
10836 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10837 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10838 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10839 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10840 UNSPEC_TLSDTPRELLO))]
10841 "HAVE_AS_TLS"
10842 "addi %0,%1,%2@dtprel@l")
10844 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10845 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10846 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10847 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10848 UNSPEC_TLSGOTDTPREL))]
10849 "HAVE_AS_TLS"
10850 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10851 "&& TARGET_CMODEL != CMODEL_SMALL"
10852 [(set (match_dup 3)
10853 (high:TLSmode
10854 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10855 (set (match_dup 0)
10856 (lo_sum:TLSmode (match_dup 3)
10857 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10858 "
10859 {
10860 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10861 }"
10862 [(set (attr "length")
10863 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10864 (const_int 8)
10865 (const_int 4)))])
10867 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10868 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10869 (high:TLSmode
10870 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10871 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10872 UNSPEC_TLSGOTDTPREL)))]
10873 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10874 "addis %0,%1,%2@got@dtprel@ha"
10875 [(set_attr "length" "4")])
10877 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10878 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10879 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10880 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10881 UNSPEC_TLSGOTDTPREL)))]
10882 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10883 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10884 [(set_attr "length" "4")])
10886 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10887 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10888 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10889 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10890 UNSPEC_TLSTPREL))]
10891 "HAVE_AS_TLS"
10892 "addi %0,%1,%2@tprel")
10894 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10895 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10896 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10897 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10898 UNSPEC_TLSTPRELHA))]
10899 "HAVE_AS_TLS"
10900 "addis %0,%1,%2@tprel@ha")
10902 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10903 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10904 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10905 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10906 UNSPEC_TLSTPRELLO))]
10907 "HAVE_AS_TLS"
10908 "addi %0,%1,%2@tprel@l")
10910 ;; "b" output constraint here and on tls_tls input to support linker tls
10911 ;; optimization. The linker may edit the instructions emitted by a
10912 ;; tls_got_tprel/tls_tls pair to addis,addi.
10913 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10914 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10915 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10916 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10917 UNSPEC_TLSGOTTPREL))]
10918 "HAVE_AS_TLS"
10919 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10920 "&& TARGET_CMODEL != CMODEL_SMALL"
10921 [(set (match_dup 3)
10922 (high:TLSmode
10923 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10924 (set (match_dup 0)
10925 (lo_sum:TLSmode (match_dup 3)
10926 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10927 "
10928 {
10929 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10930 }"
10931 [(set (attr "length")
10932 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10933 (const_int 8)
10934 (const_int 4)))])
10936 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10937 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10938 (high:TLSmode
10939 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10940 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10941 UNSPEC_TLSGOTTPREL)))]
10942 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10943 "addis %0,%1,%2@got@tprel@ha"
10944 [(set_attr "length" "4")])
10946 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10947 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10948 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10949 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10950 UNSPEC_TLSGOTTPREL)))]
10951 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10952 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10953 [(set_attr "length" "4")])
10955 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10956 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10957 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10958 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10959 UNSPEC_TLSTLS))]
10960 "TARGET_ELF && HAVE_AS_TLS"
10961 "add %0,%1,%2@tls")
10963 (define_expand "tls_get_tpointer"
10964 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10965 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10966 "TARGET_XCOFF && HAVE_AS_TLS"
10967 "
10968 {
10969 emit_insn (gen_tls_get_tpointer_internal ());
10970 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10971 DONE;
10972 }")
10974 (define_insn "tls_get_tpointer_internal"
10975 [(set (reg:SI 3)
10976 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10977 (clobber (reg:SI LR_REGNO))]
10978 "TARGET_XCOFF && HAVE_AS_TLS"
10979 "bla __get_tpointer")
10981 (define_expand "tls_get_addr<mode>"
10982 [(set (match_operand:P 0 "gpc_reg_operand" "")
10983 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10984 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10985 "TARGET_XCOFF && HAVE_AS_TLS"
10986 "
10987 {
10988 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10989 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10990 emit_insn (gen_tls_get_addr_internal<mode> ());
10991 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10992 DONE;
10993 }")
10995 (define_insn "tls_get_addr_internal<mode>"
10996 [(set (reg:P 3)
10997 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10998 (clobber (reg:P 0))
10999 (clobber (reg:P 4))
11000 (clobber (reg:P 5))
11001 (clobber (reg:P 11))
11002 (clobber (reg:CC CR0_REGNO))
11003 (clobber (reg:P LR_REGNO))]
11004 "TARGET_XCOFF && HAVE_AS_TLS"
11005 "bla __tls_get_addr")
11006 \f
11007 ;; Next come insns related to the calling sequence.
11008 ;;
11009 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11010 ;; We move the back-chain and decrement the stack pointer.
11012 (define_expand "allocate_stack"
11013 [(set (match_operand 0 "gpc_reg_operand" "")
11014 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11015 (set (reg 1)
11016 (minus (reg 1) (match_dup 1)))]
11017 ""
11018 "
11019 { rtx chain = gen_reg_rtx (Pmode);
11020 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11021 rtx neg_op0;
11022 rtx insn, par, set, mem;
11024 emit_move_insn (chain, stack_bot);
11026 /* Check stack bounds if necessary. */
11027 if (crtl->limit_stack)
11028 {
11029 rtx available;
11030 available = expand_binop (Pmode, sub_optab,
11031 stack_pointer_rtx, stack_limit_rtx,
11032 NULL_RTX, 1, OPTAB_WIDEN);
11033 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11034 }
11036 if (GET_CODE (operands[1]) != CONST_INT
11037 || INTVAL (operands[1]) < -32767
11038 || INTVAL (operands[1]) > 32768)
11039 {
11040 neg_op0 = gen_reg_rtx (Pmode);
11041 if (TARGET_32BIT)
11042 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11043 else
11044 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11045 }
11046 else
11047 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11049 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11050 : gen_movdi_di_update_stack))
11051 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11052 chain));
11053 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11054 it now and set the alias set/attributes. The above gen_*_update
11055 calls will generate a PARALLEL with the MEM set being the first
11056 operation. */
11057 par = PATTERN (insn);
11058 gcc_assert (GET_CODE (par) == PARALLEL);
11059 set = XVECEXP (par, 0, 0);
11060 gcc_assert (GET_CODE (set) == SET);
11061 mem = SET_DEST (set);
11062 gcc_assert (MEM_P (mem));
11063 MEM_NOTRAP_P (mem) = 1;
11064 set_mem_alias_set (mem, get_frame_alias_set ());
11066 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11067 DONE;
11068 }")
11070 ;; These patterns say how to save and restore the stack pointer. We need not
11071 ;; save the stack pointer at function level since we are careful to
11072 ;; preserve the backchain. At block level, we have to restore the backchain
11073 ;; when we restore the stack pointer.
11074 ;;
11075 ;; For nonlocal gotos, we must save both the stack pointer and its
11076 ;; backchain and restore both. Note that in the nonlocal case, the
11077 ;; save area is a memory location.
11079 (define_expand "save_stack_function"
11080 [(match_operand 0 "any_operand" "")
11081 (match_operand 1 "any_operand" "")]
11082 ""
11083 "DONE;")
11085 (define_expand "restore_stack_function"
11086 [(match_operand 0 "any_operand" "")
11087 (match_operand 1 "any_operand" "")]
11088 ""
11089 "DONE;")
11091 ;; Adjust stack pointer (op0) to a new value (op1).
11092 ;; First copy old stack backchain to new location, and ensure that the
11093 ;; scheduler won't reorder the sp assignment before the backchain write.
11094 (define_expand "restore_stack_block"
11095 [(set (match_dup 2) (match_dup 3))
11096 (set (match_dup 4) (match_dup 2))
11097 (match_dup 5)
11098 (set (match_operand 0 "register_operand" "")
11099 (match_operand 1 "register_operand" ""))]
11100 ""
11101 "
11102 {
11103 rtvec p;
11105 operands[1] = force_reg (Pmode, operands[1]);
11106 operands[2] = gen_reg_rtx (Pmode);
11107 operands[3] = gen_frame_mem (Pmode, operands[0]);
11108 operands[4] = gen_frame_mem (Pmode, operands[1]);
11109 p = rtvec_alloc (1);
11110 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11111 gen_frame_mem (BLKmode, operands[0]),
11112 const0_rtx);
11113 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11114 }")
11116 (define_expand "save_stack_nonlocal"
11117 [(set (match_dup 3) (match_dup 4))
11118 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11119 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11120 ""
11121 "
11122 {
11123 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11125 /* Copy the backchain to the first word, sp to the second. */
11126 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11127 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11128 operands[3] = gen_reg_rtx (Pmode);
11129 operands[4] = gen_frame_mem (Pmode, operands[1]);
11130 }")
11132 (define_expand "restore_stack_nonlocal"
11133 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11134 (set (match_dup 3) (match_dup 4))
11135 (set (match_dup 5) (match_dup 2))
11136 (match_dup 6)
11137 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11138 ""
11139 "
11140 {
11141 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11142 rtvec p;
11144 /* Restore the backchain from the first word, sp from the second. */
11145 operands[2] = gen_reg_rtx (Pmode);
11146 operands[3] = gen_reg_rtx (Pmode);
11147 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11148 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11149 operands[5] = gen_frame_mem (Pmode, operands[3]);
11150 p = rtvec_alloc (1);
11151 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11152 gen_frame_mem (BLKmode, operands[0]),
11153 const0_rtx);
11154 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11155 }")
11156 \f
11157 ;; TOC register handling.
11159 ;; Code to initialize the TOC register...
11161 (define_insn "load_toc_aix_si"
11162 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11163 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11164 (use (reg:SI 2))])]
11165 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11166 "*
11167 {
11168 char buf[30];
11169 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11170 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11171 operands[2] = gen_rtx_REG (Pmode, 2);
11172 return \"lwz %0,%1(%2)\";
11173 }"
11174 [(set_attr "type" "load")])
11176 (define_insn "load_toc_aix_di"
11177 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11178 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11179 (use (reg:DI 2))])]
11180 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11181 "*
11182 {
11183 char buf[30];
11184 #ifdef TARGET_RELOCATABLE
11185 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11186 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11187 #else
11188 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11189 #endif
11190 if (TARGET_ELF)
11191 strcat (buf, \"@toc\");
11192 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11193 operands[2] = gen_rtx_REG (Pmode, 2);
11194 return \"ld %0,%1(%2)\";
11195 }"
11196 [(set_attr "type" "load")])
11198 (define_insn "load_toc_v4_pic_si"
11199 [(set (reg:SI LR_REGNO)
11200 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11201 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11202 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11203 [(set_attr "type" "branch")
11204 (set_attr "length" "4")])
11206 (define_expand "load_toc_v4_PIC_1"
11207 [(parallel [(set (reg:SI LR_REGNO)
11208 (match_operand:SI 0 "immediate_operand" "s"))
11209 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11210 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11211 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11212 "")
11214 (define_insn "load_toc_v4_PIC_1_normal"
11215 [(set (reg:SI LR_REGNO)
11216 (match_operand:SI 0 "immediate_operand" "s"))
11217 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11218 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
11219 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11220 "bcl 20,31,%0\\n%0:"
11221 [(set_attr "type" "branch")
11222 (set_attr "length" "4")])
11224 (define_insn "load_toc_v4_PIC_1_476"
11225 [(set (reg:SI LR_REGNO)
11226 (match_operand:SI 0 "immediate_operand" "s"))
11227 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11228 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
11229 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11230 "*
11231 {
11232 char name[32];
11233 static char templ[32];
11235 get_ppc476_thunk_name (name);
11236 sprintf (templ, \"bl %s\\n%%0:\", name);
11237 return templ;
11238 }"
11239 [(set_attr "type" "branch")
11240 (set_attr "length" "4")])
11242 (define_expand "load_toc_v4_PIC_1b"
11243 [(parallel [(set (reg:SI LR_REGNO)
11244 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11245 (label_ref (match_operand 1 "" ""))]
11246 UNSPEC_TOCPTR))
11247 (match_dup 1)])]
11248 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11249 "")
11251 (define_insn "load_toc_v4_PIC_1b_normal"
11252 [(set (reg:SI LR_REGNO)
11253 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11254 (label_ref (match_operand 1 "" ""))]
11255 UNSPEC_TOCPTR))
11256 (match_dup 1)]
11257 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11258 "bcl 20,31,$+8\;.long %0-$"
11259 [(set_attr "type" "branch")
11260 (set_attr "length" "8")])
11262 (define_insn "load_toc_v4_PIC_1b_476"
11263 [(set (reg:SI LR_REGNO)
11264 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11265 (label_ref (match_operand 1 "" ""))]
11266 UNSPEC_TOCPTR))
11267 (match_dup 1)]
11268 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11269 "*
11270 {
11271 char name[32];
11272 static char templ[32];
11274 get_ppc476_thunk_name (name);
11275 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11276 return templ;
11277 }"
11278 [(set_attr "type" "branch")
11279 (set_attr "length" "16")])
11281 (define_insn "load_toc_v4_PIC_2"
11282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11283 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11284 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11285 (match_operand:SI 3 "immediate_operand" "s")))))]
11286 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11287 "lwz %0,%2-%3(%1)"
11288 [(set_attr "type" "load")])
11290 (define_insn "load_toc_v4_PIC_3b"
11291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11292 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11293 (high:SI
11294 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11295 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11296 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11297 "addis %0,%1,%2-%3@ha")
11299 (define_insn "load_toc_v4_PIC_3c"
11300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11301 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11302 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11303 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11304 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11305 "addi %0,%1,%2-%3@l")
11307 ;; If the TOC is shared over a translation unit, as happens with all
11308 ;; the kinds of PIC that we support, we need to restore the TOC
11309 ;; pointer only when jumping over units of translation.
11310 ;; On Darwin, we need to reload the picbase.
11312 (define_expand "builtin_setjmp_receiver"
11313 [(use (label_ref (match_operand 0 "" "")))]
11314 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11315 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11316 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11317 "
11318 {
11319 #if TARGET_MACHO
11320 if (DEFAULT_ABI == ABI_DARWIN)
11321 {
11322 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11323 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11324 rtx tmplabrtx;
11325 char tmplab[20];
11327 crtl->uses_pic_offset_table = 1;
11328 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11329 CODE_LABEL_NUMBER (operands[0]));
11330 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11332 emit_insn (gen_load_macho_picbase (tmplabrtx));
11333 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11334 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11335 }
11336 else
11337 #endif
11338 rs6000_emit_load_toc_table (FALSE);
11339 DONE;
11340 }")
11342 ;; Largetoc support
11343 (define_insn "*largetoc_high"
11344 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11345 (high:DI
11346 (unspec [(match_operand:DI 1 "" "")
11347 (match_operand:DI 2 "gpc_reg_operand" "b")]
11348 UNSPEC_TOCREL)))]
11349 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11350 "addis %0,%2,%1@toc@ha")
11352 (define_insn "*largetoc_high_aix<mode>"
11353 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11354 (high:P
11355 (unspec [(match_operand:P 1 "" "")
11356 (match_operand:P 2 "gpc_reg_operand" "b")]
11357 UNSPEC_TOCREL)))]
11358 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11359 "addis %0,%1@u(%2)")
11361 (define_insn "*largetoc_high_plus"
11362 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11363 (high:DI
11364 (plus:DI
11365 (unspec [(match_operand:DI 1 "" "")
11366 (match_operand:DI 2 "gpc_reg_operand" "b")]
11367 UNSPEC_TOCREL)
11368 (match_operand 3 "const_int_operand" "n"))))]
11369 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11370 "addis %0,%2,%1+%3@toc@ha")
11372 (define_insn "*largetoc_high_plus_aix<mode>"
11373 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11374 (high:P
11375 (plus:P
11376 (unspec [(match_operand:P 1 "" "")
11377 (match_operand:P 2 "gpc_reg_operand" "b")]
11378 UNSPEC_TOCREL)
11379 (match_operand 3 "const_int_operand" "n"))))]
11380 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11381 "addis %0,%1+%3@u(%2)")
11383 (define_insn "*largetoc_low"
11384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11385 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
11386 (match_operand:DI 2 "" "")))]
11387 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11388 "@
11389 addi %0,%1,%2@l
11390 addic %0,%1,%2@l")
11392 (define_insn "*largetoc_low_aix<mode>"
11393 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11394 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
11395 (match_operand:P 2 "" "")))]
11396 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11397 "la %0,%2@l(%1)")
11399 (define_insn_and_split "*tocref<mode>"
11400 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11401 (match_operand:P 1 "small_toc_ref" "R"))]
11402 "TARGET_TOC"
11403 "la %0,%a1"
11404 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11405 [(set (match_dup 0) (high:P (match_dup 1)))
11406 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
11408 ;; Elf specific ways of loading addresses for non-PIC code.
11409 ;; The output of this could be r0, but we make a very strong
11410 ;; preference for a base register because it will usually
11411 ;; be needed there.
11412 (define_insn "elf_high"
11413 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11414 (high:SI (match_operand 1 "" "")))]
11415 "TARGET_ELF && ! TARGET_64BIT"
11416 "lis %0,%1@ha")
11418 (define_insn "elf_low"
11419 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11420 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11421 (match_operand 2 "" "")))]
11422 "TARGET_ELF && ! TARGET_64BIT"
11423 "@
11424 la %0,%2@l(%1)
11425 addic %0,%1,%K2")
11426 \f
11427 ;; Call and call_value insns
11428 (define_expand "call"
11429 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11430 (match_operand 1 "" ""))
11431 (use (match_operand 2 "" ""))
11432 (clobber (reg:SI LR_REGNO))])]
11433 ""
11434 "
11435 {
11436 #if TARGET_MACHO
11437 if (MACHOPIC_INDIRECT)
11438 operands[0] = machopic_indirect_call_target (operands[0]);
11439 #endif
11441 gcc_assert (GET_CODE (operands[0]) == MEM);
11442 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11444 operands[0] = XEXP (operands[0], 0);
11446 if (GET_CODE (operands[0]) != SYMBOL_REF
11447 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11448 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11449 {
11450 if (INTVAL (operands[2]) & CALL_LONG)
11451 operands[0] = rs6000_longcall_ref (operands[0]);
11453 switch (DEFAULT_ABI)
11454 {
11455 case ABI_V4:
11456 case ABI_DARWIN:
11457 operands[0] = force_reg (Pmode, operands[0]);
11458 break;
11460 case ABI_AIX:
11461 /* AIX function pointers are really pointers to a three word
11462 area. */
11463 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
11464 DONE;
11466 default:
11467 gcc_unreachable ();
11468 }
11469 }
11470 }")
11472 (define_expand "call_value"
11473 [(parallel [(set (match_operand 0 "" "")
11474 (call (mem:SI (match_operand 1 "address_operand" ""))
11475 (match_operand 2 "" "")))
11476 (use (match_operand 3 "" ""))
11477 (clobber (reg:SI LR_REGNO))])]
11478 ""
11479 "
11480 {
11481 #if TARGET_MACHO
11482 if (MACHOPIC_INDIRECT)
11483 operands[1] = machopic_indirect_call_target (operands[1]);
11484 #endif
11486 gcc_assert (GET_CODE (operands[1]) == MEM);
11487 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11489 operands[1] = XEXP (operands[1], 0);
11491 if (GET_CODE (operands[1]) != SYMBOL_REF
11492 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11493 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11494 {
11495 if (INTVAL (operands[3]) & CALL_LONG)
11496 operands[1] = rs6000_longcall_ref (operands[1]);
11498 switch (DEFAULT_ABI)
11499 {
11500 case ABI_V4:
11501 case ABI_DARWIN:
11502 operands[1] = force_reg (Pmode, operands[1]);
11503 break;
11505 case ABI_AIX:
11506 /* AIX function pointers are really pointers to a three word
11507 area. */
11508 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
11509 DONE;
11511 default:
11512 gcc_unreachable ();
11513 }
11514 }
11515 }")
11517 ;; Call to function in current module. No TOC pointer reload needed.
11518 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11519 ;; either the function was not prototyped, or it was prototyped as a
11520 ;; variable argument function. It is > 0 if FP registers were passed
11521 ;; and < 0 if they were not.
11523 (define_insn "*call_local32"
11524 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11525 (match_operand 1 "" "g,g"))
11526 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11527 (clobber (reg:SI LR_REGNO))]
11528 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11529 "*
11530 {
11531 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11532 output_asm_insn (\"crxor 6,6,6\", operands);
11534 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11535 output_asm_insn (\"creqv 6,6,6\", operands);
11537 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11538 }"
11539 [(set_attr "type" "branch")
11540 (set_attr "length" "4,8")])
11542 (define_insn "*call_local64"
11543 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11544 (match_operand 1 "" "g,g"))
11545 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11546 (clobber (reg:SI LR_REGNO))]
11547 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11548 "*
11549 {
11550 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11551 output_asm_insn (\"crxor 6,6,6\", operands);
11553 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11554 output_asm_insn (\"creqv 6,6,6\", operands);
11556 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11557 }"
11558 [(set_attr "type" "branch")
11559 (set_attr "length" "4,8")])
11561 (define_insn "*call_value_local32"
11562 [(set (match_operand 0 "" "")
11563 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11564 (match_operand 2 "" "g,g")))
11565 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11566 (clobber (reg:SI LR_REGNO))]
11567 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11568 "*
11569 {
11570 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11571 output_asm_insn (\"crxor 6,6,6\", operands);
11573 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11574 output_asm_insn (\"creqv 6,6,6\", operands);
11576 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11577 }"
11578 [(set_attr "type" "branch")
11579 (set_attr "length" "4,8")])
11582 (define_insn "*call_value_local64"
11583 [(set (match_operand 0 "" "")
11584 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11585 (match_operand 2 "" "g,g")))
11586 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11587 (clobber (reg:SI LR_REGNO))]
11588 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11589 "*
11590 {
11591 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11592 output_asm_insn (\"crxor 6,6,6\", operands);
11594 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11595 output_asm_insn (\"creqv 6,6,6\", operands);
11597 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11598 }"
11599 [(set_attr "type" "branch")
11600 (set_attr "length" "4,8")])
11602 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11603 ;; Operand0 is the addresss of the function to call
11604 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11605 ;; Operand2 is the location in the function descriptor to load r2 from
11606 ;; Operand3 is the stack location to hold the current TOC pointer
11608 (define_insn "call_indirect_aix<ptrsize>"
11609 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11610 (match_operand 1 "" "g,g"))
11611 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11612 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11613 (use (reg:P STATIC_CHAIN_REGNUM))
11614 (clobber (reg:P LR_REGNO))]
11615 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11616 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11617 [(set_attr "type" "jmpreg")
11618 (set_attr "length" "12")])
11620 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
11621 ;; Operand0 is the addresss of the function to call
11622 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11623 ;; Operand2 is the location in the function descriptor to load r2 from
11624 ;; Operand3 is the stack location to hold the current TOC pointer
11626 (define_insn "call_indirect_aix<ptrsize>_nor11"
11627 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11628 (match_operand 1 "" "g,g"))
11629 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11630 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11631 (clobber (reg:P LR_REGNO))]
11632 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11633 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11634 [(set_attr "type" "jmpreg")
11635 (set_attr "length" "12")])
11637 ;; Operand0 is the return result of the function
11638 ;; Operand1 is the addresss of the function to call
11639 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11640 ;; Operand3 is the location in the function descriptor to load r2 from
11641 ;; Operand4 is the stack location to hold the current TOC pointer
11643 (define_insn "call_value_indirect_aix<ptrsize>"
11644 [(set (match_operand 0 "" "")
11645 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11646 (match_operand 2 "" "g,g")))
11647 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11648 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11649 (use (reg:P STATIC_CHAIN_REGNUM))
11650 (clobber (reg:P LR_REGNO))]
11651 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11652 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11653 [(set_attr "type" "jmpreg")
11654 (set_attr "length" "12")])
11656 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
11657 ;; Operand0 is the return result of the function
11658 ;; Operand1 is the addresss of the function to call
11659 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11660 ;; Operand3 is the location in the function descriptor to load r2 from
11661 ;; Operand4 is the stack location to hold the current TOC pointer
11663 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
11664 [(set (match_operand 0 "" "")
11665 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11666 (match_operand 2 "" "g,g")))
11667 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11668 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11669 (clobber (reg:P LR_REGNO))]
11670 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11671 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11672 [(set_attr "type" "jmpreg")
11673 (set_attr "length" "12")])
11675 ;; Call to function which may be in another module. Restore the TOC
11676 ;; pointer (r2) after the call unless this is System V.
11677 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11678 ;; either the function was not prototyped, or it was prototyped as a
11679 ;; variable argument function. It is > 0 if FP registers were passed
11680 ;; and < 0 if they were not.
11682 (define_insn "*call_nonlocal_aix32"
11683 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11684 (match_operand 1 "" "g"))
11685 (use (match_operand:SI 2 "immediate_operand" "O"))
11686 (clobber (reg:SI LR_REGNO))]
11687 "TARGET_32BIT
11688 && DEFAULT_ABI == ABI_AIX
11689 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11690 "bl %z0\;nop"
11691 [(set_attr "type" "branch")
11692 (set_attr "length" "8")])
11694 (define_insn "*call_nonlocal_aix64"
11695 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11696 (match_operand 1 "" "g"))
11697 (use (match_operand:SI 2 "immediate_operand" "O"))
11698 (clobber (reg:SI LR_REGNO))]
11699 "TARGET_64BIT
11700 && DEFAULT_ABI == ABI_AIX
11701 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11702 "bl %z0\;nop"
11703 [(set_attr "type" "branch")
11704 (set_attr "length" "8")])
11706 (define_insn "*call_value_nonlocal_aix32"
11707 [(set (match_operand 0 "" "")
11708 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11709 (match_operand 2 "" "g")))
11710 (use (match_operand:SI 3 "immediate_operand" "O"))
11711 (clobber (reg:SI LR_REGNO))]
11712 "TARGET_32BIT
11713 && DEFAULT_ABI == ABI_AIX
11714 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11715 "bl %z1\;nop"
11716 [(set_attr "type" "branch")
11717 (set_attr "length" "8")])
11719 (define_insn "*call_value_nonlocal_aix64"
11720 [(set (match_operand 0 "" "")
11721 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11722 (match_operand 2 "" "g")))
11723 (use (match_operand:SI 3 "immediate_operand" "O"))
11724 (clobber (reg:SI LR_REGNO))]
11725 "TARGET_64BIT
11726 && DEFAULT_ABI == ABI_AIX
11727 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11728 "bl %z1\;nop"
11729 [(set_attr "type" "branch")
11730 (set_attr "length" "8")])
11732 ;; A function pointer under System V is just a normal pointer
11733 ;; operands[0] is the function pointer
11734 ;; operands[1] is the stack size to clean up
11735 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11736 ;; which indicates how to set cr1
11738 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11739 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11740 (match_operand 1 "" "g,g,g,g"))
11741 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11742 (clobber (reg:SI LR_REGNO))]
11743 "DEFAULT_ABI == ABI_V4
11744 || DEFAULT_ABI == ABI_DARWIN"
11745 {
11746 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11747 output_asm_insn ("crxor 6,6,6", operands);
11749 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11750 output_asm_insn ("creqv 6,6,6", operands);
11752 return "b%T0l";
11753 }
11754 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11755 (set_attr "length" "4,4,8,8")])
11757 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11758 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11759 (match_operand 1 "" "g,g"))
11760 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11761 (clobber (reg:SI LR_REGNO))]
11762 "(DEFAULT_ABI == ABI_DARWIN
11763 || (DEFAULT_ABI == ABI_V4
11764 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11765 {
11766 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11767 output_asm_insn ("crxor 6,6,6", operands);
11769 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11770 output_asm_insn ("creqv 6,6,6", operands);
11772 #if TARGET_MACHO
11773 return output_call(insn, operands, 0, 2);
11774 #else
11775 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11776 {
11777 gcc_assert (!TARGET_SECURE_PLT);
11778 return "bl %z0@plt";
11779 }
11780 else
11781 return "bl %z0";
11782 #endif
11783 }
11784 "DEFAULT_ABI == ABI_V4
11785 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11786 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11787 [(parallel [(call (mem:SI (match_dup 0))
11788 (match_dup 1))
11789 (use (match_dup 2))
11790 (use (match_dup 3))
11791 (clobber (reg:SI LR_REGNO))])]
11792 {
11793 operands[3] = pic_offset_table_rtx;
11794 }
11795 [(set_attr "type" "branch,branch")
11796 (set_attr "length" "4,8")])
11798 (define_insn "*call_nonlocal_sysv_secure<mode>"
11799 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11800 (match_operand 1 "" "g,g"))
11801 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11802 (use (match_operand:SI 3 "register_operand" "r,r"))
11803 (clobber (reg:SI LR_REGNO))]
11804 "(DEFAULT_ABI == ABI_V4
11805 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11806 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11807 {
11808 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11809 output_asm_insn ("crxor 6,6,6", operands);
11811 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11812 output_asm_insn ("creqv 6,6,6", operands);
11814 if (flag_pic == 2)
11815 /* The magic 32768 offset here and in the other sysv call insns
11816 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11817 See sysv4.h:toc_section. */
11818 return "bl %z0+32768@plt";
11819 else
11820 return "bl %z0@plt";
11821 }
11822 [(set_attr "type" "branch,branch")
11823 (set_attr "length" "4,8")])
11825 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11826 [(set (match_operand 0 "" "")
11827 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11828 (match_operand 2 "" "g,g,g,g")))
11829 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11830 (clobber (reg:SI LR_REGNO))]
11831 "DEFAULT_ABI == ABI_V4
11832 || DEFAULT_ABI == ABI_DARWIN"
11833 {
11834 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11835 output_asm_insn ("crxor 6,6,6", operands);
11837 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11838 output_asm_insn ("creqv 6,6,6", operands);
11840 return "b%T1l";
11841 }
11842 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11843 (set_attr "length" "4,4,8,8")])
11845 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11846 [(set (match_operand 0 "" "")
11847 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11848 (match_operand 2 "" "g,g")))
11849 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11850 (clobber (reg:SI LR_REGNO))]
11851 "(DEFAULT_ABI == ABI_DARWIN
11852 || (DEFAULT_ABI == ABI_V4
11853 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11854 {
11855 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11856 output_asm_insn ("crxor 6,6,6", operands);
11858 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11859 output_asm_insn ("creqv 6,6,6", operands);
11861 #if TARGET_MACHO
11862 return output_call(insn, operands, 1, 3);
11863 #else
11864 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11865 {
11866 gcc_assert (!TARGET_SECURE_PLT);
11867 return "bl %z1@plt";
11868 }
11869 else
11870 return "bl %z1";
11871 #endif
11872 }
11873 "DEFAULT_ABI == ABI_V4
11874 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11875 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11876 [(parallel [(set (match_dup 0)
11877 (call (mem:SI (match_dup 1))
11878 (match_dup 2)))
11879 (use (match_dup 3))
11880 (use (match_dup 4))
11881 (clobber (reg:SI LR_REGNO))])]
11882 {
11883 operands[4] = pic_offset_table_rtx;
11884 }
11885 [(set_attr "type" "branch,branch")
11886 (set_attr "length" "4,8")])
11888 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11889 [(set (match_operand 0 "" "")
11890 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11891 (match_operand 2 "" "g,g")))
11892 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11893 (use (match_operand:SI 4 "register_operand" "r,r"))
11894 (clobber (reg:SI LR_REGNO))]
11895 "(DEFAULT_ABI == ABI_V4
11896 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11897 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11898 {
11899 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11900 output_asm_insn ("crxor 6,6,6", operands);
11902 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11903 output_asm_insn ("creqv 6,6,6", operands);
11905 if (flag_pic == 2)
11906 return "bl %z1+32768@plt";
11907 else
11908 return "bl %z1@plt";
11909 }
11910 [(set_attr "type" "branch,branch")
11911 (set_attr "length" "4,8")])
11913 ;; Call subroutine returning any type.
11914 (define_expand "untyped_call"
11915 [(parallel [(call (match_operand 0 "" "")
11916 (const_int 0))
11917 (match_operand 1 "" "")
11918 (match_operand 2 "" "")])]
11919 ""
11920 "
11921 {
11922 int i;
11924 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11926 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11927 {
11928 rtx set = XVECEXP (operands[2], 0, i);
11929 emit_move_insn (SET_DEST (set), SET_SRC (set));
11930 }
11932 /* The optimizer does not know that the call sets the function value
11933 registers we stored in the result block. We avoid problems by
11934 claiming that all hard registers are used and clobbered at this
11935 point. */
11936 emit_insn (gen_blockage ());
11938 DONE;
11939 }")
11941 ;; sibling call patterns
11942 (define_expand "sibcall"
11943 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11944 (match_operand 1 "" ""))
11945 (use (match_operand 2 "" ""))
11946 (use (reg:SI LR_REGNO))
11947 (simple_return)])]
11948 ""
11949 "
11950 {
11951 #if TARGET_MACHO
11952 if (MACHOPIC_INDIRECT)
11953 operands[0] = machopic_indirect_call_target (operands[0]);
11954 #endif
11956 gcc_assert (GET_CODE (operands[0]) == MEM);
11957 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11959 operands[0] = XEXP (operands[0], 0);
11960 }")
11962 ;; this and similar patterns must be marked as using LR, otherwise
11963 ;; dataflow will try to delete the store into it. This is true
11964 ;; even when the actual reg to jump to is in CTR, when LR was
11965 ;; saved and restored around the PIC-setting BCL.
11966 (define_insn "*sibcall_local32"
11967 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11968 (match_operand 1 "" "g,g"))
11969 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11970 (use (reg:SI LR_REGNO))
11971 (simple_return)]
11972 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11973 "*
11974 {
11975 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11976 output_asm_insn (\"crxor 6,6,6\", operands);
11978 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11979 output_asm_insn (\"creqv 6,6,6\", operands);
11981 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11982 }"
11983 [(set_attr "type" "branch")
11984 (set_attr "length" "4,8")])
11986 (define_insn "*sibcall_local64"
11987 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11988 (match_operand 1 "" "g,g"))
11989 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11990 (use (reg:SI LR_REGNO))
11991 (simple_return)]
11992 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11993 "*
11994 {
11995 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11996 output_asm_insn (\"crxor 6,6,6\", operands);
11998 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11999 output_asm_insn (\"creqv 6,6,6\", operands);
12001 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12002 }"
12003 [(set_attr "type" "branch")
12004 (set_attr "length" "4,8")])
12006 (define_insn "*sibcall_value_local32"
12007 [(set (match_operand 0 "" "")
12008 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12009 (match_operand 2 "" "g,g")))
12010 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12011 (use (reg:SI LR_REGNO))
12012 (simple_return)]
12013 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12014 "*
12015 {
12016 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12017 output_asm_insn (\"crxor 6,6,6\", operands);
12019 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12020 output_asm_insn (\"creqv 6,6,6\", operands);
12022 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12023 }"
12024 [(set_attr "type" "branch")
12025 (set_attr "length" "4,8")])
12028 (define_insn "*sibcall_value_local64"
12029 [(set (match_operand 0 "" "")
12030 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12031 (match_operand 2 "" "g,g")))
12032 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12033 (use (reg:SI LR_REGNO))
12034 (simple_return)]
12035 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12036 "*
12037 {
12038 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12039 output_asm_insn (\"crxor 6,6,6\", operands);
12041 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12042 output_asm_insn (\"creqv 6,6,6\", operands);
12044 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12045 }"
12046 [(set_attr "type" "branch")
12047 (set_attr "length" "4,8")])
12049 (define_insn "*sibcall_nonlocal_aix<mode>"
12050 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12051 (match_operand 1 "" "g,g"))
12052 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12053 (use (reg:SI LR_REGNO))
12054 (simple_return)]
12055 "DEFAULT_ABI == ABI_AIX
12056 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12057 "@
12058 b %z0
12059 b%T0"
12060 [(set_attr "type" "branch")
12061 (set_attr "length" "4")])
12063 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12064 [(set (match_operand 0 "" "")
12065 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12066 (match_operand 2 "" "g,g")))
12067 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12068 (use (reg:SI LR_REGNO))
12069 (simple_return)]
12070 "DEFAULT_ABI == ABI_AIX
12071 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12072 "@
12073 b %z1
12074 b%T1"
12075 [(set_attr "type" "branch")
12076 (set_attr "length" "4")])
12078 (define_insn "*sibcall_nonlocal_sysv<mode>"
12079 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12080 (match_operand 1 "" ""))
12081 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12082 (use (reg:SI LR_REGNO))
12083 (simple_return)]
12084 "(DEFAULT_ABI == ABI_DARWIN
12085 || DEFAULT_ABI == ABI_V4)
12086 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12087 "*
12088 {
12089 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12090 output_asm_insn (\"crxor 6,6,6\", operands);
12092 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12093 output_asm_insn (\"creqv 6,6,6\", operands);
12095 if (which_alternative >= 2)
12096 return \"b%T0\";
12097 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12098 {
12099 gcc_assert (!TARGET_SECURE_PLT);
12100 return \"b %z0@plt\";
12101 }
12102 else
12103 return \"b %z0\";
12104 }"
12105 [(set_attr "type" "branch")
12106 (set_attr "length" "4,8,4,8")])
12108 (define_expand "sibcall_value"
12109 [(parallel [(set (match_operand 0 "register_operand" "")
12110 (call (mem:SI (match_operand 1 "address_operand" ""))
12111 (match_operand 2 "" "")))
12112 (use (match_operand 3 "" ""))
12113 (use (reg:SI LR_REGNO))
12114 (simple_return)])]
12115 ""
12116 "
12117 {
12118 #if TARGET_MACHO
12119 if (MACHOPIC_INDIRECT)
12120 operands[1] = machopic_indirect_call_target (operands[1]);
12121 #endif
12123 gcc_assert (GET_CODE (operands[1]) == MEM);
12124 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12126 operands[1] = XEXP (operands[1], 0);
12127 }")
12129 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12130 [(set (match_operand 0 "" "")
12131 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12132 (match_operand 2 "" "")))
12133 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12134 (use (reg:SI LR_REGNO))
12135 (simple_return)]
12136 "(DEFAULT_ABI == ABI_DARWIN
12137 || DEFAULT_ABI == ABI_V4)
12138 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12139 "*
12140 {
12141 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12142 output_asm_insn (\"crxor 6,6,6\", operands);
12144 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12145 output_asm_insn (\"creqv 6,6,6\", operands);
12147 if (which_alternative >= 2)
12148 return \"b%T1\";
12149 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12150 {
12151 gcc_assert (!TARGET_SECURE_PLT);
12152 return \"b %z1@plt\";
12153 }
12154 else
12155 return \"b %z1\";
12156 }"
12157 [(set_attr "type" "branch")
12158 (set_attr "length" "4,8,4,8")])
12160 (define_expand "sibcall_epilogue"
12161 [(use (const_int 0))]
12162 ""
12163 {
12164 if (!TARGET_SCHED_PROLOG)
12165 emit_insn (gen_blockage ());
12166 rs6000_emit_epilogue (TRUE);
12167 DONE;
12168 })
12170 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12171 ;; all of memory. This blocks insns from being moved across this point.
12173 (define_insn "blockage"
12174 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12175 ""
12176 "")
12178 (define_expand "probe_stack"
12179 [(set (match_operand 0 "memory_operand" "=m")
12180 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12181 ""
12182 {
12183 if (TARGET_64BIT)
12184 emit_insn (gen_probe_stack_di (operands[0]));
12185 else
12186 emit_insn (gen_probe_stack_si (operands[0]));
12187 DONE;
12188 })
12190 (define_insn "probe_stack_<mode>"
12191 [(set (match_operand:P 0 "memory_operand" "=m")
12192 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12193 ""
12194 {
12195 operands[1] = gen_rtx_REG (Pmode, 0);
12196 return "st<wd>%U0%X0 %1,%0";
12197 }
12198 [(set (attr "type")
12199 (if_then_else
12200 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
12201 (const_string "store_ux")
12202 (if_then_else
12203 (match_test "update_address_mem (operands[0], VOIDmode)")
12204 (const_string "store_u")
12205 (const_string "store"))))
12206 (set_attr "length" "4")])
12208 (define_insn "probe_stack_range<P:mode>"
12209 [(set (match_operand:P 0 "register_operand" "=r")
12210 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12211 (match_operand:P 2 "register_operand" "r")]
12212 UNSPECV_PROBE_STACK_RANGE))]
12213 ""
12214 "* return output_probe_stack_range (operands[0], operands[2]);"
12215 [(set_attr "type" "three")])
12216 \f
12217 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12218 ;; signed & unsigned, and one type of branch.
12219 ;;
12220 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12221 ;; insns, and branches.
12223 (define_expand "cbranch<mode>4"
12224 [(use (match_operator 0 "rs6000_cbranch_operator"
12225 [(match_operand:GPR 1 "gpc_reg_operand" "")
12226 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12227 (use (match_operand 3 ""))]
12228 ""
12229 "
12230 {
12231 /* Take care of the possibility that operands[2] might be negative but
12232 this might be a logical operation. That insn doesn't exist. */
12233 if (GET_CODE (operands[2]) == CONST_INT
12234 && INTVAL (operands[2]) < 0)
12235 {
12236 operands[2] = force_reg (<MODE>mode, operands[2]);
12237 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12238 GET_MODE (operands[0]),
12239 operands[1], operands[2]);
12240 }
12242 rs6000_emit_cbranch (<MODE>mode, operands);
12243 DONE;
12244 }")
12246 (define_expand "cbranch<mode>4"
12247 [(use (match_operator 0 "rs6000_cbranch_operator"
12248 [(match_operand:FP 1 "gpc_reg_operand" "")
12249 (match_operand:FP 2 "gpc_reg_operand" "")]))
12250 (use (match_operand 3 ""))]
12251 ""
12252 "
12253 {
12254 rs6000_emit_cbranch (<MODE>mode, operands);
12255 DONE;
12256 }")
12258 (define_expand "cstore<mode>4"
12259 [(use (match_operator 1 "rs6000_cbranch_operator"
12260 [(match_operand:GPR 2 "gpc_reg_operand" "")
12261 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12262 (clobber (match_operand:SI 0 "register_operand"))]
12263 ""
12264 "
12265 {
12266 /* Take care of the possibility that operands[3] might be negative but
12267 this might be a logical operation. That insn doesn't exist. */
12268 if (GET_CODE (operands[3]) == CONST_INT
12269 && INTVAL (operands[3]) < 0)
12270 {
12271 operands[3] = force_reg (<MODE>mode, operands[3]);
12272 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12273 GET_MODE (operands[1]),
12274 operands[2], operands[3]);
12275 }
12277 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12278 For SEQ, likewise, except that comparisons with zero should be done
12279 with an scc insns. However, due to the order that combine see the
12280 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12281 the cases we don't want to handle or are best handled by portable
12282 code. */
12283 if (GET_CODE (operands[1]) == NE)
12284 FAIL;
12285 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12286 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12287 && operands[3] == const0_rtx)
12288 FAIL;
12289 rs6000_emit_sCOND (<MODE>mode, operands);
12290 DONE;
12291 }")
12293 (define_expand "cstore<mode>4"
12294 [(use (match_operator 1 "rs6000_cbranch_operator"
12295 [(match_operand:FP 2 "gpc_reg_operand" "")
12296 (match_operand:FP 3 "gpc_reg_operand" "")]))
12297 (clobber (match_operand:SI 0 "register_operand"))]
12298 ""
12299 "
12300 {
12301 rs6000_emit_sCOND (<MODE>mode, operands);
12302 DONE;
12303 }")
12306 (define_expand "stack_protect_set"
12307 [(match_operand 0 "memory_operand" "")
12308 (match_operand 1 "memory_operand" "")]
12309 ""
12310 {
12311 #ifdef TARGET_THREAD_SSP_OFFSET
12312 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12313 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12314 operands[1] = gen_rtx_MEM (Pmode, addr);
12315 #endif
12316 if (TARGET_64BIT)
12317 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12318 else
12319 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12320 DONE;
12321 })
12323 (define_insn "stack_protect_setsi"
12324 [(set (match_operand:SI 0 "memory_operand" "=m")
12325 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12326 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12327 "TARGET_32BIT"
12328 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12329 [(set_attr "type" "three")
12330 (set_attr "length" "12")])
12332 (define_insn "stack_protect_setdi"
12333 [(set (match_operand:DI 0 "memory_operand" "=Y")
12334 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12335 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12336 "TARGET_64BIT"
12337 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12338 [(set_attr "type" "three")
12339 (set_attr "length" "12")])
12341 (define_expand "stack_protect_test"
12342 [(match_operand 0 "memory_operand" "")
12343 (match_operand 1 "memory_operand" "")
12344 (match_operand 2 "" "")]
12345 ""
12346 {
12347 rtx test, op0, op1;
12348 #ifdef TARGET_THREAD_SSP_OFFSET
12349 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12350 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12351 operands[1] = gen_rtx_MEM (Pmode, addr);
12352 #endif
12353 op0 = operands[0];
12354 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12355 test = gen_rtx_EQ (VOIDmode, op0, op1);
12356 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12357 DONE;
12358 })
12360 (define_insn "stack_protect_testsi"
12361 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12362 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12363 (match_operand:SI 2 "memory_operand" "m,m")]
12364 UNSPEC_SP_TEST))
12365 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12366 (clobber (match_scratch:SI 3 "=&r,&r"))]
12367 "TARGET_32BIT"
12368 "@
12369 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12370 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12371 [(set_attr "length" "16,20")])
12373 (define_insn "stack_protect_testdi"
12374 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12375 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12376 (match_operand:DI 2 "memory_operand" "Y,Y")]
12377 UNSPEC_SP_TEST))
12378 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12379 (clobber (match_scratch:DI 3 "=&r,&r"))]
12380 "TARGET_64BIT"
12381 "@
12382 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12383 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12384 [(set_attr "length" "16,20")])
12386 \f
12387 ;; Here are the actual compare insns.
12388 (define_insn "*cmp<mode>_internal1"
12389 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12390 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12391 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12392 ""
12393 "cmp<wd>%I2 %0,%1,%2"
12394 [(set_attr "type" "cmp")])
12396 ;; If we are comparing a register for equality with a large constant,
12397 ;; we can do this with an XOR followed by a compare. But this is profitable
12398 ;; only if the large constant is only used for the comparison (and in this
12399 ;; case we already have a register to reuse as scratch).
12400 ;;
12401 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12402 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12404 (define_peephole2
12405 [(set (match_operand:SI 0 "register_operand")
12406 (match_operand:SI 1 "logical_const_operand" ""))
12407 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12408 [(match_dup 0)
12409 (match_operand:SI 2 "logical_const_operand" "")]))
12410 (set (match_operand:CC 4 "cc_reg_operand" "")
12411 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12412 (match_dup 0)))
12413 (set (pc)
12414 (if_then_else (match_operator 6 "equality_operator"
12415 [(match_dup 4) (const_int 0)])
12416 (match_operand 7 "" "")
12417 (match_operand 8 "" "")))]
12418 "peep2_reg_dead_p (3, operands[0])
12419 && peep2_reg_dead_p (4, operands[4])"
12420 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12421 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12422 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12424 {
12425 /* Get the constant we are comparing against, and see what it looks like
12426 when sign-extended from 16 to 32 bits. Then see what constant we could
12427 XOR with SEXTC to get the sign-extended value. */
12428 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12429 SImode,
12430 operands[1], operands[2]);
12431 HOST_WIDE_INT c = INTVAL (cnst);
12432 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12433 HOST_WIDE_INT xorv = c ^ sextc;
12435 operands[9] = GEN_INT (xorv);
12436 operands[10] = GEN_INT (sextc);
12437 })
12439 (define_insn "*cmpsi_internal2"
12440 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12441 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12442 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12443 ""
12444 "cmplw%I2 %0,%1,%b2"
12445 [(set_attr "type" "cmp")])
12447 (define_insn "*cmpdi_internal2"
12448 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12449 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12450 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12451 ""
12452 "cmpld%I2 %0,%1,%b2"
12453 [(set_attr "type" "cmp")])
12455 ;; The following two insns don't exist as single insns, but if we provide
12456 ;; them, we can swap an add and compare, which will enable us to overlap more
12457 ;; of the required delay between a compare and branch. We generate code for
12458 ;; them by splitting.
12460 (define_insn ""
12461 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12462 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12463 (match_operand:SI 2 "short_cint_operand" "i")))
12464 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12465 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12466 ""
12467 "#"
12468 [(set_attr "length" "8")])
12470 (define_insn ""
12471 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12472 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12473 (match_operand:SI 2 "u_short_cint_operand" "i")))
12474 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12475 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12476 ""
12477 "#"
12478 [(set_attr "length" "8")])
12480 (define_split
12481 [(set (match_operand:CC 3 "cc_reg_operand" "")
12482 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12483 (match_operand:SI 2 "short_cint_operand" "")))
12484 (set (match_operand:SI 0 "gpc_reg_operand" "")
12485 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12486 ""
12487 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12488 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12490 (define_split
12491 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12492 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12493 (match_operand:SI 2 "u_short_cint_operand" "")))
12494 (set (match_operand:SI 0 "gpc_reg_operand" "")
12495 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12496 ""
12497 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12498 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12500 (define_insn "*cmpsf_internal1"
12501 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12502 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12503 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12504 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12505 "fcmpu %0,%1,%2"
12506 [(set_attr "type" "fpcompare")])
12508 (define_insn "*cmpdf_internal1"
12509 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12510 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12511 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12512 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12513 && !VECTOR_UNIT_VSX_P (DFmode)"
12514 "fcmpu %0,%1,%2"
12515 [(set_attr "type" "fpcompare")])
12517 ;; Only need to compare second words if first words equal
12518 (define_insn "*cmptf_internal1"
12519 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12520 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12521 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12522 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12523 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12524 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12525 [(set_attr "type" "fpcompare")
12526 (set_attr "length" "12")])
12528 (define_insn_and_split "*cmptf_internal2"
12529 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12530 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12531 (match_operand:TF 2 "gpc_reg_operand" "d")))
12532 (clobber (match_scratch:DF 3 "=d"))
12533 (clobber (match_scratch:DF 4 "=d"))
12534 (clobber (match_scratch:DF 5 "=d"))
12535 (clobber (match_scratch:DF 6 "=d"))
12536 (clobber (match_scratch:DF 7 "=d"))
12537 (clobber (match_scratch:DF 8 "=d"))
12538 (clobber (match_scratch:DF 9 "=d"))
12539 (clobber (match_scratch:DF 10 "=d"))
12540 (clobber (match_scratch:GPR 11 "=b"))]
12541 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12542 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12543 "#"
12544 "&& reload_completed"
12545 [(set (match_dup 3) (match_dup 14))
12546 (set (match_dup 4) (match_dup 15))
12547 (set (match_dup 9) (abs:DF (match_dup 5)))
12548 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12549 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12550 (label_ref (match_dup 12))
12551 (pc)))
12552 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12553 (set (pc) (label_ref (match_dup 13)))
12554 (match_dup 12)
12555 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12556 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12557 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12558 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12559 (match_dup 13)]
12560 {
12561 REAL_VALUE_TYPE rv;
12562 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12563 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12565 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12566 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12567 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12568 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12569 operands[12] = gen_label_rtx ();
12570 operands[13] = gen_label_rtx ();
12571 real_inf (&rv);
12572 operands[14] = force_const_mem (DFmode,
12573 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12574 operands[15] = force_const_mem (DFmode,
12575 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12576 DFmode));
12577 if (TARGET_TOC)
12578 {
12579 rtx tocref;
12580 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12581 operands[14] = gen_const_mem (DFmode, tocref);
12582 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12583 operands[15] = gen_const_mem (DFmode, tocref);
12584 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12585 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12586 }
12587 })
12588 \f
12589 ;; Now we have the scc insns. We can do some combinations because of the
12590 ;; way the machine works.
12591 ;;
12592 ;; Note that this is probably faster if we can put an insn between the
12593 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12594 ;; cases the insns below which don't use an intermediate CR field will
12595 ;; be used instead.
12596 (define_insn ""
12597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12598 (match_operator:SI 1 "scc_comparison_operator"
12599 [(match_operand 2 "cc_reg_operand" "y")
12600 (const_int 0)]))]
12601 ""
12602 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12603 [(set (attr "type")
12604 (cond [(match_test "TARGET_MFCRF")
12605 (const_string "mfcrf")
12606 ]
12607 (const_string "mfcr")))
12608 (set_attr "length" "8")])
12610 ;; Same as above, but get the GT bit.
12611 (define_insn "move_from_CR_gt_bit"
12612 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12613 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12614 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12615 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12616 [(set_attr "type" "mfcr")
12617 (set_attr "length" "8")])
12619 ;; Same as above, but get the OV/ORDERED bit.
12620 (define_insn "move_from_CR_ov_bit"
12621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12622 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
12623 UNSPEC_MV_CR_OV))]
12624 "TARGET_ISEL"
12625 "mfcr %0\;rlwinm %0,%0,%t1,1"
12626 [(set_attr "type" "mfcr")
12627 (set_attr "length" "8")])
12629 (define_insn ""
12630 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12631 (match_operator:DI 1 "scc_comparison_operator"
12632 [(match_operand 2 "cc_reg_operand" "y")
12633 (const_int 0)]))]
12634 "TARGET_POWERPC64"
12635 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12636 [(set (attr "type")
12637 (cond [(match_test "TARGET_MFCRF")
12638 (const_string "mfcrf")
12639 ]
12640 (const_string "mfcr")))
12641 (set_attr "length" "8")])
12643 (define_insn ""
12644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12645 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12646 [(match_operand 2 "cc_reg_operand" "y,y")
12647 (const_int 0)])
12648 (const_int 0)))
12649 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12650 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12651 "TARGET_32BIT"
12652 "@
12653 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
12654 #"
12655 [(set_attr "type" "delayed_compare")
12656 (set_attr "length" "8,16")])
12658 (define_split
12659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12660 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12661 [(match_operand 2 "cc_reg_operand" "")
12662 (const_int 0)])
12663 (const_int 0)))
12664 (set (match_operand:SI 3 "gpc_reg_operand" "")
12665 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12666 "TARGET_32BIT && reload_completed"
12667 [(set (match_dup 3)
12668 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12669 (set (match_dup 0)
12670 (compare:CC (match_dup 3)
12671 (const_int 0)))]
12672 "")
12674 (define_insn ""
12675 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12676 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12677 [(match_operand 2 "cc_reg_operand" "y")
12678 (const_int 0)])
12679 (match_operand:SI 3 "const_int_operand" "n")))]
12680 ""
12681 "*
12682 {
12683 int is_bit = ccr_bit (operands[1], 1);
12684 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12685 int count;
12687 if (is_bit >= put_bit)
12688 count = is_bit - put_bit;
12689 else
12690 count = 32 - (put_bit - is_bit);
12692 operands[4] = GEN_INT (count);
12693 operands[5] = GEN_INT (put_bit);
12695 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
12696 }"
12697 [(set (attr "type")
12698 (cond [(match_test "TARGET_MFCRF")
12699 (const_string "mfcrf")
12700 ]
12701 (const_string "mfcr")))
12702 (set_attr "length" "8")])
12704 (define_insn ""
12705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12706 (compare:CC
12707 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12708 [(match_operand 2 "cc_reg_operand" "y,y")
12709 (const_int 0)])
12710 (match_operand:SI 3 "const_int_operand" "n,n"))
12711 (const_int 0)))
12712 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12713 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12714 (match_dup 3)))]
12715 ""
12716 "*
12717 {
12718 int is_bit = ccr_bit (operands[1], 1);
12719 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12720 int count;
12722 /* Force split for non-cc0 compare. */
12723 if (which_alternative == 1)
12724 return \"#\";
12726 if (is_bit >= put_bit)
12727 count = is_bit - put_bit;
12728 else
12729 count = 32 - (put_bit - is_bit);
12731 operands[5] = GEN_INT (count);
12732 operands[6] = GEN_INT (put_bit);
12734 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12735 }"
12736 [(set_attr "type" "delayed_compare")
12737 (set_attr "length" "8,16")])
12739 (define_split
12740 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12741 (compare:CC
12742 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12743 [(match_operand 2 "cc_reg_operand" "")
12744 (const_int 0)])
12745 (match_operand:SI 3 "const_int_operand" ""))
12746 (const_int 0)))
12747 (set (match_operand:SI 4 "gpc_reg_operand" "")
12748 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12749 (match_dup 3)))]
12750 "reload_completed"
12751 [(set (match_dup 4)
12752 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12753 (match_dup 3)))
12754 (set (match_dup 0)
12755 (compare:CC (match_dup 4)
12756 (const_int 0)))]
12757 "")
12759 ;; There is a 3 cycle delay between consecutive mfcr instructions
12760 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12762 (define_peephole
12763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12764 (match_operator:SI 1 "scc_comparison_operator"
12765 [(match_operand 2 "cc_reg_operand" "y")
12766 (const_int 0)]))
12767 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12768 (match_operator:SI 4 "scc_comparison_operator"
12769 [(match_operand 5 "cc_reg_operand" "y")
12770 (const_int 0)]))]
12771 "REGNO (operands[2]) != REGNO (operands[5])"
12772 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12773 [(set_attr "type" "mfcr")
12774 (set_attr "length" "12")])
12776 (define_peephole
12777 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12778 (match_operator:DI 1 "scc_comparison_operator"
12779 [(match_operand 2 "cc_reg_operand" "y")
12780 (const_int 0)]))
12781 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12782 (match_operator:DI 4 "scc_comparison_operator"
12783 [(match_operand 5 "cc_reg_operand" "y")
12784 (const_int 0)]))]
12785 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12786 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12787 [(set_attr "type" "mfcr")
12788 (set_attr "length" "12")])
12790 ;; There are some scc insns that can be done directly, without a compare.
12791 ;; These are faster because they don't involve the communications between
12792 ;; the FXU and branch units. In fact, we will be replacing all of the
12793 ;; integer scc insns here or in the portable methods in emit_store_flag.
12794 ;;
12795 ;; Also support (neg (scc ..)) since that construct is used to replace
12796 ;; branches, (plus (scc ..) ..) since that construct is common and
12797 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12798 ;; cases where it is no more expensive than (neg (scc ..)).
12800 ;; Have reload force a constant into a register for the simple insns that
12801 ;; otherwise won't accept constants. We do this because it is faster than
12802 ;; the cmp/mfcr sequence we would otherwise generate.
12804 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12805 (DI "rKJI")])
12807 (define_insn_and_split "*eq<mode>"
12808 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12809 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12810 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12811 ""
12812 "#"
12813 ""
12814 [(set (match_dup 0)
12815 (clz:GPR (match_dup 3)))
12816 (set (match_dup 0)
12817 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12818 {
12819 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12820 {
12821 /* Use output operand as intermediate. */
12822 operands[3] = operands[0];
12824 if (logical_operand (operands[2], <MODE>mode))
12825 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12826 gen_rtx_XOR (<MODE>mode,
12827 operands[1], operands[2])));
12828 else
12829 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12830 gen_rtx_PLUS (<MODE>mode, operands[1],
12831 negate_rtx (<MODE>mode,
12832 operands[2]))));
12833 }
12834 else
12835 operands[3] = operands[1];
12837 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12838 })
12840 (define_insn_and_split "*eq<mode>_compare"
12841 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12842 (compare:CC
12843 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12844 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12845 (const_int 0)))
12846 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12847 (eq:P (match_dup 1) (match_dup 2)))]
12848 "optimize_size"
12849 "#"
12850 "optimize_size"
12851 [(set (match_dup 0)
12852 (clz:P (match_dup 4)))
12853 (parallel [(set (match_dup 3)
12854 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12855 (const_int 0)))
12856 (set (match_dup 0)
12857 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12858 {
12859 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12860 {
12861 /* Use output operand as intermediate. */
12862 operands[4] = operands[0];
12864 if (logical_operand (operands[2], <MODE>mode))
12865 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12866 gen_rtx_XOR (<MODE>mode,
12867 operands[1], operands[2])));
12868 else
12869 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12870 gen_rtx_PLUS (<MODE>mode, operands[1],
12871 negate_rtx (<MODE>mode,
12872 operands[2]))));
12873 }
12874 else
12875 operands[4] = operands[1];
12877 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12878 })
12880 ;; We have insns of the form shown by the first define_insn below. If
12881 ;; there is something inside the comparison operation, we must split it.
12882 (define_split
12883 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12884 (plus:SI (match_operator 1 "comparison_operator"
12885 [(match_operand:SI 2 "" "")
12886 (match_operand:SI 3
12887 "reg_or_cint_operand" "")])
12888 (match_operand:SI 4 "gpc_reg_operand" "")))
12889 (clobber (match_operand:SI 5 "register_operand" ""))]
12890 "! gpc_reg_operand (operands[2], SImode)"
12891 [(set (match_dup 5) (match_dup 2))
12892 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12893 (match_dup 4)))])
12895 (define_insn "*plus_eqsi"
12896 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12897 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12898 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12899 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12900 "TARGET_32BIT"
12901 "@
12902 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12903 subfic %0,%1,0\;addze %0,%3
12904 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12905 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12906 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12907 [(set_attr "type" "three,two,three,three,three")
12908 (set_attr "length" "12,8,12,12,12")])
12910 (define_insn "*compare_plus_eqsi"
12911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12912 (compare:CC
12913 (plus:SI
12914 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12915 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12916 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12917 (const_int 0)))
12918 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12919 "TARGET_32BIT && optimize_size"
12920 "@
12921 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12922 subfic %4,%1,0\;addze. %4,%3
12923 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12924 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12925 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12926 #
12927 #
12928 #
12929 #
12930 #"
12931 [(set_attr "type" "compare")
12932 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12934 (define_split
12935 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12936 (compare:CC
12937 (plus:SI
12938 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12939 (match_operand:SI 2 "scc_eq_operand" ""))
12940 (match_operand:SI 3 "gpc_reg_operand" ""))
12941 (const_int 0)))
12942 (clobber (match_scratch:SI 4 ""))]
12943 "TARGET_32BIT && optimize_size && reload_completed"
12944 [(set (match_dup 4)
12945 (plus:SI (eq:SI (match_dup 1)
12946 (match_dup 2))
12947 (match_dup 3)))
12948 (set (match_dup 0)
12949 (compare:CC (match_dup 4)
12950 (const_int 0)))]
12951 "")
12953 (define_insn "*plus_eqsi_compare"
12954 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12955 (compare:CC
12956 (plus:SI
12957 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12958 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12959 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12960 (const_int 0)))
12961 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12962 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12963 "TARGET_32BIT && optimize_size"
12964 "@
12965 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12966 subfic %0,%1,0\;addze. %0,%3
12967 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12968 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12969 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12970 #
12971 #
12972 #
12973 #
12974 #"
12975 [(set_attr "type" "compare")
12976 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12978 (define_split
12979 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12980 (compare:CC
12981 (plus:SI
12982 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12983 (match_operand:SI 2 "scc_eq_operand" ""))
12984 (match_operand:SI 3 "gpc_reg_operand" ""))
12985 (const_int 0)))
12986 (set (match_operand:SI 0 "gpc_reg_operand" "")
12987 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12988 "TARGET_32BIT && optimize_size && reload_completed"
12989 [(set (match_dup 0)
12990 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12991 (set (match_dup 4)
12992 (compare:CC (match_dup 0)
12993 (const_int 0)))]
12994 "")
12996 (define_insn "*neg_eq0<mode>"
12997 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12998 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12999 (const_int 0))))]
13000 ""
13001 "addic %0,%1,-1\;subfe %0,%0,%0"
13002 [(set_attr "type" "two")
13003 (set_attr "length" "8")])
13005 (define_insn_and_split "*neg_eq<mode>"
13006 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13007 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13008 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13009 ""
13010 "#"
13011 ""
13012 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13013 {
13014 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13015 {
13016 /* Use output operand as intermediate. */
13017 operands[3] = operands[0];
13019 if (logical_operand (operands[2], <MODE>mode))
13020 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13021 gen_rtx_XOR (<MODE>mode,
13022 operands[1], operands[2])));
13023 else
13024 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13025 gen_rtx_PLUS (<MODE>mode, operands[1],
13026 negate_rtx (<MODE>mode,
13027 operands[2]))));
13028 }
13029 else
13030 operands[3] = operands[1];
13031 })
13033 (define_insn "*ne0_<mode>"
13034 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13035 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13036 (const_int 0)))
13037 (clobber (match_scratch:P 2 "=&r"))]
13038 "!(TARGET_32BIT && TARGET_ISEL)"
13039 "addic %2,%1,-1\;subfe %0,%2,%1"
13040 [(set_attr "type" "two")
13041 (set_attr "length" "8")])
13043 (define_insn "*plus_ne0_<mode>"
13044 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13045 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13046 (const_int 0))
13047 (match_operand:P 2 "gpc_reg_operand" "r")))
13048 (clobber (match_scratch:P 3 "=&r"))]
13049 ""
13050 "addic %3,%1,-1\;addze %0,%2"
13051 [(set_attr "type" "two")
13052 (set_attr "length" "8")])
13054 (define_insn "*compare_plus_ne0_<mode>"
13055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13056 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13057 (const_int 0))
13058 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13059 (const_int 0)))
13060 (clobber (match_scratch:P 3 "=&r,&r"))
13061 (clobber (match_scratch:P 4 "=X,&r"))]
13062 ""
13063 "@
13064 addic %3,%1,-1\;addze. %3,%2
13065 #"
13066 [(set_attr "type" "compare")
13067 (set_attr "length" "8,12")])
13069 (define_split
13070 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13071 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13072 (const_int 0))
13073 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13074 (clobber (match_scratch:P 3 ""))
13075 (clobber (match_scratch:P 4 ""))]
13076 "reload_completed"
13077 [(parallel [(set (match_dup 3)
13078 (plus:P (ne:P (match_dup 1)
13079 (const_int 0))
13080 (match_dup 2)))
13081 (clobber (match_dup 4))])
13082 (set (match_dup 0)
13083 (compare:CC (match_dup 3)
13084 (const_int 0)))]
13085 "")
13087 ; For combine.
13088 (define_insn "*compare_plus_ne0_<mode>_1"
13089 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13090 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13091 (const_int 0))
13092 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13093 (clobber (match_scratch:P 3 "=&r,&r"))
13094 (clobber (match_scratch:P 4 "=X,&r"))]
13095 ""
13096 "@
13097 addic %3,%1,-1\;addze. %3,%2
13098 #"
13099 [(set_attr "type" "compare")
13100 (set_attr "length" "8,12")])
13102 (define_split
13103 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13104 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13105 (const_int 0))
13106 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13107 (clobber (match_scratch:P 3 ""))
13108 (clobber (match_scratch:P 4 ""))]
13109 "reload_completed"
13110 [(parallel [(set (match_dup 3)
13111 (plus:P (ne:P (match_dup 1)
13112 (const_int 0))
13113 (match_dup 2)))
13114 (clobber (match_dup 4))])
13115 (set (match_dup 0)
13116 (compare:CC (match_dup 3)
13117 (const_int 0)))]
13118 "")
13120 (define_insn "*plus_ne0_<mode>_compare"
13121 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13122 (compare:CC
13123 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13124 (const_int 0))
13125 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13126 (const_int 0)))
13127 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13128 (plus:P (ne:P (match_dup 1)
13129 (const_int 0))
13130 (match_dup 2)))
13131 (clobber (match_scratch:P 3 "=&r,&r"))]
13132 ""
13133 "@
13134 addic %3,%1,-1\;addze. %0,%2
13135 #"
13136 [(set_attr "type" "compare")
13137 (set_attr "length" "8,12")])
13139 (define_split
13140 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13141 (compare:CC
13142 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13143 (const_int 0))
13144 (match_operand:P 2 "gpc_reg_operand" ""))
13145 (const_int 0)))
13146 (set (match_operand:P 0 "gpc_reg_operand" "")
13147 (plus:P (ne:P (match_dup 1)
13148 (const_int 0))
13149 (match_dup 2)))
13150 (clobber (match_scratch:P 3 ""))]
13151 "reload_completed"
13152 [(parallel [(set (match_dup 0)
13153 (plus:P (ne:P (match_dup 1)
13154 (const_int 0))
13155 (match_dup 2)))
13156 (clobber (match_dup 3))])
13157 (set (match_dup 4)
13158 (compare:CC (match_dup 0)
13159 (const_int 0)))]
13160 "")
13162 (define_insn "*leu<mode>"
13163 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13164 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13165 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13166 ""
13167 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13168 [(set_attr "type" "three")
13169 (set_attr "length" "12")])
13171 (define_insn "*leu<mode>_compare"
13172 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13173 (compare:CC
13174 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13175 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13176 (const_int 0)))
13177 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13178 (leu:P (match_dup 1) (match_dup 2)))]
13179 ""
13180 "@
13181 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13182 #"
13183 [(set_attr "type" "compare")
13184 (set_attr "length" "12,16")])
13186 (define_split
13187 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13188 (compare:CC
13189 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13190 (match_operand:P 2 "reg_or_short_operand" ""))
13191 (const_int 0)))
13192 (set (match_operand:P 0 "gpc_reg_operand" "")
13193 (leu:P (match_dup 1) (match_dup 2)))]
13194 "reload_completed"
13195 [(set (match_dup 0)
13196 (leu:P (match_dup 1) (match_dup 2)))
13197 (set (match_dup 3)
13198 (compare:CC (match_dup 0)
13199 (const_int 0)))]
13200 "")
13202 (define_insn "*plus_leu<mode>"
13203 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13204 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13205 (match_operand:P 2 "reg_or_short_operand" "rI"))
13206 (match_operand:P 3 "gpc_reg_operand" "r")))]
13207 ""
13208 "subf%I2c %0,%1,%2\;addze %0,%3"
13209 [(set_attr "type" "two")
13210 (set_attr "length" "8")])
13212 (define_insn ""
13213 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13214 (compare:CC
13215 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13216 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13217 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13218 (const_int 0)))
13219 (clobber (match_scratch:SI 4 "=&r,&r"))]
13220 "TARGET_32BIT"
13221 "@
13222 subf%I2c %4,%1,%2\;addze. %4,%3
13223 #"
13224 [(set_attr "type" "compare")
13225 (set_attr "length" "8,12")])
13227 (define_split
13228 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13229 (compare:CC
13230 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13231 (match_operand:SI 2 "reg_or_short_operand" ""))
13232 (match_operand:SI 3 "gpc_reg_operand" ""))
13233 (const_int 0)))
13234 (clobber (match_scratch:SI 4 ""))]
13235 "TARGET_32BIT && reload_completed"
13236 [(set (match_dup 4)
13237 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13238 (match_dup 3)))
13239 (set (match_dup 0)
13240 (compare:CC (match_dup 4)
13241 (const_int 0)))]
13242 "")
13244 (define_insn ""
13245 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13246 (compare:CC
13247 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13248 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13249 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13250 (const_int 0)))
13251 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13252 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13253 "TARGET_32BIT"
13254 "@
13255 subf%I2c %0,%1,%2\;addze. %0,%3
13256 #"
13257 [(set_attr "type" "compare")
13258 (set_attr "length" "8,12")])
13260 (define_split
13261 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13262 (compare:CC
13263 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13264 (match_operand:SI 2 "reg_or_short_operand" ""))
13265 (match_operand:SI 3 "gpc_reg_operand" ""))
13266 (const_int 0)))
13267 (set (match_operand:SI 0 "gpc_reg_operand" "")
13268 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13269 "TARGET_32BIT && reload_completed"
13270 [(set (match_dup 0)
13271 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13272 (set (match_dup 4)
13273 (compare:CC (match_dup 0)
13274 (const_int 0)))]
13275 "")
13277 (define_insn "*neg_leu<mode>"
13278 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13279 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13280 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13281 ""
13282 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13283 [(set_attr "type" "three")
13284 (set_attr "length" "12")])
13286 (define_insn "*and_neg_leu<mode>"
13287 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13288 (and:P (neg:P
13289 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13290 (match_operand:P 2 "reg_or_short_operand" "rI")))
13291 (match_operand:P 3 "gpc_reg_operand" "r")))]
13292 ""
13293 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13294 [(set_attr "type" "three")
13295 (set_attr "length" "12")])
13297 (define_insn ""
13298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13299 (compare:CC
13300 (and:SI (neg:SI
13301 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13302 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13303 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13304 (const_int 0)))
13305 (clobber (match_scratch:SI 4 "=&r,&r"))]
13306 "TARGET_32BIT"
13307 "@
13308 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13309 #"
13310 [(set_attr "type" "compare")
13311 (set_attr "length" "12,16")])
13313 (define_split
13314 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13315 (compare:CC
13316 (and:SI (neg:SI
13317 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13318 (match_operand:SI 2 "reg_or_short_operand" "")))
13319 (match_operand:SI 3 "gpc_reg_operand" ""))
13320 (const_int 0)))
13321 (clobber (match_scratch:SI 4 ""))]
13322 "TARGET_32BIT && reload_completed"
13323 [(set (match_dup 4)
13324 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13325 (match_dup 3)))
13326 (set (match_dup 0)
13327 (compare:CC (match_dup 4)
13328 (const_int 0)))]
13329 "")
13331 (define_insn ""
13332 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13333 (compare:CC
13334 (and:SI (neg:SI
13335 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13336 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13337 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13338 (const_int 0)))
13339 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13340 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13341 "TARGET_32BIT"
13342 "@
13343 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13344 #"
13345 [(set_attr "type" "compare")
13346 (set_attr "length" "12,16")])
13348 (define_split
13349 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13350 (compare:CC
13351 (and:SI (neg:SI
13352 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13353 (match_operand:SI 2 "reg_or_short_operand" "")))
13354 (match_operand:SI 3 "gpc_reg_operand" ""))
13355 (const_int 0)))
13356 (set (match_operand:SI 0 "gpc_reg_operand" "")
13357 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13358 "TARGET_32BIT && reload_completed"
13359 [(set (match_dup 0)
13360 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13361 (match_dup 3)))
13362 (set (match_dup 4)
13363 (compare:CC (match_dup 0)
13364 (const_int 0)))]
13365 "")
13367 (define_insn_and_split "*ltu<mode>"
13368 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13369 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13370 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13371 ""
13372 "#"
13373 ""
13374 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13375 (set (match_dup 0) (neg:P (match_dup 0)))]
13376 "")
13378 (define_insn_and_split "*ltu<mode>_compare"
13379 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13380 (compare:CC
13381 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13382 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13383 (const_int 0)))
13384 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13385 (ltu:P (match_dup 1) (match_dup 2)))]
13386 ""
13387 "#"
13388 ""
13389 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13390 (parallel [(set (match_dup 3)
13391 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13392 (set (match_dup 0) (neg:P (match_dup 0)))])]
13393 "")
13395 (define_insn_and_split "*plus_ltu<mode>"
13396 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13397 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13398 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13399 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13400 ""
13401 "#"
13402 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13403 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13404 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13405 "")
13407 (define_insn_and_split "*plus_ltu<mode>_compare"
13408 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13409 (compare:CC
13410 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13411 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13412 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13413 (const_int 0)))
13414 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13415 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13416 ""
13417 "#"
13418 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13419 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13420 (parallel [(set (match_dup 4)
13421 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13422 (const_int 0)))
13423 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13424 "")
13426 (define_insn "*neg_ltu<mode>"
13427 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13428 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13429 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13430 ""
13431 "@
13432 subfc %0,%2,%1\;subfe %0,%0,%0
13433 addic %0,%1,%n2\;subfe %0,%0,%0"
13434 [(set_attr "type" "two")
13435 (set_attr "length" "8")])
13437 (define_insn "*geu<mode>"
13438 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13439 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13440 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13441 ""
13442 "@
13443 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13444 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13445 [(set_attr "type" "three")
13446 (set_attr "length" "12")])
13448 (define_insn "*geu<mode>_compare"
13449 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13450 (compare:CC
13451 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13452 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13453 (const_int 0)))
13454 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13455 (geu:P (match_dup 1) (match_dup 2)))]
13456 ""
13457 "@
13458 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13459 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13460 #
13461 #"
13462 [(set_attr "type" "compare")
13463 (set_attr "length" "12,12,16,16")])
13465 (define_split
13466 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13467 (compare:CC
13468 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13469 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13470 (const_int 0)))
13471 (set (match_operand:P 0 "gpc_reg_operand" "")
13472 (geu:P (match_dup 1) (match_dup 2)))]
13473 "reload_completed"
13474 [(set (match_dup 0)
13475 (geu:P (match_dup 1) (match_dup 2)))
13476 (set (match_dup 3)
13477 (compare:CC (match_dup 0)
13478 (const_int 0)))]
13479 "")
13481 (define_insn "*plus_geu<mode>"
13482 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13483 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13484 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13485 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13486 ""
13487 "@
13488 subfc %0,%2,%1\;addze %0,%3
13489 addic %0,%1,%n2\;addze %0,%3"
13490 [(set_attr "type" "two")
13491 (set_attr "length" "8")])
13493 (define_insn ""
13494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13495 (compare:CC
13496 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13497 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13498 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13499 (const_int 0)))
13500 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13501 "TARGET_32BIT"
13502 "@
13503 subfc %4,%2,%1\;addze. %4,%3
13504 addic %4,%1,%n2\;addze. %4,%3
13505 #
13506 #"
13507 [(set_attr "type" "compare")
13508 (set_attr "length" "8,8,12,12")])
13510 (define_split
13511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13512 (compare:CC
13513 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13514 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13515 (match_operand:SI 3 "gpc_reg_operand" ""))
13516 (const_int 0)))
13517 (clobber (match_scratch:SI 4 ""))]
13518 "TARGET_32BIT && reload_completed"
13519 [(set (match_dup 4)
13520 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13521 (match_dup 3)))
13522 (set (match_dup 0)
13523 (compare:CC (match_dup 4)
13524 (const_int 0)))]
13525 "")
13527 (define_insn ""
13528 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13529 (compare:CC
13530 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13531 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13532 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13533 (const_int 0)))
13534 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13535 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13536 "TARGET_32BIT"
13537 "@
13538 subfc %0,%2,%1\;addze. %0,%3
13539 addic %0,%1,%n2\;addze. %0,%3
13540 #
13541 #"
13542 [(set_attr "type" "compare")
13543 (set_attr "length" "8,8,12,12")])
13545 (define_split
13546 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13547 (compare:CC
13548 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13549 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13550 (match_operand:SI 3 "gpc_reg_operand" ""))
13551 (const_int 0)))
13552 (set (match_operand:SI 0 "gpc_reg_operand" "")
13553 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13554 "TARGET_32BIT && reload_completed"
13555 [(set (match_dup 0)
13556 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13557 (set (match_dup 4)
13558 (compare:CC (match_dup 0)
13559 (const_int 0)))]
13560 "")
13562 (define_insn "*neg_geu<mode>"
13563 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13564 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13565 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13566 ""
13567 "@
13568 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
13569 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
13570 [(set_attr "type" "three")
13571 (set_attr "length" "12")])
13573 (define_insn "*and_neg_geu<mode>"
13574 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13575 (and:P (neg:P
13576 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13577 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13578 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13579 ""
13580 "@
13581 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
13582 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
13583 [(set_attr "type" "three")
13584 (set_attr "length" "12")])
13586 (define_insn ""
13587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13588 (compare:CC
13589 (and:SI (neg:SI
13590 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13591 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13592 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13593 (const_int 0)))
13594 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13595 "TARGET_32BIT"
13596 "@
13597 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
13598 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
13599 #
13600 #"
13601 [(set_attr "type" "compare")
13602 (set_attr "length" "12,12,16,16")])
13604 (define_split
13605 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13606 (compare:CC
13607 (and:SI (neg:SI
13608 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13609 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13610 (match_operand:SI 3 "gpc_reg_operand" ""))
13611 (const_int 0)))
13612 (clobber (match_scratch:SI 4 ""))]
13613 "TARGET_32BIT && reload_completed"
13614 [(set (match_dup 4)
13615 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13616 (match_dup 3)))
13617 (set (match_dup 0)
13618 (compare:CC (match_dup 4)
13619 (const_int 0)))]
13620 "")
13622 (define_insn ""
13623 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13624 (compare:CC
13625 (and:SI (neg:SI
13626 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13627 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13628 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13629 (const_int 0)))
13630 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13631 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13632 "TARGET_32BIT"
13633 "@
13634 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
13635 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
13636 #
13637 #"
13638 [(set_attr "type" "compare")
13639 (set_attr "length" "12,12,16,16")])
13641 (define_split
13642 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13643 (compare:CC
13644 (and:SI (neg:SI
13645 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13646 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13647 (match_operand:SI 3 "gpc_reg_operand" ""))
13648 (const_int 0)))
13649 (set (match_operand:SI 0 "gpc_reg_operand" "")
13650 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13651 "TARGET_32BIT && reload_completed"
13652 [(set (match_dup 0)
13653 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13654 (set (match_dup 4)
13655 (compare:CC (match_dup 0)
13656 (const_int 0)))]
13657 "")
13659 (define_insn "*plus_gt0<mode>"
13660 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13661 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13662 (const_int 0))
13663 (match_operand:P 2 "gpc_reg_operand" "r")))]
13664 ""
13665 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13666 [(set_attr "type" "three")
13667 (set_attr "length" "12")])
13669 (define_insn ""
13670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13671 (compare:CC
13672 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13673 (const_int 0))
13674 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13675 (const_int 0)))
13676 (clobber (match_scratch:SI 3 "=&r,&r"))]
13677 "TARGET_32BIT"
13678 "@
13679 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13680 #"
13681 [(set_attr "type" "compare")
13682 (set_attr "length" "12,16")])
13684 (define_split
13685 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13686 (compare:CC
13687 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13688 (const_int 0))
13689 (match_operand:SI 2 "gpc_reg_operand" ""))
13690 (const_int 0)))
13691 (clobber (match_scratch:SI 3 ""))]
13692 "TARGET_32BIT && reload_completed"
13693 [(set (match_dup 3)
13694 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13695 (match_dup 2)))
13696 (set (match_dup 0)
13697 (compare:CC (match_dup 3)
13698 (const_int 0)))]
13699 "")
13701 (define_insn ""
13702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13703 (compare:CC
13704 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13705 (const_int 0))
13706 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13707 (const_int 0)))
13708 (clobber (match_scratch:DI 3 "=&r,&r"))]
13709 "TARGET_64BIT"
13710 "@
13711 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13712 #"
13713 [(set_attr "type" "compare")
13714 (set_attr "length" "12,16")])
13716 (define_split
13717 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13718 (compare:CC
13719 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13720 (const_int 0))
13721 (match_operand:DI 2 "gpc_reg_operand" ""))
13722 (const_int 0)))
13723 (clobber (match_scratch:DI 3 ""))]
13724 "TARGET_64BIT && reload_completed"
13725 [(set (match_dup 3)
13726 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13727 (match_dup 2)))
13728 (set (match_dup 0)
13729 (compare:CC (match_dup 3)
13730 (const_int 0)))]
13731 "")
13733 (define_insn ""
13734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13735 (compare:CC
13736 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13737 (const_int 0))
13738 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13739 (const_int 0)))
13740 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13741 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13742 "TARGET_32BIT"
13743 "@
13744 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13745 #"
13746 [(set_attr "type" "compare")
13747 (set_attr "length" "12,16")])
13749 (define_split
13750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13751 (compare:CC
13752 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13753 (const_int 0))
13754 (match_operand:SI 2 "gpc_reg_operand" ""))
13755 (const_int 0)))
13756 (set (match_operand:SI 0 "gpc_reg_operand" "")
13757 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13758 "TARGET_32BIT && reload_completed"
13759 [(set (match_dup 0)
13760 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13761 (set (match_dup 3)
13762 (compare:CC (match_dup 0)
13763 (const_int 0)))]
13764 "")
13766 (define_insn ""
13767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13768 (compare:CC
13769 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13770 (const_int 0))
13771 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13772 (const_int 0)))
13773 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13774 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13775 "TARGET_64BIT"
13776 "@
13777 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13778 #"
13779 [(set_attr "type" "compare")
13780 (set_attr "length" "12,16")])
13782 (define_split
13783 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13784 (compare:CC
13785 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13786 (const_int 0))
13787 (match_operand:DI 2 "gpc_reg_operand" ""))
13788 (const_int 0)))
13789 (set (match_operand:DI 0 "gpc_reg_operand" "")
13790 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13791 "TARGET_64BIT && reload_completed"
13792 [(set (match_dup 0)
13793 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13794 (set (match_dup 3)
13795 (compare:CC (match_dup 0)
13796 (const_int 0)))]
13797 "")
13799 (define_insn_and_split "*gtu<mode>"
13800 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13801 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13802 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13803 ""
13804 "#"
13805 ""
13806 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13807 (set (match_dup 0) (neg:P (match_dup 0)))]
13808 "")
13810 (define_insn_and_split "*gtu<mode>_compare"
13811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13812 (compare:CC
13813 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13814 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13815 (const_int 0)))
13816 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13817 (gtu:P (match_dup 1) (match_dup 2)))]
13818 ""
13819 "#"
13820 ""
13821 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13822 (parallel [(set (match_dup 3)
13823 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13824 (set (match_dup 0) (neg:P (match_dup 0)))])]
13825 "")
13827 (define_insn_and_split "*plus_gtu<mode>"
13828 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13829 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13830 (match_operand:P 2 "reg_or_short_operand" "rI"))
13831 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13832 ""
13833 "#"
13834 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13835 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13836 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13837 "")
13839 (define_insn_and_split "*plus_gtu<mode>_compare"
13840 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13841 (compare:CC
13842 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13843 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13844 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13845 (const_int 0)))
13846 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13847 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13848 ""
13849 "#"
13850 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13851 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13852 (parallel [(set (match_dup 4)
13853 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13854 (const_int 0)))
13855 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13856 "")
13858 (define_insn "*neg_gtu<mode>"
13859 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13860 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13861 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13862 ""
13863 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13864 [(set_attr "type" "two")
13865 (set_attr "length" "8")])
13867 \f
13868 ;; Define both directions of branch and return. If we need a reload
13869 ;; register, we'd rather use CR0 since it is much easier to copy a
13870 ;; register CC value to there.
13872 (define_insn ""
13873 [(set (pc)
13874 (if_then_else (match_operator 1 "branch_comparison_operator"
13875 [(match_operand 2
13876 "cc_reg_operand" "y")
13877 (const_int 0)])
13878 (label_ref (match_operand 0 "" ""))
13879 (pc)))]
13880 ""
13881 "*
13882 {
13883 return output_cbranch (operands[1], \"%l0\", 0, insn);
13884 }"
13885 [(set_attr "type" "branch")])
13887 (define_insn ""
13888 [(set (pc)
13889 (if_then_else (match_operator 0 "branch_comparison_operator"
13890 [(match_operand 1
13891 "cc_reg_operand" "y")
13892 (const_int 0)])
13893 (any_return)
13894 (pc)))]
13895 "<return_pred>"
13896 "*
13897 {
13898 return output_cbranch (operands[0], NULL, 0, insn);
13899 }"
13900 [(set_attr "type" "jmpreg")
13901 (set_attr "length" "4")])
13903 (define_insn ""
13904 [(set (pc)
13905 (if_then_else (match_operator 1 "branch_comparison_operator"
13906 [(match_operand 2
13907 "cc_reg_operand" "y")
13908 (const_int 0)])
13909 (pc)
13910 (label_ref (match_operand 0 "" ""))))]
13911 ""
13912 "*
13913 {
13914 return output_cbranch (operands[1], \"%l0\", 1, insn);
13915 }"
13916 [(set_attr "type" "branch")])
13918 (define_insn ""
13919 [(set (pc)
13920 (if_then_else (match_operator 0 "branch_comparison_operator"
13921 [(match_operand 1
13922 "cc_reg_operand" "y")
13923 (const_int 0)])
13924 (pc)
13925 (any_return)))]
13926 "<return_pred>"
13927 "*
13928 {
13929 return output_cbranch (operands[0], NULL, 1, insn);
13930 }"
13931 [(set_attr "type" "jmpreg")
13932 (set_attr "length" "4")])
13934 ;; Logic on condition register values.
13936 ; This pattern matches things like
13937 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13938 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13939 ; (const_int 1)))
13940 ; which are generated by the branch logic.
13941 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13943 (define_insn "*cceq_ior_compare"
13944 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13945 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13946 [(match_operator:SI 2
13947 "branch_positive_comparison_operator"
13948 [(match_operand 3
13949 "cc_reg_operand" "y,y")
13950 (const_int 0)])
13951 (match_operator:SI 4
13952 "branch_positive_comparison_operator"
13953 [(match_operand 5
13954 "cc_reg_operand" "0,y")
13955 (const_int 0)])])
13956 (const_int 1)))]
13957 ""
13958 "cr%q1 %E0,%j2,%j4"
13959 [(set_attr "type" "cr_logical,delayed_cr")])
13961 ; Why is the constant -1 here, but 1 in the previous pattern?
13962 ; Because ~1 has all but the low bit set.
13963 (define_insn ""
13964 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13965 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13966 [(not:SI (match_operator:SI 2
13967 "branch_positive_comparison_operator"
13968 [(match_operand 3
13969 "cc_reg_operand" "y,y")
13970 (const_int 0)]))
13971 (match_operator:SI 4
13972 "branch_positive_comparison_operator"
13973 [(match_operand 5
13974 "cc_reg_operand" "0,y")
13975 (const_int 0)])])
13976 (const_int -1)))]
13977 ""
13978 "cr%q1 %E0,%j2,%j4"
13979 [(set_attr "type" "cr_logical,delayed_cr")])
13981 (define_insn "*cceq_rev_compare"
13982 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13983 (compare:CCEQ (match_operator:SI 1
13984 "branch_positive_comparison_operator"
13985 [(match_operand 2
13986 "cc_reg_operand" "0,y")
13987 (const_int 0)])
13988 (const_int 0)))]
13989 ""
13990 "crnot %E0,%j1"
13991 [(set_attr "type" "cr_logical,delayed_cr")])
13993 ;; If we are comparing the result of two comparisons, this can be done
13994 ;; using creqv or crxor.
13996 (define_insn_and_split ""
13997 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13998 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13999 [(match_operand 2 "cc_reg_operand" "y")
14000 (const_int 0)])
14001 (match_operator 3 "branch_comparison_operator"
14002 [(match_operand 4 "cc_reg_operand" "y")
14003 (const_int 0)])))]
14004 ""
14005 "#"
14006 ""
14007 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14008 (match_dup 5)))]
14009 "
14010 {
14011 int positive_1, positive_2;
14013 positive_1 = branch_positive_comparison_operator (operands[1],
14014 GET_MODE (operands[1]));
14015 positive_2 = branch_positive_comparison_operator (operands[3],
14016 GET_MODE (operands[3]));
14018 if (! positive_1)
14019 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14020 GET_CODE (operands[1])),
14021 SImode,
14022 operands[2], const0_rtx);
14023 else if (GET_MODE (operands[1]) != SImode)
14024 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14025 operands[2], const0_rtx);
14027 if (! positive_2)
14028 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14029 GET_CODE (operands[3])),
14030 SImode,
14031 operands[4], const0_rtx);
14032 else if (GET_MODE (operands[3]) != SImode)
14033 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14034 operands[4], const0_rtx);
14036 if (positive_1 == positive_2)
14037 {
14038 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14039 operands[5] = constm1_rtx;
14040 }
14041 else
14042 {
14043 operands[5] = const1_rtx;
14044 }
14045 }")
14047 ;; Unconditional branch and return.
14049 (define_insn "jump"
14050 [(set (pc)
14051 (label_ref (match_operand 0 "" "")))]
14052 ""
14053 "b %l0"
14054 [(set_attr "type" "branch")])
14056 (define_insn "<return_str>return"
14057 [(any_return)]
14058 "<return_pred>"
14059 "blr"
14060 [(set_attr "type" "jmpreg")])
14062 (define_expand "indirect_jump"
14063 [(set (pc) (match_operand 0 "register_operand" ""))])
14065 (define_insn "*indirect_jump<mode>"
14066 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14067 ""
14068 "@
14069 bctr
14070 blr"
14071 [(set_attr "type" "jmpreg")])
14073 ;; Table jump for switch statements:
14074 (define_expand "tablejump"
14075 [(use (match_operand 0 "" ""))
14076 (use (label_ref (match_operand 1 "" "")))]
14077 ""
14078 "
14079 {
14080 if (TARGET_32BIT)
14081 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14082 else
14083 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14084 DONE;
14085 }")
14087 (define_expand "tablejumpsi"
14088 [(set (match_dup 3)
14089 (plus:SI (match_operand:SI 0 "" "")
14090 (match_dup 2)))
14091 (parallel [(set (pc) (match_dup 3))
14092 (use (label_ref (match_operand 1 "" "")))])]
14093 "TARGET_32BIT"
14094 "
14095 { operands[0] = force_reg (SImode, operands[0]);
14096 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14097 operands[3] = gen_reg_rtx (SImode);
14098 }")
14100 (define_expand "tablejumpdi"
14101 [(set (match_dup 4)
14102 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14103 (set (match_dup 3)
14104 (plus:DI (match_dup 4)
14105 (match_dup 2)))
14106 (parallel [(set (pc) (match_dup 3))
14107 (use (label_ref (match_operand 1 "" "")))])]
14108 "TARGET_64BIT"
14109 "
14110 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14111 operands[3] = gen_reg_rtx (DImode);
14112 operands[4] = gen_reg_rtx (DImode);
14113 }")
14115 (define_insn "*tablejump<mode>_internal1"
14116 [(set (pc)
14117 (match_operand:P 0 "register_operand" "c,*l"))
14118 (use (label_ref (match_operand 1 "" "")))]
14119 ""
14120 "@
14121 bctr
14122 blr"
14123 [(set_attr "type" "jmpreg")])
14125 (define_insn "nop"
14126 [(const_int 0)]
14127 ""
14128 "nop")
14130 (define_insn "group_ending_nop"
14131 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14132 ""
14133 "*
14134 {
14135 if (rs6000_cpu_attr == CPU_POWER6)
14136 return \"ori 1,1,0\";
14137 return \"ori 2,2,0\";
14138 }")
14139 \f
14140 ;; Define the subtract-one-and-jump insns, starting with the template
14141 ;; so loop.c knows what to generate.
14143 (define_expand "doloop_end"
14144 [(use (match_operand 0 "" "")) ; loop pseudo
14145 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14146 (use (match_operand 2 "" "")) ; max iterations
14147 (use (match_operand 3 "" "")) ; loop level
14148 (use (match_operand 4 "" "")) ; label
14149 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
14150 ""
14151 "
14152 {
14153 /* Only use this on innermost loops. */
14154 if (INTVAL (operands[3]) > 1)
14155 FAIL;
14156 if (TARGET_64BIT)
14157 {
14158 if (GET_MODE (operands[0]) != DImode)
14159 FAIL;
14160 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14161 }
14162 else
14163 {
14164 if (GET_MODE (operands[0]) != SImode)
14165 FAIL;
14166 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14167 }
14168 DONE;
14169 }")
14171 (define_expand "ctr<mode>"
14172 [(parallel [(set (pc)
14173 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14174 (const_int 1))
14175 (label_ref (match_operand 1 "" ""))
14176 (pc)))
14177 (set (match_dup 0)
14178 (plus:P (match_dup 0)
14179 (const_int -1)))
14180 (clobber (match_scratch:CC 2 ""))
14181 (clobber (match_scratch:P 3 ""))])]
14182 ""
14183 "")
14185 ;; We need to be able to do this for any operand, including MEM, or we
14186 ;; will cause reload to blow up since we don't allow output reloads on
14187 ;; JUMP_INSNs.
14188 ;; For the length attribute to be calculated correctly, the
14189 ;; label MUST be operand 0.
14191 (define_insn "*ctr<mode>_internal1"
14192 [(set (pc)
14193 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14194 (const_int 1))
14195 (label_ref (match_operand 0 "" ""))
14196 (pc)))
14197 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14198 (plus:P (match_dup 1)
14199 (const_int -1)))
14200 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14201 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14202 ""
14203 "*
14204 {
14205 if (which_alternative != 0)
14206 return \"#\";
14207 else if (get_attr_length (insn) == 4)
14208 return \"bdnz %l0\";
14209 else
14210 return \"bdz $+8\;b %l0\";
14211 }"
14212 [(set_attr "type" "branch")
14213 (set_attr "length" "*,12,16,16")])
14215 (define_insn "*ctr<mode>_internal2"
14216 [(set (pc)
14217 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14218 (const_int 1))
14219 (pc)
14220 (label_ref (match_operand 0 "" ""))))
14221 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14222 (plus:P (match_dup 1)
14223 (const_int -1)))
14224 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14225 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14226 ""
14227 "*
14228 {
14229 if (which_alternative != 0)
14230 return \"#\";
14231 else if (get_attr_length (insn) == 4)
14232 return \"bdz %l0\";
14233 else
14234 return \"bdnz $+8\;b %l0\";
14235 }"
14236 [(set_attr "type" "branch")
14237 (set_attr "length" "*,12,16,16")])
14239 ;; Similar but use EQ
14241 (define_insn "*ctr<mode>_internal5"
14242 [(set (pc)
14243 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14244 (const_int 1))
14245 (label_ref (match_operand 0 "" ""))
14246 (pc)))
14247 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14248 (plus:P (match_dup 1)
14249 (const_int -1)))
14250 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14251 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14252 ""
14253 "*
14254 {
14255 if (which_alternative != 0)
14256 return \"#\";
14257 else if (get_attr_length (insn) == 4)
14258 return \"bdz %l0\";
14259 else
14260 return \"bdnz $+8\;b %l0\";
14261 }"
14262 [(set_attr "type" "branch")
14263 (set_attr "length" "*,12,16,16")])
14265 (define_insn "*ctr<mode>_internal6"
14266 [(set (pc)
14267 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14268 (const_int 1))
14269 (pc)
14270 (label_ref (match_operand 0 "" ""))))
14271 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14272 (plus:P (match_dup 1)
14273 (const_int -1)))
14274 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14275 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14276 ""
14277 "*
14278 {
14279 if (which_alternative != 0)
14280 return \"#\";
14281 else if (get_attr_length (insn) == 4)
14282 return \"bdnz %l0\";
14283 else
14284 return \"bdz $+8\;b %l0\";
14285 }"
14286 [(set_attr "type" "branch")
14287 (set_attr "length" "*,12,16,16")])
14289 ;; Now the splitters if we could not allocate the CTR register
14291 (define_split
14292 [(set (pc)
14293 (if_then_else (match_operator 2 "comparison_operator"
14294 [(match_operand:P 1 "gpc_reg_operand" "")
14295 (const_int 1)])
14296 (match_operand 5 "" "")
14297 (match_operand 6 "" "")))
14298 (set (match_operand:P 0 "gpc_reg_operand" "")
14299 (plus:P (match_dup 1) (const_int -1)))
14300 (clobber (match_scratch:CC 3 ""))
14301 (clobber (match_scratch:P 4 ""))]
14302 "reload_completed"
14303 [(parallel [(set (match_dup 3)
14304 (compare:CC (plus:P (match_dup 1)
14305 (const_int -1))
14306 (const_int 0)))
14307 (set (match_dup 0)
14308 (plus:P (match_dup 1)
14309 (const_int -1)))])
14310 (set (pc) (if_then_else (match_dup 7)
14311 (match_dup 5)
14312 (match_dup 6)))]
14313 "
14314 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14315 operands[3], const0_rtx); }")
14317 (define_split
14318 [(set (pc)
14319 (if_then_else (match_operator 2 "comparison_operator"
14320 [(match_operand:P 1 "gpc_reg_operand" "")
14321 (const_int 1)])
14322 (match_operand 5 "" "")
14323 (match_operand 6 "" "")))
14324 (set (match_operand:P 0 "nonimmediate_operand" "")
14325 (plus:P (match_dup 1) (const_int -1)))
14326 (clobber (match_scratch:CC 3 ""))
14327 (clobber (match_scratch:P 4 ""))]
14328 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14329 [(parallel [(set (match_dup 3)
14330 (compare:CC (plus:P (match_dup 1)
14331 (const_int -1))
14332 (const_int 0)))
14333 (set (match_dup 4)
14334 (plus:P (match_dup 1)
14335 (const_int -1)))])
14336 (set (match_dup 0)
14337 (match_dup 4))
14338 (set (pc) (if_then_else (match_dup 7)
14339 (match_dup 5)
14340 (match_dup 6)))]
14341 "
14342 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14343 operands[3], const0_rtx); }")
14344 \f
14345 (define_insn "trap"
14346 [(trap_if (const_int 1) (const_int 0))]
14347 ""
14348 "trap"
14349 [(set_attr "type" "trap")])
14351 (define_expand "ctrap<mode>4"
14352 [(trap_if (match_operator 0 "ordered_comparison_operator"
14353 [(match_operand:GPR 1 "register_operand")
14354 (match_operand:GPR 2 "reg_or_short_operand")])
14355 (match_operand 3 "zero_constant" ""))]
14356 ""
14357 "")
14359 (define_insn ""
14360 [(trap_if (match_operator 0 "ordered_comparison_operator"
14361 [(match_operand:GPR 1 "register_operand" "r")
14362 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14363 (const_int 0))]
14364 ""
14365 "t<wd>%V0%I2 %1,%2"
14366 [(set_attr "type" "trap")])
14367 \f
14368 ;; Insns related to generating the function prologue and epilogue.
14370 (define_expand "prologue"
14371 [(use (const_int 0))]
14372 ""
14373 {
14374 rs6000_emit_prologue ();
14375 if (!TARGET_SCHED_PROLOG)
14376 emit_insn (gen_blockage ());
14377 DONE;
14378 })
14380 (define_insn "*movesi_from_cr_one"
14381 [(match_parallel 0 "mfcr_operation"
14382 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14383 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14384 (match_operand 3 "immediate_operand" "n")]
14385 UNSPEC_MOVESI_FROM_CR))])]
14386 "TARGET_MFCRF"
14387 "*
14388 {
14389 int mask = 0;
14390 int i;
14391 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14392 {
14393 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14394 operands[4] = GEN_INT (mask);
14395 output_asm_insn (\"mfcr %1,%4\", operands);
14396 }
14397 return \"\";
14398 }"
14399 [(set_attr "type" "mfcrf")])
14401 (define_insn "movesi_from_cr"
14402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14403 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14404 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14405 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14406 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14407 UNSPEC_MOVESI_FROM_CR))]
14408 ""
14409 "mfcr %0"
14410 [(set_attr "type" "mfcr")])
14412 (define_insn "*stmw"
14413 [(match_parallel 0 "stmw_operation"
14414 [(set (match_operand:SI 1 "memory_operand" "=m")
14415 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14416 "TARGET_MULTIPLE"
14417 "stmw %2,%1"
14418 [(set_attr "type" "store_ux")])
14420 ; The following comment applies to:
14421 ; save_gpregs_*
14422 ; save_fpregs_*
14423 ; restore_gpregs*
14424 ; return_and_restore_gpregs*
14425 ; return_and_restore_fpregs*
14426 ; return_and_restore_fpregs_aix*
14427 ;
14428 ; The out-of-line save / restore functions expects one input argument.
14429 ; Since those are not standard call_insn's, we must avoid using
14430 ; MATCH_OPERAND for that argument. That way the register rename
14431 ; optimization will not try to rename this register.
14432 ; Each pattern is repeated for each possible register number used in
14433 ; various ABIs (r11, r1, and for some functions r12)
14435 (define_insn "*save_gpregs_<mode>_r11"
14436 [(match_parallel 0 "any_parallel_operand"
14437 [(clobber (reg:P 65))
14438 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14439 (use (reg:P 11))
14440 (set (match_operand:P 2 "memory_operand" "=m")
14441 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14442 ""
14443 "bl %1"
14444 [(set_attr "type" "branch")
14445 (set_attr "length" "4")])
14447 (define_insn "*save_gpregs_<mode>_r12"
14448 [(match_parallel 0 "any_parallel_operand"
14449 [(clobber (reg:P 65))
14450 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14451 (use (reg:P 12))
14452 (set (match_operand:P 2 "memory_operand" "=m")
14453 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14454 ""
14455 "bl %1"
14456 [(set_attr "type" "branch")
14457 (set_attr "length" "4")])
14459 (define_insn "*save_gpregs_<mode>_r1"
14460 [(match_parallel 0 "any_parallel_operand"
14461 [(clobber (reg:P 65))
14462 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14463 (use (reg:P 1))
14464 (set (match_operand:P 2 "memory_operand" "=m")
14465 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14466 ""
14467 "bl %1"
14468 [(set_attr "type" "branch")
14469 (set_attr "length" "4")])
14471 (define_insn "*save_fpregs_<mode>_r11"
14472 [(match_parallel 0 "any_parallel_operand"
14473 [(clobber (reg:P 65))
14474 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14475 (use (reg:P 11))
14476 (set (match_operand:DF 2 "memory_operand" "=m")
14477 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14478 ""
14479 "bl %1"
14480 [(set_attr "type" "branch")
14481 (set_attr "length" "4")])
14483 (define_insn "*save_fpregs_<mode>_r12"
14484 [(match_parallel 0 "any_parallel_operand"
14485 [(clobber (reg:P 65))
14486 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14487 (use (reg:P 12))
14488 (set (match_operand:DF 2 "memory_operand" "=m")
14489 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14490 ""
14491 "bl %1"
14492 [(set_attr "type" "branch")
14493 (set_attr "length" "4")])
14495 (define_insn "*save_fpregs_<mode>_r1"
14496 [(match_parallel 0 "any_parallel_operand"
14497 [(clobber (reg:P 65))
14498 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14499 (use (reg:P 1))
14500 (set (match_operand:DF 2 "memory_operand" "=m")
14501 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14502 ""
14503 "bl %1"
14504 [(set_attr "type" "branch")
14505 (set_attr "length" "4")])
14507 ; This is to explain that changes to the stack pointer should
14508 ; not be moved over loads from or stores to stack memory.
14509 (define_insn "stack_tie"
14510 [(match_parallel 0 "tie_operand"
14511 [(set (mem:BLK (reg 1)) (const_int 0))])]
14512 ""
14513 ""
14514 [(set_attr "length" "0")])
14516 (define_expand "epilogue"
14517 [(use (const_int 0))]
14518 ""
14519 {
14520 if (!TARGET_SCHED_PROLOG)
14521 emit_insn (gen_blockage ());
14522 rs6000_emit_epilogue (FALSE);
14523 DONE;
14524 })
14526 ; On some processors, doing the mtcrf one CC register at a time is
14527 ; faster (like on the 604e). On others, doing them all at once is
14528 ; faster; for instance, on the 601 and 750.
14530 (define_expand "movsi_to_cr_one"
14531 [(set (match_operand:CC 0 "cc_reg_operand" "")
14532 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14533 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14534 ""
14535 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14537 (define_insn "*movsi_to_cr"
14538 [(match_parallel 0 "mtcrf_operation"
14539 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14540 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14541 (match_operand 3 "immediate_operand" "n")]
14542 UNSPEC_MOVESI_TO_CR))])]
14543 ""
14544 "*
14545 {
14546 int mask = 0;
14547 int i;
14548 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14549 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14550 operands[4] = GEN_INT (mask);
14551 return \"mtcrf %4,%2\";
14552 }"
14553 [(set_attr "type" "mtcr")])
14555 (define_insn "*mtcrfsi"
14556 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14557 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14558 (match_operand 2 "immediate_operand" "n")]
14559 UNSPEC_MOVESI_TO_CR))]
14560 "GET_CODE (operands[0]) == REG
14561 && CR_REGNO_P (REGNO (operands[0]))
14562 && GET_CODE (operands[2]) == CONST_INT
14563 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14564 "mtcrf %R0,%1"
14565 [(set_attr "type" "mtcr")])
14567 ; The load-multiple instructions have similar properties.
14568 ; Note that "load_multiple" is a name known to the machine-independent
14569 ; code that actually corresponds to the PowerPC load-string.
14571 (define_insn "*lmw"
14572 [(match_parallel 0 "lmw_operation"
14573 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14574 (match_operand:SI 2 "memory_operand" "m"))])]
14575 "TARGET_MULTIPLE"
14576 "lmw %1,%2"
14577 [(set_attr "type" "load_ux")
14578 (set_attr "cell_micro" "always")])
14580 (define_insn "*return_internal_<mode>"
14581 [(simple_return)
14582 (use (match_operand:P 0 "register_operand" "lc"))]
14583 ""
14584 "b%T0"
14585 [(set_attr "type" "jmpreg")])
14587 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14588 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14590 ; The following comment applies to:
14591 ; save_gpregs_*
14592 ; save_fpregs_*
14593 ; restore_gpregs*
14594 ; return_and_restore_gpregs*
14595 ; return_and_restore_fpregs*
14596 ; return_and_restore_fpregs_aix*
14597 ;
14598 ; The out-of-line save / restore functions expects one input argument.
14599 ; Since those are not standard call_insn's, we must avoid using
14600 ; MATCH_OPERAND for that argument. That way the register rename
14601 ; optimization will not try to rename this register.
14602 ; Each pattern is repeated for each possible register number used in
14603 ; various ABIs (r11, r1, and for some functions r12)
14605 (define_insn "*restore_gpregs_<mode>_r11"
14606 [(match_parallel 0 "any_parallel_operand"
14607 [(clobber (match_operand:P 1 "register_operand" "=l"))
14608 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14609 (use (reg:P 11))
14610 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14611 (match_operand:P 4 "memory_operand" "m"))])]
14612 ""
14613 "bl %2"
14614 [(set_attr "type" "branch")
14615 (set_attr "length" "4")])
14617 (define_insn "*restore_gpregs_<mode>_r12"
14618 [(match_parallel 0 "any_parallel_operand"
14619 [(clobber (match_operand:P 1 "register_operand" "=l"))
14620 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14621 (use (reg:P 12))
14622 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14623 (match_operand:P 4 "memory_operand" "m"))])]
14624 ""
14625 "bl %2"
14626 [(set_attr "type" "branch")
14627 (set_attr "length" "4")])
14629 (define_insn "*restore_gpregs_<mode>_r1"
14630 [(match_parallel 0 "any_parallel_operand"
14631 [(clobber (match_operand:P 1 "register_operand" "=l"))
14632 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14633 (use (reg:P 1))
14634 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14635 (match_operand:P 4 "memory_operand" "m"))])]
14636 ""
14637 "bl %2"
14638 [(set_attr "type" "branch")
14639 (set_attr "length" "4")])
14641 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14642 [(match_parallel 0 "any_parallel_operand"
14643 [(return)
14644 (clobber (match_operand:P 1 "register_operand" "=l"))
14645 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14646 (use (reg:P 11))
14647 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14648 (match_operand:P 4 "memory_operand" "m"))])]
14649 ""
14650 "b %2"
14651 [(set_attr "type" "branch")
14652 (set_attr "length" "4")])
14654 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14655 [(match_parallel 0 "any_parallel_operand"
14656 [(return)
14657 (clobber (match_operand:P 1 "register_operand" "=l"))
14658 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14659 (use (reg:P 12))
14660 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14661 (match_operand:P 4 "memory_operand" "m"))])]
14662 ""
14663 "b %2"
14664 [(set_attr "type" "branch")
14665 (set_attr "length" "4")])
14667 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14668 [(match_parallel 0 "any_parallel_operand"
14669 [(return)
14670 (clobber (match_operand:P 1 "register_operand" "=l"))
14671 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14672 (use (reg:P 1))
14673 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14674 (match_operand:P 4 "memory_operand" "m"))])]
14675 ""
14676 "b %2"
14677 [(set_attr "type" "branch")
14678 (set_attr "length" "4")])
14680 (define_insn "*return_and_restore_fpregs_<mode>_r11"
14681 [(match_parallel 0 "any_parallel_operand"
14682 [(return)
14683 (clobber (match_operand:P 1 "register_operand" "=l"))
14684 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14685 (use (reg:P 11))
14686 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14687 (match_operand:DF 4 "memory_operand" "m"))])]
14688 ""
14689 "b %2"
14690 [(set_attr "type" "branch")
14691 (set_attr "length" "4")])
14693 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14694 [(match_parallel 0 "any_parallel_operand"
14695 [(return)
14696 (clobber (match_operand:P 1 "register_operand" "=l"))
14697 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14698 (use (reg:P 12))
14699 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14700 (match_operand:DF 4 "memory_operand" "m"))])]
14701 ""
14702 "b %2"
14703 [(set_attr "type" "branch")
14704 (set_attr "length" "4")])
14706 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14707 [(match_parallel 0 "any_parallel_operand"
14708 [(return)
14709 (clobber (match_operand:P 1 "register_operand" "=l"))
14710 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14711 (use (reg:P 1))
14712 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14713 (match_operand:DF 4 "memory_operand" "m"))])]
14714 ""
14715 "b %2"
14716 [(set_attr "type" "branch")
14717 (set_attr "length" "4")])
14719 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14720 [(match_parallel 0 "any_parallel_operand"
14721 [(return)
14722 (use (match_operand:P 1 "register_operand" "l"))
14723 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14724 (use (reg:P 11))
14725 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14726 (match_operand:DF 4 "memory_operand" "m"))])]
14727 ""
14728 "b %2"
14729 [(set_attr "type" "branch")
14730 (set_attr "length" "4")])
14732 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14733 [(match_parallel 0 "any_parallel_operand"
14734 [(return)
14735 (use (match_operand:P 1 "register_operand" "l"))
14736 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14737 (use (reg:P 1))
14738 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14739 (match_operand:DF 4 "memory_operand" "m"))])]
14740 ""
14741 "b %2"
14742 [(set_attr "type" "branch")
14743 (set_attr "length" "4")])
14745 ; This is used in compiling the unwind routines.
14746 (define_expand "eh_return"
14747 [(use (match_operand 0 "general_operand" ""))]
14748 ""
14749 "
14750 {
14751 if (TARGET_32BIT)
14752 emit_insn (gen_eh_set_lr_si (operands[0]));
14753 else
14754 emit_insn (gen_eh_set_lr_di (operands[0]));
14755 DONE;
14756 }")
14758 ; We can't expand this before we know where the link register is stored.
14759 (define_insn "eh_set_lr_<mode>"
14760 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14761 UNSPECV_EH_RR)
14762 (clobber (match_scratch:P 1 "=&b"))]
14763 ""
14764 "#")
14766 (define_split
14767 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14768 (clobber (match_scratch 1 ""))]
14769 "reload_completed"
14770 [(const_int 0)]
14771 "
14772 {
14773 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14774 DONE;
14775 }")
14777 (define_insn "prefetch"
14778 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14779 (match_operand:SI 1 "const_int_operand" "n")
14780 (match_operand:SI 2 "const_int_operand" "n"))]
14781 ""
14782 "*
14783 {
14784 if (GET_CODE (operands[0]) == REG)
14785 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14786 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14787 }"
14788 [(set_attr "type" "load")])
14789 \f
14790 (define_insn "bpermd_<mode>"
14791 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14792 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14793 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14794 "TARGET_POPCNTD"
14795 "bpermd %0,%1,%2"
14796 [(set_attr "type" "popcnt")])
14798 \f
14799 ;; Builtin fma support. Handle
14800 ;; Note that the conditions for expansion are in the FMA_F iterator.
14802 (define_expand "fma<mode>4"
14803 [(set (match_operand:FMA_F 0 "register_operand" "")
14804 (fma:FMA_F
14805 (match_operand:FMA_F 1 "register_operand" "")
14806 (match_operand:FMA_F 2 "register_operand" "")
14807 (match_operand:FMA_F 3 "register_operand" "")))]
14808 ""
14809 "")
14811 ; Altivec only has fma and nfms.
14812 (define_expand "fms<mode>4"
14813 [(set (match_operand:FMA_F 0 "register_operand" "")
14814 (fma:FMA_F
14815 (match_operand:FMA_F 1 "register_operand" "")
14816 (match_operand:FMA_F 2 "register_operand" "")
14817 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14818 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14819 "")
14821 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14822 (define_expand "fnma<mode>4"
14823 [(set (match_operand:FMA_F 0 "register_operand" "")
14824 (neg:FMA_F
14825 (fma:FMA_F
14826 (match_operand:FMA_F 1 "register_operand" "")
14827 (match_operand:FMA_F 2 "register_operand" "")
14828 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14829 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14830 "")
14832 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14833 (define_expand "fnms<mode>4"
14834 [(set (match_operand:FMA_F 0 "register_operand" "")
14835 (neg:FMA_F
14836 (fma:FMA_F
14837 (match_operand:FMA_F 1 "register_operand" "")
14838 (match_operand:FMA_F 2 "register_operand" "")
14839 (match_operand:FMA_F 3 "register_operand" ""))))]
14840 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14841 "")
14843 ; Not an official optab name, but used from builtins.
14844 (define_expand "nfma<mode>4"
14845 [(set (match_operand:FMA_F 0 "register_operand" "")
14846 (neg:FMA_F
14847 (fma:FMA_F
14848 (match_operand:FMA_F 1 "register_operand" "")
14849 (match_operand:FMA_F 2 "register_operand" "")
14850 (match_operand:FMA_F 3 "register_operand" ""))))]
14851 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14852 "")
14854 ; Not an official optab name, but used from builtins.
14855 (define_expand "nfms<mode>4"
14856 [(set (match_operand:FMA_F 0 "register_operand" "")
14857 (neg:FMA_F
14858 (fma:FMA_F
14859 (match_operand:FMA_F 1 "register_operand" "")
14860 (match_operand:FMA_F 2 "register_operand" "")
14861 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14862 ""
14863 "")
14865 (define_expand "rs6000_get_timebase"
14866 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14867 ""
14868 {
14869 if (TARGET_POWERPC64)
14870 emit_insn (gen_rs6000_mftb_di (operands[0]));
14871 else
14872 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14873 DONE;
14874 })
14876 (define_insn "rs6000_get_timebase_ppc32"
14877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14878 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14879 (clobber (match_scratch:SI 1 "=r"))
14880 (clobber (match_scratch:CC 2 "=y"))]
14881 "!TARGET_POWERPC64"
14882 {
14883 if (WORDS_BIG_ENDIAN)
14884 if (TARGET_MFCRF)
14885 {
14886 return "mfspr %0,269\;"
14887 "mfspr %L0,268\;"
14888 "mfspr %1,269\;"
14889 "cmpw %2,%0,%1\;"
14890 "bne- %2,$-16";
14891 }
14892 else
14893 {
14894 return "mftbu %0\;"
14895 "mftb %L0\;"
14896 "mftbu %1\;"
14897 "cmpw %2,%0,%1\;"
14898 "bne- %2,$-16";
14899 }
14900 else
14901 if (TARGET_MFCRF)
14902 {
14903 return "mfspr %L0,269\;"
14904 "mfspr %0,268\;"
14905 "mfspr %1,269\;"
14906 "cmpw %2,%L0,%1\;"
14907 "bne- %2,$-16";
14908 }
14909 else
14910 {
14911 return "mftbu %L0\;"
14912 "mftb %0\;"
14913 "mftbu %1\;"
14914 "cmpw %2,%L0,%1\;"
14915 "bne- %2,$-16";
14916 }
14917 })
14919 (define_insn "rs6000_mftb_<mode>"
14920 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14921 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
14922 ""
14923 {
14924 if (TARGET_MFCRF)
14925 return "mfspr %0,268";
14926 else
14927 return "mftb %0";
14928 })
14930 \f
14932 (include "sync.md")
14933 (include "vector.md")
14934 (include "vsx.md")
14935 (include "altivec.md")
14936 (include "spe.md")
14937 (include "dfp.md")
14938 (include "paired.md")
14939 (include "crypto.md")