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* doc/tm.texi (INIT_CUMULATIVE_ARGS): Update doco.
[official-gcc.git] / gcc / config / mips / mips.h
blobd899143967ab846ea03b5b9e30f82b7a42689743
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SR71000
71 };
72
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
76
77 #define ABI_32 0
78 #define ABI_N32 1
79 #define ABI_64 2
80 #define ABI_EABI 3
81 #define ABI_O64 4
82
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
89 const char *name;
90
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
95
96 /* The ISA level that the processor implements. */
97 int isa;
98 };
99
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern int mips_string_length; /* length of strings for mips16 */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
129
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
132
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
136
137 \f
138 /* Run-time compilation parameters selecting different hardware subsets. */
139
140 /* Macros used in the machine description to test the flags. */
141
142 /* Bits for real switches */
143 #define MASK_INT64 0x00000001 /* ints are 64 bits */
144 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
145 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
146 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
147 multiply-add operations. */
148 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
149 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
150 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
151 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
152 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
153 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
154 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
155 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
156 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
157 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
158 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
159 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
160 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
161 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
162 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
163 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
164 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
165 #define MASK_NO_CHECK_ZERO_DIV \
166 0x00200000 /* divide by zero checking */
167 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
168 instructions. */
169 #define MASK_UNINIT_CONST_IN_RODATA \
170 0x00800000 /* Store uninitialized
171 consts in rodata */
172 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
173
174 /* Debug switches, not documented */
175 #define MASK_DEBUG 0 /* unused */
176 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
177 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_E 0 /* function_arg debug */
181 #define MASK_DEBUG_F 0 /* ??? */
182 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
183 #define MASK_DEBUG_I 0 /* unused */
184
185 /* Dummy switches used only in specs */
186 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
187
188 /* r4000 64 bit sizes */
189 #define TARGET_INT64 (target_flags & MASK_INT64)
190 #define TARGET_LONG64 (target_flags & MASK_LONG64)
191 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
192 #define TARGET_64BIT (target_flags & MASK_64BIT)
193
194 /* Mips vs. GNU linker */
195 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
196
197 /* Mips vs. GNU assembler */
198 #define TARGET_GAS (target_flags & MASK_GAS)
199 #define TARGET_MIPS_AS (!TARGET_GAS)
200
201 /* Debug Modes */
202 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
203 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
204 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
205 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
206 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
207 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
208 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
209 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
210 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
211
212 /* Reg. Naming in .s ($21 vs. $a0) */
213 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
214
215 /* call memcpy instead of inline code */
216 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
217
218 /* .abicalls, etc from Pyramid V.4 */
219 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
220 #define TARGET_XGOT (target_flags & MASK_XGOT)
221
222 /* software floating point */
223 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
224 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
225
226 /* always call through a register */
227 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
228
229 /* generate embedded PIC code;
230 requires gas. */
231 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
232
233 /* for embedded systems, optimize for
234 reduced RAM space instead of for
235 fastest code. */
236 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
237
238 /* always store uninitialized const
239 variables in rodata, requires
240 TARGET_EMBEDDED_DATA. */
241 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
242
243 /* generate big endian code. */
244 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
245
246 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
247 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
248
249 #define TARGET_MAD (target_flags & MASK_MAD)
250
251 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
252
253 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
254
255 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
256
257 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
258
259 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
260
261 /* True if we should use NewABI-style relocation operators for
262 symbolic addresses. This is never true for mips16 code,
263 which has its own conventions. */
264
265 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
266
267
268 /* True if the call patterns should be split into a jalr followed by
269 an instruction to restore $gp. This is only ever true for SVR4 PIC,
270 in which $gp is call-clobbered. It is only safe to split the load
271 from the call when every use of $gp is explicit. */
272
273 #define TARGET_SPLIT_CALLS \
274 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
275
276 /* True if we can optimize sibling calls. For simplicity, we only
277 handle cases in which call_insn_operand will reject invalid
278 sibcall addresses. There are two cases in which this isn't true:
279
280 - TARGET_MIPS16. call_insn_operand accepts constant addresses
281 but there is no direct jump instruction. It isn't worth
282 using sibling calls in this case anyway; they would usually
283 be longer than normal calls.
284
285 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
286 accepts global constants, but "jr $25" is the only allowed
287 sibcall. */
288
289 #define TARGET_SIBCALLS \
290 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
291
292 /* True if .gpword or .gpdword should be used for switch tables.
293 Not all SGI assemblers support this. */
294
295 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
296
297 /* Generate mips16 code */
298 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
299
300 /* Generic ISA defines. */
301 #define ISA_MIPS1 (mips_isa == 1)
302 #define ISA_MIPS2 (mips_isa == 2)
303 #define ISA_MIPS3 (mips_isa == 3)
304 #define ISA_MIPS4 (mips_isa == 4)
305 #define ISA_MIPS32 (mips_isa == 32)
306 #define ISA_MIPS32R2 (mips_isa == 33)
307 #define ISA_MIPS64 (mips_isa == 64)
308
309 /* Architecture target defines. */
310 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
311 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
312 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
313 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
314 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
315 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
316 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
317 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
318 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
319 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
320 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
321 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
322 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
323
324 /* Scheduling target defines. */
325 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
326 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
327 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
328 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
329 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
330 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
331 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
332 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
333 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
334 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
335 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
336
337 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
338
339 /* IRIX specific stuff. */
340 #define TARGET_IRIX 0
341 #define TARGET_IRIX5 0
342 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
343
344 /* Define preprocessor macros for the -march and -mtune options.
345 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
346 processor. If INFO's canonical name is "foo", define PREFIX to
347 be "foo", and define an additional macro PREFIX_FOO. */
348 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
349 do \
350 { \
351 char *macro, *p; \
352 \
353 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
354 for (p = macro; *p != 0; p++) \
355 *p = TOUPPER (*p); \
356 \
357 builtin_define (macro); \
358 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
359 free (macro); \
360 } \
361 while (0)
362
363 /* Target CPU builtins. */
364 #define TARGET_CPU_CPP_BUILTINS() \
365 do \
366 { \
367 builtin_assert ("cpu=mips"); \
368 builtin_define ("__mips__"); \
369 builtin_define ("_mips"); \
370 \
371 /* We do this here because __mips is defined below \
372 and so we can't use builtin_define_std. */ \
373 if (!flag_iso) \
374 builtin_define ("mips"); \
375 \
376 /* Treat _R3000 and _R4000 like register-size defines, \
377 which is how they've historically been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define ("__mips64"); \
381 builtin_define_std ("R4000"); \
382 builtin_define ("_R4000"); \
383 } \
384 else \
385 { \
386 builtin_define_std ("R3000"); \
387 builtin_define ("_R3000"); \
388 } \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (TARGET_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
398 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
399 \
400 if (ISA_MIPS1) \
401 { \
402 builtin_define ("__mips=1"); \
403 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
404 } \
405 else if (ISA_MIPS2) \
406 { \
407 builtin_define ("__mips=2"); \
408 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
409 } \
410 else if (ISA_MIPS3) \
411 { \
412 builtin_define ("__mips=3"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
414 } \
415 else if (ISA_MIPS4) \
416 { \
417 builtin_define ("__mips=4"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
419 } \
420 else if (ISA_MIPS32) \
421 { \
422 builtin_define ("__mips=32"); \
423 builtin_define ("__mips_isa_rev=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
425 } \
426 else if (ISA_MIPS32R2) \
427 { \
428 builtin_define ("__mips=32"); \
429 builtin_define ("__mips_isa_rev=2"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
431 } \
432 else if (ISA_MIPS64) \
433 { \
434 builtin_define ("__mips=64"); \
435 builtin_define ("__mips_isa_rev=1"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
437 } \
438 \
439 if (TARGET_HARD_FLOAT) \
440 builtin_define ("__mips_hard_float"); \
441 else if (TARGET_SOFT_FLOAT) \
442 builtin_define ("__mips_soft_float"); \
443 \
444 if (TARGET_SINGLE_FLOAT) \
445 builtin_define ("__mips_single_float"); \
446 \
447 if (TARGET_BIG_ENDIAN) \
448 { \
449 builtin_define_std ("MIPSEB"); \
450 builtin_define ("_MIPSEB"); \
451 } \
452 else \
453 { \
454 builtin_define_std ("MIPSEL"); \
455 builtin_define ("_MIPSEL"); \
456 } \
457 \
458 /* Macros dependent on the C dialect. */ \
459 if (preprocessing_asm_p ()) \
460 { \
461 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
462 builtin_define ("_LANGUAGE_ASSEMBLY"); \
463 } \
464 else if (c_dialect_cxx ()) \
465 { \
466 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
467 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
468 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
469 } \
470 else \
471 { \
472 builtin_define_std ("LANGUAGE_C"); \
473 builtin_define ("_LANGUAGE_C"); \
474 } \
475 if (c_dialect_objc ()) \
476 { \
477 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
478 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
479 /* Bizarre, but needed at least for Irix. */ \
480 builtin_define_std ("LANGUAGE_C"); \
481 builtin_define ("_LANGUAGE_C"); \
482 } \
483 \
484 if (mips_abi == ABI_EABI) \
485 builtin_define ("__mips_eabi"); \
486 \
487 } while (0)
488
489
490
491 /* Macro to define tables used to set the flags.
492 This is a list in braces of pairs in braces,
493 each pair being { "NAME", VALUE }
494 where VALUE is the bits to set or minus the bits to clear.
495 An empty string NAME is used to identify the default VALUE. */
496
497 #define TARGET_SWITCHES \
498 { \
499 SUBTARGET_TARGET_SWITCHES \
500 {"int64", MASK_INT64 | MASK_LONG64, \
501 N_("Use 64-bit int type")}, \
502 {"long64", MASK_LONG64, \
503 N_("Use 64-bit long type")}, \
504 {"long32", -(MASK_LONG64 | MASK_INT64), \
505 N_("Use 32-bit long type")}, \
506 {"split-addresses", MASK_SPLIT_ADDR, \
507 N_("Optimize lui/addiu address loads")}, \
508 {"no-split-addresses", -MASK_SPLIT_ADDR, \
509 N_("Don't optimize lui/addiu address loads")}, \
510 {"mips-as", -MASK_GAS, \
511 N_("Use MIPS as")}, \
512 {"gas", MASK_GAS, \
513 N_("Use GNU as")}, \
514 {"rnames", MASK_NAME_REGS, \
515 N_("Use symbolic register names")}, \
516 {"no-rnames", -MASK_NAME_REGS, \
517 N_("Don't use symbolic register names")}, \
518 {"gpOPT", 0, \
519 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
520 {"gpopt", 0, \
521 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
522 {"no-gpOPT", 0, \
523 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
524 {"no-gpopt", 0, \
525 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
526 {"stats", 0, \
527 N_("Output compiler statistics (now ignored)")}, \
528 {"no-stats", 0, \
529 N_("Don't output compiler statistics")}, \
530 {"memcpy", MASK_MEMCPY, \
531 N_("Don't optimize block moves")}, \
532 {"no-memcpy", -MASK_MEMCPY, \
533 N_("Optimize block moves")}, \
534 {"mips-tfile", MASK_MIPS_TFILE, \
535 N_("Use mips-tfile asm postpass")}, \
536 {"no-mips-tfile", -MASK_MIPS_TFILE, \
537 N_("Don't use mips-tfile asm postpass")}, \
538 {"soft-float", MASK_SOFT_FLOAT, \
539 N_("Use software floating point")}, \
540 {"hard-float", -MASK_SOFT_FLOAT, \
541 N_("Use hardware floating point")}, \
542 {"fp64", MASK_FLOAT64, \
543 N_("Use 64-bit FP registers")}, \
544 {"fp32", -MASK_FLOAT64, \
545 N_("Use 32-bit FP registers")}, \
546 {"gp64", MASK_64BIT, \
547 N_("Use 64-bit general registers")}, \
548 {"gp32", -MASK_64BIT, \
549 N_("Use 32-bit general registers")}, \
550 {"abicalls", MASK_ABICALLS, \
551 N_("Use Irix PIC")}, \
552 {"no-abicalls", -MASK_ABICALLS, \
553 N_("Don't use Irix PIC")}, \
554 {"long-calls", MASK_LONG_CALLS, \
555 N_("Use indirect calls")}, \
556 {"no-long-calls", -MASK_LONG_CALLS, \
557 N_("Don't use indirect calls")}, \
558 {"embedded-pic", MASK_EMBEDDED_PIC, \
559 N_("Use embedded PIC")}, \
560 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
561 N_("Don't use embedded PIC")}, \
562 {"embedded-data", MASK_EMBEDDED_DATA, \
563 N_("Use ROM instead of RAM")}, \
564 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
565 N_("Don't use ROM instead of RAM")}, \
566 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
567 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
568 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
569 N_("Don't put uninitialized constants in ROM")}, \
570 {"eb", MASK_BIG_ENDIAN, \
571 N_("Use big-endian byte order")}, \
572 {"el", -MASK_BIG_ENDIAN, \
573 N_("Use little-endian byte order")}, \
574 {"single-float", MASK_SINGLE_FLOAT, \
575 N_("Use single (32-bit) FP only")}, \
576 {"double-float", -MASK_SINGLE_FLOAT, \
577 N_("Don't use single (32-bit) FP only")}, \
578 {"mad", MASK_MAD, \
579 N_("Use multiply accumulate")}, \
580 {"no-mad", -MASK_MAD, \
581 N_("Don't use multiply accumulate")}, \
582 {"no-fused-madd", MASK_NO_FUSED_MADD, \
583 N_("Don't generate fused multiply/add instructions")}, \
584 {"fused-madd", -MASK_NO_FUSED_MADD, \
585 N_("Generate fused multiply/add instructions")}, \
586 {"fix4300", MASK_4300_MUL_FIX, \
587 N_("Work around early 4300 hardware bug")}, \
588 {"no-fix4300", -MASK_4300_MUL_FIX, \
589 N_("Don't work around early 4300 hardware bug")}, \
590 {"fix-sb1", MASK_FIX_SB1, \
591 N_("Work around errata for early SB-1 revision 2 cores")}, \
592 {"no-fix-sb1", -MASK_FIX_SB1, \
593 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
594 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
595 N_("Trap on integer divide by zero")}, \
596 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
597 N_("Don't trap on integer divide by zero")}, \
598 { "branch-likely", MASK_BRANCHLIKELY, \
599 N_("Use Branch Likely instructions, overriding default for arch")}, \
600 { "no-branch-likely", -MASK_BRANCHLIKELY, \
601 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
602 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
603 N_("Use NewABI-style %reloc() assembly operators")}, \
604 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
605 N_("Use assembler macros instead of relocation operators")}, \
606 {"ips16", MASK_MIPS16, \
607 N_("Generate mips16 code") }, \
608 {"no-mips16", -MASK_MIPS16, \
609 N_("Generate normal-mode code") }, \
610 {"xgot", MASK_XGOT, \
611 N_("Lift restrictions on GOT size") }, \
612 {"no-xgot", -MASK_XGOT, \
613 N_("Do not lift restrictions on GOT size") }, \
614 {"debug", MASK_DEBUG, \
615 NULL}, \
616 {"debuga", MASK_DEBUG_A, \
617 NULL}, \
618 {"debugb", MASK_DEBUG_B, \
619 NULL}, \
620 {"debugc", MASK_DEBUG_C, \
621 NULL}, \
622 {"debugd", MASK_DEBUG_D, \
623 NULL}, \
624 {"debuge", MASK_DEBUG_E, \
625 NULL}, \
626 {"debugf", MASK_DEBUG_F, \
627 NULL}, \
628 {"debugg", MASK_DEBUG_G, \
629 NULL}, \
630 {"debugi", MASK_DEBUG_I, \
631 NULL}, \
632 {"", (TARGET_DEFAULT \
633 | TARGET_CPU_DEFAULT \
634 | TARGET_ENDIAN_DEFAULT), \
635 NULL}, \
636 }
637
638 /* Default target_flags if no switches are specified */
639
640 #ifndef TARGET_DEFAULT
641 #define TARGET_DEFAULT 0
642 #endif
643
644 #ifndef TARGET_CPU_DEFAULT
645 #define TARGET_CPU_DEFAULT 0
646 #endif
647
648 #ifndef TARGET_ENDIAN_DEFAULT
649 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
650 #endif
651
652 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
653 #ifndef MIPS_ISA_DEFAULT
654 #ifndef MIPS_CPU_STRING_DEFAULT
655 #define MIPS_CPU_STRING_DEFAULT "from-abi"
656 #endif
657 #endif
658
659 #ifdef IN_LIBGCC2
660 #undef TARGET_64BIT
661 /* Make this compile time constant for libgcc2 */
662 #ifdef __mips64
663 #define TARGET_64BIT 1
664 #else
665 #define TARGET_64BIT 0
666 #endif
667 #endif /* IN_LIBGCC2 */
668
669 #ifndef MULTILIB_ENDIAN_DEFAULT
670 #if TARGET_ENDIAN_DEFAULT == 0
671 #define MULTILIB_ENDIAN_DEFAULT "EL"
672 #else
673 #define MULTILIB_ENDIAN_DEFAULT "EB"
674 #endif
675 #endif
676
677 #ifndef MULTILIB_ISA_DEFAULT
678 # if MIPS_ISA_DEFAULT == 1
679 # define MULTILIB_ISA_DEFAULT "mips1"
680 # else
681 # if MIPS_ISA_DEFAULT == 2
682 # define MULTILIB_ISA_DEFAULT "mips2"
683 # else
684 # if MIPS_ISA_DEFAULT == 3
685 # define MULTILIB_ISA_DEFAULT "mips3"
686 # else
687 # if MIPS_ISA_DEFAULT == 4
688 # define MULTILIB_ISA_DEFAULT "mips4"
689 # else
690 # if MIPS_ISA_DEFAULT == 32
691 # define MULTILIB_ISA_DEFAULT "mips32"
692 # else
693 # if MIPS_ISA_DEFAULT == 33
694 # define MULTILIB_ISA_DEFAULT "mips32r2"
695 # else
696 # if MIPS_ISA_DEFAULT == 64
697 # define MULTILIB_ISA_DEFAULT "mips64"
698 # else
699 # define MULTILIB_ISA_DEFAULT "mips1"
700 # endif
701 # endif
702 # endif
703 # endif
704 # endif
705 # endif
706 # endif
707 #endif
708
709 #ifndef MULTILIB_DEFAULTS
710 #define MULTILIB_DEFAULTS \
711 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
712 #endif
713
714 /* We must pass -EL to the linker by default for little endian embedded
715 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
716 linker will default to using big-endian output files. The OUTPUT_FORMAT
717 line must be in the linker script, otherwise -EB/-EL will not work. */
718
719 #ifndef ENDIAN_SPEC
720 #if TARGET_ENDIAN_DEFAULT == 0
721 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
722 #else
723 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
724 #endif
725 #endif
726
727 #define TARGET_OPTIONS \
728 { \
729 SUBTARGET_TARGET_OPTIONS \
730 { "tune=", &mips_tune_string, \
731 N_("Specify CPU for scheduling purposes"), 0}, \
732 { "arch=", &mips_arch_string, \
733 N_("Specify CPU for code generation purposes"), 0}, \
734 { "abi=", &mips_abi_string, \
735 N_("Specify an ABI"), 0}, \
736 { "ips", &mips_isa_string, \
737 N_("Specify a Standard MIPS ISA"), 0}, \
738 { "no-flush-func", &mips_cache_flush_func, \
739 N_("Don't call any cache flush functions"), 0}, \
740 { "flush-func=", &mips_cache_flush_func, \
741 N_("Specify cache flush function"), 0}, \
742 }
743
744 /* This is meant to be redefined in the host dependent files. */
745 #define SUBTARGET_TARGET_OPTIONS
746
747 /* Support for a compile-time default CPU, et cetera. The rules are:
748 --with-arch is ignored if -march is specified or a -mips is specified
749 (other than -mips16).
750 --with-tune is ignored if -mtune is specified.
751 --with-abi is ignored if -mabi is specified.
752 --with-float is ignored if -mhard-float or -msoft-float are
753 specified. */
754 #define OPTION_DEFAULT_SPECS \
755 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
756 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
757 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
758 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
759
760
761 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
762 && !TARGET_SR71K \
763 && !TARGET_MIPS16)
764
765 /* Generate three-operand multiply instructions for SImode. */
766 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
767 || TARGET_MIPS5400 \
768 || TARGET_MIPS5500 \
769 || TARGET_MIPS7000 \
770 || TARGET_MIPS9000 \
771 || ISA_MIPS32 \
772 || ISA_MIPS32R2 \
773 || ISA_MIPS64) \
774 && !TARGET_MIPS16)
775
776 /* Generate three-operand multiply instructions for DImode. */
777 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
778 && !TARGET_MIPS16)
779
780 /* Macros to decide whether certain features are available or not,
781 depending on the instruction set architecture level. */
782
783 #define HAVE_SQRT_P() (!ISA_MIPS1)
784
785 /* True if the ABI can only work with 64-bit integer registers. We
786 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
787 otherwise floating-point registers must also be 64-bit. */
788 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
789 || mips_abi == ABI_O64 \
790 || mips_abi == ABI_N32)
791
792 /* Likewise for 32-bit regs. */
793 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
794
795 /* True if symbols are 64 bits wide. At present, n64 is the only
796 ABI for which this is true. */
797 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
798
799 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
800 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
801 || ISA_MIPS4 \
802 || ISA_MIPS64)
803
804 /* ISA has branch likely instructions (eg. mips2). */
805 /* Disable branchlikely for tx39 until compare rewrite. They haven't
806 been generated up to this point. */
807 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
808 && !TARGET_MIPS5500)
809
810 /* ISA has the conditional move instructions introduced in mips4. */
811 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
812 || ISA_MIPS32 \
813 || ISA_MIPS32R2 \
814 || ISA_MIPS64) \
815 && !TARGET_MIPS5500 \
816 && !TARGET_MIPS16)
817
818 /* ISA has just the integer condition move instructions (movn,movz) */
819 #define ISA_HAS_INT_CONDMOVE 0
820
821 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
822 branch on CC, and move (both FP and non-FP) on CC. */
823 #define ISA_HAS_8CC (ISA_MIPS4 \
824 || ISA_MIPS32 \
825 || ISA_MIPS32R2 \
826 || ISA_MIPS64)
827
828 /* This is a catch all for other mips4 instructions: indexed load, the
829 FP madd and msub instructions, and the FP recip and recip sqrt
830 instructions. */
831 #define ISA_HAS_FP4 ((ISA_MIPS4 \
832 || ISA_MIPS64) \
833 && !TARGET_MIPS16)
834
835 /* ISA has conditional trap instructions. */
836 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
837 && !TARGET_MIPS16)
838
839 /* ISA has integer multiply-accumulate instructions, madd and msub. */
840 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
841 || ISA_MIPS32R2 \
842 || ISA_MIPS64 \
843 ) && !TARGET_MIPS16)
844
845 /* ISA has floating-point nmadd and nmsub instructions. */
846 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
847 || ISA_MIPS64) \
848 && (!TARGET_MIPS5400 || TARGET_MAD) \
849 && ! TARGET_MIPS16)
850
851 /* ISA has count leading zeroes/ones instruction (not implemented). */
852 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
853 || ISA_MIPS32R2 \
854 || ISA_MIPS64 \
855 ) && !TARGET_MIPS16)
856
857 /* ISA has double-word count leading zeroes/ones instruction (not
858 implemented). */
859 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
860 && !TARGET_MIPS16)
861
862 /* ISA has three operand multiply instructions that put
863 the high part in an accumulator: mulhi or mulhiu. */
864 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
865 || TARGET_MIPS5500 \
866 || TARGET_SR71K \
867 )
868
869 /* ISA has three operand multiply instructions that
870 negates the result and puts the result in an accumulator. */
871 #define ISA_HAS_MULS (TARGET_MIPS5400 \
872 || TARGET_MIPS5500 \
873 || TARGET_SR71K \
874 )
875
876 /* ISA has three operand multiply instructions that subtracts the
877 result from a 4th operand and puts the result in an accumulator. */
878 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
879 || TARGET_MIPS5500 \
880 || TARGET_SR71K \
881 )
882 /* ISA has three operand multiply instructions that the result
883 from a 4th operand and puts the result in an accumulator. */
884 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
885 || TARGET_MIPS5400 \
886 || TARGET_MIPS5500 \
887 || TARGET_SR71K \
888 )
889
890 /* ISA has 32-bit rotate right instruction. */
891 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
892 && (ISA_MIPS32R2 \
893 || TARGET_MIPS5400 \
894 || TARGET_MIPS5500 \
895 || TARGET_SR71K \
896 ))
897
898 /* ISA has 64-bit rotate right instruction. */
899 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
900 && !TARGET_MIPS16 \
901 && (TARGET_MIPS5400 \
902 || TARGET_MIPS5500 \
903 || TARGET_SR71K \
904 ))
905
906 /* ISA has data prefetch instructions. This controls use of 'pref'. */
907 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
908 || ISA_MIPS32 \
909 || ISA_MIPS32R2 \
910 || ISA_MIPS64) \
911 && !TARGET_MIPS16)
912
913 /* ISA has data indexed prefetch instructions. This controls use of
914 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
915 (prefx is a cop1x instruction, so can only be used if FP is
916 enabled.) */
917 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
918 || ISA_MIPS64) \
919 && !TARGET_MIPS16)
920
921 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
922 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
923 also requires TARGET_DOUBLE_FLOAT. */
924 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
925
926 /* ISA includes the MIPS32r2 seb and seh instructions. */
927 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
928 && (ISA_MIPS32R2 \
929 ))
930
931 /* True if the result of a load is not available to the next instruction.
932 A nop will then be needed between instructions like "lw $4,..."
933 and "addiu $4,$4,1". */
934 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
935 && !TARGET_MIPS3900 \
936 && !TARGET_MIPS16)
937
938 /* Likewise mtc1 and mfc1. */
939 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
940
941 /* Likewise floating-point comparisons. */
942 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
943
944 /* True if mflo and mfhi can be immediately followed by instructions
945 which write to the HI and LO registers.
946
947 According to MIPS specifications, MIPS ISAs I, II, and III need
948 (at least) two instructions between the reads of HI/LO and
949 instructions which write them, and later ISAs do not. Contradicting
950 the MIPS specifications, some MIPS IV processor user manuals (e.g.
951 the UM for the NEC Vr5000) document needing the instructions between
952 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
953 MIPS64 and later ISAs to have the interlocks, plus any specific
954 earlier-ISA CPUs for which CPU documentation declares that the
955 instructions are really interlocked. */
956 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
957 || ISA_MIPS32R2 \
958 || ISA_MIPS64 \
959 || TARGET_MIPS5500)
960 \f
961 /* Add -G xx support. */
962
963 #undef SWITCH_TAKES_ARG
964 #define SWITCH_TAKES_ARG(CHAR) \
965 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
966
967 #define OVERRIDE_OPTIONS override_options ()
968
969 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
970
971 /* Show we can debug even without a frame pointer. */
972 #define CAN_DEBUG_WITHOUT_FP
973 \f
974 /* Tell collect what flags to pass to nm. */
975 #ifndef NM_FLAGS
976 #define NM_FLAGS "-Bn"
977 #endif
978
979 \f
980 /* Assembler specs. */
981
982 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
983 than gas. */
984
985 #define MIPS_AS_ASM_SPEC "\
986 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
987 %{pipe: %e-pipe is not supported} \
988 %{K} %(subtarget_mips_as_asm_spec)"
989
990 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
991 rather than gas. It may be overridden by subtargets. */
992
993 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
994 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
995 #endif
996
997 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
998 assembler. */
999
1000 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1001
1002 #define SUBTARGET_TARGET_SWITCHES
1003
1004 #ifndef MIPS_ABI_DEFAULT
1005 #define MIPS_ABI_DEFAULT ABI_32
1006 #endif
1007
1008 /* Use the most portable ABI flag for the ASM specs. */
1009
1010 #if MIPS_ABI_DEFAULT == ABI_32
1011 #define MULTILIB_ABI_DEFAULT "mabi=32"
1012 #define ASM_ABI_DEFAULT_SPEC "-32"
1013 #endif
1014
1015 #if MIPS_ABI_DEFAULT == ABI_O64
1016 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1017 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1018 #endif
1019
1020 #if MIPS_ABI_DEFAULT == ABI_N32
1021 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1022 #define ASM_ABI_DEFAULT_SPEC "-n32"
1023 #endif
1024
1025 #if MIPS_ABI_DEFAULT == ABI_64
1026 #define MULTILIB_ABI_DEFAULT "mabi=64"
1027 #define ASM_ABI_DEFAULT_SPEC "-64"
1028 #endif
1029
1030 #if MIPS_ABI_DEFAULT == ABI_EABI
1031 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1032 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1033 #endif
1034
1035 /* Only ELF targets can switch the ABI. */
1036 #ifndef OBJECT_FORMAT_ELF
1037 #undef ASM_ABI_DEFAULT_SPEC
1038 #define ASM_ABI_DEFAULT_SPEC ""
1039 #endif
1040
1041 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1042 GAS_ASM_SPEC as the default, depending upon the value of
1043 TARGET_DEFAULT. */
1044
1045 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1046 /* GAS */
1047
1048 #define TARGET_ASM_SPEC "\
1049 %{mmips-as: %(mips_as_asm_spec)} \
1050 %{!mmips-as: %(gas_asm_spec)}"
1051
1052 #else /* not GAS */
1053
1054 #define TARGET_ASM_SPEC "\
1055 %{!mgas: %(mips_as_asm_spec)} \
1056 %{mgas: %(gas_asm_spec)}"
1057
1058 #endif /* not GAS */
1059
1060 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1061 to the assembler. It may be overridden by subtargets. */
1062 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1063 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1064 %{noasmopt:-O0} \
1065 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1066 #endif
1067
1068 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1069 the assembler. It may be overridden by subtargets. */
1070 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1071 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1072 %{g} %{g0} %{g1} %{g2} %{g3} \
1073 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1074 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1075 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1076 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1077 %(mdebug_asm_spec)"
1078 #endif
1079
1080 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1081 debugging info. */
1082 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1083 /* GAS */
1084 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1085 %{!gcoff*:-no-mdebug}"
1086 #else /* not GAS */
1087 #define MDEBUG_ASM_SPEC ""
1088 #endif /* not GAS */
1089
1090 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1091 overridden by subtargets. */
1092
1093 #ifndef SUBTARGET_ASM_SPEC
1094 #define SUBTARGET_ASM_SPEC ""
1095 #endif
1096
1097 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1098 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1099 whether we're using GAS. These options can only be used properly
1100 with GAS, and it is better to get an error from a non-GAS assembler
1101 than to silently generate bad code. */
1102
1103 #undef ASM_SPEC
1104 #define ASM_SPEC "\
1105 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1106 %{mips32} %{mips32r2} %{mips64} \
1107 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1108 %(subtarget_asm_optimizing_spec) \
1109 %(subtarget_asm_debugging_spec) \
1110 %{membedded-pic} \
1111 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1112 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1113 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1114 %(target_asm_spec) \
1115 %(subtarget_asm_spec)"
1116
1117 /* Extra switches sometimes passed to the linker. */
1118 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1119 will interpret it as a -b option. */
1120
1121 #ifndef LINK_SPEC
1122 #define LINK_SPEC "\
1123 %(endian_spec) \
1124 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1125 %{bestGnum} %{shared} %{non_shared}"
1126 #endif /* LINK_SPEC defined */
1127
1128
1129 /* Specs for the compiler proper */
1130
1131 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1132 overridden by subtargets. */
1133 #ifndef SUBTARGET_CC1_SPEC
1134 #define SUBTARGET_CC1_SPEC ""
1135 #endif
1136
1137 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1138
1139 #ifndef CC1_SPEC
1140 #define CC1_SPEC "\
1141 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1142 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1143 %{save-temps: } \
1144 %(subtarget_cc1_spec)"
1145 #endif
1146
1147 /* Preprocessor specs. */
1148
1149 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1150 overridden by subtargets. */
1151 #ifndef SUBTARGET_CPP_SPEC
1152 #define SUBTARGET_CPP_SPEC ""
1153 #endif
1154
1155 #define CPP_SPEC "%(subtarget_cpp_spec)"
1156
1157 /* This macro defines names of additional specifications to put in the specs
1158 that can be used in various specifications like CC1_SPEC. Its definition
1159 is an initializer with a subgrouping for each command option.
1160
1161 Each subgrouping contains a string constant, that defines the
1162 specification name, and a string constant that used by the GCC driver
1163 program.
1164
1165 Do not define this macro if it does not need to do anything. */
1166
1167 #define EXTRA_SPECS \
1168 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1169 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1170 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1171 { "gas_asm_spec", GAS_ASM_SPEC }, \
1172 { "target_asm_spec", TARGET_ASM_SPEC }, \
1173 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1174 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1175 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1176 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1177 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1178 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1179 { "endian_spec", ENDIAN_SPEC }, \
1180 SUBTARGET_EXTRA_SPECS
1181
1182 #ifndef SUBTARGET_EXTRA_SPECS
1183 #define SUBTARGET_EXTRA_SPECS
1184 #endif
1185
1186 /* If defined, this macro is an additional prefix to try after
1187 `STANDARD_EXEC_PREFIX'. */
1188
1189 #ifndef MD_EXEC_PREFIX
1190 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1191 #endif
1192
1193 #ifndef MD_STARTFILE_PREFIX
1194 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1195 #endif
1196
1197 \f
1198 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1199 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1200 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1201
1202 #ifndef PREFERRED_DEBUGGING_TYPE
1203 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1204 #endif
1205
1206 /* By default, turn on GDB extensions. */
1207 #define DEFAULT_GDB_EXTENSIONS 1
1208
1209 /* If we are passing smuggling stabs through the MIPS ECOFF object
1210 format, put a comment in front of the .stab<x> operation so
1211 that the MIPS assembler does not choke. The mips-tfile program
1212 will correctly put the stab into the object file. */
1213
1214 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1215 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1216 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1217
1218 /* Local compiler-generated symbols must have a prefix that the assembler
1219 understands. By default, this is $, although some targets (e.g.,
1220 NetBSD-ELF) need to override this. */
1221
1222 #ifndef LOCAL_LABEL_PREFIX
1223 #define LOCAL_LABEL_PREFIX "$"
1224 #endif
1225
1226 /* By default on the mips, external symbols do not have an underscore
1227 prepended, but some targets (e.g., NetBSD) require this. */
1228
1229 #ifndef USER_LABEL_PREFIX
1230 #define USER_LABEL_PREFIX ""
1231 #endif
1232
1233 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1234 since the length can run past this up to a continuation point. */
1235 #undef DBX_CONTIN_LENGTH
1236 #define DBX_CONTIN_LENGTH 1500
1237
1238 /* How to renumber registers for dbx and gdb. */
1239 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1240
1241 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1242 #define DWARF_FRAME_REGNUM(REG) (REG)
1243
1244 /* The DWARF 2 CFA column which tracks the return address. */
1245 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1246
1247 /* The DWARF 2 CFA column which tracks the return address from a
1248 signal handler context. */
1249 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1250
1251 /* Before the prologue, RA lives in r31. */
1252 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1253
1254 /* Describe how we implement __builtin_eh_return. */
1255 #define EH_RETURN_DATA_REGNO(N) \
1256 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1257
1258 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1259
1260 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1261 The default for this in 64-bit mode is 8, which causes problems with
1262 SFmode register saves. */
1263 #define DWARF_CIE_DATA_ALIGNMENT 4
1264
1265 /* Correct the offset of automatic variables and arguments. Note that
1266 the MIPS debug format wants all automatic variables and arguments
1267 to be in terms of the virtual frame pointer (stack pointer before
1268 any adjustment in the function), while the MIPS 3.0 linker wants
1269 the frame pointer to be the stack pointer after the initial
1270 adjustment. */
1271
1272 #define DEBUGGER_AUTO_OFFSET(X) \
1273 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1274 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1275 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1276 \f
1277 /* Target machine storage layout */
1278
1279 #define BITS_BIG_ENDIAN 0
1280 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1281 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1282
1283 /* Define this to set the endianness to use in libgcc2.c, which can
1284 not depend on target_flags. */
1285 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1286 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1287 #else
1288 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1289 #endif
1290
1291 #define MAX_BITS_PER_WORD 64
1292
1293 /* Width of a word, in units (bytes). */
1294 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1295 #define MIN_UNITS_PER_WORD 4
1296
1297 /* For MIPS, width of a floating point register. */
1298 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1299
1300 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1301 the next available register. */
1302 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1303
1304 /* The largest size of value that can be held in floating-point
1305 registers and moved with a single instruction. */
1306 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1307
1308 /* The largest size of value that can be held in floating-point
1309 registers. */
1310 #define UNITS_PER_FPVALUE \
1311 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1312
1313 /* The number of bytes in a double. */
1314 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1315
1316 /* Tell the preprocessor the maximum size of wchar_t. */
1317 #ifndef MAX_WCHAR_TYPE_SIZE
1318 #ifndef WCHAR_TYPE_SIZE
1319 #define MAX_WCHAR_TYPE_SIZE 64
1320 #endif
1321 #endif
1322
1323 /* Set the sizes of the core types. */
1324 #define SHORT_TYPE_SIZE 16
1325 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1326 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1327 #define LONG_LONG_TYPE_SIZE 64
1328
1329 #define MAX_LONG_TYPE_SIZE 64
1330
1331 #define FLOAT_TYPE_SIZE 32
1332 #define DOUBLE_TYPE_SIZE 64
1333 #define LONG_DOUBLE_TYPE_SIZE \
1334 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1335
1336 /* long double is not a fixed mode, but the idea is that, if we
1337 support long double, we also want a 128-bit integer type. */
1338 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1339
1340 #ifdef IN_LIBGCC2
1341 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1342 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1343 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1344 # else
1345 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1346 # endif
1347 #endif
1348
1349 /* Width in bits of a pointer. */
1350 #ifndef POINTER_SIZE
1351 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1352 #endif
1353
1354 #define POINTERS_EXTEND_UNSIGNED 0
1355
1356 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1357 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1358 || mips_abi == ABI_64 \
1359 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1360
1361
1362 /* Allocation boundary (in *bits*) for the code of a function. */
1363 #define FUNCTION_BOUNDARY 32
1364
1365 /* Alignment of field after `int : 0' in a structure. */
1366 #define EMPTY_FIELD_BOUNDARY 32
1367
1368 /* Every structure's size must be a multiple of this. */
1369 /* 8 is observed right on a DECstation and on riscos 4.02. */
1370 #define STRUCTURE_SIZE_BOUNDARY 8
1371
1372 /* There is no point aligning anything to a rounder boundary than this. */
1373 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1374
1375 /* All accesses must be aligned. */
1376 #define STRICT_ALIGNMENT 1
1377
1378 /* Define this if you wish to imitate the way many other C compilers
1379 handle alignment of bitfields and the structures that contain
1380 them.
1381
1382 The behavior is that the type written for a bit-field (`int',
1383 `short', or other integer type) imposes an alignment for the
1384 entire structure, as if the structure really did contain an
1385 ordinary field of that type. In addition, the bit-field is placed
1386 within the structure so that it would fit within such a field,
1387 not crossing a boundary for it.
1388
1389 Thus, on most machines, a bit-field whose type is written as `int'
1390 would not cross a four-byte boundary, and would force four-byte
1391 alignment for the whole structure. (The alignment used may not
1392 be four bytes; it is controlled by the other alignment
1393 parameters.)
1394
1395 If the macro is defined, its definition should be a C expression;
1396 a nonzero value for the expression enables this behavior. */
1397
1398 #define PCC_BITFIELD_TYPE_MATTERS 1
1399
1400 /* If defined, a C expression to compute the alignment given to a
1401 constant that is being placed in memory. CONSTANT is the constant
1402 and ALIGN is the alignment that the object would ordinarily have.
1403 The value of this macro is used instead of that alignment to align
1404 the object.
1405
1406 If this macro is not defined, then ALIGN is used.
1407
1408 The typical use of this macro is to increase alignment for string
1409 constants to be word aligned so that `strcpy' calls that copy
1410 constants can be done inline. */
1411
1412 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1413 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1414 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1415
1416 /* If defined, a C expression to compute the alignment for a static
1417 variable. TYPE is the data type, and ALIGN is the alignment that
1418 the object would ordinarily have. The value of this macro is used
1419 instead of that alignment to align the object.
1420
1421 If this macro is not defined, then ALIGN is used.
1422
1423 One use of this macro is to increase alignment of medium-size
1424 data to make it all fit in fewer cache lines. Another is to
1425 cause character arrays to be word-aligned so that `strcpy' calls
1426 that copy constants to character arrays can be done inline. */
1427
1428 #undef DATA_ALIGNMENT
1429 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1430 ((((ALIGN) < BITS_PER_WORD) \
1431 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1432 || TREE_CODE (TYPE) == UNION_TYPE \
1433 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1434
1435
1436 #define PAD_VARARGS_DOWN \
1437 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1438
1439 /* Define if operations between registers always perform the operation
1440 on the full register even if a narrower mode is specified. */
1441 #define WORD_REGISTER_OPERATIONS
1442
1443 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1444 moves. All other references are zero extended. */
1445 #define LOAD_EXTEND_OP(MODE) \
1446 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1447 ? SIGN_EXTEND : ZERO_EXTEND)
1448
1449 /* Define this macro if it is advisable to hold scalars in registers
1450 in a wider mode than that declared by the program. In such cases,
1451 the value is constrained to be within the bounds of the declared
1452 type, but kept valid in the wider mode. The signedness of the
1453 extension may differ from that of the type. */
1454
1455 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1456 if (GET_MODE_CLASS (MODE) == MODE_INT \
1457 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1458 { \
1459 if ((MODE) == SImode) \
1460 (UNSIGNEDP) = 0; \
1461 (MODE) = Pmode; \
1462 }
1463
1464 /* Define if loading short immediate values into registers sign extends. */
1465 #define SHORT_IMMEDIATES_SIGN_EXTEND
1466 \f
1467 /* Standard register usage. */
1468
1469 /* Number of hardware registers. We have:
1470
1471 - 32 integer registers
1472 - 32 floating point registers
1473 - 8 condition code registers
1474 - 2 accumulator registers (hi and lo)
1475 - 32 registers each for coprocessors 0, 2 and 3
1476 - 3 fake registers:
1477 - ARG_POINTER_REGNUM
1478 - FRAME_POINTER_REGNUM
1479 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1480 - 3 dummy entries that were used at various times in the past. */
1481
1482 #define FIRST_PSEUDO_REGISTER 176
1483
1484 /* By default, fix the kernel registers ($26 and $27), the global
1485 pointer ($28) and the stack pointer ($29). This can change
1486 depending on the command-line options.
1487
1488 Regarding coprocessor registers: without evidence to the contrary,
1489 it's best to assume that each coprocessor register has a unique
1490 use. This can be overridden, in, e.g., override_options() or
1491 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1492 for a particular target. */
1493
1494 #define FIXED_REGISTERS \
1495 { \
1496 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1499 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1500 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1501 /* COP0 registers */ \
1502 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1503 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1504 /* COP2 registers */ \
1505 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1506 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1507 /* COP3 registers */ \
1508 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1510 }
1511
1512
1513 /* Set up this array for o32 by default.
1514
1515 Note that we don't mark $31 as a call-clobbered register. The idea is
1516 that it's really the call instructions themselves which clobber $31.
1517 We don't care what the called function does with it afterwards.
1518
1519 This approach makes it easier to implement sibcalls. Unlike normal
1520 calls, sibcalls don't clobber $31, so the register reaches the
1521 called function in tact. EPILOGUE_USES says that $31 is useful
1522 to the called function. */
1523
1524 #define CALL_USED_REGISTERS \
1525 { \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 /* COP0 registers */ \
1532 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 /* COP2 registers */ \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 /* COP3 registers */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1540 }
1541
1542
1543 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1544
1545 #define CALL_REALLY_USED_REGISTERS \
1546 { /* General registers. */ \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1549 /* Floating-point registers. */ \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1552 /* Others. */ \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 /* COP0 registers */ \
1555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1557 /* COP2 registers */ \
1558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1560 /* COP3 registers */ \
1561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1562 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1563 }
1564
1565 /* Internal macros to classify a register number as to whether it's a
1566 general purpose register, a floating point register, a
1567 multiply/divide register, or a status register. */
1568
1569 #define GP_REG_FIRST 0
1570 #define GP_REG_LAST 31
1571 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1572 #define GP_DBX_FIRST 0
1573
1574 #define FP_REG_FIRST 32
1575 #define FP_REG_LAST 63
1576 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1577 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1578
1579 #define MD_REG_FIRST 64
1580 #define MD_REG_LAST 65
1581 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1582 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1583
1584 #define ST_REG_FIRST 67
1585 #define ST_REG_LAST 74
1586 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1587
1588
1589 /* FIXME: renumber. */
1590 #define COP0_REG_FIRST 80
1591 #define COP0_REG_LAST 111
1592 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1593
1594 #define COP2_REG_FIRST 112
1595 #define COP2_REG_LAST 143
1596 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1597
1598 #define COP3_REG_FIRST 144
1599 #define COP3_REG_LAST 175
1600 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1601 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1602 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1603
1604 #define AT_REGNUM (GP_REG_FIRST + 1)
1605 #define HI_REGNUM (MD_REG_FIRST + 0)
1606 #define LO_REGNUM (MD_REG_FIRST + 1)
1607
1608 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1609 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1610 should be used instead. */
1611 #define FPSW_REGNUM ST_REG_FIRST
1612
1613 #define GP_REG_P(REGNO) \
1614 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1615 #define M16_REG_P(REGNO) \
1616 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1617 #define FP_REG_P(REGNO) \
1618 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1619 #define MD_REG_P(REGNO) \
1620 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1621 #define ST_REG_P(REGNO) \
1622 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1623 #define COP0_REG_P(REGNO) \
1624 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1625 #define COP2_REG_P(REGNO) \
1626 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1627 #define COP3_REG_P(REGNO) \
1628 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1629 #define ALL_COP_REG_P(REGNO) \
1630 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1631
1632 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1633
1634 /* Return coprocessor number from register number. */
1635
1636 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1637 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1638 : COP3_REG_P (REGNO) ? '3' : '?')
1639
1640
1641 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1642
1643 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1644 array built in override_options. Because machmodes.h is not yet
1645 included before this file is processed, the MODE bound can't be
1646 expressed here. */
1647
1648 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1649
1650 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1651 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1652
1653 /* Value is 1 if it is a good idea to tie two pseudo registers
1654 when one has mode MODE1 and one has mode MODE2.
1655 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1656 for any hard reg, then this must be 0 for correct output. */
1657 #define MODES_TIEABLE_P(MODE1, MODE2) \
1658 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1659 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1660 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1661 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1662
1663 /* Register to use for pushing function arguments. */
1664 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1665
1666 /* These two registers don't really exist: they get eliminated to either
1667 the stack or hard frame pointer. */
1668 #define ARG_POINTER_REGNUM 77
1669 #define FRAME_POINTER_REGNUM 78
1670
1671 /* $30 is not available on the mips16, so we use $17 as the frame
1672 pointer. */
1673 #define HARD_FRAME_POINTER_REGNUM \
1674 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1675
1676 /* Value should be nonzero if functions must have frame pointers.
1677 Zero means the frame pointer need not be set up (and parms
1678 may be accessed via the stack pointer) in functions that seem suitable.
1679 This is computed in `reload', in reload1.c. */
1680 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1681
1682 /* Register in which static-chain is passed to a function. */
1683 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1684
1685 /* Registers used as temporaries in prologue/epilogue code. If we're
1686 generating mips16 code, these registers must come from the core set
1687 of 8. The prologue register mustn't conflict with any incoming
1688 arguments, the static chain pointer, or the frame pointer. The
1689 epilogue temporary mustn't conflict with the return registers, the
1690 frame pointer, the EH stack adjustment, or the EH data registers. */
1691
1692 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1693 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1694
1695 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1696 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1697
1698 /* Define this macro if it is as good or better to call a constant
1699 function address than to call an address kept in a register. */
1700 #define NO_FUNCTION_CSE 1
1701
1702 /* Define this macro if it is as good or better for a function to
1703 call itself with an explicit address than to call an address
1704 kept in a register. */
1705 #define NO_RECURSIVE_FUNCTION_CSE 1
1706
1707 /* The ABI-defined global pointer. Sometimes we use a different
1708 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1709 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1710
1711 /* We normally use $28 as the global pointer. However, when generating
1712 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1713 register instead. They can then avoid saving and restoring $28
1714 and perhaps avoid using a frame at all.
1715
1716 When a leaf function uses something other than $28, mips_expand_prologue
1717 will modify pic_offset_table_rtx in place. Take the register number
1718 from there after reload. */
1719 #define PIC_OFFSET_TABLE_REGNUM \
1720 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1721
1722 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1723 \f
1724 /* Define the classes of registers for register constraints in the
1725 machine description. Also define ranges of constants.
1726
1727 One of the classes must always be named ALL_REGS and include all hard regs.
1728 If there is more than one class, another class must be named NO_REGS
1729 and contain no registers.
1730
1731 The name GENERAL_REGS must be the name of a class (or an alias for
1732 another name such as ALL_REGS). This is the class of registers
1733 that is allowed by "g" or "r" in a register constraint.
1734 Also, registers outside this class are allocated only when
1735 instructions express preferences for them.
1736
1737 The classes must be numbered in nondecreasing order; that is,
1738 a larger-numbered class must never be contained completely
1739 in a smaller-numbered class.
1740
1741 For any two classes, it is very desirable that there be another
1742 class that represents their union. */
1743
1744 enum reg_class
1745 {
1746 NO_REGS, /* no registers in set */
1747 M16_NA_REGS, /* mips16 regs not used to pass args */
1748 M16_REGS, /* mips16 directly accessible registers */
1749 T_REG, /* mips16 T register ($24) */
1750 M16_T_REGS, /* mips16 registers plus T register */
1751 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1752 LEA_REGS, /* Every GPR except $25 */
1753 GR_REGS, /* integer registers */
1754 FP_REGS, /* floating point registers */
1755 HI_REG, /* hi register */
1756 LO_REG, /* lo register */
1757 MD_REGS, /* multiply/divide registers (hi/lo) */
1758 COP0_REGS, /* generic coprocessor classes */
1759 COP2_REGS,
1760 COP3_REGS,
1761 HI_AND_GR_REGS, /* union classes */
1762 LO_AND_GR_REGS,
1763 HI_AND_FP_REGS,
1764 COP0_AND_GR_REGS,
1765 COP2_AND_GR_REGS,
1766 COP3_AND_GR_REGS,
1767 ALL_COP_REGS,
1768 ALL_COP_AND_GR_REGS,
1769 ST_REGS, /* status registers (fp status) */
1770 ALL_REGS, /* all registers */
1771 LIM_REG_CLASSES /* max value + 1 */
1772 };
1773
1774 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1775
1776 #define GENERAL_REGS GR_REGS
1777
1778 /* An initializer containing the names of the register classes as C
1779 string constants. These names are used in writing some of the
1780 debugging dumps. */
1781
1782 #define REG_CLASS_NAMES \
1783 { \
1784 "NO_REGS", \
1785 "M16_NA_REGS", \
1786 "M16_REGS", \
1787 "T_REG", \
1788 "M16_T_REGS", \
1789 "PIC_FN_ADDR_REG", \
1790 "LEA_REGS", \
1791 "GR_REGS", \
1792 "FP_REGS", \
1793 "HI_REG", \
1794 "LO_REG", \
1795 "MD_REGS", \
1796 /* coprocessor registers */ \
1797 "COP0_REGS", \
1798 "COP2_REGS", \
1799 "COP3_REGS", \
1800 "HI_AND_GR_REGS", \
1801 "LO_AND_GR_REGS", \
1802 "HI_AND_FP_REGS", \
1803 "COP0_AND_GR_REGS", \
1804 "COP2_AND_GR_REGS", \
1805 "COP3_AND_GR_REGS", \
1806 "ALL_COP_REGS", \
1807 "ALL_COP_AND_GR_REGS", \
1808 "ST_REGS", \
1809 "ALL_REGS" \
1810 }
1811
1812 /* An initializer containing the contents of the register classes,
1813 as integers which are bit masks. The Nth integer specifies the
1814 contents of class N. The way the integer MASK is interpreted is
1815 that register R is in the class if `MASK & (1 << R)' is 1.
1816
1817 When the machine has more than 32 registers, an integer does not
1818 suffice. Then the integers are replaced by sub-initializers,
1819 braced groupings containing several integers. Each
1820 sub-initializer must be suitable as an initializer for the type
1821 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1822
1823 #define REG_CLASS_CONTENTS \
1824 { \
1825 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1826 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1827 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1828 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1829 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1830 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1831 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1832 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1833 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1834 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1835 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1836 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1837 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1838 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1839 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1840 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1841 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1842 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1843 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1844 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1845 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1846 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1847 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1848 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1849 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1850 }
1851
1852
1853 /* A C expression whose value is a register class containing hard
1854 register REGNO. In general there is more that one such class;
1855 choose a class which is "minimal", meaning that no smaller class
1856 also contains the register. */
1857
1858 extern const enum reg_class mips_regno_to_class[];
1859
1860 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1861
1862 /* A macro whose definition is the name of the class to which a
1863 valid base register must belong. A base register is one used in
1864 an address which is the register value plus a displacement. */
1865
1866 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1867
1868 /* A macro whose definition is the name of the class to which a
1869 valid index register must belong. An index register is one used
1870 in an address where its value is either multiplied by a scale
1871 factor or added to another register (as well as added to a
1872 displacement). */
1873
1874 #define INDEX_REG_CLASS NO_REGS
1875
1876 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1877 registers explicitly used in the rtl to be used as spill registers
1878 but prevents the compiler from extending the lifetime of these
1879 registers. */
1880
1881 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1882
1883 /* This macro is used later on in the file. */
1884 #define GR_REG_CLASS_P(CLASS) \
1885 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1886 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1887 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1888
1889 /* This macro is also used later on in the file. */
1890 #define COP_REG_CLASS_P(CLASS) \
1891 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1892
1893 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1894 is the default value (allocate the registers in numeric order). We
1895 define it just so that we can override it for the mips16 target in
1896 ORDER_REGS_FOR_LOCAL_ALLOC. */
1897
1898 #define REG_ALLOC_ORDER \
1899 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1900 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1901 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1902 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1903 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1904 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1905 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1906 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1907 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1908 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1909 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1910 }
1911
1912 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1913 to be rearranged based on a particular function. On the mips16, we
1914 want to allocate $24 (T_REG) before other registers for
1915 instructions for which it is possible. */
1916
1917 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1918
1919 /* REGISTER AND CONSTANT CLASSES */
1920
1921 /* Get reg_class from a letter such as appears in the machine
1922 description.
1923
1924 DEFINED REGISTER CLASSES:
1925
1926 'd' General (aka integer) registers
1927 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1928 'y' General registers (in both mips16 and non mips16 mode)
1929 'e' mips16 non argument registers (M16_NA_REGS)
1930 't' mips16 temporary register ($24)
1931 'f' Floating point registers
1932 'h' Hi register
1933 'l' Lo register
1934 'x' Multiply/divide registers
1935 'z' FP Status register
1936 'B' Cop0 register
1937 'C' Cop2 register
1938 'D' Cop3 register
1939 'b' All registers */
1940
1941 extern enum reg_class mips_char_to_class[256];
1942
1943 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1944
1945 /* True if VALUE is a signed 16-bit number. */
1946
1947 #define SMALL_OPERAND(VALUE) \
1948 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1949
1950 /* True if VALUE is an unsigned 16-bit number. */
1951
1952 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1953 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1954
1955 /* True if VALUE can be loaded into a register using LUI. */
1956
1957 #define LUI_OPERAND(VALUE) \
1958 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1959 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1960
1961 /* Return a value X with the low 16 bits clear, and such that
1962 VALUE - X is a signed 16-bit value. */
1963
1964 #define CONST_HIGH_PART(VALUE) \
1965 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1966
1967 #define CONST_LOW_PART(VALUE) \
1968 ((VALUE) - CONST_HIGH_PART (VALUE))
1969
1970 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1971 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1972 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1973
1974 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1975 string can be used to stand for particular ranges of immediate
1976 operands. This macro defines what the ranges are. C is the
1977 letter, and VALUE is a constant value. Return 1 if VALUE is
1978 in the range specified by C. */
1979
1980 /* For MIPS:
1981
1982 `I' is used for the range of constants an arithmetic insn can
1983 actually contain (16 bits signed integers).
1984
1985 `J' is used for the range which is just zero (ie, $r0).
1986
1987 `K' is used for the range of constants a logical insn can actually
1988 contain (16 bit zero-extended integers).
1989
1990 `L' is used for the range of constants that be loaded with lui
1991 (ie, the bottom 16 bits are zero).
1992
1993 `M' is used for the range of constants that take two words to load
1994 (ie, not matched by `I', `K', and `L').
1995
1996 `N' is used for negative 16 bit constants other than -65536.
1997
1998 `O' is a 15 bit signed integer.
1999
2000 `P' is used for positive 16 bit constants. */
2001
2002 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2003 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2004 : (C) == 'J' ? ((VALUE) == 0) \
2005 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2006 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2007 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2008 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2009 && !LUI_OPERAND (VALUE)) \
2010 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2011 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2012 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2013 : 0)
2014
2015 /* Similar, but for floating constants, and defining letters G and H.
2016 Here VALUE is the CONST_DOUBLE rtx itself. */
2017
2018 /* For Mips
2019
2020 'G' : Floating point 0 */
2021
2022 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2023 ((C) == 'G' \
2024 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2025
2026 /* Letters in the range `Q' through `U' may be defined in a
2027 machine-dependent fashion to stand for arbitrary operand types.
2028 The machine description macro `EXTRA_CONSTRAINT' is passed the
2029 operand as its first argument and the constraint letter as its
2030 second operand.
2031
2032 `Q' is for signed 16-bit constants.
2033 `R' is for single-instruction memory references. Note that this
2034 constraint has often been used in linux and glibc code.
2035 `S' is for legitimate constant call addresses.
2036 `T' is for constant move_operands that cannot be safely loaded into $25.
2037 `U' is for constant move_operands that can be safely loaded into $25.
2038 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2039 This is true for all non-mips16 references (although it can somtimes
2040 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2041 stack and constant-pool references. */
2042
2043 #define EXTRA_CONSTRAINT(OP,CODE) \
2044 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2045 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2046 && mips_fetch_insns (OP) == 1) \
2047 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2048 && call_insn_operand (OP, VOIDmode)) \
2049 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2050 && move_operand (OP, VOIDmode) \
2051 && mips_dangerous_for_la25_p (OP)) \
2052 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2053 && move_operand (OP, VOIDmode) \
2054 && !mips_dangerous_for_la25_p (OP)) \
2055 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2056 && memory_operand (OP, VOIDmode) \
2057 && (!TARGET_MIPS16 \
2058 || (!stack_operand (OP, VOIDmode) \
2059 && !CONSTANT_P (XEXP (OP, 0))))) \
2060 : FALSE)
2061
2062 /* Say which of the above are memory constraints. */
2063 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2064
2065 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2066 mips_preferred_reload_class (X, CLASS)
2067
2068 /* Certain machines have the property that some registers cannot be
2069 copied to some other registers without using memory. Define this
2070 macro on those machines to be a C expression that is nonzero if
2071 objects of mode MODE in registers of CLASS1 can only be copied to
2072 registers of class CLASS2 by storing a register of CLASS1 into
2073 memory and loading that memory location into a register of CLASS2.
2074
2075 Do not define this macro if its value would always be zero. */
2076 #if 0
2077 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2078 ((!TARGET_DEBUG_H_MODE \
2079 && GET_MODE_CLASS (MODE) == MODE_INT \
2080 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2081 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2082 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2083 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2084 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2085 #endif
2086 /* The HI and LO registers can only be reloaded via the general
2087 registers. Condition code registers can only be loaded to the
2088 general registers, and from the floating point registers. */
2089
2090 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2091 mips_secondary_reload_class (CLASS, MODE, X, 1)
2092 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2093 mips_secondary_reload_class (CLASS, MODE, X, 0)
2094
2095 /* Return the maximum number of consecutive registers
2096 needed to represent mode MODE in a register of class CLASS. */
2097
2098 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2099
2100 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2101 mips_cannot_change_mode_class (FROM, TO, CLASS)
2102 \f
2103 /* Stack layout; function entry, exit and calling. */
2104
2105 #define STACK_GROWS_DOWNWARD
2106
2107 /* The offset of the first local variable from the beginning of the frame.
2108 See compute_frame_size for details about the frame layout. */
2109 #define STARTING_FRAME_OFFSET \
2110 (current_function_outgoing_args_size \
2111 + (TARGET_ABICALLS && !TARGET_NEWABI \
2112 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2113
2114 #define RETURN_ADDR_RTX mips_return_addr
2115
2116 /* Since the mips16 ISA mode is encoded in the least-significant bit
2117 of the address, mask it off return addresses for purposes of
2118 finding exception handling regions. */
2119
2120 #define MASK_RETURN_ADDR GEN_INT (-2)
2121
2122
2123 /* Similarly, don't use the least-significant bit to tell pointers to
2124 code from vtable index. */
2125
2126 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2127
2128 /* The eliminations to $17 are only used for mips16 code. See the
2129 definition of HARD_FRAME_POINTER_REGNUM. */
2130
2131 #define ELIMINABLE_REGS \
2132 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2133 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2134 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2135 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2136 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2137 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2138
2139 /* We can always eliminate to the hard frame pointer. We can eliminate
2140 to the stack pointer unless a frame pointer is needed.
2141
2142 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2143 reload may be unable to compute the address of a local variable,
2144 since there is no way to add a large constant to the stack pointer
2145 without using a temporary register. */
2146 #define CAN_ELIMINATE(FROM, TO) \
2147 ((TO) == HARD_FRAME_POINTER_REGNUM \
2148 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2149 && (!TARGET_MIPS16 \
2150 || compute_frame_size (get_frame_size ()) < 32768)))
2151
2152 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2153 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2154
2155 /* Allocate stack space for arguments at the beginning of each function. */
2156 #define ACCUMULATE_OUTGOING_ARGS 1
2157
2158 /* The argument pointer always points to the first argument. */
2159 #define FIRST_PARM_OFFSET(FNDECL) 0
2160
2161 /* o32 and o64 reserve stack space for all argument registers. */
2162 #define REG_PARM_STACK_SPACE(FNDECL) \
2163 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2164 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2165 : 0)
2166
2167 /* Define this if it is the responsibility of the caller to
2168 allocate the area reserved for arguments passed in registers.
2169 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2170 of this macro is to determine whether the space is included in
2171 `current_function_outgoing_args_size'. */
2172 #define OUTGOING_REG_PARM_STACK_SPACE
2173
2174 #define STACK_BOUNDARY \
2175 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2176 ? 64 : 128)
2177
2178 \f
2179 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2180
2181 /* Symbolic macros for the registers used to return integer and floating
2182 point values. */
2183
2184 #define GP_RETURN (GP_REG_FIRST + 2)
2185 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2186
2187 #define MAX_ARGS_IN_REGISTERS \
2188 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2189
2190 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2191
2192 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2193
2194 /* Symbolic macros for the first/last argument registers. */
2195
2196 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2197 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2198 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2199 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2200
2201 #define LIBCALL_VALUE(MODE) \
2202 mips_function_value (NULL_TREE, NULL, (MODE))
2203
2204 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2205 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2206
2207 /* 1 if N is a possible register number for a function value.
2208 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2209 Currently, R2 and F0 are only implemented here (C has no complex type) */
2210
2211 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2212 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2213 && (N) == FP_RETURN + 2))
2214
2215 /* 1 if N is a possible register number for function argument passing.
2216 We have no FP argument registers when soft-float. When FP registers
2217 are 32 bits, we can't directly reference the odd numbered ones. */
2218
2219 #define FUNCTION_ARG_REGNO_P(N) \
2220 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2221 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2222 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2223 && !fixed_regs[N])
2224 \f
2225 /* This structure has to cope with two different argument allocation
2226 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2227 first N words go in registers and the rest go on the stack. If I < N,
2228 the Ith word might go in Ith integer argument register or the
2229 Ith floating-point one. For these ABIs, we only need to remember
2230 the number of words passed so far.
2231
2232 The EABI instead allocates the integer and floating-point arguments
2233 separately. The first N words of FP arguments go in FP registers,
2234 the rest go on the stack. Likewise, the first N words of the other
2235 arguments go in integer registers, and the rest go on the stack. We
2236 need to maintain three counts: the number of integer registers used,
2237 the number of floating-point registers used, and the number of words
2238 passed on the stack.
2239
2240 We could keep separate information for the two ABIs (a word count for
2241 the standard ABIs, and three separate counts for the EABI). But it
2242 seems simpler to view the standard ABIs as forms of EABI that do not
2243 allocate floating-point registers.
2244
2245 So for the standard ABIs, the first N words are allocated to integer
2246 registers, and function_arg decides on an argument-by-argument basis
2247 whether that argument should really go in an integer register, or in
2248 a floating-point one. */
2249
2250 typedef struct mips_args {
2251 /* Always true for varargs functions. Otherwise true if at least
2252 one argument has been passed in an integer register. */
2253 int gp_reg_found;
2254
2255 /* The number of arguments seen so far. */
2256 unsigned int arg_number;
2257
2258 /* For EABI, the number of integer registers used so far. For other
2259 ABIs, the number of words passed in registers (whether integer
2260 or floating-point). */
2261 unsigned int num_gprs;
2262
2263 /* For EABI, the number of floating-point registers used so far. */
2264 unsigned int num_fprs;
2265
2266 /* The number of words passed on the stack. */
2267 unsigned int stack_words;
2268
2269 /* On the mips16, we need to keep track of which floating point
2270 arguments were passed in general registers, but would have been
2271 passed in the FP regs if this were a 32 bit function, so that we
2272 can move them to the FP regs if we wind up calling a 32 bit
2273 function. We record this information in fp_code, encoded in base
2274 four. A zero digit means no floating point argument, a one digit
2275 means an SFmode argument, and a two digit means a DFmode argument,
2276 and a three digit is not used. The low order digit is the first
2277 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2278 an SFmode argument. ??? A more sophisticated approach will be
2279 needed if MIPS_ABI != ABI_32. */
2280 int fp_code;
2281
2282 /* True if the function has a prototype. */
2283 int prototype;
2284 } CUMULATIVE_ARGS;
2285
2286 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2287 for a call to a function whose data type is FNTYPE.
2288 For a library call, FNTYPE is 0. */
2289
2290 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2291 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2292
2293 /* Update the data in CUM to advance over an argument
2294 of mode MODE and data type TYPE.
2295 (TYPE is null for libcalls where that information may not be available.) */
2296
2297 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2298 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2299
2300 /* Determine where to put an argument to a function.
2301 Value is zero to push the argument on the stack,
2302 or a hard register in which to store the argument.
2303
2304 MODE is the argument's machine mode.
2305 TYPE is the data type of the argument (as a tree).
2306 This is null for libcalls where that information may
2307 not be available.
2308 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2309 the preceding args and about the function being called.
2310 NAMED is nonzero if this argument is a named parameter
2311 (otherwise it is an extra parameter matching an ellipsis). */
2312
2313 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2314 function_arg( &CUM, MODE, TYPE, NAMED)
2315
2316 /* For an arg passed partly in registers and partly in memory,
2317 this is the number of registers used.
2318 For args passed entirely in registers or entirely in memory, zero. */
2319
2320 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2321 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2322
2323 /* If defined, a C expression that gives the alignment boundary, in
2324 bits, of an argument with the specified mode and type. If it is
2325 not defined, `PARM_BOUNDARY' is used for all arguments. */
2326
2327 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2328 (((TYPE) != 0) \
2329 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2330 ? PARM_BOUNDARY \
2331 : TYPE_ALIGN(TYPE)) \
2332 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2333 ? PARM_BOUNDARY \
2334 : GET_MODE_ALIGNMENT(MODE)))
2335
2336 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2337 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2338
2339 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2340 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2341
2342 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2343 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2344
2345 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2346 (mips_abi == ABI_EABI && (NAMED) \
2347 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2348
2349 /* Modified version of the macro in expr.h. Only return true if
2350 the type has a variable size or if the front end requires it
2351 to be passed by reference. */
2352 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2353 ((TYPE) != 0 \
2354 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2355 || TREE_ADDRESSABLE (TYPE)))
2356
2357 /* True if using EABI and varargs can be passed in floating-point
2358 registers. Under these conditions, we need a more complex form
2359 of va_list, which tracks GPR, FPR and stack arguments separately. */
2360 #define EABI_FLOAT_VARARGS_P \
2361 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2362
2363 \f
2364 /* Say that the epilogue uses the return address register. Note that
2365 in the case of sibcalls, the values "used by the epilogue" are
2366 considered live at the start of the called function. */
2367 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2368
2369 /* Treat LOC as a byte offset from the stack pointer and round it up
2370 to the next fully-aligned offset. */
2371 #define MIPS_STACK_ALIGN(LOC) \
2372 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2373 ? ((LOC) + 7) & ~7 \
2374 : ((LOC) + 15) & ~15)
2375
2376 \f
2377 /* Implement `va_start' for varargs and stdarg. */
2378 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2379 mips_va_start (valist, nextarg)
2380
2381 /* Implement `va_arg'. */
2382 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2383 mips_va_arg (valist, type)
2384 \f
2385 /* Output assembler code to FILE to increment profiler label # LABELNO
2386 for profiling a function entry. */
2387
2388 #define FUNCTION_PROFILER(FILE, LABELNO) \
2389 { \
2390 if (TARGET_MIPS16) \
2391 sorry ("mips16 function profiling"); \
2392 fprintf (FILE, "\t.set\tnoat\n"); \
2393 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2394 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2395 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2396 { \
2397 fprintf (FILE, \
2398 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2399 TARGET_64BIT ? "dsubu" : "subu", \
2400 reg_names[STACK_POINTER_REGNUM], \
2401 reg_names[STACK_POINTER_REGNUM], \
2402 Pmode == DImode ? 16 : 8); \
2403 } \
2404 fprintf (FILE, "\tjal\t_mcount\n"); \
2405 fprintf (FILE, "\t.set\tat\n"); \
2406 }
2407
2408 /* Define this macro if the code for function profiling should come
2409 before the function prologue. Normally, the profiling code comes
2410 after. */
2411
2412 /* #define PROFILE_BEFORE_PROLOGUE */
2413
2414 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2415 the stack pointer does not matter. The value is tested only in
2416 functions that have frame pointers.
2417 No definition is equivalent to always zero. */
2418
2419 #define EXIT_IGNORE_STACK 1
2420
2421 \f
2422 /* A C statement to output, on the stream FILE, assembler code for a
2423 block of data that contains the constant parts of a trampoline.
2424 This code should not include a label--the label is taken care of
2425 automatically. */
2426
2427 #define TRAMPOLINE_TEMPLATE(STREAM) \
2428 { \
2429 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2430 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2431 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2432 if (ptr_mode == DImode) \
2433 { \
2434 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2435 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2436 } \
2437 else \
2438 { \
2439 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2440 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2441 } \
2442 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2443 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2444 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2445 if (ptr_mode == DImode) \
2446 { \
2447 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2448 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2449 } \
2450 else \
2451 { \
2452 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2453 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2454 } \
2455 }
2456
2457 /* A C expression for the size in bytes of the trampoline, as an
2458 integer. */
2459
2460 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2461
2462 /* Alignment required for trampolines, in bits. */
2463
2464 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2465
2466 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2467 program and data caches. */
2468
2469 #ifndef CACHE_FLUSH_FUNC
2470 #define CACHE_FLUSH_FUNC "_flush_cache"
2471 #endif
2472
2473 /* A C statement to initialize the variable parts of a trampoline.
2474 ADDR is an RTX for the address of the trampoline; FNADDR is an
2475 RTX for the address of the nested function; STATIC_CHAIN is an
2476 RTX for the static chain value that should be passed to the
2477 function when it is called. */
2478
2479 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2480 { \
2481 rtx func_addr, chain_addr; \
2482 \
2483 func_addr = plus_constant (ADDR, 32); \
2484 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2485 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2486 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2487 \
2488 /* Flush both caches. We need to flush the data cache in case \
2489 the system has a write-back cache. */ \
2490 /* ??? Should check the return value for errors. */ \
2491 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2492 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2493 0, VOIDmode, 3, ADDR, Pmode, \
2494 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2495 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2496 }
2497 \f
2498 /* Addressing modes, and classification of registers for them. */
2499
2500 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2501 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2502 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2503
2504 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2505 and check its validity for a certain class.
2506 We have two alternate definitions for each of them.
2507 The usual definition accepts all pseudo regs; the other rejects them all.
2508 The symbol REG_OK_STRICT causes the latter definition to be used.
2509
2510 Most source files want to accept pseudo regs in the hope that
2511 they will get allocated to the class that the insn wants them to be in.
2512 Some source files that are used after register allocation
2513 need to be strict. */
2514
2515 #ifndef REG_OK_STRICT
2516 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2517 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2518 #else
2519 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2520 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2521 #endif
2522
2523 #define REG_OK_FOR_INDEX_P(X) 0
2524
2525 \f
2526 /* Maximum number of registers that can appear in a valid memory address. */
2527
2528 #define MAX_REGS_PER_ADDRESS 1
2529
2530 /* A C compound statement with a conditional `goto LABEL;' executed
2531 if X (an RTX) is a legitimate memory address on the target
2532 machine for a memory operand of mode MODE. */
2533
2534 #if 1
2535 #define GO_PRINTF(x) fprintf(stderr, (x))
2536 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2537 #define GO_DEBUG_RTX(x) debug_rtx(x)
2538
2539 #else
2540 #define GO_PRINTF(x)
2541 #define GO_PRINTF2(x,y)
2542 #define GO_DEBUG_RTX(x)
2543 #endif
2544
2545 #ifdef REG_OK_STRICT
2546 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2547 { \
2548 if (mips_legitimate_address_p (MODE, X, 1)) \
2549 goto ADDR; \
2550 }
2551 #else
2552 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2553 { \
2554 if (mips_legitimate_address_p (MODE, X, 0)) \
2555 goto ADDR; \
2556 }
2557 #endif
2558
2559 /* Check for constness inline but use mips_legitimate_address_p
2560 to check whether a constant really is an address. */
2561
2562 #define CONSTANT_ADDRESS_P(X) \
2563 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2564
2565 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2566
2567 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2568 do { \
2569 if (mips_legitimize_address (&(X), MODE)) \
2570 goto WIN; \
2571 } while (0)
2572
2573
2574 /* A C statement or compound statement with a conditional `goto
2575 LABEL;' executed if memory address X (an RTX) can have different
2576 meanings depending on the machine mode of the memory reference it
2577 is used for.
2578
2579 Autoincrement and autodecrement addresses typically have
2580 mode-dependent effects because the amount of the increment or
2581 decrement is the size of the operand being addressed. Some
2582 machines have other mode-dependent addresses. Many RISC machines
2583 have no mode-dependent addresses.
2584
2585 You may assume that ADDR is a valid address for the machine. */
2586
2587 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2588
2589 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2590 'the start of the function that this code is output in'. */
2591
2592 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2593 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2594 asm_fprintf ((FILE), "%U%s", \
2595 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2596 else \
2597 asm_fprintf ((FILE), "%U%s", (NAME))
2598
2599 /* The mips16 wants the constant pool to be after the function,
2600 because the PC relative load instructions use unsigned offsets. */
2601
2602 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2603
2604 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2605 mips_string_length = 0;
2606 \f
2607 /* Specify the machine mode that this machine uses
2608 for the index in the tablejump instruction.
2609 ??? Using HImode in mips16 mode can cause overflow. */
2610 #define CASE_VECTOR_MODE \
2611 (TARGET_MIPS16 ? HImode : ptr_mode)
2612
2613 /* Define as C expression which evaluates to nonzero if the tablejump
2614 instruction expects the table to contain offsets from the address of the
2615 table.
2616 Do not define this if the table should contain absolute addresses. */
2617 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2618
2619 /* Define this as 1 if `char' should by default be signed; else as 0. */
2620 #ifndef DEFAULT_SIGNED_CHAR
2621 #define DEFAULT_SIGNED_CHAR 1
2622 #endif
2623
2624 /* Max number of bytes we can move from memory to memory
2625 in one reasonably fast instruction. */
2626 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2627 #define MAX_MOVE_MAX 8
2628
2629 /* Define this macro as a C expression which is nonzero if
2630 accessing less than a word of memory (i.e. a `char' or a
2631 `short') is no faster than accessing a word of memory, i.e., if
2632 such access require more than one instruction or if there is no
2633 difference in cost between byte and (aligned) word loads.
2634
2635 On RISC machines, it tends to generate better code to define
2636 this as 1, since it avoids making a QI or HI mode register. */
2637 #define SLOW_BYTE_ACCESS 1
2638
2639 /* Define this to be nonzero if shift instructions ignore all but the low-order
2640 few bits. */
2641 #define SHIFT_COUNT_TRUNCATED 1
2642
2643 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2644 is done just by pretending it is already truncated. */
2645 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2646 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2647
2648
2649 /* Specify the machine mode that pointers have.
2650 After generation of rtl, the compiler makes no further distinction
2651 between pointers and any other objects of this machine mode. */
2652
2653 #ifndef Pmode
2654 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2655 #endif
2656
2657 /* Give call MEMs SImode since it is the "most permissive" mode
2658 for both 32-bit and 64-bit targets. */
2659
2660 #define FUNCTION_MODE SImode
2661
2662 \f
2663 /* The cost of loading values from the constant pool. It should be
2664 larger than the cost of any constant we want to synthesize in-line. */
2665
2666 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2667
2668 /* A C expression for the cost of moving data from a register in
2669 class FROM to one in class TO. The classes are expressed using
2670 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2671 the default; other values are interpreted relative to that.
2672
2673 It is not required that the cost always equal 2 when FROM is the
2674 same as TO; on some machines it is expensive to move between
2675 registers if they are not general registers.
2676
2677 If reload sees an insn consisting of a single `set' between two
2678 hard registers, and if `REGISTER_MOVE_COST' applied to their
2679 classes returns a value of 2, reload does not check to ensure
2680 that the constraints of the insn are met. Setting a cost of
2681 other than 2 will allow reload to verify that the constraints are
2682 met. You should do this if the `movM' pattern's constraints do
2683 not allow such copying. */
2684
2685 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2686 mips_register_move_cost (MODE, FROM, TO)
2687
2688 /* ??? Fix this to be right for the R8000. */
2689 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2690 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2691 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2692
2693 /* Define if copies to/from condition code registers should be avoided.
2694
2695 This is needed for the MIPS because reload_outcc is not complete;
2696 it needs to handle cases where the source is a general or another
2697 condition code register. */
2698 #define AVOID_CCMODE_COPIES
2699
2700 /* A C expression for the cost of a branch instruction. A value of
2701 1 is the default; other values are interpreted relative to that. */
2702
2703 /* ??? Fix this to be right for the R8000. */
2704 #define BRANCH_COST \
2705 ((! TARGET_MIPS16 \
2706 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2707 ? 2 : 1)
2708
2709 /* If defined, modifies the length assigned to instruction INSN as a
2710 function of the context in which it is used. LENGTH is an lvalue
2711 that contains the initially computed length of the insn and should
2712 be updated with the correct length of the insn. */
2713 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2714 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2715
2716 \f
2717 /* Optionally define this if you have added predicates to
2718 `MACHINE.c'. This macro is called within an initializer of an
2719 array of structures. The first field in the structure is the
2720 name of a predicate and the second field is an array of rtl
2721 codes. For each predicate, list all rtl codes that can be in
2722 expressions matched by the predicate. The list should have a
2723 trailing comma. Here is an example of two entries in the list
2724 for a typical RISC machine:
2725
2726 #define PREDICATE_CODES \
2727 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2728 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2729
2730 Defining this macro does not affect the generated code (however,
2731 incorrect definitions that omit an rtl code that may be matched
2732 by the predicate can cause the compiler to malfunction).
2733 Instead, it allows the table built by `genrecog' to be more
2734 compact and efficient, thus speeding up the compiler. The most
2735 important predicates to include in the list specified by this
2736 macro are thoses used in the most insn patterns. */
2737
2738 #define PREDICATE_CODES \
2739 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2740 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2741 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2742 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2743 {"const_arith_operand", { CONST_INT }}, \
2744 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2745 UNSPEC_VOLATILE }}, \
2746 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2747 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2748 {"small_int", { CONST_INT }}, \
2749 {"const_float_1_operand", { CONST_DOUBLE }}, \
2750 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2751 {"equality_op", { EQ, NE }}, \
2752 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2753 LTU, LEU }}, \
2754 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2755 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2756 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2757 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2758 SYMBOL_REF, LABEL_REF, SUBREG, \
2759 REG, MEM}}, \
2760 {"stack_operand", { MEM }}, \
2761 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2762 CONST_DOUBLE, CONST }}, \
2763 {"fcc_register_operand", { REG, SUBREG }}, \
2764 {"hilo_operand", { REG }}, \
2765 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2766
2767 /* A list of predicates that do special things with modes, and so
2768 should not elicit warnings for VOIDmode match_operand. */
2769
2770 #define SPECIAL_MODE_PREDICATES \
2771 "pc_or_label_operand",
2772 \f
2773 /* Control the assembler format that we output. */
2774
2775 /* Output to assembler file text saying following lines
2776 may contain character constants, extra white space, comments, etc. */
2777
2778 #ifndef ASM_APP_ON
2779 #define ASM_APP_ON " #APP\n"
2780 #endif
2781
2782 /* Output to assembler file text saying following lines
2783 no longer contain unusual constructs. */
2784
2785 #ifndef ASM_APP_OFF
2786 #define ASM_APP_OFF " #NO_APP\n"
2787 #endif
2788
2789 /* How to refer to registers in assembler output.
2790 This sequence is indexed by compiler's hard-register-number (see above).
2791
2792 In order to support the two different conventions for register names,
2793 we use the name of a table set up in mips.c, which is overwritten
2794 if -mrnames is used. */
2795
2796 #define REGISTER_NAMES \
2797 { \
2798 &mips_reg_names[ 0][0], \
2799 &mips_reg_names[ 1][0], \
2800 &mips_reg_names[ 2][0], \
2801 &mips_reg_names[ 3][0], \
2802 &mips_reg_names[ 4][0], \
2803 &mips_reg_names[ 5][0], \
2804 &mips_reg_names[ 6][0], \
2805 &mips_reg_names[ 7][0], \
2806 &mips_reg_names[ 8][0], \
2807 &mips_reg_names[ 9][0], \
2808 &mips_reg_names[10][0], \
2809 &mips_reg_names[11][0], \
2810 &mips_reg_names[12][0], \
2811 &mips_reg_names[13][0], \
2812 &mips_reg_names[14][0], \
2813 &mips_reg_names[15][0], \
2814 &mips_reg_names[16][0], \
2815 &mips_reg_names[17][0], \
2816 &mips_reg_names[18][0], \
2817 &mips_reg_names[19][0], \
2818 &mips_reg_names[20][0], \
2819 &mips_reg_names[21][0], \
2820 &mips_reg_names[22][0], \
2821 &mips_reg_names[23][0], \
2822 &mips_reg_names[24][0], \
2823 &mips_reg_names[25][0], \
2824 &mips_reg_names[26][0], \
2825 &mips_reg_names[27][0], \
2826 &mips_reg_names[28][0], \
2827 &mips_reg_names[29][0], \
2828 &mips_reg_names[30][0], \
2829 &mips_reg_names[31][0], \
2830 &mips_reg_names[32][0], \
2831 &mips_reg_names[33][0], \
2832 &mips_reg_names[34][0], \
2833 &mips_reg_names[35][0], \
2834 &mips_reg_names[36][0], \
2835 &mips_reg_names[37][0], \
2836 &mips_reg_names[38][0], \
2837 &mips_reg_names[39][0], \
2838 &mips_reg_names[40][0], \
2839 &mips_reg_names[41][0], \
2840 &mips_reg_names[42][0], \
2841 &mips_reg_names[43][0], \
2842 &mips_reg_names[44][0], \
2843 &mips_reg_names[45][0], \
2844 &mips_reg_names[46][0], \
2845 &mips_reg_names[47][0], \
2846 &mips_reg_names[48][0], \
2847 &mips_reg_names[49][0], \
2848 &mips_reg_names[50][0], \
2849 &mips_reg_names[51][0], \
2850 &mips_reg_names[52][0], \
2851 &mips_reg_names[53][0], \
2852 &mips_reg_names[54][0], \
2853 &mips_reg_names[55][0], \
2854 &mips_reg_names[56][0], \
2855 &mips_reg_names[57][0], \
2856 &mips_reg_names[58][0], \
2857 &mips_reg_names[59][0], \
2858 &mips_reg_names[60][0], \
2859 &mips_reg_names[61][0], \
2860 &mips_reg_names[62][0], \
2861 &mips_reg_names[63][0], \
2862 &mips_reg_names[64][0], \
2863 &mips_reg_names[65][0], \
2864 &mips_reg_names[66][0], \
2865 &mips_reg_names[67][0], \
2866 &mips_reg_names[68][0], \
2867 &mips_reg_names[69][0], \
2868 &mips_reg_names[70][0], \
2869 &mips_reg_names[71][0], \
2870 &mips_reg_names[72][0], \
2871 &mips_reg_names[73][0], \
2872 &mips_reg_names[74][0], \
2873 &mips_reg_names[75][0], \
2874 &mips_reg_names[76][0], \
2875 &mips_reg_names[77][0], \
2876 &mips_reg_names[78][0], \
2877 &mips_reg_names[79][0], \
2878 &mips_reg_names[80][0], \
2879 &mips_reg_names[81][0], \
2880 &mips_reg_names[82][0], \
2881 &mips_reg_names[83][0], \
2882 &mips_reg_names[84][0], \
2883 &mips_reg_names[85][0], \
2884 &mips_reg_names[86][0], \
2885 &mips_reg_names[87][0], \
2886 &mips_reg_names[88][0], \
2887 &mips_reg_names[89][0], \
2888 &mips_reg_names[90][0], \
2889 &mips_reg_names[91][0], \
2890 &mips_reg_names[92][0], \
2891 &mips_reg_names[93][0], \
2892 &mips_reg_names[94][0], \
2893 &mips_reg_names[95][0], \
2894 &mips_reg_names[96][0], \
2895 &mips_reg_names[97][0], \
2896 &mips_reg_names[98][0], \
2897 &mips_reg_names[99][0], \
2898 &mips_reg_names[100][0], \
2899 &mips_reg_names[101][0], \
2900 &mips_reg_names[102][0], \
2901 &mips_reg_names[103][0], \
2902 &mips_reg_names[104][0], \
2903 &mips_reg_names[105][0], \
2904 &mips_reg_names[106][0], \
2905 &mips_reg_names[107][0], \
2906 &mips_reg_names[108][0], \
2907 &mips_reg_names[109][0], \
2908 &mips_reg_names[110][0], \
2909 &mips_reg_names[111][0], \
2910 &mips_reg_names[112][0], \
2911 &mips_reg_names[113][0], \
2912 &mips_reg_names[114][0], \
2913 &mips_reg_names[115][0], \
2914 &mips_reg_names[116][0], \
2915 &mips_reg_names[117][0], \
2916 &mips_reg_names[118][0], \
2917 &mips_reg_names[119][0], \
2918 &mips_reg_names[120][0], \
2919 &mips_reg_names[121][0], \
2920 &mips_reg_names[122][0], \
2921 &mips_reg_names[123][0], \
2922 &mips_reg_names[124][0], \
2923 &mips_reg_names[125][0], \
2924 &mips_reg_names[126][0], \
2925 &mips_reg_names[127][0], \
2926 &mips_reg_names[128][0], \
2927 &mips_reg_names[129][0], \
2928 &mips_reg_names[130][0], \
2929 &mips_reg_names[131][0], \
2930 &mips_reg_names[132][0], \
2931 &mips_reg_names[133][0], \
2932 &mips_reg_names[134][0], \
2933 &mips_reg_names[135][0], \
2934 &mips_reg_names[136][0], \
2935 &mips_reg_names[137][0], \
2936 &mips_reg_names[138][0], \
2937 &mips_reg_names[139][0], \
2938 &mips_reg_names[140][0], \
2939 &mips_reg_names[141][0], \
2940 &mips_reg_names[142][0], \
2941 &mips_reg_names[143][0], \
2942 &mips_reg_names[144][0], \
2943 &mips_reg_names[145][0], \
2944 &mips_reg_names[146][0], \
2945 &mips_reg_names[147][0], \
2946 &mips_reg_names[148][0], \
2947 &mips_reg_names[149][0], \
2948 &mips_reg_names[150][0], \
2949 &mips_reg_names[151][0], \
2950 &mips_reg_names[152][0], \
2951 &mips_reg_names[153][0], \
2952 &mips_reg_names[154][0], \
2953 &mips_reg_names[155][0], \
2954 &mips_reg_names[156][0], \
2955 &mips_reg_names[157][0], \
2956 &mips_reg_names[158][0], \
2957 &mips_reg_names[159][0], \
2958 &mips_reg_names[160][0], \
2959 &mips_reg_names[161][0], \
2960 &mips_reg_names[162][0], \
2961 &mips_reg_names[163][0], \
2962 &mips_reg_names[164][0], \
2963 &mips_reg_names[165][0], \
2964 &mips_reg_names[166][0], \
2965 &mips_reg_names[167][0], \
2966 &mips_reg_names[168][0], \
2967 &mips_reg_names[169][0], \
2968 &mips_reg_names[170][0], \
2969 &mips_reg_names[171][0], \
2970 &mips_reg_names[172][0], \
2971 &mips_reg_names[173][0], \
2972 &mips_reg_names[174][0], \
2973 &mips_reg_names[175][0] \
2974 }
2975
2976 /* If defined, a C initializer for an array of structures
2977 containing a name and a register number. This macro defines
2978 additional names for hard registers, thus allowing the `asm'
2979 option in declarations to refer to registers using alternate
2980 names.
2981
2982 We define both names for the integer registers here. */
2983
2984 #define ADDITIONAL_REGISTER_NAMES \
2985 { \
2986 { "$0", 0 + GP_REG_FIRST }, \
2987 { "$1", 1 + GP_REG_FIRST }, \
2988 { "$2", 2 + GP_REG_FIRST }, \
2989 { "$3", 3 + GP_REG_FIRST }, \
2990 { "$4", 4 + GP_REG_FIRST }, \
2991 { "$5", 5 + GP_REG_FIRST }, \
2992 { "$6", 6 + GP_REG_FIRST }, \
2993 { "$7", 7 + GP_REG_FIRST }, \
2994 { "$8", 8 + GP_REG_FIRST }, \
2995 { "$9", 9 + GP_REG_FIRST }, \
2996 { "$10", 10 + GP_REG_FIRST }, \
2997 { "$11", 11 + GP_REG_FIRST }, \
2998 { "$12", 12 + GP_REG_FIRST }, \
2999 { "$13", 13 + GP_REG_FIRST }, \
3000 { "$14", 14 + GP_REG_FIRST }, \
3001 { "$15", 15 + GP_REG_FIRST }, \
3002 { "$16", 16 + GP_REG_FIRST }, \
3003 { "$17", 17 + GP_REG_FIRST }, \
3004 { "$18", 18 + GP_REG_FIRST }, \
3005 { "$19", 19 + GP_REG_FIRST }, \
3006 { "$20", 20 + GP_REG_FIRST }, \
3007 { "$21", 21 + GP_REG_FIRST }, \
3008 { "$22", 22 + GP_REG_FIRST }, \
3009 { "$23", 23 + GP_REG_FIRST }, \
3010 { "$24", 24 + GP_REG_FIRST }, \
3011 { "$25", 25 + GP_REG_FIRST }, \
3012 { "$26", 26 + GP_REG_FIRST }, \
3013 { "$27", 27 + GP_REG_FIRST }, \
3014 { "$28", 28 + GP_REG_FIRST }, \
3015 { "$29", 29 + GP_REG_FIRST }, \
3016 { "$30", 30 + GP_REG_FIRST }, \
3017 { "$31", 31 + GP_REG_FIRST }, \
3018 { "$sp", 29 + GP_REG_FIRST }, \
3019 { "$fp", 30 + GP_REG_FIRST }, \
3020 { "at", 1 + GP_REG_FIRST }, \
3021 { "v0", 2 + GP_REG_FIRST }, \
3022 { "v1", 3 + GP_REG_FIRST }, \
3023 { "a0", 4 + GP_REG_FIRST }, \
3024 { "a1", 5 + GP_REG_FIRST }, \
3025 { "a2", 6 + GP_REG_FIRST }, \
3026 { "a3", 7 + GP_REG_FIRST }, \
3027 { "t0", 8 + GP_REG_FIRST }, \
3028 { "t1", 9 + GP_REG_FIRST }, \
3029 { "t2", 10 + GP_REG_FIRST }, \
3030 { "t3", 11 + GP_REG_FIRST }, \
3031 { "t4", 12 + GP_REG_FIRST }, \
3032 { "t5", 13 + GP_REG_FIRST }, \
3033 { "t6", 14 + GP_REG_FIRST }, \
3034 { "t7", 15 + GP_REG_FIRST }, \
3035 { "s0", 16 + GP_REG_FIRST }, \
3036 { "s1", 17 + GP_REG_FIRST }, \
3037 { "s2", 18 + GP_REG_FIRST }, \
3038 { "s3", 19 + GP_REG_FIRST }, \
3039 { "s4", 20 + GP_REG_FIRST }, \
3040 { "s5", 21 + GP_REG_FIRST }, \
3041 { "s6", 22 + GP_REG_FIRST }, \
3042 { "s7", 23 + GP_REG_FIRST }, \
3043 { "t8", 24 + GP_REG_FIRST }, \
3044 { "t9", 25 + GP_REG_FIRST }, \
3045 { "k0", 26 + GP_REG_FIRST }, \
3046 { "k1", 27 + GP_REG_FIRST }, \
3047 { "gp", 28 + GP_REG_FIRST }, \
3048 { "sp", 29 + GP_REG_FIRST }, \
3049 { "fp", 30 + GP_REG_FIRST }, \
3050 { "ra", 31 + GP_REG_FIRST }, \
3051 { "$sp", 29 + GP_REG_FIRST }, \
3052 { "$fp", 30 + GP_REG_FIRST } \
3053 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3054 }
3055
3056 /* This is meant to be redefined in the host dependent files. It is a
3057 set of alternative names and regnums for mips coprocessors. */
3058
3059 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3060
3061 /* A C compound statement to output to stdio stream STREAM the
3062 assembler syntax for an instruction operand X. X is an RTL
3063 expression.
3064
3065 CODE is a value that can be used to specify one of several ways
3066 of printing the operand. It is used when identical operands
3067 must be printed differently depending on the context. CODE
3068 comes from the `%' specification that was used to request
3069 printing of the operand. If the specification was just `%DIGIT'
3070 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3071 is the ASCII code for LTR.
3072
3073 If X is a register, this macro should print the register's name.
3074 The names can be found in an array `reg_names' whose type is
3075 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3076
3077 When the machine description has a specification `%PUNCT' (a `%'
3078 followed by a punctuation character), this macro is called with
3079 a null pointer for X and the punctuation character for CODE.
3080
3081 See mips.c for the MIPS specific codes. */
3082
3083 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3084
3085 /* A C expression which evaluates to true if CODE is a valid
3086 punctuation character for use in the `PRINT_OPERAND' macro. If
3087 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3088 punctuation characters (except for the standard one, `%') are
3089 used in this way. */
3090
3091 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3092
3093 /* A C compound statement to output to stdio stream STREAM the
3094 assembler syntax for an instruction operand that is a memory
3095 reference whose address is ADDR. ADDR is an RTL expression. */
3096
3097 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3098
3099
3100 /* A C statement, to be executed after all slot-filler instructions
3101 have been output. If necessary, call `dbr_sequence_length' to
3102 determine the number of slots filled in a sequence (zero if not
3103 currently outputting a sequence), to decide how many no-ops to
3104 output, or whatever.
3105
3106 Don't define this macro if it has nothing to do, but it is
3107 helpful in reading assembly output if the extent of the delay
3108 sequence is made explicit (e.g. with white space).
3109
3110 Note that output routines for instructions with delay slots must
3111 be prepared to deal with not being output as part of a sequence
3112 (i.e. when the scheduling pass is not run, or when no slot
3113 fillers could be found.) The variable `final_sequence' is null
3114 when not processing a sequence, otherwise it contains the
3115 `sequence' rtx being output. */
3116
3117 #define DBR_OUTPUT_SEQEND(STREAM) \
3118 do \
3119 { \
3120 if (set_nomacro > 0 && --set_nomacro == 0) \
3121 fputs ("\t.set\tmacro\n", STREAM); \
3122 \
3123 if (set_noreorder > 0 && --set_noreorder == 0) \
3124 fputs ("\t.set\treorder\n", STREAM); \
3125 \
3126 fputs ("\n", STREAM); \
3127 } \
3128 while (0)
3129
3130
3131 /* How to tell the debugger about changes of source files. */
3132
3133 #ifndef SET_FILE_NUMBER
3134 #define SET_FILE_NUMBER() ++num_source_filenames
3135 #endif
3136
3137 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3138 mips_output_filename (STREAM, NAME)
3139
3140 /* This is defined so that it can be overridden in iris6.h. */
3141 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3142 do \
3143 { \
3144 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3145 output_quoted_string (STREAM, NAME); \
3146 fputs ("\n", STREAM); \
3147 } \
3148 while (0)
3149
3150 /* This is how to output a note the debugger telling it the line number
3151 to which the following sequence of instructions corresponds.
3152 Silicon graphics puts a label after each .loc. */
3153
3154 #ifndef LABEL_AFTER_LOC
3155 #define LABEL_AFTER_LOC(STREAM)
3156 #endif
3157
3158 #ifndef ASM_OUTPUT_SOURCE_LINE
3159 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3160 mips_output_lineno (STREAM, LINE)
3161 #endif
3162
3163 /* The MIPS implementation uses some labels for its own purpose. The
3164 following lists what labels are created, and are all formed by the
3165 pattern $L[a-z].*. The machine independent portion of GCC creates
3166 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3167
3168 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3169 $Lb[0-9]+ Begin blocks for MIPS debug support
3170 $Lc[0-9]+ Label for use in s<xx> operation.
3171 $Le[0-9]+ End blocks for MIPS debug support */
3172
3173 #undef ASM_DECLARE_OBJECT_NAME
3174 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3175 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3176
3177 /* Globalizing directive for a label. */
3178 #define GLOBAL_ASM_OP "\t.globl\t"
3179
3180 /* This says how to define a global common symbol. */
3181
3182 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3183 do { \
3184 /* If the target wants uninitialized const declarations in \
3185 .rdata then don't put them in .comm */ \
3186 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3187 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3188 && (DECL_INITIAL (DECL) == 0 \
3189 || DECL_INITIAL (DECL) == error_mark_node)) \
3190 { \
3191 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3192 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3193 \
3194 readonly_data_section (); \
3195 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3196 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3197 (SIZE)); \
3198 } \
3199 else \
3200 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3201 (SIZE)); \
3202 } while (0)
3203
3204
3205 /* This says how to define a local common symbol (ie, not visible to
3206 linker). */
3207
3208 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3209 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3210
3211
3212 /* This says how to output an external. It would be possible not to
3213 output anything and let undefined symbol become external. However
3214 the assembler uses length information on externals to allocate in
3215 data/sdata bss/sbss, thereby saving exec time. */
3216
3217 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3218 mips_output_external(STREAM,DECL,NAME)
3219
3220 /* This is how to declare a function name. The actual work of
3221 emitting the label is moved to function_prologue, so that we can
3222 get the line number correctly emitted before the .ent directive,
3223 and after any .file directives. Define as empty so that the function
3224 is not declared before the .ent directive elsewhere. */
3225
3226 #undef ASM_DECLARE_FUNCTION_NAME
3227 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3228
3229 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3230 #define FUNCTION_NAME_ALREADY_DECLARED 0
3231 #endif
3232
3233 /* This is how to store into the string LABEL
3234 the symbol_ref name of an internal numbered label where
3235 PREFIX is the class of label and NUM is the number within the class.
3236 This is suitable for output with `assemble_name'. */
3237
3238 #undef ASM_GENERATE_INTERNAL_LABEL
3239 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3240 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3241
3242 /* This is how to output an element of a case-vector that is absolute. */
3243
3244 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3245 fprintf (STREAM, "\t%s\t%sL%d\n", \
3246 ptr_mode == DImode ? ".dword" : ".word", \
3247 LOCAL_LABEL_PREFIX, \
3248 VALUE)
3249
3250 /* This is how to output an element of a case-vector that is relative.
3251 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3252 TARGET_EMBEDDED_PIC). */
3253
3254 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3255 do { \
3256 if (TARGET_MIPS16) \
3257 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3258 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3259 else if (TARGET_EMBEDDED_PIC) \
3260 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3261 ptr_mode == DImode ? ".dword" : ".word", \
3262 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3263 else if (TARGET_GPWORD) \
3264 fprintf (STREAM, "\t%s\t%sL%d\n", \
3265 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3266 LOCAL_LABEL_PREFIX, VALUE); \
3267 else \
3268 fprintf (STREAM, "\t%s\t%sL%d\n", \
3269 ptr_mode == DImode ? ".dword" : ".word", \
3270 LOCAL_LABEL_PREFIX, VALUE); \
3271 } while (0)
3272
3273 /* When generating embedded PIC or mips16 code we want to put the jump
3274 table in the .text section. In all other cases, we want to put the
3275 jump table in the .rdata section. Unfortunately, we can't use
3276 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3277 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3278 section if appropriate. */
3279 #undef ASM_OUTPUT_CASE_LABEL
3280 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3281 do { \
3282 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3283 function_section (current_function_decl); \
3284 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3285 } while (0)
3286
3287 /* This is how to output an assembler line
3288 that says to advance the location counter
3289 to a multiple of 2**LOG bytes. */
3290
3291 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3292 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3293
3294 /* This is how to output an assembler line to advance the location
3295 counter by SIZE bytes. */
3296
3297 #undef ASM_OUTPUT_SKIP
3298 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3299 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3300
3301 /* This is how to output a string. */
3302 #undef ASM_OUTPUT_ASCII
3303 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3304 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3305
3306 /* Output #ident as a in the read-only data section. */
3307 #undef ASM_OUTPUT_IDENT
3308 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3309 { \
3310 const char *p = STRING; \
3311 int size = strlen (p) + 1; \
3312 readonly_data_section (); \
3313 assemble_string (p, size); \
3314 }
3315 \f
3316 /* Default to -G 8 */
3317 #ifndef MIPS_DEFAULT_GVALUE
3318 #define MIPS_DEFAULT_GVALUE 8
3319 #endif
3320
3321 /* Define the strings to put out for each section in the object file. */
3322 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3323 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3324 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3325
3326 #undef READONLY_DATA_SECTION_ASM_OP
3327 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3328
3329 /* Given a decl node or constant node, choose the section to output it in
3330 and select that section. */
3331
3332 #undef TARGET_ASM_SELECT_SECTION
3333 #define TARGET_ASM_SELECT_SECTION mips_select_section
3334 \f
3335 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3336 do \
3337 { \
3338 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3339 TARGET_64BIT ? "dsubu" : "subu", \
3340 reg_names[STACK_POINTER_REGNUM], \
3341 reg_names[STACK_POINTER_REGNUM], \
3342 TARGET_64BIT ? "sd" : "sw", \
3343 reg_names[REGNO], \
3344 reg_names[STACK_POINTER_REGNUM]); \
3345 } \
3346 while (0)
3347
3348 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3349 do \
3350 { \
3351 if (! set_noreorder) \
3352 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3353 \
3354 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3355 TARGET_64BIT ? "ld" : "lw", \
3356 reg_names[REGNO], \
3357 reg_names[STACK_POINTER_REGNUM], \
3358 TARGET_64BIT ? "daddu" : "addu", \
3359 reg_names[STACK_POINTER_REGNUM], \
3360 reg_names[STACK_POINTER_REGNUM]); \
3361 \
3362 if (! set_noreorder) \
3363 fprintf (STREAM, "\t.set\treorder\n"); \
3364 } \
3365 while (0)
3366
3367 /* How to start an assembler comment.
3368 The leading space is important (the mips native assembler requires it). */
3369 #ifndef ASM_COMMENT_START
3370 #define ASM_COMMENT_START " #"
3371 #endif
3372 \f
3373 /* Default definitions for size_t and ptrdiff_t. We must override the
3374 definitions from ../svr4.h on mips-*-linux-gnu. */
3375
3376 #undef SIZE_TYPE
3377 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3378
3379 #undef PTRDIFF_TYPE
3380 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3381
3382 /* See mips_expand_prologue's use of loadgp for when this should be
3383 true. */
3384
3385 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3386 && mips_abi != ABI_32 \
3387 && mips_abi != ABI_O64)
3388 \f
3389
3390 #define DFMODE_NAN \
3391 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
3392 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
3393 #define SFMODE_NAN \
3394 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
3395 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
3396
3397 /* Generate calls to memcpy, etc., not bcopy, etc. */
3398 #define TARGET_MEM_FUNCTIONS
3399
3400 #ifndef __mips16
3401 /* Since the bits of the _init and _fini function is spread across
3402 many object files, each potentially with its own GP, we must assume
3403 we need to load our GP. We don't preserve $gp or $ra, since each
3404 init/fini chunk is supposed to initialize $gp, and crti/crtn
3405 already take care of preserving $ra and, when appropriate, $gp. */
3406 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3407 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3408 asm (SECTION_OP "\n\
3409 .set noreorder\n\
3410 bal 1f\n\
3411 nop\n\
3412 1: .cpload $31\n\
3413 .set reorder\n\
3414 jal " USER_LABEL_PREFIX #FUNC "\n\
3415 " TEXT_SECTION_ASM_OP);
3416 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3417 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3418 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3419 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3420 asm (SECTION_OP "\n\
3421 .set noreorder\n\
3422 bal 1f\n\
3423 nop\n\
3424 1: .set reorder\n\
3425 .cpsetup $31, $2, 1b\n\
3426 jal " USER_LABEL_PREFIX #FUNC "\n\
3427 " TEXT_SECTION_ASM_OP);
3428 #endif
3429 #endif
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