| blob | 00bdad63e98d00aa80023d2cd8a54665c70ca55a |
1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Things to do:
23 - longlong.h?
24 */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
29 #undef SIZE_TYPE
30 #undef PTRDIFF_TYPE
31 #undef WCHAR_TYPE
32 #undef WCHAR_TYPE_SIZE
33 #undef TARGET_VERSION
34 #undef CPP_SPEC
35 #undef ASM_SPEC
36 #undef LINK_SPEC
37 #undef STARTFILE_SPEC
38 #undef ENDFILE_SPEC
39 #undef SUBTARGET_SWITCHES
41 #undef ASM_APP_ON
42 #undef ASM_APP_OFF
43 \f
45 /* M32R/X overrides. */
46 /* Print subsidiary information on the compiler version in use. */
49 /* Additional flags for the preprocessor. */
51 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
52 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
53 "
55 /* Assembler switches. */
56 #define ASM_CPU_SPEC \
57 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
59 /* Use m32rx specific crt0/crtinit/crtfini files. */
60 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
63 /* Extra machine dependent switches. */
64 #define SUBTARGET_SWITCHES \
69 /* Define this macro as a C expression for the initializer of an array of
70 strings to tell the driver program which options are defaults for this
71 target and thus do not need to be handled specially when using
72 `MULTILIB_OPTIONS'. */
75 /* Number of additional registers the subtarget defines. */
76 #define SUBTARGET_NUM_REGISTERS 1
78 /* 1 for registers that cannot be allocated. */
79 #define SUBTARGET_FIXED_REGISTERS , 1
81 /* 1 for registers that are not available across function calls. */
82 #define SUBTARGET_CALL_USED_REGISTERS , 1
84 /* Order to allocate model specific registers. */
85 #define SUBTARGET_REG_ALLOC_ORDER , 19
87 /* Registers which are accumulators. */
88 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
90 /* All registers added. */
91 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
93 /* Additional accumulator registers. */
94 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
96 /* Define additional register names. */
98 /* end M32R/X overrides. */
100 /* Print subsidiary information on the compiler version in use. */
101 #ifndef TARGET_VERSION
103 #endif
105 /* Switch Recognition by gcc.c. Add -G xx support. */
107 #undef SWITCH_TAKES_ARG
108 #define SWITCH_TAKES_ARG(CHAR) \
111 /* Names to predefine in the preprocessor for this target machine. */
112 /* __M32R__ is defined by the existing compiler so we use that. */
113 #define TARGET_CPU_CPP_BUILTINS() \
114 do \
115 { \
120 builtin_define (TARGET_BIG_ENDIAN \
122 if (flag_pic) \
123 { \
126 } \
127 } \
128 while (0)
130 /* This macro defines names of additional specifications to put in the specs
131 that can be used in various specifications like CC1_SPEC. Its definition
132 is an initializer with a subgrouping for each command option.
134 Each subgrouping contains a string constant, that defines the
135 specification name, and a string constant that used by the GCC driver
136 program.
138 Do not define this macro if it does not need to do anything. */
140 #ifndef SUBTARGET_EXTRA_SPECS
141 #define SUBTARGET_EXTRA_SPECS
142 #endif
144 #ifndef ASM_CPU_SPEC
146 #endif
148 #ifndef CPP_CPU_SPEC
150 #endif
152 #ifndef CC1_CPU_SPEC
154 #endif
156 #ifndef LINK_CPU_SPEC
158 #endif
160 #ifndef STARTFILE_CPU_SPEC
162 #endif
164 #ifndef ENDFILE_CPU_SPEC
166 #endif
168 #ifndef RELAX_SPEC
171 #else
173 #endif
174 #endif
176 #define EXTRA_SPECS \
184 SUBTARGET_EXTRA_SPECS
188 #undef CC1_SPEC
191 /* Options to pass on to the assembler. */
192 #undef ASM_SPEC
197 #undef STARTFILE_SPEC
200 #undef ENDFILE_SPEC
203 #undef LIB_SPEC
204 \f
205 /* Run-time compilation parameters selecting different hardware subsets. */
209 /* If nonzero, tell the linker to do relaxing.
210 We don't do anything with the option, other than recognize it.
211 LINK_SPEC handles passing -relax to the linker.
212 This can cause incorrect debugging information as line numbers may
213 turn out wrong. This shouldn't be specified unless accompanied with -O2
214 [where the user expects debugging information to be less accurate]. */
215 #define TARGET_RELAX_MASK (1 << 0)
217 /* For miscellaneous debugging purposes. */
218 #define TARGET_DEBUG_MASK (1 << 1)
219 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
221 /* Align loops to 32 byte boundaries (cache line size). */
222 /* ??? This option is experimental and is not documented. */
223 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
224 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
226 /* Change issue rate. */
227 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
228 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
230 /* Change branch cost */
231 #define TARGET_BRANCH_COST_MASK (1 << 4)
232 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
234 /* Target machine to compile for. */
235 #define TARGET_M32R 1
237 /* Support extended instruction set. */
238 #define TARGET_M32RX_MASK (1 << 5)
239 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
240 #undef TARGET_M32R
241 #define TARGET_M32R (! TARGET_M32RX)
243 /* Support extended instruction set of m32r2. */
244 #define TARGET_M32R2_MASK (1 << 6)
245 #define TARGET_M32R2 (target_flags & TARGET_M32R2_MASK)
246 #undef TARGET_M32R
247 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
249 /* Big Endian Flag. */
250 #define BIG_ENDIAN_BIT (1 << 7)
251 #define TARGET_BIG_ENDIAN (target_flags & BIG_ENDIAN_BIT)
253 /* Little Endian Flag. */
254 #define LITTLE_ENDIAN_BIT (1 << 8)
256 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
257 #endif
259 /* Macro to define tables used to set the flags.
260 This is a list in braces of pairs in braces,
261 each pair being { "NAME", VALUE }
262 where VALUE is the bits to set or minus the bits to clear.
263 An empty string NAME is used to identify the default VALUE. */
265 #ifndef SUBTARGET_SWITCHES
266 #define SUBTARGET_SWITCHES
267 #endif
269 #ifndef TARGET_DEFAULT
270 #define TARGET_DEFAULT 0
271 #endif
273 #define TARGET_SWITCHES \
274 { \
275 /* { "relax", TARGET_RELAX_MASK, "" }, \
288 SUBTARGET_SWITCHES \
290 }
295 /* Cache-flush support. */
300 #ifndef SUBTARGET_OPTIONS
301 #define SUBTARGET_OPTIONS
302 #endif
304 #define TARGET_OPTIONS \
305 { \
318 SUBTARGET_OPTIONS \
319 }
321 /* Code Models
323 Code models are used to select between two choices of two separate
324 possibilities (address space size, call insn to use):
326 small: addresses use 24 bits, use bl to make calls
327 medium: addresses use 32 bits, use bl to make calls (*1)
328 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
330 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
331 using this one doesn't make much sense.
333 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
334 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
336 Internally these are recorded as TARGET_ADDR{24,32} and
337 TARGET_CALL{26,32}.
339 The __model__ attribute can be used to select the code model to use when
340 accessing particular objects. */
345 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
346 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
347 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
348 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
349 #define TARGET_ADDR32 (! TARGET_ADDR24)
350 #define TARGET_CALL26 (! TARGET_CALL32)
351 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
353 /* The default is the small model. */
354 #ifndef M32R_MODEL_DEFAULT
356 #endif
358 /* Small Data Area
360 The SDA consists of sections .sdata, .sbss, and .scommon.
361 .scommon isn't a real section, symbols in it have their section index
362 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
364 Two switches control the SDA:
366 -G NNN - specifies the maximum size of variable to go in the SDA
368 -msdata=foo - specifies how such variables are handled
370 -msdata=none - small data area is disabled
372 -msdata=sdata - small data goes in the SDA, special code isn't
373 generated to use it, and special relocs aren't
374 generated
376 -msdata=use - small data goes in the SDA, special code is generated
377 to use the SDA and special relocs are generated
379 The SDA is not multilib'd, it isn't necessary.
380 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
381 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
382 -msdata=use will successfully link with them (references in header files
383 will cause the compiler to emit code that refers to library objects in
384 .data). ??? There can be a problem if the user passes a -G value greater
385 than the default and a library object in a header file is that size.
386 The default is 8 so this should be rare - if it occurs the user
387 is required to rebuild the libraries or use a smaller value for -G. */
389 /* Maximum size of variables that go in .sdata/.sbss.
390 The -msdata=foo switch also controls how small variables are handled. */
391 #ifndef SDATA_DEFAULT_SIZE
392 #define SDATA_DEFAULT_SIZE 8
393 #endif
398 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
399 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
400 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
402 /* Default is to disable the SDA
403 [for upward compatibility with previous toolchains]. */
404 #ifndef M32R_SDATA_DEFAULT
406 #endif
408 /* Define this macro as a C expression for the initializer of an array of
409 strings to tell the driver program which options are defaults for this
410 target and thus do not need to be handled specially when using
411 `MULTILIB_OPTIONS'. */
412 #ifndef SUBTARGET_MULTILIB_DEFAULTS
413 #define SUBTARGET_MULTILIB_DEFAULTS
414 #endif
416 #ifndef MULTILIB_DEFAULTS
418 #endif
420 /* Sometimes certain combinations of command options do not make
421 sense on a particular target machine. You can define a macro
422 `OVERRIDE_OPTIONS' to take account of this. This macro, if
423 defined, is executed once just after all the command options have
424 been parsed.
426 Don't use this macro to turn on various extra optimizations for
427 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
429 #ifndef SUBTARGET_OVERRIDE_OPTIONS
430 #define SUBTARGET_OVERRIDE_OPTIONS
431 #endif
433 #define OVERRIDE_OPTIONS \
434 do \
435 { \
436 /* These need to be done at start up. \
438 m32r_init (); \
439 SUBTARGET_OVERRIDE_OPTIONS \
440 } \
441 while (0)
443 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
444 #define SUBTARGET_OPTIMIZATION_OPTIONS
445 #endif
447 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
448 do \
449 { \
450 if (LEVEL == 1) \
451 flag_regmove = TRUE; \
452 \
453 if (SIZE) \
454 { \
455 flag_omit_frame_pointer = TRUE; \
456 flag_strength_reduce = FALSE; \
457 } \
458 \
459 SUBTARGET_OPTIMIZATION_OPTIONS \
460 } \
461 while (0)
463 /* Define this macro if debugging can be performed even without a
464 frame pointer. If this macro is defined, GCC will turn on the
465 `-fomit-frame-pointer' option whenever `-O' is specified. */
466 #define CAN_DEBUG_WITHOUT_FP
467 \f
468 /* Target machine storage layout. */
470 /* Define this if most significant bit is lowest numbered
471 in instructions that operate on numbered bit-fields. */
472 #define BITS_BIG_ENDIAN 1
474 /* Define this if most significant byte of a word is the lowest numbered. */
475 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
477 /* Define this if most significant word of a multiword number is the lowest
478 numbered. */
479 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
481 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
482 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
483 which will be used only when compiling libgcc2.c. Typically the
484 value will be set based on preprocessor defines. */
485 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
487 /* Width of a word, in units (bytes). */
488 #define UNITS_PER_WORD 4
490 /* Define this macro if it is advisable to hold scalars in registers
491 in a wider mode than that declared by the program. In such cases,
492 the value is constrained to be within the bounds of the declared
493 type, but kept valid in the wider mode. The signedness of the
494 extension may differ from that of the type. */
495 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
496 if (GET_MODE_CLASS (MODE) == MODE_INT \
497 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
498 { \
499 (MODE) = SImode; \
500 }
502 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
503 #define PARM_BOUNDARY 32
505 /* Boundary (in *bits*) on which stack pointer should be aligned. */
506 #define STACK_BOUNDARY 32
508 /* ALIGN FRAMES on word boundaries */
509 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
511 /* Allocation boundary (in *bits*) for the code of a function. */
512 #define FUNCTION_BOUNDARY 32
514 /* Alignment of field after `int : 0' in a structure. */
515 #define EMPTY_FIELD_BOUNDARY 32
517 /* Every structure's size must be a multiple of this. */
518 #define STRUCTURE_SIZE_BOUNDARY 8
520 /* A bit-field declared as `int' forces `int' alignment for the struct. */
521 #define PCC_BITFIELD_TYPE_MATTERS 1
523 /* No data type wants to be aligned rounder than this. */
524 #define BIGGEST_ALIGNMENT 32
526 /* The best alignment to use in cases where we have a choice. */
527 #define FASTEST_ALIGNMENT 32
529 /* Make strings word-aligned so strcpy from constants will be faster. */
530 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
531 ((TREE_CODE (EXP) == STRING_CST \
532 && (ALIGN) < FASTEST_ALIGNMENT) \
533 ? FASTEST_ALIGNMENT : (ALIGN))
535 /* Make arrays of chars word-aligned for the same reasons. */
536 #define DATA_ALIGNMENT(TYPE, ALIGN) \
537 (TREE_CODE (TYPE) == ARRAY_TYPE \
538 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
539 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
541 /* Set this nonzero if move instructions will actually fail to work
542 when given unaligned data. */
543 #define STRICT_ALIGNMENT 1
545 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
546 #define LABEL_ALIGN(insn) 2
547 \f
548 /* Layout of source language data types. */
550 #define SHORT_TYPE_SIZE 16
551 #define INT_TYPE_SIZE 32
552 #define LONG_TYPE_SIZE 32
553 #define LONG_LONG_TYPE_SIZE 64
554 #define FLOAT_TYPE_SIZE 32
555 #define DOUBLE_TYPE_SIZE 64
556 #define LONG_DOUBLE_TYPE_SIZE 64
558 /* Define this as 1 if `char' should by default be signed; else as 0. */
559 #define DEFAULT_SIGNED_CHAR 1
564 #define WCHAR_TYPE_SIZE 16
565 \f
566 /* Standard register usage. */
568 /* Number of actual hardware registers.
569 The hardware registers are assigned numbers for the compiler
570 from 0 to just below FIRST_PSEUDO_REGISTER.
571 All registers that the compiler knows about must be given numbers,
572 even those that are not normally considered general registers. */
574 #define M32R_NUM_REGISTERS 19
576 #ifndef SUBTARGET_NUM_REGISTERS
577 #define SUBTARGET_NUM_REGISTERS 0
578 #endif
580 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
582 /* 1 for registers that have pervasive standard uses
583 and are not available for the register allocator.
585 0-3 - arguments/results
586 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
587 6 - call used, gptmp
588 7 - call used, static chain pointer
589 8-11 - call saved
590 12 - call saved [reserved for global pointer]
591 13 - frame pointer
592 14 - subroutine link register
593 15 - stack pointer
594 16 - arg pointer
595 17 - carry flag
596 18 - accumulator
597 19 - accumulator 1 in the m32r/x
598 By default, the extension registers are not available. */
600 #ifndef SUBTARGET_FIXED_REGISTERS
601 #define SUBTARGET_FIXED_REGISTERS
602 #endif
604 #define FIXED_REGISTERS \
605 { \
606 0, 0, 0, 0, 0, 0, 0, 0, \
607 0, 0, 0, 0, 0, 0, 0, 1, \
608 1, 1, 1 \
609 SUBTARGET_FIXED_REGISTERS \
610 }
612 /* 1 for registers not available across function calls.
613 These must include the FIXED_REGISTERS and also any
614 registers that can be used without being saved.
615 The latter must include the registers where values are returned
616 and the register where structure-value addresses are passed.
617 Aside from that, you can include as many other registers as you like. */
619 #ifndef SUBTARGET_CALL_USED_REGISTERS
620 #define SUBTARGET_CALL_USED_REGISTERS
621 #endif
623 #define CALL_USED_REGISTERS \
624 { \
625 1, 1, 1, 1, 1, 1, 1, 1, \
626 0, 0, 0, 0, 0, 0, 1, 1, \
627 1, 1, 1 \
628 SUBTARGET_CALL_USED_REGISTERS \
629 }
631 /* Zero or more C statements that may conditionally modify two variables
632 `fixed_regs' and `call_used_regs' (both of type `char []') after they
633 have been initialized from the two preceding macros.
635 This is necessary in case the fixed or call-clobbered registers depend
636 on target flags.
638 You need not define this macro if it has no work to do. */
640 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
641 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
642 #else
643 #define CONDITIONAL_REGISTER_USAGE \
644 do \
645 { \
646 if (flag_pic) \
647 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
648 } \
649 while (0)
650 #endif
652 /* If defined, an initializer for a vector of integers, containing the
653 numbers of hard registers in the order in which GCC should
654 prefer to use them (from most preferred to least). */
656 #ifndef SUBTARGET_REG_ALLOC_ORDER
657 #define SUBTARGET_REG_ALLOC_ORDER
658 #endif
661 #define REG_ALLOC_ORDER \
662 { \
663 4, 5, 6, 7, 2, 3, 8, 9, 10, \
664 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
665 SUBTARGET_REG_ALLOC_ORDER \
666 }
669 #define REG_ALLOC_ORDER \
670 { \
671 0, 1, 2, 3, 4, 5, 6, 7, 8, \
672 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
673 SUBTARGET_REG_ALLOC_ORDER \
674 }
675 #endif
677 /* Return number of consecutive hard regs needed starting at reg REGNO
678 to hold something of mode MODE.
679 This is ordinarily the length in words of a value of mode MODE
680 but can be less for certain modes in special long registers. */
681 #define HARD_REGNO_NREGS(REGNO, MODE) \
682 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
684 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
687 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
688 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
690 /* A C expression that is nonzero if it is desirable to choose
691 register allocation so as to avoid move instructions between a
692 value of mode MODE1 and a value of mode MODE2.
694 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
695 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
696 MODE2)' must be zero. */
698 /* Tie QI/HI/SI modes together. */
699 #define MODES_TIEABLE_P(MODE1, MODE2) \
700 ( GET_MODE_CLASS (MODE1) == MODE_INT \
701 && GET_MODE_CLASS (MODE2) == MODE_INT \
702 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
703 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
705 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
706 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
707 \f
708 /* Register classes and constants. */
710 /* Define the classes of registers for register constraints in the
711 machine description. Also define ranges of constants.
713 One of the classes must always be named ALL_REGS and include all hard regs.
714 If there is more than one class, another class must be named NO_REGS
715 and contain no registers.
717 The name GENERAL_REGS must be the name of a class (or an alias for
718 another name such as ALL_REGS). This is the class of registers
719 that is allowed by "g" or "r" in a register constraint.
720 Also, registers outside this class are allocated only when
721 instructions express preferences for them.
723 The classes must be numbered in nondecreasing order; that is,
724 a larger-numbered class must never be contained completely
725 in a smaller-numbered class.
727 For any two classes, it is very desirable that there be another
728 class that represents their union.
730 It is important that any condition codes have class NO_REGS.
731 See `register_operand'. */
733 enum reg_class
734 {
736 };
738 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
740 /* Give names of register classes as strings for dump file. */
741 #define REG_CLASS_NAMES \
744 /* Define which registers fit in which classes.
745 This is an initializer for a vector of HARD_REG_SET
746 of length N_REG_CLASSES. */
748 #ifndef SUBTARGET_REG_CLASS_CARRY
749 #define SUBTARGET_REG_CLASS_CARRY 0
750 #endif
752 #ifndef SUBTARGET_REG_CLASS_ACCUM
753 #define SUBTARGET_REG_CLASS_ACCUM 0
754 #endif
756 #ifndef SUBTARGET_REG_CLASS_GENERAL
757 #define SUBTARGET_REG_CLASS_GENERAL 0
758 #endif
760 #ifndef SUBTARGET_REG_CLASS_ALL
761 #define SUBTARGET_REG_CLASS_ALL 0
762 #endif
764 #define REG_CLASS_CONTENTS \
765 { \
766 { 0x00000 }, \
767 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
768 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
769 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
770 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
771 }
773 /* The same information, inverted:
774 Return the class number of the smallest class containing
775 reg number REGNO. This could be a conditional expression
776 or could index an array. */
778 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
780 /* The class value for index registers, and the one for base regs. */
781 #define INDEX_REG_CLASS GENERAL_REGS
782 #define BASE_REG_CLASS GENERAL_REGS
784 #define REG_CLASS_FROM_LETTER(C) \
787 : NO_REGS)
789 /* These assume that REGNO is a hard or pseudo reg number.
790 They give nonzero only if REGNO is a hard reg of the suitable class
791 or a pseudo reg currently allocated to a suitable hard reg.
792 Since they use reg_renumber, they are safe only once reg_renumber
793 has been allocated, which happens in local-alloc.c. */
794 #define REGNO_OK_FOR_BASE_P(REGNO) \
795 ((REGNO) < FIRST_PSEUDO_REGISTER \
796 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
797 : GPR_P (reg_renumber[REGNO]))
799 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
801 /* Given an rtx X being reloaded into a reg required to be
802 in class CLASS, return the class of reg to actually use.
803 In general this is just CLASS; but on some machines
804 in some cases it is preferable to use a more restrictive class. */
805 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
807 /* Return the maximum number of consecutive registers
808 needed to represent mode MODE in a register of class CLASS. */
809 #define CLASS_MAX_NREGS(CLASS, MODE) \
810 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
812 /* The letters I, J, K, L, M, N, O, P in a register constraint string
813 can be used to stand for particular ranges of immediate operands.
814 This macro defines what the ranges are.
815 C is the letter, and VALUE is a constant value.
816 Return 1 if VALUE is in the range specified by C. */
817 /* 'I' is used for 8 bit signed immediates.
818 'J' is used for 16 bit signed immediates.
819 'K' is used for 16 bit unsigned immediates.
820 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
821 'M' is used for 24 bit unsigned immediates.
822 'N' is used for any 32 bit non-symbolic value.
823 'O' is used for 5 bit unsigned immediates (shift count).
824 'P' is used for 16 bit signed immediates for compares
825 (values in the range -32767 to +32768). */
827 /* Return true if a value is inside a range. */
828 #define IN_RANGE_P(VALUE, LOW, HIGH) \
829 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
830 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
832 /* Local to this file. */
833 #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f)
834 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
835 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
836 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
837 && ((X) >> 16) >= - 0x8000 \
838 && ((X) >> 16) <= 0x7fff)
839 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
840 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
841 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
842 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
843 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
845 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
854 : 0)
856 /* Similar, but for floating constants, and defining letters G and H.
857 Here VALUE is the CONST_DOUBLE rtx itself.
858 For the m32r, handle a few constants inline.
859 ??? We needn't treat DI and DF modes differently, but for now we do. */
860 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
863 : 0)
865 /* A C expression that defines the optional machine-dependent constraint
866 letters that can be used to segregate specific types of operands,
867 usually memory references, for the target machine. It should return 1 if
868 VALUE corresponds to the operand type represented by the constraint letter
869 C. If C is not defined as an extra constraint, the value returned should
870 be 0 regardless of VALUE. */
871 /* Q is for symbolic addresses loadable with ld24.
872 R is for symbolic addresses when ld24 can't be used.
873 S is for stores with pre {inc,dec}rement
874 T is for indirect of a pointer.
875 U is for loads with post increment. */
877 #define EXTRA_CONSTRAINT(VALUE, C) \
879 || addr24_operand (VALUE, VOIDmode)) \
881 || addr32_operand (VALUE, VOIDmode)) \
883 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
884 XEXP (VALUE, 0))) \
886 && memreg_operand (VALUE, GET_MODE (VALUE))) \
888 && LOAD_POSTINC_P (GET_MODE (VALUE), \
889 XEXP (VALUE, 0))) \
890 : 0)
891 \f
892 /* Stack layout and stack pointer usage. */
894 /* Define this macro if pushing a word onto the stack moves the stack
895 pointer to a smaller address. */
896 #define STACK_GROWS_DOWNWARD
898 /* Offset from frame pointer to start allocating local variables at.
899 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
900 first local allocated. Otherwise, it is the offset to the BEGINNING
901 of the first local allocated. */
902 /* The frame pointer points at the same place as the stack pointer, except if
903 alloca has been called. */
904 #define STARTING_FRAME_OFFSET \
905 M32R_STACK_ALIGN (current_function_outgoing_args_size)
907 /* Offset from the stack pointer register to the first location at which
908 outgoing arguments are placed. */
909 #define STACK_POINTER_OFFSET 0
911 /* Offset of first parameter from the argument pointer register value. */
912 #define FIRST_PARM_OFFSET(FNDECL) 0
914 /* Register to use for pushing function arguments. */
915 #define STACK_POINTER_REGNUM 15
917 /* Base register for access to local variables of the function. */
918 #define FRAME_POINTER_REGNUM 13
920 /* Base register for access to arguments of the function. */
921 #define ARG_POINTER_REGNUM 16
923 /* Register in which static-chain is passed to a function.
924 This must not be a register used by the prologue. */
925 #define STATIC_CHAIN_REGNUM 7
927 /* These aren't official macros. */
928 #define PROLOGUE_TMP_REGNUM 4
929 #define RETURN_ADDR_REGNUM 14
930 /* #define GP_REGNUM 12 */
931 #define CARRY_REGNUM 17
932 #define ACCUM_REGNUM 18
933 #define M32R_MAX_INT_REGS 16
935 #ifndef SUBTARGET_GPR_P
936 #define SUBTARGET_GPR_P(REGNO) 0
937 #endif
939 #ifndef SUBTARGET_ACCUM_P
940 #define SUBTARGET_ACCUM_P(REGNO) 0
941 #endif
943 #ifndef SUBTARGET_CARRY_P
944 #define SUBTARGET_CARRY_P(REGNO) 0
945 #endif
947 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
948 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
949 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
950 \f
951 /* Eliminating the frame and arg pointers. */
953 /* A C expression which is nonzero if a function must have and use a
954 frame pointer. This expression is evaluated in the reload pass.
955 If its value is nonzero the function will have a frame pointer. */
956 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
958 #if 0
959 /* C statement to store the difference between the frame pointer
960 and the stack pointer values immediately after the function prologue.
961 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
962 need not be defined. */
963 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
964 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
965 #endif
967 /* If defined, this macro specifies a table of register pairs used to
968 eliminate unneeded registers that point into the stack frame. If
969 it is not defined, the only elimination attempted by the compiler
970 is to replace references to the frame pointer with references to
971 the stack pointer.
973 Note that the elimination of the argument pointer with the stack
974 pointer is specified first since that is the preferred elimination. */
976 #define ELIMINABLE_REGS \
977 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
978 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
979 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
981 /* A C expression that returns nonzero if the compiler is allowed to
982 try to replace register number FROM-REG with register number
983 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
984 defined, and will usually be the constant 1, since most of the
985 cases preventing register elimination are things that the compiler
986 already knows about. */
988 #define CAN_ELIMINATE(FROM, TO) \
989 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
990 ? ! frame_pointer_needed \
991 : 1)
993 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
994 specifies the initial difference between the specified pair of
995 registers. This macro must be defined if `ELIMINABLE_REGS' is
996 defined. */
998 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
999 do \
1000 { \
1001 int size = m32r_compute_frame_size (get_frame_size ()); \
1002 \
1003 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1004 (OFFSET) = 0; \
1005 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1006 (OFFSET) = size - current_function_pretend_args_size; \
1007 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1008 (OFFSET) = size - current_function_pretend_args_size; \
1009 else \
1010 abort (); \
1011 } \
1012 while (0)
1013 \f
1014 /* Function argument passing. */
1016 /* If defined, the maximum amount of space required for outgoing
1017 arguments will be computed and placed into the variable
1018 `current_function_outgoing_args_size'. No space will be pushed
1019 onto the stack for each call; instead, the function prologue should
1020 increase the stack frame size by this amount. */
1021 #define ACCUMULATE_OUTGOING_ARGS 1
1023 /* Value is the number of bytes of arguments automatically
1024 popped when returning from a subroutine call.
1025 FUNDECL is the declaration node of the function (as a tree),
1026 FUNTYPE is the data type of the function (as a tree),
1027 or for a library call it is an identifier node for the subroutine name.
1028 SIZE is the number of bytes of arguments passed on the stack. */
1029 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1031 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1032 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1033 ((TYPE) != 0 \
1034 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1035 || TREE_ADDRESSABLE (TYPE)))
1037 /* Define a data type for recording info about an argument list
1038 during the scan of that argument list. This data type should
1039 hold all necessary information about the function itself
1040 and about the args processed so far, enough to enable macros
1041 such as FUNCTION_ARG to determine where the next arg should go. */
1042 #define CUMULATIVE_ARGS int
1044 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1045 for a call to a function whose data type is FNTYPE.
1046 For a library call, FNTYPE is 0. */
1047 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1048 ((CUM) = 0)
1050 /* The number of registers used for parameter passing. Local to this file. */
1051 #define M32R_MAX_PARM_REGS 4
1053 /* 1 if N is a possible register number for function argument passing. */
1054 #define FUNCTION_ARG_REGNO_P(N) \
1055 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1057 /* The ROUND_ADVANCE* macros are local to this file. */
1058 /* Round SIZE up to a word boundary. */
1059 #define ROUND_ADVANCE(SIZE) \
1060 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1062 /* Round arg MODE/TYPE up to the next word boundary. */
1063 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1064 ((MODE) == BLKmode \
1065 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1066 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1068 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1069 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1071 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1072 a reg. This includes arguments that have to be passed by reference as the
1073 pointer to them is passed in a reg if one is available (and that is what
1074 we're given).
1075 This macro is only used in this file. */
1076 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1077 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1079 /* Determine where to put an argument to a function.
1080 Value is zero to push the argument on the stack,
1081 or a hard register in which to store the argument.
1083 MODE is the argument's machine mode.
1084 TYPE is the data type of the argument (as a tree).
1085 This is null for libcalls where that information may
1086 not be available.
1087 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1088 the preceding args and about the function being called.
1089 NAMED is nonzero if this argument is a named parameter
1090 (otherwise it is an extra parameter matching an ellipsis). */
1091 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1092 and the rest are pushed. */
1093 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1094 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1095 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1096 : 0)
1098 /* A C expression for the number of words, at the beginning of an
1099 argument, must be put in registers. The value must be zero for
1100 arguments that are passed entirely in registers or that are entirely
1101 pushed on the stack.
1103 On some machines, certain arguments must be passed partially in
1104 registers and partially in memory. On these machines, typically the
1105 first @var{n} words of arguments are passed in registers, and the rest
1106 on the stack. If a multi-word argument (a @code{double} or a
1107 structure) crosses that boundary, its first few words must be passed
1108 in registers and the rest must be pushed. This macro tells the
1109 compiler when this occurs, and how many of the words should go in
1110 registers. */
1111 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1112 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
1114 /* A C expression that indicates when an argument must be passed by
1115 reference. If nonzero for an argument, a copy of that argument is
1116 made in memory and a pointer to the argument is passed instead of
1117 the argument itself. The pointer is passed in whatever way is
1118 appropriate for passing a pointer to that type. */
1119 /* All arguments greater than 8 bytes are passed this way. */
1120 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1121 ((TYPE) && m32r_pass_by_reference (TYPE))
1123 /* Update the data in CUM to advance over an argument
1124 of mode MODE and data type TYPE.
1125 (TYPE is null for libcalls where that information may not be available.) */
1126 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1127 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1128 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1130 /* If defined, a C expression that gives the alignment boundary, in bits,
1131 of an argument with the specified mode and type. If it is not defined,
1132 PARM_BOUNDARY is used for all arguments. */
1133 #if 0
1134 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1135 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1136 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1137 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
1138 #endif
1140 /* Implement `va_arg'. */
1141 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1142 m32r_va_arg (valist, type)
1143 \f
1144 /* Function results. */
1146 /* Define how to find the value returned by a function.
1147 VALTYPE is the data type of the value (as a tree).
1148 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1149 otherwise, FUNC is 0. */
1150 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1152 /* Define how to find the value returned by a library function
1153 assuming the value has mode MODE. */
1154 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1156 /* 1 if N is a possible register number for a function value
1157 as seen by the caller. */
1158 /* ??? What about r1 in DI/DF values. */
1159 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1161 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
1162 #define DEFAULT_PCC_STRUCT_RETURN 0
1163 \f
1164 /* Function entry and exit. */
1166 /* Initialize data used by insn expanders. This is called from
1167 init_emit, once for each function, before code is generated. */
1168 #define INIT_EXPANDERS m32r_init_expanders ()
1170 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1171 the stack pointer does not matter. The value is tested only in
1172 functions that have frame pointers.
1173 No definition is equivalent to always zero. */
1174 #define EXIT_IGNORE_STACK 1
1176 /* Output assembler code to FILE to increment profiler label # LABELNO
1177 for profiling a function entry. */
1178 #undef FUNCTION_PROFILER
1179 #define FUNCTION_PROFILER(FILE, LABELNO) \
1180 do \
1181 { \
1182 if (flag_pic) \
1183 { \
1188 } \
1189 else \
1190 { \
1191 if (TARGET_ADDR24) \
1193 else \
1194 { \
1198 } \
1199 } \
1201 } \
1202 while (0)
1203 \f
1204 /* Trampolines. */
1206 /* On the M32R, the trampoline is:
1208 mv r7, lr -> bl L1 ; 178e 7e01
1209 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
1210 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
1211 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
1212 L2: .word STATIC
1213 .word FUNCTION */
1215 #ifndef CACHE_FLUSH_FUNC
1217 #endif
1218 #ifndef CACHE_FLUSH_TRAP
1220 #endif
1222 /* Length in bytes of the trampoline for entering a nested function. */
1223 #define TRAMPOLINE_SIZE 24
1225 /* Emit RTL insns to initialize the variable parts of a trampoline.
1226 FNADDR is an RTX for the address of the function's pure code.
1227 CXT is an RTX for the static chain value for the function. */
1228 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1229 do \
1230 { \
1231 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1232 GEN_INT \
1233 (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \
1234 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1235 GEN_INT \
1236 (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \
1237 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1238 GEN_INT \
1239 (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \
1240 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \
1241 GEN_INT \
1242 (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \
1243 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \
1244 (CXT)); \
1245 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \
1246 (FNADDR)); \
1247 if (m32r_cache_flush_trap_string && m32r_cache_flush_trap_string[0]) \
1248 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
1249 GEN_INT (m32r_cache_flush_trap) )); \
1250 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \
1251 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, m32r_cache_flush_func), \
1252 0, VOIDmode, 3, TRAMP, Pmode, \
1253 GEN_INT (TRAMPOLINE_SIZE), SImode, \
1254 GEN_INT (3), SImode); \
1255 } \
1256 while (0)
1257 \f
1258 /* Library calls. */
1260 /* Generate calls to memcpy, memcmp and memset. */
1261 #define TARGET_MEM_FUNCTIONS
1262 \f
1263 /* Addressing modes, and classification of registers for them. */
1265 /* Maximum number of registers that can appear in a valid memory address. */
1266 #define MAX_REGS_PER_ADDRESS 1
1268 /* We have post-inc load and pre-dec,pre-inc store,
1269 but only for 4 byte vals. */
1270 #define HAVE_PRE_DECREMENT 1
1271 #define HAVE_PRE_INCREMENT 1
1272 #define HAVE_POST_INCREMENT 1
1274 /* Recognize any constant value that is a valid address. */
1275 #define CONSTANT_ADDRESS_P(X) \
1276 ( GET_CODE (X) == LABEL_REF \
1277 || GET_CODE (X) == SYMBOL_REF \
1278 || GET_CODE (X) == CONST_INT \
1279 || (GET_CODE (X) == CONST \
1280 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
1282 /* Nonzero if the constant value X is a legitimate general operand.
1283 We don't allow (plus symbol large-constant) as the relocations can't
1284 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1285 We allow all CONST_DOUBLE's as the md file patterns will force the
1286 constant to memory if they can't handle them. */
1288 #define LEGITIMATE_CONSTANT_P(X) \
1289 (! (GET_CODE (X) == CONST \
1290 && GET_CODE (XEXP (X, 0)) == PLUS \
1291 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1292 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1293 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1295 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1296 and check its validity for a certain class.
1297 We have two alternate definitions for each of them.
1298 The usual definition accepts all pseudo regs; the other rejects
1299 them unless they have been allocated suitable hard regs.
1300 The symbol REG_OK_STRICT causes the latter definition to be used.
1302 Most source files want to accept pseudo regs in the hope that
1303 they will get allocated to the class that the insn wants them to be in.
1304 Source files for reload pass need to be strict.
1305 After reload, it makes no difference, since pseudo regs have
1306 been eliminated by then. */
1308 #ifdef REG_OK_STRICT
1310 /* Nonzero if X is a hard reg that can be used as a base reg. */
1311 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1312 /* Nonzero if X is a hard reg that can be used as an index. */
1313 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1315 #else
1317 /* Nonzero if X is a hard reg that can be used as a base reg
1318 or if it is a pseudo reg. */
1319 #define REG_OK_FOR_BASE_P(X) \
1320 (GPR_P (REGNO (X)) \
1321 || (REGNO (X)) == ARG_POINTER_REGNUM \
1322 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1323 /* Nonzero if X is a hard reg that can be used as an index
1324 or if it is a pseudo reg. */
1325 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1327 #endif
1329 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1330 that is a valid memory address for an instruction.
1331 The MODE argument is the machine mode for the MEM expression
1332 that wants to use this address. */
1334 /* Local to this file. */
1335 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1337 /* Local to this file. */
1338 #define RTX_OK_FOR_OFFSET_P(X) \
1339 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1341 /* Local to this file. */
1342 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1343 (GET_CODE (X) == PLUS \
1344 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1345 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1347 /* Local to this file. */
1348 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1349 since more than one instruction will be required. */
1350 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1351 (GET_CODE (X) == LO_SUM \
1352 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
1353 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1354 && CONSTANT_P (XEXP (X, 1)))
1356 /* Local to this file. */
1357 /* Is this a load and increment operation. */
1358 #define LOAD_POSTINC_P(MODE, X) \
1359 (((MODE) == SImode || (MODE) == SFmode) \
1360 && GET_CODE (X) == POST_INC \
1361 && GET_CODE (XEXP (X, 0)) == REG \
1362 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1364 /* Local to this file. */
1365 /* Is this an increment/decrement and store operation. */
1366 #define STORE_PREINC_PREDEC_P(MODE, X) \
1367 (((MODE) == SImode || (MODE) == SFmode) \
1368 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1369 && GET_CODE (XEXP (X, 0)) == REG \
1370 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1372 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1373 do \
1374 { \
1375 if (RTX_OK_FOR_BASE_P (X)) \
1376 goto ADDR; \
1377 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1378 goto ADDR; \
1379 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1380 goto ADDR; \
1381 if (LOAD_POSTINC_P ((MODE), (X))) \
1382 goto ADDR; \
1383 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1384 goto ADDR; \
1385 } \
1386 while (0)
1388 /* Try machine-dependent ways of modifying an illegitimate address
1389 to be legitimate. If we find one, return the new, valid address.
1390 This macro is used in only one place: `memory_address' in explow.c.
1392 OLDX is the address as it was before break_out_memory_refs was called.
1393 In some cases it is useful to look at this to decide what needs to be done.
1395 MODE and WIN are passed so that this macro can use
1396 GO_IF_LEGITIMATE_ADDRESS.
1398 It is always safe for this macro to do nothing. It exists to recognize
1399 opportunities to optimize the output. */
1401 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1402 do \
1403 { \
1404 if (flag_pic) \
1405 (X) = m32r_legitimize_pic_address (X, NULL_RTX); \
1406 if (memory_address_p (MODE, X)) \
1407 goto WIN; \
1408 } \
1409 while (0)
1411 /* Go to LABEL if ADDR (a legitimate address expression)
1412 has an effect that depends on the machine mode it is used for. */
1413 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1414 do \
1415 { \
1416 if ( GET_CODE (ADDR) == PRE_DEC \
1417 || GET_CODE (ADDR) == PRE_INC \
1418 || GET_CODE (ADDR) == POST_INC \
1419 || GET_CODE (ADDR) == LO_SUM) \
1420 goto LABEL; \
1421 } \
1422 while (0)
1423 \f
1424 /* Condition code usage. */
1426 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
1427 floating point inequality comparison. */
1429 \f
1430 /* Costs. */
1432 /* Compute extra cost of moving data between one register class
1433 and another. */
1434 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1436 /* Compute the cost of moving data between registers and memory. */
1437 /* Memory is 3 times as expensive as registers.
1438 ??? Is that the right way to look at it? */
1439 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1440 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1442 /* The cost of a branch insn. */
1443 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1444 while (a < N && a). Branches aren't that expensive on the M32R so
1445 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1446 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1448 /* Nonzero if access to memory by bytes is slow and undesirable.
1449 For RISC chips, it means that access to memory by bytes is no
1450 better than access by words when possible, so grab a whole word
1451 and maybe make use of that. */
1452 #define SLOW_BYTE_ACCESS 1
1454 /* Define this macro if it is as good or better to call a constant
1455 function address than to call an address kept in a register. */
1456 #define NO_FUNCTION_CSE
1458 /* Define this macro if it is as good or better for a function to call
1459 itself with an explicit address than to call an address kept in a
1460 register. */
1461 #define NO_RECURSIVE_FUNCTION_CSE
1462 \f
1463 /* Section selection. */
1469 /* Define this macro if jump tables (for tablejump insns) should be
1470 output in the text section, along with the assembler instructions.
1471 Otherwise, the readonly data section is used.
1472 This macro is irrelevant if there is no separate readonly data section. */
1473 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1474 \f
1475 /* Position Independent Code. */
1477 /* The register number of the register used to address a table of static
1478 data addresses in memory. In some cases this register is defined by a
1479 processor's ``application binary interface'' (ABI). When this macro
1480 is defined, RTL is generated for this register once, as with the stack
1481 pointer and frame pointer registers. If this macro is not defined, it
1482 is up to the machine-dependent files to allocate such a register (if
1483 necessary). */
1484 #define PIC_OFFSET_TABLE_REGNUM 12
1486 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1487 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1488 is not defined. */
1489 /* This register is call-saved on the M32R. */
1490 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1492 /* By generating position-independent code, when two different programs (A
1493 and B) share a common library (libC.a), the text of the library can be
1494 shared whether or not the library is linked at the same address for both
1495 programs. In some of these environments, position-independent code
1496 requires not only the use of different addressing modes, but also
1497 special code to enable the use of these addressing modes.
1499 The FINALIZE_PIC macro serves as a hook to emit these special
1500 codes once the function is being compiled into assembly code, but not
1501 before. (It is not done before, because in the case of compiling an
1502 inline function, it would lead to multiple PIC prologues being
1503 included in functions which used inline functions and were compiled to
1504 assembly language.) */
1506 #define FINALIZE_PIC m32r_finalize_pic ()
1508 /* A C expression that is nonzero if X is a legitimate immediate
1509 operand on the target machine when generating position independent code.
1510 You can assume that X satisfies CONSTANT_P, so you need not
1511 check this. You can also assume `flag_pic' is true, so you need not
1512 check it either. You need not define this macro if all constants
1513 (including SYMBOL_REF) can be immediate operands when generating
1514 position independent code. */
1515 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1516 \f
1517 /* Control the assembler format that we output. */
1519 /* A C string constant describing how to begin a comment in the target
1520 assembler language. The compiler assumes that the comment will
1521 end at the end of the line. */
1524 /* Output to assembler file text saying following lines
1525 may contain character constants, extra white space, comments, etc. */
1528 /* Output to assembler file text saying following lines
1529 no longer contain unusual constructs. */
1532 /* Globalizing directive for a label. */
1535 /* If -Os, don't force line number labels to begin at the beginning of
1536 the word; we still want the assembler to try to put things in parallel,
1537 should that be possible.
1538 For m32r/d, instructions are never in parallel (other than with a nop)
1539 and the simulator and stub both handle a breakpoint in the middle of
1540 a word so don't ever force line number labels to begin at the beginning
1541 of a word. */
1543 #undef ASM_OUTPUT_SOURCE_LINE
1544 #define ASM_OUTPUT_SOURCE_LINE(file, line, counter) \
1545 do \
1546 { \
1548 line, counter); \
1549 assemble_name \
1550 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
1551 fprintf (file, (optimize_size || TARGET_M32R) \
1554 counter); \
1555 } \
1556 while (0)
1558 /* How to refer to registers in assembler output.
1559 This sequence is indexed by compiler's hard-register-number (see above). */
1560 #ifndef SUBTARGET_REGISTER_NAMES
1561 #define SUBTARGET_REGISTER_NAMES
1562 #endif
1564 #define REGISTER_NAMES \
1565 { \
1569 SUBTARGET_REGISTER_NAMES \
1570 }
1572 /* If defined, a C initializer for an array of structures containing
1573 a name and a register number. This macro defines additional names
1574 for hard registers, thus allowing the `asm' option in declarations
1575 to refer to registers using alternate names. */
1576 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1577 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1578 #endif
1580 #define ADDITIONAL_REGISTER_NAMES \
1581 { \
1586 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1587 }
1589 /* A C expression which evaluates to true if CODE is a valid
1590 punctuation character for use in the `PRINT_OPERAND' macro. */
1592 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1593 m32r_punct_chars[(unsigned char) (CHAR)]
1595 /* Print operand X (an rtx) in assembler syntax to file FILE.
1596 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1597 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1598 #define PRINT_OPERAND(FILE, X, CODE) \
1599 m32r_print_operand (FILE, X, CODE)
1601 /* A C compound statement to output to stdio stream STREAM the
1602 assembler syntax for an instruction operand that is a memory
1603 reference whose address is ADDR. ADDR is an RTL expression. */
1604 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1605 m32r_print_operand_address (FILE, ADDR)
1607 /* If defined, C string expressions to be used for the `%R', `%L',
1608 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1609 are useful when a single `md' file must support multiple assembler
1610 formats. In that case, the various `tm.h' files can define these
1611 macros differently. */
1617 /* This is how to output an element of a case-vector that is absolute. */
1618 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1619 do \
1620 { \
1621 char label[30]; \
1624 assemble_name (FILE, label); \
1626 } \
1627 while (0)
1629 /* This is how to output an element of a case-vector that is relative. */
1630 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1631 do \
1632 { \
1633 char label[30]; \
1636 assemble_name (FILE, label); \
1639 assemble_name (FILE, label); \
1641 } \
1642 while (0)
1644 /* The desired alignment for the location counter at the beginning
1645 of a loop. */
1646 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1647 if -malign-loops. */
1648 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1650 /* Define this to be the maximum number of insns to move around when moving
1651 a loop test from the top of a loop to the bottom
1652 and seeing whether to duplicate it. The default is thirty.
1654 Loop unrolling currently doesn't like this optimization, so
1655 disable doing if we are unrolling loops and saving space. */
1656 #define LOOP_TEST_THRESHOLD (optimize_size \
1657 && !flag_unroll_loops \
1658 && !flag_unroll_all_loops ? 2 : 30)
1660 /* This is how to output an assembler line
1661 that says to advance the location counter
1662 to a multiple of 2**LOG bytes. */
1663 /* .balign is used to avoid confusion. */
1664 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1665 do \
1666 { \
1667 if ((LOG) != 0) \
1669 } \
1670 while (0)
1672 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1673 separate, explicit argument. If you define this macro, it is used in
1674 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1675 handling the required alignment of the variable. The alignment is
1676 specified as the number of bits. */
1680 #undef ASM_OUTPUT_ALIGNED_COMMON
1681 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1682 do \
1683 { \
1684 if (! TARGET_SDATA_NONE \
1685 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1687 else \
1689 assemble_name ((FILE), (NAME)); \
1691 } \
1692 while (0)
1694 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1695 do \
1696 { \
1697 if (! TARGET_SDATA_NONE \
1698 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1700 else \
1701 bss_section (); \
1702 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1703 last_assemble_variable_decl = DECL; \
1704 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1705 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1706 } \
1707 while (0)
1708 \f
1709 /* Debugging information. */
1711 /* Generate DBX and DWARF debugging information. */
1712 #define DBX_DEBUGGING_INFO 1
1713 #define DWARF2_DEBUGGING_INFO 1
1715 /* Prefer STABS (for now). */
1716 #undef PREFERRED_DEBUGGING_TYPE
1717 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
1719 /* Turn off splitting of long stabs. */
1720 #define DBX_CONTIN_LENGTH 0
1721 \f
1722 /* Miscellaneous. */
1724 /* Specify the machine mode that this machine uses
1725 for the index in the tablejump instruction. */
1726 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1728 /* Define as C expression which evaluates to nonzero if the tablejump
1729 instruction expects the table to contain offsets from the address of the
1730 table.
1731 Do not define this if the table should contain absolute addresses. */
1732 /* It's not clear what PIC will look like or whether we want to use -fpic
1733 for the embedded form currently being talked about. For now require -fpic
1734 to get pc relative switch tables. */
1735 /*#define CASE_VECTOR_PC_RELATIVE 1 */
1737 /* Define if operations between registers always perform the operation
1738 on the full register even if a narrower mode is specified. */
1739 #define WORD_REGISTER_OPERATIONS
1741 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1742 will either zero-extend or sign-extend. The value of this macro should
1743 be the code that says which one of the two operations is implicitly
1744 done, NIL if none. */
1745 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1747 /* Max number of bytes we can move from memory
1748 to memory in one reasonably fast instruction. */
1749 #define MOVE_MAX 4
1751 /* Define this to be nonzero if shift instructions ignore all but the low-order
1752 few bits. */
1753 #define SHIFT_COUNT_TRUNCATED 1
1755 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1756 is done just by pretending it is already truncated. */
1757 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1759 /* Specify the machine mode that pointers have.
1760 After generation of rtl, the compiler makes no further distinction
1761 between pointers and any other objects of this machine mode. */
1762 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
1763 it's own problems (you have to add extendpsisi2 and truncsipsi2).
1764 Try to avoid it. */
1765 #define Pmode SImode
1767 /* A function address in a call instruction. */
1768 #define FUNCTION_MODE SImode
1769 \f
1770 /* Define the information needed to generate branch and scc insns. This is
1771 stored from the compare operation. Note that we can't use "rtx" here
1772 since it hasn't been defined! */
1776 /* M32R function types. */
1777 enum m32r_function_type
1778 {
1780 };
1782 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1784 /* Define this if you have defined special-purpose predicates in the
1785 file `MACHINE.c'. This macro is called within an initializer of an
1786 array of structures. The first field in the structure is the name
1787 of a predicate and the second field is an array of rtl codes. For
1788 each predicate, list all rtl codes that can be in expressions
1789 matched by the predicate. The list should have a trailing comma. */
1791 #define PREDICATE_CODES \
1799 CONST_DOUBLE, LABEL_REF, CONST, \
1800 SYMBOL_REF }}, \
1802 CONST_DOUBLE }}, \