1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* Information we maitain about each quantity. */
84 /* The number of refs to quantity Q. */
88 /* Insn number (counting from head of basic block)
89 where quantity Q was born. -1 if birth has not been recorded. */
93 /* Insn number (counting from head of basic block)
94 where given quantity died. Due to the way tying is done,
95 and the fact that we consider in this pass only regs that die but once,
96 a quantity can die only once. Each quantity's life span
97 is a set of consecutive insns. -1 if death has not been recorded. */
101 /* Number of words needed to hold the data in given quantity.
102 This depends on its machine mode. It is used for these purposes:
103 1. It is used in computing the relative importances of qtys,
104 which determines the order in which we look for regs for them.
105 2. It is used in rules that prevent tying several registers of
106 different sizes in a way that is geometrically impossible
107 (see combine_regs). */
111 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
115 /* The register number of one pseudo register whose reg_qty value is Q.
116 This register should be the head of the chain
117 maintained in reg_next_in_qty. */
121 /* Reg class contained in (smaller than) the preferred classes of all
122 the pseudo regs that are tied in given quantity.
123 This is the preferred class for allocating that quantity. */
125 enum reg_class min_class
;
127 /* Register class within which we allocate given qty if we can't get
128 its preferred class. */
130 enum reg_class alternate_class
;
132 /* This holds the mode of the registers that are tied to given qty,
133 or VOIDmode if registers with differing modes are tied together. */
135 enum machine_mode mode
;
137 /* the hard reg number chosen for given quantity,
138 or -1 if none was found. */
142 /* Nonzero if this quantity has been used in a SUBREG in some
143 way that is illegal. */
149 static struct qty
*qty
;
151 /* These fields are kept separately to speedup their clearing. */
153 /* We maintain two hard register sets that indicate suggested hard registers
154 for each quantity. The first, phys_copy_sugg, contains hard registers
155 that are tied to the quantity by a simple copy. The second contains all
156 hard registers that are tied to the quantity via an arithmetic operation.
158 The former register set is given priority for allocation. This tends to
159 eliminate copy insns. */
161 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 static HARD_REG_SET
*qty_phys_copy_sugg
;
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET
*qty_phys_sugg
;
171 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
173 static short *qty_phys_num_copy_sugg
;
175 /* Element Q is the number of suggested registers in qty_phys_sugg. */
177 static short *qty_phys_num_sugg
;
179 /* If (REG N) has been assigned a quantity number, is a register number
180 of another register assigned the same quantity number, or -1 for the
181 end of the chain. qty->first_reg point to the head of this chain. */
183 static int *reg_next_in_qty
;
185 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
187 of -1 if this register cannot be allocated by local-alloc,
188 or -2 if not known yet.
190 Note that if we see a use or death of pseudo register N with
191 reg_qty[N] == -2, register N must be local to the current block. If
192 it were used in more than one block, we would have reg_qty[N] == -1.
193 This relies on the fact that if reg_basic_block[N] is >= 0, register N
194 will not appear in any other block. We save a considerable number of
195 tests by exploiting this.
197 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
202 /* The offset (in words) of register N within its quantity.
203 This can be nonzero if register N is SImode, and has been tied
204 to a subreg of a DImode register. */
206 static char *reg_offset
;
208 /* Vector of substitutions of register numbers,
209 used to map pseudo regs into hardware regs.
210 This is set up as a result of register allocation.
211 Element N is the hard reg assigned to pseudo reg N,
212 or is -1 if no hard reg was assigned.
213 If N is a hard reg number, element N is N. */
217 /* Set of hard registers live at the current point in the scan
218 of the instructions in a basic block. */
220 static HARD_REG_SET regs_live
;
222 /* Each set of hard registers indicates registers live at a particular
223 point in the basic block. For N even, regs_live_at[N] says which
224 hard registers are needed *after* insn N/2 (i.e., they may not
225 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
227 If an object is to conflict with the inputs of insn J but not the
228 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
229 if it is to conflict with the outputs of insn J but not the inputs of
230 insn J + 1, it is said to die at index J*2 + 1. */
232 static HARD_REG_SET
*regs_live_at
;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number
;
237 static rtx this_insn
;
239 /* Used to communicate changes made by update_equiv_regs to
240 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
241 found or created, so that we can keep track of what memory accesses might
242 be created later, e.g. by reload. */
244 static rtx
*reg_equiv_replacement
;
246 /* Used for communication between update_equiv_regs and no_equiv. */
247 static rtx
*reg_equiv_init_insns
;
249 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
250 static int recorded_label_ref
;
252 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
253 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
254 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
255 static int contains_replace_regs
PARAMS ((rtx
, char *));
256 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
257 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
258 static void update_equiv_regs
PARAMS ((void));
259 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
260 static void block_alloc
PARAMS ((int));
261 static int qty_sugg_compare
PARAMS ((int, int));
262 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
263 static int qty_compare
PARAMS ((int, int));
264 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
265 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
266 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
267 static void update_qty_class
PARAMS ((int, int));
268 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
269 static void reg_is_born
PARAMS ((rtx
, int));
270 static void wipe_dead_reg
PARAMS ((rtx
, int));
271 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
272 int, int, int, int, int));
273 static void mark_life
PARAMS ((int, enum machine_mode
, int));
274 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
275 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
276 static int requires_inout
PARAMS ((const char *));
278 /* Allocate a new quantity (new within current basic block)
279 for register number REGNO which is born at index BIRTH
280 within the block. MODE and SIZE are info on reg REGNO. */
283 alloc_qty (regno
, mode
, size
, birth
)
285 enum machine_mode mode
;
288 register int qtyno
= next_qty
++;
290 reg_qty
[regno
] = qtyno
;
291 reg_offset
[regno
] = 0;
292 reg_next_in_qty
[regno
] = -1;
294 qty
[qtyno
].first_reg
= regno
;
295 qty
[qtyno
].size
= size
;
296 qty
[qtyno
].mode
= mode
;
297 qty
[qtyno
].birth
= birth
;
298 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
299 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
300 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
301 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
302 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
305 /* Main entry point of this file. */
313 /* We need to keep track of whether or not we recorded a LABEL_REF so
314 that we know if the jump optimizer needs to be rerun. */
315 recorded_label_ref
= 0;
317 /* Leaf functions and non-leaf functions have different needs.
318 If defined, let the machine say what kind of ordering we
320 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
321 ORDER_REGS_FOR_LOCAL_ALLOC
;
324 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
326 update_equiv_regs ();
328 /* This sets the maximum number of quantities we can have. Quantity
329 numbers start at zero and we can have one for each pseudo. */
330 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
332 /* Allocate vectors of temporary data.
333 See the declarations of these variables, above,
334 for what they mean. */
336 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
338 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
339 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
340 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
341 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
343 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
344 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
345 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
347 /* Allocate the reg_renumber array. */
348 allocate_reg_info (max_regno
, FALSE
, TRUE
);
350 /* Determine which pseudo-registers can be allocated by local-alloc.
351 In general, these are the registers used only in a single block and
352 which only die once. However, if a register's preferred class has only
353 a few entries, don't allocate this register here unless it is preferred
354 or nothing since retry_global_alloc won't be able to move it to
355 GENERAL_REGS if a reload register of this class is needed.
357 We need not be concerned with which block actually uses the register
358 since we will never see it outside that block. */
360 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
362 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1
363 && (reg_alternate_class (i
) == NO_REGS
364 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i
))))
370 /* Force loop below to initialize entire quantity array. */
373 /* Allocate each block's local registers, block by block. */
375 for (b
= 0; b
< n_basic_blocks
; b
++)
377 /* NEXT_QTY indicates which elements of the `qty_...'
378 vectors might need to be initialized because they were used
379 for the previous block; it is set to the entire array before
380 block 0. Initialize those, with explicit loop if there are few,
381 else with bzero and bcopy. Do not initialize vectors that are
382 explicit set by `alloc_qty'. */
386 for (i
= 0; i
< next_qty
; i
++)
388 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
389 qty_phys_num_copy_sugg
[i
] = 0;
390 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
391 qty_phys_num_sugg
[i
] = 0;
396 #define CLEAR(vector) \
397 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
399 CLEAR (qty_phys_copy_sugg
);
400 CLEAR (qty_phys_num_copy_sugg
);
401 CLEAR (qty_phys_sugg
);
402 CLEAR (qty_phys_num_sugg
);
411 free (qty_phys_copy_sugg
);
412 free (qty_phys_num_copy_sugg
);
413 free (qty_phys_sugg
);
414 free (qty_phys_num_sugg
);
418 free (reg_next_in_qty
);
420 return recorded_label_ref
;
423 /* Depth of loops we are in while in update_equiv_regs. */
424 static int loop_depth
;
426 /* Used for communication between the following two functions: contains
427 a MEM that we wish to ensure remains unchanged. */
428 static rtx equiv_mem
;
430 /* Set nonzero if EQUIV_MEM is modified. */
431 static int equiv_mem_modified
;
433 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
434 Called via note_stores. */
437 validate_equiv_mem_from_store (dest
, set
, data
)
439 rtx set ATTRIBUTE_UNUSED
;
440 void *data ATTRIBUTE_UNUSED
;
442 if ((GET_CODE (dest
) == REG
443 && reg_overlap_mentioned_p (dest
, equiv_mem
))
444 || (GET_CODE (dest
) == MEM
445 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
446 equiv_mem_modified
= 1;
449 /* Verify that no store between START and the death of REG invalidates
450 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
451 by storing into an overlapping memory location, or with a non-const
454 Return 1 if MEMREF remains valid. */
457 validate_equiv_mem (start
, reg
, memref
)
466 equiv_mem_modified
= 0;
468 /* If the memory reference has side effects or is volatile, it isn't a
469 valid equivalence. */
470 if (side_effects_p (memref
))
473 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
478 if (find_reg_note (insn
, REG_DEAD
, reg
))
481 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
482 && ! CONST_CALL_P (insn
))
485 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
487 /* If a register mentioned in MEMREF is modified via an
488 auto-increment, we lose the equivalence. Do the same if one
489 dies; although we could extend the life, it doesn't seem worth
492 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
493 if ((REG_NOTE_KIND (note
) == REG_INC
494 || REG_NOTE_KIND (note
) == REG_DEAD
)
495 && GET_CODE (XEXP (note
, 0)) == REG
496 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
503 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
506 contains_replace_regs (x
, reg_equiv_replace
)
508 char *reg_equiv_replace
;
512 enum rtx_code code
= GET_CODE (x
);
528 return reg_equiv_replace
[REGNO (x
)];
534 fmt
= GET_RTX_FORMAT (code
);
535 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
539 if (contains_replace_regs (XEXP (x
, i
), reg_equiv_replace
))
543 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
544 if (contains_replace_regs (XVECEXP (x
, i
, j
), reg_equiv_replace
))
552 /* TRUE if X references a memory location that would be affected by a store
556 memref_referenced_p (memref
, x
)
562 enum rtx_code code
= GET_CODE (x
);
578 return (reg_equiv_replacement
[REGNO (x
)]
579 && memref_referenced_p (memref
,
580 reg_equiv_replacement
[REGNO (x
)]));
583 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
588 /* If we are setting a MEM, it doesn't count (its address does), but any
589 other SET_DEST that has a MEM in it is referencing the MEM. */
590 if (GET_CODE (SET_DEST (x
)) == MEM
)
592 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
595 else if (memref_referenced_p (memref
, SET_DEST (x
)))
598 return memref_referenced_p (memref
, SET_SRC (x
));
604 fmt
= GET_RTX_FORMAT (code
);
605 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
609 if (memref_referenced_p (memref
, XEXP (x
, i
)))
613 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
614 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
622 /* TRUE if some insn in the range (START, END] references a memory location
623 that would be affected by a store to MEMREF. */
626 memref_used_between_p (memref
, start
, end
)
633 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
634 insn
= NEXT_INSN (insn
))
635 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
641 /* Return nonzero if the rtx X is invariant over the current function. */
643 function_invariant_p (x
)
648 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
650 if (GET_CODE (x
) == PLUS
651 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
652 && CONSTANT_P (XEXP (x
, 1)))
657 /* Find registers that are equivalent to a single value throughout the
658 compilation (either because they can be referenced in memory or are set once
659 from a single constant). Lower their priority for a register.
661 If such a register is only referenced once, try substituting its value
662 into the using insn. If it succeeds, we can eliminate the register
668 /* Set when an attempt should be made to replace a register with the
669 associated reg_equiv_replacement entry at the end of this function. */
670 char *reg_equiv_replace
;
674 reg_equiv_replace
= (char *) xcalloc (max_regno
, sizeof *reg_equiv_replace
);
675 reg_equiv_init_insns
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
676 reg_equiv_replacement
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
678 init_alias_analysis ();
682 /* Scan the insns and find which registers have equivalences. Do this
683 in a separate scan of the insns because (due to -fcse-follow-jumps)
684 a register can be set below its use. */
685 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
692 if (GET_CODE (insn
) == NOTE
)
694 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
696 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
703 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
704 if (REG_NOTE_KIND (note
) == REG_INC
)
705 no_equiv (XEXP (note
, 0), note
, NULL
);
707 set
= single_set (insn
);
709 /* If this insn contains more (or less) than a single SET,
710 only mark all destinations as having no known equivalence. */
713 note_stores (PATTERN (insn
), no_equiv
, NULL
);
716 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
720 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
722 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
724 note_stores (part
, no_equiv
, NULL
);
728 dest
= SET_DEST (set
);
731 /* If this sets a MEM to the contents of a REG that is only used
732 in a single basic block, see if the register is always equivalent
733 to that memory location and if moving the store from INSN to the
734 insn that set REG is safe. If so, put a REG_EQUIV note on the
737 Don't add a REG_EQUIV note if the insn already has one. The existing
738 REG_EQUIV is likely more useful than the one we are adding.
740 If one of the regs in the address is marked as reg_equiv_replace,
741 then we can't add this REG_EQUIV note. The reg_equiv_replace
742 optimization may move the set of this register immediately before
743 insn, which puts it after reg_equiv_init_insns[regno], and hence
744 the mention in the REG_EQUIV note would be to an uninitialized
746 /* ????? This test isn't good enough; we might see a MEM with a use of
747 a pseudo register before we see its setting insn that will cause
748 reg_equiv_replace for that pseudo to be set.
749 Equivalences to MEMs should be made in another pass, after the
750 reg_equiv_replace information has been gathered. */
752 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
753 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
754 && REG_BASIC_BLOCK (regno
) >= 0
755 && REG_N_SETS (regno
) == 1
756 && reg_equiv_init_insns
[regno
] != 0
757 && reg_equiv_init_insns
[regno
] != const0_rtx
758 && ! find_reg_note (XEXP (reg_equiv_init_insns
[regno
], 0),
760 && ! contains_replace_regs (XEXP (dest
, 0), reg_equiv_replace
))
762 rtx init_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
763 if (validate_equiv_mem (init_insn
, src
, dest
)
764 && ! memref_used_between_p (dest
, init_insn
, insn
))
765 REG_NOTES (init_insn
)
766 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
769 /* We only handle the case of a pseudo register being set
770 once, or always to the same value. */
771 /* ??? The mn10200 port breaks if we add equivalences for
772 values that need an ADDRESS_REGS register and set them equivalent
773 to a MEM of a pseudo. The actual problem is in the over-conservative
774 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
775 calculate_needs, but we traditionally work around this problem
776 here by rejecting equivalences when the destination is in a register
777 that's likely spilled. This is fragile, of course, since the
778 preferred class of a pseudo depends on all instructions that set
781 if (GET_CODE (dest
) != REG
782 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
783 || reg_equiv_init_insns
[regno
] == const0_rtx
784 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
785 && GET_CODE (src
) == MEM
))
787 /* This might be seting a SUBREG of a pseudo, a pseudo that is
788 also set somewhere else to a constant. */
789 note_stores (set
, no_equiv
, NULL
);
792 /* Don't handle the equivalence if the source is in a register
793 class that's likely to be spilled. */
794 if (GET_CODE (src
) == REG
795 && REGNO (src
) >= FIRST_PSEUDO_REGISTER
796 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src
))))
798 no_equiv (dest
, set
, NULL
);
802 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
804 if (REG_N_SETS (regno
) != 1
806 || ! function_invariant_p (XEXP (note
, 0))
807 || (reg_equiv_replacement
[regno
]
808 && ! rtx_equal_p (XEXP (note
, 0),
809 reg_equiv_replacement
[regno
]))))
811 no_equiv (dest
, set
, NULL
);
814 /* Record this insn as initializing this register. */
815 reg_equiv_init_insns
[regno
]
816 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init_insns
[regno
]);
818 /* If this register is known to be equal to a constant, record that
819 it is always equivalent to the constant. */
820 if (note
&& function_invariant_p (XEXP (note
, 0)))
821 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
823 /* If this insn introduces a "constant" register, decrease the priority
824 of that register. Record this insn if the register is only used once
825 more and the equivalence value is the same as our source.
827 The latter condition is checked for two reasons: First, it is an
828 indication that it may be more efficient to actually emit the insn
829 as written (if no registers are available, reload will substitute
830 the equivalence). Secondly, it avoids problems with any registers
831 dying in this insn whose death notes would be missed.
833 If we don't have a REG_EQUIV note, see if this insn is loading
834 a register used only in one basic block from a MEM. If so, and the
835 MEM remains unchanged for the life of the register, add a REG_EQUIV
838 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
840 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
841 && GET_CODE (SET_SRC (set
)) == MEM
842 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
843 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
848 int regno
= REGNO (dest
);
850 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
851 We might end up substituting the LABEL_REF for uses of the
852 pseudo here or later. That kind of transformation may turn an
853 indirect jump into a direct jump, in which case we must rerun the
854 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
855 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
856 || (GET_CODE (XEXP (note
, 0)) == CONST
857 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
858 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
860 recorded_label_ref
= 1;
862 reg_equiv_replacement
[regno
] = XEXP (note
, 0);
864 /* Don't mess with things live during setjmp. */
865 if (REG_LIVE_LENGTH (regno
) >= 0)
867 /* Note that the statement below does not affect the priority
869 REG_LIVE_LENGTH (regno
) *= 2;
872 /* If the register is referenced exactly twice, meaning it is
873 set once and used once, indicate that the reference may be
874 replaced by the equivalence we computed above. If the
875 register is only used in one basic block, this can't succeed
876 or combine would have done it.
878 It would be nice to use "loop_depth * 2" in the compare
879 below. Unfortunately, LOOP_DEPTH need not be constant within
880 a basic block so this would be too complicated.
882 This case normally occurs when a parameter is read from
883 memory and then used exactly once, not in a loop. */
885 if (REG_N_REFS (regno
) == 2
886 && REG_BASIC_BLOCK (regno
) < 0
887 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
888 reg_equiv_replace
[regno
] = 1;
893 /* Now scan all regs killed in an insn to see if any of them are
894 registers only used that once. If so, see if we can replace the
895 reference with the equivalent from. If we can, delete the
896 initializing reference and this register will go away. If we
897 can't replace the reference, and the instruction is not in a
898 loop, then move the register initialization just before the use,
899 so that they are in the same basic block. */
902 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
906 /* Keep track of which basic block we are in. */
907 if (block
+ 1 < n_basic_blocks
908 && BLOCK_HEAD (block
+ 1) == insn
)
913 if (GET_CODE (insn
) == NOTE
)
915 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
917 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
928 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
930 if (REG_NOTE_KIND (link
) == REG_DEAD
931 /* Make sure this insn still refers to the register. */
932 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
934 int regno
= REGNO (XEXP (link
, 0));
937 if (! reg_equiv_replace
[regno
])
940 /* reg_equiv_replace[REGNO] gets set only when
941 REG_N_REFS[REGNO] is 2, i.e. the register is set
942 once and used once. (If it were only set, but not used,
943 flow would have deleted the setting insns.) Hence
944 there can only be one insn in reg_equiv_init_insns. */
945 equiv_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
947 if (validate_replace_rtx (regno_reg_rtx
[regno
],
948 reg_equiv_replacement
[regno
], insn
))
950 remove_death (regno
, insn
);
951 REG_N_REFS (regno
) = 0;
952 PUT_CODE (equiv_insn
, NOTE
);
953 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
954 NOTE_SOURCE_FILE (equiv_insn
) = 0;
956 /* If we aren't in a loop, and there are no calls in
957 INSN or in the initialization of the register, then
958 move the initialization of the register to just
959 before INSN. Update the flow information. */
961 && GET_CODE (equiv_insn
) == INSN
962 && GET_CODE (insn
) == INSN
963 && REG_BASIC_BLOCK (regno
) < 0)
967 emit_insn_before (copy_rtx (PATTERN (equiv_insn
)), insn
);
968 REG_NOTES (PREV_INSN (insn
)) = REG_NOTES (equiv_insn
);
969 REG_NOTES (equiv_insn
) = 0;
971 PUT_CODE (equiv_insn
, NOTE
);
972 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
973 NOTE_SOURCE_FILE (equiv_insn
) = 0;
976 REG_BASIC_BLOCK (regno
) = 0;
978 REG_BASIC_BLOCK (regno
) = block
;
979 REG_N_CALLS_CROSSED (regno
) = 0;
980 REG_LIVE_LENGTH (regno
) = 2;
982 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
983 BLOCK_HEAD (block
) = PREV_INSN (insn
);
985 for (l
= 0; l
< n_basic_blocks
; l
++)
986 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
994 end_alias_analysis ();
995 free (reg_equiv_replace
);
996 free (reg_equiv_init_insns
);
997 free (reg_equiv_replacement
);
1000 /* Mark REG as having no known equivalence.
1001 Some instructions might have been proceessed before and furnished
1002 with REG_EQUIV notes for this register; these notes will have to be
1004 STORE is the piece of RTL that does the non-constant / conflicting
1005 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1006 but needs to be there because this function is called from note_stores. */
1008 no_equiv (reg
, store
, data
)
1009 rtx reg
, store ATTRIBUTE_UNUSED
;
1010 void *data ATTRIBUTE_UNUSED
;
1015 if (GET_CODE (reg
) != REG
)
1017 regno
= REGNO (reg
);
1018 list
= reg_equiv_init_insns
[regno
];
1019 if (list
== const0_rtx
)
1021 for (; list
; list
= XEXP (list
, 1))
1023 rtx insn
= XEXP (list
, 0);
1024 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1026 reg_equiv_init_insns
[regno
] = const0_rtx
;
1027 reg_equiv_replacement
[regno
] = NULL_RTX
;
1030 /* Allocate hard regs to the pseudo regs used only within block number B.
1031 Only the pseudos that die but once can be handled. */
1040 int insn_number
= 0;
1042 int max_uid
= get_max_uid ();
1044 int no_conflict_combined_regno
= -1;
1046 /* Count the instructions in the basic block. */
1048 insn
= BLOCK_END (b
);
1051 if (GET_CODE (insn
) != NOTE
)
1052 if (++insn_count
> max_uid
)
1054 if (insn
== BLOCK_HEAD (b
))
1056 insn
= PREV_INSN (insn
);
1059 /* +2 to leave room for a post_mark_life at the last insn and for
1060 the birth of a CLOBBER in the first insn. */
1061 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1062 sizeof (HARD_REG_SET
));
1064 /* Initialize table of hardware registers currently live. */
1066 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1068 /* This loop scans the instructions of the basic block
1069 and assigns quantities to registers.
1070 It computes which registers to tie. */
1072 insn
= BLOCK_HEAD (b
);
1075 if (GET_CODE (insn
) != NOTE
)
1080 register rtx link
, set
;
1081 register int win
= 0;
1082 register rtx r0
, r1
= NULL_RTX
;
1083 int combined_regno
= -1;
1086 this_insn_number
= insn_number
;
1089 extract_insn (insn
);
1090 which_alternative
= -1;
1092 /* Is this insn suitable for tying two registers?
1093 If so, try doing that.
1094 Suitable insns are those with at least two operands and where
1095 operand 0 is an output that is a register that is not
1098 We can tie operand 0 with some operand that dies in this insn.
1099 First look for operands that are required to be in the same
1100 register as operand 0. If we find such, only try tying that
1101 operand or one that can be put into that operand if the
1102 operation is commutative. If we don't find an operand
1103 that is required to be in the same register as operand 0,
1104 we can tie with any operand.
1106 Subregs in place of regs are also ok.
1108 If tying is done, WIN is set nonzero. */
1111 && recog_data
.n_operands
> 1
1112 && recog_data
.constraints
[0][0] == '='
1113 && recog_data
.constraints
[0][1] != '&')
1115 /* If non-negative, is an operand that must match operand 0. */
1116 int must_match_0
= -1;
1117 /* Counts number of alternatives that require a match with
1119 int n_matching_alts
= 0;
1121 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1123 const char *p
= recog_data
.constraints
[i
];
1124 int this_match
= (requires_inout (p
));
1126 n_matching_alts
+= this_match
;
1127 if (this_match
== recog_data
.n_alternatives
)
1131 r0
= recog_data
.operand
[0];
1132 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1134 /* Skip this operand if we found an operand that
1135 must match operand 0 and this operand isn't it
1136 and can't be made to be it by commutativity. */
1138 if (must_match_0
>= 0 && i
!= must_match_0
1139 && ! (i
== must_match_0
+ 1
1140 && recog_data
.constraints
[i
-1][0] == '%')
1141 && ! (i
== must_match_0
- 1
1142 && recog_data
.constraints
[i
][0] == '%'))
1145 /* Likewise if each alternative has some operand that
1146 must match operand zero. In that case, skip any
1147 operand that doesn't list operand 0 since we know that
1148 the operand always conflicts with operand 0. We
1149 ignore commutatity in this case to keep things simple. */
1150 if (n_matching_alts
== recog_data
.n_alternatives
1151 && 0 == requires_inout (recog_data
.constraints
[i
]))
1154 r1
= recog_data
.operand
[i
];
1156 /* If the operand is an address, find a register in it.
1157 There may be more than one register, but we only try one
1159 if (recog_data
.constraints
[i
][0] == 'p')
1160 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1163 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1165 /* We have two priorities for hard register preferences.
1166 If we have a move insn or an insn whose first input
1167 can only be in the same register as the output, give
1168 priority to an equivalence found from that insn. */
1170 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1172 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1173 win
= combine_regs (r1
, r0
, may_save_copy
,
1174 insn_number
, insn
, 0);
1181 /* Recognize an insn sequence with an ultimate result
1182 which can safely overlap one of the inputs.
1183 The sequence begins with a CLOBBER of its result,
1184 and ends with an insn that copies the result to itself
1185 and has a REG_EQUAL note for an equivalent formula.
1186 That note indicates what the inputs are.
1187 The result and the input can overlap if each insn in
1188 the sequence either doesn't mention the input
1189 or has a REG_NO_CONFLICT note to inhibit the conflict.
1191 We do the combining test at the CLOBBER so that the
1192 destination register won't have had a quantity number
1193 assigned, since that would prevent combining. */
1196 && GET_CODE (PATTERN (insn
)) == CLOBBER
1197 && (r0
= XEXP (PATTERN (insn
), 0),
1198 GET_CODE (r0
) == REG
)
1199 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1200 && XEXP (link
, 0) != 0
1201 && GET_CODE (XEXP (link
, 0)) == INSN
1202 && (set
= single_set (XEXP (link
, 0))) != 0
1203 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1204 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1207 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1208 /* Check that we have such a sequence. */
1209 && no_conflict_p (insn
, r0
, r1
))
1210 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1211 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1212 && (r1
= XEXP (XEXP (note
, 0), 0),
1213 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1214 && no_conflict_p (insn
, r0
, r1
))
1215 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1217 /* Here we care if the operation to be computed is
1219 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1220 || GET_CODE (XEXP (note
, 0)) == NE
1221 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1222 && (r1
= XEXP (XEXP (note
, 0), 1),
1223 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1224 && no_conflict_p (insn
, r0
, r1
))
1225 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1227 /* If we did combine something, show the register number
1228 in question so that we know to ignore its death. */
1230 no_conflict_combined_regno
= REGNO (r1
);
1233 /* If registers were just tied, set COMBINED_REGNO
1234 to the number of the register used in this insn
1235 that was tied to the register set in this insn.
1236 This register's qty should not be "killed". */
1240 while (GET_CODE (r1
) == SUBREG
)
1241 r1
= SUBREG_REG (r1
);
1242 combined_regno
= REGNO (r1
);
1245 /* Mark the death of everything that dies in this instruction,
1246 except for anything that was just combined. */
1248 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1249 if (REG_NOTE_KIND (link
) == REG_DEAD
1250 && GET_CODE (XEXP (link
, 0)) == REG
1251 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1252 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1253 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1255 wipe_dead_reg (XEXP (link
, 0), 0);
1257 /* Allocate qty numbers for all registers local to this block
1258 that are born (set) in this instruction.
1259 A pseudo that already has a qty is not changed. */
1261 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1263 /* If anything is set in this insn and then unused, mark it as dying
1264 after this insn, so it will conflict with our outputs. This
1265 can't match with something that combined, and it doesn't matter
1266 if it did. Do this after the calls to reg_is_set since these
1267 die after, not during, the current insn. */
1269 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1270 if (REG_NOTE_KIND (link
) == REG_UNUSED
1271 && GET_CODE (XEXP (link
, 0)) == REG
)
1272 wipe_dead_reg (XEXP (link
, 0), 1);
1274 /* If this is an insn that has a REG_RETVAL note pointing at a
1275 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1276 block, so clear any register number that combined within it. */
1277 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1278 && GET_CODE (XEXP (note
, 0)) == INSN
1279 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1280 no_conflict_combined_regno
= -1;
1283 /* Set the registers live after INSN_NUMBER. Note that we never
1284 record the registers live before the block's first insn, since no
1285 pseudos we care about are live before that insn. */
1287 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1288 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1290 if (insn
== BLOCK_END (b
))
1293 insn
= NEXT_INSN (insn
);
1296 /* Now every register that is local to this basic block
1297 should have been given a quantity, or else -1 meaning ignore it.
1298 Every quantity should have a known birth and death.
1300 Order the qtys so we assign them registers in order of the
1301 number of suggested registers they need so we allocate those with
1302 the most restrictive needs first. */
1304 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1305 for (i
= 0; i
< next_qty
; i
++)
1308 #define EXCHANGE(I1, I2) \
1309 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1314 /* Make qty_order[2] be the one to allocate last. */
1315 if (qty_sugg_compare (0, 1) > 0)
1317 if (qty_sugg_compare (1, 2) > 0)
1320 /* ... Fall through ... */
1322 /* Put the best one to allocate in qty_order[0]. */
1323 if (qty_sugg_compare (0, 1) > 0)
1326 /* ... Fall through ... */
1330 /* Nothing to do here. */
1334 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1337 /* Try to put each quantity in a suggested physical register, if it has one.
1338 This may cause registers to be allocated that otherwise wouldn't be, but
1339 this seems acceptable in local allocation (unlike global allocation). */
1340 for (i
= 0; i
< next_qty
; i
++)
1343 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1344 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1345 0, 1, qty
[q
].birth
, qty
[q
].death
);
1347 qty
[q
].phys_reg
= -1;
1350 /* Order the qtys so we assign them registers in order of
1351 decreasing length of life. Normally call qsort, but if we
1352 have only a very small number of quantities, sort them ourselves. */
1354 for (i
= 0; i
< next_qty
; i
++)
1357 #define EXCHANGE(I1, I2) \
1358 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1363 /* Make qty_order[2] be the one to allocate last. */
1364 if (qty_compare (0, 1) > 0)
1366 if (qty_compare (1, 2) > 0)
1369 /* ... Fall through ... */
1371 /* Put the best one to allocate in qty_order[0]. */
1372 if (qty_compare (0, 1) > 0)
1375 /* ... Fall through ... */
1379 /* Nothing to do here. */
1383 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1386 /* Now for each qty that is not a hardware register,
1387 look for a hardware register to put it in.
1388 First try the register class that is cheapest for this qty,
1389 if there is more than one class. */
1391 for (i
= 0; i
< next_qty
; i
++)
1394 if (qty
[q
].phys_reg
< 0)
1396 #ifdef INSN_SCHEDULING
1397 /* These values represent the adjusted lifetime of a qty so
1398 that it conflicts with qtys which appear near the start/end
1399 of this qty's lifetime.
1401 The purpose behind extending the lifetime of this qty is to
1402 discourage the register allocator from creating false
1405 The adjustment value is choosen to indicate that this qty
1406 conflicts with all the qtys in the instructions immediately
1407 before and after the lifetime of this qty.
1409 Experiments have shown that higher values tend to hurt
1410 overall code performance.
1412 If allocation using the extended lifetime fails we will try
1413 again with the qty's unadjusted lifetime. */
1414 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1415 int fake_death
= MIN (insn_number
* 2 + 1,
1416 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1419 if (N_REG_CLASSES
> 1)
1421 #ifdef INSN_SCHEDULING
1422 /* We try to avoid using hard registers allocated to qtys which
1423 are born immediately after this qty or die immediately before
1426 This optimization is only appropriate when we will run
1427 a scheduling pass after reload and we are not optimizing
1429 if (flag_schedule_insns_after_reload
1431 && !SMALL_REGISTER_CLASSES
)
1433 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1434 qty
[q
].mode
, q
, 0, 0,
1435 fake_birth
, fake_death
);
1436 if (qty
[q
].phys_reg
>= 0)
1440 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1441 qty
[q
].mode
, q
, 0, 0,
1442 qty
[q
].birth
, qty
[q
].death
);
1443 if (qty
[q
].phys_reg
>= 0)
1447 #ifdef INSN_SCHEDULING
1448 /* Similarly, avoid false dependencies. */
1449 if (flag_schedule_insns_after_reload
1451 && !SMALL_REGISTER_CLASSES
1452 && qty
[q
].alternate_class
!= NO_REGS
)
1453 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1454 qty
[q
].mode
, q
, 0, 0,
1455 fake_birth
, fake_death
);
1457 if (qty
[q
].alternate_class
!= NO_REGS
)
1458 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1459 qty
[q
].mode
, q
, 0, 0,
1460 qty
[q
].birth
, qty
[q
].death
);
1464 /* Now propagate the register assignments
1465 to the pseudo regs belonging to the qtys. */
1467 for (q
= 0; q
< next_qty
; q
++)
1468 if (qty
[q
].phys_reg
>= 0)
1470 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1471 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1475 free (regs_live_at
);
1479 /* Compare two quantities' priority for getting real registers.
1480 We give shorter-lived quantities higher priority.
1481 Quantities with more references are also preferred, as are quantities that
1482 require multiple registers. This is the identical prioritization as
1483 done by global-alloc.
1485 We used to give preference to registers with *longer* lives, but using
1486 the same algorithm in both local- and global-alloc can speed up execution
1487 of some programs by as much as a factor of three! */
1489 /* Note that the quotient will never be bigger than
1490 the value of floor_log2 times the maximum number of
1491 times a register can occur in one insn (surely less than 100).
1492 Multiplying this by 10000 can't overflow.
1493 QTY_CMP_PRI is also used by qty_sugg_compare. */
1495 #define QTY_CMP_PRI(q) \
1496 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
1497 / (qty[q].death - qty[q].birth)) * 10000))
1500 qty_compare (q1
, q2
)
1503 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1507 qty_compare_1 (q1p
, q2p
)
1511 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1512 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1517 /* If qtys are equally good, sort by qty number,
1518 so that the results of qsort leave nothing to chance. */
1522 /* Compare two quantities' priority for getting real registers. This version
1523 is called for quantities that have suggested hard registers. First priority
1524 goes to quantities that have copy preferences, then to those that have
1525 normal preferences. Within those groups, quantities with the lower
1526 number of preferences have the highest priority. Of those, we use the same
1527 algorithm as above. */
1529 #define QTY_CMP_SUGG(q) \
1530 (qty_phys_num_copy_sugg[q] \
1531 ? qty_phys_num_copy_sugg[q] \
1532 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1535 qty_sugg_compare (q1
, q2
)
1538 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1543 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1547 qty_sugg_compare_1 (q1p
, q2p
)
1551 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1552 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1557 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1561 /* If qtys are equally good, sort by qty number,
1562 so that the results of qsort leave nothing to chance. */
1569 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1570 Returns 1 if have done so, or 0 if cannot.
1572 Combining registers means marking them as having the same quantity
1573 and adjusting the offsets within the quantity if either of
1576 We don't actually combine a hard reg with a pseudo; instead
1577 we just record the hard reg as the suggestion for the pseudo's quantity.
1578 If we really combined them, we could lose if the pseudo lives
1579 across an insn that clobbers the hard reg (eg, movstr).
1581 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1582 there is no REG_DEAD note on INSN. This occurs during the processing
1583 of REG_NO_CONFLICT blocks.
1585 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1586 SETREG or if the input and output must share a register.
1587 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1589 There are elaborate checks for the validity of combining. */
1592 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1593 rtx usedreg
, setreg
;
1599 register int ureg
, sreg
;
1600 register int offset
= 0;
1604 /* Determine the numbers and sizes of registers being used. If a subreg
1605 is present that does not change the entire register, don't consider
1606 this a copy insn. */
1608 while (GET_CODE (usedreg
) == SUBREG
)
1610 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1612 offset
+= SUBREG_WORD (usedreg
);
1613 usedreg
= SUBREG_REG (usedreg
);
1615 if (GET_CODE (usedreg
) != REG
)
1617 ureg
= REGNO (usedreg
);
1618 usize
= REG_SIZE (usedreg
);
1620 while (GET_CODE (setreg
) == SUBREG
)
1622 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1624 offset
-= SUBREG_WORD (setreg
);
1625 setreg
= SUBREG_REG (setreg
);
1627 if (GET_CODE (setreg
) != REG
)
1629 sreg
= REGNO (setreg
);
1630 ssize
= REG_SIZE (setreg
);
1632 /* If UREG is a pseudo-register that hasn't already been assigned a
1633 quantity number, it means that it is not local to this block or dies
1634 more than once. In either event, we can't do anything with it. */
1635 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1636 /* Do not combine registers unless one fits within the other. */
1637 || (offset
> 0 && usize
+ offset
> ssize
)
1638 || (offset
< 0 && usize
+ offset
< ssize
)
1639 /* Do not combine with a smaller already-assigned object
1640 if that smaller object is already combined with something bigger. */
1641 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1642 && usize
< qty
[reg_qty
[ureg
]].size
)
1643 /* Can't combine if SREG is not a register we can allocate. */
1644 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1645 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1646 These have already been taken care of. This probably wouldn't
1647 combine anyway, but don't take any chances. */
1648 || (ureg
>= FIRST_PSEUDO_REGISTER
1649 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1650 /* Don't tie something to itself. In most cases it would make no
1651 difference, but it would screw up if the reg being tied to itself
1652 also dies in this insn. */
1654 /* Don't try to connect two different hardware registers. */
1655 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1656 /* Don't use a hard reg that might be spilled. */
1657 || (ureg
< FIRST_PSEUDO_REGISTER
1658 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg
)))
1659 || (sreg
< FIRST_PSEUDO_REGISTER
1660 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg
)))
1661 /* Don't connect two different machine modes if they have different
1662 implications as to which registers may be used. */
1663 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1666 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1667 qty_phys_sugg for the pseudo instead of tying them.
1669 Return "failure" so that the lifespan of UREG is terminated here;
1670 that way the two lifespans will be disjoint and nothing will prevent
1671 the pseudo reg from being given this hard reg. */
1673 if (ureg
< FIRST_PSEUDO_REGISTER
)
1675 /* Allocate a quantity number so we have a place to put our
1677 if (reg_qty
[sreg
] == -2)
1678 reg_is_born (setreg
, 2 * insn_number
);
1680 if (reg_qty
[sreg
] >= 0)
1683 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1685 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1686 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1688 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1690 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1691 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1697 /* Similarly for SREG a hard register and UREG a pseudo register. */
1699 if (sreg
< FIRST_PSEUDO_REGISTER
)
1702 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1704 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1705 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1707 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1709 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1710 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1715 /* At this point we know that SREG and UREG are both pseudos.
1716 Do nothing if SREG already has a quantity or is a register that we
1718 if (reg_qty
[sreg
] >= -1
1719 /* If we are not going to let any regs live across calls,
1720 don't tie a call-crossing reg to a non-call-crossing reg. */
1721 || (current_function_has_nonlocal_label
1722 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1723 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1726 /* We don't already know about SREG, so tie it to UREG
1727 if this is the last use of UREG, provided the classes they want
1730 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1731 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1733 /* Add SREG to UREG's quantity. */
1734 sqty
= reg_qty
[ureg
];
1735 reg_qty
[sreg
] = sqty
;
1736 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1737 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1738 qty
[sqty
].first_reg
= sreg
;
1740 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1741 update_qty_class (sqty
, sreg
);
1743 /* Update info about quantity SQTY. */
1744 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1745 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1750 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1751 reg_offset
[i
] -= offset
;
1753 qty
[sqty
].size
= ssize
;
1754 qty
[sqty
].mode
= GET_MODE (setreg
);
1763 /* Return 1 if the preferred class of REG allows it to be tied
1764 to a quantity or register whose class is CLASS.
1765 True if REG's reg class either contains or is contained in CLASS. */
1768 reg_meets_class_p (reg
, class)
1770 enum reg_class
class;
1772 register enum reg_class rclass
= reg_preferred_class (reg
);
1773 return (reg_class_subset_p (rclass
, class)
1774 || reg_class_subset_p (class, rclass
));
1777 /* Update the class of QTYNO assuming that REG is being tied to it. */
1780 update_qty_class (qtyno
, reg
)
1784 enum reg_class rclass
= reg_preferred_class (reg
);
1785 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1786 qty
[qtyno
].min_class
= rclass
;
1788 rclass
= reg_alternate_class (reg
);
1789 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1790 qty
[qtyno
].alternate_class
= rclass
;
1792 if (REG_CHANGES_MODE (reg
))
1793 qty
[qtyno
].changes_mode
= 1;
1796 /* Handle something which alters the value of an rtx REG.
1798 REG is whatever is set or clobbered. SETTER is the rtx that
1799 is modifying the register.
1801 If it is not really a register, we do nothing.
1802 The file-global variables `this_insn' and `this_insn_number'
1803 carry info from `block_alloc'. */
1806 reg_is_set (reg
, setter
, data
)
1809 void *data ATTRIBUTE_UNUSED
;
1811 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1812 a hard register. These may actually not exist any more. */
1814 if (GET_CODE (reg
) != SUBREG
1815 && GET_CODE (reg
) != REG
)
1818 /* Mark this register as being born. If it is used in a CLOBBER, mark
1819 it as being born halfway between the previous insn and this insn so that
1820 it conflicts with our inputs but not the outputs of the previous insn. */
1822 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1825 /* Handle beginning of the life of register REG.
1826 BIRTH is the index at which this is happening. */
1829 reg_is_born (reg
, birth
)
1835 if (GET_CODE (reg
) == SUBREG
)
1836 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1838 regno
= REGNO (reg
);
1840 if (regno
< FIRST_PSEUDO_REGISTER
)
1842 mark_life (regno
, GET_MODE (reg
), 1);
1844 /* If the register was to have been born earlier that the present
1845 insn, mark it as live where it is actually born. */
1846 if (birth
< 2 * this_insn_number
)
1847 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1851 if (reg_qty
[regno
] == -2)
1852 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1854 /* If this register has a quantity number, show that it isn't dead. */
1855 if (reg_qty
[regno
] >= 0)
1856 qty
[reg_qty
[regno
]].death
= -1;
1860 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1861 REG is an output that is dying (i.e., it is never used), otherwise it
1862 is an input (the normal case).
1863 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1866 wipe_dead_reg (reg
, output_p
)
1870 register int regno
= REGNO (reg
);
1872 /* If this insn has multiple results,
1873 and the dead reg is used in one of the results,
1874 extend its life to after this insn,
1875 so it won't get allocated together with any other result of this insn.
1877 It is unsafe to use !single_set here since it will ignore an unused
1878 output. Just because an output is unused does not mean the compiler
1879 can assume the side effect will not occur. Consider if REG appears
1880 in the address of an output and we reload the output. If we allocate
1881 REG to the same hard register as an unused output we could set the hard
1882 register before the output reload insn. */
1883 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1884 && multiple_sets (this_insn
))
1887 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1889 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1890 if (GET_CODE (set
) == SET
1891 && GET_CODE (SET_DEST (set
)) != REG
1892 && !rtx_equal_p (reg
, SET_DEST (set
))
1893 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1898 /* If this register is used in an auto-increment address, then extend its
1899 life to after this insn, so that it won't get allocated together with
1900 the result of this insn. */
1901 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
1904 if (regno
< FIRST_PSEUDO_REGISTER
)
1906 mark_life (regno
, GET_MODE (reg
), 0);
1908 /* If a hard register is dying as an output, mark it as in use at
1909 the beginning of this insn (the above statement would cause this
1912 post_mark_life (regno
, GET_MODE (reg
), 1,
1913 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1916 else if (reg_qty
[regno
] >= 0)
1917 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
1920 /* Find a block of SIZE words of hard regs in reg_class CLASS
1921 that can hold something of machine-mode MODE
1922 (but actually we test only the first of the block for holding MODE)
1923 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1924 and return the number of the first of them.
1925 Return -1 if such a block cannot be found.
1926 If QTYNO crosses calls, insist on a register preserved by calls,
1927 unless ACCEPT_CALL_CLOBBERED is nonzero.
1929 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1930 register is available. If not, return -1. */
1933 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
1934 born_index
, dead_index
)
1935 enum reg_class
class;
1936 enum machine_mode mode
;
1938 int accept_call_clobbered
;
1939 int just_try_suggested
;
1940 int born_index
, dead_index
;
1942 register int i
, ins
;
1944 /* Declare it register if it's a scalar. */
1947 HARD_REG_SET used
, first_used
;
1948 #ifdef ELIMINABLE_REGS
1949 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1952 /* Validate our parameters. */
1953 if (born_index
< 0 || born_index
> dead_index
)
1956 /* Don't let a pseudo live in a reg across a function call
1957 if we might get a nonlocal goto. */
1958 if (current_function_has_nonlocal_label
1959 && qty
[qtyno
].n_calls_crossed
> 0)
1962 if (accept_call_clobbered
)
1963 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1964 else if (qty
[qtyno
].n_calls_crossed
== 0)
1965 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1967 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1969 if (accept_call_clobbered
)
1970 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
1972 for (ins
= born_index
; ins
< dead_index
; ins
++)
1973 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1975 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1977 /* Don't use the frame pointer reg in local-alloc even if
1978 we may omit the frame pointer, because if we do that and then we
1979 need a frame pointer, reload won't know how to move the pseudo
1980 to another hard reg. It can move only regs made by global-alloc.
1982 This is true of any register that can be eliminated. */
1983 #ifdef ELIMINABLE_REGS
1984 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
1985 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
1986 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1987 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1988 that it might be eliminated into. */
1989 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
1992 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
1995 #ifdef CLASS_CANNOT_CHANGE_MODE
1996 if (qty
[qtyno
].changes_mode
)
1997 IOR_HARD_REG_SET (used
,
1998 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
2001 /* Normally, the registers that can be used for the first register in
2002 a multi-register quantity are the same as those that can be used for
2003 subsequent registers. However, if just trying suggested registers,
2004 restrict our consideration to them. If there are copy-suggested
2005 register, try them. Otherwise, try the arithmetic-suggested
2007 COPY_HARD_REG_SET (first_used
, used
);
2009 if (just_try_suggested
)
2011 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2012 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2014 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2017 /* If all registers are excluded, we can't do anything. */
2018 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2020 /* If at least one would be suitable, test each hard reg. */
2022 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2024 #ifdef REG_ALLOC_ORDER
2025 int regno
= reg_alloc_order
[i
];
2029 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2030 && HARD_REGNO_MODE_OK (regno
, mode
)
2031 && (qty
[qtyno
].n_calls_crossed
== 0
2032 || accept_call_clobbered
2033 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2036 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2037 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2040 /* Mark that this register is in use between its birth and death
2042 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2045 #ifndef REG_ALLOC_ORDER
2046 /* Skip starting points we know will lose. */
2053 /* If we are just trying suggested register, we have just tried copy-
2054 suggested registers, and there are arithmetic-suggested registers,
2057 /* If it would be profitable to allocate a call-clobbered register
2058 and save and restore it around calls, do that. */
2059 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2060 && qty_phys_num_sugg
[qtyno
] != 0)
2062 /* Don't try the copy-suggested regs again. */
2063 qty_phys_num_copy_sugg
[qtyno
] = 0;
2064 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2065 born_index
, dead_index
);
2068 /* We need not check to see if the current function has nonlocal
2069 labels because we don't put any pseudos that are live over calls in
2070 registers in that case. */
2072 if (! accept_call_clobbered
2073 && flag_caller_saves
2074 && ! just_try_suggested
2075 && qty
[qtyno
].n_calls_crossed
!= 0
2076 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2077 qty
[qtyno
].n_calls_crossed
))
2079 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2081 caller_save_needed
= 1;
2087 /* Mark that REGNO with machine-mode MODE is live starting from the current
2088 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2092 mark_life (regno
, mode
, life
)
2094 enum machine_mode mode
;
2097 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2100 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2103 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2106 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2107 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2108 to insn number DEATH (exclusive). */
2111 post_mark_life (regno
, mode
, life
, birth
, death
)
2113 enum machine_mode mode
;
2114 int life
, birth
, death
;
2116 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2118 /* Declare it register if it's a scalar. */
2121 HARD_REG_SET this_reg
;
2123 CLEAR_HARD_REG_SET (this_reg
);
2125 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2128 while (birth
< death
)
2130 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2134 while (birth
< death
)
2136 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2141 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2142 is the register being clobbered, and R1 is a register being used in
2143 the equivalent expression.
2145 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2146 in which it is used, return 1.
2148 Otherwise, return 0. */
2151 no_conflict_p (insn
, r0
, r1
)
2152 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2155 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2158 /* If R1 is a hard register, return 0 since we handle this case
2159 when we scan the insns that actually use it. */
2162 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2163 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2164 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2167 last
= XEXP (note
, 0);
2169 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2172 if (find_reg_note (p
, REG_DEAD
, r1
))
2175 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2176 some earlier optimization pass has inserted instructions into
2177 the sequence, and it is not safe to perform this optimization.
2178 Note that emit_no_conflict_block always ensures that this is
2179 true when these sequences are created. */
2180 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2187 /* Return the number of alternatives for which the constraint string P
2188 indicates that the operand must be equal to operand 0 and that no register
2197 int reg_allowed
= 0;
2198 int num_matching_alts
= 0;
2203 case '=': case '+': case '?':
2204 case '#': case '&': case '!':
2206 case '1': case '2': case '3': case '4': case '5':
2207 case '6': case '7': case '8': case '9':
2208 case 'm': case '<': case '>': case 'V': case 'o':
2209 case 'E': case 'F': case 'G': case 'H':
2210 case 's': case 'i': case 'n':
2211 case 'I': case 'J': case 'K': case 'L':
2212 case 'M': case 'N': case 'O': case 'P':
2213 #ifdef EXTRA_CONSTRAINT
2214 case 'Q': case 'R': case 'S': case 'T': case 'U':
2217 /* These don't say anything we care about. */
2221 if (found_zero
&& ! reg_allowed
)
2222 num_matching_alts
++;
2224 found_zero
= reg_allowed
= 0;
2238 if (found_zero
&& ! reg_allowed
)
2239 num_matching_alts
++;
2241 return num_matching_alts
;
2245 dump_local_alloc (file
)
2249 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2250 if (reg_renumber
[i
] != -1)
2251 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);