1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2015 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; Return true if OP is a non-fp register_operand.
31 (define_predicate "register_and_not_any_fp_reg_operand"
32 (and (match_code "reg")
33 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
35 ;; True if the operand is a GENERAL class register.
36 (define_predicate "general_reg_operand"
37 (and (match_code "reg")
38 (match_test "GENERAL_REG_P (op)")))
40 ;; Return true if OP is a register operand other than an i387 fp register.
41 (define_predicate "register_and_not_fp_reg_operand"
42 (and (match_code "reg")
43 (not (match_test "STACK_REGNO_P (REGNO (op))"))))
45 ;; True if the operand is an MMX register.
46 (define_predicate "mmx_reg_operand"
47 (and (match_code "reg")
48 (match_test "MMX_REGNO_P (REGNO (op))")))
50 ;; True if the operand is an SSE register.
51 (define_predicate "sse_reg_operand"
52 (and (match_code "reg")
53 (match_test "SSE_REGNO_P (REGNO (op))")))
55 ;; True if the operand is an AVX-512 new register.
56 (define_predicate "ext_sse_reg_operand"
57 (and (match_code "reg")
58 (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
60 ;; True if the operand is an AVX-512 mask register.
61 (define_predicate "mask_reg_operand"
62 (and (match_code "reg")
63 (match_test "MASK_REGNO_P (REGNO (op))")))
65 ;; True if the operand is a Q_REGS class register.
66 (define_predicate "q_regs_operand"
67 (match_operand 0 "register_operand")
69 if (GET_CODE (op) == SUBREG)
71 return ANY_QI_REG_P (op);
74 ;; Return true if OP is a memory operands that can be used in sibcalls.
75 (define_predicate "sibcall_memory_operand"
76 (and (match_operand 0 "memory_operand")
77 (match_test "CONSTANT_P (XEXP (op, 0))")))
79 ;; Match an SI or HImode register for a zero_extract.
80 (define_special_predicate "ext_register_operand"
81 (match_operand 0 "register_operand")
83 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
84 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
86 if (GET_CODE (op) == SUBREG)
89 /* Be careful to accept only registers having upper parts. */
91 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
94 ;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
95 (define_predicate "nonimmediate_x64nomem_operand"
96 (if_then_else (match_test "TARGET_64BIT")
97 (match_operand 0 "register_operand")
98 (match_operand 0 "nonimmediate_operand")))
100 ;; Match general operands, but exclude memory operands on 64bit targets.
101 (define_predicate "general_x64nomem_operand"
102 (if_then_else (match_test "TARGET_64BIT")
103 (match_operand 0 "nonmemory_operand")
104 (match_operand 0 "general_operand")))
106 ;; Return true if op is the AX register.
107 (define_predicate "ax_reg_operand"
108 (and (match_code "reg")
109 (match_test "REGNO (op) == AX_REG")))
111 ;; Return true if op is the flags register.
112 (define_predicate "flags_reg_operand"
113 (and (match_code "reg")
114 (match_test "REGNO (op) == FLAGS_REG")))
116 ;; Return true if op is one of QImode registers: %[abcd][hl].
117 (define_predicate "QIreg_operand"
118 (match_test "QI_REG_P (op)"))
120 ;; Return true if op is a QImode register operand other than
122 (define_predicate "ext_QIreg_operand"
123 (and (match_code "reg")
124 (match_test "TARGET_64BIT")
125 (match_test "REGNO (op) > BX_REG")))
127 ;; Return true if VALUE is symbol reference
128 (define_predicate "symbol_operand"
129 (match_code "symbol_ref"))
131 ;; Return true if VALUE can be stored in a sign extended immediate field.
132 (define_predicate "x86_64_immediate_operand"
133 (match_code "const_int,symbol_ref,label_ref,const")
136 return immediate_operand (op, mode);
138 switch (GET_CODE (op))
141 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
142 to be at least 32 and this all acceptable constants are
143 represented as CONST_INT. */
144 if (HOST_BITS_PER_WIDE_INT == 32)
148 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
149 return trunc_int_for_mode (val, SImode) == val;
154 /* For certain code models, the symbolic references are known to fit.
155 in CM_SMALL_PIC model we know it fits if it is local to the shared
156 library. Don't count TLS SYMBOL_REFs here, since they should fit
157 only if inside of UNSPEC handled below. */
158 /* TLS symbols are not constant. */
159 if (SYMBOL_REF_TLS_MODEL (op))
161 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
162 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
165 /* For certain code models, the code is near as well. */
166 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
167 || ix86_cmodel == CM_KERNEL);
170 /* We also may accept the offsetted memory references in certain
172 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
173 switch (XINT (XEXP (op, 0), 1))
175 case UNSPEC_GOTPCREL:
177 case UNSPEC_GOTNTPOFF:
184 if (GET_CODE (XEXP (op, 0)) == PLUS)
186 rtx op1 = XEXP (XEXP (op, 0), 0);
187 rtx op2 = XEXP (XEXP (op, 0), 1);
188 HOST_WIDE_INT offset;
190 if (ix86_cmodel == CM_LARGE)
192 if (!CONST_INT_P (op2))
194 offset = trunc_int_for_mode (INTVAL (op2), DImode);
195 switch (GET_CODE (op1))
198 /* TLS symbols are not constant. */
199 if (SYMBOL_REF_TLS_MODEL (op1))
201 /* For CM_SMALL assume that latest object is 16MB before
202 end of 31bits boundary. We may also accept pretty
203 large negative constants knowing that all objects are
204 in the positive half of address space. */
205 if ((ix86_cmodel == CM_SMALL
206 || (ix86_cmodel == CM_MEDIUM
207 && !SYMBOL_REF_FAR_ADDR_P (op1)))
208 && offset < 16*1024*1024
209 && trunc_int_for_mode (offset, SImode) == offset)
211 /* For CM_KERNEL we know that all object resist in the
212 negative half of 32bits address space. We may not
213 accept negative offsets, since they may be just off
214 and we may accept pretty large positive ones. */
215 if (ix86_cmodel == CM_KERNEL
217 && trunc_int_for_mode (offset, SImode) == offset)
222 /* These conditions are similar to SYMBOL_REF ones, just the
223 constraints for code models differ. */
224 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
225 && offset < 16*1024*1024
226 && trunc_int_for_mode (offset, SImode) == offset)
228 if (ix86_cmodel == CM_KERNEL
230 && trunc_int_for_mode (offset, SImode) == offset)
235 switch (XINT (op1, 1))
239 if (trunc_int_for_mode (offset, SImode) == offset)
257 ;; Return true if VALUE can be stored in the zero extended immediate field.
258 (define_predicate "x86_64_zext_immediate_operand"
259 (match_code "const_double,const_int,symbol_ref,label_ref,const")
261 switch (GET_CODE (op))
264 if (HOST_BITS_PER_WIDE_INT == 32)
265 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
270 if (HOST_BITS_PER_WIDE_INT == 32)
271 return INTVAL (op) >= 0;
273 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
276 /* For certain code models, the symbolic references are known to fit. */
277 /* TLS symbols are not constant. */
278 if (SYMBOL_REF_TLS_MODEL (op))
280 return (ix86_cmodel == CM_SMALL
281 || (ix86_cmodel == CM_MEDIUM
282 && !SYMBOL_REF_FAR_ADDR_P (op)));
285 /* For certain code models, the code is near as well. */
286 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
289 /* We also may accept the offsetted memory references in certain
291 if (GET_CODE (XEXP (op, 0)) == PLUS)
293 rtx op1 = XEXP (XEXP (op, 0), 0);
294 rtx op2 = XEXP (XEXP (op, 0), 1);
296 if (ix86_cmodel == CM_LARGE)
298 switch (GET_CODE (op1))
301 /* TLS symbols are not constant. */
302 if (SYMBOL_REF_TLS_MODEL (op1))
304 /* For small code model we may accept pretty large positive
305 offsets, since one bit is available for free. Negative
306 offsets are limited by the size of NULL pointer area
307 specified by the ABI. */
308 if ((ix86_cmodel == CM_SMALL
309 || (ix86_cmodel == CM_MEDIUM
310 && !SYMBOL_REF_FAR_ADDR_P (op1)))
312 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
313 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
315 /* ??? For the kernel, we may accept adjustment of
316 -0x10000000, since we know that it will just convert
317 negative address space to positive, but perhaps this
318 is not worthwhile. */
322 /* These conditions are similar to SYMBOL_REF ones, just the
323 constraints for code models differ. */
324 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
326 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
327 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
343 ;; Return true if size of VALUE can be stored in a sign
344 ;; extended immediate field.
345 (define_predicate "x86_64_immediate_size_operand"
346 (and (match_code "symbol_ref")
347 (ior (not (match_test "TARGET_64BIT"))
348 (match_test "ix86_cmodel == CM_SMALL")
349 (match_test "ix86_cmodel == CM_KERNEL"))))
351 ;; Return true if OP is general operand representable on x86_64.
352 (define_predicate "x86_64_general_operand"
353 (if_then_else (match_test "TARGET_64BIT")
354 (ior (match_operand 0 "nonimmediate_operand")
355 (match_operand 0 "x86_64_immediate_operand"))
356 (match_operand 0 "general_operand")))
358 ;; Return true if OP is non-VOIDmode general operand representable
359 ;; on x86_64. This predicate is used in sign-extending conversion
360 ;; operations that require non-VOIDmode immediate operands.
361 (define_predicate "x86_64_sext_operand"
362 (and (match_test "GET_MODE (op) != VOIDmode")
363 (match_operand 0 "x86_64_general_operand")))
365 ;; Return true if OP is non-VOIDmode general operand. This predicate
366 ;; is used in sign-extending conversion operations that require
367 ;; non-VOIDmode immediate operands.
368 (define_predicate "sext_operand"
369 (and (match_test "GET_MODE (op) != VOIDmode")
370 (match_operand 0 "general_operand")))
372 ;; Return true if OP is representable on x86_64 as zero-extended operand.
373 ;; This predicate is used in zero-extending conversion operations that
374 ;; require non-VOIDmode immediate operands.
375 (define_predicate "x86_64_zext_operand"
376 (if_then_else (match_test "TARGET_64BIT")
377 (ior (match_operand 0 "nonimmediate_operand")
378 (and (match_operand 0 "x86_64_zext_immediate_operand")
379 (match_test "GET_MODE (op) != VOIDmode")))
380 (match_operand 0 "nonimmediate_operand")))
382 ;; Return true if OP is general operand representable on x86_64
383 ;; as either sign extended or zero extended constant.
384 (define_predicate "x86_64_szext_general_operand"
385 (if_then_else (match_test "TARGET_64BIT")
386 (ior (match_operand 0 "nonimmediate_operand")
387 (match_operand 0 "x86_64_immediate_operand")
388 (match_operand 0 "x86_64_zext_immediate_operand"))
389 (match_operand 0 "general_operand")))
391 ;; Return true if OP is nonmemory operand representable on x86_64.
392 (define_predicate "x86_64_nonmemory_operand"
393 (if_then_else (match_test "TARGET_64BIT")
394 (ior (match_operand 0 "register_operand")
395 (match_operand 0 "x86_64_immediate_operand"))
396 (match_operand 0 "nonmemory_operand")))
398 ;; Return true if OP is nonmemory operand representable on x86_64.
399 (define_predicate "x86_64_szext_nonmemory_operand"
400 (if_then_else (match_test "TARGET_64BIT")
401 (ior (match_operand 0 "register_operand")
402 (match_operand 0 "x86_64_immediate_operand")
403 (match_operand 0 "x86_64_zext_immediate_operand"))
404 (match_operand 0 "nonmemory_operand")))
406 ;; Return true when operand is PIC expression that can be computed by lea
408 (define_predicate "pic_32bit_operand"
409 (match_code "const,symbol_ref,label_ref")
414 /* Rule out relocations that translate into 64bit constants. */
415 if (TARGET_64BIT && GET_CODE (op) == CONST)
418 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
420 if (GET_CODE (op) == UNSPEC
421 && (XINT (op, 1) == UNSPEC_GOTOFF
422 || XINT (op, 1) == UNSPEC_GOT))
426 return symbolic_operand (op, mode);
429 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
430 (define_predicate "x86_64_movabs_operand"
431 (and (match_operand 0 "nonmemory_operand")
432 (not (match_operand 0 "pic_32bit_operand"))))
434 ;; Return true if OP is either a symbol reference or a sum of a symbol
435 ;; reference and a constant.
436 (define_predicate "symbolic_operand"
437 (match_code "symbol_ref,label_ref,const")
439 switch (GET_CODE (op))
447 if (GET_CODE (op) == SYMBOL_REF
448 || GET_CODE (op) == LABEL_REF
449 || (GET_CODE (op) == UNSPEC
450 && (XINT (op, 1) == UNSPEC_GOT
451 || XINT (op, 1) == UNSPEC_GOTOFF
452 || XINT (op, 1) == UNSPEC_PCREL
453 || XINT (op, 1) == UNSPEC_GOTPCREL)))
455 if (GET_CODE (op) != PLUS
456 || !CONST_INT_P (XEXP (op, 1)))
460 if (GET_CODE (op) == SYMBOL_REF
461 || GET_CODE (op) == LABEL_REF)
463 /* Only @GOTOFF gets offsets. */
464 if (GET_CODE (op) != UNSPEC
465 || XINT (op, 1) != UNSPEC_GOTOFF)
468 op = XVECEXP (op, 0, 0);
469 if (GET_CODE (op) == SYMBOL_REF
470 || GET_CODE (op) == LABEL_REF)
479 ;; Return true if OP is a symbolic operand that resolves locally.
480 (define_predicate "local_symbolic_operand"
481 (match_code "const,label_ref,symbol_ref")
483 if (GET_CODE (op) == CONST
484 && GET_CODE (XEXP (op, 0)) == PLUS
485 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
486 op = XEXP (XEXP (op, 0), 0);
488 if (GET_CODE (op) == LABEL_REF)
491 if (GET_CODE (op) != SYMBOL_REF)
494 if (SYMBOL_REF_TLS_MODEL (op))
497 /* Dll-imported symbols are always external. */
498 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
500 if (SYMBOL_REF_LOCAL_P (op))
503 /* There is, however, a not insubstantial body of code in the rest of
504 the compiler that assumes it can just stick the results of
505 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
506 /* ??? This is a hack. Should update the body of the compiler to
507 always create a DECL an invoke targetm.encode_section_info. */
508 if (strncmp (XSTR (op, 0), internal_label_prefix,
509 internal_label_prefix_len) == 0)
515 ;; Test for a legitimate @GOTOFF operand.
517 ;; VxWorks does not impose a fixed gap between segments; the run-time
518 ;; gap can be different from the object-file gap. We therefore can't
519 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
520 ;; same segment as the GOT. Unfortunately, the flexibility of linker
521 ;; scripts means that we can't be sure of that in general, so assume
522 ;; that @GOTOFF is never valid on VxWorks.
523 (define_predicate "gotoff_operand"
524 (and (not (match_test "TARGET_VXWORKS_RTP"))
525 (match_operand 0 "local_symbolic_operand")))
527 ;; Test for various thread-local symbols.
528 (define_special_predicate "tls_symbolic_operand"
529 (and (match_code "symbol_ref")
530 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
532 (define_special_predicate "tls_modbase_operand"
533 (and (match_code "symbol_ref")
534 (match_test "op == ix86_tls_module_base ()")))
536 ;; Test for a pc-relative call operand
537 (define_predicate "constant_call_address_operand"
538 (match_code "symbol_ref")
540 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
542 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
547 ;; P6 processors will jump to the address after the decrement when %esp
548 ;; is used as a call operand, so they will execute return address as a code.
549 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
551 (define_predicate "call_register_no_elim_operand"
552 (match_operand 0 "register_operand")
554 if (GET_CODE (op) == SUBREG)
555 op = SUBREG_REG (op);
557 if (!TARGET_64BIT && op == stack_pointer_rtx)
560 return register_no_elim_operand (op, mode);
563 ;; True for any non-virtual or eliminable register. Used in places where
564 ;; instantiation of such a register may cause the pattern to not be recognized.
565 (define_predicate "register_no_elim_operand"
566 (match_operand 0 "register_operand")
568 if (GET_CODE (op) == SUBREG)
569 op = SUBREG_REG (op);
570 return !(op == arg_pointer_rtx
571 || op == frame_pointer_rtx
572 || IN_RANGE (REGNO (op),
573 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
576 ;; Similarly, but include the stack pointer. This is used to prevent esp
577 ;; from being used as an index reg.
578 (define_predicate "index_register_operand"
579 (match_operand 0 "register_operand")
581 if (GET_CODE (op) == SUBREG)
582 op = SUBREG_REG (op);
583 if (reload_in_progress || reload_completed)
584 return REG_OK_FOR_INDEX_STRICT_P (op);
586 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
589 ;; Return false if this is any eliminable register. Otherwise general_operand.
590 (define_predicate "general_no_elim_operand"
591 (if_then_else (match_code "reg,subreg")
592 (match_operand 0 "register_no_elim_operand")
593 (match_operand 0 "general_operand")))
595 ;; Return false if this is any eliminable register. Otherwise
596 ;; register_operand or a constant.
597 (define_predicate "nonmemory_no_elim_operand"
598 (ior (match_operand 0 "register_no_elim_operand")
599 (match_operand 0 "immediate_operand")))
601 ;; Test for a valid operand for indirect branch.
602 (define_predicate "indirect_branch_operand"
603 (ior (match_operand 0 "register_operand")
604 (and (not (match_test "TARGET_X32"))
605 (match_operand 0 "memory_operand"))))
607 ;; Test for a valid operand for a call instruction.
608 ;; Allow constant call address operands in Pmode only.
609 (define_special_predicate "call_insn_operand"
610 (ior (match_test "constant_call_address_operand
611 (op, mode == VOIDmode ? mode : Pmode)")
612 (match_operand 0 "call_register_no_elim_operand")
613 (and (not (match_test "TARGET_X32"))
614 (match_operand 0 "memory_operand"))))
616 ;; Similarly, but for tail calls, in which we cannot allow memory references.
617 (define_special_predicate "sibcall_insn_operand"
618 (ior (match_test "constant_call_address_operand
619 (op, mode == VOIDmode ? mode : Pmode)")
620 (match_operand 0 "register_no_elim_operand")
621 (and (not (match_test "TARGET_X32"))
622 (match_operand 0 "sibcall_memory_operand"))))
624 ;; Match exactly zero.
625 (define_predicate "const0_operand"
626 (match_code "const_int,const_double,const_vector")
628 if (mode == VOIDmode)
629 mode = GET_MODE (op);
630 return op == CONST0_RTX (mode);
634 (define_predicate "constm1_operand"
635 (match_code "const_int,const_double,const_vector")
637 if (mode == VOIDmode)
638 mode = GET_MODE (op);
639 return op == CONSTM1_RTX (mode);
642 ;; Match one or vector filled with ones.
643 (define_predicate "const1_operand"
644 (match_code "const_int,const_double,const_vector")
646 if (mode == VOIDmode)
647 mode = GET_MODE (op);
648 return op == CONST1_RTX (mode);
651 ;; Match exactly eight.
652 (define_predicate "const8_operand"
653 (and (match_code "const_int")
654 (match_test "INTVAL (op) == 8")))
656 ;; Match exactly 128.
657 (define_predicate "const128_operand"
658 (and (match_code "const_int")
659 (match_test "INTVAL (op) == 128")))
661 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
662 (define_predicate "const_32bit_mask"
663 (and (match_code "const_int")
664 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
665 == (HOST_WIDE_INT) 0xffffffff")))
667 ;; Match 2, 4, or 8. Used for leal multiplicands.
668 (define_predicate "const248_operand"
669 (match_code "const_int")
671 HOST_WIDE_INT i = INTVAL (op);
672 return i == 2 || i == 4 || i == 8;
675 ;; Match 2, 3, 6, or 7
676 (define_predicate "const2367_operand"
677 (match_code "const_int")
679 HOST_WIDE_INT i = INTVAL (op);
680 return i == 2 || i == 3 || i == 6 || i == 7;
683 ;; Match 1, 2, 4, or 8
684 (define_predicate "const1248_operand"
685 (match_code "const_int")
687 HOST_WIDE_INT i = INTVAL (op);
688 return i == 1 || i == 2 || i == 4 || i == 8;
691 ;; Match 3, 5, or 9. Used for leal multiplicands.
692 (define_predicate "const359_operand"
693 (match_code "const_int")
695 HOST_WIDE_INT i = INTVAL (op);
696 return i == 3 || i == 5 || i == 9;
699 ;; Match 4 or 8 to 11. Used for embeded rounding.
700 (define_predicate "const_4_or_8_to_11_operand"
701 (match_code "const_int")
703 HOST_WIDE_INT i = INTVAL (op);
704 return i == 4 || (i >= 8 && i <= 11);
707 ;; Match 4 or 8. Used for SAE.
708 (define_predicate "const48_operand"
709 (match_code "const_int")
711 HOST_WIDE_INT i = INTVAL (op);
712 return i == 4 || i == 8;
716 (define_predicate "const_0_to_1_operand"
717 (and (match_code "const_int")
718 (ior (match_test "op == const0_rtx")
719 (match_test "op == const1_rtx"))))
722 (define_predicate "const_0_to_3_operand"
723 (and (match_code "const_int")
724 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
727 (define_predicate "const_0_to_4_operand"
728 (and (match_code "const_int")
729 (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
732 (define_predicate "const_0_to_5_operand"
733 (and (match_code "const_int")
734 (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
737 (define_predicate "const_0_to_7_operand"
738 (and (match_code "const_int")
739 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
742 (define_predicate "const_0_to_15_operand"
743 (and (match_code "const_int")
744 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
747 (define_predicate "const_0_to_31_operand"
748 (and (match_code "const_int")
749 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
752 (define_predicate "const_0_to_63_operand"
753 (and (match_code "const_int")
754 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
757 (define_predicate "const_0_to_255_operand"
758 (and (match_code "const_int")
759 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
761 ;; Match (0 to 255) * 8
762 (define_predicate "const_0_to_255_mul_8_operand"
763 (match_code "const_int")
765 unsigned HOST_WIDE_INT val = INTVAL (op);
766 return val <= 255*8 && val % 8 == 0;
769 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
770 ;; for shift & compare patterns, as shifting by 0 does not change flags).
771 (define_predicate "const_1_to_31_operand"
772 (and (match_code "const_int")
773 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
775 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
776 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
777 (define_predicate "const_1_to_63_operand"
778 (and (match_code "const_int")
779 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
782 (define_predicate "const_2_to_3_operand"
783 (and (match_code "const_int")
784 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
787 (define_predicate "const_4_to_5_operand"
788 (and (match_code "const_int")
789 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
792 (define_predicate "const_4_to_7_operand"
793 (and (match_code "const_int")
794 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
797 (define_predicate "const_6_to_7_operand"
798 (and (match_code "const_int")
799 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
802 (define_predicate "const_8_to_9_operand"
803 (and (match_code "const_int")
804 (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
807 (define_predicate "const_8_to_11_operand"
808 (and (match_code "const_int")
809 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
812 (define_predicate "const_8_to_15_operand"
813 (and (match_code "const_int")
814 (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
817 (define_predicate "const_10_to_11_operand"
818 (and (match_code "const_int")
819 (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
822 (define_predicate "const_12_to_13_operand"
823 (and (match_code "const_int")
824 (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
827 (define_predicate "const_12_to_15_operand"
828 (and (match_code "const_int")
829 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
832 (define_predicate "const_14_to_15_operand"
833 (and (match_code "const_int")
834 (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
837 (define_predicate "const_16_to_19_operand"
838 (and (match_code "const_int")
839 (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
842 (define_predicate "const_16_to_31_operand"
843 (and (match_code "const_int")
844 (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
847 (define_predicate "const_20_to_23_operand"
848 (and (match_code "const_int")
849 (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
852 (define_predicate "const_24_to_27_operand"
853 (and (match_code "const_int")
854 (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
857 (define_predicate "const_28_to_31_operand"
858 (and (match_code "const_int")
859 (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
861 ;; True if this is a constant appropriate for an increment or decrement.
862 (define_predicate "incdec_operand"
863 (match_code "const_int")
865 /* On Pentium4, the inc and dec operations causes extra dependency on flag
866 registers, since carry flag is not set. */
867 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
869 return op == const1_rtx || op == constm1_rtx;
872 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
873 (define_predicate "reg_or_pm1_operand"
874 (ior (match_operand 0 "register_operand")
875 (and (match_code "const_int")
876 (ior (match_test "op == const1_rtx")
877 (match_test "op == constm1_rtx")))))
879 ;; True if OP is acceptable as operand of DImode shift expander.
880 (define_predicate "shiftdi_operand"
881 (if_then_else (match_test "TARGET_64BIT")
882 (match_operand 0 "nonimmediate_operand")
883 (match_operand 0 "register_operand")))
885 (define_predicate "ashldi_input_operand"
886 (if_then_else (match_test "TARGET_64BIT")
887 (match_operand 0 "nonimmediate_operand")
888 (match_operand 0 "reg_or_pm1_operand")))
890 ;; Return true if OP is a vector load from the constant pool with just
891 ;; the first element nonzero.
892 (define_predicate "zero_extended_scalar_load_operand"
896 op = maybe_get_pool_constant (op);
898 if (!(op && GET_CODE (op) == CONST_VECTOR))
901 n_elts = CONST_VECTOR_NUNITS (op);
903 for (n_elts--; n_elts > 0; n_elts--)
905 rtx elt = CONST_VECTOR_ELT (op, n_elts);
906 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
912 /* Return true if operand is a vector constant that is all ones. */
913 (define_predicate "vector_all_ones_operand"
914 (match_code "const_vector")
916 int nunits = GET_MODE_NUNITS (mode);
918 if (GET_CODE (op) == CONST_VECTOR
919 && CONST_VECTOR_NUNITS (op) == nunits)
922 for (i = 0; i < nunits; ++i)
924 rtx x = CONST_VECTOR_ELT (op, i);
925 if (x != constm1_rtx)
934 ; Return true when OP is operand acceptable for standard SSE move.
935 (define_predicate "vector_move_operand"
936 (ior (match_operand 0 "nonimmediate_operand")
937 (match_operand 0 "const0_operand")))
939 ;; Return true when OP is either nonimmediate operand, or any
941 (define_predicate "nonimmediate_or_const_vector_operand"
942 (ior (match_operand 0 "nonimmediate_operand")
943 (match_code "const_vector")))
945 ;; Return true when OP is nonimmediate or standard SSE constant.
946 (define_predicate "nonimmediate_or_sse_const_operand"
947 (match_operand 0 "general_operand")
949 if (nonimmediate_operand (op, mode))
951 if (standard_sse_constant_p (op) > 0)
956 ;; Return true if OP is a register or a zero.
957 (define_predicate "reg_or_0_operand"
958 (ior (match_operand 0 "register_operand")
959 (match_operand 0 "const0_operand")))
961 ;; Return true for RTX codes that force SImode address.
962 (define_predicate "SImode_address_operand"
963 (match_code "subreg,zero_extend,and"))
965 ;; Return true if op if a valid address for LEA, and does not contain
966 ;; a segment override. Defined as a special predicate to allow
967 ;; mode-less const_int operands pass to address_operand.
968 (define_special_predicate "address_no_seg_operand"
969 (match_test "address_operand (op, VOIDmode)")
971 struct ix86_address parts;
974 if (!CONST_INT_P (op)
976 && GET_MODE (op) != mode)
979 ok = ix86_decompose_address (op, &parts);
981 return parts.seg == SEG_DEFAULT;
984 ;; Return true if op if a valid base register, displacement or
985 ;; sum of base register and displacement for VSIB addressing.
986 (define_predicate "vsib_address_operand"
987 (match_test "address_operand (op, VOIDmode)")
989 struct ix86_address parts;
993 ok = ix86_decompose_address (op, &parts);
995 if (parts.index || parts.seg != SEG_DEFAULT)
998 /* VSIB addressing doesn't support (%rip). */
1002 if (GET_CODE (disp) == CONST)
1004 disp = XEXP (disp, 0);
1005 if (GET_CODE (disp) == PLUS)
1006 disp = XEXP (disp, 0);
1007 if (GET_CODE (disp) == UNSPEC)
1008 switch (XINT (disp, 1))
1010 case UNSPEC_GOTPCREL:
1012 case UNSPEC_GOTNTPOFF:
1018 && (GET_CODE (disp) == SYMBOL_REF
1019 || GET_CODE (disp) == LABEL_REF))
1026 ;; Return true if op is valid MPX address operand without base
1027 (define_predicate "address_mpx_no_base_operand"
1028 (match_test "address_operand (op, VOIDmode)")
1030 struct ix86_address parts;
1033 ok = ix86_decompose_address (op, &parts);
1036 if (parts.index && parts.base)
1039 if (parts.seg != SEG_DEFAULT)
1042 /* Do not support (%rip). */
1043 if (parts.disp && flag_pic && TARGET_64BIT
1044 && SYMBOLIC_CONST (parts.disp))
1046 if (GET_CODE (parts.disp) != CONST
1047 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1048 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1049 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1050 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1051 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF))
1058 ;; Return true if op is valid MPX address operand without index
1059 (define_predicate "address_mpx_no_index_operand"
1060 (match_test "address_operand (op, VOIDmode)")
1062 struct ix86_address parts;
1065 ok = ix86_decompose_address (op, &parts);
1071 if (parts.seg != SEG_DEFAULT)
1074 /* Do not support (%rip). */
1075 if (parts.disp && flag_pic && TARGET_64BIT
1076 && SYMBOLIC_CONST (parts.disp)
1077 && (GET_CODE (parts.disp) != CONST
1078 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1079 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1080 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1081 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1082 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF)))
1088 (define_predicate "vsib_mem_operator"
1091 (define_predicate "bnd_mem_operator"
1094 ;; Return true if the rtx is known to be at least 32 bits aligned.
1095 (define_predicate "aligned_operand"
1096 (match_operand 0 "general_operand")
1098 struct ix86_address parts;
1101 /* Registers and immediate operands are always "aligned". */
1105 /* All patterns using aligned_operand on memory operands ends up
1106 in promoting memory operand to 64bit and thus causing memory mismatch. */
1107 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1110 /* Don't even try to do any aligned optimizations with volatiles. */
1111 if (MEM_VOLATILE_P (op))
1114 if (MEM_ALIGN (op) >= 32)
1119 /* Pushes and pops are only valid on the stack pointer. */
1120 if (GET_CODE (op) == PRE_DEC
1121 || GET_CODE (op) == POST_INC)
1124 /* Decode the address. */
1125 ok = ix86_decompose_address (op, &parts);
1128 if (parts.base && GET_CODE (parts.base) == SUBREG)
1129 parts.base = SUBREG_REG (parts.base);
1130 if (parts.index && GET_CODE (parts.index) == SUBREG)
1131 parts.index = SUBREG_REG (parts.index);
1133 /* Look for some component that isn't known to be aligned. */
1136 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1141 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1146 if (!CONST_INT_P (parts.disp)
1147 || (INTVAL (parts.disp) & 3))
1151 /* Didn't find one -- this must be an aligned address. */
1155 ;; Return true if OP is memory operand with a displacement.
1156 (define_predicate "memory_displacement_operand"
1157 (match_operand 0 "memory_operand")
1159 struct ix86_address parts;
1162 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1164 return parts.disp != NULL_RTX;
1167 ;; Return true if OP is memory operand with a displacement only.
1168 (define_predicate "memory_displacement_only_operand"
1169 (match_operand 0 "memory_operand")
1171 struct ix86_address parts;
1177 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1180 if (parts.base || parts.index)
1183 return parts.disp != NULL_RTX;
1186 ;; Return true if OP is memory operand that cannot be represented
1187 ;; by the modRM array.
1188 (define_predicate "long_memory_operand"
1189 (and (match_operand 0 "memory_operand")
1190 (match_test "memory_address_length (op, false)")))
1192 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1193 (define_predicate "fcmov_comparison_operator"
1194 (match_operand 0 "comparison_operator")
1196 machine_mode inmode = GET_MODE (XEXP (op, 0));
1197 enum rtx_code code = GET_CODE (op);
1199 if (inmode == CCFPmode || inmode == CCFPUmode)
1201 if (!ix86_trivial_fp_comparison_operator (op, mode))
1203 code = ix86_fp_compare_code_to_integer (code);
1205 /* i387 supports just limited amount of conditional codes. */
1208 case LTU: case GTU: case LEU: case GEU:
1209 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1210 || inmode == CCCmode)
1213 case ORDERED: case UNORDERED:
1221 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1222 ;; The first set are supported directly; the second set can't be done with
1223 ;; full IEEE support, i.e. NaNs.
1225 (define_predicate "sse_comparison_operator"
1226 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1227 (and (match_test "TARGET_AVX")
1228 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1230 (define_predicate "ix86_comparison_int_operator"
1231 (match_code "ne,eq,ge,gt,le,lt"))
1233 (define_predicate "ix86_comparison_uns_operator"
1234 (match_code "ne,eq,geu,gtu,leu,ltu"))
1236 (define_predicate "bt_comparison_operator"
1237 (match_code "ne,eq"))
1239 ;; Return true if OP is a valid comparison operator in valid mode.
1240 (define_predicate "ix86_comparison_operator"
1241 (match_operand 0 "comparison_operator")
1243 machine_mode inmode = GET_MODE (XEXP (op, 0));
1244 enum rtx_code code = GET_CODE (op);
1246 if (inmode == CCFPmode || inmode == CCFPUmode)
1247 return ix86_trivial_fp_comparison_operator (op, mode);
1254 if (inmode == CCmode || inmode == CCGCmode
1255 || inmode == CCGOCmode || inmode == CCNOmode)
1258 case LTU: case GTU: case LEU: case GEU:
1259 if (inmode == CCmode || inmode == CCCmode)
1262 case ORDERED: case UNORDERED:
1263 if (inmode == CCmode)
1267 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1275 ;; Return true if OP is a valid comparison operator
1276 ;; testing carry flag to be set.
1277 (define_predicate "ix86_carry_flag_operator"
1278 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1280 machine_mode inmode = GET_MODE (XEXP (op, 0));
1281 enum rtx_code code = GET_CODE (op);
1283 if (inmode == CCFPmode || inmode == CCFPUmode)
1285 if (!ix86_trivial_fp_comparison_operator (op, mode))
1287 code = ix86_fp_compare_code_to_integer (code);
1289 else if (inmode == CCCmode)
1290 return code == LTU || code == GTU;
1291 else if (inmode != CCmode)
1297 ;; Return true if this comparison only requires testing one flag bit.
1298 (define_predicate "ix86_trivial_fp_comparison_operator"
1299 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1301 ;; Return true if we know how to do this comparison. Others require
1302 ;; testing more than one flag bit, and we let the generic middle-end
1304 (define_predicate "ix86_fp_comparison_operator"
1305 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1306 == IX86_FPCMP_ARITH")
1307 (match_operand 0 "comparison_operator")
1308 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1310 ;; Same as above, but for swapped comparison used in *jcc<fp>_<int>_i387.
1311 (define_predicate "ix86_swapped_fp_comparison_operator"
1312 (match_operand 0 "comparison_operator")
1314 enum rtx_code code = GET_CODE (op);
1317 PUT_CODE (op, swap_condition (code));
1318 ret = ix86_fp_comparison_operator (op, mode);
1319 PUT_CODE (op, code);
1323 ;; Nearly general operand, but accept any const_double, since we wish
1324 ;; to be able to drop them into memory rather than have them get pulled
1326 (define_predicate "cmp_fp_expander_operand"
1327 (ior (match_code "const_double")
1328 (match_operand 0 "general_operand")))
1330 ;; Return true if this is a valid binary floating-point operation.
1331 (define_predicate "binary_fp_operator"
1332 (match_code "plus,minus,mult,div"))
1334 ;; Return true if this is a multiply operation.
1335 (define_predicate "mult_operator"
1336 (match_code "mult"))
1338 ;; Return true if this is a division operation.
1339 (define_predicate "div_operator"
1342 ;; Return true if this is a plus, minus, and, ior or xor operation.
1343 (define_predicate "plusminuslogic_operator"
1344 (match_code "plus,minus,and,ior,xor"))
1346 ;; Return true if this is a float extend operation.
1347 (define_predicate "float_operator"
1348 (match_code "float"))
1350 ;; Return true for ARITHMETIC_P.
1351 (define_predicate "arith_or_logical_operator"
1352 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1353 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1355 ;; Return true for COMMUTATIVE_P.
1356 (define_predicate "commutative_operator"
1357 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1359 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1360 (define_predicate "promotable_binary_operator"
1361 (ior (match_code "plus,minus,and,ior,xor,ashift")
1362 (and (match_code "mult")
1363 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1365 (define_predicate "compare_operator"
1366 (match_code "compare"))
1368 (define_predicate "absneg_operator"
1369 (match_code "abs,neg"))
1371 ;; Return true if OP is misaligned memory operand
1372 (define_predicate "misaligned_operand"
1373 (and (match_code "mem")
1374 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1376 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1377 (define_predicate "emms_operation"
1378 (match_code "parallel")
1382 if (XVECLEN (op, 0) != 17)
1385 for (i = 0; i < 8; i++)
1387 rtx elt = XVECEXP (op, 0, i+1);
1389 if (GET_CODE (elt) != CLOBBER
1390 || GET_CODE (SET_DEST (elt)) != REG
1391 || GET_MODE (SET_DEST (elt)) != XFmode
1392 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1395 elt = XVECEXP (op, 0, i+9);
1397 if (GET_CODE (elt) != CLOBBER
1398 || GET_CODE (SET_DEST (elt)) != REG
1399 || GET_MODE (SET_DEST (elt)) != DImode
1400 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1406 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1407 (define_predicate "vzeroall_operation"
1408 (match_code "parallel")
1410 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1412 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1415 for (i = 0; i < nregs; i++)
1417 rtx elt = XVECEXP (op, 0, i+1);
1419 if (GET_CODE (elt) != SET
1420 || GET_CODE (SET_DEST (elt)) != REG
1421 || GET_MODE (SET_DEST (elt)) != V8SImode
1422 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1423 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1429 ;; return true if OP is a vzeroupper operation.
1430 (define_predicate "vzeroupper_operation"
1431 (and (match_code "unspec_volatile")
1432 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1434 ;; Return true if OP is a parallel for a vbroadcast permute.
1436 (define_predicate "avx_vbroadcast_operand"
1437 (and (match_code "parallel")
1438 (match_code "const_int" "a"))
1440 rtx elt = XVECEXP (op, 0, 0);
1441 int i, nelt = XVECLEN (op, 0);
1443 /* Don't bother checking there are the right number of operands,
1444 merely that they're all identical. */
1445 for (i = 1; i < nelt; ++i)
1446 if (XVECEXP (op, 0, i) != elt)
1451 ;; Return true if OP is a parallel for a palignr permute.
1452 (define_predicate "palignr_operand"
1453 (and (match_code "parallel")
1454 (match_code "const_int" "a"))
1456 int elt = INTVAL (XVECEXP (op, 0, 0));
1457 int i, nelt = XVECLEN (op, 0);
1459 /* Check that an order in the permutation is suitable for palignr.
1460 For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
1461 for (i = 1; i < nelt; ++i)
1462 if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
1467 ;; Return true if OP is a proper third operand to vpblendw256.
1468 (define_predicate "avx2_pblendw_operand"
1469 (match_code "const_int")
1471 HOST_WIDE_INT val = INTVAL (op);
1472 HOST_WIDE_INT low = val & 0xff;
1473 return val == ((low << 8) | low);
1476 ;; Return true if OP is nonimmediate_operand or CONST_VECTOR.
1477 (define_predicate "general_vector_operand"
1478 (ior (match_operand 0 "nonimmediate_operand")
1479 (match_code "const_vector")))
1481 ;; Return true if OP is either -1 constant or stored in register.
1482 (define_predicate "register_or_constm1_operand"
1483 (ior (match_operand 0 "register_operand")
1484 (and (match_code "const_int")
1485 (match_test "op == constm1_rtx"))))