gcc/testsuite/gcc.target/aarch64/sve/ext_1.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O -msve-vector-bits=256" } */
   3
   4 #include <stdint.h>
   5
   6 typedef int64_t vnx2di __attribute__((vector_size (32)));
   7 typedef int32_t vnx4si __attribute__((vector_size (32)));
   8 typedef int16_t vnx8hi __attribute__((vector_size (32)));
   9 typedef int8_t vnx16qi __attribute__((vector_size (32)));
  10 typedef double vnx2df __attribute__((vector_size (32)));
  11 typedef float vnx4sf __attribute__((vector_size (32)));
  12 typedef _Float16 vnx8hf __attribute__((vector_size (32)));
  13
  14 #define MASK_2(X) X, X + 1
  15 #define MASK_4(X) MASK_2 (X), MASK_2 (X + 2)
  16 #define MASK_8(X) MASK_4 (X), MASK_4 (X + 4)
  17 #define MASK_16(X) MASK_8 (X), MASK_8 (X + 8)
  18 #define MASK_32(X) MASK_16 (X), MASK_16 (X + 16)
  19
  20 #define INDEX_4 vnx2di
  21 #define INDEX_8 vnx4si
  22 #define INDEX_16 vnx8hi
  23 #define INDEX_32 vnx16qi
  24
  25 #define DUP_LANE(TYPE, NUNITS, INDEX)                                        \
  26   TYPE dup_##INDEX##_##TYPE (TYPE values1, TYPE values2)                     \
  27   {                                                                          \
  28     return __builtin_shuffle (values1, values2,                              \
  29                               ((INDEX_##NUNITS) { MASK_##NUNITS (INDEX) })); \
  30   }
  31
  32 #define TEST_ALL(T)                             \
  33   T (vnx2di, 4, 1)                              \
  34   T (vnx2di, 4, 2)                              \
  35   T (vnx2di, 4, 3)                              \
  36   T (vnx4si, 8, 1)                              \
  37   T (vnx4si, 8, 5)                              \
  38   T (vnx4si, 8, 7)                              \
  39   T (vnx8hi, 16, 1)                             \
  40   T (vnx8hi, 16, 6)                             \
  41   T (vnx8hi, 16, 15)                            \
  42   T (vnx16qi, 32, 1)                            \
  43   T (vnx16qi, 32, 19)                           \
  44   T (vnx16qi, 32, 31)                           \
  45   T (vnx2df, 4, 1)                              \
  46   T (vnx2df, 4, 2)                              \
  47   T (vnx2df, 4, 3)                              \
  48   T (vnx4sf, 8, 1)                              \
  49   T (vnx4sf, 8, 5)                              \
  50   T (vnx4sf, 8, 7)                              \
  51   T (vnx8hf, 16, 1)                             \
  52   T (vnx8hf, 16, 6)                             \
  53   T (vnx8hf, 16, 15)                            \
  54
  55 TEST_ALL (DUP_LANE)
  56
  57 /* { dg-final { scan-assembler-not {\ttbl\t} } } */
  58
  59 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #1\n} 1 } } */
  60 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #2\n} 2 } } */
  61 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #4\n} 2 } } */
  62 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #8\n} 2 } } */
  63 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #12\n} 2 } } */
  64 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #16\n} 2 } } */
  65 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #19\n} 1 } } */
  66 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #20\n} 2 } } */
  67 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #24\n} 2 } } */
  68 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #28\n} 2 } } */
  69 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #30\n} 2 } } */
  70 /* { dg-final { scan-assembler-times {\text\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b, #31\n} 1 } } */