Create embedded-5_0-branch branch for development on ARM embedded cores.
[official-gcc.git] / embedded-5_0-branch / gcc / testsuite / gcc.target / arm / neon / vld3Qu32.c
blob21f20f880eb9e6a355eb75b7ca1c794dfe1082d1
1 /* Test the `vld3Qu32' ARM Neon intrinsic. */
2 /* This file was autogenerated by neon-testgen. */
4 /* { dg-do assemble } */
5 /* { dg-require-effective-target arm_neon_ok } */
6 /* { dg-options "-save-temps -O0" } */
7 /* { dg-add-options arm_neon } */
9 #include "arm_neon.h"
11 void test_vld3Qu32 (void)
13 uint32x4x3_t out_uint32x4x3_t;
15 out_uint32x4x3_t = vld3q_u32 (0);
18 /* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
19 /* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
20 /* { dg-final { cleanup-saved-temps } } */