1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
59 #include "hash-table.h"
61 #include "basic-block.h"
62 #include "tree-ssa-alias.h"
63 #include "internal-fn.h"
64 #include "gimple-fold.h"
66 #include "gimple-expr.h"
70 #include "gimple-iterator.h"
71 #include "gimple-walk.h"
74 #include "tm-constrs.h"
77 #include "tree-vectorizer.h"
80 #include "target-globals.h"
83 #include "tree-pass.h"
86 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
89 #include "gstab.h" /* for N_SLINE */
92 #ifndef TARGET_NO_PROTOTYPE
93 #define TARGET_NO_PROTOTYPE 0
96 #define min(A,B) ((A) < (B) ? (A) : (B))
97 #define max(A,B) ((A) > (B) ? (A) : (B))
99 /* Structure used to define the rs6000 stack */
100 typedef struct rs6000_stack
{
101 int reload_completed
; /* stack info won't change from here on */
102 int first_gp_reg_save
; /* first callee saved GP register used */
103 int first_fp_reg_save
; /* first callee saved FP register used */
104 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
105 int lr_save_p
; /* true if the link reg needs to be saved */
106 int cr_save_p
; /* true if the CR reg needs to be saved */
107 unsigned int vrsave_mask
; /* mask of vec registers to save */
108 int push_p
; /* true if we need to allocate stack space */
109 int calls_p
; /* true if the function makes any calls */
110 int world_save_p
; /* true if we're saving *everything*:
111 r13-r31, cr, f14-f31, vrsave, v20-v31 */
112 enum rs6000_abi abi
; /* which ABI to use */
113 int gp_save_offset
; /* offset to save GP regs from initial SP */
114 int fp_save_offset
; /* offset to save FP regs from initial SP */
115 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
116 int lr_save_offset
; /* offset to save LR from initial SP */
117 int cr_save_offset
; /* offset to save CR from initial SP */
118 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
119 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
120 int varargs_save_offset
; /* offset to save the varargs registers */
121 int ehrd_offset
; /* offset to EH return data */
122 int ehcr_offset
; /* offset to EH CR field data */
123 int reg_size
; /* register size (4 or 8) */
124 HOST_WIDE_INT vars_size
; /* variable save area size */
125 int parm_size
; /* outgoing parameter size */
126 int save_size
; /* save area size */
127 int fixed_size
; /* fixed size of stack frame */
128 int gp_size
; /* size of saved GP registers */
129 int fp_size
; /* size of saved FP registers */
130 int altivec_size
; /* size of saved AltiVec registers */
131 int cr_size
; /* size to hold CR if not in save_size */
132 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
133 int altivec_padding_size
; /* size of altivec alignment padding if
135 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
136 int spe_padding_size
;
137 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
138 int spe_64bit_regs_used
;
142 /* A C structure for machine-specific, per-function data.
143 This is added to the cfun structure. */
144 typedef struct GTY(()) machine_function
146 /* Whether the instruction chain has been scanned already. */
147 int insn_chain_scanned_p
;
148 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
149 int ra_needs_full_frame
;
150 /* Flags if __builtin_return_address (0) was used. */
152 /* Cache lr_save_p after expansion of builtin_eh_return. */
154 /* Whether we need to save the TOC to the reserved stack location in the
155 function prologue. */
156 bool save_toc_in_prologue
;
157 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
158 varargs save area. */
159 HOST_WIDE_INT varargs_save_offset
;
160 /* Temporary stack slot to use for SDmode copies. This slot is
161 64-bits wide and is allocated early enough so that the offset
162 does not overflow the 16-bit load/store offset field. */
163 rtx sdmode_stack_slot
;
164 /* Flag if r2 setup is needed with ELFv2 ABI. */
165 bool r2_setup_needed
;
168 /* Support targetm.vectorize.builtin_mask_for_load. */
169 static GTY(()) tree altivec_builtin_mask_for_load
;
171 /* Set to nonzero once AIX common-mode calls have been defined. */
172 static GTY(()) int common_mode_defined
;
174 /* Label number of label created for -mrelocatable, to call to so we can
175 get the address of the GOT section */
176 static int rs6000_pic_labelno
;
179 /* Counter for labels which are to be placed in .fixup. */
180 int fixuplabelno
= 0;
183 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
186 /* Specify the machine mode that pointers have. After generation of rtl, the
187 compiler makes no further distinction between pointers and any other objects
188 of this machine mode. The type is unsigned since not all things that
189 include rs6000.h also include machmode.h. */
190 unsigned rs6000_pmode
;
192 /* Width in bits of a pointer. */
193 unsigned rs6000_pointer_size
;
195 #ifdef HAVE_AS_GNU_ATTRIBUTE
196 /* Flag whether floating point values have been passed/returned. */
197 static bool rs6000_passes_float
;
198 /* Flag whether vector values have been passed/returned. */
199 static bool rs6000_passes_vector
;
200 /* Flag whether small (<= 8 byte) structures have been returned. */
201 static bool rs6000_returns_struct
;
204 /* Value is TRUE if register/mode pair is acceptable. */
205 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
207 /* Maximum number of registers needed for a given register class and mode. */
208 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
210 /* How many registers are needed for a given register and mode. */
211 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
213 /* Map register number to register class. */
214 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
216 static int dbg_cost_ctrl
;
218 /* Built in types. */
219 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
220 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
222 /* Flag to say the TOC is initialized */
224 char toc_label_name
[10];
226 /* Cached value of rs6000_variable_issue. This is cached in
227 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
228 static short cached_can_issue_more
;
230 static GTY(()) section
*read_only_data_section
;
231 static GTY(()) section
*private_data_section
;
232 static GTY(()) section
*tls_data_section
;
233 static GTY(()) section
*tls_private_data_section
;
234 static GTY(()) section
*read_only_private_data_section
;
235 static GTY(()) section
*sdata2_section
;
236 static GTY(()) section
*toc_section
;
238 struct builtin_description
240 const HOST_WIDE_INT mask
;
241 const enum insn_code icode
;
242 const char *const name
;
243 const enum rs6000_builtins code
;
246 /* Describe the vector unit used for modes. */
247 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
248 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
250 /* Register classes for various constraints that are based on the target
252 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
254 /* Describe the alignment of a vector. */
255 int rs6000_vector_align
[NUM_MACHINE_MODES
];
257 /* Map selected modes to types for builtins. */
258 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
260 /* What modes to automatically generate reciprocal divide estimate (fre) and
261 reciprocal sqrt (frsqrte) for. */
262 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
264 /* Masks to determine which reciprocal esitmate instructions to generate
266 enum rs6000_recip_mask
{
267 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
268 RECIP_DF_DIV
= 0x002,
269 RECIP_V4SF_DIV
= 0x004,
270 RECIP_V2DF_DIV
= 0x008,
272 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
273 RECIP_DF_RSQRT
= 0x020,
274 RECIP_V4SF_RSQRT
= 0x040,
275 RECIP_V2DF_RSQRT
= 0x080,
277 /* Various combination of flags for -mrecip=xxx. */
279 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
280 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
281 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
283 RECIP_HIGH_PRECISION
= RECIP_ALL
,
285 /* On low precision machines like the power5, don't enable double precision
286 reciprocal square root estimate, since it isn't accurate enough. */
287 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
290 /* -mrecip options. */
293 const char *string
; /* option name */
294 unsigned int mask
; /* mask bits to set */
295 } recip_options
[] = {
296 { "all", RECIP_ALL
},
297 { "none", RECIP_NONE
},
298 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
300 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
301 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
302 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
303 | RECIP_V2DF_RSQRT
) },
304 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
305 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
308 /* Pointer to function (in rs6000-c.c) that can define or undefine target
309 macros that have changed. Languages that don't support the preprocessor
310 don't link in rs6000-c.c, so we can't call it directly. */
311 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
313 /* Simplfy register classes into simpler classifications. We assume
314 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
315 check for standard register classes (gpr/floating/altivec/vsx) and
316 floating/vector classes (float/altivec/vsx). */
318 enum rs6000_reg_type
{
331 /* Map register class to register type. */
332 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
334 /* First/last register type for the 'normal' register types (i.e. general
335 purpose, floating point, altivec, and VSX registers). */
336 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
338 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
341 /* Register classes we care about in secondary reload or go if legitimate
342 address. We only need to worry about GPR, FPR, and Altivec registers here,
343 along an ANY field that is the OR of the 3 register classes. */
345 enum rs6000_reload_reg_type
{
346 RELOAD_REG_GPR
, /* General purpose registers. */
347 RELOAD_REG_FPR
, /* Traditional floating point regs. */
348 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
349 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
353 /* For setting up register classes, loop through the 3 register classes mapping
354 into real registers, and skip the ANY class, which is just an OR of the
356 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
357 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
359 /* Map reload register type to a register in the register class. */
360 struct reload_reg_map_type
{
361 const char *name
; /* Register class name. */
362 int reg
; /* Register in the register class. */
365 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
366 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
367 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
368 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
369 { "Any", -1 }, /* RELOAD_REG_ANY. */
372 /* Mask bits for each register class, indexed per mode. Historically the
373 compiler has been more restrictive which types can do PRE_MODIFY instead of
374 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
375 typedef unsigned char addr_mask_type
;
377 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
378 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
379 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
380 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
381 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
382 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
384 /* Register type masks based on the type, of valid addressing modes. */
385 struct rs6000_reg_addr
{
386 enum insn_code reload_load
; /* INSN to reload for loading. */
387 enum insn_code reload_store
; /* INSN to reload for storing. */
388 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
389 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
390 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
391 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
392 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
395 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
397 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
399 mode_supports_pre_incdec_p (enum machine_mode mode
)
401 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
405 /* Helper function to say whether a mode supports PRE_MODIFY. */
407 mode_supports_pre_modify_p (enum machine_mode mode
)
409 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
414 /* Target cpu costs. */
416 struct processor_costs
{
417 const int mulsi
; /* cost of SImode multiplication. */
418 const int mulsi_const
; /* cost of SImode multiplication by constant. */
419 const int mulsi_const9
; /* cost of SImode mult by short constant. */
420 const int muldi
; /* cost of DImode multiplication. */
421 const int divsi
; /* cost of SImode division. */
422 const int divdi
; /* cost of DImode division. */
423 const int fp
; /* cost of simple SFmode and DFmode insns. */
424 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
425 const int sdiv
; /* cost of SFmode division (fdivs). */
426 const int ddiv
; /* cost of DFmode division (fdiv). */
427 const int cache_line_size
; /* cache line size in bytes. */
428 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
429 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
430 const int simultaneous_prefetches
; /* number of parallel prefetch
434 const struct processor_costs
*rs6000_cost
;
436 /* Processor costs (relative to an add) */
438 /* Instruction size costs on 32bit processors. */
440 struct processor_costs size32_cost
= {
441 COSTS_N_INSNS (1), /* mulsi */
442 COSTS_N_INSNS (1), /* mulsi_const */
443 COSTS_N_INSNS (1), /* mulsi_const9 */
444 COSTS_N_INSNS (1), /* muldi */
445 COSTS_N_INSNS (1), /* divsi */
446 COSTS_N_INSNS (1), /* divdi */
447 COSTS_N_INSNS (1), /* fp */
448 COSTS_N_INSNS (1), /* dmul */
449 COSTS_N_INSNS (1), /* sdiv */
450 COSTS_N_INSNS (1), /* ddiv */
457 /* Instruction size costs on 64bit processors. */
459 struct processor_costs size64_cost
= {
460 COSTS_N_INSNS (1), /* mulsi */
461 COSTS_N_INSNS (1), /* mulsi_const */
462 COSTS_N_INSNS (1), /* mulsi_const9 */
463 COSTS_N_INSNS (1), /* muldi */
464 COSTS_N_INSNS (1), /* divsi */
465 COSTS_N_INSNS (1), /* divdi */
466 COSTS_N_INSNS (1), /* fp */
467 COSTS_N_INSNS (1), /* dmul */
468 COSTS_N_INSNS (1), /* sdiv */
469 COSTS_N_INSNS (1), /* ddiv */
476 /* Instruction costs on RS64A processors. */
478 struct processor_costs rs64a_cost
= {
479 COSTS_N_INSNS (20), /* mulsi */
480 COSTS_N_INSNS (12), /* mulsi_const */
481 COSTS_N_INSNS (8), /* mulsi_const9 */
482 COSTS_N_INSNS (34), /* muldi */
483 COSTS_N_INSNS (65), /* divsi */
484 COSTS_N_INSNS (67), /* divdi */
485 COSTS_N_INSNS (4), /* fp */
486 COSTS_N_INSNS (4), /* dmul */
487 COSTS_N_INSNS (31), /* sdiv */
488 COSTS_N_INSNS (31), /* ddiv */
489 128, /* cache line size */
495 /* Instruction costs on MPCCORE processors. */
497 struct processor_costs mpccore_cost
= {
498 COSTS_N_INSNS (2), /* mulsi */
499 COSTS_N_INSNS (2), /* mulsi_const */
500 COSTS_N_INSNS (2), /* mulsi_const9 */
501 COSTS_N_INSNS (2), /* muldi */
502 COSTS_N_INSNS (6), /* divsi */
503 COSTS_N_INSNS (6), /* divdi */
504 COSTS_N_INSNS (4), /* fp */
505 COSTS_N_INSNS (5), /* dmul */
506 COSTS_N_INSNS (10), /* sdiv */
507 COSTS_N_INSNS (17), /* ddiv */
508 32, /* cache line size */
514 /* Instruction costs on PPC403 processors. */
516 struct processor_costs ppc403_cost
= {
517 COSTS_N_INSNS (4), /* mulsi */
518 COSTS_N_INSNS (4), /* mulsi_const */
519 COSTS_N_INSNS (4), /* mulsi_const9 */
520 COSTS_N_INSNS (4), /* muldi */
521 COSTS_N_INSNS (33), /* divsi */
522 COSTS_N_INSNS (33), /* divdi */
523 COSTS_N_INSNS (11), /* fp */
524 COSTS_N_INSNS (11), /* dmul */
525 COSTS_N_INSNS (11), /* sdiv */
526 COSTS_N_INSNS (11), /* ddiv */
527 32, /* cache line size */
533 /* Instruction costs on PPC405 processors. */
535 struct processor_costs ppc405_cost
= {
536 COSTS_N_INSNS (5), /* mulsi */
537 COSTS_N_INSNS (4), /* mulsi_const */
538 COSTS_N_INSNS (3), /* mulsi_const9 */
539 COSTS_N_INSNS (5), /* muldi */
540 COSTS_N_INSNS (35), /* divsi */
541 COSTS_N_INSNS (35), /* divdi */
542 COSTS_N_INSNS (11), /* fp */
543 COSTS_N_INSNS (11), /* dmul */
544 COSTS_N_INSNS (11), /* sdiv */
545 COSTS_N_INSNS (11), /* ddiv */
546 32, /* cache line size */
552 /* Instruction costs on PPC440 processors. */
554 struct processor_costs ppc440_cost
= {
555 COSTS_N_INSNS (3), /* mulsi */
556 COSTS_N_INSNS (2), /* mulsi_const */
557 COSTS_N_INSNS (2), /* mulsi_const9 */
558 COSTS_N_INSNS (3), /* muldi */
559 COSTS_N_INSNS (34), /* divsi */
560 COSTS_N_INSNS (34), /* divdi */
561 COSTS_N_INSNS (5), /* fp */
562 COSTS_N_INSNS (5), /* dmul */
563 COSTS_N_INSNS (19), /* sdiv */
564 COSTS_N_INSNS (33), /* ddiv */
565 32, /* cache line size */
571 /* Instruction costs on PPC476 processors. */
573 struct processor_costs ppc476_cost
= {
574 COSTS_N_INSNS (4), /* mulsi */
575 COSTS_N_INSNS (4), /* mulsi_const */
576 COSTS_N_INSNS (4), /* mulsi_const9 */
577 COSTS_N_INSNS (4), /* muldi */
578 COSTS_N_INSNS (11), /* divsi */
579 COSTS_N_INSNS (11), /* divdi */
580 COSTS_N_INSNS (6), /* fp */
581 COSTS_N_INSNS (6), /* dmul */
582 COSTS_N_INSNS (19), /* sdiv */
583 COSTS_N_INSNS (33), /* ddiv */
584 32, /* l1 cache line size */
590 /* Instruction costs on PPC601 processors. */
592 struct processor_costs ppc601_cost
= {
593 COSTS_N_INSNS (5), /* mulsi */
594 COSTS_N_INSNS (5), /* mulsi_const */
595 COSTS_N_INSNS (5), /* mulsi_const9 */
596 COSTS_N_INSNS (5), /* muldi */
597 COSTS_N_INSNS (36), /* divsi */
598 COSTS_N_INSNS (36), /* divdi */
599 COSTS_N_INSNS (4), /* fp */
600 COSTS_N_INSNS (5), /* dmul */
601 COSTS_N_INSNS (17), /* sdiv */
602 COSTS_N_INSNS (31), /* ddiv */
603 32, /* cache line size */
609 /* Instruction costs on PPC603 processors. */
611 struct processor_costs ppc603_cost
= {
612 COSTS_N_INSNS (5), /* mulsi */
613 COSTS_N_INSNS (3), /* mulsi_const */
614 COSTS_N_INSNS (2), /* mulsi_const9 */
615 COSTS_N_INSNS (5), /* muldi */
616 COSTS_N_INSNS (37), /* divsi */
617 COSTS_N_INSNS (37), /* divdi */
618 COSTS_N_INSNS (3), /* fp */
619 COSTS_N_INSNS (4), /* dmul */
620 COSTS_N_INSNS (18), /* sdiv */
621 COSTS_N_INSNS (33), /* ddiv */
622 32, /* cache line size */
628 /* Instruction costs on PPC604 processors. */
630 struct processor_costs ppc604_cost
= {
631 COSTS_N_INSNS (4), /* mulsi */
632 COSTS_N_INSNS (4), /* mulsi_const */
633 COSTS_N_INSNS (4), /* mulsi_const9 */
634 COSTS_N_INSNS (4), /* muldi */
635 COSTS_N_INSNS (20), /* divsi */
636 COSTS_N_INSNS (20), /* divdi */
637 COSTS_N_INSNS (3), /* fp */
638 COSTS_N_INSNS (3), /* dmul */
639 COSTS_N_INSNS (18), /* sdiv */
640 COSTS_N_INSNS (32), /* ddiv */
641 32, /* cache line size */
647 /* Instruction costs on PPC604e processors. */
649 struct processor_costs ppc604e_cost
= {
650 COSTS_N_INSNS (2), /* mulsi */
651 COSTS_N_INSNS (2), /* mulsi_const */
652 COSTS_N_INSNS (2), /* mulsi_const9 */
653 COSTS_N_INSNS (2), /* muldi */
654 COSTS_N_INSNS (20), /* divsi */
655 COSTS_N_INSNS (20), /* divdi */
656 COSTS_N_INSNS (3), /* fp */
657 COSTS_N_INSNS (3), /* dmul */
658 COSTS_N_INSNS (18), /* sdiv */
659 COSTS_N_INSNS (32), /* ddiv */
660 32, /* cache line size */
666 /* Instruction costs on PPC620 processors. */
668 struct processor_costs ppc620_cost
= {
669 COSTS_N_INSNS (5), /* mulsi */
670 COSTS_N_INSNS (4), /* mulsi_const */
671 COSTS_N_INSNS (3), /* mulsi_const9 */
672 COSTS_N_INSNS (7), /* muldi */
673 COSTS_N_INSNS (21), /* divsi */
674 COSTS_N_INSNS (37), /* divdi */
675 COSTS_N_INSNS (3), /* fp */
676 COSTS_N_INSNS (3), /* dmul */
677 COSTS_N_INSNS (18), /* sdiv */
678 COSTS_N_INSNS (32), /* ddiv */
679 128, /* cache line size */
685 /* Instruction costs on PPC630 processors. */
687 struct processor_costs ppc630_cost
= {
688 COSTS_N_INSNS (5), /* mulsi */
689 COSTS_N_INSNS (4), /* mulsi_const */
690 COSTS_N_INSNS (3), /* mulsi_const9 */
691 COSTS_N_INSNS (7), /* muldi */
692 COSTS_N_INSNS (21), /* divsi */
693 COSTS_N_INSNS (37), /* divdi */
694 COSTS_N_INSNS (3), /* fp */
695 COSTS_N_INSNS (3), /* dmul */
696 COSTS_N_INSNS (17), /* sdiv */
697 COSTS_N_INSNS (21), /* ddiv */
698 128, /* cache line size */
704 /* Instruction costs on Cell processor. */
705 /* COSTS_N_INSNS (1) ~ one add. */
707 struct processor_costs ppccell_cost
= {
708 COSTS_N_INSNS (9/2)+2, /* mulsi */
709 COSTS_N_INSNS (6/2), /* mulsi_const */
710 COSTS_N_INSNS (6/2), /* mulsi_const9 */
711 COSTS_N_INSNS (15/2)+2, /* muldi */
712 COSTS_N_INSNS (38/2), /* divsi */
713 COSTS_N_INSNS (70/2), /* divdi */
714 COSTS_N_INSNS (10/2), /* fp */
715 COSTS_N_INSNS (10/2), /* dmul */
716 COSTS_N_INSNS (74/2), /* sdiv */
717 COSTS_N_INSNS (74/2), /* ddiv */
718 128, /* cache line size */
724 /* Instruction costs on PPC750 and PPC7400 processors. */
726 struct processor_costs ppc750_cost
= {
727 COSTS_N_INSNS (5), /* mulsi */
728 COSTS_N_INSNS (3), /* mulsi_const */
729 COSTS_N_INSNS (2), /* mulsi_const9 */
730 COSTS_N_INSNS (5), /* muldi */
731 COSTS_N_INSNS (17), /* divsi */
732 COSTS_N_INSNS (17), /* divdi */
733 COSTS_N_INSNS (3), /* fp */
734 COSTS_N_INSNS (3), /* dmul */
735 COSTS_N_INSNS (17), /* sdiv */
736 COSTS_N_INSNS (31), /* ddiv */
737 32, /* cache line size */
743 /* Instruction costs on PPC7450 processors. */
745 struct processor_costs ppc7450_cost
= {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (3), /* mulsi_const */
748 COSTS_N_INSNS (3), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (23), /* divsi */
751 COSTS_N_INSNS (23), /* divdi */
752 COSTS_N_INSNS (5), /* fp */
753 COSTS_N_INSNS (5), /* dmul */
754 COSTS_N_INSNS (21), /* sdiv */
755 COSTS_N_INSNS (35), /* ddiv */
756 32, /* cache line size */
762 /* Instruction costs on PPC8540 processors. */
764 struct processor_costs ppc8540_cost
= {
765 COSTS_N_INSNS (4), /* mulsi */
766 COSTS_N_INSNS (4), /* mulsi_const */
767 COSTS_N_INSNS (4), /* mulsi_const9 */
768 COSTS_N_INSNS (4), /* muldi */
769 COSTS_N_INSNS (19), /* divsi */
770 COSTS_N_INSNS (19), /* divdi */
771 COSTS_N_INSNS (4), /* fp */
772 COSTS_N_INSNS (4), /* dmul */
773 COSTS_N_INSNS (29), /* sdiv */
774 COSTS_N_INSNS (29), /* ddiv */
775 32, /* cache line size */
778 1, /* prefetch streams /*/
781 /* Instruction costs on E300C2 and E300C3 cores. */
783 struct processor_costs ppce300c2c3_cost
= {
784 COSTS_N_INSNS (4), /* mulsi */
785 COSTS_N_INSNS (4), /* mulsi_const */
786 COSTS_N_INSNS (4), /* mulsi_const9 */
787 COSTS_N_INSNS (4), /* muldi */
788 COSTS_N_INSNS (19), /* divsi */
789 COSTS_N_INSNS (19), /* divdi */
790 COSTS_N_INSNS (3), /* fp */
791 COSTS_N_INSNS (4), /* dmul */
792 COSTS_N_INSNS (18), /* sdiv */
793 COSTS_N_INSNS (33), /* ddiv */
797 1, /* prefetch streams /*/
800 /* Instruction costs on PPCE500MC processors. */
802 struct processor_costs ppce500mc_cost
= {
803 COSTS_N_INSNS (4), /* mulsi */
804 COSTS_N_INSNS (4), /* mulsi_const */
805 COSTS_N_INSNS (4), /* mulsi_const9 */
806 COSTS_N_INSNS (4), /* muldi */
807 COSTS_N_INSNS (14), /* divsi */
808 COSTS_N_INSNS (14), /* divdi */
809 COSTS_N_INSNS (8), /* fp */
810 COSTS_N_INSNS (10), /* dmul */
811 COSTS_N_INSNS (36), /* sdiv */
812 COSTS_N_INSNS (66), /* ddiv */
813 64, /* cache line size */
816 1, /* prefetch streams /*/
819 /* Instruction costs on PPCE500MC64 processors. */
821 struct processor_costs ppce500mc64_cost
= {
822 COSTS_N_INSNS (4), /* mulsi */
823 COSTS_N_INSNS (4), /* mulsi_const */
824 COSTS_N_INSNS (4), /* mulsi_const9 */
825 COSTS_N_INSNS (4), /* muldi */
826 COSTS_N_INSNS (14), /* divsi */
827 COSTS_N_INSNS (14), /* divdi */
828 COSTS_N_INSNS (4), /* fp */
829 COSTS_N_INSNS (10), /* dmul */
830 COSTS_N_INSNS (36), /* sdiv */
831 COSTS_N_INSNS (66), /* ddiv */
832 64, /* cache line size */
835 1, /* prefetch streams /*/
838 /* Instruction costs on PPCE5500 processors. */
840 struct processor_costs ppce5500_cost
= {
841 COSTS_N_INSNS (5), /* mulsi */
842 COSTS_N_INSNS (5), /* mulsi_const */
843 COSTS_N_INSNS (4), /* mulsi_const9 */
844 COSTS_N_INSNS (5), /* muldi */
845 COSTS_N_INSNS (14), /* divsi */
846 COSTS_N_INSNS (14), /* divdi */
847 COSTS_N_INSNS (7), /* fp */
848 COSTS_N_INSNS (10), /* dmul */
849 COSTS_N_INSNS (36), /* sdiv */
850 COSTS_N_INSNS (66), /* ddiv */
851 64, /* cache line size */
854 1, /* prefetch streams /*/
857 /* Instruction costs on PPCE6500 processors. */
859 struct processor_costs ppce6500_cost
= {
860 COSTS_N_INSNS (5), /* mulsi */
861 COSTS_N_INSNS (5), /* mulsi_const */
862 COSTS_N_INSNS (4), /* mulsi_const9 */
863 COSTS_N_INSNS (5), /* muldi */
864 COSTS_N_INSNS (14), /* divsi */
865 COSTS_N_INSNS (14), /* divdi */
866 COSTS_N_INSNS (7), /* fp */
867 COSTS_N_INSNS (10), /* dmul */
868 COSTS_N_INSNS (36), /* sdiv */
869 COSTS_N_INSNS (66), /* ddiv */
870 64, /* cache line size */
873 1, /* prefetch streams /*/
876 /* Instruction costs on AppliedMicro Titan processors. */
878 struct processor_costs titan_cost
= {
879 COSTS_N_INSNS (5), /* mulsi */
880 COSTS_N_INSNS (5), /* mulsi_const */
881 COSTS_N_INSNS (5), /* mulsi_const9 */
882 COSTS_N_INSNS (5), /* muldi */
883 COSTS_N_INSNS (18), /* divsi */
884 COSTS_N_INSNS (18), /* divdi */
885 COSTS_N_INSNS (10), /* fp */
886 COSTS_N_INSNS (10), /* dmul */
887 COSTS_N_INSNS (46), /* sdiv */
888 COSTS_N_INSNS (72), /* ddiv */
889 32, /* cache line size */
892 1, /* prefetch streams /*/
895 /* Instruction costs on POWER4 and POWER5 processors. */
897 struct processor_costs power4_cost
= {
898 COSTS_N_INSNS (3), /* mulsi */
899 COSTS_N_INSNS (2), /* mulsi_const */
900 COSTS_N_INSNS (2), /* mulsi_const9 */
901 COSTS_N_INSNS (4), /* muldi */
902 COSTS_N_INSNS (18), /* divsi */
903 COSTS_N_INSNS (34), /* divdi */
904 COSTS_N_INSNS (3), /* fp */
905 COSTS_N_INSNS (3), /* dmul */
906 COSTS_N_INSNS (17), /* sdiv */
907 COSTS_N_INSNS (17), /* ddiv */
908 128, /* cache line size */
911 8, /* prefetch streams /*/
914 /* Instruction costs on POWER6 processors. */
916 struct processor_costs power6_cost
= {
917 COSTS_N_INSNS (8), /* mulsi */
918 COSTS_N_INSNS (8), /* mulsi_const */
919 COSTS_N_INSNS (8), /* mulsi_const9 */
920 COSTS_N_INSNS (8), /* muldi */
921 COSTS_N_INSNS (22), /* divsi */
922 COSTS_N_INSNS (28), /* divdi */
923 COSTS_N_INSNS (3), /* fp */
924 COSTS_N_INSNS (3), /* dmul */
925 COSTS_N_INSNS (13), /* sdiv */
926 COSTS_N_INSNS (16), /* ddiv */
927 128, /* cache line size */
930 16, /* prefetch streams */
933 /* Instruction costs on POWER7 processors. */
935 struct processor_costs power7_cost
= {
936 COSTS_N_INSNS (2), /* mulsi */
937 COSTS_N_INSNS (2), /* mulsi_const */
938 COSTS_N_INSNS (2), /* mulsi_const9 */
939 COSTS_N_INSNS (2), /* muldi */
940 COSTS_N_INSNS (18), /* divsi */
941 COSTS_N_INSNS (34), /* divdi */
942 COSTS_N_INSNS (3), /* fp */
943 COSTS_N_INSNS (3), /* dmul */
944 COSTS_N_INSNS (13), /* sdiv */
945 COSTS_N_INSNS (16), /* ddiv */
946 128, /* cache line size */
949 12, /* prefetch streams */
952 /* Instruction costs on POWER8 processors. */
954 struct processor_costs power8_cost
= {
955 COSTS_N_INSNS (3), /* mulsi */
956 COSTS_N_INSNS (3), /* mulsi_const */
957 COSTS_N_INSNS (3), /* mulsi_const9 */
958 COSTS_N_INSNS (3), /* muldi */
959 COSTS_N_INSNS (19), /* divsi */
960 COSTS_N_INSNS (35), /* divdi */
961 COSTS_N_INSNS (3), /* fp */
962 COSTS_N_INSNS (3), /* dmul */
963 COSTS_N_INSNS (14), /* sdiv */
964 COSTS_N_INSNS (17), /* ddiv */
965 128, /* cache line size */
968 12, /* prefetch streams */
971 /* Instruction costs on POWER A2 processors. */
973 struct processor_costs ppca2_cost
= {
974 COSTS_N_INSNS (16), /* mulsi */
975 COSTS_N_INSNS (16), /* mulsi_const */
976 COSTS_N_INSNS (16), /* mulsi_const9 */
977 COSTS_N_INSNS (16), /* muldi */
978 COSTS_N_INSNS (22), /* divsi */
979 COSTS_N_INSNS (28), /* divdi */
980 COSTS_N_INSNS (3), /* fp */
981 COSTS_N_INSNS (3), /* dmul */
982 COSTS_N_INSNS (59), /* sdiv */
983 COSTS_N_INSNS (72), /* ddiv */
987 16, /* prefetch streams */
991 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
992 #undef RS6000_BUILTIN_1
993 #undef RS6000_BUILTIN_2
994 #undef RS6000_BUILTIN_3
995 #undef RS6000_BUILTIN_A
996 #undef RS6000_BUILTIN_D
997 #undef RS6000_BUILTIN_E
998 #undef RS6000_BUILTIN_H
999 #undef RS6000_BUILTIN_P
1000 #undef RS6000_BUILTIN_Q
1001 #undef RS6000_BUILTIN_S
1002 #undef RS6000_BUILTIN_X
1004 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1005 { NAME, ICODE, MASK, ATTR },
1007 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1008 { NAME, ICODE, MASK, ATTR },
1010 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1011 { NAME, ICODE, MASK, ATTR },
1013 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1014 { NAME, ICODE, MASK, ATTR },
1016 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1017 { NAME, ICODE, MASK, ATTR },
1019 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1020 { NAME, ICODE, MASK, ATTR },
1022 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1023 { NAME, ICODE, MASK, ATTR },
1025 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1026 { NAME, ICODE, MASK, ATTR },
1028 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1029 { NAME, ICODE, MASK, ATTR },
1031 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1032 { NAME, ICODE, MASK, ATTR },
1034 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1035 { NAME, ICODE, MASK, ATTR },
1037 struct rs6000_builtin_info_type
{
1039 const enum insn_code icode
;
1040 const HOST_WIDE_INT mask
;
1041 const unsigned attr
;
1044 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1046 #include "rs6000-builtin.def"
1049 #undef RS6000_BUILTIN_1
1050 #undef RS6000_BUILTIN_2
1051 #undef RS6000_BUILTIN_3
1052 #undef RS6000_BUILTIN_A
1053 #undef RS6000_BUILTIN_D
1054 #undef RS6000_BUILTIN_E
1055 #undef RS6000_BUILTIN_H
1056 #undef RS6000_BUILTIN_P
1057 #undef RS6000_BUILTIN_Q
1058 #undef RS6000_BUILTIN_S
1059 #undef RS6000_BUILTIN_X
1061 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1062 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1065 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1066 static bool spe_func_has_64bit_regs_p (void);
1067 static struct machine_function
* rs6000_init_machine_status (void);
1068 static int rs6000_ra_ever_killed (void);
1069 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1070 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1071 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1072 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1073 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1074 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1075 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1076 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1078 static int rs6000_debug_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
1079 static bool is_microcoded_insn (rtx_insn
*);
1080 static bool is_nonpipeline_insn (rtx_insn
*);
1081 static bool is_cracked_insn (rtx_insn
*);
1082 static bool is_load_insn (rtx
, rtx
*);
1083 static bool is_store_insn (rtx
, rtx
*);
1084 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1085 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1086 static bool insn_must_be_first_in_group (rtx_insn
*);
1087 static bool insn_must_be_last_in_group (rtx_insn
*);
1088 static void altivec_init_builtins (void);
1089 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1090 enum machine_mode
, enum machine_mode
,
1091 enum rs6000_builtins
, const char *name
);
1092 static void rs6000_common_init_builtins (void);
1093 static void paired_init_builtins (void);
1094 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1095 static void spe_init_builtins (void);
1096 static void htm_init_builtins (void);
1097 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1098 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1099 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1100 static rs6000_stack_t
*rs6000_stack_info (void);
1101 static void is_altivec_return_reg (rtx
, void *);
1102 int easy_vector_constant (rtx
, enum machine_mode
);
1103 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1104 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1105 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1108 static void macho_branch_islands (void);
1110 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1112 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1114 static bool rs6000_mode_dependent_address (const_rtx
);
1115 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1116 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1117 enum machine_mode
, rtx
);
1118 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1121 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1122 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1124 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1126 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1129 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1132 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1135 static bool rs6000_save_toc_in_prologue_p (void);
1137 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1139 = rs6000_legitimize_reload_address
;
1141 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1142 = rs6000_mode_dependent_address
;
1144 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1145 enum machine_mode
, rtx
)
1146 = rs6000_secondary_reload_class
;
1148 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1149 = rs6000_preferred_reload_class
;
1151 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1153 = rs6000_secondary_memory_needed
;
1155 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1158 = rs6000_cannot_change_mode_class
;
1160 const int INSN_NOT_AVAILABLE
= -1;
1162 static void rs6000_print_isa_options (FILE *, int, const char *,
1164 static void rs6000_print_builtin_options (FILE *, int, const char *,
1167 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1168 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1169 enum rs6000_reg_type
,
1171 secondary_reload_info
*,
1173 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1175 /* Hash table stuff for keeping track of TOC entries. */
1177 struct GTY(()) toc_hash_struct
1179 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1180 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1182 enum machine_mode key_mode
;
1186 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1188 /* Hash table to keep track of the argument types for builtin functions. */
1190 struct GTY(()) builtin_hash_struct
1193 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1194 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1197 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1200 /* Default register names. */
1201 char rs6000_reg_names
[][8] =
1203 "0", "1", "2", "3", "4", "5", "6", "7",
1204 "8", "9", "10", "11", "12", "13", "14", "15",
1205 "16", "17", "18", "19", "20", "21", "22", "23",
1206 "24", "25", "26", "27", "28", "29", "30", "31",
1207 "0", "1", "2", "3", "4", "5", "6", "7",
1208 "8", "9", "10", "11", "12", "13", "14", "15",
1209 "16", "17", "18", "19", "20", "21", "22", "23",
1210 "24", "25", "26", "27", "28", "29", "30", "31",
1211 "mq", "lr", "ctr","ap",
1212 "0", "1", "2", "3", "4", "5", "6", "7",
1214 /* AltiVec registers. */
1215 "0", "1", "2", "3", "4", "5", "6", "7",
1216 "8", "9", "10", "11", "12", "13", "14", "15",
1217 "16", "17", "18", "19", "20", "21", "22", "23",
1218 "24", "25", "26", "27", "28", "29", "30", "31",
1220 /* SPE registers. */
1221 "spe_acc", "spefscr",
1222 /* Soft frame pointer. */
1224 /* HTM SPR registers. */
1225 "tfhar", "tfiar", "texasr",
1226 /* SPE High registers. */
1227 "0", "1", "2", "3", "4", "5", "6", "7",
1228 "8", "9", "10", "11", "12", "13", "14", "15",
1229 "16", "17", "18", "19", "20", "21", "22", "23",
1230 "24", "25", "26", "27", "28", "29", "30", "31"
1233 #ifdef TARGET_REGNAMES
1234 static const char alt_reg_names
[][8] =
1236 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1237 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1238 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1239 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1240 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1241 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1242 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1243 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1244 "mq", "lr", "ctr", "ap",
1245 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1247 /* AltiVec registers. */
1248 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1249 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1250 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1251 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1253 /* SPE registers. */
1254 "spe_acc", "spefscr",
1255 /* Soft frame pointer. */
1257 /* HTM SPR registers. */
1258 "tfhar", "tfiar", "texasr",
1259 /* SPE High registers. */
1260 "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
1261 "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
1262 "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
1263 "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
1267 /* Table of valid machine attributes. */
1269 static const struct attribute_spec rs6000_attribute_table
[] =
1271 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1272 affects_type_identity } */
1273 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1275 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1277 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1279 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1281 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1283 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1284 SUBTARGET_ATTRIBUTE_TABLE
,
1286 { NULL
, 0, 0, false, false, false, NULL
, false }
1289 #ifndef TARGET_PROFILE_KERNEL
1290 #define TARGET_PROFILE_KERNEL 0
1293 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1294 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1296 /* Initialize the GCC target structure. */
1297 #undef TARGET_ATTRIBUTE_TABLE
1298 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1299 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1300 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1301 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1302 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1304 #undef TARGET_ASM_ALIGNED_DI_OP
1305 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1307 /* Default unaligned ops are only provided for ELF. Find the ops needed
1308 for non-ELF systems. */
1309 #ifndef OBJECT_FORMAT_ELF
1311 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1313 #undef TARGET_ASM_UNALIGNED_HI_OP
1314 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1315 #undef TARGET_ASM_UNALIGNED_SI_OP
1316 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1317 #undef TARGET_ASM_UNALIGNED_DI_OP
1318 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1321 #undef TARGET_ASM_UNALIGNED_HI_OP
1322 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1323 #undef TARGET_ASM_UNALIGNED_SI_OP
1324 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1325 #undef TARGET_ASM_UNALIGNED_DI_OP
1326 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1327 #undef TARGET_ASM_ALIGNED_DI_OP
1328 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1332 /* This hook deals with fixups for relocatable code and DI-mode objects
1334 #undef TARGET_ASM_INTEGER
1335 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1337 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1338 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1339 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1342 #undef TARGET_SET_UP_BY_PROLOGUE
1343 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1345 #undef TARGET_HAVE_TLS
1346 #define TARGET_HAVE_TLS HAVE_AS_TLS
1348 #undef TARGET_CANNOT_FORCE_CONST_MEM
1349 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1351 #undef TARGET_DELEGITIMIZE_ADDRESS
1352 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1354 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1355 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1357 #undef TARGET_ASM_FUNCTION_PROLOGUE
1358 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1359 #undef TARGET_ASM_FUNCTION_EPILOGUE
1360 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1362 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1363 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1365 #undef TARGET_LEGITIMIZE_ADDRESS
1366 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1368 #undef TARGET_SCHED_VARIABLE_ISSUE
1369 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1371 #undef TARGET_SCHED_ISSUE_RATE
1372 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1373 #undef TARGET_SCHED_ADJUST_COST
1374 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1375 #undef TARGET_SCHED_ADJUST_PRIORITY
1376 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1377 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1378 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1379 #undef TARGET_SCHED_INIT
1380 #define TARGET_SCHED_INIT rs6000_sched_init
1381 #undef TARGET_SCHED_FINISH
1382 #define TARGET_SCHED_FINISH rs6000_sched_finish
1383 #undef TARGET_SCHED_REORDER
1384 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1385 #undef TARGET_SCHED_REORDER2
1386 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1388 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1389 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1391 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1392 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1394 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1395 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1396 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1397 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1398 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1399 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1400 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1401 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1403 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1404 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1405 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1406 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1407 rs6000_builtin_support_vector_misalignment
1408 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1409 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1410 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1411 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1412 rs6000_builtin_vectorization_cost
1413 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1414 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1415 rs6000_preferred_simd_mode
1416 #undef TARGET_VECTORIZE_INIT_COST
1417 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1418 #undef TARGET_VECTORIZE_ADD_STMT_COST
1419 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1420 #undef TARGET_VECTORIZE_FINISH_COST
1421 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1422 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1423 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1425 #undef TARGET_INIT_BUILTINS
1426 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1427 #undef TARGET_BUILTIN_DECL
1428 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1430 #undef TARGET_EXPAND_BUILTIN
1431 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1433 #undef TARGET_MANGLE_TYPE
1434 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1436 #undef TARGET_INIT_LIBFUNCS
1437 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1440 #undef TARGET_BINDS_LOCAL_P
1441 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1444 #undef TARGET_MS_BITFIELD_LAYOUT_P
1445 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1447 #undef TARGET_ASM_OUTPUT_MI_THUNK
1448 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1450 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1451 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1453 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1454 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1456 #undef TARGET_REGISTER_MOVE_COST
1457 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1458 #undef TARGET_MEMORY_MOVE_COST
1459 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1460 #undef TARGET_RTX_COSTS
1461 #define TARGET_RTX_COSTS rs6000_rtx_costs
1462 #undef TARGET_ADDRESS_COST
1463 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1465 #undef TARGET_DWARF_REGISTER_SPAN
1466 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1468 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1469 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1471 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1472 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1474 /* On rs6000, function arguments are promoted, as are function return
1476 #undef TARGET_PROMOTE_FUNCTION_MODE
1477 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1479 #undef TARGET_RETURN_IN_MEMORY
1480 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1482 #undef TARGET_RETURN_IN_MSB
1483 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1485 #undef TARGET_SETUP_INCOMING_VARARGS
1486 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1488 /* Always strict argument naming on rs6000. */
1489 #undef TARGET_STRICT_ARGUMENT_NAMING
1490 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1491 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1492 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1493 #undef TARGET_SPLIT_COMPLEX_ARG
1494 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1495 #undef TARGET_MUST_PASS_IN_STACK
1496 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1497 #undef TARGET_PASS_BY_REFERENCE
1498 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1499 #undef TARGET_ARG_PARTIAL_BYTES
1500 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1501 #undef TARGET_FUNCTION_ARG_ADVANCE
1502 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1503 #undef TARGET_FUNCTION_ARG
1504 #define TARGET_FUNCTION_ARG rs6000_function_arg
1505 #undef TARGET_FUNCTION_ARG_BOUNDARY
1506 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1508 #undef TARGET_BUILD_BUILTIN_VA_LIST
1509 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1511 #undef TARGET_EXPAND_BUILTIN_VA_START
1512 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1514 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1515 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1517 #undef TARGET_EH_RETURN_FILTER_MODE
1518 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1520 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1521 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1523 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1524 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1526 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1527 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1529 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1530 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1532 #undef TARGET_OPTION_OVERRIDE
1533 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1535 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1536 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1537 rs6000_builtin_vectorized_function
1540 #undef TARGET_STACK_PROTECT_FAIL
1541 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1544 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1545 The PowerPC architecture requires only weak consistency among
1546 processors--that is, memory accesses between processors need not be
1547 sequentially consistent and memory accesses among processors can occur
1548 in any order. The ability to order memory accesses weakly provides
1549 opportunities for more efficient use of the system bus. Unless a
1550 dependency exists, the 604e allows read operations to precede store
1552 #undef TARGET_RELAXED_ORDERING
1553 #define TARGET_RELAXED_ORDERING true
1556 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1557 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1560 /* Use a 32-bit anchor range. This leads to sequences like:
1562 addis tmp,anchor,high
1565 where tmp itself acts as an anchor, and can be shared between
1566 accesses to the same 64k page. */
1567 #undef TARGET_MIN_ANCHOR_OFFSET
1568 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1569 #undef TARGET_MAX_ANCHOR_OFFSET
1570 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1571 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1572 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1573 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1574 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1576 #undef TARGET_BUILTIN_RECIPROCAL
1577 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1579 #undef TARGET_EXPAND_TO_RTL_HOOK
1580 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1582 #undef TARGET_INSTANTIATE_DECLS
1583 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1585 #undef TARGET_SECONDARY_RELOAD
1586 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1588 #undef TARGET_LEGITIMATE_ADDRESS_P
1589 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1591 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1592 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1595 #define TARGET_LRA_P rs6000_lra_p
1597 #undef TARGET_CAN_ELIMINATE
1598 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1600 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1601 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1603 #undef TARGET_TRAMPOLINE_INIT
1604 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1606 #undef TARGET_FUNCTION_VALUE
1607 #define TARGET_FUNCTION_VALUE rs6000_function_value
1609 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1610 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1612 #undef TARGET_OPTION_SAVE
1613 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1615 #undef TARGET_OPTION_RESTORE
1616 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1618 #undef TARGET_OPTION_PRINT
1619 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1621 #undef TARGET_CAN_INLINE_P
1622 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1624 #undef TARGET_SET_CURRENT_FUNCTION
1625 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1627 #undef TARGET_LEGITIMATE_CONSTANT_P
1628 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1630 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1631 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1633 #undef TARGET_CAN_USE_DOLOOP_P
1634 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1637 /* Processor table. */
1640 const char *const name
; /* Canonical processor name. */
1641 const enum processor_type processor
; /* Processor type enum value. */
1642 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1645 static struct rs6000_ptt
const processor_target_table
[] =
1647 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1648 #include "rs6000-cpus.def"
1652 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1656 rs6000_cpu_name_lookup (const char *name
)
1662 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1663 if (! strcmp (name
, processor_target_table
[i
].name
))
1671 /* Return number of consecutive hard regs needed starting at reg REGNO
1672 to hold something of mode MODE.
1673 This is ordinarily the length in words of a value of mode MODE
1674 but can be less for certain modes in special long registers.
1676 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1677 scalar instructions. The upper 32 bits are only available to the
1680 POWER and PowerPC GPRs hold 32 bits worth;
1681 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1684 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1686 unsigned HOST_WIDE_INT reg_size
;
1688 /* TF/TD modes are special in that they always take 2 registers. */
1689 if (FP_REGNO_P (regno
))
1690 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1691 ? UNITS_PER_VSX_WORD
1692 : UNITS_PER_FP_WORD
);
1694 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1695 reg_size
= UNITS_PER_SPE_WORD
;
1697 else if (ALTIVEC_REGNO_P (regno
))
1698 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1700 /* The value returned for SCmode in the E500 double case is 2 for
1701 ABI compatibility; storing an SCmode value in a single register
1702 would require function_arg and rs6000_spe_function_arg to handle
1703 SCmode so as to pass the value correctly in a pair of
1705 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1706 && !DECIMAL_FLOAT_MODE_P (mode
))
1707 reg_size
= UNITS_PER_FP_WORD
;
1710 reg_size
= UNITS_PER_WORD
;
1712 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1715 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1718 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1720 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1722 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1723 register combinations, and use PTImode where we need to deal with quad
1724 word memory operations. Don't allow quad words in the argument or frame
1725 pointer registers, just registers 0..31. */
1726 if (mode
== PTImode
)
1727 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1728 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1729 && ((regno
& 1) == 0));
1731 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1732 implementations. Don't allow an item to be split between a FP register
1733 and an Altivec register. Allow TImode in all VSX registers if the user
1735 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1736 && (VECTOR_MEM_VSX_P (mode
)
1737 || reg_addr
[mode
].scalar_in_vmx_p
1738 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1739 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1741 if (FP_REGNO_P (regno
))
1742 return FP_REGNO_P (last_regno
);
1744 if (ALTIVEC_REGNO_P (regno
))
1746 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
1749 return ALTIVEC_REGNO_P (last_regno
);
1753 /* The GPRs can hold any mode, but values bigger than one register
1754 cannot go past R31. */
1755 if (INT_REGNO_P (regno
))
1756 return INT_REGNO_P (last_regno
);
1758 /* The float registers (except for VSX vector modes) can only hold floating
1759 modes and DImode. */
1760 if (FP_REGNO_P (regno
))
1762 if (SCALAR_FLOAT_MODE_P (mode
)
1763 && (mode
!= TDmode
|| (regno
% 2) == 0)
1764 && FP_REGNO_P (last_regno
))
1767 if (GET_MODE_CLASS (mode
) == MODE_INT
1768 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1771 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1772 && PAIRED_VECTOR_MODE (mode
))
1778 /* The CR register can only hold CC modes. */
1779 if (CR_REGNO_P (regno
))
1780 return GET_MODE_CLASS (mode
) == MODE_CC
;
1782 if (CA_REGNO_P (regno
))
1783 return mode
== Pmode
|| mode
== SImode
;
1785 /* AltiVec only in AldyVec registers. */
1786 if (ALTIVEC_REGNO_P (regno
))
1787 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1788 || mode
== V1TImode
);
1790 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1791 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1794 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1795 and it must be able to fit within the register set. */
1797 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1800 /* Print interesting facts about registers. */
1802 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1806 for (r
= first_regno
; r
<= last_regno
; ++r
)
1808 const char *comma
= "";
1811 if (first_regno
== last_regno
)
1812 fprintf (stderr
, "%s:\t", reg_name
);
1814 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1817 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1818 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1822 fprintf (stderr
, ",\n\t");
1827 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1828 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1829 rs6000_hard_regno_nregs
[m
][r
]);
1831 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1836 if (call_used_regs
[r
])
1840 fprintf (stderr
, ",\n\t");
1845 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1853 fprintf (stderr
, ",\n\t");
1858 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1864 fprintf (stderr
, ",\n\t");
1868 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1869 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1874 fprintf (stderr
, ",\n\t");
1878 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1883 rs6000_debug_vector_unit (enum rs6000_vector v
)
1889 case VECTOR_NONE
: ret
= "none"; break;
1890 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1891 case VECTOR_VSX
: ret
= "vsx"; break;
1892 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1893 case VECTOR_PAIRED
: ret
= "paired"; break;
1894 case VECTOR_SPE
: ret
= "spe"; break;
1895 case VECTOR_OTHER
: ret
= "other"; break;
1896 default: ret
= "unknown"; break;
1902 /* Print the address masks in a human readble fashion. */
1904 rs6000_debug_print_mode (ssize_t m
)
1908 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1909 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1911 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1913 " %s: %c%c%c%c%c%c",
1914 reload_reg_map
[rc
].name
,
1915 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1916 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1917 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1918 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1919 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1920 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1923 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1924 || rs6000_vector_mem
[m
] != VECTOR_NONE
1925 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1926 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
)
1927 || reg_addr
[m
].scalar_in_vmx_p
)
1930 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c",
1931 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1932 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1933 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1934 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*',
1935 (reg_addr
[m
].scalar_in_vmx_p
) ? 'y' : 'n');
1938 fputs ("\n", stderr
);
1941 #define DEBUG_FMT_ID "%-32s= "
1942 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1943 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1944 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1946 /* Print various interesting information with -mdebug=reg. */
1948 rs6000_debug_reg_global (void)
1950 static const char *const tf
[2] = { "false", "true" };
1951 const char *nl
= (const char *)0;
1954 char costly_num
[20];
1956 char flags_buffer
[40];
1957 const char *costly_str
;
1958 const char *nop_str
;
1959 const char *trace_str
;
1960 const char *abi_str
;
1961 const char *cmodel_str
;
1962 struct cl_target_option cl_opts
;
1964 /* Modes we want tieable information on. */
1965 static const enum machine_mode print_tieable_modes
[] = {
2001 /* Virtual regs we are interested in. */
2002 const static struct {
2003 int regno
; /* register number. */
2004 const char *name
; /* register name. */
2005 } virtual_regs
[] = {
2006 { STACK_POINTER_REGNUM
, "stack pointer:" },
2007 { TOC_REGNUM
, "toc: " },
2008 { STATIC_CHAIN_REGNUM
, "static chain: " },
2009 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2010 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2011 { ARG_POINTER_REGNUM
, "arg pointer: " },
2012 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2013 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2014 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2015 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2016 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2017 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2018 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2019 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2020 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2021 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2024 fputs ("\nHard register information:\n", stderr
);
2025 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2026 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2027 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2030 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2031 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2032 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2033 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2034 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2035 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2036 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2037 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2039 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2040 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2041 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2045 "d reg_class = %s\n"
2046 "f reg_class = %s\n"
2047 "v reg_class = %s\n"
2048 "wa reg_class = %s\n"
2049 "wd reg_class = %s\n"
2050 "wf reg_class = %s\n"
2051 "wg reg_class = %s\n"
2052 "wh reg_class = %s\n"
2053 "wi reg_class = %s\n"
2054 "wj reg_class = %s\n"
2055 "wk reg_class = %s\n"
2056 "wl reg_class = %s\n"
2057 "wm reg_class = %s\n"
2058 "wr reg_class = %s\n"
2059 "ws reg_class = %s\n"
2060 "wt reg_class = %s\n"
2061 "wu reg_class = %s\n"
2062 "wv reg_class = %s\n"
2063 "ww reg_class = %s\n"
2064 "wx reg_class = %s\n"
2065 "wy reg_class = %s\n"
2066 "wz reg_class = %s\n"
2068 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2069 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2070 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2071 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2072 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2073 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2074 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2075 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2076 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2077 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2078 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2079 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2080 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2081 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2082 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2083 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2084 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2085 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2086 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2087 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2088 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2089 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2092 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2093 rs6000_debug_print_mode (m
);
2095 fputs ("\n", stderr
);
2097 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2099 enum machine_mode mode1
= print_tieable_modes
[m1
];
2100 bool first_time
= true;
2102 nl
= (const char *)0;
2103 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2105 enum machine_mode mode2
= print_tieable_modes
[m2
];
2106 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2110 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2115 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2120 fputs ("\n", stderr
);
2126 if (rs6000_recip_control
)
2128 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2130 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2131 if (rs6000_recip_bits
[m
])
2134 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2136 (RS6000_RECIP_AUTO_RE_P (m
)
2138 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2139 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2141 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2144 fputs ("\n", stderr
);
2147 if (rs6000_cpu_index
>= 0)
2149 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2151 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2153 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2154 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2157 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2159 if (rs6000_tune_index
>= 0)
2161 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2163 = processor_target_table
[rs6000_tune_index
].target_enable
;
2165 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2166 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2169 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2171 cl_target_option_save (&cl_opts
, &global_options
);
2172 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2175 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2176 rs6000_isa_flags_explicit
);
2178 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2179 rs6000_builtin_mask
);
2181 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2183 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2184 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2186 switch (rs6000_sched_costly_dep
)
2188 case max_dep_latency
:
2189 costly_str
= "max_dep_latency";
2193 costly_str
= "no_dep_costly";
2196 case all_deps_costly
:
2197 costly_str
= "all_deps_costly";
2200 case true_store_to_load_dep_costly
:
2201 costly_str
= "true_store_to_load_dep_costly";
2204 case store_to_load_dep_costly
:
2205 costly_str
= "store_to_load_dep_costly";
2209 costly_str
= costly_num
;
2210 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2214 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2216 switch (rs6000_sched_insert_nops
)
2218 case sched_finish_regroup_exact
:
2219 nop_str
= "sched_finish_regroup_exact";
2222 case sched_finish_pad_groups
:
2223 nop_str
= "sched_finish_pad_groups";
2226 case sched_finish_none
:
2227 nop_str
= "sched_finish_none";
2232 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2236 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2238 switch (rs6000_sdata
)
2245 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2249 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2253 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2258 switch (rs6000_traceback
)
2260 case traceback_default
: trace_str
= "default"; break;
2261 case traceback_none
: trace_str
= "none"; break;
2262 case traceback_part
: trace_str
= "part"; break;
2263 case traceback_full
: trace_str
= "full"; break;
2264 default: trace_str
= "unknown"; break;
2267 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2269 switch (rs6000_current_cmodel
)
2271 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2272 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2273 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2274 default: cmodel_str
= "unknown"; break;
2277 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2279 switch (rs6000_current_abi
)
2281 case ABI_NONE
: abi_str
= "none"; break;
2282 case ABI_AIX
: abi_str
= "aix"; break;
2283 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2284 case ABI_V4
: abi_str
= "V4"; break;
2285 case ABI_DARWIN
: abi_str
= "darwin"; break;
2286 default: abi_str
= "unknown"; break;
2289 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2291 if (rs6000_altivec_abi
)
2292 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2295 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2297 if (rs6000_darwin64_abi
)
2298 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2300 if (rs6000_float_gprs
)
2301 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2303 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2304 (TARGET_FPRS
? "true" : "false"));
2306 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2307 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2309 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2310 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2312 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2313 (TARGET_SOFT_FLOAT
? "true" : "false"));
2315 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2316 (TARGET_E500_SINGLE
? "true" : "false"));
2318 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2319 (TARGET_E500_DOUBLE
? "true" : "false"));
2321 if (TARGET_LINK_STACK
)
2322 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2324 if (targetm
.lra_p ())
2325 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2327 if (TARGET_P8_FUSION
)
2328 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2329 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2331 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2332 TARGET_SECURE_PLT
? "secure" : "bss");
2333 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2334 aix_struct_return
? "aix" : "sysv");
2335 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2336 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2337 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2338 tf
[!!rs6000_align_branch_targets
]);
2339 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2340 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2341 rs6000_long_double_type_size
);
2342 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2343 (int)rs6000_sched_restricted_insns_priority
);
2344 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2346 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2347 (int)RS6000_BUILTIN_COUNT
);
2350 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2351 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2355 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2356 legitimate address support to figure out the appropriate addressing to
2360 rs6000_setup_reg_addr_masks (void)
2362 ssize_t rc
, reg
, m
, nregs
;
2363 addr_mask_type any_addr_mask
, addr_mask
;
2365 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2367 enum machine_mode m2
= (enum machine_mode
)m
;
2369 /* SDmode is special in that we want to access it only via REG+REG
2370 addressing on power7 and above, since we want to use the LFIWZX and
2371 STFIWZX instructions to load it. */
2372 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2375 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2378 reg
= reload_reg_map
[rc
].reg
;
2380 /* Can mode values go in the GPR/FPR/Altivec registers? */
2381 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2383 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2384 addr_mask
|= RELOAD_REG_VALID
;
2386 /* Indicate if the mode takes more than 1 physical register. If
2387 it takes a single register, indicate it can do REG+REG
2389 if (nregs
> 1 || m
== BLKmode
)
2390 addr_mask
|= RELOAD_REG_MULTIPLE
;
2392 addr_mask
|= RELOAD_REG_INDEXED
;
2394 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2395 addressing. Restrict addressing on SPE for 64-bit types
2396 because of the SUBREG hackery used to address 64-bit floats in
2397 '32-bit' GPRs. To simplify secondary reload, don't allow
2398 update forms on scalar floating point types that can go in the
2402 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2403 && GET_MODE_SIZE (m2
) <= 8
2404 && !VECTOR_MODE_P (m2
)
2405 && !COMPLEX_MODE_P (m2
)
2407 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m2
) == 8)
2408 && !reg_addr
[m2
].scalar_in_vmx_p
)
2410 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2412 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2413 we don't allow PRE_MODIFY for some multi-register
2418 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2422 if (TARGET_POWERPC64
)
2423 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2429 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2435 /* GPR and FPR registers can do REG+OFFSET addressing, except
2436 possibly for SDmode. */
2437 if ((addr_mask
!= 0) && !indexed_only_p
2438 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2439 addr_mask
|= RELOAD_REG_OFFSET
;
2441 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2442 any_addr_mask
|= addr_mask
;
2445 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2450 /* Initialize the various global tables that are based on register size. */
2452 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2458 /* Precalculate REGNO_REG_CLASS. */
2459 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2460 for (r
= 1; r
< 32; ++r
)
2461 rs6000_regno_regclass
[r
] = BASE_REGS
;
2463 for (r
= 32; r
< 64; ++r
)
2464 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2466 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2467 rs6000_regno_regclass
[r
] = NO_REGS
;
2469 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2470 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2472 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2473 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2474 rs6000_regno_regclass
[r
] = CR_REGS
;
2476 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2477 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2478 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
2479 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2480 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2481 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2482 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2483 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2484 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2485 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2486 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2487 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2489 /* Precalculate register class to simpler reload register class. We don't
2490 need all of the register classes that are combinations of different
2491 classes, just the simple ones that have constraint letters. */
2492 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2493 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2495 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2496 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2497 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2498 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2499 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2500 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2501 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2502 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2503 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2504 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2505 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2506 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2510 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2511 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2515 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2516 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2519 /* Precalculate the valid memory formats as well as the vector information,
2520 this must be set up before the rs6000_hard_regno_nregs_internal calls
2522 gcc_assert ((int)VECTOR_NONE
== 0);
2523 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2524 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2526 gcc_assert ((int)CODE_FOR_nothing
== 0);
2527 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2529 gcc_assert ((int)NO_REGS
== 0);
2530 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2532 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2533 believes it can use native alignment or still uses 128-bit alignment. */
2534 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2545 /* V2DF mode, VSX only. */
2548 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2549 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2550 rs6000_vector_align
[V2DFmode
] = align64
;
2553 /* V4SF mode, either VSX or Altivec. */
2556 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2557 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2558 rs6000_vector_align
[V4SFmode
] = align32
;
2560 else if (TARGET_ALTIVEC
)
2562 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2563 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2564 rs6000_vector_align
[V4SFmode
] = align32
;
2567 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2571 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2572 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2573 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2574 rs6000_vector_align
[V4SImode
] = align32
;
2575 rs6000_vector_align
[V8HImode
] = align32
;
2576 rs6000_vector_align
[V16QImode
] = align32
;
2580 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2581 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2582 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2586 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2587 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2588 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2592 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2593 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2596 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2597 rs6000_vector_unit
[V2DImode
]
2598 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2599 rs6000_vector_align
[V2DImode
] = align64
;
2601 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2602 rs6000_vector_unit
[V1TImode
]
2603 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2604 rs6000_vector_align
[V1TImode
] = 128;
2607 /* DFmode, see if we want to use the VSX unit. */
2608 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2610 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2611 rs6000_vector_mem
[DFmode
]
2612 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2613 rs6000_vector_align
[DFmode
] = align64
;
2616 /* Allow TImode in VSX register and set the VSX memory macros. */
2617 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2619 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2620 rs6000_vector_align
[TImode
] = align64
;
2623 /* TODO add SPE and paired floating point vector support. */
2625 /* Register class constraints for the constraints that depend on compile
2626 switches. When the VSX code was added, different constraints were added
2627 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2628 of the VSX registers are used. The register classes for scalar floating
2629 point types is set, based on whether we allow that type into the upper
2630 (Altivec) registers. GCC has register classes to target the Altivec
2631 registers for load/store operations, to select using a VSX memory
2632 operation instead of the traditional floating point operation. The
2635 d - Register class to use with traditional DFmode instructions.
2636 f - Register class to use with traditional SFmode instructions.
2637 v - Altivec register.
2638 wa - Any VSX register.
2639 wc - Reserved to represent individual CR bits (used in LLVM).
2640 wd - Preferred register class for V2DFmode.
2641 wf - Preferred register class for V4SFmode.
2642 wg - Float register for power6x move insns.
2643 wh - FP register for direct move instructions.
2644 wi - FP or VSX register to hold 64-bit integers for VSX insns.
2645 wj - FP or VSX register to hold 64-bit integers for direct moves.
2646 wk - FP or VSX register to hold 64-bit doubles for direct moves.
2647 wl - Float register if we can do 32-bit signed int loads.
2648 wm - VSX register for ISA 2.07 direct move operations.
2649 wn - always NO_REGS.
2650 wr - GPR if 64-bit mode is permitted.
2651 ws - Register class to do ISA 2.06 DF operations.
2652 wt - VSX register for TImode in VSX registers.
2653 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2654 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2655 ww - Register class to do SF conversions in with VSX operations.
2656 wx - Float register if we can do 32-bit int stores.
2657 wy - Register class to do ISA 2.07 SF operations.
2658 wz - Float register if we can do 32-bit unsigned int loads. */
2660 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2661 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
2663 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2664 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
2668 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2669 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
2670 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
2671 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = FLOAT_REGS
; /* DImode */
2673 if (TARGET_VSX_TIMODE
)
2674 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
2676 if (TARGET_UPPER_REGS_DF
) /* DFmode */
2678 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2679 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2682 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2685 /* Add conditional constraints based on various options, to allow us to
2686 collapse multiple insn patterns. */
2688 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2690 if (TARGET_MFPGPR
) /* DFmode */
2691 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2694 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
2696 if (TARGET_DIRECT_MOVE
)
2698 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
2699 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
2700 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
2701 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
2702 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
2703 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2706 if (TARGET_POWERPC64
)
2707 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2709 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
) /* SFmode */
2711 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2712 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2713 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2715 else if (TARGET_P8_VECTOR
)
2717 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2718 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2720 else if (TARGET_VSX
)
2721 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2724 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
2727 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
2729 /* Set up the reload helper and direct move functions. */
2730 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2734 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2735 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2736 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2737 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2738 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2739 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2740 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2741 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2742 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
2743 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
2744 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2745 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2746 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2747 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2748 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2750 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2751 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2752 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
2753 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2754 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2756 if (TARGET_P8_VECTOR
)
2758 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2759 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2760 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2761 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2762 if (TARGET_UPPER_REGS_SF
)
2763 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
2765 if (TARGET_VSX_TIMODE
)
2767 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2768 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2770 if (TARGET_DIRECT_MOVE
)
2772 if (TARGET_POWERPC64
)
2774 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2775 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
2776 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2777 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2778 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2779 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2780 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2781 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2782 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2784 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2785 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
2786 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2787 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2788 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2789 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2790 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2791 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2792 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2796 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2797 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2798 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2804 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2805 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2806 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2807 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2808 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2809 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2810 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2811 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2812 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
2813 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
2814 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2815 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2816 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2817 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2818 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2820 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2821 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2822 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
2823 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2824 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2826 if (TARGET_P8_VECTOR
)
2828 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2829 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2830 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2831 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2832 if (TARGET_UPPER_REGS_SF
)
2833 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
2835 if (TARGET_VSX_TIMODE
)
2837 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2838 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2843 /* Precalculate HARD_REGNO_NREGS. */
2844 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2845 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2846 rs6000_hard_regno_nregs
[m
][r
]
2847 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2849 /* Precalculate HARD_REGNO_MODE_OK. */
2850 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2851 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2852 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2853 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2855 /* Precalculate CLASS_MAX_NREGS sizes. */
2856 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2860 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2861 reg_size
= UNITS_PER_VSX_WORD
;
2863 else if (c
== ALTIVEC_REGS
)
2864 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2866 else if (c
== FLOAT_REGS
)
2867 reg_size
= UNITS_PER_FP_WORD
;
2870 reg_size
= UNITS_PER_WORD
;
2872 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2874 enum machine_mode m2
= (enum machine_mode
)m
;
2875 int reg_size2
= reg_size
;
2877 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2878 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2879 && (m
== TDmode
|| m
== TFmode
))
2880 reg_size2
= UNITS_PER_FP_WORD
;
2882 rs6000_class_max_nregs
[m
][c
]
2883 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
2887 if (TARGET_E500_DOUBLE
)
2888 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2890 /* Calculate which modes to automatically generate code to use a the
2891 reciprocal divide and square root instructions. In the future, possibly
2892 automatically generate the instructions even if the user did not specify
2893 -mrecip. The older machines double precision reciprocal sqrt estimate is
2894 not accurate enough. */
2895 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2897 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2899 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2900 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2901 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2902 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2903 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2905 if (TARGET_FRSQRTES
)
2906 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2908 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2909 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2910 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2911 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2912 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2914 if (rs6000_recip_control
)
2916 if (!flag_finite_math_only
)
2917 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2918 if (flag_trapping_math
)
2919 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2920 if (!flag_reciprocal_math
)
2921 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2922 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2924 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2925 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2926 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2928 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2929 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2930 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2932 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2933 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2934 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2936 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2937 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2938 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2940 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2941 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2942 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2944 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2945 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2946 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2948 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2949 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2950 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2952 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2953 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2954 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2958 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2959 legitimate address support to figure out the appropriate addressing to
2961 rs6000_setup_reg_addr_masks ();
2963 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2965 if (TARGET_DEBUG_REG
)
2966 rs6000_debug_reg_global ();
2968 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2970 "SImode variable mult cost = %d\n"
2971 "SImode constant mult cost = %d\n"
2972 "SImode short constant mult cost = %d\n"
2973 "DImode multipliciation cost = %d\n"
2974 "SImode division cost = %d\n"
2975 "DImode division cost = %d\n"
2976 "Simple fp operation cost = %d\n"
2977 "DFmode multiplication cost = %d\n"
2978 "SFmode division cost = %d\n"
2979 "DFmode division cost = %d\n"
2980 "cache line size = %d\n"
2981 "l1 cache size = %d\n"
2982 "l2 cache size = %d\n"
2983 "simultaneous prefetches = %d\n"
2986 rs6000_cost
->mulsi_const
,
2987 rs6000_cost
->mulsi_const9
,
2995 rs6000_cost
->cache_line_size
,
2996 rs6000_cost
->l1_cache_size
,
2997 rs6000_cost
->l2_cache_size
,
2998 rs6000_cost
->simultaneous_prefetches
);
3003 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3006 darwin_rs6000_override_options (void)
3008 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3010 rs6000_altivec_abi
= 1;
3011 TARGET_ALTIVEC_VRSAVE
= 1;
3012 rs6000_current_abi
= ABI_DARWIN
;
3014 if (DEFAULT_ABI
== ABI_DARWIN
3016 darwin_one_byte_bool
= 1;
3018 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3020 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3021 warning (0, "-m64 requires PowerPC64 architecture, enabling");
3025 rs6000_default_long_calls
= 1;
3026 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3029 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3031 if (!flag_mkernel
&& !flag_apple_kext
3033 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3034 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3036 /* Unless the user (not the configurer) has explicitly overridden
3037 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3038 G4 unless targeting the kernel. */
3041 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3042 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3043 && ! global_options_set
.x_rs6000_cpu_index
)
3045 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3050 /* If not otherwise specified by a target, make 'long double' equivalent to
3053 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3054 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3057 /* Return the builtin mask of the various options used that could affect which
3058 builtins were used. In the past we used target_flags, but we've run out of
3059 bits, and some options like SPE and PAIRED are no longer in
3063 rs6000_builtin_mask_calculate (void)
3065 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3066 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3067 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3068 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3069 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3070 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3071 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3072 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3073 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3074 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3075 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3076 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3077 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3078 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3079 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3080 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0));
3083 /* Override command line options. Mostly we process the processor type and
3084 sometimes adjust other TARGET_ options. */
3087 rs6000_option_override_internal (bool global_init_p
)
3090 bool have_cpu
= false;
3092 /* The default cpu requested at configure time, if any. */
3093 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3095 HOST_WIDE_INT set_masks
;
3098 struct cl_target_option
*main_target_opt
3099 = ((global_init_p
|| target_option_default_node
== NULL
)
3100 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3102 /* Remember the explicit arguments. */
3104 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3106 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3107 library functions, so warn about it. The flag may be useful for
3108 performance studies from time to time though, so don't disable it
3110 if (global_options_set
.x_rs6000_alignment_flags
3111 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3112 && DEFAULT_ABI
== ABI_DARWIN
3114 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3115 " it is incompatible with the installed C and C++ libraries");
3117 /* Numerous experiment shows that IRA based loop pressure
3118 calculation works better for RTL loop invariant motion on targets
3119 with enough (>= 32) registers. It is an expensive optimization.
3120 So it is on only for peak performance. */
3121 if (optimize
>= 3 && global_init_p
3122 && !global_options_set
.x_flag_ira_loop_pressure
)
3123 flag_ira_loop_pressure
= 1;
3125 /* Set the pointer size. */
3128 rs6000_pmode
= (int)DImode
;
3129 rs6000_pointer_size
= 64;
3133 rs6000_pmode
= (int)SImode
;
3134 rs6000_pointer_size
= 32;
3137 /* Some OSs don't support saving the high part of 64-bit registers on context
3138 switch. Other OSs don't support saving Altivec registers. On those OSs,
3139 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3140 if the user wants either, the user must explicitly specify them and we
3141 won't interfere with the user's specification. */
3143 set_masks
= POWERPC_MASKS
;
3144 #ifdef OS_MISSING_POWERPC64
3145 if (OS_MISSING_POWERPC64
)
3146 set_masks
&= ~OPTION_MASK_POWERPC64
;
3148 #ifdef OS_MISSING_ALTIVEC
3149 if (OS_MISSING_ALTIVEC
)
3150 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3153 /* Don't override by the processor default if given explicitly. */
3154 set_masks
&= ~rs6000_isa_flags_explicit
;
3156 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3157 the cpu in a target attribute or pragma, but did not specify a tuning
3158 option, use the cpu for the tuning option rather than the option specified
3159 with -mtune on the command line. Process a '--with-cpu' configuration
3160 request as an implicit --cpu. */
3161 if (rs6000_cpu_index
>= 0)
3163 cpu_index
= rs6000_cpu_index
;
3166 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3168 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3171 else if (implicit_cpu
)
3173 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3178 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3179 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3183 gcc_assert (cpu_index
>= 0);
3185 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3186 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3187 with those from the cpu, except for options that were explicitly set. If
3188 we don't have a cpu, do not override the target bits set in
3192 rs6000_isa_flags
&= ~set_masks
;
3193 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3197 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3198 & ~rs6000_isa_flags_explicit
);
3200 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3201 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3202 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3203 to using rs6000_isa_flags, we need to do the initialization here. */
3205 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3207 if (rs6000_tune_index
>= 0)
3208 tune_index
= rs6000_tune_index
;
3210 rs6000_tune_index
= tune_index
= cpu_index
;
3214 enum processor_type tune_proc
3215 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3218 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3219 if (processor_target_table
[i
].processor
== tune_proc
)
3221 rs6000_tune_index
= tune_index
= i
;
3226 gcc_assert (tune_index
>= 0);
3227 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3229 /* Pick defaults for SPE related control flags. Do this early to make sure
3230 that the TARGET_ macros are representative ASAP. */
3232 int spe_capable_cpu
=
3233 (rs6000_cpu
== PROCESSOR_PPC8540
3234 || rs6000_cpu
== PROCESSOR_PPC8548
);
3236 if (!global_options_set
.x_rs6000_spe_abi
)
3237 rs6000_spe_abi
= spe_capable_cpu
;
3239 if (!global_options_set
.x_rs6000_spe
)
3240 rs6000_spe
= spe_capable_cpu
;
3242 if (!global_options_set
.x_rs6000_float_gprs
)
3244 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3245 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3249 if (global_options_set
.x_rs6000_spe_abi
3252 error ("not configured for SPE ABI");
3254 if (global_options_set
.x_rs6000_spe
3257 error ("not configured for SPE instruction set");
3259 if (main_target_opt
!= NULL
3260 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3261 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3262 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3263 error ("target attribute or pragma changes SPE ABI");
3265 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3266 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3267 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3270 error ("AltiVec not supported in this target");
3272 error ("SPE not supported in this target");
3274 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3277 error ("SPE not supported in this target");
3280 /* Disable Cell microcode if we are optimizing for the Cell
3281 and not optimizing for size. */
3282 if (rs6000_gen_cell_microcode
== -1)
3283 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3286 /* If we are optimizing big endian systems for space and it's OK to
3287 use instructions that would be microcoded on the Cell, use the
3288 load/store multiple and string instructions. */
3289 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3290 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3291 | OPTION_MASK_STRING
);
3293 /* Don't allow -mmultiple or -mstring on little endian systems
3294 unless the cpu is a 750, because the hardware doesn't support the
3295 instructions used in little endian mode, and causes an alignment
3296 trap. The 750 does not cause an alignment trap (except when the
3297 target is unaligned). */
3299 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3301 if (TARGET_MULTIPLE
)
3303 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3304 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3305 warning (0, "-mmultiple is not supported on little endian systems");
3310 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3311 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3312 warning (0, "-mstring is not supported on little endian systems");
3316 /* If little-endian, default to -mstrict-align on older processors.
3317 Testing for htm matches power8 and later. */
3318 if (!BYTES_BIG_ENDIAN
3319 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3320 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3322 /* -maltivec={le,be} implies -maltivec. */
3323 if (rs6000_altivec_element_order
!= 0)
3324 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3326 /* Disallow -maltivec=le in big endian mode for now. This is not
3327 known to be useful for anyone. */
3328 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3330 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3331 rs6000_altivec_element_order
= 0;
3334 /* Add some warnings for VSX. */
3337 const char *msg
= NULL
;
3338 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3339 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3341 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3342 msg
= N_("-mvsx requires hardware floating point");
3345 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3346 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3349 else if (TARGET_PAIRED_FLOAT
)
3350 msg
= N_("-mvsx and -mpaired are incompatible");
3351 else if (TARGET_AVOID_XFORM
> 0)
3352 msg
= N_("-mvsx needs indexed addressing");
3353 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3354 & OPTION_MASK_ALTIVEC
))
3356 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3357 msg
= N_("-mvsx and -mno-altivec are incompatible");
3359 msg
= N_("-mno-altivec disables vsx");
3365 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3366 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3370 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3371 the -mcpu setting to enable options that conflict. */
3372 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3373 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3374 | OPTION_MASK_ALTIVEC
3375 | OPTION_MASK_VSX
)) != 0)
3376 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3377 | OPTION_MASK_DIRECT_MOVE
)
3378 & ~rs6000_isa_flags_explicit
);
3380 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3381 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3383 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3384 unless the user explicitly used the -mno-<option> to disable the code. */
3385 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3386 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3387 else if (TARGET_VSX
)
3388 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3389 else if (TARGET_POPCNTD
)
3390 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3391 else if (TARGET_DFP
)
3392 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3393 else if (TARGET_CMPB
)
3394 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3395 else if (TARGET_FPRND
)
3396 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3397 else if (TARGET_POPCNTB
)
3398 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3399 else if (TARGET_ALTIVEC
)
3400 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3402 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3404 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3405 error ("-mcrypto requires -maltivec");
3406 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3409 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3411 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3412 error ("-mdirect-move requires -mvsx");
3413 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3416 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3418 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3419 error ("-mpower8-vector requires -maltivec");
3420 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3423 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3425 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3426 error ("-mpower8-vector requires -mvsx");
3427 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3430 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3432 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3433 error ("-mvsx-timode requires -mvsx");
3434 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3437 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
3439 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
3440 error ("-mhard-dfp requires -mhard-float");
3441 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
3444 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3445 silently turn off quad memory mode. */
3446 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3448 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3449 warning (0, N_("-mquad-memory requires 64-bit mode"));
3451 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3452 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3454 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3455 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3458 /* Non-atomic quad memory load/store are disabled for little endian, since
3459 the words are reversed, but atomic operations can still be done by
3460 swapping the words. */
3461 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
3463 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3464 warning (0, N_("-mquad-memory is not available in little endian mode"));
3466 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3469 /* Assume if the user asked for normal quad memory instructions, they want
3470 the atomic versions as well, unless they explicity told us not to use quad
3471 word atomic instructions. */
3472 if (TARGET_QUAD_MEMORY
3473 && !TARGET_QUAD_MEMORY_ATOMIC
3474 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
3475 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
3477 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3478 generating power8 instructions. */
3479 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3480 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3481 & OPTION_MASK_P8_FUSION
);
3483 /* Power8 does not fuse sign extended loads with the addis. If we are
3484 optimizing at high levels for speed, convert a sign extended load into a
3485 zero extending load, and an explicit sign extension. */
3486 if (TARGET_P8_FUSION
3487 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3488 && optimize_function_for_speed_p (cfun
)
3490 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3492 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3493 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3495 /* E500mc does "better" if we inline more aggressively. Respect the
3496 user's opinion, though. */
3497 if (rs6000_block_move_inline_limit
== 0
3498 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3499 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3500 || rs6000_cpu
== PROCESSOR_PPCE5500
3501 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3502 rs6000_block_move_inline_limit
= 128;
3504 /* store_one_arg depends on expand_block_move to handle at least the
3505 size of reg_parm_stack_space. */
3506 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3507 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3511 /* If the appropriate debug option is enabled, replace the target hooks
3512 with debug versions that call the real version and then prints
3513 debugging information. */
3514 if (TARGET_DEBUG_COST
)
3516 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3517 targetm
.address_cost
= rs6000_debug_address_cost
;
3518 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3521 if (TARGET_DEBUG_ADDR
)
3523 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3524 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3525 rs6000_secondary_reload_class_ptr
3526 = rs6000_debug_secondary_reload_class
;
3527 rs6000_secondary_memory_needed_ptr
3528 = rs6000_debug_secondary_memory_needed
;
3529 rs6000_cannot_change_mode_class_ptr
3530 = rs6000_debug_cannot_change_mode_class
;
3531 rs6000_preferred_reload_class_ptr
3532 = rs6000_debug_preferred_reload_class
;
3533 rs6000_legitimize_reload_address_ptr
3534 = rs6000_debug_legitimize_reload_address
;
3535 rs6000_mode_dependent_address_ptr
3536 = rs6000_debug_mode_dependent_address
;
3539 if (rs6000_veclibabi_name
)
3541 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3542 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3545 error ("unknown vectorization library ABI type (%s) for "
3546 "-mveclibabi= switch", rs6000_veclibabi_name
);
3552 if (!global_options_set
.x_rs6000_long_double_type_size
)
3554 if (main_target_opt
!= NULL
3555 && (main_target_opt
->x_rs6000_long_double_type_size
3556 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3557 error ("target attribute or pragma changes long double size");
3559 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3562 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3563 if (!global_options_set
.x_rs6000_ieeequad
)
3564 rs6000_ieeequad
= 1;
3567 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3568 target attribute or pragma which automatically enables both options,
3569 unless the altivec ABI was set. This is set by default for 64-bit, but
3571 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3572 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3573 & ~rs6000_isa_flags_explicit
);
3575 /* Enable Altivec ABI for AIX -maltivec. */
3576 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3578 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3579 error ("target attribute or pragma changes AltiVec ABI");
3581 rs6000_altivec_abi
= 1;
3584 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3585 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3586 be explicitly overridden in either case. */
3589 if (!global_options_set
.x_rs6000_altivec_abi
3590 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3592 if (main_target_opt
!= NULL
&&
3593 !main_target_opt
->x_rs6000_altivec_abi
)
3594 error ("target attribute or pragma changes AltiVec ABI");
3596 rs6000_altivec_abi
= 1;
3600 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3601 So far, the only darwin64 targets are also MACH-O. */
3603 && DEFAULT_ABI
== ABI_DARWIN
3606 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3607 error ("target attribute or pragma changes darwin64 ABI");
3610 rs6000_darwin64_abi
= 1;
3611 /* Default to natural alignment, for better performance. */
3612 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3616 /* Place FP constants in the constant pool instead of TOC
3617 if section anchors enabled. */
3618 if (flag_section_anchors
3619 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3620 TARGET_NO_FP_IN_TOC
= 1;
3622 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3623 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3625 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3626 SUBTARGET_OVERRIDE_OPTIONS
;
3628 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3629 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3631 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3632 SUB3TARGET_OVERRIDE_OPTIONS
;
3635 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3636 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3638 /* For the E500 family of cores, reset the single/double FP flags to let us
3639 check that they remain constant across attributes or pragmas. Also,
3640 clear a possible request for string instructions, not supported and which
3641 we might have silently queried above for -Os.
3643 For other families, clear ISEL in case it was set implicitly.
3648 case PROCESSOR_PPC8540
:
3649 case PROCESSOR_PPC8548
:
3650 case PROCESSOR_PPCE500MC
:
3651 case PROCESSOR_PPCE500MC64
:
3652 case PROCESSOR_PPCE5500
:
3653 case PROCESSOR_PPCE6500
:
3655 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3656 rs6000_double_float
= TARGET_E500_DOUBLE
;
3658 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3664 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3665 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3670 if (main_target_opt
)
3672 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3673 error ("target attribute or pragma changes single precision floating "
3675 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3676 error ("target attribute or pragma changes double precision floating "
3680 /* Detect invalid option combinations with E500. */
3683 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3684 && rs6000_cpu
!= PROCESSOR_POWER5
3685 && rs6000_cpu
!= PROCESSOR_POWER6
3686 && rs6000_cpu
!= PROCESSOR_POWER7
3687 && rs6000_cpu
!= PROCESSOR_POWER8
3688 && rs6000_cpu
!= PROCESSOR_PPCA2
3689 && rs6000_cpu
!= PROCESSOR_CELL
3690 && rs6000_cpu
!= PROCESSOR_PPC476
);
3691 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3692 || rs6000_cpu
== PROCESSOR_POWER5
3693 || rs6000_cpu
== PROCESSOR_POWER7
3694 || rs6000_cpu
== PROCESSOR_POWER8
);
3695 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3696 || rs6000_cpu
== PROCESSOR_POWER5
3697 || rs6000_cpu
== PROCESSOR_POWER6
3698 || rs6000_cpu
== PROCESSOR_POWER7
3699 || rs6000_cpu
== PROCESSOR_POWER8
3700 || rs6000_cpu
== PROCESSOR_PPCE500MC
3701 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3702 || rs6000_cpu
== PROCESSOR_PPCE5500
3703 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3705 /* Allow debug switches to override the above settings. These are set to -1
3706 in rs6000.opt to indicate the user hasn't directly set the switch. */
3707 if (TARGET_ALWAYS_HINT
>= 0)
3708 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3710 if (TARGET_SCHED_GROUPS
>= 0)
3711 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3713 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3714 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3716 rs6000_sched_restricted_insns_priority
3717 = (rs6000_sched_groups
? 1 : 0);
3719 /* Handle -msched-costly-dep option. */
3720 rs6000_sched_costly_dep
3721 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3723 if (rs6000_sched_costly_dep_str
)
3725 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3726 rs6000_sched_costly_dep
= no_dep_costly
;
3727 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3728 rs6000_sched_costly_dep
= all_deps_costly
;
3729 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3730 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3731 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3732 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3734 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3735 atoi (rs6000_sched_costly_dep_str
));
3738 /* Handle -minsert-sched-nops option. */
3739 rs6000_sched_insert_nops
3740 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3742 if (rs6000_sched_insert_nops_str
)
3744 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3745 rs6000_sched_insert_nops
= sched_finish_none
;
3746 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3747 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3748 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3749 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3751 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3752 atoi (rs6000_sched_insert_nops_str
));
3757 #ifdef TARGET_REGNAMES
3758 /* If the user desires alternate register names, copy in the
3759 alternate names now. */
3760 if (TARGET_REGNAMES
)
3761 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3764 /* Set aix_struct_return last, after the ABI is determined.
3765 If -maix-struct-return or -msvr4-struct-return was explicitly
3766 used, don't override with the ABI default. */
3767 if (!global_options_set
.x_aix_struct_return
)
3768 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3771 /* IBM XL compiler defaults to unsigned bitfields. */
3772 if (TARGET_XL_COMPAT
)
3773 flag_signed_bitfields
= 0;
3776 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3777 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3780 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3782 /* We can only guarantee the availability of DI pseudo-ops when
3783 assembling for 64-bit targets. */
3786 targetm
.asm_out
.aligned_op
.di
= NULL
;
3787 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3791 /* Set branch target alignment, if not optimizing for size. */
3794 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3795 aligned 8byte to avoid misprediction by the branch predictor. */
3796 if (rs6000_cpu
== PROCESSOR_TITAN
3797 || rs6000_cpu
== PROCESSOR_CELL
)
3799 if (align_functions
<= 0)
3800 align_functions
= 8;
3801 if (align_jumps
<= 0)
3803 if (align_loops
<= 0)
3806 if (rs6000_align_branch_targets
)
3808 if (align_functions
<= 0)
3809 align_functions
= 16;
3810 if (align_jumps
<= 0)
3812 if (align_loops
<= 0)
3814 can_override_loop_align
= 1;
3818 if (align_jumps_max_skip
<= 0)
3819 align_jumps_max_skip
= 15;
3820 if (align_loops_max_skip
<= 0)
3821 align_loops_max_skip
= 15;
3824 /* Arrange to save and restore machine status around nested functions. */
3825 init_machine_status
= rs6000_init_machine_status
;
3827 /* We should always be splitting complex arguments, but we can't break
3828 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3829 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3830 targetm
.calls
.split_complex_arg
= NULL
;
3833 /* Initialize rs6000_cost with the appropriate target costs. */
3835 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3839 case PROCESSOR_RS64A
:
3840 rs6000_cost
= &rs64a_cost
;
3843 case PROCESSOR_MPCCORE
:
3844 rs6000_cost
= &mpccore_cost
;
3847 case PROCESSOR_PPC403
:
3848 rs6000_cost
= &ppc403_cost
;
3851 case PROCESSOR_PPC405
:
3852 rs6000_cost
= &ppc405_cost
;
3855 case PROCESSOR_PPC440
:
3856 rs6000_cost
= &ppc440_cost
;
3859 case PROCESSOR_PPC476
:
3860 rs6000_cost
= &ppc476_cost
;
3863 case PROCESSOR_PPC601
:
3864 rs6000_cost
= &ppc601_cost
;
3867 case PROCESSOR_PPC603
:
3868 rs6000_cost
= &ppc603_cost
;
3871 case PROCESSOR_PPC604
:
3872 rs6000_cost
= &ppc604_cost
;
3875 case PROCESSOR_PPC604e
:
3876 rs6000_cost
= &ppc604e_cost
;
3879 case PROCESSOR_PPC620
:
3880 rs6000_cost
= &ppc620_cost
;
3883 case PROCESSOR_PPC630
:
3884 rs6000_cost
= &ppc630_cost
;
3887 case PROCESSOR_CELL
:
3888 rs6000_cost
= &ppccell_cost
;
3891 case PROCESSOR_PPC750
:
3892 case PROCESSOR_PPC7400
:
3893 rs6000_cost
= &ppc750_cost
;
3896 case PROCESSOR_PPC7450
:
3897 rs6000_cost
= &ppc7450_cost
;
3900 case PROCESSOR_PPC8540
:
3901 case PROCESSOR_PPC8548
:
3902 rs6000_cost
= &ppc8540_cost
;
3905 case PROCESSOR_PPCE300C2
:
3906 case PROCESSOR_PPCE300C3
:
3907 rs6000_cost
= &ppce300c2c3_cost
;
3910 case PROCESSOR_PPCE500MC
:
3911 rs6000_cost
= &ppce500mc_cost
;
3914 case PROCESSOR_PPCE500MC64
:
3915 rs6000_cost
= &ppce500mc64_cost
;
3918 case PROCESSOR_PPCE5500
:
3919 rs6000_cost
= &ppce5500_cost
;
3922 case PROCESSOR_PPCE6500
:
3923 rs6000_cost
= &ppce6500_cost
;
3926 case PROCESSOR_TITAN
:
3927 rs6000_cost
= &titan_cost
;
3930 case PROCESSOR_POWER4
:
3931 case PROCESSOR_POWER5
:
3932 rs6000_cost
= &power4_cost
;
3935 case PROCESSOR_POWER6
:
3936 rs6000_cost
= &power6_cost
;
3939 case PROCESSOR_POWER7
:
3940 rs6000_cost
= &power7_cost
;
3943 case PROCESSOR_POWER8
:
3944 rs6000_cost
= &power8_cost
;
3947 case PROCESSOR_PPCA2
:
3948 rs6000_cost
= &ppca2_cost
;
3957 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3958 rs6000_cost
->simultaneous_prefetches
,
3959 global_options
.x_param_values
,
3960 global_options_set
.x_param_values
);
3961 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3962 global_options
.x_param_values
,
3963 global_options_set
.x_param_values
);
3964 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3965 rs6000_cost
->cache_line_size
,
3966 global_options
.x_param_values
,
3967 global_options_set
.x_param_values
);
3968 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3969 global_options
.x_param_values
,
3970 global_options_set
.x_param_values
);
3972 /* Increase loop peeling limits based on performance analysis. */
3973 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3974 global_options
.x_param_values
,
3975 global_options_set
.x_param_values
);
3976 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3977 global_options
.x_param_values
,
3978 global_options_set
.x_param_values
);
3980 /* If using typedef char *va_list, signal that
3981 __builtin_va_start (&ap, 0) can be optimized to
3982 ap = __builtin_next_arg (0). */
3983 if (DEFAULT_ABI
!= ABI_V4
)
3984 targetm
.expand_builtin_va_start
= NULL
;
3987 /* Set up single/double float flags.
3988 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3989 then set both flags. */
3990 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3991 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3992 rs6000_single_float
= rs6000_double_float
= 1;
3994 /* If not explicitly specified via option, decide whether to generate indexed
3995 load/store instructions. */
3996 if (TARGET_AVOID_XFORM
== -1)
3997 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3998 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3999 need indexed accesses and the type used is the scalar type of the element
4000 being loaded or stored. */
4001 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
4002 && !TARGET_ALTIVEC
);
4004 /* Set the -mrecip options. */
4005 if (rs6000_recip_name
)
4007 char *p
= ASTRDUP (rs6000_recip_name
);
4009 unsigned int mask
, i
;
4012 while ((q
= strtok (p
, ",")) != NULL
)
4023 if (!strcmp (q
, "default"))
4024 mask
= ((TARGET_RECIP_PRECISION
)
4025 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4028 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4029 if (!strcmp (q
, recip_options
[i
].string
))
4031 mask
= recip_options
[i
].mask
;
4035 if (i
== ARRAY_SIZE (recip_options
))
4037 error ("unknown option for -mrecip=%s", q
);
4045 rs6000_recip_control
&= ~mask
;
4047 rs6000_recip_control
|= mask
;
4051 /* Set the builtin mask of the various options used that could affect which
4052 builtins were used. In the past we used target_flags, but we've run out
4053 of bits, and some options like SPE and PAIRED are no longer in
4055 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4056 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4059 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
4060 rs6000_builtin_mask
);
4061 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
4064 /* Initialize all of the registers. */
4065 rs6000_init_hard_regno_mode_ok (global_init_p
);
4067 /* Save the initial options in case the user does function specific options */
4069 target_option_default_node
= target_option_current_node
4070 = build_target_option_node (&global_options
);
4072 /* If not explicitly specified via option, decide whether to generate the
4073 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4074 if (TARGET_LINK_STACK
== -1)
4075 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4080 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4081 define the target cpu type. */
4084 rs6000_option_override (void)
4086 (void) rs6000_option_override_internal (true);
4088 /* Register machine-specific passes. This needs to be done at start-up.
4089 It's convenient to do it here (like i386 does). */
4090 opt_pass
*pass_analyze_swaps
= make_pass_analyze_swaps (g
);
4092 static struct register_pass_info analyze_swaps_info
4093 = { pass_analyze_swaps
, "cse1", 1, PASS_POS_INSERT_BEFORE
};
4095 register_pass (&analyze_swaps_info
);
4099 /* Implement targetm.vectorize.builtin_mask_for_load. */
4101 rs6000_builtin_mask_for_load (void)
4103 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4104 return altivec_builtin_mask_for_load
;
4109 /* Implement LOOP_ALIGN. */
4111 rs6000_loop_align (rtx label
)
4116 /* Don't override loop alignment if -falign-loops was specified. */
4117 if (!can_override_loop_align
)
4118 return align_loops_log
;
4120 bb
= BLOCK_FOR_INSN (label
);
4121 ninsns
= num_loop_insns(bb
->loop_father
);
4123 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4124 if (ninsns
> 4 && ninsns
<= 8
4125 && (rs6000_cpu
== PROCESSOR_POWER4
4126 || rs6000_cpu
== PROCESSOR_POWER5
4127 || rs6000_cpu
== PROCESSOR_POWER6
4128 || rs6000_cpu
== PROCESSOR_POWER7
4129 || rs6000_cpu
== PROCESSOR_POWER8
))
4132 return align_loops_log
;
4135 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4137 rs6000_loop_align_max_skip (rtx_insn
*label
)
4139 return (1 << rs6000_loop_align (label
)) - 1;
4142 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4143 after applying N number of iterations. This routine does not determine
4144 how may iterations are required to reach desired alignment. */
4147 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4154 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4157 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4167 /* Assuming that all other types are naturally aligned. CHECKME! */
4172 /* Return true if the vector misalignment factor is supported by the
4175 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4182 /* Return if movmisalign pattern is not supported for this mode. */
4183 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4186 if (misalignment
== -1)
4188 /* Misalignment factor is unknown at compile time but we know
4189 it's word aligned. */
4190 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4192 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4194 if (element_size
== 64 || element_size
== 32)
4201 /* VSX supports word-aligned vector. */
4202 if (misalignment
% 4 == 0)
4208 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4210 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4211 tree vectype
, int misalign
)
4216 switch (type_of_cost
)
4226 case cond_branch_not_taken
:
4235 case vec_promote_demote
:
4241 case cond_branch_taken
:
4244 case unaligned_load
:
4245 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4247 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4249 /* Double word aligned. */
4257 /* Double word aligned. */
4261 /* Unknown misalignment. */
4274 /* Misaligned loads are not supported. */
4279 case unaligned_store
:
4280 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4282 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4284 /* Double word aligned. */
4292 /* Double word aligned. */
4296 /* Unknown misalignment. */
4309 /* Misaligned stores are not supported. */
4315 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4316 elem_type
= TREE_TYPE (vectype
);
4317 /* 32-bit vectors loaded into registers are stored as double
4318 precision, so we need n/2 converts in addition to the usual
4319 n/2 merges to construct a vector of short floats from them. */
4320 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4321 && TYPE_PRECISION (elem_type
) == 32)
4322 return elements
+ 1;
4324 return elements
/ 2 + 1;
4331 /* Implement targetm.vectorize.preferred_simd_mode. */
4333 static enum machine_mode
4334 rs6000_preferred_simd_mode (enum machine_mode mode
)
4343 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4369 if (TARGET_PAIRED_FLOAT
4375 typedef struct _rs6000_cost_data
4377 struct loop
*loop_info
;
4381 /* Test for likely overcommitment of vector hardware resources. If a
4382 loop iteration is relatively large, and too large a percentage of
4383 instructions in the loop are vectorized, the cost model may not
4384 adequately reflect delays from unavailable vector resources.
4385 Penalize the loop body cost for this case. */
4388 rs6000_density_test (rs6000_cost_data
*data
)
4390 const int DENSITY_PCT_THRESHOLD
= 85;
4391 const int DENSITY_SIZE_THRESHOLD
= 70;
4392 const int DENSITY_PENALTY
= 10;
4393 struct loop
*loop
= data
->loop_info
;
4394 basic_block
*bbs
= get_loop_body (loop
);
4395 int nbbs
= loop
->num_nodes
;
4396 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4399 for (i
= 0; i
< nbbs
; i
++)
4401 basic_block bb
= bbs
[i
];
4402 gimple_stmt_iterator gsi
;
4404 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4406 gimple stmt
= gsi_stmt (gsi
);
4407 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4409 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4410 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4416 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4418 if (density_pct
> DENSITY_PCT_THRESHOLD
4419 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4421 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4422 if (dump_enabled_p ())
4423 dump_printf_loc (MSG_NOTE
, vect_location
,
4424 "density %d%%, cost %d exceeds threshold, penalizing "
4425 "loop body cost by %d%%", density_pct
,
4426 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4430 /* Implement targetm.vectorize.init_cost. */
4433 rs6000_init_cost (struct loop
*loop_info
)
4435 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4436 data
->loop_info
= loop_info
;
4437 data
->cost
[vect_prologue
] = 0;
4438 data
->cost
[vect_body
] = 0;
4439 data
->cost
[vect_epilogue
] = 0;
4443 /* Implement targetm.vectorize.add_stmt_cost. */
4446 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4447 struct _stmt_vec_info
*stmt_info
, int misalign
,
4448 enum vect_cost_model_location where
)
4450 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4451 unsigned retval
= 0;
4453 if (flag_vect_cost_model
)
4455 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4456 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4458 /* Statements in an inner loop relative to the loop being
4459 vectorized are weighted more heavily. The value here is
4460 arbitrary and could potentially be improved with analysis. */
4461 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4462 count
*= 50; /* FIXME. */
4464 retval
= (unsigned) (count
* stmt_cost
);
4465 cost_data
->cost
[where
] += retval
;
4471 /* Implement targetm.vectorize.finish_cost. */
4474 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4475 unsigned *body_cost
, unsigned *epilogue_cost
)
4477 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4479 if (cost_data
->loop_info
)
4480 rs6000_density_test (cost_data
);
4482 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4483 *body_cost
= cost_data
->cost
[vect_body
];
4484 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4487 /* Implement targetm.vectorize.destroy_cost_data. */
4490 rs6000_destroy_cost_data (void *data
)
4495 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4496 library with vectorized intrinsics. */
4499 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4502 const char *suffix
= NULL
;
4503 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4506 enum machine_mode el_mode
, in_mode
;
4509 /* Libmass is suitable for unsafe math only as it does not correctly support
4510 parts of IEEE with the required precision such as denormals. Only support
4511 it if we have VSX to use the simd d2 or f4 functions.
4512 XXX: Add variable length support. */
4513 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4516 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4517 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4518 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4519 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4520 if (el_mode
!= in_mode
4524 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4526 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4529 case BUILT_IN_ATAN2
:
4530 case BUILT_IN_HYPOT
:
4536 case BUILT_IN_ACOSH
:
4538 case BUILT_IN_ASINH
:
4540 case BUILT_IN_ATANH
:
4548 case BUILT_IN_EXPM1
:
4549 case BUILT_IN_LGAMMA
:
4550 case BUILT_IN_LOG10
:
4551 case BUILT_IN_LOG1P
:
4559 bdecl
= builtin_decl_implicit (fn
);
4560 suffix
= "d2"; /* pow -> powd2 */
4561 if (el_mode
!= DFmode
4567 case BUILT_IN_ATAN2F
:
4568 case BUILT_IN_HYPOTF
:
4573 case BUILT_IN_ACOSF
:
4574 case BUILT_IN_ACOSHF
:
4575 case BUILT_IN_ASINF
:
4576 case BUILT_IN_ASINHF
:
4577 case BUILT_IN_ATANF
:
4578 case BUILT_IN_ATANHF
:
4579 case BUILT_IN_CBRTF
:
4581 case BUILT_IN_COSHF
:
4583 case BUILT_IN_ERFCF
:
4584 case BUILT_IN_EXP2F
:
4586 case BUILT_IN_EXPM1F
:
4587 case BUILT_IN_LGAMMAF
:
4588 case BUILT_IN_LOG10F
:
4589 case BUILT_IN_LOG1PF
:
4590 case BUILT_IN_LOG2F
:
4593 case BUILT_IN_SINHF
:
4594 case BUILT_IN_SQRTF
:
4596 case BUILT_IN_TANHF
:
4597 bdecl
= builtin_decl_implicit (fn
);
4598 suffix
= "4"; /* powf -> powf4 */
4599 if (el_mode
!= SFmode
4612 gcc_assert (suffix
!= NULL
);
4613 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4617 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4618 strcat (name
, suffix
);
4621 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4622 else if (n_args
== 2)
4623 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4627 /* Build a function declaration for the vectorized function. */
4628 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4629 FUNCTION_DECL
, get_identifier (name
), fntype
);
4630 TREE_PUBLIC (new_fndecl
) = 1;
4631 DECL_EXTERNAL (new_fndecl
) = 1;
4632 DECL_IS_NOVOPS (new_fndecl
) = 1;
4633 TREE_READONLY (new_fndecl
) = 1;
4638 /* Returns a function decl for a vectorized version of the builtin function
4639 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4640 if it is not available. */
4643 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4646 enum machine_mode in_mode
, out_mode
;
4649 if (TARGET_DEBUG_BUILTIN
)
4650 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4651 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4652 GET_MODE_NAME (TYPE_MODE (type_out
)),
4653 GET_MODE_NAME (TYPE_MODE (type_in
)));
4655 if (TREE_CODE (type_out
) != VECTOR_TYPE
4656 || TREE_CODE (type_in
) != VECTOR_TYPE
4657 || !TARGET_VECTORIZE_BUILTINS
)
4660 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4661 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4662 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4663 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4665 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4667 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4670 case BUILT_IN_CLZIMAX
:
4671 case BUILT_IN_CLZLL
:
4674 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4676 if (out_mode
== QImode
&& out_n
== 16)
4677 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4678 else if (out_mode
== HImode
&& out_n
== 8)
4679 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4680 else if (out_mode
== SImode
&& out_n
== 4)
4681 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4682 else if (out_mode
== DImode
&& out_n
== 2)
4683 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4686 case BUILT_IN_COPYSIGN
:
4687 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4688 && out_mode
== DFmode
&& out_n
== 2
4689 && in_mode
== DFmode
&& in_n
== 2)
4690 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4692 case BUILT_IN_COPYSIGNF
:
4693 if (out_mode
!= SFmode
|| out_n
!= 4
4694 || in_mode
!= SFmode
|| in_n
!= 4)
4696 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4697 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4698 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4699 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4701 case BUILT_IN_POPCOUNTIMAX
:
4702 case BUILT_IN_POPCOUNTLL
:
4703 case BUILT_IN_POPCOUNTL
:
4704 case BUILT_IN_POPCOUNT
:
4705 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4707 if (out_mode
== QImode
&& out_n
== 16)
4708 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4709 else if (out_mode
== HImode
&& out_n
== 8)
4710 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4711 else if (out_mode
== SImode
&& out_n
== 4)
4712 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4713 else if (out_mode
== DImode
&& out_n
== 2)
4714 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4718 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4719 && out_mode
== DFmode
&& out_n
== 2
4720 && in_mode
== DFmode
&& in_n
== 2)
4721 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4723 case BUILT_IN_SQRTF
:
4724 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4725 && out_mode
== SFmode
&& out_n
== 4
4726 && in_mode
== SFmode
&& in_n
== 4)
4727 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4730 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4731 && out_mode
== DFmode
&& out_n
== 2
4732 && in_mode
== DFmode
&& in_n
== 2)
4733 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4735 case BUILT_IN_CEILF
:
4736 if (out_mode
!= SFmode
|| out_n
!= 4
4737 || in_mode
!= SFmode
|| in_n
!= 4)
4739 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4740 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4741 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4742 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4744 case BUILT_IN_FLOOR
:
4745 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4746 && out_mode
== DFmode
&& out_n
== 2
4747 && in_mode
== DFmode
&& in_n
== 2)
4748 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4750 case BUILT_IN_FLOORF
:
4751 if (out_mode
!= SFmode
|| out_n
!= 4
4752 || in_mode
!= SFmode
|| in_n
!= 4)
4754 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4755 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4756 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4757 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4760 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4761 && out_mode
== DFmode
&& out_n
== 2
4762 && in_mode
== DFmode
&& in_n
== 2)
4763 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4766 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4767 && out_mode
== SFmode
&& out_n
== 4
4768 && in_mode
== SFmode
&& in_n
== 4)
4769 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4770 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4771 && out_mode
== SFmode
&& out_n
== 4
4772 && in_mode
== SFmode
&& in_n
== 4)
4773 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4775 case BUILT_IN_TRUNC
:
4776 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4777 && out_mode
== DFmode
&& out_n
== 2
4778 && in_mode
== DFmode
&& in_n
== 2)
4779 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4781 case BUILT_IN_TRUNCF
:
4782 if (out_mode
!= SFmode
|| out_n
!= 4
4783 || in_mode
!= SFmode
|| in_n
!= 4)
4785 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4786 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4787 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4788 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4790 case BUILT_IN_NEARBYINT
:
4791 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4792 && flag_unsafe_math_optimizations
4793 && out_mode
== DFmode
&& out_n
== 2
4794 && in_mode
== DFmode
&& in_n
== 2)
4795 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4797 case BUILT_IN_NEARBYINTF
:
4798 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4799 && flag_unsafe_math_optimizations
4800 && out_mode
== SFmode
&& out_n
== 4
4801 && in_mode
== SFmode
&& in_n
== 4)
4802 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4805 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4806 && !flag_trapping_math
4807 && out_mode
== DFmode
&& out_n
== 2
4808 && in_mode
== DFmode
&& in_n
== 2)
4809 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4811 case BUILT_IN_RINTF
:
4812 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4813 && !flag_trapping_math
4814 && out_mode
== SFmode
&& out_n
== 4
4815 && in_mode
== SFmode
&& in_n
== 4)
4816 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4823 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4825 enum rs6000_builtins fn
4826 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4829 case RS6000_BUILTIN_RSQRTF
:
4830 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4831 && out_mode
== SFmode
&& out_n
== 4
4832 && in_mode
== SFmode
&& in_n
== 4)
4833 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4835 case RS6000_BUILTIN_RSQRT
:
4836 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4837 && out_mode
== DFmode
&& out_n
== 2
4838 && in_mode
== DFmode
&& in_n
== 2)
4839 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4841 case RS6000_BUILTIN_RECIPF
:
4842 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4843 && out_mode
== SFmode
&& out_n
== 4
4844 && in_mode
== SFmode
&& in_n
== 4)
4845 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4847 case RS6000_BUILTIN_RECIP
:
4848 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4849 && out_mode
== DFmode
&& out_n
== 2
4850 && in_mode
== DFmode
&& in_n
== 2)
4851 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4858 /* Generate calls to libmass if appropriate. */
4859 if (rs6000_veclib_handler
)
4860 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4865 /* Default CPU string for rs6000*_file_start functions. */
4866 static const char *rs6000_default_cpu
;
4868 /* Do anything needed at the start of the asm file. */
4871 rs6000_file_start (void)
4874 const char *start
= buffer
;
4875 FILE *file
= asm_out_file
;
4877 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4879 default_file_start ();
4881 if (flag_verbose_asm
)
4883 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4885 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4887 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4891 if (global_options_set
.x_rs6000_cpu_index
)
4893 fprintf (file
, "%s -mcpu=%s", start
,
4894 processor_target_table
[rs6000_cpu_index
].name
);
4898 if (global_options_set
.x_rs6000_tune_index
)
4900 fprintf (file
, "%s -mtune=%s", start
,
4901 processor_target_table
[rs6000_tune_index
].name
);
4905 if (PPC405_ERRATUM77
)
4907 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4911 #ifdef USING_ELFOS_H
4912 switch (rs6000_sdata
)
4914 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4915 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4916 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4917 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4920 if (rs6000_sdata
&& g_switch_value
)
4922 fprintf (file
, "%s -G %d", start
,
4932 if (DEFAULT_ABI
== ABI_ELFv2
)
4933 fprintf (file
, "\t.abiversion 2\n");
4935 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4936 || (TARGET_ELF
&& flag_pic
== 2))
4938 switch_to_section (toc_section
);
4939 switch_to_section (text_section
);
4944 /* Return nonzero if this function is known to have a null epilogue. */
4947 direct_return (void)
4949 if (reload_completed
)
4951 rs6000_stack_t
*info
= rs6000_stack_info ();
4953 if (info
->first_gp_reg_save
== 32
4954 && info
->first_fp_reg_save
== 64
4955 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4956 && ! info
->lr_save_p
4957 && ! info
->cr_save_p
4958 && info
->vrsave_mask
== 0
4966 /* Return the number of instructions it takes to form a constant in an
4967 integer register. */
4970 num_insns_constant_wide (HOST_WIDE_INT value
)
4972 /* signed constant loadable with addi */
4973 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4976 /* constant loadable with addis */
4977 else if ((value
& 0xffff) == 0
4978 && (value
>> 31 == -1 || value
>> 31 == 0))
4981 else if (TARGET_POWERPC64
)
4983 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4984 HOST_WIDE_INT high
= value
>> 31;
4986 if (high
== 0 || high
== -1)
4992 return num_insns_constant_wide (high
) + 1;
4994 return num_insns_constant_wide (low
) + 1;
4996 return (num_insns_constant_wide (high
)
4997 + num_insns_constant_wide (low
) + 1);
5005 num_insns_constant (rtx op
, enum machine_mode mode
)
5007 HOST_WIDE_INT low
, high
;
5009 switch (GET_CODE (op
))
5012 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
5013 && mask64_operand (op
, mode
))
5016 return num_insns_constant_wide (INTVAL (op
));
5018 case CONST_WIDE_INT
:
5021 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
5022 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5023 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
5028 if (mode
== SFmode
|| mode
== SDmode
)
5033 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5034 if (DECIMAL_FLOAT_MODE_P (mode
))
5035 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
5037 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5038 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5044 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5045 if (DECIMAL_FLOAT_MODE_P (mode
))
5046 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
5048 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
5049 high
= l
[WORDS_BIG_ENDIAN
== 0];
5050 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5053 return (num_insns_constant_wide (low
)
5054 + num_insns_constant_wide (high
));
5057 if ((high
== 0 && low
>= 0)
5058 || (high
== -1 && low
< 0))
5059 return num_insns_constant_wide (low
);
5061 else if (mask64_operand (op
, mode
))
5065 return num_insns_constant_wide (high
) + 1;
5068 return (num_insns_constant_wide (high
)
5069 + num_insns_constant_wide (low
) + 1);
5077 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5078 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5079 corresponding element of the vector, but for V4SFmode and V2SFmode,
5080 the corresponding "float" is interpreted as an SImode integer. */
5083 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5087 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5088 gcc_assert (GET_MODE (op
) != V2DImode
5089 && GET_MODE (op
) != V2DFmode
);
5091 tmp
= CONST_VECTOR_ELT (op
, elt
);
5092 if (GET_MODE (op
) == V4SFmode
5093 || GET_MODE (op
) == V2SFmode
)
5094 tmp
= gen_lowpart (SImode
, tmp
);
5095 return INTVAL (tmp
);
5098 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5099 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5100 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5101 all items are set to the same value and contain COPIES replicas of the
5102 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5103 operand and the others are set to the value of the operand's msb. */
5106 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5108 enum machine_mode mode
= GET_MODE (op
);
5109 enum machine_mode inner
= GET_MODE_INNER (mode
);
5117 HOST_WIDE_INT splat_val
;
5118 HOST_WIDE_INT msb_val
;
5120 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5123 nunits
= GET_MODE_NUNITS (mode
);
5124 bitsize
= GET_MODE_BITSIZE (inner
);
5125 mask
= GET_MODE_MASK (inner
);
5127 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5129 msb_val
= val
>= 0 ? 0 : -1;
5131 /* Construct the value to be splatted, if possible. If not, return 0. */
5132 for (i
= 2; i
<= copies
; i
*= 2)
5134 HOST_WIDE_INT small_val
;
5136 small_val
= splat_val
>> bitsize
;
5138 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5140 splat_val
= small_val
;
5143 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5144 if (EASY_VECTOR_15 (splat_val
))
5147 /* Also check if we can splat, and then add the result to itself. Do so if
5148 the value is positive, of if the splat instruction is using OP's mode;
5149 for splat_val < 0, the splat and the add should use the same mode. */
5150 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5151 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5154 /* Also check if are loading up the most significant bit which can be done by
5155 loading up -1 and shifting the value left by -1. */
5156 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5162 /* Check if VAL is present in every STEP-th element, and the
5163 other elements are filled with its most significant bit. */
5164 for (i
= 1; i
< nunits
; ++i
)
5166 HOST_WIDE_INT desired_val
;
5167 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5168 if ((i
& (step
- 1)) == 0)
5171 desired_val
= msb_val
;
5173 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5181 /* Return true if OP is of the given MODE and can be synthesized
5182 with a vspltisb, vspltish or vspltisw. */
5185 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5187 unsigned step
, copies
;
5189 if (mode
== VOIDmode
)
5190 mode
= GET_MODE (op
);
5191 else if (mode
!= GET_MODE (op
))
5194 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5196 if (mode
== V2DFmode
)
5197 return zero_constant (op
, mode
);
5199 else if (mode
== V2DImode
)
5201 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5202 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5205 if (zero_constant (op
, mode
))
5208 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5209 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5215 /* V1TImode is a special container for TImode. Ignore for now. */
5216 else if (mode
== V1TImode
)
5219 /* Start with a vspltisw. */
5220 step
= GET_MODE_NUNITS (mode
) / 4;
5223 if (vspltis_constant (op
, step
, copies
))
5226 /* Then try with a vspltish. */
5232 if (vspltis_constant (op
, step
, copies
))
5235 /* And finally a vspltisb. */
5241 if (vspltis_constant (op
, step
, copies
))
5247 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5248 result is OP. Abort if it is not possible. */
5251 gen_easy_altivec_constant (rtx op
)
5253 enum machine_mode mode
= GET_MODE (op
);
5254 int nunits
= GET_MODE_NUNITS (mode
);
5255 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5256 unsigned step
= nunits
/ 4;
5257 unsigned copies
= 1;
5259 /* Start with a vspltisw. */
5260 if (vspltis_constant (op
, step
, copies
))
5261 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5263 /* Then try with a vspltish. */
5269 if (vspltis_constant (op
, step
, copies
))
5270 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5272 /* And finally a vspltisb. */
5278 if (vspltis_constant (op
, step
, copies
))
5279 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5285 output_vec_const_move (rtx
*operands
)
5288 enum machine_mode mode
;
5293 mode
= GET_MODE (dest
);
5297 if (zero_constant (vec
, mode
))
5298 return "xxlxor %x0,%x0,%x0";
5300 if ((mode
== V2DImode
|| mode
== V1TImode
)
5301 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5302 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5303 return "vspltisw %0,-1";
5309 if (zero_constant (vec
, mode
))
5310 return "vxor %0,%0,%0";
5312 splat_vec
= gen_easy_altivec_constant (vec
);
5313 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5314 operands
[1] = XEXP (splat_vec
, 0);
5315 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5318 switch (GET_MODE (splat_vec
))
5321 return "vspltisw %0,%1";
5324 return "vspltish %0,%1";
5327 return "vspltisb %0,%1";
5334 gcc_assert (TARGET_SPE
);
5336 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5337 pattern of V1DI, V4HI, and V2SF.
5339 FIXME: We should probably return # and add post reload
5340 splitters for these, but this way is so easy ;-). */
5341 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5342 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5343 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5344 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5346 return "li %0,%1\n\tevmergelo %0,%0,%0";
5347 else if (WORDS_BIG_ENDIAN
)
5348 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5350 return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
5353 /* Initialize TARGET of vector PAIRED to VALS. */
5356 paired_expand_vector_init (rtx target
, rtx vals
)
5358 enum machine_mode mode
= GET_MODE (target
);
5359 int n_elts
= GET_MODE_NUNITS (mode
);
5361 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5364 for (i
= 0; i
< n_elts
; ++i
)
5366 x
= XVECEXP (vals
, 0, i
);
5367 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
5372 /* Load from constant pool. */
5373 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5379 /* The vector is initialized only with non-constants. */
5380 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5381 XVECEXP (vals
, 0, 1));
5383 emit_move_insn (target
, new_rtx
);
5387 /* One field is non-constant and the other one is a constant. Load the
5388 constant from the constant pool and use ps_merge instruction to
5389 construct the whole vector. */
5390 op1
= XVECEXP (vals
, 0, 0);
5391 op2
= XVECEXP (vals
, 0, 1);
5393 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5395 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5396 emit_move_insn (tmp
, constant_op
);
5398 if (CONSTANT_P (op1
))
5399 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5401 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5403 emit_move_insn (target
, new_rtx
);
5407 paired_expand_vector_move (rtx operands
[])
5409 rtx op0
= operands
[0], op1
= operands
[1];
5411 emit_move_insn (op0
, op1
);
5414 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5415 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5416 operands for the relation operation COND. This is a recursive
5420 paired_emit_vector_compare (enum rtx_code rcode
,
5421 rtx dest
, rtx op0
, rtx op1
,
5422 rtx cc_op0
, rtx cc_op1
)
5424 rtx tmp
= gen_reg_rtx (V2SFmode
);
5427 gcc_assert (TARGET_PAIRED_FLOAT
);
5428 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5434 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5438 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5439 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5443 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5446 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5449 tmp1
= gen_reg_rtx (V2SFmode
);
5450 max
= gen_reg_rtx (V2SFmode
);
5451 min
= gen_reg_rtx (V2SFmode
);
5452 gen_reg_rtx (V2SFmode
);
5454 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5455 emit_insn (gen_selv2sf4
5456 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5457 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5458 emit_insn (gen_selv2sf4
5459 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5460 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5461 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5464 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5467 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5470 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5473 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5476 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5485 /* Emit vector conditional expression.
5486 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5487 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5490 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5491 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5493 enum rtx_code rcode
= GET_CODE (cond
);
5495 if (!TARGET_PAIRED_FLOAT
)
5498 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5503 /* Initialize vector TARGET to VALS. */
5506 rs6000_expand_vector_init (rtx target
, rtx vals
)
5508 enum machine_mode mode
= GET_MODE (target
);
5509 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5510 int n_elts
= GET_MODE_NUNITS (mode
);
5511 int n_var
= 0, one_var
= -1;
5512 bool all_same
= true, all_const_zero
= true;
5516 for (i
= 0; i
< n_elts
; ++i
)
5518 x
= XVECEXP (vals
, 0, i
);
5519 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
5520 ++n_var
, one_var
= i
;
5521 else if (x
!= CONST0_RTX (inner_mode
))
5522 all_const_zero
= false;
5524 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5530 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5531 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5532 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5534 /* Zero register. */
5535 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5536 gen_rtx_XOR (mode
, target
, target
)));
5539 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5541 /* Splat immediate. */
5542 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5547 /* Load from constant pool. */
5548 emit_move_insn (target
, const_vec
);
5553 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5554 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5556 rtx op0
= XVECEXP (vals
, 0, 0);
5557 rtx op1
= XVECEXP (vals
, 0, 1);
5560 if (!MEM_P (op0
) && !REG_P (op0
))
5561 op0
= force_reg (inner_mode
, op0
);
5562 if (mode
== V2DFmode
)
5563 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5565 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5569 op0
= force_reg (inner_mode
, op0
);
5570 op1
= force_reg (inner_mode
, op1
);
5571 if (mode
== V2DFmode
)
5572 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5574 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5579 /* With single precision floating point on VSX, know that internally single
5580 precision is actually represented as a double, and either make 2 V2DF
5581 vectors, and convert these vectors to single precision, or do one
5582 conversion, and splat the result to the other elements. */
5583 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5587 rtx freg
= gen_reg_rtx (V4SFmode
);
5588 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5589 rtx cvt
= ((TARGET_XSCVDPSPN
)
5590 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5591 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5594 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
5598 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5599 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5600 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5601 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5602 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5603 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5604 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5605 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5607 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5608 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5609 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5610 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5611 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5616 /* Store value to stack temp. Load vector element. Splat. However, splat
5617 of 64-bit items is not supported on Altivec. */
5618 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5620 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5621 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5622 XVECEXP (vals
, 0, 0));
5623 x
= gen_rtx_UNSPEC (VOIDmode
,
5624 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5625 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5627 gen_rtx_SET (VOIDmode
,
5630 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5631 gen_rtx_PARALLEL (VOIDmode
,
5632 gen_rtvec (1, const0_rtx
)));
5633 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5634 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5638 /* One field is non-constant. Load constant then overwrite
5642 rtx copy
= copy_rtx (vals
);
5644 /* Load constant part of vector, substitute neighboring value for
5646 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5647 rs6000_expand_vector_init (target
, copy
);
5649 /* Insert variable. */
5650 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5654 /* Construct the vector in memory one field at a time
5655 and load the whole vector. */
5656 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5657 for (i
= 0; i
< n_elts
; i
++)
5658 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5659 i
* GET_MODE_SIZE (inner_mode
)),
5660 XVECEXP (vals
, 0, i
));
5661 emit_move_insn (target
, mem
);
5664 /* Set field ELT of TARGET to VAL. */
5667 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5669 enum machine_mode mode
= GET_MODE (target
);
5670 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5671 rtx reg
= gen_reg_rtx (mode
);
5673 int width
= GET_MODE_SIZE (inner_mode
);
5676 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5678 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5679 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5680 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5684 /* Simplify setting single element vectors like V1TImode. */
5685 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
5687 emit_move_insn (target
, gen_lowpart (mode
, val
));
5691 /* Load single variable value. */
5692 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5693 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5694 x
= gen_rtx_UNSPEC (VOIDmode
,
5695 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5696 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5698 gen_rtx_SET (VOIDmode
,
5702 /* Linear sequence. */
5703 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5704 for (i
= 0; i
< 16; ++i
)
5705 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5707 /* Set permute mask to insert element into target. */
5708 for (i
= 0; i
< width
; ++i
)
5709 XVECEXP (mask
, 0, elt
*width
+ i
)
5710 = GEN_INT (i
+ 0x10);
5711 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5713 if (BYTES_BIG_ENDIAN
)
5714 x
= gen_rtx_UNSPEC (mode
,
5715 gen_rtvec (3, target
, reg
,
5716 force_reg (V16QImode
, x
)),
5720 /* Invert selector. We prefer to generate VNAND on P8 so
5721 that future fusion opportunities can kick in, but must
5722 generate VNOR elsewhere. */
5723 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
5724 rtx iorx
= (TARGET_P8_VECTOR
5725 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
5726 : gen_rtx_AND (V16QImode
, notx
, notx
));
5727 rtx tmp
= gen_reg_rtx (V16QImode
);
5728 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, iorx
));
5730 /* Permute with operands reversed and adjusted selector. */
5731 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5735 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5738 /* Extract field ELT from VEC into TARGET. */
5741 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5743 enum machine_mode mode
= GET_MODE (vec
);
5744 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5747 if (VECTOR_MEM_VSX_P (mode
))
5754 gcc_assert (elt
== 0 && inner_mode
== TImode
);
5755 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
5758 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5761 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5764 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5769 /* Allocate mode-sized buffer. */
5770 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5772 emit_move_insn (mem
, vec
);
5774 /* Add offset to field within buffer matching vector element. */
5775 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5777 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5780 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5781 implement ANDing by the mask IN. */
5783 build_mask64_2_operands (rtx in
, rtx
*out
)
5785 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5788 gcc_assert (GET_CODE (in
) == CONST_INT
);
5793 /* Assume c initially something like 0x00fff000000fffff. The idea
5794 is to rotate the word so that the middle ^^^^^^ group of zeros
5795 is at the MS end and can be cleared with an rldicl mask. We then
5796 rotate back and clear off the MS ^^ group of zeros with a
5798 c
= ~c
; /* c == 0xff000ffffff00000 */
5799 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5800 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5801 c
= ~c
; /* c == 0x00fff000000fffff */
5802 c
&= -lsb
; /* c == 0x00fff00000000000 */
5803 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5804 c
= ~c
; /* c == 0xff000fffffffffff */
5805 c
&= -lsb
; /* c == 0xff00000000000000 */
5807 while ((lsb
>>= 1) != 0)
5808 shift
++; /* shift == 44 on exit from loop */
5809 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5810 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5811 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5815 /* Assume c initially something like 0xff000f0000000000. The idea
5816 is to rotate the word so that the ^^^ middle group of zeros
5817 is at the LS end and can be cleared with an rldicr mask. We then
5818 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5820 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5821 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5822 c
= ~c
; /* c == 0x00fff0ffffffffff */
5823 c
&= -lsb
; /* c == 0x00fff00000000000 */
5824 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5825 c
= ~c
; /* c == 0xff000fffffffffff */
5826 c
&= -lsb
; /* c == 0xff00000000000000 */
5828 while ((lsb
>>= 1) != 0)
5829 shift
++; /* shift == 44 on exit from loop */
5830 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5831 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5832 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5835 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5836 masks will be all 1's. We are guaranteed more than one transition. */
5837 out
[0] = GEN_INT (64 - shift
);
5838 out
[1] = GEN_INT (m1
);
5839 out
[2] = GEN_INT (shift
);
5840 out
[3] = GEN_INT (m2
);
5843 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5846 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5848 if (TARGET_E500_DOUBLE
)
5850 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5851 subreg:TI and reg:TF. Decimal float modes are like integer
5852 modes (only low part of each register used) for this
5854 if (GET_CODE (op
) == SUBREG
5855 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5856 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5857 && REG_P (SUBREG_REG (op
))
5858 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5859 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5862 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5864 if (GET_CODE (op
) == SUBREG
5865 && (mode
== DFmode
|| mode
== TFmode
)
5866 && REG_P (SUBREG_REG (op
))
5867 && (GET_MODE (SUBREG_REG (op
)) == DImode
5868 || GET_MODE (SUBREG_REG (op
)) == TImode
5869 || GET_MODE (SUBREG_REG (op
)) == PTImode
5870 || GET_MODE (SUBREG_REG (op
)) == DDmode
5871 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5876 && GET_CODE (op
) == SUBREG
5878 && REG_P (SUBREG_REG (op
))
5879 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5885 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5886 selects whether the alignment is abi mandated, optional, or
5887 both abi and optional alignment. */
5890 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5892 if (how
!= align_opt
)
5894 if (TREE_CODE (type
) == VECTOR_TYPE
)
5896 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5897 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5902 else if (align
< 128)
5905 else if (TARGET_E500_DOUBLE
5906 && TREE_CODE (type
) == REAL_TYPE
5907 && TYPE_MODE (type
) == DFmode
)
5914 if (how
!= align_abi
)
5916 if (TREE_CODE (type
) == ARRAY_TYPE
5917 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5919 if (align
< BITS_PER_WORD
)
5920 align
= BITS_PER_WORD
;
5927 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
5930 rs6000_special_adjust_field_align_p (tree field
, unsigned int computed
)
5932 if (TARGET_ALTIVEC
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5934 if (computed
!= 128)
5937 if (!warned
&& warn_psabi
)
5940 inform (input_location
,
5941 "the layout of aggregates containing vectors with"
5942 " %d-byte alignment has changed in GCC 5",
5943 computed
/ BITS_PER_UNIT
);
5946 /* In current GCC there is no special case. */
5953 /* AIX increases natural record alignment to doubleword if the first
5954 field is an FP double while the FP fields remain word aligned. */
5957 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5958 unsigned int specified
)
5960 unsigned int align
= MAX (computed
, specified
);
5961 tree field
= TYPE_FIELDS (type
);
5963 /* Skip all non field decls */
5964 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5965 field
= DECL_CHAIN (field
);
5967 if (field
!= NULL
&& field
!= type
)
5969 type
= TREE_TYPE (field
);
5970 while (TREE_CODE (type
) == ARRAY_TYPE
)
5971 type
= TREE_TYPE (type
);
5973 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5974 align
= MAX (align
, 64);
5980 /* Darwin increases record alignment to the natural alignment of
5984 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5985 unsigned int specified
)
5987 unsigned int align
= MAX (computed
, specified
);
5989 if (TYPE_PACKED (type
))
5992 /* Find the first field, looking down into aggregates. */
5994 tree field
= TYPE_FIELDS (type
);
5995 /* Skip all non field decls */
5996 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5997 field
= DECL_CHAIN (field
);
6000 /* A packed field does not contribute any extra alignment. */
6001 if (DECL_PACKED (field
))
6003 type
= TREE_TYPE (field
);
6004 while (TREE_CODE (type
) == ARRAY_TYPE
)
6005 type
= TREE_TYPE (type
);
6006 } while (AGGREGATE_TYPE_P (type
));
6008 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
6009 align
= MAX (align
, TYPE_ALIGN (type
));
6014 /* Return 1 for an operand in small memory on V.4/eabi. */
6017 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
6018 enum machine_mode mode ATTRIBUTE_UNUSED
)
6023 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
6026 if (DEFAULT_ABI
!= ABI_V4
)
6029 /* Vector and float memory instructions have a limited offset on the
6030 SPE, so using a vector or float variable directly as an operand is
6033 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
6036 if (GET_CODE (op
) == SYMBOL_REF
)
6039 else if (GET_CODE (op
) != CONST
6040 || GET_CODE (XEXP (op
, 0)) != PLUS
6041 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
6042 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
6047 rtx sum
= XEXP (op
, 0);
6048 HOST_WIDE_INT summand
;
6050 /* We have to be careful here, because it is the referenced address
6051 that must be 32k from _SDA_BASE_, not just the symbol. */
6052 summand
= INTVAL (XEXP (sum
, 1));
6053 if (summand
< 0 || summand
> g_switch_value
)
6056 sym_ref
= XEXP (sum
, 0);
6059 return SYMBOL_REF_SMALL_P (sym_ref
);
6065 /* Return true if either operand is a general purpose register. */
6068 gpr_or_gpr_p (rtx op0
, rtx op1
)
6070 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
6071 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
6074 /* Return true if this is a move direct operation between GPR registers and
6075 floating point/VSX registers. */
6078 direct_move_p (rtx op0
, rtx op1
)
6082 if (!REG_P (op0
) || !REG_P (op1
))
6085 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
6088 regno0
= REGNO (op0
);
6089 regno1
= REGNO (op1
);
6090 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
6093 if (INT_REGNO_P (regno0
))
6094 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
6096 else if (INT_REGNO_P (regno1
))
6098 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
6101 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
6108 /* Return true if this is a load or store quad operation. This function does
6109 not handle the atomic quad memory instructions. */
6112 quad_load_store_p (rtx op0
, rtx op1
)
6116 if (!TARGET_QUAD_MEMORY
)
6119 else if (REG_P (op0
) && MEM_P (op1
))
6120 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6121 && quad_memory_operand (op1
, GET_MODE (op1
))
6122 && !reg_overlap_mentioned_p (op0
, op1
));
6124 else if (MEM_P (op0
) && REG_P (op1
))
6125 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6126 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6131 if (TARGET_DEBUG_ADDR
)
6133 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6134 ret
? "true" : "false");
6135 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
6141 /* Given an address, return a constant offset term if one exists. */
6144 address_offset (rtx op
)
6146 if (GET_CODE (op
) == PRE_INC
6147 || GET_CODE (op
) == PRE_DEC
)
6149 else if (GET_CODE (op
) == PRE_MODIFY
6150 || GET_CODE (op
) == LO_SUM
)
6153 if (GET_CODE (op
) == CONST
)
6156 if (GET_CODE (op
) == PLUS
)
6159 if (CONST_INT_P (op
))
6165 /* Return true if the MEM operand is a memory operand suitable for use
6166 with a (full width, possibly multiple) gpr load/store. On
6167 powerpc64 this means the offset must be divisible by 4.
6168 Implements 'Y' constraint.
6170 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6171 a constraint function we know the operand has satisfied a suitable
6172 memory predicate. Also accept some odd rtl generated by reload
6173 (see rs6000_legitimize_reload_address for various forms). It is
6174 important that reload rtl be accepted by appropriate constraints
6175 but not by the operand predicate.
6177 Offsetting a lo_sum should not be allowed, except where we know by
6178 alignment that a 32k boundary is not crossed, but see the ???
6179 comment in rs6000_legitimize_reload_address. Note that by
6180 "offsetting" here we mean a further offset to access parts of the
6181 MEM. It's fine to have a lo_sum where the inner address is offset
6182 from a sym, since the same sym+offset will appear in the high part
6183 of the address calculation. */
6186 mem_operand_gpr (rtx op
, enum machine_mode mode
)
6188 unsigned HOST_WIDE_INT offset
;
6190 rtx addr
= XEXP (op
, 0);
6192 op
= address_offset (addr
);
6196 offset
= INTVAL (op
);
6197 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6200 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6204 if (GET_CODE (addr
) == LO_SUM
)
6205 /* For lo_sum addresses, we must allow any offset except one that
6206 causes a wrap, so test only the low 16 bits. */
6207 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6209 return offset
+ 0x8000 < 0x10000u
- extra
;
6212 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6215 reg_offset_addressing_ok_p (enum machine_mode mode
)
6227 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6228 TImode is not a vector mode, if we want to use the VSX registers to
6229 move it around, we need to restrict ourselves to reg+reg
6231 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6239 /* Paired vector modes. Only reg+reg addressing is valid. */
6240 if (TARGET_PAIRED_FLOAT
)
6245 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6246 addressing for the LFIWZX and STFIWX instructions. */
6247 if (TARGET_NO_SDMODE_STACK
)
6259 virtual_stack_registers_memory_p (rtx op
)
6263 if (GET_CODE (op
) == REG
)
6264 regnum
= REGNO (op
);
6266 else if (GET_CODE (op
) == PLUS
6267 && GET_CODE (XEXP (op
, 0)) == REG
6268 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6269 regnum
= REGNO (XEXP (op
, 0));
6274 return (regnum
>= FIRST_VIRTUAL_REGISTER
6275 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6278 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6279 is known to not straddle a 32k boundary. */
6282 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6283 enum machine_mode mode
)
6286 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6288 if (GET_CODE (op
) != SYMBOL_REF
)
6291 dsize
= GET_MODE_SIZE (mode
);
6292 decl
= SYMBOL_REF_DECL (op
);
6298 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6299 replacing memory addresses with an anchor plus offset. We
6300 could find the decl by rummaging around in the block->objects
6301 VEC for the given offset but that seems like too much work. */
6302 dalign
= BITS_PER_UNIT
;
6303 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6304 && SYMBOL_REF_ANCHOR_P (op
)
6305 && SYMBOL_REF_BLOCK (op
) != NULL
)
6307 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6309 dalign
= block
->alignment
;
6310 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6312 else if (CONSTANT_POOL_ADDRESS_P (op
))
6314 /* It would be nice to have get_pool_align().. */
6315 enum machine_mode cmode
= get_pool_mode (op
);
6317 dalign
= GET_MODE_ALIGNMENT (cmode
);
6320 else if (DECL_P (decl
))
6322 dalign
= DECL_ALIGN (decl
);
6326 /* Allow BLKmode when the entire object is known to not
6327 cross a 32k boundary. */
6328 if (!DECL_SIZE_UNIT (decl
))
6331 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6334 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6338 return dalign
/ BITS_PER_UNIT
>= dsize
;
6343 type
= TREE_TYPE (decl
);
6345 dalign
= TYPE_ALIGN (type
);
6346 if (CONSTANT_CLASS_P (decl
))
6347 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6349 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6353 /* BLKmode, check the entire object. */
6354 if (TREE_CODE (decl
) == STRING_CST
)
6355 dsize
= TREE_STRING_LENGTH (decl
);
6356 else if (TYPE_SIZE_UNIT (type
)
6357 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6358 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6364 return dalign
/ BITS_PER_UNIT
>= dsize
;
6368 /* Find how many bits of the alignment we know for this access. */
6369 mask
= dalign
/ BITS_PER_UNIT
- 1;
6370 lsb
= offset
& -offset
;
6374 return dalign
>= dsize
;
6378 constant_pool_expr_p (rtx op
)
6382 split_const (op
, &base
, &offset
);
6383 return (GET_CODE (base
) == SYMBOL_REF
6384 && CONSTANT_POOL_ADDRESS_P (base
)
6385 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6388 static const_rtx tocrel_base
, tocrel_offset
;
6390 /* Return true if OP is a toc pointer relative address (the output
6391 of create_TOC_reference). If STRICT, do not match high part or
6392 non-split -mcmodel=large/medium toc pointer relative addresses. */
6395 toc_relative_expr_p (const_rtx op
, bool strict
)
6400 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6402 /* Only match the low part. */
6403 if (GET_CODE (op
) == LO_SUM
6404 && REG_P (XEXP (op
, 0))
6405 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6412 tocrel_offset
= const0_rtx
;
6413 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6415 tocrel_base
= XEXP (op
, 0);
6416 tocrel_offset
= XEXP (op
, 1);
6419 return (GET_CODE (tocrel_base
) == UNSPEC
6420 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6423 /* Return true if X is a constant pool address, and also for cmodel=medium
6424 if X is a toc-relative address known to be offsettable within MODE. */
6427 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6430 return (toc_relative_expr_p (x
, strict
)
6431 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6432 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6434 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6435 INTVAL (tocrel_offset
), mode
)));
6439 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6441 return (DEFAULT_ABI
== ABI_V4
6442 && !flag_pic
&& !TARGET_TOC
6443 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6444 && small_data_operand (x
, mode
));
6447 /* SPE offset addressing is limited to 5-bits worth of double words. */
6448 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6451 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6452 bool strict
, bool worst_case
)
6454 unsigned HOST_WIDE_INT offset
;
6457 if (GET_CODE (x
) != PLUS
)
6459 if (!REG_P (XEXP (x
, 0)))
6461 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6463 if (!reg_offset_addressing_ok_p (mode
))
6464 return virtual_stack_registers_memory_p (x
);
6465 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6467 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6470 offset
= INTVAL (XEXP (x
, 1));
6478 /* SPE vector modes. */
6479 return SPE_CONST_OFFSET_OK (offset
);
6484 /* On e500v2, we may have:
6486 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6488 Which gets addressed with evldd instructions. */
6489 if (TARGET_E500_DOUBLE
)
6490 return SPE_CONST_OFFSET_OK (offset
);
6492 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6494 if (VECTOR_MEM_VSX_P (mode
))
6499 if (!TARGET_POWERPC64
)
6501 else if (offset
& 3)
6506 if (TARGET_E500_DOUBLE
)
6507 return (SPE_CONST_OFFSET_OK (offset
)
6508 && SPE_CONST_OFFSET_OK (offset
+ 8));
6517 if (!TARGET_POWERPC64
)
6519 else if (offset
& 3)
6528 return offset
< 0x10000 - extra
;
6532 legitimate_indexed_address_p (rtx x
, int strict
)
6536 if (GET_CODE (x
) != PLUS
)
6542 /* Recognize the rtl generated by reload which we know will later be
6543 replaced with proper base and index regs. */
6545 && reload_in_progress
6546 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6550 return (REG_P (op0
) && REG_P (op1
)
6551 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6552 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6553 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6554 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6558 avoiding_indexed_address_p (enum machine_mode mode
)
6560 /* Avoid indexed addressing for modes that have non-indexed
6561 load/store instruction forms. */
6562 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6566 legitimate_indirect_address_p (rtx x
, int strict
)
6568 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6572 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6574 if (!TARGET_MACHO
|| !flag_pic
6575 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6579 if (GET_CODE (x
) != LO_SUM
)
6581 if (GET_CODE (XEXP (x
, 0)) != REG
)
6583 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6587 return CONSTANT_P (x
);
6591 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6593 if (GET_CODE (x
) != LO_SUM
)
6595 if (GET_CODE (XEXP (x
, 0)) != REG
)
6597 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6599 /* Restrict addressing for DI because of our SUBREG hackery. */
6600 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6604 if (TARGET_ELF
|| TARGET_MACHO
)
6608 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6610 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6611 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6612 recognizes some LO_SUM addresses as valid although this
6613 function says opposite. In most cases, LRA through different
6614 transformations can generate correct code for address reloads.
6615 It can not manage only some LO_SUM cases. So we need to add
6616 code analogous to one in rs6000_legitimize_reload_address for
6617 LOW_SUM here saying that some addresses are still valid. */
6618 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6619 && small_toc_ref (x
, VOIDmode
));
6620 if (TARGET_TOC
&& ! large_toc_ok
)
6622 if (GET_MODE_NUNITS (mode
) != 1)
6624 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6625 && !(/* ??? Assume floating point reg based on mode? */
6626 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6627 && (mode
== DFmode
|| mode
== DDmode
)))
6630 return CONSTANT_P (x
) || large_toc_ok
;
6637 /* Try machine-dependent ways of modifying an illegitimate address
6638 to be legitimate. If we find one, return the new, valid address.
6639 This is used from only one place: `memory_address' in explow.c.
6641 OLDX is the address as it was before break_out_memory_refs was
6642 called. In some cases it is useful to look at this to decide what
6645 It is always safe for this function to do nothing. It exists to
6646 recognize opportunities to optimize the output.
6648 On RS/6000, first check for the sum of a register with a constant
6649 integer that is out of range. If so, generate code to add the
6650 constant with the low-order 16 bits masked to the register and force
6651 this result into another register (this can be done with `cau').
6652 Then generate an address of REG+(CONST&0xffff), allowing for the
6653 possibility of bit 16 being a one.
6655 Then check for the sum of a register and something not constant, try to
6656 load the other things into a register and return the sum. */
6659 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6660 enum machine_mode mode
)
6664 if (!reg_offset_addressing_ok_p (mode
))
6666 if (virtual_stack_registers_memory_p (x
))
6669 /* In theory we should not be seeing addresses of the form reg+0,
6670 but just in case it is generated, optimize it away. */
6671 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6672 return force_reg (Pmode
, XEXP (x
, 0));
6674 /* For TImode with load/store quad, restrict addresses to just a single
6675 pointer, so it works with both GPRs and VSX registers. */
6676 /* Make sure both operands are registers. */
6677 else if (GET_CODE (x
) == PLUS
6678 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6679 return gen_rtx_PLUS (Pmode
,
6680 force_reg (Pmode
, XEXP (x
, 0)),
6681 force_reg (Pmode
, XEXP (x
, 1)));
6683 return force_reg (Pmode
, x
);
6685 if (GET_CODE (x
) == SYMBOL_REF
)
6687 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6689 return rs6000_legitimize_tls_address (x
, model
);
6699 /* As in legitimate_offset_address_p we do not assume
6700 worst-case. The mode here is just a hint as to the registers
6701 used. A TImode is usually in gprs, but may actually be in
6702 fprs. Leave worst-case scenario for reload to handle via
6703 insn constraints. PTImode is only GPRs. */
6710 if (GET_CODE (x
) == PLUS
6711 && GET_CODE (XEXP (x
, 0)) == REG
6712 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6713 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6715 && !(SPE_VECTOR_MODE (mode
)
6716 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6718 HOST_WIDE_INT high_int
, low_int
;
6720 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6721 if (low_int
>= 0x8000 - extra
)
6723 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6724 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6725 GEN_INT (high_int
)), 0);
6726 return plus_constant (Pmode
, sum
, low_int
);
6728 else if (GET_CODE (x
) == PLUS
6729 && GET_CODE (XEXP (x
, 0)) == REG
6730 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6731 && GET_MODE_NUNITS (mode
) == 1
6732 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6733 || (/* ??? Assume floating point reg based on mode? */
6734 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6735 && (mode
== DFmode
|| mode
== DDmode
)))
6736 && !avoiding_indexed_address_p (mode
))
6738 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6739 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6741 else if (SPE_VECTOR_MODE (mode
)
6742 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6746 /* We accept [reg + reg] and [reg + OFFSET]. */
6748 if (GET_CODE (x
) == PLUS
)
6750 rtx op1
= XEXP (x
, 0);
6751 rtx op2
= XEXP (x
, 1);
6754 op1
= force_reg (Pmode
, op1
);
6756 if (GET_CODE (op2
) != REG
6757 && (GET_CODE (op2
) != CONST_INT
6758 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6759 || (GET_MODE_SIZE (mode
) > 8
6760 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6761 op2
= force_reg (Pmode
, op2
);
6763 /* We can't always do [reg + reg] for these, because [reg +
6764 reg + offset] is not a legitimate addressing mode. */
6765 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6767 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6768 return force_reg (Pmode
, y
);
6773 return force_reg (Pmode
, x
);
6775 else if ((TARGET_ELF
6777 || !MACHO_DYNAMIC_NO_PIC_P
6783 && GET_CODE (x
) != CONST_INT
6784 && GET_CODE (x
) != CONST_WIDE_INT
6785 && GET_CODE (x
) != CONST_DOUBLE
6787 && GET_MODE_NUNITS (mode
) == 1
6788 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6789 || (/* ??? Assume floating point reg based on mode? */
6790 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6791 && (mode
== DFmode
|| mode
== DDmode
))))
6793 rtx reg
= gen_reg_rtx (Pmode
);
6795 emit_insn (gen_elf_high (reg
, x
));
6797 emit_insn (gen_macho_high (reg
, x
));
6798 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6801 && GET_CODE (x
) == SYMBOL_REF
6802 && constant_pool_expr_p (x
)
6803 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6804 return create_TOC_reference (x
, NULL_RTX
);
6809 /* Debug version of rs6000_legitimize_address. */
6811 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6817 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6818 insns
= get_insns ();
6824 "\nrs6000_legitimize_address: mode %s, old code %s, "
6825 "new code %s, modified\n",
6826 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6827 GET_RTX_NAME (GET_CODE (ret
)));
6829 fprintf (stderr
, "Original address:\n");
6832 fprintf (stderr
, "oldx:\n");
6835 fprintf (stderr
, "New address:\n");
6840 fprintf (stderr
, "Insns added:\n");
6841 debug_rtx_list (insns
, 20);
6847 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6848 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6859 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6860 We need to emit DTP-relative relocations. */
6862 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6864 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6869 fputs ("\t.long\t", file
);
6872 fputs (DOUBLE_INT_ASM_OP
, file
);
6877 output_addr_const (file
, x
);
6878 fputs ("@dtprel+0x8000", file
);
6881 /* Return true if X is a symbol that refers to real (rather than emulated)
6885 rs6000_real_tls_symbol_ref_p (rtx x
)
6887 return (GET_CODE (x
) == SYMBOL_REF
6888 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
6891 /* In the name of slightly smaller debug output, and to cater to
6892 general assembler lossage, recognize various UNSPEC sequences
6893 and turn them back into a direct symbol reference. */
6896 rs6000_delegitimize_address (rtx orig_x
)
6900 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6906 if (TARGET_CMODEL
!= CMODEL_SMALL
6907 && GET_CODE (y
) == LO_SUM
)
6911 if (GET_CODE (y
) == PLUS
6912 && GET_MODE (y
) == Pmode
6913 && CONST_INT_P (XEXP (y
, 1)))
6915 offset
= XEXP (y
, 1);
6919 if (GET_CODE (y
) == UNSPEC
6920 && XINT (y
, 1) == UNSPEC_TOCREL
)
6922 #ifdef ENABLE_CHECKING
6923 if (REG_P (XVECEXP (y
, 0, 1))
6924 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6928 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6930 /* Weirdness alert. df_note_compute can replace r2 with a
6931 debug_expr when this unspec is in a debug_insn.
6932 Seen in gcc.dg/pr51957-1.c */
6940 y
= XVECEXP (y
, 0, 0);
6943 /* Do not associate thread-local symbols with the original
6944 constant pool symbol. */
6946 && GET_CODE (y
) == SYMBOL_REF
6947 && CONSTANT_POOL_ADDRESS_P (y
)
6948 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
6952 if (offset
!= NULL_RTX
)
6953 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6954 if (!MEM_P (orig_x
))
6957 return replace_equiv_address_nv (orig_x
, y
);
6961 && GET_CODE (orig_x
) == LO_SUM
6962 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6964 y
= XEXP (XEXP (orig_x
, 1), 0);
6965 if (GET_CODE (y
) == UNSPEC
6966 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6967 return XVECEXP (y
, 0, 0);
6973 /* Return true if X shouldn't be emitted into the debug info.
6974 The linker doesn't like .toc section references from
6975 .debug_* sections, so reject .toc section symbols. */
6978 rs6000_const_not_ok_for_debug_p (rtx x
)
6980 if (GET_CODE (x
) == SYMBOL_REF
6981 && CONSTANT_POOL_ADDRESS_P (x
))
6983 rtx c
= get_pool_constant (x
);
6984 enum machine_mode cmode
= get_pool_mode (x
);
6985 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6992 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6994 static GTY(()) rtx rs6000_tls_symbol
;
6996 rs6000_tls_get_addr (void)
6998 if (!rs6000_tls_symbol
)
6999 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
7001 return rs6000_tls_symbol
;
7004 /* Construct the SYMBOL_REF for TLS GOT references. */
7006 static GTY(()) rtx rs6000_got_symbol
;
7008 rs6000_got_sym (void)
7010 if (!rs6000_got_symbol
)
7012 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7013 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
7014 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
7017 return rs6000_got_symbol
;
7020 /* AIX Thread-Local Address support. */
7023 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
7025 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
7029 name
= XSTR (addr
, 0);
7030 /* Append TLS CSECT qualifier, unless the symbol already is qualified
7031 or the symbol will be in TLS private data section. */
7032 if (name
[strlen (name
) - 1] != ']'
7033 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
7034 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
7036 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
7037 strcpy (tlsname
, name
);
7039 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
7040 tlsaddr
= copy_rtx (addr
);
7041 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
7046 /* Place addr into TOC constant pool. */
7047 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
7049 /* Output the TOC entry and create the MEM referencing the value. */
7050 if (constant_pool_expr_p (XEXP (sym
, 0))
7051 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
7053 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
7054 mem
= gen_const_mem (Pmode
, tocref
);
7055 set_mem_alias_set (mem
, get_TOC_alias_set ());
7060 /* Use global-dynamic for local-dynamic. */
7061 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
7062 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
7064 /* Create new TOC reference for @m symbol. */
7065 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
7066 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
7067 strcpy (tlsname
, "*LCM");
7068 strcat (tlsname
, name
+ 3);
7069 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
7070 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
7071 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
7072 rtx modmem
= gen_const_mem (Pmode
, tocref
);
7073 set_mem_alias_set (modmem
, get_TOC_alias_set ());
7075 rtx modreg
= gen_reg_rtx (Pmode
);
7076 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
7078 tmpreg
= gen_reg_rtx (Pmode
);
7079 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
7081 dest
= gen_reg_rtx (Pmode
);
7083 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
7085 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
7088 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7089 else if (TARGET_32BIT
)
7091 tlsreg
= gen_reg_rtx (SImode
);
7092 emit_insn (gen_tls_get_tpointer (tlsreg
));
7095 tlsreg
= gen_rtx_REG (DImode
, 13);
7097 /* Load the TOC value into temporary register. */
7098 tmpreg
= gen_reg_rtx (Pmode
);
7099 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
7100 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
7101 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
7103 /* Add TOC symbol value to TLS pointer. */
7104 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
7109 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7110 this (thread-local) address. */
7113 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
7118 return rs6000_legitimize_tls_address_aix (addr
, model
);
7120 dest
= gen_reg_rtx (Pmode
);
7121 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7127 tlsreg
= gen_rtx_REG (Pmode
, 13);
7128 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7132 tlsreg
= gen_rtx_REG (Pmode
, 2);
7133 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7137 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7141 tmp
= gen_reg_rtx (Pmode
);
7144 tlsreg
= gen_rtx_REG (Pmode
, 13);
7145 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7149 tlsreg
= gen_rtx_REG (Pmode
, 2);
7150 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7154 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7156 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7161 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7163 /* We currently use relocations like @got@tlsgd for tls, which
7164 means the linker will handle allocation of tls entries, placing
7165 them in the .got section. So use a pointer to the .got section,
7166 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7167 or to secondary GOT sections used by 32-bit -fPIC. */
7169 got
= gen_rtx_REG (Pmode
, 2);
7173 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7176 rtx gsym
= rs6000_got_sym ();
7177 got
= gen_reg_rtx (Pmode
);
7179 rs6000_emit_move (got
, gsym
, Pmode
);
7184 tmp1
= gen_reg_rtx (Pmode
);
7185 tmp2
= gen_reg_rtx (Pmode
);
7186 mem
= gen_const_mem (Pmode
, tmp1
);
7187 lab
= gen_label_rtx ();
7188 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7189 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7190 if (TARGET_LINK_STACK
)
7191 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7192 emit_move_insn (tmp2
, mem
);
7193 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7194 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7199 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7201 tga
= rs6000_tls_get_addr ();
7202 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7203 1, const0_rtx
, Pmode
);
7205 r3
= gen_rtx_REG (Pmode
, 3);
7206 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7209 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7211 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7213 else if (DEFAULT_ABI
== ABI_V4
)
7214 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7217 call_insn
= last_call_insn ();
7218 PATTERN (call_insn
) = insn
;
7219 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7220 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7221 pic_offset_table_rtx
);
7223 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7225 tga
= rs6000_tls_get_addr ();
7226 tmp1
= gen_reg_rtx (Pmode
);
7227 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7228 1, const0_rtx
, Pmode
);
7230 r3
= gen_rtx_REG (Pmode
, 3);
7231 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7234 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7236 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7238 else if (DEFAULT_ABI
== ABI_V4
)
7239 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7242 call_insn
= last_call_insn ();
7243 PATTERN (call_insn
) = insn
;
7244 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7245 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7246 pic_offset_table_rtx
);
7248 if (rs6000_tls_size
== 16)
7251 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7253 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7255 else if (rs6000_tls_size
== 32)
7257 tmp2
= gen_reg_rtx (Pmode
);
7259 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7261 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7264 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7266 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7270 tmp2
= gen_reg_rtx (Pmode
);
7272 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7274 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7276 insn
= gen_rtx_SET (Pmode
, dest
,
7277 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7283 /* IE, or 64-bit offset LE. */
7284 tmp2
= gen_reg_rtx (Pmode
);
7286 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7288 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7291 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7293 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7301 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7304 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7306 if (GET_CODE (x
) == HIGH
7307 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7310 /* A TLS symbol in the TOC cannot contain a sum. */
7311 if (GET_CODE (x
) == CONST
7312 && GET_CODE (XEXP (x
, 0)) == PLUS
7313 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7314 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7317 /* Do not place an ELF TLS symbol in the constant pool. */
7318 return TARGET_ELF
&& tls_referenced_p (x
);
7321 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7322 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7323 can be addressed relative to the toc pointer. */
7326 use_toc_relative_ref (rtx sym
)
7328 return ((constant_pool_expr_p (sym
)
7329 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7330 get_pool_mode (sym
)))
7331 || (TARGET_CMODEL
== CMODEL_MEDIUM
7332 && SYMBOL_REF_LOCAL_P (sym
)));
7335 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7336 replace the input X, or the original X if no replacement is called for.
7337 The output parameter *WIN is 1 if the calling macro should goto WIN,
7340 For RS/6000, we wish to handle large displacements off a base
7341 register by splitting the addend across an addiu/addis and the mem insn.
7342 This cuts number of extra insns needed from 3 to 1.
7344 On Darwin, we use this to generate code for floating point constants.
7345 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7346 The Darwin code is inside #if TARGET_MACHO because only then are the
7347 machopic_* functions defined. */
7349 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7350 int opnum
, int type
,
7351 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7353 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7355 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7356 DFmode/DImode MEM. */
7359 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7360 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7361 reg_offset_p
= false;
7363 /* We must recognize output that we have already generated ourselves. */
7364 if (GET_CODE (x
) == PLUS
7365 && GET_CODE (XEXP (x
, 0)) == PLUS
7366 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7367 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7368 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7370 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7371 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7372 opnum
, (enum reload_type
) type
);
7377 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7378 if (GET_CODE (x
) == LO_SUM
7379 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7381 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7382 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7383 opnum
, (enum reload_type
) type
);
7389 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7390 && GET_CODE (x
) == LO_SUM
7391 && GET_CODE (XEXP (x
, 0)) == PLUS
7392 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7393 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7394 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7395 && machopic_operand_p (XEXP (x
, 1)))
7397 /* Result of previous invocation of this function on Darwin
7398 floating point constant. */
7399 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7400 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7401 opnum
, (enum reload_type
) type
);
7407 if (TARGET_CMODEL
!= CMODEL_SMALL
7409 && small_toc_ref (x
, VOIDmode
))
7411 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7412 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7413 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7414 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7415 opnum
, (enum reload_type
) type
);
7420 if (GET_CODE (x
) == PLUS
7421 && GET_CODE (XEXP (x
, 0)) == REG
7422 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7423 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7424 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7426 && !SPE_VECTOR_MODE (mode
)
7427 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7428 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7430 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7431 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7433 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7435 /* Check for 32-bit overflow. */
7436 if (high
+ low
!= val
)
7442 /* Reload the high part into a base reg; leave the low part
7443 in the mem directly. */
7445 x
= gen_rtx_PLUS (GET_MODE (x
),
7446 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7450 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7451 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7452 opnum
, (enum reload_type
) type
);
7457 if (GET_CODE (x
) == SYMBOL_REF
7459 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7460 && !SPE_VECTOR_MODE (mode
)
7462 && DEFAULT_ABI
== ABI_DARWIN
7463 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7464 && machopic_symbol_defined_p (x
)
7466 && DEFAULT_ABI
== ABI_V4
7469 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7470 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7472 ??? Assume floating point reg based on mode? This assumption is
7473 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7474 where reload ends up doing a DFmode load of a constant from
7475 mem using two gprs. Unfortunately, at this point reload
7476 hasn't yet selected regs so poking around in reload data
7477 won't help and even if we could figure out the regs reliably,
7478 we'd still want to allow this transformation when the mem is
7479 naturally aligned. Since we say the address is good here, we
7480 can't disable offsets from LO_SUMs in mem_operand_gpr.
7481 FIXME: Allow offset from lo_sum for other modes too, when
7482 mem is sufficiently aligned. */
7485 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7487 && (mode
!= DImode
|| TARGET_POWERPC64
)
7488 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7489 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7494 rtx offset
= machopic_gen_offset (x
);
7495 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7496 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7497 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7501 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7502 gen_rtx_HIGH (Pmode
, x
), x
);
7504 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7505 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7506 opnum
, (enum reload_type
) type
);
7511 /* Reload an offset address wrapped by an AND that represents the
7512 masking of the lower bits. Strip the outer AND and let reload
7513 convert the offset address into an indirect address. For VSX,
7514 force reload to create the address with an AND in a separate
7515 register, because we can't guarantee an altivec register will
7517 if (VECTOR_MEM_ALTIVEC_P (mode
)
7518 && GET_CODE (x
) == AND
7519 && GET_CODE (XEXP (x
, 0)) == PLUS
7520 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7521 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7522 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7523 && INTVAL (XEXP (x
, 1)) == -16)
7532 && GET_CODE (x
) == SYMBOL_REF
7533 && use_toc_relative_ref (x
))
7535 x
= create_TOC_reference (x
, NULL_RTX
);
7536 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7537 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7538 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7539 opnum
, (enum reload_type
) type
);
7547 /* Debug version of rs6000_legitimize_reload_address. */
7549 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7550 int opnum
, int type
,
7551 int ind_levels
, int *win
)
7553 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7556 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7557 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7558 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7562 fprintf (stderr
, "Same address returned\n");
7564 fprintf (stderr
, "NULL returned\n");
7567 fprintf (stderr
, "New address:\n");
7574 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7575 that is a valid memory address for an instruction.
7576 The MODE argument is the machine mode for the MEM expression
7577 that wants to use this address.
7579 On the RS/6000, there are four valid address: a SYMBOL_REF that
7580 refers to a constant pool entry of an address (or the sum of it
7581 plus a constant), a short (16-bit signed) constant plus a register,
7582 the sum of two registers, or a register indirect, possibly with an
7583 auto-increment. For DFmode, DDmode and DImode with a constant plus
7584 register, we must ensure that both words are addressable or PowerPC64
7585 with offset word aligned.
7587 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7588 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7589 because adjacent memory cells are accessed by adding word-sized offsets
7590 during assembly output. */
7592 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7594 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7596 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7597 if (VECTOR_MEM_ALTIVEC_P (mode
)
7598 && GET_CODE (x
) == AND
7599 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7600 && INTVAL (XEXP (x
, 1)) == -16)
7603 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7605 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7608 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7609 && mode_supports_pre_incdec_p (mode
)
7610 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7612 if (virtual_stack_registers_memory_p (x
))
7614 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7617 && legitimate_constant_pool_address_p (x
, mode
,
7618 reg_ok_strict
|| lra_in_progress
))
7620 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7621 allow register indirect addresses. This will allow the values to go in
7622 either GPRs or VSX registers without reloading. The vector types would
7623 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7624 somewhat split, in that some uses are GPR based, and some VSX based. */
7625 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7627 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7630 && GET_CODE (x
) == PLUS
7631 && GET_CODE (XEXP (x
, 0)) == REG
7632 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7633 || XEXP (x
, 0) == arg_pointer_rtx
)
7634 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7636 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7640 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7642 || (mode
!= DFmode
&& mode
!= DDmode
)
7643 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7644 && (TARGET_POWERPC64
|| mode
!= DImode
)
7645 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7647 && !avoiding_indexed_address_p (mode
)
7648 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7650 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7651 && mode_supports_pre_modify_p (mode
)
7652 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7653 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7654 reg_ok_strict
, false)
7655 || (!avoiding_indexed_address_p (mode
)
7656 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7657 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7659 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7664 /* Debug version of rs6000_legitimate_address_p. */
7666 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7669 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7671 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7672 "strict = %d, reload = %s, code = %s\n",
7673 ret
? "true" : "false",
7674 GET_MODE_NAME (mode
),
7678 : (reload_in_progress
? "progress" : "before")),
7679 GET_RTX_NAME (GET_CODE (x
)));
7685 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7688 rs6000_mode_dependent_address_p (const_rtx addr
,
7689 addr_space_t as ATTRIBUTE_UNUSED
)
7691 return rs6000_mode_dependent_address_ptr (addr
);
7694 /* Go to LABEL if ADDR (a legitimate address expression)
7695 has an effect that depends on the machine mode it is used for.
7697 On the RS/6000 this is true of all integral offsets (since AltiVec
7698 and VSX modes don't allow them) or is a pre-increment or decrement.
7700 ??? Except that due to conceptual problems in offsettable_address_p
7701 we can't really report the problems of integral offsets. So leave
7702 this assuming that the adjustable offset must be valid for the
7703 sub-words of a TFmode operand, which is what we had before. */
7706 rs6000_mode_dependent_address (const_rtx addr
)
7708 switch (GET_CODE (addr
))
7711 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7712 is considered a legitimate address before reload, so there
7713 are no offset restrictions in that case. Note that this
7714 condition is safe in strict mode because any address involving
7715 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7716 been rejected as illegitimate. */
7717 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7718 && XEXP (addr
, 0) != arg_pointer_rtx
7719 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7721 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7722 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7727 /* Anything in the constant pool is sufficiently aligned that
7728 all bytes have the same high part address. */
7729 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7731 /* Auto-increment cases are now treated generically in recog.c. */
7733 return TARGET_UPDATE
;
7735 /* AND is only allowed in Altivec loads. */
7746 /* Debug version of rs6000_mode_dependent_address. */
7748 rs6000_debug_mode_dependent_address (const_rtx addr
)
7750 bool ret
= rs6000_mode_dependent_address (addr
);
7752 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7753 ret
? "true" : "false");
7759 /* Implement FIND_BASE_TERM. */
7762 rs6000_find_base_term (rtx op
)
7767 if (GET_CODE (base
) == CONST
)
7768 base
= XEXP (base
, 0);
7769 if (GET_CODE (base
) == PLUS
)
7770 base
= XEXP (base
, 0);
7771 if (GET_CODE (base
) == UNSPEC
)
7772 switch (XINT (base
, 1))
7775 case UNSPEC_MACHOPIC_OFFSET
:
7776 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7777 for aliasing purposes. */
7778 return XVECEXP (base
, 0, 0);
7784 /* More elaborate version of recog's offsettable_memref_p predicate
7785 that works around the ??? note of rs6000_mode_dependent_address.
7786 In particular it accepts
7788 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7790 in 32-bit mode, that the recog predicate rejects. */
7793 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7800 /* First mimic offsettable_memref_p. */
7801 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7804 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7805 the latter predicate knows nothing about the mode of the memory
7806 reference and, therefore, assumes that it is the largest supported
7807 mode (TFmode). As a consequence, legitimate offsettable memory
7808 references are rejected. rs6000_legitimate_offset_address_p contains
7809 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7810 at least with a little bit of help here given that we know the
7811 actual registers used. */
7812 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7813 || GET_MODE_SIZE (reg_mode
) == 4);
7814 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7818 /* Change register usage conditional on target flags. */
7820 rs6000_conditional_register_usage (void)
7824 if (TARGET_DEBUG_TARGET
)
7825 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7827 /* Set MQ register fixed (already call_used) so that it will not be
7831 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7833 fixed_regs
[13] = call_used_regs
[13]
7834 = call_really_used_regs
[13] = 1;
7836 /* Conditionally disable FPRs. */
7837 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7838 for (i
= 32; i
< 64; i
++)
7839 fixed_regs
[i
] = call_used_regs
[i
]
7840 = call_really_used_regs
[i
] = 1;
7842 /* The TOC register is not killed across calls in a way that is
7843 visible to the compiler. */
7844 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7845 call_really_used_regs
[2] = 0;
7847 if (DEFAULT_ABI
== ABI_V4
7848 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7850 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7852 if (DEFAULT_ABI
== ABI_V4
7853 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7855 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7856 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7857 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7859 if (DEFAULT_ABI
== ABI_DARWIN
7860 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7861 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7862 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7863 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7865 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7866 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7867 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7871 global_regs
[SPEFSCR_REGNO
] = 1;
7872 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7873 registers in prologues and epilogues. We no longer use r14
7874 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7875 pool for link-compatibility with older versions of GCC. Once
7876 "old" code has died out, we can return r14 to the allocation
7879 = call_used_regs
[14]
7880 = call_really_used_regs
[14] = 1;
7883 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7885 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7886 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7887 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7890 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7891 global_regs
[VSCR_REGNO
] = 1;
7893 if (TARGET_ALTIVEC_ABI
)
7895 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7896 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7898 /* AIX reserves VR20:31 in non-extended ABI mode. */
7900 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7901 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7906 /* Output insns to set DEST equal to the constant SOURCE as a series of
7907 lis, ori and shl instructions and return TRUE. */
7910 rs6000_emit_set_const (rtx dest
, rtx source
)
7912 enum machine_mode mode
= GET_MODE (dest
);
7917 gcc_checking_assert (CONST_INT_P (source
));
7918 c
= INTVAL (source
);
7923 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7927 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7929 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (temp
),
7930 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
7931 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7932 gen_rtx_IOR (SImode
, copy_rtx (temp
),
7933 GEN_INT (c
& 0xffff))));
7937 if (!TARGET_POWERPC64
)
7941 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
7943 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
7945 emit_move_insn (hi
, GEN_INT (c
>> 32));
7946 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
7947 emit_move_insn (lo
, GEN_INT (c
));
7950 rs6000_emit_set_long_const (dest
, c
);
7957 insn
= get_last_insn ();
7958 set
= single_set (insn
);
7959 if (! CONSTANT_P (SET_SRC (set
)))
7960 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
7965 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
7966 Output insns to set DEST equal to the constant C as a series of
7967 lis, ori and shl instructions. */
7970 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
7973 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7983 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7984 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7985 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7987 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7988 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7990 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
7992 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
7993 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
7995 emit_move_insn (dest
,
7996 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7999 else if (ud3
== 0 && ud4
== 0)
8001 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8003 gcc_assert (ud2
& 0x8000);
8004 emit_move_insn (copy_rtx (temp
),
8005 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8007 emit_move_insn (copy_rtx (temp
),
8008 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8010 emit_move_insn (dest
,
8011 gen_rtx_ZERO_EXTEND (DImode
,
8012 gen_lowpart (SImode
,
8015 else if ((ud4
== 0xffff && (ud3
& 0x8000))
8016 || (ud4
== 0 && ! (ud3
& 0x8000)))
8018 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8020 emit_move_insn (copy_rtx (temp
),
8021 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
8023 emit_move_insn (copy_rtx (temp
),
8024 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8026 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8027 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8030 emit_move_insn (dest
,
8031 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8036 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8038 emit_move_insn (copy_rtx (temp
),
8039 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
8041 emit_move_insn (copy_rtx (temp
),
8042 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8045 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
8046 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8049 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8050 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8051 GEN_INT (ud2
<< 16)));
8053 emit_move_insn (dest
,
8054 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8059 /* Helper for the following. Get rid of [r+r] memory refs
8060 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8063 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
8065 if (reload_in_progress
)
8068 if (GET_CODE (operands
[0]) == MEM
8069 && GET_CODE (XEXP (operands
[0], 0)) != REG
8070 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
8071 GET_MODE (operands
[0]), false))
8073 = replace_equiv_address (operands
[0],
8074 copy_addr_to_reg (XEXP (operands
[0], 0)));
8076 if (GET_CODE (operands
[1]) == MEM
8077 && GET_CODE (XEXP (operands
[1], 0)) != REG
8078 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
8079 GET_MODE (operands
[1]), false))
8081 = replace_equiv_address (operands
[1],
8082 copy_addr_to_reg (XEXP (operands
[1], 0)));
8085 /* Generate a vector of constants to permute MODE for a little-endian
8086 storage operation by swapping the two halves of a vector. */
8088 rs6000_const_vec (enum machine_mode mode
)
8116 v
= rtvec_alloc (subparts
);
8118 for (i
= 0; i
< subparts
/ 2; ++i
)
8119 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8120 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8121 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8126 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8127 for a VSX load or store operation. */
8129 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
8131 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8132 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8135 /* Emit a little-endian load from vector memory location SOURCE to VSX
8136 register DEST in mode MODE. The load is done with two permuting
8137 insn's that represent an lxvd2x and xxpermdi. */
8139 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
8141 rtx tmp
, permute_mem
, permute_reg
;
8143 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8145 if (mode
== TImode
|| mode
== V1TImode
)
8148 dest
= gen_lowpart (V2DImode
, dest
);
8149 source
= adjust_address (source
, V2DImode
, 0);
8152 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8153 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8154 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8155 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
8156 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
8159 /* Emit a little-endian store to vector memory location DEST from VSX
8160 register SOURCE in mode MODE. The store is done with two permuting
8161 insn's that represent an xxpermdi and an stxvd2x. */
8163 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
8165 rtx tmp
, permute_src
, permute_tmp
;
8167 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8169 if (mode
== TImode
|| mode
== V1TImode
)
8172 dest
= adjust_address (dest
, V2DImode
, 0);
8173 source
= gen_lowpart (V2DImode
, source
);
8176 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8177 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8178 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8179 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
8180 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
8183 /* Emit a sequence representing a little-endian VSX load or store,
8184 moving data from SOURCE to DEST in mode MODE. This is done
8185 separately from rs6000_emit_move to ensure it is called only
8186 during expand. LE VSX loads and stores introduced later are
8187 handled with a split. The expand-time RTL generation allows
8188 us to optimize away redundant pairs of register-permutes. */
8190 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
8192 gcc_assert (!BYTES_BIG_ENDIAN
8193 && VECTOR_MEM_VSX_P (mode
)
8194 && !gpr_or_gpr_p (dest
, source
)
8195 && (MEM_P (source
) ^ MEM_P (dest
)));
8199 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8200 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8204 if (!REG_P (source
))
8205 source
= force_reg (mode
, source
);
8206 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8210 /* Emit a move from SOURCE to DEST in mode MODE. */
8212 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8216 operands
[1] = source
;
8218 if (TARGET_DEBUG_ADDR
)
8221 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8222 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8223 GET_MODE_NAME (mode
),
8226 can_create_pseudo_p ());
8228 fprintf (stderr
, "source:\n");
8232 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8233 if (CONST_WIDE_INT_P (operands
[1])
8234 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8236 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8240 /* Check if GCC is setting up a block move that will end up using FP
8241 registers as temporaries. We must make sure this is acceptable. */
8242 if (GET_CODE (operands
[0]) == MEM
8243 && GET_CODE (operands
[1]) == MEM
8245 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8246 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8247 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8248 ? 32 : MEM_ALIGN (operands
[0])))
8249 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8251 : MEM_ALIGN (operands
[1]))))
8252 && ! MEM_VOLATILE_P (operands
[0])
8253 && ! MEM_VOLATILE_P (operands
[1]))
8255 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8256 adjust_address (operands
[1], SImode
, 0));
8257 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8258 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8262 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8263 && !gpc_reg_operand (operands
[1], mode
))
8264 operands
[1] = force_reg (mode
, operands
[1]);
8266 /* Recognize the case where operand[1] is a reference to thread-local
8267 data and load its address to a register. */
8268 if (tls_referenced_p (operands
[1]))
8270 enum tls_model model
;
8271 rtx tmp
= operands
[1];
8274 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8276 addend
= XEXP (XEXP (tmp
, 0), 1);
8277 tmp
= XEXP (XEXP (tmp
, 0), 0);
8280 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8281 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8282 gcc_assert (model
!= 0);
8284 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8287 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8288 tmp
= force_operand (tmp
, operands
[0]);
8293 /* Handle the case where reload calls us with an invalid address. */
8294 if (reload_in_progress
&& mode
== Pmode
8295 && (! general_operand (operands
[1], mode
)
8296 || ! nonimmediate_operand (operands
[0], mode
)))
8299 /* 128-bit constant floating-point values on Darwin should really be
8300 loaded as two parts. */
8301 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8302 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8304 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8305 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8307 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8308 GET_MODE_SIZE (DFmode
)),
8309 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8310 GET_MODE_SIZE (DFmode
)),
8315 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8316 cfun
->machine
->sdmode_stack_slot
=
8317 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8320 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
8321 p1:SD) if p1 is not of floating point class and p0 is spilled as
8322 we can have no analogous movsd_store for this. */
8323 if (lra_in_progress
&& mode
== DDmode
8324 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8325 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8326 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
8327 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
8330 int regno
= REGNO (SUBREG_REG (operands
[1]));
8332 if (regno
>= FIRST_PSEUDO_REGISTER
)
8334 cl
= reg_preferred_class (regno
);
8335 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
8337 if (regno
>= 0 && ! FP_REGNO_P (regno
))
8340 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
8341 operands
[1] = SUBREG_REG (operands
[1]);
8346 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8347 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8348 && (REG_P (operands
[1])
8349 || (GET_CODE (operands
[1]) == SUBREG
8350 && REG_P (SUBREG_REG (operands
[1])))))
8352 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8353 ? SUBREG_REG (operands
[1]) : operands
[1]);
8356 if (regno
>= FIRST_PSEUDO_REGISTER
)
8358 cl
= reg_preferred_class (regno
);
8359 gcc_assert (cl
!= NO_REGS
);
8360 regno
= ira_class_hard_regs
[cl
][0];
8362 if (FP_REGNO_P (regno
))
8364 if (GET_MODE (operands
[0]) != DDmode
)
8365 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8366 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8368 else if (INT_REGNO_P (regno
))
8369 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8374 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
8375 p:DD)) if p0 is not of floating point class and p1 is spilled as
8376 we can have no analogous movsd_load for this. */
8377 if (lra_in_progress
&& mode
== DDmode
8378 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
8379 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
8380 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8381 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8384 int regno
= REGNO (SUBREG_REG (operands
[0]));
8386 if (regno
>= FIRST_PSEUDO_REGISTER
)
8388 cl
= reg_preferred_class (regno
);
8389 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
8391 if (regno
>= 0 && ! FP_REGNO_P (regno
))
8394 operands
[0] = SUBREG_REG (operands
[0]);
8395 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
8400 && (REG_P (operands
[0])
8401 || (GET_CODE (operands
[0]) == SUBREG
8402 && REG_P (SUBREG_REG (operands
[0]))))
8403 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8404 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8406 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8407 ? SUBREG_REG (operands
[0]) : operands
[0]);
8410 if (regno
>= FIRST_PSEUDO_REGISTER
)
8412 cl
= reg_preferred_class (regno
);
8413 gcc_assert (cl
!= NO_REGS
);
8414 regno
= ira_class_hard_regs
[cl
][0];
8416 if (FP_REGNO_P (regno
))
8418 if (GET_MODE (operands
[1]) != DDmode
)
8419 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8420 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8422 else if (INT_REGNO_P (regno
))
8423 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8429 if (reload_in_progress
8431 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8432 && MEM_P (operands
[0])
8433 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8434 && REG_P (operands
[1]))
8436 if (FP_REGNO_P (REGNO (operands
[1])))
8438 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8439 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8440 emit_insn (gen_movsd_store (mem
, operands
[1]));
8442 else if (INT_REGNO_P (REGNO (operands
[1])))
8444 rtx mem
= operands
[0];
8445 if (BYTES_BIG_ENDIAN
)
8446 mem
= adjust_address_nv (mem
, mode
, 4);
8447 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8448 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8454 if (reload_in_progress
8456 && REG_P (operands
[0])
8457 && MEM_P (operands
[1])
8458 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8459 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8461 if (FP_REGNO_P (REGNO (operands
[0])))
8463 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8464 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8465 emit_insn (gen_movsd_load (operands
[0], mem
));
8467 else if (INT_REGNO_P (REGNO (operands
[0])))
8469 rtx mem
= operands
[1];
8470 if (BYTES_BIG_ENDIAN
)
8471 mem
= adjust_address_nv (mem
, mode
, 4);
8472 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8473 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8480 /* FIXME: In the long term, this switch statement should go away
8481 and be replaced by a sequence of tests based on things like
8487 if (CONSTANT_P (operands
[1])
8488 && GET_CODE (operands
[1]) != CONST_INT
)
8489 operands
[1] = force_const_mem (mode
, operands
[1]);
8494 rs6000_eliminate_indexed_memrefs (operands
);
8501 if (CONSTANT_P (operands
[1])
8502 && ! easy_fp_constant (operands
[1], mode
))
8503 operands
[1] = force_const_mem (mode
, operands
[1]);
8517 if (CONSTANT_P (operands
[1])
8518 && !easy_vector_constant (operands
[1], mode
))
8519 operands
[1] = force_const_mem (mode
, operands
[1]);
8524 /* Use default pattern for address of ELF small data */
8527 && DEFAULT_ABI
== ABI_V4
8528 && (GET_CODE (operands
[1]) == SYMBOL_REF
8529 || GET_CODE (operands
[1]) == CONST
)
8530 && small_data_operand (operands
[1], mode
))
8532 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8536 if (DEFAULT_ABI
== ABI_V4
8537 && mode
== Pmode
&& mode
== SImode
8538 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8540 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8544 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8548 && CONSTANT_P (operands
[1])
8549 && GET_CODE (operands
[1]) != HIGH
8550 && GET_CODE (operands
[1]) != CONST_INT
)
8552 rtx target
= (!can_create_pseudo_p ()
8554 : gen_reg_rtx (mode
));
8556 /* If this is a function address on -mcall-aixdesc,
8557 convert it to the address of the descriptor. */
8558 if (DEFAULT_ABI
== ABI_AIX
8559 && GET_CODE (operands
[1]) == SYMBOL_REF
8560 && XSTR (operands
[1], 0)[0] == '.')
8562 const char *name
= XSTR (operands
[1], 0);
8564 while (*name
== '.')
8566 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8567 CONSTANT_POOL_ADDRESS_P (new_ref
)
8568 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8569 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8570 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8571 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8572 operands
[1] = new_ref
;
8575 if (DEFAULT_ABI
== ABI_DARWIN
)
8578 if (MACHO_DYNAMIC_NO_PIC_P
)
8580 /* Take care of any required data indirection. */
8581 operands
[1] = rs6000_machopic_legitimize_pic_address (
8582 operands
[1], mode
, operands
[0]);
8583 if (operands
[0] != operands
[1])
8584 emit_insn (gen_rtx_SET (VOIDmode
,
8585 operands
[0], operands
[1]));
8589 emit_insn (gen_macho_high (target
, operands
[1]));
8590 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8594 emit_insn (gen_elf_high (target
, operands
[1]));
8595 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8599 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8600 and we have put it in the TOC, we just need to make a TOC-relative
8603 && GET_CODE (operands
[1]) == SYMBOL_REF
8604 && use_toc_relative_ref (operands
[1]))
8605 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8606 else if (mode
== Pmode
8607 && CONSTANT_P (operands
[1])
8608 && GET_CODE (operands
[1]) != HIGH
8609 && ((GET_CODE (operands
[1]) != CONST_INT
8610 && ! easy_fp_constant (operands
[1], mode
))
8611 || (GET_CODE (operands
[1]) == CONST_INT
8612 && (num_insns_constant (operands
[1], mode
)
8613 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8614 || (GET_CODE (operands
[0]) == REG
8615 && FP_REGNO_P (REGNO (operands
[0]))))
8616 && !toc_relative_expr_p (operands
[1], false)
8617 && (TARGET_CMODEL
== CMODEL_SMALL
8618 || can_create_pseudo_p ()
8619 || (REG_P (operands
[0])
8620 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8624 /* Darwin uses a special PIC legitimizer. */
8625 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8628 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8630 if (operands
[0] != operands
[1])
8631 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8636 /* If we are to limit the number of things we put in the TOC and
8637 this is a symbol plus a constant we can add in one insn,
8638 just put the symbol in the TOC and add the constant. Don't do
8639 this if reload is in progress. */
8640 if (GET_CODE (operands
[1]) == CONST
8641 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8642 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8643 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8644 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8645 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8646 && ! side_effects_p (operands
[0]))
8649 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8650 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8652 sym
= force_reg (mode
, sym
);
8653 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8657 operands
[1] = force_const_mem (mode
, operands
[1]);
8660 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8661 && constant_pool_expr_p (XEXP (operands
[1], 0))
8662 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8663 get_pool_constant (XEXP (operands
[1], 0)),
8664 get_pool_mode (XEXP (operands
[1], 0))))
8666 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8668 operands
[1] = gen_const_mem (mode
, tocref
);
8669 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8675 if (!VECTOR_MEM_VSX_P (TImode
))
8676 rs6000_eliminate_indexed_memrefs (operands
);
8680 rs6000_eliminate_indexed_memrefs (operands
);
8684 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8687 /* Above, we may have called force_const_mem which may have returned
8688 an invalid address. If we can, fix this up; otherwise, reload will
8689 have to deal with it. */
8690 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8691 operands
[1] = validize_mem (operands
[1]);
8694 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8697 /* Return true if a structure, union or array containing FIELD should be
8698 accessed using `BLKMODE'.
8700 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8701 entire thing in a DI and use subregs to access the internals.
8702 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8703 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8704 best thing to do is set structs to BLKmode and avoid Severe Tire
8707 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8708 fit into 1, whereas DI still needs two. */
8711 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8713 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8714 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8717 /* Nonzero if we can use a floating-point register to pass this arg. */
8718 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8719 (SCALAR_FLOAT_MODE_P (MODE) \
8720 && (CUM)->fregno <= FP_ARG_MAX_REG \
8721 && TARGET_HARD_FLOAT && TARGET_FPRS)
8723 /* Nonzero if we can use an AltiVec register to pass this arg. */
8724 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8725 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8726 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8727 && TARGET_ALTIVEC_ABI \
8730 /* Walk down the type tree of TYPE counting consecutive base elements.
8731 If *MODEP is VOIDmode, then set it to the first valid floating point
8732 or vector type. If a non-floating point or vector type is found, or
8733 if a floating point or vector type that doesn't match a non-VOIDmode
8734 *MODEP is found, then return -1, otherwise return the count in the
8738 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8740 enum machine_mode mode
;
8743 switch (TREE_CODE (type
))
8746 mode
= TYPE_MODE (type
);
8747 if (!SCALAR_FLOAT_MODE_P (mode
))
8750 if (*modep
== VOIDmode
)
8759 mode
= TYPE_MODE (TREE_TYPE (type
));
8760 if (!SCALAR_FLOAT_MODE_P (mode
))
8763 if (*modep
== VOIDmode
)
8772 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8775 /* Use V4SImode as representative of all 128-bit vector types. */
8776 size
= int_size_in_bytes (type
);
8786 if (*modep
== VOIDmode
)
8789 /* Vector modes are considered to be opaque: two vectors are
8790 equivalent for the purposes of being homogeneous aggregates
8791 if they are the same size. */
8800 tree index
= TYPE_DOMAIN (type
);
8802 /* Can't handle incomplete types nor sizes that are not
8804 if (!COMPLETE_TYPE_P (type
)
8805 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8808 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8811 || !TYPE_MAX_VALUE (index
)
8812 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
8813 || !TYPE_MIN_VALUE (index
)
8814 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
8818 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
8819 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
8821 /* There must be no padding. */
8822 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8834 /* Can't handle incomplete types nor sizes that are not
8836 if (!COMPLETE_TYPE_P (type
)
8837 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8840 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8842 if (TREE_CODE (field
) != FIELD_DECL
)
8845 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8851 /* There must be no padding. */
8852 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8859 case QUAL_UNION_TYPE
:
8861 /* These aren't very interesting except in a degenerate case. */
8866 /* Can't handle incomplete types nor sizes that are not
8868 if (!COMPLETE_TYPE_P (type
)
8869 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8872 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8874 if (TREE_CODE (field
) != FIELD_DECL
)
8877 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8880 count
= count
> sub_count
? count
: sub_count
;
8883 /* There must be no padding. */
8884 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8897 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8898 float or vector aggregate that shall be passed in FP/vector registers
8899 according to the ELFv2 ABI, return the homogeneous element mode in
8900 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8902 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8905 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8906 enum machine_mode
*elt_mode
,
8909 /* Note that we do not accept complex types at the top level as
8910 homogeneous aggregates; these types are handled via the
8911 targetm.calls.split_complex_arg mechanism. Complex types
8912 can be elements of homogeneous aggregates, however. */
8913 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8915 enum machine_mode field_mode
= VOIDmode
;
8916 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8918 if (field_count
> 0)
8920 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8921 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8923 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8924 up to AGGR_ARG_NUM_REG registers. */
8925 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8928 *elt_mode
= field_mode
;
8930 *n_elts
= field_count
;
8943 /* Return a nonzero value to say to return the function value in
8944 memory, just as large structures are always returned. TYPE will be
8945 the data type of the value, and FNTYPE will be the type of the
8946 function doing the returning, or @code{NULL} for libcalls.
8948 The AIX ABI for the RS/6000 specifies that all structures are
8949 returned in memory. The Darwin ABI does the same.
8951 For the Darwin 64 Bit ABI, a function result can be returned in
8952 registers or in memory, depending on the size of the return data
8953 type. If it is returned in registers, the value occupies the same
8954 registers as it would if it were the first and only function
8955 argument. Otherwise, the function places its result in memory at
8956 the location pointed to by GPR3.
8958 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8959 but a draft put them in memory, and GCC used to implement the draft
8960 instead of the final standard. Therefore, aix_struct_return
8961 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8962 compatibility can change DRAFT_V4_STRUCT_RET to override the
8963 default, and -m switches get the final word. See
8964 rs6000_option_override_internal for more details.
8966 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8967 long double support is enabled. These values are returned in memory.
8969 int_size_in_bytes returns -1 for variable size objects, which go in
8970 memory always. The cast to unsigned makes -1 > 8. */
8973 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8975 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8977 && rs6000_darwin64_abi
8978 && TREE_CODE (type
) == RECORD_TYPE
8979 && int_size_in_bytes (type
) > 0)
8981 CUMULATIVE_ARGS valcum
;
8985 valcum
.fregno
= FP_ARG_MIN_REG
;
8986 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8987 /* Do a trial code generation as if this were going to be passed
8988 as an argument; if any part goes in memory, we return NULL. */
8989 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8992 /* Otherwise fall through to more conventional ABI rules. */
8995 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8996 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
9000 /* The ELFv2 ABI returns aggregates up to 16B in registers */
9001 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
9002 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
9005 if (AGGREGATE_TYPE_P (type
)
9006 && (aix_struct_return
9007 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
9010 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9011 modes only exist for GCC vector types if -maltivec. */
9012 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
9013 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9016 /* Return synthetic vectors in memory. */
9017 if (TREE_CODE (type
) == VECTOR_TYPE
9018 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9020 static bool warned_for_return_big_vectors
= false;
9021 if (!warned_for_return_big_vectors
)
9023 warning (0, "GCC vector returned by reference: "
9024 "non-standard ABI extension with no compatibility guarantee");
9025 warned_for_return_big_vectors
= true;
9030 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
9036 /* Specify whether values returned in registers should be at the most
9037 significant end of a register. We want aggregates returned by
9038 value to match the way aggregates are passed to functions. */
9041 rs6000_return_in_msb (const_tree valtype
)
9043 return (DEFAULT_ABI
== ABI_ELFv2
9045 && AGGREGATE_TYPE_P (valtype
)
9046 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
9049 #ifdef HAVE_AS_GNU_ATTRIBUTE
9050 /* Return TRUE if a call to function FNDECL may be one that
9051 potentially affects the function calling ABI of the object file. */
9054 call_ABI_of_interest (tree fndecl
)
9056 if (symtab
->state
== EXPANSION
)
9058 struct cgraph_node
*c_node
;
9060 /* Libcalls are always interesting. */
9061 if (fndecl
== NULL_TREE
)
9064 /* Any call to an external function is interesting. */
9065 if (DECL_EXTERNAL (fndecl
))
9068 /* Interesting functions that we are emitting in this object file. */
9069 c_node
= cgraph_node::get (fndecl
);
9070 c_node
= c_node
->ultimate_alias_target ();
9071 return !c_node
->only_called_directly_p ();
9077 /* Initialize a variable CUM of type CUMULATIVE_ARGS
9078 for a call to a function whose data type is FNTYPE.
9079 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
9081 For incoming args we set the number of arguments in the prototype large
9082 so we never return a PARALLEL. */
9085 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
9086 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
9087 int libcall
, int n_named_args
,
9088 tree fndecl ATTRIBUTE_UNUSED
,
9089 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
9091 static CUMULATIVE_ARGS zero_cumulative
;
9093 *cum
= zero_cumulative
;
9095 cum
->fregno
= FP_ARG_MIN_REG
;
9096 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
9097 cum
->prototype
= (fntype
&& prototype_p (fntype
));
9098 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
9099 ? CALL_LIBCALL
: CALL_NORMAL
);
9100 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
9101 cum
->stdarg
= stdarg_p (fntype
);
9103 cum
->nargs_prototype
= 0;
9104 if (incoming
|| cum
->prototype
)
9105 cum
->nargs_prototype
= n_named_args
;
9107 /* Check for a longcall attribute. */
9108 if ((!fntype
&& rs6000_default_long_calls
)
9110 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
9111 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
9112 cum
->call_cookie
|= CALL_LONG
;
9114 if (TARGET_DEBUG_ARG
)
9116 fprintf (stderr
, "\ninit_cumulative_args:");
9119 tree ret_type
= TREE_TYPE (fntype
);
9120 fprintf (stderr
, " ret code = %s,",
9121 get_tree_code_name (TREE_CODE (ret_type
)));
9124 if (cum
->call_cookie
& CALL_LONG
)
9125 fprintf (stderr
, " longcall,");
9127 fprintf (stderr
, " proto = %d, nargs = %d\n",
9128 cum
->prototype
, cum
->nargs_prototype
);
9131 #ifdef HAVE_AS_GNU_ATTRIBUTE
9132 if (DEFAULT_ABI
== ABI_V4
)
9134 cum
->escapes
= call_ABI_of_interest (fndecl
);
9141 return_type
= TREE_TYPE (fntype
);
9142 return_mode
= TYPE_MODE (return_type
);
9145 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9147 if (return_type
!= NULL
)
9149 if (TREE_CODE (return_type
) == RECORD_TYPE
9150 && TYPE_TRANSPARENT_AGGR (return_type
))
9152 return_type
= TREE_TYPE (first_field (return_type
));
9153 return_mode
= TYPE_MODE (return_type
);
9155 if (AGGREGATE_TYPE_P (return_type
)
9156 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9158 rs6000_returns_struct
= true;
9160 if (SCALAR_FLOAT_MODE_P (return_mode
))
9161 rs6000_passes_float
= true;
9162 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9163 || SPE_VECTOR_MODE (return_mode
))
9164 rs6000_passes_vector
= true;
9171 && TARGET_ALTIVEC_ABI
9172 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9174 error ("cannot return value in vector register because"
9175 " altivec instructions are disabled, use -maltivec"
9180 /* Return true if TYPE must be passed on the stack and not in registers. */
9183 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
9185 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9186 return must_pass_in_stack_var_size (mode
, type
);
9188 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9191 /* If defined, a C expression which determines whether, and in which
9192 direction, to pad out an argument with extra space. The value
9193 should be of type `enum direction': either `upward' to pad above
9194 the argument, `downward' to pad below, or `none' to inhibit
9197 For the AIX ABI structs are always stored left shifted in their
9201 function_arg_padding (enum machine_mode mode
, const_tree type
)
9203 #ifndef AGGREGATE_PADDING_FIXED
9204 #define AGGREGATE_PADDING_FIXED 0
9206 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9207 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9210 if (!AGGREGATE_PADDING_FIXED
)
9212 /* GCC used to pass structures of the same size as integer types as
9213 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9214 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9215 passed padded downward, except that -mstrict-align further
9216 muddied the water in that multi-component structures of 2 and 4
9217 bytes in size were passed padded upward.
9219 The following arranges for best compatibility with previous
9220 versions of gcc, but removes the -mstrict-align dependency. */
9221 if (BYTES_BIG_ENDIAN
)
9223 HOST_WIDE_INT size
= 0;
9225 if (mode
== BLKmode
)
9227 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9228 size
= int_size_in_bytes (type
);
9231 size
= GET_MODE_SIZE (mode
);
9233 if (size
== 1 || size
== 2 || size
== 4)
9239 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9241 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9245 /* Fall back to the default. */
9246 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9249 /* If defined, a C expression that gives the alignment boundary, in bits,
9250 of an argument with the specified mode and type. If it is not defined,
9251 PARM_BOUNDARY is used for all arguments.
9253 V.4 wants long longs and doubles to be double word aligned. Just
9254 testing the mode size is a boneheaded way to do this as it means
9255 that other types such as complex int are also double word aligned.
9256 However, we're stuck with this because changing the ABI might break
9257 existing library interfaces.
9259 Doubleword align SPE vectors.
9260 Quadword align Altivec/VSX vectors.
9261 Quadword align large synthetic vector types. */
9264 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9266 enum machine_mode elt_mode
;
9269 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9271 if (DEFAULT_ABI
== ABI_V4
9272 && (GET_MODE_SIZE (mode
) == 8
9273 || (TARGET_HARD_FLOAT
9275 && (mode
== TFmode
|| mode
== TDmode
))))
9277 else if (SPE_VECTOR_MODE (mode
)
9278 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9279 && int_size_in_bytes (type
) >= 8
9280 && int_size_in_bytes (type
) < 16))
9282 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9283 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9284 && int_size_in_bytes (type
) >= 16))
9287 /* Aggregate types that need > 8 byte alignment are quadword-aligned
9288 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
9289 -mcompat-align-parm is used. */
9290 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
9291 || DEFAULT_ABI
== ABI_ELFv2
)
9292 && type
&& TYPE_ALIGN (type
) > 64)
9294 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
9295 or homogeneous float/vector aggregates here. We already handled
9296 vector aggregates above, but still need to check for float here. */
9297 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
9298 && !SCALAR_FLOAT_MODE_P (elt_mode
));
9300 /* We used to check for BLKmode instead of the above aggregate type
9301 check. Warn when this results in any difference to the ABI. */
9302 if (aggregate_p
!= (mode
== BLKmode
))
9305 if (!warned
&& warn_psabi
)
9308 inform (input_location
,
9309 "the ABI of passing aggregates with %d-byte alignment"
9310 " has changed in GCC 5",
9311 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
9319 /* Similar for the Darwin64 ABI. Note that for historical reasons we
9320 implement the "aggregate type" check as a BLKmode check here; this
9321 means certain aggregate types are in fact not aligned. */
9322 if (TARGET_MACHO
&& rs6000_darwin64_abi
9324 && type
&& TYPE_ALIGN (type
) > 64)
9327 return PARM_BOUNDARY
;
9330 /* The offset in words to the start of the parameter save area. */
9333 rs6000_parm_offset (void)
9335 return (DEFAULT_ABI
== ABI_V4
? 2
9336 : DEFAULT_ABI
== ABI_ELFv2
? 4
9340 /* For a function parm of MODE and TYPE, return the starting word in
9341 the parameter area. NWORDS of the parameter area are already used. */
9344 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9345 unsigned int nwords
)
9349 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9350 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9353 /* Compute the size (in words) of a function argument. */
9355 static unsigned long
9356 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9360 if (mode
!= BLKmode
)
9361 size
= GET_MODE_SIZE (mode
);
9363 size
= int_size_in_bytes (type
);
9366 return (size
+ 3) >> 2;
9368 return (size
+ 7) >> 3;
9371 /* Use this to flush pending int fields. */
9374 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9375 HOST_WIDE_INT bitpos
, int final
)
9377 unsigned int startbit
, endbit
;
9378 int intregs
, intoffset
;
9379 enum machine_mode mode
;
9381 /* Handle the situations where a float is taking up the first half
9382 of the GPR, and the other half is empty (typically due to
9383 alignment restrictions). We can detect this by a 8-byte-aligned
9384 int field, or by seeing that this is the final flush for this
9385 argument. Count the word and continue on. */
9386 if (cum
->floats_in_gpr
== 1
9387 && (cum
->intoffset
% 64 == 0
9388 || (cum
->intoffset
== -1 && final
)))
9391 cum
->floats_in_gpr
= 0;
9394 if (cum
->intoffset
== -1)
9397 intoffset
= cum
->intoffset
;
9398 cum
->intoffset
= -1;
9399 cum
->floats_in_gpr
= 0;
9401 if (intoffset
% BITS_PER_WORD
!= 0)
9403 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9405 if (mode
== BLKmode
)
9407 /* We couldn't find an appropriate mode, which happens,
9408 e.g., in packed structs when there are 3 bytes to load.
9409 Back intoffset back to the beginning of the word in this
9411 intoffset
= intoffset
& -BITS_PER_WORD
;
9415 startbit
= intoffset
& -BITS_PER_WORD
;
9416 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9417 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9418 cum
->words
+= intregs
;
9419 /* words should be unsigned. */
9420 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9422 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9427 /* The darwin64 ABI calls for us to recurse down through structs,
9428 looking for elements passed in registers. Unfortunately, we have
9429 to track int register count here also because of misalignments
9430 in powerpc alignment mode. */
9433 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9435 HOST_WIDE_INT startbitpos
)
9439 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9440 if (TREE_CODE (f
) == FIELD_DECL
)
9442 HOST_WIDE_INT bitpos
= startbitpos
;
9443 tree ftype
= TREE_TYPE (f
);
9444 enum machine_mode mode
;
9445 if (ftype
== error_mark_node
)
9447 mode
= TYPE_MODE (ftype
);
9449 if (DECL_SIZE (f
) != 0
9450 && tree_fits_uhwi_p (bit_position (f
)))
9451 bitpos
+= int_bit_position (f
);
9453 /* ??? FIXME: else assume zero offset. */
9455 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9456 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9457 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9459 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9460 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9461 cum
->fregno
+= n_fpregs
;
9462 /* Single-precision floats present a special problem for
9463 us, because they are smaller than an 8-byte GPR, and so
9464 the structure-packing rules combined with the standard
9465 varargs behavior mean that we want to pack float/float
9466 and float/int combinations into a single register's
9467 space. This is complicated by the arg advance flushing,
9468 which works on arbitrarily large groups of int-type
9472 if (cum
->floats_in_gpr
== 1)
9474 /* Two floats in a word; count the word and reset
9477 cum
->floats_in_gpr
= 0;
9479 else if (bitpos
% 64 == 0)
9481 /* A float at the beginning of an 8-byte word;
9482 count it and put off adjusting cum->words until
9483 we see if a arg advance flush is going to do it
9485 cum
->floats_in_gpr
++;
9489 /* The float is at the end of a word, preceded
9490 by integer fields, so the arg advance flush
9491 just above has already set cum->words and
9492 everything is taken care of. */
9496 cum
->words
+= n_fpregs
;
9498 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9500 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9504 else if (cum
->intoffset
== -1)
9505 cum
->intoffset
= bitpos
;
9509 /* Check for an item that needs to be considered specially under the darwin 64
9510 bit ABI. These are record types where the mode is BLK or the structure is
9513 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9515 return rs6000_darwin64_abi
9516 && ((mode
== BLKmode
9517 && TREE_CODE (type
) == RECORD_TYPE
9518 && int_size_in_bytes (type
) > 0)
9519 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9520 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9523 /* Update the data in CUM to advance over an argument
9524 of mode MODE and data type TYPE.
9525 (TYPE is null for libcalls where that information may not be available.)
9527 Note that for args passed by reference, function_arg will be called
9528 with MODE and TYPE set to that of the pointer to the arg, not the arg
9532 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9533 const_tree type
, bool named
, int depth
)
9535 enum machine_mode elt_mode
;
9538 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9540 /* Only tick off an argument if we're not recursing. */
9542 cum
->nargs_prototype
--;
9544 #ifdef HAVE_AS_GNU_ATTRIBUTE
9545 if (DEFAULT_ABI
== ABI_V4
9548 if (SCALAR_FLOAT_MODE_P (mode
))
9549 rs6000_passes_float
= true;
9550 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9551 rs6000_passes_vector
= true;
9552 else if (SPE_VECTOR_MODE (mode
)
9554 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9555 rs6000_passes_vector
= true;
9559 if (TARGET_ALTIVEC_ABI
9560 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9561 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9562 && int_size_in_bytes (type
) == 16)))
9566 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9568 cum
->vregno
+= n_elts
;
9570 if (!TARGET_ALTIVEC
)
9571 error ("cannot pass argument in vector register because"
9572 " altivec instructions are disabled, use -maltivec"
9575 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9576 even if it is going to be passed in a vector register.
9577 Darwin does the same for variable-argument functions. */
9578 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9580 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9590 /* Vector parameters must be 16-byte aligned. In 32-bit
9591 mode this means we need to take into account the offset
9592 to the parameter save area. In 64-bit mode, they just
9593 have to start on an even word, since the parameter save
9594 area is 16-byte aligned. */
9596 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9598 align
= cum
->words
& 1;
9599 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9601 if (TARGET_DEBUG_ARG
)
9603 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9605 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9606 cum
->nargs_prototype
, cum
->prototype
,
9607 GET_MODE_NAME (mode
));
9611 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9613 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9616 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9618 int size
= int_size_in_bytes (type
);
9619 /* Variable sized types have size == -1 and are
9620 treated as if consisting entirely of ints.
9621 Pad to 16 byte boundary if needed. */
9622 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9623 && (cum
->words
% 2) != 0)
9625 /* For varargs, we can just go up by the size of the struct. */
9627 cum
->words
+= (size
+ 7) / 8;
9630 /* It is tempting to say int register count just goes up by
9631 sizeof(type)/8, but this is wrong in a case such as
9632 { int; double; int; } [powerpc alignment]. We have to
9633 grovel through the fields for these too. */
9635 cum
->floats_in_gpr
= 0;
9636 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9637 rs6000_darwin64_record_arg_advance_flush (cum
,
9638 size
* BITS_PER_UNIT
, 1);
9640 if (TARGET_DEBUG_ARG
)
9642 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9643 cum
->words
, TYPE_ALIGN (type
), size
);
9645 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9646 cum
->nargs_prototype
, cum
->prototype
,
9647 GET_MODE_NAME (mode
));
9650 else if (DEFAULT_ABI
== ABI_V4
)
9652 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9653 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9654 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9655 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9656 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9658 /* _Decimal128 must use an even/odd register pair. This assumes
9659 that the register number is odd when fregno is odd. */
9660 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9663 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9664 <= FP_ARG_V4_MAX_REG
)
9665 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9668 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9669 if (mode
== DFmode
|| mode
== TFmode
9670 || mode
== DDmode
|| mode
== TDmode
)
9671 cum
->words
+= cum
->words
& 1;
9672 cum
->words
+= rs6000_arg_size (mode
, type
);
9677 int n_words
= rs6000_arg_size (mode
, type
);
9678 int gregno
= cum
->sysv_gregno
;
9680 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9681 (r7,r8) or (r9,r10). As does any other 2 word item such
9682 as complex int due to a historical mistake. */
9684 gregno
+= (1 - gregno
) & 1;
9686 /* Multi-reg args are not split between registers and stack. */
9687 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9689 /* Long long and SPE vectors are aligned on the stack.
9690 So are other 2 word items such as complex int due to
9691 a historical mistake. */
9693 cum
->words
+= cum
->words
& 1;
9694 cum
->words
+= n_words
;
9697 /* Note: continuing to accumulate gregno past when we've started
9698 spilling to the stack indicates the fact that we've started
9699 spilling to the stack to expand_builtin_saveregs. */
9700 cum
->sysv_gregno
= gregno
+ n_words
;
9703 if (TARGET_DEBUG_ARG
)
9705 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9706 cum
->words
, cum
->fregno
);
9707 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9708 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9709 fprintf (stderr
, "mode = %4s, named = %d\n",
9710 GET_MODE_NAME (mode
), named
);
9715 int n_words
= rs6000_arg_size (mode
, type
);
9716 int start_words
= cum
->words
;
9717 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9719 cum
->words
= align_words
+ n_words
;
9721 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9722 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9724 /* _Decimal128 must be passed in an even/odd float register pair.
9725 This assumes that the register number is odd when fregno is
9727 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9729 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9732 if (TARGET_DEBUG_ARG
)
9734 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9735 cum
->words
, cum
->fregno
);
9736 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9737 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9738 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9739 named
, align_words
- start_words
, depth
);
9745 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9746 const_tree type
, bool named
)
9748 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9753 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9760 r1
= gen_rtx_REG (DImode
, gregno
);
9761 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9762 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9766 r1
= gen_rtx_REG (DImode
, gregno
);
9767 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9768 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9769 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9770 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9773 r1
= gen_rtx_REG (DImode
, gregno
);
9774 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9775 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9776 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9777 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9778 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9779 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9780 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9781 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9788 /* Determine where to put a SIMD argument on the SPE. */
9790 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9793 int gregno
= cum
->sysv_gregno
;
9795 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9796 are passed and returned in a pair of GPRs for ABI compatibility. */
9797 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9798 || mode
== DCmode
|| mode
== TCmode
))
9800 int n_words
= rs6000_arg_size (mode
, type
);
9802 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9804 gregno
+= (1 - gregno
) & 1;
9806 /* Multi-reg args are not split between registers and stack. */
9807 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9810 return spe_build_register_parallel (mode
, gregno
);
9814 int n_words
= rs6000_arg_size (mode
, type
);
9816 /* SPE vectors are put in odd registers. */
9817 if (n_words
== 2 && (gregno
& 1) == 0)
9820 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9823 enum machine_mode m
= SImode
;
9825 r1
= gen_rtx_REG (m
, gregno
);
9826 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9827 r2
= gen_rtx_REG (m
, gregno
+ 1);
9828 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9829 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9836 if (gregno
<= GP_ARG_MAX_REG
)
9837 return gen_rtx_REG (mode
, gregno
);
9843 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9844 structure between cum->intoffset and bitpos to integer registers. */
9847 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9848 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9850 enum machine_mode mode
;
9852 unsigned int startbit
, endbit
;
9853 int this_regno
, intregs
, intoffset
;
9856 if (cum
->intoffset
== -1)
9859 intoffset
= cum
->intoffset
;
9860 cum
->intoffset
= -1;
9862 /* If this is the trailing part of a word, try to only load that
9863 much into the register. Otherwise load the whole register. Note
9864 that in the latter case we may pick up unwanted bits. It's not a
9865 problem at the moment but may wish to revisit. */
9867 if (intoffset
% BITS_PER_WORD
!= 0)
9869 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9871 if (mode
== BLKmode
)
9873 /* We couldn't find an appropriate mode, which happens,
9874 e.g., in packed structs when there are 3 bytes to load.
9875 Back intoffset back to the beginning of the word in this
9877 intoffset
= intoffset
& -BITS_PER_WORD
;
9884 startbit
= intoffset
& -BITS_PER_WORD
;
9885 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9886 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9887 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9889 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9892 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9896 intoffset
/= BITS_PER_UNIT
;
9899 regno
= GP_ARG_MIN_REG
+ this_regno
;
9900 reg
= gen_rtx_REG (mode
, regno
);
9902 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9905 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9909 while (intregs
> 0);
9912 /* Recursive workhorse for the following. */
9915 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9916 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9921 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9922 if (TREE_CODE (f
) == FIELD_DECL
)
9924 HOST_WIDE_INT bitpos
= startbitpos
;
9925 tree ftype
= TREE_TYPE (f
);
9926 enum machine_mode mode
;
9927 if (ftype
== error_mark_node
)
9929 mode
= TYPE_MODE (ftype
);
9931 if (DECL_SIZE (f
) != 0
9932 && tree_fits_uhwi_p (bit_position (f
)))
9933 bitpos
+= int_bit_position (f
);
9935 /* ??? FIXME: else assume zero offset. */
9937 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9938 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9939 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9941 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9945 case SCmode
: mode
= SFmode
; break;
9946 case DCmode
: mode
= DFmode
; break;
9947 case TCmode
: mode
= TFmode
; break;
9951 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9952 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9954 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9955 && (mode
== TFmode
|| mode
== TDmode
));
9956 /* Long double or _Decimal128 split over regs and memory. */
9957 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9961 = gen_rtx_EXPR_LIST (VOIDmode
,
9962 gen_rtx_REG (mode
, cum
->fregno
++),
9963 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9964 if (mode
== TFmode
|| mode
== TDmode
)
9967 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9969 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9971 = gen_rtx_EXPR_LIST (VOIDmode
,
9972 gen_rtx_REG (mode
, cum
->vregno
++),
9973 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9975 else if (cum
->intoffset
== -1)
9976 cum
->intoffset
= bitpos
;
9980 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9981 the register(s) to be used for each field and subfield of a struct
9982 being passed by value, along with the offset of where the
9983 register's value may be found in the block. FP fields go in FP
9984 register, vector fields go in vector registers, and everything
9985 else goes in int registers, packed as in memory.
9987 This code is also used for function return values. RETVAL indicates
9988 whether this is the case.
9990 Much of this is taken from the SPARC V9 port, which has a similar
9991 calling convention. */
9994 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9995 bool named
, bool retval
)
9997 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9998 int k
= 1, kbase
= 1;
9999 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
10000 /* This is a copy; modifications are not visible to our caller. */
10001 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
10002 CUMULATIVE_ARGS
*cum
= ©_cum
;
10004 /* Pad to 16 byte boundary if needed. */
10005 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
10006 && (cum
->words
% 2) != 0)
10009 cum
->intoffset
= 0;
10010 cum
->use_stack
= 0;
10011 cum
->named
= named
;
10013 /* Put entries into rvec[] for individual FP and vector fields, and
10014 for the chunks of memory that go in int regs. Note we start at
10015 element 1; 0 is reserved for an indication of using memory, and
10016 may or may not be filled in below. */
10017 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
10018 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
10020 /* If any part of the struct went on the stack put all of it there.
10021 This hack is because the generic code for
10022 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
10023 parts of the struct are not at the beginning. */
10024 if (cum
->use_stack
)
10027 return NULL_RTX
; /* doesn't go in registers at all */
10029 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10031 if (k
> 1 || cum
->use_stack
)
10032 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
10037 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
10040 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
10045 rtx rvec
[GP_ARG_NUM_REG
+ 1];
10047 if (align_words
>= GP_ARG_NUM_REG
)
10050 n_units
= rs6000_arg_size (mode
, type
);
10052 /* Optimize the simple case where the arg fits in one gpr, except in
10053 the case of BLKmode due to assign_parms assuming that registers are
10054 BITS_PER_WORD wide. */
10056 || (n_units
== 1 && mode
!= BLKmode
))
10057 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10060 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
10061 /* Not all of the arg fits in gprs. Say that it goes in memory too,
10062 using a magic NULL_RTX component.
10063 This is not strictly correct. Only some of the arg belongs in
10064 memory, not all of it. However, the normal scheme using
10065 function_arg_partial_nregs can result in unusual subregs, eg.
10066 (subreg:SI (reg:DF) 4), which are not handled well. The code to
10067 store the whole arg to memory is often more efficient than code
10068 to store pieces, and we know that space is available in the right
10069 place for the whole arg. */
10070 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10075 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
10076 rtx off
= GEN_INT (i
++ * 4);
10077 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10079 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
10081 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10084 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
10085 but must also be copied into the parameter save area starting at
10086 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
10087 to the GPRs and/or memory. Return the number of elements used. */
10090 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
10091 int align_words
, rtx
*rvec
)
10095 if (align_words
< GP_ARG_NUM_REG
)
10097 int n_words
= rs6000_arg_size (mode
, type
);
10099 if (align_words
+ n_words
> GP_ARG_NUM_REG
10101 || (TARGET_32BIT
&& TARGET_POWERPC64
))
10103 /* If this is partially on the stack, then we only
10104 include the portion actually in registers here. */
10105 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10108 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10110 /* Not all of the arg fits in gprs. Say that it goes in memory
10111 too, using a magic NULL_RTX component. Also see comment in
10112 rs6000_mixed_function_arg for why the normal
10113 function_arg_partial_nregs scheme doesn't work in this case. */
10114 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10119 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10120 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
10121 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10123 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10127 /* The whole arg fits in gprs. */
10128 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10129 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
10134 /* It's entirely in memory. */
10135 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10141 /* RVEC is a vector of K components of an argument of mode MODE.
10142 Construct the final function_arg return value from it. */
10145 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
10147 gcc_assert (k
>= 1);
10149 /* Avoid returning a PARALLEL in the trivial cases. */
10152 if (XEXP (rvec
[0], 0) == NULL_RTX
)
10155 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
10156 return XEXP (rvec
[0], 0);
10159 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10162 /* Determine where to put an argument to a function.
10163 Value is zero to push the argument on the stack,
10164 or a hard register in which to store the argument.
10166 MODE is the argument's machine mode.
10167 TYPE is the data type of the argument (as a tree).
10168 This is null for libcalls where that information may
10170 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10171 the preceding args and about the function being called. It is
10172 not modified in this routine.
10173 NAMED is nonzero if this argument is a named parameter
10174 (otherwise it is an extra parameter matching an ellipsis).
10176 On RS/6000 the first eight words of non-FP are normally in registers
10177 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10178 Under V.4, the first 8 FP args are in registers.
10180 If this is floating-point and no prototype is specified, we use
10181 both an FP and integer register (or possibly FP reg and stack). Library
10182 functions (when CALL_LIBCALL is set) always have the proper types for args,
10183 so we can pass the FP value just in one register. emit_library_function
10184 doesn't support PARALLEL anyway.
10186 Note that for args passed by reference, function_arg will be called
10187 with MODE and TYPE set to that of the pointer to the arg, not the arg
10191 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
10192 const_tree type
, bool named
)
10194 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10195 enum rs6000_abi abi
= DEFAULT_ABI
;
10196 enum machine_mode elt_mode
;
10199 /* Return a marker to indicate whether CR1 needs to set or clear the
10200 bit that V.4 uses to say fp args were passed in registers.
10201 Assume that we don't need the marker for software floating point,
10202 or compiler generated library calls. */
10203 if (mode
== VOIDmode
)
10206 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10208 || (cum
->nargs_prototype
< 0
10209 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10211 /* For the SPE, we need to crxor CR6 always. */
10212 if (TARGET_SPE_ABI
)
10213 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10214 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10215 return GEN_INT (cum
->call_cookie
10216 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10217 ? CALL_V4_SET_FP_ARGS
10218 : CALL_V4_CLEAR_FP_ARGS
));
10221 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10224 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10226 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10228 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10229 if (rslt
!= NULL_RTX
)
10231 /* Else fall through to usual handling. */
10234 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10236 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10240 /* Do we also need to pass this argument in the parameter
10242 if (TARGET_64BIT
&& ! cum
->prototype
)
10244 int align_words
= (cum
->words
+ 1) & ~1;
10245 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10248 /* Describe where this argument goes in the vector registers. */
10249 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
10251 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
10252 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10253 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10256 return rs6000_finish_function_arg (mode
, rvec
, k
);
10258 else if (TARGET_ALTIVEC_ABI
10259 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
10260 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10261 && int_size_in_bytes (type
) == 16)))
10263 if (named
|| abi
== ABI_V4
)
10267 /* Vector parameters to varargs functions under AIX or Darwin
10268 get passed in memory and possibly also in GPRs. */
10269 int align
, align_words
, n_words
;
10270 enum machine_mode part_mode
;
10272 /* Vector parameters must be 16-byte aligned. In 32-bit
10273 mode this means we need to take into account the offset
10274 to the parameter save area. In 64-bit mode, they just
10275 have to start on an even word, since the parameter save
10276 area is 16-byte aligned. */
10278 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10280 align
= cum
->words
& 1;
10281 align_words
= cum
->words
+ align
;
10283 /* Out of registers? Memory, then. */
10284 if (align_words
>= GP_ARG_NUM_REG
)
10287 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10288 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10290 /* The vector value goes in GPRs. Only the part of the
10291 value in GPRs is reported here. */
10293 n_words
= rs6000_arg_size (mode
, type
);
10294 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10295 /* Fortunately, there are only two possibilities, the value
10296 is either wholly in GPRs or half in GPRs and half not. */
10297 part_mode
= DImode
;
10299 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10302 else if (TARGET_SPE_ABI
&& TARGET_SPE
10303 && (SPE_VECTOR_MODE (mode
)
10304 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10307 || mode
== TCmode
))))
10308 return rs6000_spe_function_arg (cum
, mode
, type
);
10310 else if (abi
== ABI_V4
)
10312 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10313 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10314 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10315 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10316 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10318 /* _Decimal128 must use an even/odd register pair. This assumes
10319 that the register number is odd when fregno is odd. */
10320 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10323 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10324 <= FP_ARG_V4_MAX_REG
)
10325 return gen_rtx_REG (mode
, cum
->fregno
);
10331 int n_words
= rs6000_arg_size (mode
, type
);
10332 int gregno
= cum
->sysv_gregno
;
10334 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10335 (r7,r8) or (r9,r10). As does any other 2 word item such
10336 as complex int due to a historical mistake. */
10338 gregno
+= (1 - gregno
) & 1;
10340 /* Multi-reg args are not split between registers and stack. */
10341 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10344 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10345 return rs6000_mixed_function_arg (mode
, type
,
10346 gregno
- GP_ARG_MIN_REG
);
10347 return gen_rtx_REG (mode
, gregno
);
10352 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10354 /* _Decimal128 must be passed in an even/odd float register pair.
10355 This assumes that the register number is odd when fregno is odd. */
10356 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10359 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10361 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10364 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10367 /* Do we also need to pass this argument in the parameter
10369 if (type
&& (cum
->nargs_prototype
<= 0
10370 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10371 && TARGET_XL_COMPAT
10372 && align_words
>= GP_ARG_NUM_REG
)))
10373 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10375 /* Describe where this argument goes in the fprs. */
10376 for (i
= 0; i
< n_elts
10377 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10379 /* Check if the argument is split over registers and memory.
10380 This can only ever happen for long double or _Decimal128;
10381 complex types are handled via split_complex_arg. */
10382 enum machine_mode fmode
= elt_mode
;
10383 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10385 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10386 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10389 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10390 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10391 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10394 /* If there were not enough FPRs to hold the argument, the rest
10395 usually goes into memory. However, if the current position
10396 is still within the register parameter area, a portion may
10397 actually have to go into GPRs.
10399 Note that it may happen that the portion of the argument
10400 passed in the first "half" of the first GPR was already
10401 passed in the last FPR as well.
10403 For unnamed arguments, we already set up GPRs to cover the
10404 whole argument in rs6000_psave_function_arg, so there is
10405 nothing further to do at this point. */
10406 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
10407 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
10408 && cum
->nargs_prototype
> 0)
10410 static bool warned
;
10412 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10413 int n_words
= rs6000_arg_size (mode
, type
);
10415 align_words
+= fpr_words
;
10416 n_words
-= fpr_words
;
10420 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10421 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
10422 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10424 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10426 if (!warned
&& warn_psabi
)
10429 inform (input_location
,
10430 "the ABI of passing homogeneous float aggregates"
10431 " has changed in GCC 5");
10435 return rs6000_finish_function_arg (mode
, rvec
, k
);
10437 else if (align_words
< GP_ARG_NUM_REG
)
10439 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10440 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10442 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10449 /* For an arg passed partly in registers and partly in memory, this is
10450 the number of bytes passed in registers. For args passed entirely in
10451 registers or entirely in memory, zero. When an arg is described by a
10452 PARALLEL, perhaps using more than one register type, this function
10453 returns the number of bytes used by the first element of the PARALLEL. */
10456 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10457 tree type
, bool named
)
10459 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10460 bool passed_in_gprs
= true;
10463 enum machine_mode elt_mode
;
10466 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10468 if (DEFAULT_ABI
== ABI_V4
)
10471 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10473 /* If we are passing this arg in the fixed parameter save area
10474 (gprs or memory) as well as VRs, we do not use the partial
10475 bytes mechanism; instead, rs6000_function_arg will return a
10476 PARALLEL including a memory element as necessary. */
10477 if (TARGET_64BIT
&& ! cum
->prototype
)
10480 /* Otherwise, we pass in VRs only. Check for partial copies. */
10481 passed_in_gprs
= false;
10482 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10483 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10486 /* In this complicated case we just disable the partial_nregs code. */
10487 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10490 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10492 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10494 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10496 /* If we are passing this arg in the fixed parameter save area
10497 (gprs or memory) as well as FPRs, we do not use the partial
10498 bytes mechanism; instead, rs6000_function_arg will return a
10499 PARALLEL including a memory element as necessary. */
10501 && (cum
->nargs_prototype
<= 0
10502 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10503 && TARGET_XL_COMPAT
10504 && align_words
>= GP_ARG_NUM_REG
)))
10507 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10508 passed_in_gprs
= false;
10509 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10511 /* Compute number of bytes / words passed in FPRs. If there
10512 is still space available in the register parameter area
10513 *after* that amount, a part of the argument will be passed
10514 in GPRs. In that case, the total amount passed in any
10515 registers is equal to the amount that would have been passed
10516 in GPRs if everything were passed there, so we fall back to
10517 the GPR code below to compute the appropriate value. */
10518 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10519 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10520 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
10522 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
10523 passed_in_gprs
= true;
10530 && align_words
< GP_ARG_NUM_REG
10531 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10532 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10534 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10535 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10540 /* A C expression that indicates when an argument must be passed by
10541 reference. If nonzero for an argument, a copy of that argument is
10542 made in memory and a pointer to the argument is passed instead of
10543 the argument itself. The pointer is passed in whatever way is
10544 appropriate for passing a pointer to that type.
10546 Under V.4, aggregates and long double are passed by reference.
10548 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10549 reference unless the AltiVec vector extension ABI is in force.
10551 As an extension to all ABIs, variable sized types are passed by
10555 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10556 enum machine_mode mode
, const_tree type
,
10557 bool named ATTRIBUTE_UNUSED
)
10559 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10561 if (TARGET_DEBUG_ARG
)
10562 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10569 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10571 if (TARGET_DEBUG_ARG
)
10572 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10576 if (int_size_in_bytes (type
) < 0)
10578 if (TARGET_DEBUG_ARG
)
10579 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10583 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10584 modes only exist for GCC vector types if -maltivec. */
10585 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10587 if (TARGET_DEBUG_ARG
)
10588 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10592 /* Pass synthetic vectors in memory. */
10593 if (TREE_CODE (type
) == VECTOR_TYPE
10594 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10596 static bool warned_for_pass_big_vectors
= false;
10597 if (TARGET_DEBUG_ARG
)
10598 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10599 if (!warned_for_pass_big_vectors
)
10601 warning (0, "GCC vector passed by reference: "
10602 "non-standard ABI extension with no compatibility guarantee");
10603 warned_for_pass_big_vectors
= true;
10611 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10612 already processes. Return true if the parameter must be passed
10613 (fully or partially) on the stack. */
10616 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10618 enum machine_mode mode
;
10622 /* Catch errors. */
10623 if (type
== NULL
|| type
== error_mark_node
)
10626 /* Handle types with no storage requirement. */
10627 if (TYPE_MODE (type
) == VOIDmode
)
10630 /* Handle complex types. */
10631 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10632 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10633 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10635 /* Handle transparent aggregates. */
10636 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10637 && TYPE_TRANSPARENT_AGGR (type
))
10638 type
= TREE_TYPE (first_field (type
));
10640 /* See if this arg was passed by invisible reference. */
10641 if (pass_by_reference (get_cumulative_args (args_so_far
),
10642 TYPE_MODE (type
), type
, true))
10643 type
= build_pointer_type (type
);
10645 /* Find mode as it is passed by the ABI. */
10646 unsignedp
= TYPE_UNSIGNED (type
);
10647 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10649 /* If we must pass in stack, we need a stack. */
10650 if (rs6000_must_pass_in_stack (mode
, type
))
10653 /* If there is no incoming register, we need a stack. */
10654 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10655 if (entry_parm
== NULL
)
10658 /* Likewise if we need to pass both in registers and on the stack. */
10659 if (GET_CODE (entry_parm
) == PARALLEL
10660 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10663 /* Also true if we're partially in registers and partially not. */
10664 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10667 /* Update info on where next arg arrives in registers. */
10668 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10672 /* Return true if FUN has no prototype, has a variable argument
10673 list, or passes any parameter in memory. */
10676 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
10678 tree fntype
, result
;
10679 CUMULATIVE_ARGS args_so_far_v
;
10680 cumulative_args_t args_so_far
;
10683 /* Must be a libcall, all of which only use reg parms. */
10688 fntype
= TREE_TYPE (fun
);
10690 /* Varargs functions need the parameter save area. */
10691 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
10694 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
10695 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10697 /* When incoming, we will have been passed the function decl.
10698 It is necessary to use the decl to handle K&R style functions,
10699 where TYPE_ARG_TYPES may not be available. */
10702 gcc_assert (DECL_P (fun
));
10703 result
= DECL_RESULT (fun
);
10706 result
= TREE_TYPE (fntype
);
10708 if (result
&& aggregate_value_p (result
, fntype
))
10710 if (!TYPE_P (result
))
10711 result
= TREE_TYPE (result
);
10712 result
= build_pointer_type (result
);
10713 rs6000_parm_needs_stack (args_so_far
, result
);
10720 for (parm
= DECL_ARGUMENTS (fun
);
10721 parm
&& parm
!= void_list_node
;
10722 parm
= TREE_CHAIN (parm
))
10723 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
10728 function_args_iterator args_iter
;
10731 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
10732 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10739 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10740 usually a constant depending on the ABI. However, in the ELFv2 ABI
10741 the register parameter area is optional when calling a function that
10742 has a prototype is scope, has no variable argument list, and passes
10743 all parameters in registers. */
10746 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
10748 int reg_parm_stack_space
;
10750 switch (DEFAULT_ABI
)
10753 reg_parm_stack_space
= 0;
10758 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10762 /* ??? Recomputing this every time is a bit expensive. Is there
10763 a place to cache this information? */
10764 if (rs6000_function_parms_need_stack (fun
, incoming
))
10765 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10767 reg_parm_stack_space
= 0;
10771 return reg_parm_stack_space
;
10775 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10778 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10783 for (i
= 0; i
< nregs
; i
++)
10785 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10786 if (reload_completed
)
10788 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10791 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10792 i
* GET_MODE_SIZE (reg_mode
));
10795 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10799 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10803 /* Perform any needed actions needed for a function that is receiving a
10804 variable number of arguments.
10808 MODE and TYPE are the mode and type of the current parameter.
10810 PRETEND_SIZE is a variable that should be set to the amount of stack
10811 that must be pushed by the prolog to pretend that our caller pushed
10814 Normally, this macro will push all remaining incoming registers on the
10815 stack and set PRETEND_SIZE to the length of the registers pushed. */
10818 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10819 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10822 CUMULATIVE_ARGS next_cum
;
10823 int reg_size
= TARGET_32BIT
? 4 : 8;
10824 rtx save_area
= NULL_RTX
, mem
;
10825 int first_reg_offset
;
10826 alias_set_type set
;
10828 /* Skip the last named argument. */
10829 next_cum
= *get_cumulative_args (cum
);
10830 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10832 if (DEFAULT_ABI
== ABI_V4
)
10834 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10838 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10839 HOST_WIDE_INT offset
= 0;
10841 /* Try to optimize the size of the varargs save area.
10842 The ABI requires that ap.reg_save_area is doubleword
10843 aligned, but we don't need to allocate space for all
10844 the bytes, only those to which we actually will save
10846 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10847 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10848 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10849 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10850 && cfun
->va_list_fpr_size
)
10853 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10854 * UNITS_PER_FP_WORD
;
10855 if (cfun
->va_list_fpr_size
10856 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10857 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10859 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10860 * UNITS_PER_FP_WORD
;
10864 offset
= -((first_reg_offset
* reg_size
) & ~7);
10865 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10867 gpr_reg_num
= cfun
->va_list_gpr_size
;
10868 if (reg_size
== 4 && (first_reg_offset
& 1))
10871 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10874 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10875 * UNITS_PER_FP_WORD
10876 - (int) (GP_ARG_NUM_REG
* reg_size
);
10878 if (gpr_size
+ fpr_size
)
10881 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10882 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10883 reg_save_area
= XEXP (reg_save_area
, 0);
10884 if (GET_CODE (reg_save_area
) == PLUS
)
10886 gcc_assert (XEXP (reg_save_area
, 0)
10887 == virtual_stack_vars_rtx
);
10888 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10889 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10892 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10895 cfun
->machine
->varargs_save_offset
= offset
;
10896 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10901 first_reg_offset
= next_cum
.words
;
10902 save_area
= virtual_incoming_args_rtx
;
10904 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10905 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10908 set
= get_varargs_alias_set ();
10909 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10910 && cfun
->va_list_gpr_size
)
10912 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10914 if (va_list_gpr_counter_field
)
10915 /* V4 va_list_gpr_size counts number of registers needed. */
10916 n_gpr
= cfun
->va_list_gpr_size
;
10918 /* char * va_list instead counts number of bytes needed. */
10919 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10924 mem
= gen_rtx_MEM (BLKmode
,
10925 plus_constant (Pmode
, save_area
,
10926 first_reg_offset
* reg_size
));
10927 MEM_NOTRAP_P (mem
) = 1;
10928 set_mem_alias_set (mem
, set
);
10929 set_mem_align (mem
, BITS_PER_WORD
);
10931 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10935 /* Save FP registers if needed. */
10936 if (DEFAULT_ABI
== ABI_V4
10937 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10939 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10940 && cfun
->va_list_fpr_size
)
10942 int fregno
= next_cum
.fregno
, nregs
;
10943 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10944 rtx lab
= gen_label_rtx ();
10945 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10946 * UNITS_PER_FP_WORD
);
10949 (gen_rtx_SET (VOIDmode
,
10951 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10952 gen_rtx_NE (VOIDmode
, cr1
,
10954 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10958 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10959 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10961 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10963 plus_constant (Pmode
, save_area
, off
));
10964 MEM_NOTRAP_P (mem
) = 1;
10965 set_mem_alias_set (mem
, set
);
10966 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10967 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10968 ? DFmode
: SFmode
));
10969 emit_move_insn (mem
, gen_rtx_REG (
10970 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10971 ? DFmode
: SFmode
, fregno
));
10978 /* Create the va_list data type. */
10981 rs6000_build_builtin_va_list (void)
10983 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10985 /* For AIX, prefer 'char *' because that's what the system
10986 header files like. */
10987 if (DEFAULT_ABI
!= ABI_V4
)
10988 return build_pointer_type (char_type_node
);
10990 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10991 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10992 get_identifier ("__va_list_tag"), record
);
10994 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10995 unsigned_char_type_node
);
10996 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10997 unsigned_char_type_node
);
10998 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10999 every user file. */
11000 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11001 get_identifier ("reserved"), short_unsigned_type_node
);
11002 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11003 get_identifier ("overflow_arg_area"),
11005 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11006 get_identifier ("reg_save_area"),
11009 va_list_gpr_counter_field
= f_gpr
;
11010 va_list_fpr_counter_field
= f_fpr
;
11012 DECL_FIELD_CONTEXT (f_gpr
) = record
;
11013 DECL_FIELD_CONTEXT (f_fpr
) = record
;
11014 DECL_FIELD_CONTEXT (f_res
) = record
;
11015 DECL_FIELD_CONTEXT (f_ovf
) = record
;
11016 DECL_FIELD_CONTEXT (f_sav
) = record
;
11018 TYPE_STUB_DECL (record
) = type_decl
;
11019 TYPE_NAME (record
) = type_decl
;
11020 TYPE_FIELDS (record
) = f_gpr
;
11021 DECL_CHAIN (f_gpr
) = f_fpr
;
11022 DECL_CHAIN (f_fpr
) = f_res
;
11023 DECL_CHAIN (f_res
) = f_ovf
;
11024 DECL_CHAIN (f_ovf
) = f_sav
;
11026 layout_type (record
);
11028 /* The correct type is an array type of one element. */
11029 return build_array_type (record
, build_index_type (size_zero_node
));
11032 /* Implement va_start. */
11035 rs6000_va_start (tree valist
, rtx nextarg
)
11037 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
11038 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11039 tree gpr
, fpr
, ovf
, sav
, t
;
11041 /* Only SVR4 needs something special. */
11042 if (DEFAULT_ABI
!= ABI_V4
)
11044 std_expand_builtin_va_start (valist
, nextarg
);
11048 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11049 f_fpr
= DECL_CHAIN (f_gpr
);
11050 f_res
= DECL_CHAIN (f_fpr
);
11051 f_ovf
= DECL_CHAIN (f_res
);
11052 f_sav
= DECL_CHAIN (f_ovf
);
11054 valist
= build_simple_mem_ref (valist
);
11055 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11056 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11058 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11060 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11063 /* Count number of gp and fp argument registers used. */
11064 words
= crtl
->args
.info
.words
;
11065 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
11067 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
11070 if (TARGET_DEBUG_ARG
)
11071 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
11072 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
11073 words
, n_gpr
, n_fpr
);
11075 if (cfun
->va_list_gpr_size
)
11077 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
11078 build_int_cst (NULL_TREE
, n_gpr
));
11079 TREE_SIDE_EFFECTS (t
) = 1;
11080 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11083 if (cfun
->va_list_fpr_size
)
11085 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
11086 build_int_cst (NULL_TREE
, n_fpr
));
11087 TREE_SIDE_EFFECTS (t
) = 1;
11088 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11090 #ifdef HAVE_AS_GNU_ATTRIBUTE
11091 if (call_ABI_of_interest (cfun
->decl
))
11092 rs6000_passes_float
= true;
11096 /* Find the overflow area. */
11097 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
11099 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
11100 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
11101 TREE_SIDE_EFFECTS (t
) = 1;
11102 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11104 /* If there were no va_arg invocations, don't set up the register
11106 if (!cfun
->va_list_gpr_size
11107 && !cfun
->va_list_fpr_size
11108 && n_gpr
< GP_ARG_NUM_REG
11109 && n_fpr
< FP_ARG_V4_MAX_REG
)
11112 /* Find the register save area. */
11113 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
11114 if (cfun
->machine
->varargs_save_offset
)
11115 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
11116 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
11117 TREE_SIDE_EFFECTS (t
) = 1;
11118 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11121 /* Implement va_arg. */
11124 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
11125 gimple_seq
*post_p
)
11127 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11128 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
11129 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
11130 tree lab_false
, lab_over
, addr
;
11132 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
11136 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
11138 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
11139 return build_va_arg_indirect_ref (t
);
11142 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
11143 earlier version of gcc, with the property that it always applied alignment
11144 adjustments to the va-args (even for zero-sized types). The cheapest way
11145 to deal with this is to replicate the effect of the part of
11146 std_gimplify_va_arg_expr that carries out the align adjust, for the case
11148 We don't need to check for pass-by-reference because of the test above.
11149 We can return a simplifed answer, since we know there's no offset to add. */
11152 && rs6000_darwin64_abi
)
11153 || DEFAULT_ABI
== ABI_ELFv2
11154 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
11155 && integer_zerop (TYPE_SIZE (type
)))
11157 unsigned HOST_WIDE_INT align
, boundary
;
11158 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
11159 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
11160 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
11161 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
11162 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
11163 boundary
/= BITS_PER_UNIT
;
11164 if (boundary
> align
)
11167 /* This updates arg ptr by the amount that would be necessary
11168 to align the zero-sized (but not zero-alignment) item. */
11169 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11170 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
11171 gimplify_and_add (t
, pre_p
);
11173 t
= fold_convert (sizetype
, valist_tmp
);
11174 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11175 fold_convert (TREE_TYPE (valist
),
11176 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
11177 size_int (-boundary
))));
11178 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
11179 gimplify_and_add (t
, pre_p
);
11181 /* Since it is zero-sized there's no increment for the item itself. */
11182 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
11183 return build_va_arg_indirect_ref (valist_tmp
);
11186 if (DEFAULT_ABI
!= ABI_V4
)
11188 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
11190 tree elem_type
= TREE_TYPE (type
);
11191 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
11192 int elem_size
= GET_MODE_SIZE (elem_mode
);
11194 if (elem_size
< UNITS_PER_WORD
)
11196 tree real_part
, imag_part
;
11197 gimple_seq post
= NULL
;
11199 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11201 /* Copy the value into a temporary, lest the formal temporary
11202 be reused out from under us. */
11203 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
11204 gimple_seq_add_seq (pre_p
, post
);
11206 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11209 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
11213 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
11216 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11217 f_fpr
= DECL_CHAIN (f_gpr
);
11218 f_res
= DECL_CHAIN (f_fpr
);
11219 f_ovf
= DECL_CHAIN (f_res
);
11220 f_sav
= DECL_CHAIN (f_ovf
);
11222 valist
= build_va_arg_indirect_ref (valist
);
11223 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11224 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11226 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11228 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11231 size
= int_size_in_bytes (type
);
11232 rsize
= (size
+ 3) / 4;
11235 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11236 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
11237 || (TARGET_DOUBLE_FLOAT
11238 && (TYPE_MODE (type
) == DFmode
11239 || TYPE_MODE (type
) == TFmode
11240 || TYPE_MODE (type
) == SDmode
11241 || TYPE_MODE (type
) == DDmode
11242 || TYPE_MODE (type
) == TDmode
))))
11244 /* FP args go in FP registers, if present. */
11246 n_reg
= (size
+ 7) / 8;
11247 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
11248 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
11249 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
11254 /* Otherwise into GP registers. */
11263 /* Pull the value out of the saved registers.... */
11266 addr
= create_tmp_var (ptr_type_node
, "addr");
11268 /* AltiVec vectors never go in registers when -mabi=altivec. */
11269 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11273 lab_false
= create_artificial_label (input_location
);
11274 lab_over
= create_artificial_label (input_location
);
11276 /* Long long and SPE vectors are aligned in the registers.
11277 As are any other 2 gpr item such as complex int due to a
11278 historical mistake. */
11280 if (n_reg
== 2 && reg
== gpr
)
11283 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11284 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
11285 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
11286 unshare_expr (reg
), u
);
11288 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11289 reg number is 0 for f1, so we want to make it odd. */
11290 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
11292 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11293 build_int_cst (TREE_TYPE (reg
), 1));
11294 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
11297 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
11298 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
11299 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11300 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11301 gimplify_and_add (t
, pre_p
);
11305 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11307 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11308 build_int_cst (TREE_TYPE (reg
), n_reg
));
11309 u
= fold_convert (sizetype
, u
);
11310 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
11311 t
= fold_build_pointer_plus (t
, u
);
11313 /* _Decimal32 varargs are located in the second word of the 64-bit
11314 FP register for 32-bit binaries. */
11315 if (!TARGET_POWERPC64
11316 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11317 && TYPE_MODE (type
) == SDmode
)
11318 t
= fold_build_pointer_plus_hwi (t
, size
);
11320 gimplify_assign (addr
, t
, pre_p
);
11322 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11324 stmt
= gimple_build_label (lab_false
);
11325 gimple_seq_add_stmt (pre_p
, stmt
);
11327 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
11329 /* Ensure that we don't find any more args in regs.
11330 Alignment has taken care of for special cases. */
11331 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
11335 /* ... otherwise out of the overflow area. */
11337 /* Care for on-stack alignment if needed. */
11341 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
11342 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
11343 build_int_cst (TREE_TYPE (t
), -align
));
11345 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11347 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
11349 t
= fold_build_pointer_plus_hwi (t
, size
);
11350 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11354 stmt
= gimple_build_label (lab_over
);
11355 gimple_seq_add_stmt (pre_p
, stmt
);
11358 if (STRICT_ALIGNMENT
11359 && (TYPE_ALIGN (type
)
11360 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11362 /* The value (of type complex double, for example) may not be
11363 aligned in memory in the saved registers, so copy via a
11364 temporary. (This is the same code as used for SPARC.) */
11365 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11366 tree dest_addr
= build_fold_addr_expr (tmp
);
11368 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11369 3, dest_addr
, addr
, size_int (rsize
* 4));
11371 gimplify_and_add (copy
, pre_p
);
11375 addr
= fold_convert (ptrtype
, addr
);
11376 return build_va_arg_indirect_ref (addr
);
11382 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11385 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11386 const char *attr_string
= "";
11388 gcc_assert (name
!= NULL
);
11389 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11391 if (rs6000_builtin_decls
[(int)code
])
11392 fatal_error ("internal error: builtin function %s already processed", name
);
11394 rs6000_builtin_decls
[(int)code
] = t
=
11395 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11397 /* Set any special attributes. */
11398 if ((classify
& RS6000_BTC_CONST
) != 0)
11400 /* const function, function only depends on the inputs. */
11401 TREE_READONLY (t
) = 1;
11402 TREE_NOTHROW (t
) = 1;
11403 attr_string
= ", pure";
11405 else if ((classify
& RS6000_BTC_PURE
) != 0)
11407 /* pure function, function can read global memory, but does not set any
11409 DECL_PURE_P (t
) = 1;
11410 TREE_NOTHROW (t
) = 1;
11411 attr_string
= ", const";
11413 else if ((classify
& RS6000_BTC_FP
) != 0)
11415 /* Function is a math function. If rounding mode is on, then treat the
11416 function as not reading global memory, but it can have arbitrary side
11417 effects. If it is off, then assume the function is a const function.
11418 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11419 builtin-attribute.def that is used for the math functions. */
11420 TREE_NOTHROW (t
) = 1;
11421 if (flag_rounding_math
)
11423 DECL_PURE_P (t
) = 1;
11424 DECL_IS_NOVOPS (t
) = 1;
11425 attr_string
= ", fp, pure";
11429 TREE_READONLY (t
) = 1;
11430 attr_string
= ", fp, const";
11433 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11434 gcc_unreachable ();
11436 if (TARGET_DEBUG_BUILTIN
)
11437 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11438 (int)code
, name
, attr_string
);
11441 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11443 #undef RS6000_BUILTIN_1
11444 #undef RS6000_BUILTIN_2
11445 #undef RS6000_BUILTIN_3
11446 #undef RS6000_BUILTIN_A
11447 #undef RS6000_BUILTIN_D
11448 #undef RS6000_BUILTIN_E
11449 #undef RS6000_BUILTIN_H
11450 #undef RS6000_BUILTIN_P
11451 #undef RS6000_BUILTIN_Q
11452 #undef RS6000_BUILTIN_S
11453 #undef RS6000_BUILTIN_X
11455 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11456 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11457 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11458 { MASK, ICODE, NAME, ENUM },
11460 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11461 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11462 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11463 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11464 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11465 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11466 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11467 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11469 static const struct builtin_description bdesc_3arg
[] =
11471 #include "rs6000-builtin.def"
11474 /* DST operations: void foo (void *, const int, const char). */
11476 #undef RS6000_BUILTIN_1
11477 #undef RS6000_BUILTIN_2
11478 #undef RS6000_BUILTIN_3
11479 #undef RS6000_BUILTIN_A
11480 #undef RS6000_BUILTIN_D
11481 #undef RS6000_BUILTIN_E
11482 #undef RS6000_BUILTIN_H
11483 #undef RS6000_BUILTIN_P
11484 #undef RS6000_BUILTIN_Q
11485 #undef RS6000_BUILTIN_S
11486 #undef RS6000_BUILTIN_X
11488 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11489 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11490 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11491 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11492 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11493 { MASK, ICODE, NAME, ENUM },
11495 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11496 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11497 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11498 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11499 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11500 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11502 static const struct builtin_description bdesc_dst
[] =
11504 #include "rs6000-builtin.def"
11507 /* Simple binary operations: VECc = foo (VECa, VECb). */
11509 #undef RS6000_BUILTIN_1
11510 #undef RS6000_BUILTIN_2
11511 #undef RS6000_BUILTIN_3
11512 #undef RS6000_BUILTIN_A
11513 #undef RS6000_BUILTIN_D
11514 #undef RS6000_BUILTIN_E
11515 #undef RS6000_BUILTIN_H
11516 #undef RS6000_BUILTIN_P
11517 #undef RS6000_BUILTIN_Q
11518 #undef RS6000_BUILTIN_S
11519 #undef RS6000_BUILTIN_X
11521 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11522 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11523 { MASK, ICODE, NAME, ENUM },
11525 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11526 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11527 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11528 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11529 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11530 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11531 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11532 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11533 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11535 static const struct builtin_description bdesc_2arg
[] =
11537 #include "rs6000-builtin.def"
11540 #undef RS6000_BUILTIN_1
11541 #undef RS6000_BUILTIN_2
11542 #undef RS6000_BUILTIN_3
11543 #undef RS6000_BUILTIN_A
11544 #undef RS6000_BUILTIN_D
11545 #undef RS6000_BUILTIN_E
11546 #undef RS6000_BUILTIN_H
11547 #undef RS6000_BUILTIN_P
11548 #undef RS6000_BUILTIN_Q
11549 #undef RS6000_BUILTIN_S
11550 #undef RS6000_BUILTIN_X
11552 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11553 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11554 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11555 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11556 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11557 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11558 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11559 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11560 { MASK, ICODE, NAME, ENUM },
11562 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11563 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11564 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11566 /* AltiVec predicates. */
11568 static const struct builtin_description bdesc_altivec_preds
[] =
11570 #include "rs6000-builtin.def"
11573 /* SPE predicates. */
11574 #undef RS6000_BUILTIN_1
11575 #undef RS6000_BUILTIN_2
11576 #undef RS6000_BUILTIN_3
11577 #undef RS6000_BUILTIN_A
11578 #undef RS6000_BUILTIN_D
11579 #undef RS6000_BUILTIN_E
11580 #undef RS6000_BUILTIN_H
11581 #undef RS6000_BUILTIN_P
11582 #undef RS6000_BUILTIN_Q
11583 #undef RS6000_BUILTIN_S
11584 #undef RS6000_BUILTIN_X
11586 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11587 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11588 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11589 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11590 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11591 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11592 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11593 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11594 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11595 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11596 { MASK, ICODE, NAME, ENUM },
11598 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11600 static const struct builtin_description bdesc_spe_predicates
[] =
11602 #include "rs6000-builtin.def"
11605 /* SPE evsel predicates. */
11606 #undef RS6000_BUILTIN_1
11607 #undef RS6000_BUILTIN_2
11608 #undef RS6000_BUILTIN_3
11609 #undef RS6000_BUILTIN_A
11610 #undef RS6000_BUILTIN_D
11611 #undef RS6000_BUILTIN_E
11612 #undef RS6000_BUILTIN_H
11613 #undef RS6000_BUILTIN_P
11614 #undef RS6000_BUILTIN_Q
11615 #undef RS6000_BUILTIN_S
11616 #undef RS6000_BUILTIN_X
11618 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11619 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11620 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11621 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11622 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11623 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11624 { MASK, ICODE, NAME, ENUM },
11626 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11627 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11628 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11629 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11630 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11632 static const struct builtin_description bdesc_spe_evsel
[] =
11634 #include "rs6000-builtin.def"
11637 /* PAIRED predicates. */
11638 #undef RS6000_BUILTIN_1
11639 #undef RS6000_BUILTIN_2
11640 #undef RS6000_BUILTIN_3
11641 #undef RS6000_BUILTIN_A
11642 #undef RS6000_BUILTIN_D
11643 #undef RS6000_BUILTIN_E
11644 #undef RS6000_BUILTIN_H
11645 #undef RS6000_BUILTIN_P
11646 #undef RS6000_BUILTIN_Q
11647 #undef RS6000_BUILTIN_S
11648 #undef RS6000_BUILTIN_X
11650 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11651 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11652 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11653 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11654 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11655 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11656 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11657 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11658 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11659 { MASK, ICODE, NAME, ENUM },
11661 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11662 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11664 static const struct builtin_description bdesc_paired_preds
[] =
11666 #include "rs6000-builtin.def"
11669 /* ABS* operations. */
11671 #undef RS6000_BUILTIN_1
11672 #undef RS6000_BUILTIN_2
11673 #undef RS6000_BUILTIN_3
11674 #undef RS6000_BUILTIN_A
11675 #undef RS6000_BUILTIN_D
11676 #undef RS6000_BUILTIN_E
11677 #undef RS6000_BUILTIN_H
11678 #undef RS6000_BUILTIN_P
11679 #undef RS6000_BUILTIN_Q
11680 #undef RS6000_BUILTIN_S
11681 #undef RS6000_BUILTIN_X
11683 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11684 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11685 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11686 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11687 { MASK, ICODE, NAME, ENUM },
11689 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11690 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11691 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11692 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11693 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11694 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11695 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11697 static const struct builtin_description bdesc_abs
[] =
11699 #include "rs6000-builtin.def"
11702 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11705 #undef RS6000_BUILTIN_1
11706 #undef RS6000_BUILTIN_2
11707 #undef RS6000_BUILTIN_3
11708 #undef RS6000_BUILTIN_A
11709 #undef RS6000_BUILTIN_D
11710 #undef RS6000_BUILTIN_E
11711 #undef RS6000_BUILTIN_H
11712 #undef RS6000_BUILTIN_P
11713 #undef RS6000_BUILTIN_Q
11714 #undef RS6000_BUILTIN_S
11715 #undef RS6000_BUILTIN_X
11717 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11718 { MASK, ICODE, NAME, ENUM },
11720 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11721 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11722 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11723 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11724 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11725 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11726 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11727 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11728 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11729 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11731 static const struct builtin_description bdesc_1arg
[] =
11733 #include "rs6000-builtin.def"
11736 /* HTM builtins. */
11737 #undef RS6000_BUILTIN_1
11738 #undef RS6000_BUILTIN_2
11739 #undef RS6000_BUILTIN_3
11740 #undef RS6000_BUILTIN_A
11741 #undef RS6000_BUILTIN_D
11742 #undef RS6000_BUILTIN_E
11743 #undef RS6000_BUILTIN_H
11744 #undef RS6000_BUILTIN_P
11745 #undef RS6000_BUILTIN_Q
11746 #undef RS6000_BUILTIN_S
11747 #undef RS6000_BUILTIN_X
11749 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11750 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11751 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11752 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11753 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11754 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11755 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11756 { MASK, ICODE, NAME, ENUM },
11758 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11759 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11760 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11761 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11763 static const struct builtin_description bdesc_htm
[] =
11765 #include "rs6000-builtin.def"
11768 #undef RS6000_BUILTIN_1
11769 #undef RS6000_BUILTIN_2
11770 #undef RS6000_BUILTIN_3
11771 #undef RS6000_BUILTIN_A
11772 #undef RS6000_BUILTIN_D
11773 #undef RS6000_BUILTIN_E
11774 #undef RS6000_BUILTIN_H
11775 #undef RS6000_BUILTIN_P
11776 #undef RS6000_BUILTIN_Q
11777 #undef RS6000_BUILTIN_S
11779 /* Return true if a builtin function is overloaded. */
11781 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11783 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11786 /* Expand an expression EXP that calls a builtin without arguments. */
11788 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11791 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11793 if (icode
== CODE_FOR_nothing
)
11794 /* Builtin not supported on this processor. */
11798 || GET_MODE (target
) != tmode
11799 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11800 target
= gen_reg_rtx (tmode
);
11802 pat
= GEN_FCN (icode
) (target
);
11812 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
11815 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11816 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11817 rtx op0
= expand_normal (arg0
);
11818 rtx op1
= expand_normal (arg1
);
11819 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11820 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11822 if (icode
== CODE_FOR_nothing
)
11823 /* Builtin not supported on this processor. */
11826 /* If we got invalid arguments bail out before generating bad rtl. */
11827 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11830 if (GET_CODE (op0
) != CONST_INT
11831 || INTVAL (op0
) > 255
11832 || INTVAL (op0
) < 0)
11834 error ("argument 1 must be an 8-bit field value");
11838 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11839 op0
= copy_to_mode_reg (mode0
, op0
);
11841 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11842 op1
= copy_to_mode_reg (mode1
, op1
);
11844 pat
= GEN_FCN (icode
) (op0
, op1
);
11854 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11857 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11858 rtx op0
= expand_normal (arg0
);
11859 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11860 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11862 if (icode
== CODE_FOR_nothing
)
11863 /* Builtin not supported on this processor. */
11866 /* If we got invalid arguments bail out before generating bad rtl. */
11867 if (arg0
== error_mark_node
)
11870 if (icode
== CODE_FOR_altivec_vspltisb
11871 || icode
== CODE_FOR_altivec_vspltish
11872 || icode
== CODE_FOR_altivec_vspltisw
11873 || icode
== CODE_FOR_spe_evsplatfi
11874 || icode
== CODE_FOR_spe_evsplati
)
11876 /* Only allow 5-bit *signed* literals. */
11877 if (GET_CODE (op0
) != CONST_INT
11878 || INTVAL (op0
) > 15
11879 || INTVAL (op0
) < -16)
11881 error ("argument 1 must be a 5-bit signed literal");
11887 || GET_MODE (target
) != tmode
11888 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11889 target
= gen_reg_rtx (tmode
);
11891 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11892 op0
= copy_to_mode_reg (mode0
, op0
);
11894 pat
= GEN_FCN (icode
) (target
, op0
);
11903 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11905 rtx pat
, scratch1
, scratch2
;
11906 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11907 rtx op0
= expand_normal (arg0
);
11908 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11909 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11911 /* If we have invalid arguments, bail out before generating bad rtl. */
11912 if (arg0
== error_mark_node
)
11916 || GET_MODE (target
) != tmode
11917 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11918 target
= gen_reg_rtx (tmode
);
11920 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11921 op0
= copy_to_mode_reg (mode0
, op0
);
11923 scratch1
= gen_reg_rtx (mode0
);
11924 scratch2
= gen_reg_rtx (mode0
);
11926 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11935 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11938 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11939 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11940 rtx op0
= expand_normal (arg0
);
11941 rtx op1
= expand_normal (arg1
);
11942 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11943 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11944 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11946 if (icode
== CODE_FOR_nothing
)
11947 /* Builtin not supported on this processor. */
11950 /* If we got invalid arguments bail out before generating bad rtl. */
11951 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11954 if (icode
== CODE_FOR_altivec_vcfux
11955 || icode
== CODE_FOR_altivec_vcfsx
11956 || icode
== CODE_FOR_altivec_vctsxs
11957 || icode
== CODE_FOR_altivec_vctuxs
11958 || icode
== CODE_FOR_altivec_vspltb
11959 || icode
== CODE_FOR_altivec_vsplth
11960 || icode
== CODE_FOR_altivec_vspltw
11961 || icode
== CODE_FOR_spe_evaddiw
11962 || icode
== CODE_FOR_spe_evldd
11963 || icode
== CODE_FOR_spe_evldh
11964 || icode
== CODE_FOR_spe_evldw
11965 || icode
== CODE_FOR_spe_evlhhesplat
11966 || icode
== CODE_FOR_spe_evlhhossplat
11967 || icode
== CODE_FOR_spe_evlhhousplat
11968 || icode
== CODE_FOR_spe_evlwhe
11969 || icode
== CODE_FOR_spe_evlwhos
11970 || icode
== CODE_FOR_spe_evlwhou
11971 || icode
== CODE_FOR_spe_evlwhsplat
11972 || icode
== CODE_FOR_spe_evlwwsplat
11973 || icode
== CODE_FOR_spe_evrlwi
11974 || icode
== CODE_FOR_spe_evslwi
11975 || icode
== CODE_FOR_spe_evsrwis
11976 || icode
== CODE_FOR_spe_evsubifw
11977 || icode
== CODE_FOR_spe_evsrwiu
)
11979 /* Only allow 5-bit unsigned literals. */
11981 if (TREE_CODE (arg1
) != INTEGER_CST
11982 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11984 error ("argument 2 must be a 5-bit unsigned literal");
11990 || GET_MODE (target
) != tmode
11991 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11992 target
= gen_reg_rtx (tmode
);
11994 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11995 op0
= copy_to_mode_reg (mode0
, op0
);
11996 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11997 op1
= copy_to_mode_reg (mode1
, op1
);
11999 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12008 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12011 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
12012 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12013 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12014 rtx op0
= expand_normal (arg0
);
12015 rtx op1
= expand_normal (arg1
);
12016 enum machine_mode tmode
= SImode
;
12017 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12018 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12021 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
12023 error ("argument 1 of __builtin_altivec_predicate must be a constant");
12027 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
12029 gcc_assert (mode0
== mode1
);
12031 /* If we have invalid arguments, bail out before generating bad rtl. */
12032 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12036 || GET_MODE (target
) != tmode
12037 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12038 target
= gen_reg_rtx (tmode
);
12040 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12041 op0
= copy_to_mode_reg (mode0
, op0
);
12042 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12043 op1
= copy_to_mode_reg (mode1
, op1
);
12045 scratch
= gen_reg_rtx (mode0
);
12047 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12052 /* The vec_any* and vec_all* predicates use the same opcodes for two
12053 different operations, but the bits in CR6 will be different
12054 depending on what information we want. So we have to play tricks
12055 with CR6 to get the right bits out.
12057 If you think this is disgusting, look at the specs for the
12058 AltiVec predicates. */
12060 switch (cr6_form_int
)
12063 emit_insn (gen_cr6_test_for_zero (target
));
12066 emit_insn (gen_cr6_test_for_zero_reverse (target
));
12069 emit_insn (gen_cr6_test_for_lt (target
));
12072 emit_insn (gen_cr6_test_for_lt_reverse (target
));
12075 error ("argument 1 of __builtin_altivec_predicate is out of range");
12083 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
12086 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12087 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12088 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12089 enum machine_mode mode0
= Pmode
;
12090 enum machine_mode mode1
= Pmode
;
12091 rtx op0
= expand_normal (arg0
);
12092 rtx op1
= expand_normal (arg1
);
12094 if (icode
== CODE_FOR_nothing
)
12095 /* Builtin not supported on this processor. */
12098 /* If we got invalid arguments bail out before generating bad rtl. */
12099 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12103 || GET_MODE (target
) != tmode
12104 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12105 target
= gen_reg_rtx (tmode
);
12107 op1
= copy_to_mode_reg (mode1
, op1
);
12109 if (op0
== const0_rtx
)
12111 addr
= gen_rtx_MEM (tmode
, op1
);
12115 op0
= copy_to_mode_reg (mode0
, op0
);
12116 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12119 pat
= GEN_FCN (icode
) (target
, addr
);
12128 /* Return a constant vector for use as a little-endian permute control vector
12129 to reverse the order of elements of the given vector mode. */
12131 swap_selector_for_mode (enum machine_mode mode
)
12133 /* These are little endian vectors, so their elements are reversed
12134 from what you would normally expect for a permute control vector. */
12135 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
12136 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
12137 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
12138 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
12139 unsigned int *swaparray
, i
;
12156 swaparray
= swap16
;
12159 gcc_unreachable ();
12162 for (i
= 0; i
< 16; ++i
)
12163 perm
[i
] = GEN_INT (swaparray
[i
]);
12165 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
12168 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
12169 with -maltivec=be specified. Issue the load followed by an element-reversing
12172 altivec_expand_lvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
12174 rtx tmp
= gen_reg_rtx (mode
);
12175 rtx load
= gen_rtx_SET (VOIDmode
, tmp
, op1
);
12176 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12177 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
12178 rtx sel
= swap_selector_for_mode (mode
);
12179 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
12181 gcc_assert (REG_P (op0
));
12183 emit_insn (gen_rtx_SET (VOIDmode
, op0
, vperm
));
12186 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
12187 with -maltivec=be specified. Issue the store preceded by an element-reversing
12190 altivec_expand_stvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
12192 rtx tmp
= gen_reg_rtx (mode
);
12193 rtx store
= gen_rtx_SET (VOIDmode
, op0
, tmp
);
12194 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12195 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
12196 rtx sel
= swap_selector_for_mode (mode
);
12199 gcc_assert (REG_P (op1
));
12200 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12201 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
12205 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
12206 specified. Issue the store preceded by an element-reversing permute. */
12208 altivec_expand_stvex_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
12210 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
12211 rtx tmp
= gen_reg_rtx (mode
);
12212 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
12213 rtx sel
= swap_selector_for_mode (mode
);
12216 gcc_assert (REG_P (op1
));
12217 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12218 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
12219 emit_insn (gen_rtx_SET (VOIDmode
, op0
, stvx
));
12223 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
12226 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12227 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12228 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12229 enum machine_mode mode0
= Pmode
;
12230 enum machine_mode mode1
= Pmode
;
12231 rtx op0
= expand_normal (arg0
);
12232 rtx op1
= expand_normal (arg1
);
12234 if (icode
== CODE_FOR_nothing
)
12235 /* Builtin not supported on this processor. */
12238 /* If we got invalid arguments bail out before generating bad rtl. */
12239 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12243 || GET_MODE (target
) != tmode
12244 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12245 target
= gen_reg_rtx (tmode
);
12247 op1
= copy_to_mode_reg (mode1
, op1
);
12249 if (op0
== const0_rtx
)
12251 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
12255 op0
= copy_to_mode_reg (mode0
, op0
);
12256 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12259 pat
= GEN_FCN (icode
) (target
, addr
);
12269 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
12271 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12272 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12273 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12274 rtx op0
= expand_normal (arg0
);
12275 rtx op1
= expand_normal (arg1
);
12276 rtx op2
= expand_normal (arg2
);
12278 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12279 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12280 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
12282 /* Invalid arguments. Bail before doing anything stoopid! */
12283 if (arg0
== error_mark_node
12284 || arg1
== error_mark_node
12285 || arg2
== error_mark_node
)
12288 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
12289 op0
= copy_to_mode_reg (mode2
, op0
);
12290 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
12291 op1
= copy_to_mode_reg (mode0
, op1
);
12292 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12293 op2
= copy_to_mode_reg (mode1
, op2
);
12295 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
12302 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
12304 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12305 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12306 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12307 rtx op0
= expand_normal (arg0
);
12308 rtx op1
= expand_normal (arg1
);
12309 rtx op2
= expand_normal (arg2
);
12311 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12312 enum machine_mode mode1
= Pmode
;
12313 enum machine_mode mode2
= Pmode
;
12315 /* Invalid arguments. Bail before doing anything stoopid! */
12316 if (arg0
== error_mark_node
12317 || arg1
== error_mark_node
12318 || arg2
== error_mark_node
)
12321 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
12322 op0
= copy_to_mode_reg (tmode
, op0
);
12324 op2
= copy_to_mode_reg (mode2
, op2
);
12326 if (op1
== const0_rtx
)
12328 addr
= gen_rtx_MEM (tmode
, op2
);
12332 op1
= copy_to_mode_reg (mode1
, op1
);
12333 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12336 pat
= GEN_FCN (icode
) (addr
, op0
);
12343 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
12345 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12346 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12347 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12348 rtx op0
= expand_normal (arg0
);
12349 rtx op1
= expand_normal (arg1
);
12350 rtx op2
= expand_normal (arg2
);
12352 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12353 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
12354 enum machine_mode mode1
= Pmode
;
12355 enum machine_mode mode2
= Pmode
;
12357 /* Invalid arguments. Bail before doing anything stoopid! */
12358 if (arg0
== error_mark_node
12359 || arg1
== error_mark_node
12360 || arg2
== error_mark_node
)
12363 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
12364 op0
= copy_to_mode_reg (smode
, op0
);
12366 op2
= copy_to_mode_reg (mode2
, op2
);
12368 if (op1
== const0_rtx
)
12370 addr
= gen_rtx_MEM (tmode
, op2
);
12374 op1
= copy_to_mode_reg (mode1
, op1
);
12375 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12378 pat
= GEN_FCN (icode
) (addr
, op0
);
12384 /* Return the appropriate SPR number associated with the given builtin. */
12385 static inline HOST_WIDE_INT
12386 htm_spr_num (enum rs6000_builtins code
)
12388 if (code
== HTM_BUILTIN_GET_TFHAR
12389 || code
== HTM_BUILTIN_SET_TFHAR
)
12391 else if (code
== HTM_BUILTIN_GET_TFIAR
12392 || code
== HTM_BUILTIN_SET_TFIAR
)
12394 else if (code
== HTM_BUILTIN_GET_TEXASR
12395 || code
== HTM_BUILTIN_SET_TEXASR
)
12397 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
12398 || code
== HTM_BUILTIN_SET_TEXASRU
);
12399 return TEXASRU_SPR
;
12402 /* Return the appropriate SPR regno associated with the given builtin. */
12403 static inline HOST_WIDE_INT
12404 htm_spr_regno (enum rs6000_builtins code
)
12406 if (code
== HTM_BUILTIN_GET_TFHAR
12407 || code
== HTM_BUILTIN_SET_TFHAR
)
12408 return TFHAR_REGNO
;
12409 else if (code
== HTM_BUILTIN_GET_TFIAR
12410 || code
== HTM_BUILTIN_SET_TFIAR
)
12411 return TFIAR_REGNO
;
12412 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
12413 || code
== HTM_BUILTIN_SET_TEXASR
12414 || code
== HTM_BUILTIN_GET_TEXASRU
12415 || code
== HTM_BUILTIN_SET_TEXASRU
);
12416 return TEXASR_REGNO
;
12419 /* Return the correct ICODE value depending on whether we are
12420 setting or reading the HTM SPRs. */
12421 static inline enum insn_code
12422 rs6000_htm_spr_icode (bool nonvoid
)
12425 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
12427 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
12430 /* Expand the HTM builtin in EXP and store the result in TARGET.
12431 Store true in *EXPANDEDP if we found a builtin to expand. */
12433 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12435 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12436 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
12437 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12438 const struct builtin_description
*d
;
12441 *expandedp
= false;
12443 /* Expand the HTM builtins. */
12445 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
12446 if (d
->code
== fcode
)
12448 rtx op
[MAX_HTM_OPERANDS
], pat
;
12451 call_expr_arg_iterator iter
;
12452 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
12453 enum insn_code icode
= d
->icode
;
12455 if (attr
& RS6000_BTC_SPR
)
12456 icode
= rs6000_htm_spr_icode (nonvoid
);
12460 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12462 || GET_MODE (target
) != tmode
12463 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12464 target
= gen_reg_rtx (tmode
);
12465 op
[nopnds
++] = target
;
12468 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
12470 const struct insn_operand_data
*insn_op
;
12472 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
12475 insn_op
= &insn_data
[icode
].operand
[nopnds
];
12477 op
[nopnds
] = expand_normal (arg
);
12479 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
12481 if (!strcmp (insn_op
->constraint
, "n"))
12483 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
12484 if (!CONST_INT_P (op
[nopnds
]))
12485 error ("argument %d must be an unsigned literal", arg_num
);
12487 error ("argument %d is an unsigned literal that is "
12488 "out of range", arg_num
);
12491 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12497 /* Handle the builtins for extended mnemonics. These accept
12498 no arguments, but map to builtins that take arguments. */
12501 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12502 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12503 op
[nopnds
++] = GEN_INT (1);
12504 #ifdef ENABLE_CHECKING
12505 attr
|= RS6000_BTC_UNARY
;
12508 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12509 op
[nopnds
++] = GEN_INT (0);
12510 #ifdef ENABLE_CHECKING
12511 attr
|= RS6000_BTC_UNARY
;
12518 /* If this builtin accesses SPRs, then pass in the appropriate
12519 SPR number and SPR regno as the last two operands. */
12520 if (attr
& RS6000_BTC_SPR
)
12522 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12523 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12526 #ifdef ENABLE_CHECKING
12527 int expected_nopnds
= 0;
12528 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12529 expected_nopnds
= 1;
12530 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12531 expected_nopnds
= 2;
12532 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12533 expected_nopnds
= 3;
12534 if (!(attr
& RS6000_BTC_VOID
))
12535 expected_nopnds
+= 1;
12536 if (attr
& RS6000_BTC_SPR
)
12537 expected_nopnds
+= 2;
12539 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12545 pat
= GEN_FCN (icode
) (op
[0]);
12548 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12551 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12554 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12557 gcc_unreachable ();
12573 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12576 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12577 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12578 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12579 rtx op0
= expand_normal (arg0
);
12580 rtx op1
= expand_normal (arg1
);
12581 rtx op2
= expand_normal (arg2
);
12582 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12583 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12584 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12585 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12587 if (icode
== CODE_FOR_nothing
)
12588 /* Builtin not supported on this processor. */
12591 /* If we got invalid arguments bail out before generating bad rtl. */
12592 if (arg0
== error_mark_node
12593 || arg1
== error_mark_node
12594 || arg2
== error_mark_node
)
12597 /* Check and prepare argument depending on the instruction code.
12599 Note that a switch statement instead of the sequence of tests
12600 would be incorrect as many of the CODE_FOR values could be
12601 CODE_FOR_nothing and that would yield multiple alternatives
12602 with identical values. We'd never reach here at runtime in
12604 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12605 || icode
== CODE_FOR_altivec_vsldoi_v4si
12606 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12607 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12609 /* Only allow 4-bit unsigned literals. */
12611 if (TREE_CODE (arg2
) != INTEGER_CST
12612 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12614 error ("argument 3 must be a 4-bit unsigned literal");
12618 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12619 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12620 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12621 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12622 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12623 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12624 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12625 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12627 /* Only allow 2-bit unsigned literals. */
12629 if (TREE_CODE (arg2
) != INTEGER_CST
12630 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12632 error ("argument 3 must be a 2-bit unsigned literal");
12636 else if (icode
== CODE_FOR_vsx_set_v2df
12637 || icode
== CODE_FOR_vsx_set_v2di
12638 || icode
== CODE_FOR_bcdadd
12639 || icode
== CODE_FOR_bcdadd_lt
12640 || icode
== CODE_FOR_bcdadd_eq
12641 || icode
== CODE_FOR_bcdadd_gt
12642 || icode
== CODE_FOR_bcdsub
12643 || icode
== CODE_FOR_bcdsub_lt
12644 || icode
== CODE_FOR_bcdsub_eq
12645 || icode
== CODE_FOR_bcdsub_gt
)
12647 /* Only allow 1-bit unsigned literals. */
12649 if (TREE_CODE (arg2
) != INTEGER_CST
12650 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12652 error ("argument 3 must be a 1-bit unsigned literal");
12656 else if (icode
== CODE_FOR_dfp_ddedpd_dd
12657 || icode
== CODE_FOR_dfp_ddedpd_td
)
12659 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
12661 if (TREE_CODE (arg0
) != INTEGER_CST
12662 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12664 error ("argument 1 must be 0 or 2");
12668 else if (icode
== CODE_FOR_dfp_denbcd_dd
12669 || icode
== CODE_FOR_dfp_denbcd_td
)
12671 /* Only allow 1-bit unsigned literals. */
12673 if (TREE_CODE (arg0
) != INTEGER_CST
12674 || TREE_INT_CST_LOW (arg0
) & ~0x1)
12676 error ("argument 1 must be a 1-bit unsigned literal");
12680 else if (icode
== CODE_FOR_dfp_dscli_dd
12681 || icode
== CODE_FOR_dfp_dscli_td
12682 || icode
== CODE_FOR_dfp_dscri_dd
12683 || icode
== CODE_FOR_dfp_dscri_td
)
12685 /* Only allow 6-bit unsigned literals. */
12687 if (TREE_CODE (arg1
) != INTEGER_CST
12688 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
12690 error ("argument 2 must be a 6-bit unsigned literal");
12694 else if (icode
== CODE_FOR_crypto_vshasigmaw
12695 || icode
== CODE_FOR_crypto_vshasigmad
)
12697 /* Check whether the 2nd and 3rd arguments are integer constants and in
12698 range and prepare arguments. */
12700 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
12702 error ("argument 2 must be 0 or 1");
12707 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
12709 error ("argument 3 must be in the range 0..15");
12715 || GET_MODE (target
) != tmode
12716 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12717 target
= gen_reg_rtx (tmode
);
12719 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12720 op0
= copy_to_mode_reg (mode0
, op0
);
12721 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12722 op1
= copy_to_mode_reg (mode1
, op1
);
12723 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12724 op2
= copy_to_mode_reg (mode2
, op2
);
12726 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12727 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12729 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12737 /* Expand the lvx builtins. */
12739 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12741 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12742 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12744 enum machine_mode tmode
, mode0
;
12746 enum insn_code icode
;
12750 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12751 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12753 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12754 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12756 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12757 icode
= CODE_FOR_vector_altivec_load_v4si
;
12759 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12760 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12762 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12763 icode
= CODE_FOR_vector_altivec_load_v2df
;
12765 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12766 icode
= CODE_FOR_vector_altivec_load_v2di
;
12767 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
12768 icode
= CODE_FOR_vector_altivec_load_v1ti
;
12771 *expandedp
= false;
12777 arg0
= CALL_EXPR_ARG (exp
, 0);
12778 op0
= expand_normal (arg0
);
12779 tmode
= insn_data
[icode
].operand
[0].mode
;
12780 mode0
= insn_data
[icode
].operand
[1].mode
;
12783 || GET_MODE (target
) != tmode
12784 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12785 target
= gen_reg_rtx (tmode
);
12787 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12788 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12790 pat
= GEN_FCN (icode
) (target
, op0
);
12797 /* Expand the stvx builtins. */
12799 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12802 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12803 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12805 enum machine_mode mode0
, mode1
;
12807 enum insn_code icode
;
12811 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12812 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12814 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12815 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12817 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12818 icode
= CODE_FOR_vector_altivec_store_v4si
;
12820 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12821 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12823 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12824 icode
= CODE_FOR_vector_altivec_store_v2df
;
12826 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12827 icode
= CODE_FOR_vector_altivec_store_v2di
;
12828 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
12829 icode
= CODE_FOR_vector_altivec_store_v1ti
;
12832 *expandedp
= false;
12836 arg0
= CALL_EXPR_ARG (exp
, 0);
12837 arg1
= CALL_EXPR_ARG (exp
, 1);
12838 op0
= expand_normal (arg0
);
12839 op1
= expand_normal (arg1
);
12840 mode0
= insn_data
[icode
].operand
[0].mode
;
12841 mode1
= insn_data
[icode
].operand
[1].mode
;
12843 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12844 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12845 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12846 op1
= copy_to_mode_reg (mode1
, op1
);
12848 pat
= GEN_FCN (icode
) (op0
, op1
);
12856 /* Expand the dst builtins. */
12858 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12861 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12862 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12863 tree arg0
, arg1
, arg2
;
12864 enum machine_mode mode0
, mode1
;
12865 rtx pat
, op0
, op1
, op2
;
12866 const struct builtin_description
*d
;
12869 *expandedp
= false;
12871 /* Handle DST variants. */
12873 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12874 if (d
->code
== fcode
)
12876 arg0
= CALL_EXPR_ARG (exp
, 0);
12877 arg1
= CALL_EXPR_ARG (exp
, 1);
12878 arg2
= CALL_EXPR_ARG (exp
, 2);
12879 op0
= expand_normal (arg0
);
12880 op1
= expand_normal (arg1
);
12881 op2
= expand_normal (arg2
);
12882 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12883 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12885 /* Invalid arguments, bail out before generating bad rtl. */
12886 if (arg0
== error_mark_node
12887 || arg1
== error_mark_node
12888 || arg2
== error_mark_node
)
12893 if (TREE_CODE (arg2
) != INTEGER_CST
12894 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12896 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12900 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12901 op0
= copy_to_mode_reg (Pmode
, op0
);
12902 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12903 op1
= copy_to_mode_reg (mode1
, op1
);
12905 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12915 /* Expand vec_init builtin. */
12917 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12919 enum machine_mode tmode
= TYPE_MODE (type
);
12920 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12921 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12923 gcc_assert (VECTOR_MODE_P (tmode
));
12924 gcc_assert (n_elt
== call_expr_nargs (exp
));
12926 if (!target
|| !register_operand (target
, tmode
))
12927 target
= gen_reg_rtx (tmode
);
12929 /* If we have a vector compromised of a single element, such as V1TImode, do
12930 the initialization directly. */
12931 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
12933 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
12934 emit_move_insn (target
, gen_lowpart (tmode
, x
));
12938 rtvec v
= rtvec_alloc (n_elt
);
12940 for (i
= 0; i
< n_elt
; ++i
)
12942 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12943 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12946 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12952 /* Return the integer constant in ARG. Constrain it to be in the range
12953 of the subparts of VEC_TYPE; issue an error if not. */
12956 get_element_number (tree vec_type
, tree arg
)
12958 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12960 if (!tree_fits_uhwi_p (arg
)
12961 || (elt
= tree_to_uhwi (arg
), elt
> max
))
12963 error ("selector must be an integer constant in the range 0..%wi", max
);
12970 /* Expand vec_set builtin. */
12972 altivec_expand_vec_set_builtin (tree exp
)
12974 enum machine_mode tmode
, mode1
;
12975 tree arg0
, arg1
, arg2
;
12979 arg0
= CALL_EXPR_ARG (exp
, 0);
12980 arg1
= CALL_EXPR_ARG (exp
, 1);
12981 arg2
= CALL_EXPR_ARG (exp
, 2);
12983 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12984 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12985 gcc_assert (VECTOR_MODE_P (tmode
));
12987 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12988 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12989 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12991 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12992 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12994 op0
= force_reg (tmode
, op0
);
12995 op1
= force_reg (mode1
, op1
);
12997 rs6000_expand_vector_set (op0
, op1
, elt
);
13002 /* Expand vec_ext builtin. */
13004 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
13006 enum machine_mode tmode
, mode0
;
13011 arg0
= CALL_EXPR_ARG (exp
, 0);
13012 arg1
= CALL_EXPR_ARG (exp
, 1);
13014 op0
= expand_normal (arg0
);
13015 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
13017 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13018 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
13019 gcc_assert (VECTOR_MODE_P (mode0
));
13021 op0
= force_reg (mode0
, op0
);
13023 if (optimize
|| !target
|| !register_operand (target
, tmode
))
13024 target
= gen_reg_rtx (tmode
);
13026 rs6000_expand_vector_extract (target
, op0
, elt
);
13031 /* Expand the builtin in EXP and store the result in TARGET. Store
13032 true in *EXPANDEDP if we found a builtin to expand. */
13034 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13036 const struct builtin_description
*d
;
13038 enum insn_code icode
;
13039 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13042 enum machine_mode tmode
, mode0
;
13043 enum rs6000_builtins fcode
13044 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13046 if (rs6000_overloaded_builtin_p (fcode
))
13049 error ("unresolved overload for Altivec builtin %qF", fndecl
);
13051 /* Given it is invalid, just generate a normal call. */
13052 return expand_call (exp
, target
, false);
13055 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
13059 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
13063 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
13071 case ALTIVEC_BUILTIN_STVX_V2DF
:
13072 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
13073 case ALTIVEC_BUILTIN_STVX_V2DI
:
13074 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
13075 case ALTIVEC_BUILTIN_STVX_V4SF
:
13076 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
13077 case ALTIVEC_BUILTIN_STVX
:
13078 case ALTIVEC_BUILTIN_STVX_V4SI
:
13079 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
13080 case ALTIVEC_BUILTIN_STVX_V8HI
:
13081 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
13082 case ALTIVEC_BUILTIN_STVX_V16QI
:
13083 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
13084 case ALTIVEC_BUILTIN_STVEBX
:
13085 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
13086 case ALTIVEC_BUILTIN_STVEHX
:
13087 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
13088 case ALTIVEC_BUILTIN_STVEWX
:
13089 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
13090 case ALTIVEC_BUILTIN_STVXL_V2DF
:
13091 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
13092 case ALTIVEC_BUILTIN_STVXL_V2DI
:
13093 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
13094 case ALTIVEC_BUILTIN_STVXL_V4SF
:
13095 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
13096 case ALTIVEC_BUILTIN_STVXL
:
13097 case ALTIVEC_BUILTIN_STVXL_V4SI
:
13098 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
13099 case ALTIVEC_BUILTIN_STVXL_V8HI
:
13100 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
13101 case ALTIVEC_BUILTIN_STVXL_V16QI
:
13102 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
13104 case ALTIVEC_BUILTIN_STVLX
:
13105 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
13106 case ALTIVEC_BUILTIN_STVLXL
:
13107 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
13108 case ALTIVEC_BUILTIN_STVRX
:
13109 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
13110 case ALTIVEC_BUILTIN_STVRXL
:
13111 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
13113 case VSX_BUILTIN_STXVD2X_V1TI
:
13114 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
13115 case VSX_BUILTIN_STXVD2X_V2DF
:
13116 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
13117 case VSX_BUILTIN_STXVD2X_V2DI
:
13118 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
13119 case VSX_BUILTIN_STXVW4X_V4SF
:
13120 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
13121 case VSX_BUILTIN_STXVW4X_V4SI
:
13122 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
13123 case VSX_BUILTIN_STXVW4X_V8HI
:
13124 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
13125 case VSX_BUILTIN_STXVW4X_V16QI
:
13126 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
13128 case ALTIVEC_BUILTIN_MFVSCR
:
13129 icode
= CODE_FOR_altivec_mfvscr
;
13130 tmode
= insn_data
[icode
].operand
[0].mode
;
13133 || GET_MODE (target
) != tmode
13134 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13135 target
= gen_reg_rtx (tmode
);
13137 pat
= GEN_FCN (icode
) (target
);
13143 case ALTIVEC_BUILTIN_MTVSCR
:
13144 icode
= CODE_FOR_altivec_mtvscr
;
13145 arg0
= CALL_EXPR_ARG (exp
, 0);
13146 op0
= expand_normal (arg0
);
13147 mode0
= insn_data
[icode
].operand
[0].mode
;
13149 /* If we got invalid arguments bail out before generating bad rtl. */
13150 if (arg0
== error_mark_node
)
13153 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13154 op0
= copy_to_mode_reg (mode0
, op0
);
13156 pat
= GEN_FCN (icode
) (op0
);
13161 case ALTIVEC_BUILTIN_DSSALL
:
13162 emit_insn (gen_altivec_dssall ());
13165 case ALTIVEC_BUILTIN_DSS
:
13166 icode
= CODE_FOR_altivec_dss
;
13167 arg0
= CALL_EXPR_ARG (exp
, 0);
13169 op0
= expand_normal (arg0
);
13170 mode0
= insn_data
[icode
].operand
[0].mode
;
13172 /* If we got invalid arguments bail out before generating bad rtl. */
13173 if (arg0
== error_mark_node
)
13176 if (TREE_CODE (arg0
) != INTEGER_CST
13177 || TREE_INT_CST_LOW (arg0
) & ~0x3)
13179 error ("argument to dss must be a 2-bit unsigned literal");
13183 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13184 op0
= copy_to_mode_reg (mode0
, op0
);
13186 emit_insn (gen_altivec_dss (op0
));
13189 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
13190 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
13191 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
13192 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
13193 case VSX_BUILTIN_VEC_INIT_V2DF
:
13194 case VSX_BUILTIN_VEC_INIT_V2DI
:
13195 case VSX_BUILTIN_VEC_INIT_V1TI
:
13196 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
13198 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
13199 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
13200 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
13201 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
13202 case VSX_BUILTIN_VEC_SET_V2DF
:
13203 case VSX_BUILTIN_VEC_SET_V2DI
:
13204 case VSX_BUILTIN_VEC_SET_V1TI
:
13205 return altivec_expand_vec_set_builtin (exp
);
13207 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
13208 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
13209 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
13210 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
13211 case VSX_BUILTIN_VEC_EXT_V2DF
:
13212 case VSX_BUILTIN_VEC_EXT_V2DI
:
13213 case VSX_BUILTIN_VEC_EXT_V1TI
:
13214 return altivec_expand_vec_ext_builtin (exp
, target
);
13218 /* Fall through. */
13221 /* Expand abs* operations. */
13223 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13224 if (d
->code
== fcode
)
13225 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
13227 /* Expand the AltiVec predicates. */
13228 d
= bdesc_altivec_preds
;
13229 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13230 if (d
->code
== fcode
)
13231 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
13233 /* LV* are funky. We initialized them differently. */
13236 case ALTIVEC_BUILTIN_LVSL
:
13237 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
13238 exp
, target
, false);
13239 case ALTIVEC_BUILTIN_LVSR
:
13240 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
13241 exp
, target
, false);
13242 case ALTIVEC_BUILTIN_LVEBX
:
13243 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
13244 exp
, target
, false);
13245 case ALTIVEC_BUILTIN_LVEHX
:
13246 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
13247 exp
, target
, false);
13248 case ALTIVEC_BUILTIN_LVEWX
:
13249 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
13250 exp
, target
, false);
13251 case ALTIVEC_BUILTIN_LVXL_V2DF
:
13252 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
13253 exp
, target
, false);
13254 case ALTIVEC_BUILTIN_LVXL_V2DI
:
13255 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
13256 exp
, target
, false);
13257 case ALTIVEC_BUILTIN_LVXL_V4SF
:
13258 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
13259 exp
, target
, false);
13260 case ALTIVEC_BUILTIN_LVXL
:
13261 case ALTIVEC_BUILTIN_LVXL_V4SI
:
13262 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
13263 exp
, target
, false);
13264 case ALTIVEC_BUILTIN_LVXL_V8HI
:
13265 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
13266 exp
, target
, false);
13267 case ALTIVEC_BUILTIN_LVXL_V16QI
:
13268 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
13269 exp
, target
, false);
13270 case ALTIVEC_BUILTIN_LVX_V2DF
:
13271 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
13272 exp
, target
, false);
13273 case ALTIVEC_BUILTIN_LVX_V2DI
:
13274 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
13275 exp
, target
, false);
13276 case ALTIVEC_BUILTIN_LVX_V4SF
:
13277 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
13278 exp
, target
, false);
13279 case ALTIVEC_BUILTIN_LVX
:
13280 case ALTIVEC_BUILTIN_LVX_V4SI
:
13281 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
13282 exp
, target
, false);
13283 case ALTIVEC_BUILTIN_LVX_V8HI
:
13284 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
13285 exp
, target
, false);
13286 case ALTIVEC_BUILTIN_LVX_V16QI
:
13287 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
13288 exp
, target
, false);
13289 case ALTIVEC_BUILTIN_LVLX
:
13290 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
13291 exp
, target
, true);
13292 case ALTIVEC_BUILTIN_LVLXL
:
13293 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
13294 exp
, target
, true);
13295 case ALTIVEC_BUILTIN_LVRX
:
13296 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
13297 exp
, target
, true);
13298 case ALTIVEC_BUILTIN_LVRXL
:
13299 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
13300 exp
, target
, true);
13301 case VSX_BUILTIN_LXVD2X_V1TI
:
13302 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
13303 exp
, target
, false);
13304 case VSX_BUILTIN_LXVD2X_V2DF
:
13305 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
13306 exp
, target
, false);
13307 case VSX_BUILTIN_LXVD2X_V2DI
:
13308 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
13309 exp
, target
, false);
13310 case VSX_BUILTIN_LXVW4X_V4SF
:
13311 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
13312 exp
, target
, false);
13313 case VSX_BUILTIN_LXVW4X_V4SI
:
13314 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
13315 exp
, target
, false);
13316 case VSX_BUILTIN_LXVW4X_V8HI
:
13317 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
13318 exp
, target
, false);
13319 case VSX_BUILTIN_LXVW4X_V16QI
:
13320 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
13321 exp
, target
, false);
13325 /* Fall through. */
13328 *expandedp
= false;
13332 /* Expand the builtin in EXP and store the result in TARGET. Store
13333 true in *EXPANDEDP if we found a builtin to expand. */
13335 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13337 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13338 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13339 const struct builtin_description
*d
;
13346 case PAIRED_BUILTIN_STX
:
13347 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
13348 case PAIRED_BUILTIN_LX
:
13349 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
13352 /* Fall through. */
13355 /* Expand the paired predicates. */
13356 d
= bdesc_paired_preds
;
13357 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
13358 if (d
->code
== fcode
)
13359 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
13361 *expandedp
= false;
13365 /* Binops that need to be initialized manually, but can be expanded
13366 automagically by rs6000_expand_binop_builtin. */
13367 static const struct builtin_description bdesc_2arg_spe
[] =
13369 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
13370 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
13371 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
13372 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
13373 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
13374 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
13375 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
13376 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
13377 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
13378 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
13379 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
13380 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
13381 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
13382 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
13383 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
13384 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
13385 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
13386 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
13387 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
13388 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
13389 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
13390 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
13393 /* Expand the builtin in EXP and store the result in TARGET. Store
13394 true in *EXPANDEDP if we found a builtin to expand.
13396 This expands the SPE builtins that are not simple unary and binary
13399 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13401 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13403 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13404 enum insn_code icode
;
13405 enum machine_mode tmode
, mode0
;
13407 const struct builtin_description
*d
;
13412 /* Syntax check for a 5-bit unsigned immediate. */
13415 case SPE_BUILTIN_EVSTDD
:
13416 case SPE_BUILTIN_EVSTDH
:
13417 case SPE_BUILTIN_EVSTDW
:
13418 case SPE_BUILTIN_EVSTWHE
:
13419 case SPE_BUILTIN_EVSTWHO
:
13420 case SPE_BUILTIN_EVSTWWE
:
13421 case SPE_BUILTIN_EVSTWWO
:
13422 arg1
= CALL_EXPR_ARG (exp
, 2);
13423 if (TREE_CODE (arg1
) != INTEGER_CST
13424 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13426 error ("argument 2 must be a 5-bit unsigned literal");
13434 /* The evsplat*i instructions are not quite generic. */
13437 case SPE_BUILTIN_EVSPLATFI
:
13438 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
13440 case SPE_BUILTIN_EVSPLATI
:
13441 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
13447 d
= bdesc_2arg_spe
;
13448 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
13449 if (d
->code
== fcode
)
13450 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13452 d
= bdesc_spe_predicates
;
13453 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
13454 if (d
->code
== fcode
)
13455 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
13457 d
= bdesc_spe_evsel
;
13458 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
13459 if (d
->code
== fcode
)
13460 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
13464 case SPE_BUILTIN_EVSTDDX
:
13465 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
13466 case SPE_BUILTIN_EVSTDHX
:
13467 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
13468 case SPE_BUILTIN_EVSTDWX
:
13469 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
13470 case SPE_BUILTIN_EVSTWHEX
:
13471 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
13472 case SPE_BUILTIN_EVSTWHOX
:
13473 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
13474 case SPE_BUILTIN_EVSTWWEX
:
13475 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
13476 case SPE_BUILTIN_EVSTWWOX
:
13477 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
13478 case SPE_BUILTIN_EVSTDD
:
13479 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
13480 case SPE_BUILTIN_EVSTDH
:
13481 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
13482 case SPE_BUILTIN_EVSTDW
:
13483 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
13484 case SPE_BUILTIN_EVSTWHE
:
13485 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
13486 case SPE_BUILTIN_EVSTWHO
:
13487 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
13488 case SPE_BUILTIN_EVSTWWE
:
13489 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
13490 case SPE_BUILTIN_EVSTWWO
:
13491 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
13492 case SPE_BUILTIN_MFSPEFSCR
:
13493 icode
= CODE_FOR_spe_mfspefscr
;
13494 tmode
= insn_data
[icode
].operand
[0].mode
;
13497 || GET_MODE (target
) != tmode
13498 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13499 target
= gen_reg_rtx (tmode
);
13501 pat
= GEN_FCN (icode
) (target
);
13506 case SPE_BUILTIN_MTSPEFSCR
:
13507 icode
= CODE_FOR_spe_mtspefscr
;
13508 arg0
= CALL_EXPR_ARG (exp
, 0);
13509 op0
= expand_normal (arg0
);
13510 mode0
= insn_data
[icode
].operand
[0].mode
;
13512 if (arg0
== error_mark_node
)
13515 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13516 op0
= copy_to_mode_reg (mode0
, op0
);
13518 pat
= GEN_FCN (icode
) (op0
);
13526 *expandedp
= false;
13531 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13533 rtx pat
, scratch
, tmp
;
13534 tree form
= CALL_EXPR_ARG (exp
, 0);
13535 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13536 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13537 rtx op0
= expand_normal (arg0
);
13538 rtx op1
= expand_normal (arg1
);
13539 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13540 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13542 enum rtx_code code
;
13544 if (TREE_CODE (form
) != INTEGER_CST
)
13546 error ("argument 1 of __builtin_paired_predicate must be a constant");
13550 form_int
= TREE_INT_CST_LOW (form
);
13552 gcc_assert (mode0
== mode1
);
13554 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13558 || GET_MODE (target
) != SImode
13559 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13560 target
= gen_reg_rtx (SImode
);
13561 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13562 op0
= copy_to_mode_reg (mode0
, op0
);
13563 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13564 op1
= copy_to_mode_reg (mode1
, op1
);
13566 scratch
= gen_reg_rtx (CCFPmode
);
13568 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13590 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13593 error ("argument 1 of __builtin_paired_predicate is out of range");
13597 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13598 emit_move_insn (target
, tmp
);
13603 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13605 rtx pat
, scratch
, tmp
;
13606 tree form
= CALL_EXPR_ARG (exp
, 0);
13607 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13608 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13609 rtx op0
= expand_normal (arg0
);
13610 rtx op1
= expand_normal (arg1
);
13611 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13612 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13614 enum rtx_code code
;
13616 if (TREE_CODE (form
) != INTEGER_CST
)
13618 error ("argument 1 of __builtin_spe_predicate must be a constant");
13622 form_int
= TREE_INT_CST_LOW (form
);
13624 gcc_assert (mode0
== mode1
);
13626 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13630 || GET_MODE (target
) != SImode
13631 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13632 target
= gen_reg_rtx (SImode
);
13634 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13635 op0
= copy_to_mode_reg (mode0
, op0
);
13636 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13637 op1
= copy_to_mode_reg (mode1
, op1
);
13639 scratch
= gen_reg_rtx (CCmode
);
13641 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13646 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13647 _lower_. We use one compare, but look in different bits of the
13648 CR for each variant.
13650 There are 2 elements in each SPE simd type (upper/lower). The CR
13651 bits are set as follows:
13653 BIT0 | BIT 1 | BIT 2 | BIT 3
13654 U | L | (U | L) | (U & L)
13656 So, for an "all" relationship, BIT 3 would be set.
13657 For an "any" relationship, BIT 2 would be set. Etc.
13659 Following traditional nomenclature, these bits map to:
13661 BIT0 | BIT 1 | BIT 2 | BIT 3
13664 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13669 /* All variant. OV bit. */
13671 /* We need to get to the OV bit, which is the ORDERED bit. We
13672 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13673 that's ugly and will make validate_condition_mode die.
13674 So let's just use another pattern. */
13675 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13677 /* Any variant. EQ bit. */
13681 /* Upper variant. LT bit. */
13685 /* Lower variant. GT bit. */
13690 error ("argument 1 of __builtin_spe_predicate is out of range");
13694 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13695 emit_move_insn (target
, tmp
);
13700 /* The evsel builtins look like this:
13702 e = __builtin_spe_evsel_OP (a, b, c, d);
13704 and work like this:
13706 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13707 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13711 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13714 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13715 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13716 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13717 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13718 rtx op0
= expand_normal (arg0
);
13719 rtx op1
= expand_normal (arg1
);
13720 rtx op2
= expand_normal (arg2
);
13721 rtx op3
= expand_normal (arg3
);
13722 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13723 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13725 gcc_assert (mode0
== mode1
);
13727 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13728 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13732 || GET_MODE (target
) != mode0
13733 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13734 target
= gen_reg_rtx (mode0
);
13736 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13737 op0
= copy_to_mode_reg (mode0
, op0
);
13738 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13739 op1
= copy_to_mode_reg (mode0
, op1
);
13740 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13741 op2
= copy_to_mode_reg (mode0
, op2
);
13742 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13743 op3
= copy_to_mode_reg (mode0
, op3
);
13745 /* Generate the compare. */
13746 scratch
= gen_reg_rtx (CCmode
);
13747 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13752 if (mode0
== V2SImode
)
13753 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13755 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13760 /* Raise an error message for a builtin function that is called without the
13761 appropriate target options being set. */
13764 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13766 size_t uns_fncode
= (size_t)fncode
;
13767 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13768 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13770 gcc_assert (name
!= NULL
);
13771 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13772 error ("Builtin function %s is only valid for the cell processor", name
);
13773 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13774 error ("Builtin function %s requires the -mvsx option", name
);
13775 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13776 error ("Builtin function %s requires the -mhtm option", name
);
13777 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13778 error ("Builtin function %s requires the -maltivec option", name
);
13779 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13780 error ("Builtin function %s requires the -mpaired option", name
);
13781 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13782 error ("Builtin function %s requires the -mspe option", name
);
13783 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
13784 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
13785 error ("Builtin function %s requires the -mhard-dfp and"
13786 " -mpower8-vector options", name
);
13787 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
13788 error ("Builtin function %s requires the -mhard-dfp option", name
);
13789 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
13790 error ("Builtin function %s requires the -mpower8-vector option", name
);
13791 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
13792 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
13793 error ("Builtin function %s requires the -mhard-float and"
13794 " -mlong-double-128 options", name
);
13795 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
13796 error ("Builtin function %s requires the -mhard-float option", name
);
13798 error ("Builtin function %s is not supported with the current options",
13802 /* Expand an expression EXP that calls a built-in function,
13803 with result going to TARGET if that's convenient
13804 (and in mode MODE if that's convenient).
13805 SUBTARGET may be used as the target for computing one of EXP's operands.
13806 IGNORE is nonzero if the value is to be ignored. */
13809 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13810 enum machine_mode mode ATTRIBUTE_UNUSED
,
13811 int ignore ATTRIBUTE_UNUSED
)
13813 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13814 enum rs6000_builtins fcode
13815 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13816 size_t uns_fcode
= (size_t)fcode
;
13817 const struct builtin_description
*d
;
13821 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13822 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13824 if (TARGET_DEBUG_BUILTIN
)
13826 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13827 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13828 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13829 ? get_insn_name ((int)icode
)
13833 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13835 default: name3
= "unknown"; break;
13836 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13837 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13838 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13839 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13840 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13841 case RS6000_BTC_ABS
: name3
= "abs"; break;
13842 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13843 case RS6000_BTC_DST
: name3
= "dst"; break;
13848 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13849 (name1
) ? name1
: "---", fcode
,
13850 (name2
) ? name2
: "---", (int)icode
,
13852 func_valid_p
? "" : ", not valid");
13857 rs6000_invalid_builtin (fcode
);
13859 /* Given it is invalid, just generate a normal call. */
13860 return expand_call (exp
, target
, ignore
);
13865 case RS6000_BUILTIN_RECIP
:
13866 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13868 case RS6000_BUILTIN_RECIPF
:
13869 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13871 case RS6000_BUILTIN_RSQRTF
:
13872 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13874 case RS6000_BUILTIN_RSQRT
:
13875 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13877 case POWER7_BUILTIN_BPERMD
:
13878 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13879 ? CODE_FOR_bpermd_di
13880 : CODE_FOR_bpermd_si
), exp
, target
);
13882 case RS6000_BUILTIN_GET_TB
:
13883 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13886 case RS6000_BUILTIN_MFTB
:
13887 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13888 ? CODE_FOR_rs6000_mftb_di
13889 : CODE_FOR_rs6000_mftb_si
),
13892 case RS6000_BUILTIN_MFFS
:
13893 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
13895 case RS6000_BUILTIN_MTFSF
:
13896 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
13898 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13899 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13901 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13902 : (int) CODE_FOR_altivec_lvsl
);
13903 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13904 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13908 gcc_assert (TARGET_ALTIVEC
);
13910 arg
= CALL_EXPR_ARG (exp
, 0);
13911 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13912 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13913 addr
= memory_address (mode
, op
);
13914 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13918 /* For the load case need to negate the address. */
13919 op
= gen_reg_rtx (GET_MODE (addr
));
13920 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13921 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13923 op
= gen_rtx_MEM (mode
, op
);
13926 || GET_MODE (target
) != tmode
13927 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13928 target
= gen_reg_rtx (tmode
);
13930 /*pat = gen_altivec_lvsr (target, op);*/
13931 pat
= GEN_FCN (icode
) (target
, op
);
13939 case ALTIVEC_BUILTIN_VCFUX
:
13940 case ALTIVEC_BUILTIN_VCFSX
:
13941 case ALTIVEC_BUILTIN_VCTUXS
:
13942 case ALTIVEC_BUILTIN_VCTSXS
:
13943 /* FIXME: There's got to be a nicer way to handle this case than
13944 constructing a new CALL_EXPR. */
13945 if (call_expr_nargs (exp
) == 1)
13947 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13948 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13956 if (TARGET_ALTIVEC
)
13958 ret
= altivec_expand_builtin (exp
, target
, &success
);
13965 ret
= spe_expand_builtin (exp
, target
, &success
);
13970 if (TARGET_PAIRED_FLOAT
)
13972 ret
= paired_expand_builtin (exp
, target
, &success
);
13979 ret
= htm_expand_builtin (exp
, target
, &success
);
13985 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
13986 gcc_assert (attr
== RS6000_BTC_UNARY
13987 || attr
== RS6000_BTC_BINARY
13988 || attr
== RS6000_BTC_TERNARY
);
13990 /* Handle simple unary operations. */
13992 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13993 if (d
->code
== fcode
)
13994 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13996 /* Handle simple binary operations. */
13998 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13999 if (d
->code
== fcode
)
14000 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
14002 /* Handle simple ternary operations. */
14004 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14005 if (d
->code
== fcode
)
14006 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
14008 gcc_unreachable ();
14012 rs6000_init_builtins (void)
14016 enum machine_mode mode
;
14018 if (TARGET_DEBUG_BUILTIN
)
14019 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
14020 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
14021 (TARGET_SPE
) ? ", spe" : "",
14022 (TARGET_ALTIVEC
) ? ", altivec" : "",
14023 (TARGET_VSX
) ? ", vsx" : "");
14025 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
14026 V2SF_type_node
= build_vector_type (float_type_node
, 2);
14027 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
14028 V2DF_type_node
= build_vector_type (double_type_node
, 2);
14029 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
14030 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
14031 V4SF_type_node
= build_vector_type (float_type_node
, 4);
14032 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
14033 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
14035 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
14036 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
14037 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
14038 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
14040 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
14041 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
14042 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
14043 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
14045 /* We use V1TI mode as a special container to hold __int128_t items that
14046 must live in VSX registers. */
14047 if (intTI_type_node
)
14049 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
14050 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
14053 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
14054 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
14055 'vector unsigned short'. */
14057 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
14058 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14059 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
14060 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
14061 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14063 long_integer_type_internal_node
= long_integer_type_node
;
14064 long_unsigned_type_internal_node
= long_unsigned_type_node
;
14065 long_long_integer_type_internal_node
= long_long_integer_type_node
;
14066 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
14067 intQI_type_internal_node
= intQI_type_node
;
14068 uintQI_type_internal_node
= unsigned_intQI_type_node
;
14069 intHI_type_internal_node
= intHI_type_node
;
14070 uintHI_type_internal_node
= unsigned_intHI_type_node
;
14071 intSI_type_internal_node
= intSI_type_node
;
14072 uintSI_type_internal_node
= unsigned_intSI_type_node
;
14073 intDI_type_internal_node
= intDI_type_node
;
14074 uintDI_type_internal_node
= unsigned_intDI_type_node
;
14075 intTI_type_internal_node
= intTI_type_node
;
14076 uintTI_type_internal_node
= unsigned_intTI_type_node
;
14077 float_type_internal_node
= float_type_node
;
14078 double_type_internal_node
= double_type_node
;
14079 long_double_type_internal_node
= long_double_type_node
;
14080 dfloat64_type_internal_node
= dfloat64_type_node
;
14081 dfloat128_type_internal_node
= dfloat128_type_node
;
14082 void_type_internal_node
= void_type_node
;
14084 /* Initialize the modes for builtin_function_type, mapping a machine mode to
14086 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
14087 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
14088 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
14089 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
14090 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
14091 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
14092 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
14093 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
14094 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
14095 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
14096 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
14097 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
14098 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
14099 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
14100 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
14101 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
14102 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
14103 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
14104 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
14105 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
14106 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
14107 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
14108 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
14109 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
14110 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
14111 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
14112 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
14113 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
14115 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
14116 TYPE_NAME (bool_char_type_node
) = tdecl
;
14118 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
14119 TYPE_NAME (bool_short_type_node
) = tdecl
;
14121 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
14122 TYPE_NAME (bool_int_type_node
) = tdecl
;
14124 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
14125 TYPE_NAME (pixel_type_node
) = tdecl
;
14127 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
14128 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
14129 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
14130 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
14131 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
14133 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
14134 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
14136 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
14137 TYPE_NAME (V16QI_type_node
) = tdecl
;
14139 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
14140 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
14142 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
14143 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
14145 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
14146 TYPE_NAME (V8HI_type_node
) = tdecl
;
14148 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
14149 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
14151 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
14152 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
14154 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
14155 TYPE_NAME (V4SI_type_node
) = tdecl
;
14157 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
14158 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
14160 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
14161 TYPE_NAME (V4SF_type_node
) = tdecl
;
14163 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
14164 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
14166 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
14167 TYPE_NAME (V2DF_type_node
) = tdecl
;
14169 if (TARGET_POWERPC64
)
14171 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
14172 TYPE_NAME (V2DI_type_node
) = tdecl
;
14174 tdecl
= add_builtin_type ("__vector unsigned long",
14175 unsigned_V2DI_type_node
);
14176 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
14178 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
14179 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14183 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
14184 TYPE_NAME (V2DI_type_node
) = tdecl
;
14186 tdecl
= add_builtin_type ("__vector unsigned long long",
14187 unsigned_V2DI_type_node
);
14188 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
14190 tdecl
= add_builtin_type ("__vector __bool long long",
14191 bool_V2DI_type_node
);
14192 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14195 if (V1TI_type_node
)
14197 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
14198 TYPE_NAME (V1TI_type_node
) = tdecl
;
14200 tdecl
= add_builtin_type ("__vector unsigned __int128",
14201 unsigned_V1TI_type_node
);
14202 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
14205 /* Paired and SPE builtins are only available if you build a compiler with
14206 the appropriate options, so only create those builtins with the
14207 appropriate compiler option. Create Altivec and VSX builtins on machines
14208 with at least the general purpose extensions (970 and newer) to allow the
14209 use of the target attribute. */
14210 if (TARGET_PAIRED_FLOAT
)
14211 paired_init_builtins ();
14213 spe_init_builtins ();
14214 if (TARGET_EXTRA_BUILTINS
)
14215 altivec_init_builtins ();
14217 htm_init_builtins ();
14219 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
14220 rs6000_common_init_builtins ();
14222 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
14223 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
14224 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
14226 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
14227 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
14228 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
14230 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
14231 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
14232 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
14234 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
14235 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
14236 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
14238 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
14239 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
14240 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
14241 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
14243 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14245 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
14248 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14251 ftype
= build_function_type_list (unsigned_intSI_type_node
,
14253 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
14255 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
14256 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
14258 ftype
= build_function_type_list (void_type_node
,
14259 intSI_type_node
, double_type_node
,
14261 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
14264 /* AIX libm provides clog as __clog. */
14265 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
14266 set_user_assembler_name (tdecl
, "__clog");
14269 #ifdef SUBTARGET_INIT_BUILTINS
14270 SUBTARGET_INIT_BUILTINS
;
14274 /* Returns the rs6000 builtin decl for CODE. */
14277 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
14279 HOST_WIDE_INT fnmask
;
14281 if (code
>= RS6000_BUILTIN_COUNT
)
14282 return error_mark_node
;
14284 fnmask
= rs6000_builtin_info
[code
].mask
;
14285 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
14287 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
14288 return error_mark_node
;
14291 return rs6000_builtin_decls
[code
];
14295 spe_init_builtins (void)
14297 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
14298 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
14299 const struct builtin_description
*d
;
14302 tree v2si_ftype_4_v2si
14303 = build_function_type_list (opaque_V2SI_type_node
,
14304 opaque_V2SI_type_node
,
14305 opaque_V2SI_type_node
,
14306 opaque_V2SI_type_node
,
14307 opaque_V2SI_type_node
,
14310 tree v2sf_ftype_4_v2sf
14311 = build_function_type_list (opaque_V2SF_type_node
,
14312 opaque_V2SF_type_node
,
14313 opaque_V2SF_type_node
,
14314 opaque_V2SF_type_node
,
14315 opaque_V2SF_type_node
,
14318 tree int_ftype_int_v2si_v2si
14319 = build_function_type_list (integer_type_node
,
14321 opaque_V2SI_type_node
,
14322 opaque_V2SI_type_node
,
14325 tree int_ftype_int_v2sf_v2sf
14326 = build_function_type_list (integer_type_node
,
14328 opaque_V2SF_type_node
,
14329 opaque_V2SF_type_node
,
14332 tree void_ftype_v2si_puint_int
14333 = build_function_type_list (void_type_node
,
14334 opaque_V2SI_type_node
,
14339 tree void_ftype_v2si_puint_char
14340 = build_function_type_list (void_type_node
,
14341 opaque_V2SI_type_node
,
14346 tree void_ftype_v2si_pv2si_int
14347 = build_function_type_list (void_type_node
,
14348 opaque_V2SI_type_node
,
14349 opaque_p_V2SI_type_node
,
14353 tree void_ftype_v2si_pv2si_char
14354 = build_function_type_list (void_type_node
,
14355 opaque_V2SI_type_node
,
14356 opaque_p_V2SI_type_node
,
14360 tree void_ftype_int
14361 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14363 tree int_ftype_void
14364 = build_function_type_list (integer_type_node
, NULL_TREE
);
14366 tree v2si_ftype_pv2si_int
14367 = build_function_type_list (opaque_V2SI_type_node
,
14368 opaque_p_V2SI_type_node
,
14372 tree v2si_ftype_puint_int
14373 = build_function_type_list (opaque_V2SI_type_node
,
14378 tree v2si_ftype_pushort_int
14379 = build_function_type_list (opaque_V2SI_type_node
,
14384 tree v2si_ftype_signed_char
14385 = build_function_type_list (opaque_V2SI_type_node
,
14386 signed_char_type_node
,
14389 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
14391 /* Initialize irregular SPE builtins. */
14393 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
14394 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
14395 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
14396 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
14397 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
14398 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
14399 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
14400 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
14401 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
14402 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
14403 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
14404 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
14405 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
14406 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
14407 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
14408 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
14409 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
14410 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
14413 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
14414 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
14415 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
14416 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
14417 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
14418 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
14419 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
14420 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
14421 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
14422 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
14423 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
14424 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
14425 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
14426 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
14427 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
14428 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
14429 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
14430 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
14431 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
14432 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
14433 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
14434 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
14437 d
= bdesc_spe_predicates
;
14438 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
14442 switch (insn_data
[d
->icode
].operand
[1].mode
)
14445 type
= int_ftype_int_v2si_v2si
;
14448 type
= int_ftype_int_v2sf_v2sf
;
14451 gcc_unreachable ();
14454 def_builtin (d
->name
, type
, d
->code
);
14457 /* Evsel predicates. */
14458 d
= bdesc_spe_evsel
;
14459 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
14463 switch (insn_data
[d
->icode
].operand
[1].mode
)
14466 type
= v2si_ftype_4_v2si
;
14469 type
= v2sf_ftype_4_v2sf
;
14472 gcc_unreachable ();
14475 def_builtin (d
->name
, type
, d
->code
);
14480 paired_init_builtins (void)
14482 const struct builtin_description
*d
;
14485 tree int_ftype_int_v2sf_v2sf
14486 = build_function_type_list (integer_type_node
,
14491 tree pcfloat_type_node
=
14492 build_pointer_type (build_qualified_type
14493 (float_type_node
, TYPE_QUAL_CONST
));
14495 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
14496 long_integer_type_node
,
14499 tree void_ftype_v2sf_long_pcfloat
=
14500 build_function_type_list (void_type_node
,
14502 long_integer_type_node
,
14507 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
14508 PAIRED_BUILTIN_LX
);
14511 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
14512 PAIRED_BUILTIN_STX
);
14515 d
= bdesc_paired_preds
;
14516 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
14520 if (TARGET_DEBUG_BUILTIN
)
14521 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
14522 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
14523 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
14525 switch (insn_data
[d
->icode
].operand
[1].mode
)
14528 type
= int_ftype_int_v2sf_v2sf
;
14531 gcc_unreachable ();
14534 def_builtin (d
->name
, type
, d
->code
);
14539 altivec_init_builtins (void)
14541 const struct builtin_description
*d
;
14546 tree pvoid_type_node
= build_pointer_type (void_type_node
);
14548 tree pcvoid_type_node
14549 = build_pointer_type (build_qualified_type (void_type_node
,
14552 tree int_ftype_opaque
14553 = build_function_type_list (integer_type_node
,
14554 opaque_V4SI_type_node
, NULL_TREE
);
14555 tree opaque_ftype_opaque
14556 = build_function_type_list (integer_type_node
, NULL_TREE
);
14557 tree opaque_ftype_opaque_int
14558 = build_function_type_list (opaque_V4SI_type_node
,
14559 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
14560 tree opaque_ftype_opaque_opaque_int
14561 = build_function_type_list (opaque_V4SI_type_node
,
14562 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
14563 integer_type_node
, NULL_TREE
);
14564 tree int_ftype_int_opaque_opaque
14565 = build_function_type_list (integer_type_node
,
14566 integer_type_node
, opaque_V4SI_type_node
,
14567 opaque_V4SI_type_node
, NULL_TREE
);
14568 tree int_ftype_int_v4si_v4si
14569 = build_function_type_list (integer_type_node
,
14570 integer_type_node
, V4SI_type_node
,
14571 V4SI_type_node
, NULL_TREE
);
14572 tree int_ftype_int_v2di_v2di
14573 = build_function_type_list (integer_type_node
,
14574 integer_type_node
, V2DI_type_node
,
14575 V2DI_type_node
, NULL_TREE
);
14576 tree void_ftype_v4si
14577 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
14578 tree v8hi_ftype_void
14579 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
14580 tree void_ftype_void
14581 = build_function_type_list (void_type_node
, NULL_TREE
);
14582 tree void_ftype_int
14583 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14585 tree opaque_ftype_long_pcvoid
14586 = build_function_type_list (opaque_V4SI_type_node
,
14587 long_integer_type_node
, pcvoid_type_node
,
14589 tree v16qi_ftype_long_pcvoid
14590 = build_function_type_list (V16QI_type_node
,
14591 long_integer_type_node
, pcvoid_type_node
,
14593 tree v8hi_ftype_long_pcvoid
14594 = build_function_type_list (V8HI_type_node
,
14595 long_integer_type_node
, pcvoid_type_node
,
14597 tree v4si_ftype_long_pcvoid
14598 = build_function_type_list (V4SI_type_node
,
14599 long_integer_type_node
, pcvoid_type_node
,
14601 tree v4sf_ftype_long_pcvoid
14602 = build_function_type_list (V4SF_type_node
,
14603 long_integer_type_node
, pcvoid_type_node
,
14605 tree v2df_ftype_long_pcvoid
14606 = build_function_type_list (V2DF_type_node
,
14607 long_integer_type_node
, pcvoid_type_node
,
14609 tree v2di_ftype_long_pcvoid
14610 = build_function_type_list (V2DI_type_node
,
14611 long_integer_type_node
, pcvoid_type_node
,
14614 tree void_ftype_opaque_long_pvoid
14615 = build_function_type_list (void_type_node
,
14616 opaque_V4SI_type_node
, long_integer_type_node
,
14617 pvoid_type_node
, NULL_TREE
);
14618 tree void_ftype_v4si_long_pvoid
14619 = build_function_type_list (void_type_node
,
14620 V4SI_type_node
, long_integer_type_node
,
14621 pvoid_type_node
, NULL_TREE
);
14622 tree void_ftype_v16qi_long_pvoid
14623 = build_function_type_list (void_type_node
,
14624 V16QI_type_node
, long_integer_type_node
,
14625 pvoid_type_node
, NULL_TREE
);
14626 tree void_ftype_v8hi_long_pvoid
14627 = build_function_type_list (void_type_node
,
14628 V8HI_type_node
, long_integer_type_node
,
14629 pvoid_type_node
, NULL_TREE
);
14630 tree void_ftype_v4sf_long_pvoid
14631 = build_function_type_list (void_type_node
,
14632 V4SF_type_node
, long_integer_type_node
,
14633 pvoid_type_node
, NULL_TREE
);
14634 tree void_ftype_v2df_long_pvoid
14635 = build_function_type_list (void_type_node
,
14636 V2DF_type_node
, long_integer_type_node
,
14637 pvoid_type_node
, NULL_TREE
);
14638 tree void_ftype_v2di_long_pvoid
14639 = build_function_type_list (void_type_node
,
14640 V2DI_type_node
, long_integer_type_node
,
14641 pvoid_type_node
, NULL_TREE
);
14642 tree int_ftype_int_v8hi_v8hi
14643 = build_function_type_list (integer_type_node
,
14644 integer_type_node
, V8HI_type_node
,
14645 V8HI_type_node
, NULL_TREE
);
14646 tree int_ftype_int_v16qi_v16qi
14647 = build_function_type_list (integer_type_node
,
14648 integer_type_node
, V16QI_type_node
,
14649 V16QI_type_node
, NULL_TREE
);
14650 tree int_ftype_int_v4sf_v4sf
14651 = build_function_type_list (integer_type_node
,
14652 integer_type_node
, V4SF_type_node
,
14653 V4SF_type_node
, NULL_TREE
);
14654 tree int_ftype_int_v2df_v2df
14655 = build_function_type_list (integer_type_node
,
14656 integer_type_node
, V2DF_type_node
,
14657 V2DF_type_node
, NULL_TREE
);
14658 tree v2di_ftype_v2di
14659 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
14660 tree v4si_ftype_v4si
14661 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
14662 tree v8hi_ftype_v8hi
14663 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
14664 tree v16qi_ftype_v16qi
14665 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
14666 tree v4sf_ftype_v4sf
14667 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
14668 tree v2df_ftype_v2df
14669 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
14670 tree void_ftype_pcvoid_int_int
14671 = build_function_type_list (void_type_node
,
14672 pcvoid_type_node
, integer_type_node
,
14673 integer_type_node
, NULL_TREE
);
14675 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
14676 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
14677 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
14678 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
14679 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
14680 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
14681 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
14682 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
14683 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
14684 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
14685 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
14686 ALTIVEC_BUILTIN_LVXL_V2DF
);
14687 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
14688 ALTIVEC_BUILTIN_LVXL_V2DI
);
14689 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
14690 ALTIVEC_BUILTIN_LVXL_V4SF
);
14691 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
14692 ALTIVEC_BUILTIN_LVXL_V4SI
);
14693 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
14694 ALTIVEC_BUILTIN_LVXL_V8HI
);
14695 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
14696 ALTIVEC_BUILTIN_LVXL_V16QI
);
14697 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
14698 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
14699 ALTIVEC_BUILTIN_LVX_V2DF
);
14700 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
14701 ALTIVEC_BUILTIN_LVX_V2DI
);
14702 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
14703 ALTIVEC_BUILTIN_LVX_V4SF
);
14704 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
14705 ALTIVEC_BUILTIN_LVX_V4SI
);
14706 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
14707 ALTIVEC_BUILTIN_LVX_V8HI
);
14708 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
14709 ALTIVEC_BUILTIN_LVX_V16QI
);
14710 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
14711 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
14712 ALTIVEC_BUILTIN_STVX_V2DF
);
14713 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
14714 ALTIVEC_BUILTIN_STVX_V2DI
);
14715 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
14716 ALTIVEC_BUILTIN_STVX_V4SF
);
14717 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
14718 ALTIVEC_BUILTIN_STVX_V4SI
);
14719 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
14720 ALTIVEC_BUILTIN_STVX_V8HI
);
14721 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
14722 ALTIVEC_BUILTIN_STVX_V16QI
);
14723 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
14724 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
14725 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
14726 ALTIVEC_BUILTIN_STVXL_V2DF
);
14727 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
14728 ALTIVEC_BUILTIN_STVXL_V2DI
);
14729 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
14730 ALTIVEC_BUILTIN_STVXL_V4SF
);
14731 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
14732 ALTIVEC_BUILTIN_STVXL_V4SI
);
14733 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
14734 ALTIVEC_BUILTIN_STVXL_V8HI
);
14735 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
14736 ALTIVEC_BUILTIN_STVXL_V16QI
);
14737 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
14738 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
14739 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
14740 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
14741 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
14742 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
14743 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
14744 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
14745 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
14746 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
14747 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
14748 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
14749 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
14750 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
14751 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
14752 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
14754 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
14755 VSX_BUILTIN_LXVD2X_V2DF
);
14756 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14757 VSX_BUILTIN_LXVD2X_V2DI
);
14758 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14759 VSX_BUILTIN_LXVW4X_V4SF
);
14760 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14761 VSX_BUILTIN_LXVW4X_V4SI
);
14762 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14763 VSX_BUILTIN_LXVW4X_V8HI
);
14764 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14765 VSX_BUILTIN_LXVW4X_V16QI
);
14766 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14767 VSX_BUILTIN_STXVD2X_V2DF
);
14768 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14769 VSX_BUILTIN_STXVD2X_V2DI
);
14770 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14771 VSX_BUILTIN_STXVW4X_V4SF
);
14772 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14773 VSX_BUILTIN_STXVW4X_V4SI
);
14774 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14775 VSX_BUILTIN_STXVW4X_V8HI
);
14776 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14777 VSX_BUILTIN_STXVW4X_V16QI
);
14778 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14779 VSX_BUILTIN_VEC_LD
);
14780 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14781 VSX_BUILTIN_VEC_ST
);
14783 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14784 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14785 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14787 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14788 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14789 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14790 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14791 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14792 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14793 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14794 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14795 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14796 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14797 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14798 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14800 /* Cell builtins. */
14801 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14802 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14803 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14804 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14806 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14807 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14808 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14809 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14811 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14812 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14813 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14814 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14816 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14817 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14818 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14819 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14821 /* Add the DST variants. */
14823 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14824 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14826 /* Initialize the predicates. */
14827 d
= bdesc_altivec_preds
;
14828 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14830 enum machine_mode mode1
;
14833 if (rs6000_overloaded_builtin_p (d
->code
))
14836 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14841 type
= int_ftype_int_opaque_opaque
;
14844 type
= int_ftype_int_v2di_v2di
;
14847 type
= int_ftype_int_v4si_v4si
;
14850 type
= int_ftype_int_v8hi_v8hi
;
14853 type
= int_ftype_int_v16qi_v16qi
;
14856 type
= int_ftype_int_v4sf_v4sf
;
14859 type
= int_ftype_int_v2df_v2df
;
14862 gcc_unreachable ();
14865 def_builtin (d
->name
, type
, d
->code
);
14868 /* Initialize the abs* operators. */
14870 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14872 enum machine_mode mode0
;
14875 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14880 type
= v2di_ftype_v2di
;
14883 type
= v4si_ftype_v4si
;
14886 type
= v8hi_ftype_v8hi
;
14889 type
= v16qi_ftype_v16qi
;
14892 type
= v4sf_ftype_v4sf
;
14895 type
= v2df_ftype_v2df
;
14898 gcc_unreachable ();
14901 def_builtin (d
->name
, type
, d
->code
);
14904 /* Initialize target builtin that implements
14905 targetm.vectorize.builtin_mask_for_load. */
14907 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14908 v16qi_ftype_long_pcvoid
,
14909 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14910 BUILT_IN_MD
, NULL
, NULL_TREE
);
14911 TREE_READONLY (decl
) = 1;
14912 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14913 altivec_builtin_mask_for_load
= decl
;
14915 /* Access to the vec_init patterns. */
14916 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14917 integer_type_node
, integer_type_node
,
14918 integer_type_node
, NULL_TREE
);
14919 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14921 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14922 short_integer_type_node
,
14923 short_integer_type_node
,
14924 short_integer_type_node
,
14925 short_integer_type_node
,
14926 short_integer_type_node
,
14927 short_integer_type_node
,
14928 short_integer_type_node
, NULL_TREE
);
14929 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14931 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14932 char_type_node
, char_type_node
,
14933 char_type_node
, char_type_node
,
14934 char_type_node
, char_type_node
,
14935 char_type_node
, char_type_node
,
14936 char_type_node
, char_type_node
,
14937 char_type_node
, char_type_node
,
14938 char_type_node
, char_type_node
,
14939 char_type_node
, NULL_TREE
);
14940 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14941 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14943 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14944 float_type_node
, float_type_node
,
14945 float_type_node
, NULL_TREE
);
14946 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14948 /* VSX builtins. */
14949 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14950 double_type_node
, NULL_TREE
);
14951 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14953 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14954 intDI_type_node
, NULL_TREE
);
14955 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14957 /* Access to the vec_set patterns. */
14958 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14960 integer_type_node
, NULL_TREE
);
14961 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14963 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14965 integer_type_node
, NULL_TREE
);
14966 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14968 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14970 integer_type_node
, NULL_TREE
);
14971 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14973 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14975 integer_type_node
, NULL_TREE
);
14976 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14978 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14980 integer_type_node
, NULL_TREE
);
14981 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14983 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14985 integer_type_node
, NULL_TREE
);
14986 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14988 /* Access to the vec_extract patterns. */
14989 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14990 integer_type_node
, NULL_TREE
);
14991 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14993 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14994 integer_type_node
, NULL_TREE
);
14995 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14997 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14998 integer_type_node
, NULL_TREE
);
14999 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
15001 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
15002 integer_type_node
, NULL_TREE
);
15003 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
15005 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
15006 integer_type_node
, NULL_TREE
);
15007 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
15009 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
15010 integer_type_node
, NULL_TREE
);
15011 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
15014 if (V1TI_type_node
)
15016 tree v1ti_ftype_long_pcvoid
15017 = build_function_type_list (V1TI_type_node
,
15018 long_integer_type_node
, pcvoid_type_node
,
15020 tree void_ftype_v1ti_long_pvoid
15021 = build_function_type_list (void_type_node
,
15022 V1TI_type_node
, long_integer_type_node
,
15023 pvoid_type_node
, NULL_TREE
);
15024 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
15025 VSX_BUILTIN_LXVD2X_V1TI
);
15026 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
15027 VSX_BUILTIN_STXVD2X_V1TI
);
15028 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
15029 NULL_TREE
, NULL_TREE
);
15030 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
15031 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
15033 integer_type_node
, NULL_TREE
);
15034 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
15035 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
15036 integer_type_node
, NULL_TREE
);
15037 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
15043 htm_init_builtins (void)
15045 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15046 const struct builtin_description
*d
;
15050 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
15052 tree op
[MAX_HTM_OPERANDS
], type
;
15053 HOST_WIDE_INT mask
= d
->mask
;
15054 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
15055 bool void_func
= (attr
& RS6000_BTC_VOID
);
15056 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
15058 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
15059 : unsigned_type_node
;
15061 if ((mask
& builtin_mask
) != mask
)
15063 if (TARGET_DEBUG_BUILTIN
)
15064 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
15070 if (TARGET_DEBUG_BUILTIN
)
15071 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
15072 (long unsigned) i
);
15076 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
15078 if (attr_args
== RS6000_BTC_UNARY
)
15079 op
[nopnds
++] = argtype
;
15080 else if (attr_args
== RS6000_BTC_BINARY
)
15082 op
[nopnds
++] = argtype
;
15083 op
[nopnds
++] = argtype
;
15085 else if (attr_args
== RS6000_BTC_TERNARY
)
15087 op
[nopnds
++] = argtype
;
15088 op
[nopnds
++] = argtype
;
15089 op
[nopnds
++] = argtype
;
15095 type
= build_function_type_list (op
[0], NULL_TREE
);
15098 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
15101 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
15104 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
15108 gcc_unreachable ();
15111 def_builtin (d
->name
, type
, d
->code
);
15115 /* Hash function for builtin functions with up to 3 arguments and a return
15118 builtin_hash_function (const void *hash_entry
)
15122 const struct builtin_hash_struct
*bh
=
15123 (const struct builtin_hash_struct
*) hash_entry
;
15125 for (i
= 0; i
< 4; i
++)
15127 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
15128 ret
= (ret
* 2) + bh
->uns_p
[i
];
15134 /* Compare builtin hash entries H1 and H2 for equivalence. */
15136 builtin_hash_eq (const void *h1
, const void *h2
)
15138 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
15139 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
15141 return ((p1
->mode
[0] == p2
->mode
[0])
15142 && (p1
->mode
[1] == p2
->mode
[1])
15143 && (p1
->mode
[2] == p2
->mode
[2])
15144 && (p1
->mode
[3] == p2
->mode
[3])
15145 && (p1
->uns_p
[0] == p2
->uns_p
[0])
15146 && (p1
->uns_p
[1] == p2
->uns_p
[1])
15147 && (p1
->uns_p
[2] == p2
->uns_p
[2])
15148 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
15151 /* Map types for builtin functions with an explicit return type and up to 3
15152 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
15153 of the argument. */
15155 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
15156 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
15157 enum rs6000_builtins builtin
, const char *name
)
15159 struct builtin_hash_struct h
;
15160 struct builtin_hash_struct
*h2
;
15164 tree ret_type
= NULL_TREE
;
15165 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
15167 /* Create builtin_hash_table. */
15168 if (builtin_hash_table
== NULL
)
15169 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
15170 builtin_hash_eq
, NULL
);
15172 h
.type
= NULL_TREE
;
15173 h
.mode
[0] = mode_ret
;
15174 h
.mode
[1] = mode_arg0
;
15175 h
.mode
[2] = mode_arg1
;
15176 h
.mode
[3] = mode_arg2
;
15182 /* If the builtin is a type that produces unsigned results or takes unsigned
15183 arguments, and it is returned as a decl for the vectorizer (such as
15184 widening multiplies, permute), make sure the arguments and return value
15185 are type correct. */
15188 /* unsigned 1 argument functions. */
15189 case CRYPTO_BUILTIN_VSBOX
:
15190 case P8V_BUILTIN_VGBBD
:
15191 case MISC_BUILTIN_CDTBCD
:
15192 case MISC_BUILTIN_CBCDTD
:
15197 /* unsigned 2 argument functions. */
15198 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
15199 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
15200 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
15201 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
15202 case CRYPTO_BUILTIN_VCIPHER
:
15203 case CRYPTO_BUILTIN_VCIPHERLAST
:
15204 case CRYPTO_BUILTIN_VNCIPHER
:
15205 case CRYPTO_BUILTIN_VNCIPHERLAST
:
15206 case CRYPTO_BUILTIN_VPMSUMB
:
15207 case CRYPTO_BUILTIN_VPMSUMH
:
15208 case CRYPTO_BUILTIN_VPMSUMW
:
15209 case CRYPTO_BUILTIN_VPMSUMD
:
15210 case CRYPTO_BUILTIN_VPMSUM
:
15211 case MISC_BUILTIN_ADDG6S
:
15212 case MISC_BUILTIN_DIVWEU
:
15213 case MISC_BUILTIN_DIVWEUO
:
15214 case MISC_BUILTIN_DIVDEU
:
15215 case MISC_BUILTIN_DIVDEUO
:
15221 /* unsigned 3 argument functions. */
15222 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
15223 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
15224 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
15225 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
15226 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
15227 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
15228 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
15229 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
15230 case VSX_BUILTIN_VPERM_16QI_UNS
:
15231 case VSX_BUILTIN_VPERM_8HI_UNS
:
15232 case VSX_BUILTIN_VPERM_4SI_UNS
:
15233 case VSX_BUILTIN_VPERM_2DI_UNS
:
15234 case VSX_BUILTIN_XXSEL_16QI_UNS
:
15235 case VSX_BUILTIN_XXSEL_8HI_UNS
:
15236 case VSX_BUILTIN_XXSEL_4SI_UNS
:
15237 case VSX_BUILTIN_XXSEL_2DI_UNS
:
15238 case CRYPTO_BUILTIN_VPERMXOR
:
15239 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
15240 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
15241 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
15242 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
15243 case CRYPTO_BUILTIN_VSHASIGMAW
:
15244 case CRYPTO_BUILTIN_VSHASIGMAD
:
15245 case CRYPTO_BUILTIN_VSHASIGMA
:
15252 /* signed permute functions with unsigned char mask. */
15253 case ALTIVEC_BUILTIN_VPERM_16QI
:
15254 case ALTIVEC_BUILTIN_VPERM_8HI
:
15255 case ALTIVEC_BUILTIN_VPERM_4SI
:
15256 case ALTIVEC_BUILTIN_VPERM_4SF
:
15257 case ALTIVEC_BUILTIN_VPERM_2DI
:
15258 case ALTIVEC_BUILTIN_VPERM_2DF
:
15259 case VSX_BUILTIN_VPERM_16QI
:
15260 case VSX_BUILTIN_VPERM_8HI
:
15261 case VSX_BUILTIN_VPERM_4SI
:
15262 case VSX_BUILTIN_VPERM_4SF
:
15263 case VSX_BUILTIN_VPERM_2DI
:
15264 case VSX_BUILTIN_VPERM_2DF
:
15268 /* unsigned args, signed return. */
15269 case VSX_BUILTIN_XVCVUXDDP_UNS
:
15270 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
15274 /* signed args, unsigned return. */
15275 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
15276 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
15277 case MISC_BUILTIN_UNPACK_TD
:
15278 case MISC_BUILTIN_UNPACK_V1TI
:
15282 /* unsigned arguments for 128-bit pack instructions. */
15283 case MISC_BUILTIN_PACK_TD
:
15284 case MISC_BUILTIN_PACK_V1TI
:
15293 /* Figure out how many args are present. */
15294 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
15298 fatal_error ("internal error: builtin function %s had no type", name
);
15300 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
15301 if (!ret_type
&& h
.uns_p
[0])
15302 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
15305 fatal_error ("internal error: builtin function %s had an unexpected "
15306 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
15308 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
15309 arg_type
[i
] = NULL_TREE
;
15311 for (i
= 0; i
< num_args
; i
++)
15313 int m
= (int) h
.mode
[i
+1];
15314 int uns_p
= h
.uns_p
[i
+1];
15316 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
15317 if (!arg_type
[i
] && uns_p
)
15318 arg_type
[i
] = builtin_mode_to_type
[m
][0];
15321 fatal_error ("internal error: builtin function %s, argument %d "
15322 "had unexpected argument type %s", name
, i
,
15323 GET_MODE_NAME (m
));
15326 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
15327 if (*found
== NULL
)
15329 h2
= ggc_alloc
<builtin_hash_struct
> ();
15331 *found
= (void *)h2
;
15333 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
15334 arg_type
[2], NULL_TREE
);
15337 return ((struct builtin_hash_struct
*)(*found
))->type
;
15341 rs6000_common_init_builtins (void)
15343 const struct builtin_description
*d
;
15346 tree opaque_ftype_opaque
= NULL_TREE
;
15347 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
15348 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
15349 tree v2si_ftype_qi
= NULL_TREE
;
15350 tree v2si_ftype_v2si_qi
= NULL_TREE
;
15351 tree v2si_ftype_int_qi
= NULL_TREE
;
15352 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15354 if (!TARGET_PAIRED_FLOAT
)
15356 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
15357 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
15360 /* Paired and SPE builtins are only available if you build a compiler with
15361 the appropriate options, so only create those builtins with the
15362 appropriate compiler option. Create Altivec and VSX builtins on machines
15363 with at least the general purpose extensions (970 and newer) to allow the
15364 use of the target attribute.. */
15366 if (TARGET_EXTRA_BUILTINS
)
15367 builtin_mask
|= RS6000_BTM_COMMON
;
15369 /* Add the ternary operators. */
15371 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
15374 HOST_WIDE_INT mask
= d
->mask
;
15376 if ((mask
& builtin_mask
) != mask
)
15378 if (TARGET_DEBUG_BUILTIN
)
15379 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
15383 if (rs6000_overloaded_builtin_p (d
->code
))
15385 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
15386 type
= opaque_ftype_opaque_opaque_opaque
15387 = build_function_type_list (opaque_V4SI_type_node
,
15388 opaque_V4SI_type_node
,
15389 opaque_V4SI_type_node
,
15390 opaque_V4SI_type_node
,
15395 enum insn_code icode
= d
->icode
;
15398 if (TARGET_DEBUG_BUILTIN
)
15399 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15405 if (icode
== CODE_FOR_nothing
)
15407 if (TARGET_DEBUG_BUILTIN
)
15408 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
15414 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
15415 insn_data
[icode
].operand
[1].mode
,
15416 insn_data
[icode
].operand
[2].mode
,
15417 insn_data
[icode
].operand
[3].mode
,
15421 def_builtin (d
->name
, type
, d
->code
);
15424 /* Add the binary operators. */
15426 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
15428 enum machine_mode mode0
, mode1
, mode2
;
15430 HOST_WIDE_INT mask
= d
->mask
;
15432 if ((mask
& builtin_mask
) != mask
)
15434 if (TARGET_DEBUG_BUILTIN
)
15435 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
15439 if (rs6000_overloaded_builtin_p (d
->code
))
15441 if (! (type
= opaque_ftype_opaque_opaque
))
15442 type
= opaque_ftype_opaque_opaque
15443 = build_function_type_list (opaque_V4SI_type_node
,
15444 opaque_V4SI_type_node
,
15445 opaque_V4SI_type_node
,
15450 enum insn_code icode
= d
->icode
;
15453 if (TARGET_DEBUG_BUILTIN
)
15454 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15460 if (icode
== CODE_FOR_nothing
)
15462 if (TARGET_DEBUG_BUILTIN
)
15463 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
15469 mode0
= insn_data
[icode
].operand
[0].mode
;
15470 mode1
= insn_data
[icode
].operand
[1].mode
;
15471 mode2
= insn_data
[icode
].operand
[2].mode
;
15473 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
15475 if (! (type
= v2si_ftype_v2si_qi
))
15476 type
= v2si_ftype_v2si_qi
15477 = build_function_type_list (opaque_V2SI_type_node
,
15478 opaque_V2SI_type_node
,
15483 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
15484 && mode2
== QImode
)
15486 if (! (type
= v2si_ftype_int_qi
))
15487 type
= v2si_ftype_int_qi
15488 = build_function_type_list (opaque_V2SI_type_node
,
15495 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
15499 def_builtin (d
->name
, type
, d
->code
);
15502 /* Add the simple unary operators. */
15504 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
15506 enum machine_mode mode0
, mode1
;
15508 HOST_WIDE_INT mask
= d
->mask
;
15510 if ((mask
& builtin_mask
) != mask
)
15512 if (TARGET_DEBUG_BUILTIN
)
15513 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
15517 if (rs6000_overloaded_builtin_p (d
->code
))
15519 if (! (type
= opaque_ftype_opaque
))
15520 type
= opaque_ftype_opaque
15521 = build_function_type_list (opaque_V4SI_type_node
,
15522 opaque_V4SI_type_node
,
15527 enum insn_code icode
= d
->icode
;
15530 if (TARGET_DEBUG_BUILTIN
)
15531 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15537 if (icode
== CODE_FOR_nothing
)
15539 if (TARGET_DEBUG_BUILTIN
)
15540 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
15546 mode0
= insn_data
[icode
].operand
[0].mode
;
15547 mode1
= insn_data
[icode
].operand
[1].mode
;
15549 if (mode0
== V2SImode
&& mode1
== QImode
)
15551 if (! (type
= v2si_ftype_qi
))
15552 type
= v2si_ftype_qi
15553 = build_function_type_list (opaque_V2SI_type_node
,
15559 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
15563 def_builtin (d
->name
, type
, d
->code
);
15568 rs6000_init_libfuncs (void)
15570 if (!TARGET_IEEEQUAD
)
15571 /* AIX/Darwin/64-bit Linux quad floating point routines. */
15572 if (!TARGET_XL_COMPAT
)
15574 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
15575 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
15576 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
15577 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
15579 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
15581 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
15582 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
15583 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
15584 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
15585 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
15586 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
15587 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
15589 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
15590 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
15591 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
15592 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
15593 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
15594 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
15595 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
15596 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
15599 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
15600 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
15604 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
15605 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
15606 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
15607 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
15611 /* 32-bit SVR4 quad floating point routines. */
15613 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
15614 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
15615 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
15616 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
15617 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
15618 if (TARGET_PPC_GPOPT
)
15619 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
15621 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
15622 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
15623 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
15624 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
15625 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
15626 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
15628 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
15629 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
15630 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
15631 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
15632 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
15633 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
15634 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
15635 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
15640 /* Expand a block clear operation, and return 1 if successful. Return 0
15641 if we should let the compiler generate normal code.
15643 operands[0] is the destination
15644 operands[1] is the length
15645 operands[3] is the alignment */
15648 expand_block_clear (rtx operands
[])
15650 rtx orig_dest
= operands
[0];
15651 rtx bytes_rtx
= operands
[1];
15652 rtx align_rtx
= operands
[3];
15653 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15654 HOST_WIDE_INT align
;
15655 HOST_WIDE_INT bytes
;
15660 /* If this is not a fixed size move, just call memcpy */
15664 /* This must be a fixed size alignment */
15665 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15666 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15668 /* Anything to clear? */
15669 bytes
= INTVAL (bytes_rtx
);
15673 /* Use the builtin memset after a point, to avoid huge code bloat.
15674 When optimize_size, avoid any significant code bloat; calling
15675 memset is about 4 instructions, so allow for one instruction to
15676 load zero and three to do clearing. */
15677 if (TARGET_ALTIVEC
&& align
>= 128)
15679 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
15681 else if (TARGET_SPE
&& align
>= 64)
15686 if (optimize_size
&& bytes
> 3 * clear_step
)
15688 if (! optimize_size
&& bytes
> 8 * clear_step
)
15691 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
15693 enum machine_mode mode
= BLKmode
;
15696 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
15701 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
15706 else if (bytes
>= 8 && TARGET_POWERPC64
15707 && (align
>= 64 || !STRICT_ALIGNMENT
))
15711 if (offset
== 0 && align
< 64)
15715 /* If the address form is reg+offset with offset not a
15716 multiple of four, reload into reg indirect form here
15717 rather than waiting for reload. This way we get one
15718 reload, not one per store. */
15719 addr
= XEXP (orig_dest
, 0);
15720 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15721 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15722 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15724 addr
= copy_addr_to_reg (addr
);
15725 orig_dest
= replace_equiv_address (orig_dest
, addr
);
15729 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15730 { /* move 4 bytes */
15734 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15735 { /* move 2 bytes */
15739 else /* move 1 byte at a time */
15745 dest
= adjust_address (orig_dest
, mode
, offset
);
15747 emit_move_insn (dest
, CONST0_RTX (mode
));
15754 /* Expand a block move operation, and return 1 if successful. Return 0
15755 if we should let the compiler generate normal code.
15757 operands[0] is the destination
15758 operands[1] is the source
15759 operands[2] is the length
15760 operands[3] is the alignment */
15762 #define MAX_MOVE_REG 4
15765 expand_block_move (rtx operands
[])
15767 rtx orig_dest
= operands
[0];
15768 rtx orig_src
= operands
[1];
15769 rtx bytes_rtx
= operands
[2];
15770 rtx align_rtx
= operands
[3];
15771 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15776 rtx stores
[MAX_MOVE_REG
];
15779 /* If this is not a fixed size move, just call memcpy */
15783 /* This must be a fixed size alignment */
15784 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15785 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15787 /* Anything to move? */
15788 bytes
= INTVAL (bytes_rtx
);
15792 if (bytes
> rs6000_block_move_inline_limit
)
15795 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
15798 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
15799 rtx (*mov
) (rtx
, rtx
);
15801 enum machine_mode mode
= BLKmode
;
15804 /* Altivec first, since it will be faster than a string move
15805 when it applies, and usually not significantly larger. */
15806 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
15810 gen_func
.mov
= gen_movv4si
;
15812 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15816 gen_func
.mov
= gen_movv2si
;
15818 else if (TARGET_STRING
15819 && bytes
> 24 /* move up to 32 bytes at a time */
15825 && ! fixed_regs
[10]
15826 && ! fixed_regs
[11]
15827 && ! fixed_regs
[12])
15829 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15830 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15832 else if (TARGET_STRING
15833 && bytes
> 16 /* move up to 24 bytes at a time */
15839 && ! fixed_regs
[10])
15841 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15842 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15844 else if (TARGET_STRING
15845 && bytes
> 8 /* move up to 16 bytes at a time */
15849 && ! fixed_regs
[8])
15851 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15852 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15854 else if (bytes
>= 8 && TARGET_POWERPC64
15855 && (align
>= 64 || !STRICT_ALIGNMENT
))
15859 gen_func
.mov
= gen_movdi
;
15860 if (offset
== 0 && align
< 64)
15864 /* If the address form is reg+offset with offset not a
15865 multiple of four, reload into reg indirect form here
15866 rather than waiting for reload. This way we get one
15867 reload, not one per load and/or store. */
15868 addr
= XEXP (orig_dest
, 0);
15869 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15870 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15871 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15873 addr
= copy_addr_to_reg (addr
);
15874 orig_dest
= replace_equiv_address (orig_dest
, addr
);
15876 addr
= XEXP (orig_src
, 0);
15877 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15878 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15879 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15881 addr
= copy_addr_to_reg (addr
);
15882 orig_src
= replace_equiv_address (orig_src
, addr
);
15886 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15887 { /* move up to 8 bytes at a time */
15888 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15889 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15891 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15892 { /* move 4 bytes */
15895 gen_func
.mov
= gen_movsi
;
15897 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15898 { /* move 2 bytes */
15901 gen_func
.mov
= gen_movhi
;
15903 else if (TARGET_STRING
&& bytes
> 1)
15904 { /* move up to 4 bytes at a time */
15905 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15906 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15908 else /* move 1 byte at a time */
15912 gen_func
.mov
= gen_movqi
;
15915 src
= adjust_address (orig_src
, mode
, offset
);
15916 dest
= adjust_address (orig_dest
, mode
, offset
);
15918 if (mode
!= BLKmode
)
15920 rtx tmp_reg
= gen_reg_rtx (mode
);
15922 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15923 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15926 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15929 for (i
= 0; i
< num_reg
; i
++)
15930 emit_insn (stores
[i
]);
15934 if (mode
== BLKmode
)
15936 /* Move the address into scratch registers. The movmemsi
15937 patterns require zero offset. */
15938 if (!REG_P (XEXP (src
, 0)))
15940 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15941 src
= replace_equiv_address (src
, src_reg
);
15943 set_mem_size (src
, move_bytes
);
15945 if (!REG_P (XEXP (dest
, 0)))
15947 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15948 dest
= replace_equiv_address (dest
, dest_reg
);
15950 set_mem_size (dest
, move_bytes
);
15952 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15953 GEN_INT (move_bytes
& 31),
15962 /* Return a string to perform a load_multiple operation.
15963 operands[0] is the vector.
15964 operands[1] is the source address.
15965 operands[2] is the first destination register. */
15968 rs6000_output_load_multiple (rtx operands
[3])
15970 /* We have to handle the case where the pseudo used to contain the address
15971 is assigned to one of the output registers. */
15973 int words
= XVECLEN (operands
[0], 0);
15976 if (XVECLEN (operands
[0], 0) == 1)
15977 return "lwz %2,0(%1)";
15979 for (i
= 0; i
< words
; i
++)
15980 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15981 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15985 xop
[0] = GEN_INT (4 * (words
-1));
15986 xop
[1] = operands
[1];
15987 xop
[2] = operands
[2];
15988 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15993 xop
[0] = GEN_INT (4 * (words
-1));
15994 xop
[1] = operands
[1];
15995 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15996 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
16001 for (j
= 0; j
< words
; j
++)
16004 xop
[0] = GEN_INT (j
* 4);
16005 xop
[1] = operands
[1];
16006 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
16007 output_asm_insn ("lwz %2,%0(%1)", xop
);
16009 xop
[0] = GEN_INT (i
* 4);
16010 xop
[1] = operands
[1];
16011 output_asm_insn ("lwz %1,%0(%1)", xop
);
16016 return "lswi %2,%1,%N0";
16020 /* A validation routine: say whether CODE, a condition code, and MODE
16021 match. The other alternatives either don't make sense or should
16022 never be generated. */
16025 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
16027 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
16028 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
16029 && GET_MODE_CLASS (mode
) == MODE_CC
);
16031 /* These don't make sense. */
16032 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
16033 || mode
!= CCUNSmode
);
16035 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
16036 || mode
== CCUNSmode
);
16038 gcc_assert (mode
== CCFPmode
16039 || (code
!= ORDERED
&& code
!= UNORDERED
16040 && code
!= UNEQ
&& code
!= LTGT
16041 && code
!= UNGT
&& code
!= UNLT
16042 && code
!= UNGE
&& code
!= UNLE
));
16044 /* These should never be generated except for
16045 flag_finite_math_only. */
16046 gcc_assert (mode
!= CCFPmode
16047 || flag_finite_math_only
16048 || (code
!= LE
&& code
!= GE
16049 && code
!= UNEQ
&& code
!= LTGT
16050 && code
!= UNGT
&& code
!= UNLT
));
16052 /* These are invalid; the information is not there. */
16053 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
16057 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
16058 mask required to convert the result of a rotate insn into a shift
16059 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
16062 includes_lshift_p (rtx shiftop
, rtx andop
)
16064 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
16066 shift_mask
<<= INTVAL (shiftop
);
16068 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
16071 /* Similar, but for right shift. */
16074 includes_rshift_p (rtx shiftop
, rtx andop
)
16076 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
16078 shift_mask
>>= INTVAL (shiftop
);
16080 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
16083 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
16084 to perform a left shift. It must have exactly SHIFTOP least
16085 significant 0's, then one or more 1's, then zero or more 0's. */
16088 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
16090 if (GET_CODE (andop
) == CONST_INT
)
16092 HOST_WIDE_INT c
, lsb
, shift_mask
;
16094 c
= INTVAL (andop
);
16095 if (c
== 0 || c
== ~0)
16099 shift_mask
<<= INTVAL (shiftop
);
16101 /* Find the least significant one bit. */
16104 /* It must coincide with the LSB of the shift mask. */
16105 if (-lsb
!= shift_mask
)
16108 /* Invert to look for the next transition (if any). */
16111 /* Remove the low group of ones (originally low group of zeros). */
16114 /* Again find the lsb, and check we have all 1's above. */
16122 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
16123 to perform a left shift. It must have SHIFTOP or more least
16124 significant 0's, with the remainder of the word 1's. */
16127 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
16129 if (GET_CODE (andop
) == CONST_INT
)
16131 HOST_WIDE_INT c
, lsb
, shift_mask
;
16134 shift_mask
<<= INTVAL (shiftop
);
16135 c
= INTVAL (andop
);
16137 /* Find the least significant one bit. */
16140 /* It must be covered by the shift mask.
16141 This test also rejects c == 0. */
16142 if ((lsb
& shift_mask
) == 0)
16145 /* Check we have all 1's above the transition, and reject all 1's. */
16146 return c
== -lsb
&& lsb
!= 1;
16152 /* Return 1 if operands will generate a valid arguments to rlwimi
16153 instruction for insert with right shift in 64-bit mode. The mask may
16154 not start on the first bit or stop on the last bit because wrap-around
16155 effects of instruction do not correspond to semantics of RTL insn. */
16158 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
16160 if (INTVAL (startop
) > 32
16161 && INTVAL (startop
) < 64
16162 && INTVAL (sizeop
) > 1
16163 && INTVAL (sizeop
) + INTVAL (startop
) < 64
16164 && INTVAL (shiftop
) > 0
16165 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
16166 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
16172 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
16173 for lfq and stfq insns iff the registers are hard registers. */
16176 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
16178 /* We might have been passed a SUBREG. */
16179 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
16182 /* We might have been passed non floating point registers. */
16183 if (!FP_REGNO_P (REGNO (reg1
))
16184 || !FP_REGNO_P (REGNO (reg2
)))
16187 return (REGNO (reg1
) == REGNO (reg2
) - 1);
16190 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
16191 addr1 and addr2 must be in consecutive memory locations
16192 (addr2 == addr1 + 8). */
16195 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
16198 unsigned int reg1
, reg2
;
16199 int offset1
, offset2
;
16201 /* The mems cannot be volatile. */
16202 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
16205 addr1
= XEXP (mem1
, 0);
16206 addr2
= XEXP (mem2
, 0);
16208 /* Extract an offset (if used) from the first addr. */
16209 if (GET_CODE (addr1
) == PLUS
)
16211 /* If not a REG, return zero. */
16212 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
16216 reg1
= REGNO (XEXP (addr1
, 0));
16217 /* The offset must be constant! */
16218 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
16220 offset1
= INTVAL (XEXP (addr1
, 1));
16223 else if (GET_CODE (addr1
) != REG
)
16227 reg1
= REGNO (addr1
);
16228 /* This was a simple (mem (reg)) expression. Offset is 0. */
16232 /* And now for the second addr. */
16233 if (GET_CODE (addr2
) == PLUS
)
16235 /* If not a REG, return zero. */
16236 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
16240 reg2
= REGNO (XEXP (addr2
, 0));
16241 /* The offset must be constant. */
16242 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
16244 offset2
= INTVAL (XEXP (addr2
, 1));
16247 else if (GET_CODE (addr2
) != REG
)
16251 reg2
= REGNO (addr2
);
16252 /* This was a simple (mem (reg)) expression. Offset is 0. */
16256 /* Both of these must have the same base register. */
16260 /* The offset for the second addr must be 8 more than the first addr. */
16261 if (offset2
!= offset1
+ 8)
16264 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
16271 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
16273 static bool eliminated
= false;
16276 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
16277 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
16280 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
16281 gcc_assert (mem
!= NULL_RTX
);
16285 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
16286 cfun
->machine
->sdmode_stack_slot
= mem
;
16292 if (TARGET_DEBUG_ADDR
)
16294 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
16295 GET_MODE_NAME (mode
));
16297 fprintf (stderr
, "\tNULL_RTX\n");
16305 /* Return the mode to be used for memory when a secondary memory
16306 location is needed. For SDmode values we need to use DDmode, in
16307 all other cases we can use the same mode. */
16309 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
16311 if (lra_in_progress
&& mode
== SDmode
)
16317 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
16319 /* Don't walk into types. */
16320 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
16322 *walk_subtrees
= 0;
16326 switch (TREE_CODE (*tp
))
16335 case VIEW_CONVERT_EXPR
:
16336 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
16346 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
16347 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
16348 only work on the traditional altivec registers, note if an altivec register
16351 static enum rs6000_reg_type
16352 register_to_reg_type (rtx reg
, bool *is_altivec
)
16354 HOST_WIDE_INT regno
;
16355 enum reg_class rclass
;
16357 if (GET_CODE (reg
) == SUBREG
)
16358 reg
= SUBREG_REG (reg
);
16361 return NO_REG_TYPE
;
16363 regno
= REGNO (reg
);
16364 if (regno
>= FIRST_PSEUDO_REGISTER
)
16366 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
16367 return PSEUDO_REG_TYPE
;
16369 regno
= true_regnum (reg
);
16370 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16371 return PSEUDO_REG_TYPE
;
16374 gcc_assert (regno
>= 0);
16376 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
16377 *is_altivec
= true;
16379 rclass
= rs6000_regno_regclass
[regno
];
16380 return reg_class_to_reg_type
[(int)rclass
];
16383 /* Helper function for rs6000_secondary_reload to return true if a move to a
16384 different register classe is really a simple move. */
16387 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
16388 enum rs6000_reg_type from_type
,
16389 enum machine_mode mode
)
16393 /* Add support for various direct moves available. In this function, we only
16394 look at cases where we don't need any extra registers, and one or more
16395 simple move insns are issued. At present, 32-bit integers are not allowed
16396 in FPR/VSX registers. Single precision binary floating is not a simple
16397 move because we need to convert to the single precision memory layout.
16398 The 4-byte SDmode can be moved. */
16399 size
= GET_MODE_SIZE (mode
);
16400 if (TARGET_DIRECT_MOVE
16401 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
16402 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16403 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16406 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
16407 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
16408 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16411 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
16412 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
16413 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16419 /* Power8 helper function for rs6000_secondary_reload, handle all of the
16420 special direct moves that involve allocating an extra register, return the
16421 insn code of the helper function if there is such a function or
16422 CODE_FOR_nothing if not. */
16425 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
16426 enum rs6000_reg_type from_type
,
16427 enum machine_mode mode
,
16428 secondary_reload_info
*sri
,
16432 enum insn_code icode
= CODE_FOR_nothing
;
16434 int size
= GET_MODE_SIZE (mode
);
16436 if (TARGET_POWERPC64
)
16440 /* Handle moving 128-bit values from GPRs to VSX point registers on
16441 power8 when running in 64-bit mode using XXPERMDI to glue the two
16442 64-bit values back together. */
16443 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16445 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16446 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16449 /* Handle moving 128-bit values from VSX point registers to GPRs on
16450 power8 when running in 64-bit mode using XXPERMDI to get access to the
16451 bottom 64-bit value. */
16452 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16454 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16455 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16459 else if (mode
== SFmode
)
16461 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16463 cost
= 3; /* xscvdpspn, mfvsrd, and. */
16464 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16467 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16469 cost
= 2; /* mtvsrz, xscvspdpn. */
16470 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16475 if (TARGET_POWERPC64
&& size
== 16)
16477 /* Handle moving 128-bit values from GPRs to VSX point registers on
16478 power8 when running in 64-bit mode using XXPERMDI to glue the two
16479 64-bit values back together. */
16480 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16482 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16483 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16486 /* Handle moving 128-bit values from VSX point registers to GPRs on
16487 power8 when running in 64-bit mode using XXPERMDI to get access to the
16488 bottom 64-bit value. */
16489 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16491 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16492 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16496 else if (!TARGET_POWERPC64
&& size
== 8)
16498 /* Handle moving 64-bit values from GPRs to floating point registers on
16499 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
16500 values back together. Altivec register classes must be handled
16501 specially since a different instruction is used, and the secondary
16502 reload support requires a single instruction class in the scratch
16503 register constraint. However, right now TFmode is not allowed in
16504 Altivec registers, so the pattern will never match. */
16505 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
16507 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
16508 icode
= reg_addr
[mode
].reload_fpr_gpr
;
16512 if (icode
!= CODE_FOR_nothing
)
16517 sri
->icode
= icode
;
16518 sri
->extra_cost
= cost
;
16525 /* Return whether a move between two register classes can be done either
16526 directly (simple move) or via a pattern that uses a single extra temporary
16527 (using power8's direct move in this case. */
16530 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
16531 enum rs6000_reg_type from_type
,
16532 enum machine_mode mode
,
16533 secondary_reload_info
*sri
,
16536 /* Fall back to load/store reloads if either type is not a register. */
16537 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
16540 /* If we haven't allocated registers yet, assume the move can be done for the
16541 standard register types. */
16542 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
16543 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
16544 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
16547 /* Moves to the same set of registers is a simple move for non-specialized
16549 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
16552 /* Check whether a simple move can be done directly. */
16553 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
16557 sri
->icode
= CODE_FOR_nothing
;
16558 sri
->extra_cost
= 0;
16563 /* Now check if we can do it in a few steps. */
16564 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
16568 /* Inform reload about cases where moving X with a mode MODE to a register in
16569 RCLASS requires an extra scratch or immediate register. Return the class
16570 needed for the immediate register.
16572 For VSX and Altivec, we may need a register to convert sp+offset into
16575 For misaligned 64-bit gpr loads and stores we need a register to
16576 convert an offset address to indirect. */
16579 rs6000_secondary_reload (bool in_p
,
16581 reg_class_t rclass_i
,
16582 enum machine_mode mode
,
16583 secondary_reload_info
*sri
)
16585 enum reg_class rclass
= (enum reg_class
) rclass_i
;
16586 reg_class_t ret
= ALL_REGS
;
16587 enum insn_code icode
;
16588 bool default_p
= false;
16590 sri
->icode
= CODE_FOR_nothing
;
16592 ? reg_addr
[mode
].reload_load
16593 : reg_addr
[mode
].reload_store
);
16595 if (REG_P (x
) || register_operand (x
, mode
))
16597 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
16598 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
16599 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
16603 enum rs6000_reg_type exchange
= to_type
;
16604 to_type
= from_type
;
16605 from_type
= exchange
;
16608 /* Can we do a direct move of some sort? */
16609 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
16612 icode
= (enum insn_code
)sri
->icode
;
16618 /* Handle vector moves with reload helper functions. */
16619 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
16622 sri
->icode
= CODE_FOR_nothing
;
16623 sri
->extra_cost
= 0;
16625 if (GET_CODE (x
) == MEM
)
16627 rtx addr
= XEXP (x
, 0);
16629 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
16630 an extra register in that case, but it would need an extra
16631 register if the addressing is reg+reg or (reg+reg)&(-16). Special
16632 case load/store quad. */
16633 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
16635 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
16636 && GET_MODE_SIZE (mode
) == 16
16637 && quad_memory_operand (x
, mode
))
16639 sri
->icode
= icode
;
16640 sri
->extra_cost
= 2;
16643 else if (!legitimate_indirect_address_p (addr
, false)
16644 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16647 sri
->icode
= icode
;
16648 /* account for splitting the loads, and converting the
16649 address from reg+reg to reg. */
16650 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
16651 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
16654 /* Allow scalar loads to/from the traditional floating point
16655 registers, even if VSX memory is set. */
16656 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16657 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16658 && (legitimate_indirect_address_p (addr
, false)
16659 || legitimate_indirect_address_p (addr
, false)
16660 || rs6000_legitimate_offset_address_p (mode
, addr
,
16664 /* Loads to and stores from vector registers can only do reg+reg
16665 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
16666 scalar modes loading up the traditional floating point registers
16667 to use offset addresses. */
16668 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
16669 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16671 if (!VECTOR_MEM_ALTIVEC_P (mode
)
16672 && GET_CODE (addr
) == AND
16673 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16674 && INTVAL (XEXP (addr
, 1)) == -16
16675 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16676 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
16678 sri
->icode
= icode
;
16679 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
16682 else if (!legitimate_indirect_address_p (addr
, false)
16683 && (rclass
== NO_REGS
16684 || !legitimate_indexed_address_p (addr
, false)))
16686 sri
->icode
= icode
;
16687 sri
->extra_cost
= 1;
16690 icode
= CODE_FOR_nothing
;
16692 /* Any other loads, including to pseudo registers which haven't been
16693 assigned to a register yet, default to require a scratch
16697 sri
->icode
= icode
;
16698 sri
->extra_cost
= 2;
16701 else if (REG_P (x
))
16703 int regno
= true_regnum (x
);
16705 icode
= CODE_FOR_nothing
;
16706 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16710 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
16711 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
16712 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
16714 /* If memory is needed, use default_secondary_reload to create the
16716 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
16725 else if (TARGET_POWERPC64
16726 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16728 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
16730 rtx addr
= XEXP (x
, 0);
16731 rtx off
= address_offset (addr
);
16733 if (off
!= NULL_RTX
)
16735 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16736 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16738 /* We need a secondary reload when our legitimate_address_p
16739 says the address is good (as otherwise the entire address
16740 will be reloaded), and the offset is not a multiple of
16741 four or we have an address wrap. Address wrap will only
16742 occur for LO_SUMs since legitimate_offset_address_p
16743 rejects addresses for 16-byte mems that will wrap. */
16744 if (GET_CODE (addr
) == LO_SUM
16745 ? (1 /* legitimate_address_p allows any offset for lo_sum */
16746 && ((offset
& 3) != 0
16747 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
16748 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
16749 && (offset
& 3) != 0))
16752 sri
->icode
= CODE_FOR_reload_di_load
;
16754 sri
->icode
= CODE_FOR_reload_di_store
;
16755 sri
->extra_cost
= 2;
16764 else if (!TARGET_POWERPC64
16765 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16767 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
16769 rtx addr
= XEXP (x
, 0);
16770 rtx off
= address_offset (addr
);
16772 if (off
!= NULL_RTX
)
16774 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16775 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16777 /* We need a secondary reload when our legitimate_address_p
16778 says the address is good (as otherwise the entire address
16779 will be reloaded), and we have a wrap.
16781 legitimate_lo_sum_address_p allows LO_SUM addresses to
16782 have any offset so test for wrap in the low 16 bits.
16784 legitimate_offset_address_p checks for the range
16785 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
16786 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
16787 [0x7ff4,0x7fff] respectively, so test for the
16788 intersection of these ranges, [0x7ffc,0x7fff] and
16789 [0x7ff4,0x7ff7] respectively.
16791 Note that the address we see here may have been
16792 manipulated by legitimize_reload_address. */
16793 if (GET_CODE (addr
) == LO_SUM
16794 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
16795 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
16798 sri
->icode
= CODE_FOR_reload_si_load
;
16800 sri
->icode
= CODE_FOR_reload_si_store
;
16801 sri
->extra_cost
= 2;
16814 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
16816 gcc_assert (ret
!= ALL_REGS
);
16818 if (TARGET_DEBUG_ADDR
)
16821 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
16823 reg_class_names
[ret
],
16824 in_p
? "true" : "false",
16825 reg_class_names
[rclass
],
16826 GET_MODE_NAME (mode
));
16829 fprintf (stderr
, ", default secondary reload");
16831 if (sri
->icode
!= CODE_FOR_nothing
)
16832 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
16833 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
16835 fprintf (stderr
, "\n");
16843 /* Better tracing for rs6000_secondary_reload_inner. */
16846 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16851 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16853 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16854 store_p
? "store" : "load");
16857 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16859 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16861 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16862 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16866 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16869 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16870 gcc_unreachable ();
16873 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16874 to SP+reg addressing. */
16877 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16879 int regno
= true_regnum (reg
);
16880 enum machine_mode mode
= GET_MODE (reg
);
16881 enum reg_class rclass
;
16883 rtx and_op2
= NULL_RTX
;
16886 rtx scratch_or_premodify
= scratch
;
16890 if (TARGET_DEBUG_ADDR
)
16891 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16893 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16894 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16896 if (GET_CODE (mem
) != MEM
)
16897 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16899 rclass
= REGNO_REG_CLASS (regno
);
16900 addr
= find_replacement (&XEXP (mem
, 0));
16904 /* GPRs can handle reg + small constant, all other addresses need to use
16905 the scratch register. */
16908 if (GET_CODE (addr
) == AND
)
16910 and_op2
= XEXP (addr
, 1);
16911 addr
= find_replacement (&XEXP (addr
, 0));
16914 if (GET_CODE (addr
) == PRE_MODIFY
)
16916 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16917 if (!REG_P (scratch_or_premodify
))
16918 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16920 addr
= find_replacement (&XEXP (addr
, 1));
16921 if (GET_CODE (addr
) != PLUS
)
16922 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16925 if (GET_CODE (addr
) == PLUS
16926 && (and_op2
!= NULL_RTX
16927 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16930 /* find_replacement already recurses into both operands of
16931 PLUS so we don't need to call it here. */
16932 addr_op1
= XEXP (addr
, 0);
16933 addr_op2
= XEXP (addr
, 1);
16934 if (!legitimate_indirect_address_p (addr_op1
, false))
16935 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16937 if (!REG_P (addr_op2
)
16938 && (GET_CODE (addr_op2
) != CONST_INT
16939 || !satisfies_constraint_I (addr_op2
)))
16941 if (TARGET_DEBUG_ADDR
)
16944 "\nMove plus addr to register %s, mode = %s: ",
16945 rs6000_reg_names
[REGNO (scratch
)],
16946 GET_MODE_NAME (mode
));
16947 debug_rtx (addr_op2
);
16949 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16950 addr_op2
= scratch
;
16953 emit_insn (gen_rtx_SET (VOIDmode
,
16954 scratch_or_premodify
,
16955 gen_rtx_PLUS (Pmode
,
16959 addr
= scratch_or_premodify
;
16960 scratch_or_premodify
= scratch
;
16962 else if (!legitimate_indirect_address_p (addr
, false)
16963 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16966 if (TARGET_DEBUG_ADDR
)
16968 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16969 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16970 GET_MODE_NAME (mode
));
16973 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16974 addr
= scratch_or_premodify
;
16975 scratch_or_premodify
= scratch
;
16979 /* Float registers can do offset+reg addressing for scalar types. */
16981 if (legitimate_indirect_address_p (addr
, false) /* reg */
16982 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16983 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16984 && and_op2
== NULL_RTX
16985 && scratch_or_premodify
== scratch
16986 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16989 /* If this isn't a legacy floating point load/store, fall through to the
16992 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16993 addresses into a scratch register. */
16997 /* With float regs, we need to handle the AND ourselves, since we can't
16998 use the Altivec instruction with an implicit AND -16. Allow scalar
16999 loads to float registers to use reg+offset even if VSX. */
17000 if (GET_CODE (addr
) == AND
17001 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
17002 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
17003 || INTVAL (XEXP (addr
, 1)) != -16
17004 || !VECTOR_MEM_ALTIVEC_P (mode
)))
17006 and_op2
= XEXP (addr
, 1);
17007 addr
= find_replacement (&XEXP (addr
, 0));
17010 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
17011 as the address later. */
17012 if (GET_CODE (addr
) == PRE_MODIFY
17013 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
17014 && (rclass
!= FLOAT_REGS
17015 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
17016 || and_op2
!= NULL_RTX
17017 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
17019 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
17020 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
17021 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17023 addr
= find_replacement (&XEXP (addr
, 1));
17024 if (GET_CODE (addr
) != PLUS
)
17025 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17028 if (legitimate_indirect_address_p (addr
, false) /* reg */
17029 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
17030 || (GET_CODE (addr
) == AND
/* Altivec memory */
17031 && rclass
== ALTIVEC_REGS
17032 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
17033 && INTVAL (XEXP (addr
, 1)) == -16
17034 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
17035 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
17038 else if (GET_CODE (addr
) == PLUS
)
17040 addr_op1
= XEXP (addr
, 0);
17041 addr_op2
= XEXP (addr
, 1);
17042 if (!REG_P (addr_op1
))
17043 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17045 if (TARGET_DEBUG_ADDR
)
17047 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
17048 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
17049 debug_rtx (addr_op2
);
17051 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
17052 emit_insn (gen_rtx_SET (VOIDmode
,
17053 scratch_or_premodify
,
17054 gen_rtx_PLUS (Pmode
,
17057 addr
= scratch_or_premodify
;
17058 scratch_or_premodify
= scratch
;
17061 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
17062 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
17065 if (TARGET_DEBUG_ADDR
)
17067 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
17068 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
17069 GET_MODE_NAME (mode
));
17073 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
17074 addr
= scratch_or_premodify
;
17075 scratch_or_premodify
= scratch
;
17079 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17084 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17087 /* If the original address involved a pre-modify that we couldn't use the VSX
17088 memory instruction with update, and we haven't taken care of already,
17089 store the address in the pre-modify register and use that as the
17091 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
17093 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
17094 addr
= scratch_or_premodify
;
17097 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
17098 memory instruction, recreate the AND now, including the clobber which is
17099 generated by the general ANDSI3/ANDDI3 patterns for the
17100 andi. instruction. */
17101 if (and_op2
!= NULL_RTX
)
17103 if (! legitimate_indirect_address_p (addr
, false))
17105 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
17109 if (TARGET_DEBUG_ADDR
)
17111 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
17112 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
17113 debug_rtx (and_op2
);
17116 and_rtx
= gen_rtx_SET (VOIDmode
,
17118 gen_rtx_AND (Pmode
,
17122 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
17123 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
17124 gen_rtvec (2, and_rtx
, cc_clobber
)));
17128 /* Adjust the address if it changed. */
17129 if (addr
!= XEXP (mem
, 0))
17131 mem
= replace_equiv_address_nv (mem
, addr
);
17132 if (TARGET_DEBUG_ADDR
)
17133 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
17136 /* Now create the move. */
17138 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
17140 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
17145 /* Convert reloads involving 64-bit gprs and misaligned offset
17146 addressing, or multiple 32-bit gprs and offsets that are too large,
17147 to use indirect addressing. */
17150 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
17152 int regno
= true_regnum (reg
);
17153 enum reg_class rclass
;
17155 rtx scratch_or_premodify
= scratch
;
17157 if (TARGET_DEBUG_ADDR
)
17159 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
17160 store_p
? "store" : "load");
17161 fprintf (stderr
, "reg:\n");
17163 fprintf (stderr
, "mem:\n");
17165 fprintf (stderr
, "scratch:\n");
17166 debug_rtx (scratch
);
17169 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
17170 gcc_assert (GET_CODE (mem
) == MEM
);
17171 rclass
= REGNO_REG_CLASS (regno
);
17172 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
17173 addr
= XEXP (mem
, 0);
17175 if (GET_CODE (addr
) == PRE_MODIFY
)
17177 scratch_or_premodify
= XEXP (addr
, 0);
17178 gcc_assert (REG_P (scratch_or_premodify
));
17179 addr
= XEXP (addr
, 1);
17181 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
17183 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
17185 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
17187 /* Now create the move. */
17189 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
17191 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
17196 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
17197 this function has any SDmode references. If we are on a power7 or later, we
17198 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
17199 can load/store the value. */
17202 rs6000_alloc_sdmode_stack_slot (void)
17206 gimple_stmt_iterator gsi
;
17208 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
17209 /* We use a different approach for dealing with the secondary
17214 if (TARGET_NO_SDMODE_STACK
)
17217 FOR_EACH_BB_FN (bb
, cfun
)
17218 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
17220 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
17223 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17224 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17230 /* Check for any SDmode parameters of the function. */
17231 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
17233 if (TREE_TYPE (t
) == error_mark_node
)
17236 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
17237 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
17239 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17240 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17248 rs6000_instantiate_decls (void)
17250 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
17251 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
17254 /* Given an rtx X being reloaded into a reg required to be
17255 in class CLASS, return the class of reg to actually use.
17256 In general this is just CLASS; but on some machines
17257 in some cases it is preferable to use a more restrictive class.
17259 On the RS/6000, we have to return NO_REGS when we want to reload a
17260 floating-point CONST_DOUBLE to force it to be copied to memory.
17262 We also don't want to reload integer values into floating-point
17263 registers if we can at all help it. In fact, this can
17264 cause reload to die, if it tries to generate a reload of CTR
17265 into a FP register and discovers it doesn't have the memory location
17268 ??? Would it be a good idea to have reload do the converse, that is
17269 try to reload floating modes into FP registers if possible?
17272 static enum reg_class
17273 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
17275 enum machine_mode mode
= GET_MODE (x
);
17277 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
17280 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
17281 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
17282 && easy_vector_constant (x
, mode
))
17283 return ALTIVEC_REGS
;
17285 if ((CONSTANT_P (x
) || GET_CODE (x
) == PLUS
))
17287 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
17288 return GENERAL_REGS
;
17289 if (reg_class_subset_p (BASE_REGS
, rclass
))
17294 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
17295 return GENERAL_REGS
;
17297 /* For VSX, prefer the traditional registers for 64-bit values because we can
17298 use the non-VSX loads. Prefer the Altivec registers if Altivec is
17299 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
17300 prefer Altivec loads.. */
17301 if (rclass
== VSX_REGS
)
17303 if (MEM_P (x
) && reg_addr
[mode
].scalar_in_vmx_p
)
17305 rtx addr
= XEXP (x
, 0);
17306 if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true)
17307 || legitimate_lo_sum_address_p (mode
, addr
, false))
17310 else if (GET_MODE_SIZE (mode
) <= 8 && !reg_addr
[mode
].scalar_in_vmx_p
)
17313 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
17314 || mode
== V1TImode
)
17315 return ALTIVEC_REGS
;
17323 /* Debug version of rs6000_preferred_reload_class. */
17324 static enum reg_class
17325 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
17327 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
17330 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
17332 reg_class_names
[ret
], reg_class_names
[rclass
],
17333 GET_MODE_NAME (GET_MODE (x
)));
17339 /* If we are copying between FP or AltiVec registers and anything else, we need
17340 a memory location. The exception is when we are targeting ppc64 and the
17341 move to/from fpr to gpr instructions are available. Also, under VSX, you
17342 can copy vector registers from the FP register set to the Altivec register
17343 set and vice versa. */
17346 rs6000_secondary_memory_needed (enum reg_class from_class
,
17347 enum reg_class to_class
,
17348 enum machine_mode mode
)
17350 enum rs6000_reg_type from_type
, to_type
;
17351 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
17352 || (to_class
== ALTIVEC_REGS
));
17354 /* If a simple/direct move is available, we don't need secondary memory */
17355 from_type
= reg_class_to_reg_type
[(int)from_class
];
17356 to_type
= reg_class_to_reg_type
[(int)to_class
];
17358 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
17359 (secondary_reload_info
*)0, altivec_p
))
17362 /* If we have a floating point or vector register class, we need to use
17363 memory to transfer the data. */
17364 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
17370 /* Debug version of rs6000_secondary_memory_needed. */
17372 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
17373 enum reg_class to_class
,
17374 enum machine_mode mode
)
17376 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
17379 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
17380 "to_class = %s, mode = %s\n",
17381 ret
? "true" : "false",
17382 reg_class_names
[from_class
],
17383 reg_class_names
[to_class
],
17384 GET_MODE_NAME (mode
));
17389 /* Return the register class of a scratch register needed to copy IN into
17390 or out of a register in RCLASS in MODE. If it can be done directly,
17391 NO_REGS is returned. */
17393 static enum reg_class
17394 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
17399 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
17401 && MACHOPIC_INDIRECT
17405 /* We cannot copy a symbolic operand directly into anything
17406 other than BASE_REGS for TARGET_ELF. So indicate that a
17407 register from BASE_REGS is needed as an intermediate
17410 On Darwin, pic addresses require a load from memory, which
17411 needs a base register. */
17412 if (rclass
!= BASE_REGS
17413 && (GET_CODE (in
) == SYMBOL_REF
17414 || GET_CODE (in
) == HIGH
17415 || GET_CODE (in
) == LABEL_REF
17416 || GET_CODE (in
) == CONST
))
17420 if (GET_CODE (in
) == REG
)
17422 regno
= REGNO (in
);
17423 if (regno
>= FIRST_PSEUDO_REGISTER
)
17425 regno
= true_regnum (in
);
17426 if (regno
>= FIRST_PSEUDO_REGISTER
)
17430 else if (GET_CODE (in
) == SUBREG
)
17432 regno
= true_regnum (in
);
17433 if (regno
>= FIRST_PSEUDO_REGISTER
)
17439 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
17441 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
17442 || (regno
>= 0 && INT_REGNO_P (regno
)))
17445 /* Constants, memory, and FP registers can go into FP registers. */
17446 if ((regno
== -1 || FP_REGNO_P (regno
))
17447 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
17448 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
17450 /* Memory, and FP/altivec registers can go into fp/altivec registers under
17451 VSX. However, for scalar variables, use the traditional floating point
17452 registers so that we can use offset+register addressing. */
17454 && (regno
== -1 || VSX_REGNO_P (regno
))
17455 && VSX_REG_CLASS_P (rclass
))
17457 if (GET_MODE_SIZE (mode
) < 16)
17463 /* Memory, and AltiVec registers can go into AltiVec registers. */
17464 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
17465 && rclass
== ALTIVEC_REGS
)
17468 /* We can copy among the CR registers. */
17469 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
17470 && regno
>= 0 && CR_REGNO_P (regno
))
17473 /* Otherwise, we need GENERAL_REGS. */
17474 return GENERAL_REGS
;
17477 /* Debug version of rs6000_secondary_reload_class. */
17478 static enum reg_class
17479 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
17480 enum machine_mode mode
, rtx in
)
17482 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
17484 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
17485 "mode = %s, input rtx:\n",
17486 reg_class_names
[ret
], reg_class_names
[rclass
],
17487 GET_MODE_NAME (mode
));
17493 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
17496 rs6000_cannot_change_mode_class (enum machine_mode from
,
17497 enum machine_mode to
,
17498 enum reg_class rclass
)
17500 unsigned from_size
= GET_MODE_SIZE (from
);
17501 unsigned to_size
= GET_MODE_SIZE (to
);
17503 if (from_size
!= to_size
)
17505 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
17507 if (reg_classes_intersect_p (xclass
, rclass
))
17509 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
17510 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
17512 /* Don't allow 64-bit types to overlap with 128-bit types that take a
17513 single register under VSX because the scalar part of the register
17514 is in the upper 64-bits, and not the lower 64-bits. Types like
17515 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
17516 IEEE floating point can't overlap, and neither can small
17519 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
17522 /* TDmode in floating-mode registers must always go into a register
17523 pair with the most significant word in the even-numbered register
17524 to match ISA requirements. In little-endian mode, this does not
17525 match subreg numbering, so we cannot allow subregs. */
17526 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
17529 if (from_size
< 8 || to_size
< 8)
17532 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
17535 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
17544 if (TARGET_E500_DOUBLE
17545 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
17546 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
17547 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
17548 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
17549 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
17552 /* Since the VSX register set includes traditional floating point registers
17553 and altivec registers, just check for the size being different instead of
17554 trying to check whether the modes are vector modes. Otherwise it won't
17555 allow say DF and DI to change classes. For types like TFmode and TDmode
17556 that take 2 64-bit registers, rather than a single 128-bit register, don't
17557 allow subregs of those types to other 128 bit types. */
17558 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
17560 unsigned num_regs
= (from_size
+ 15) / 16;
17561 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
17562 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
17565 return (from_size
!= 8 && from_size
!= 16);
17568 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
17569 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
17572 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
17573 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
17579 /* Debug version of rs6000_cannot_change_mode_class. */
17581 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
17582 enum machine_mode to
,
17583 enum reg_class rclass
)
17585 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
17588 "rs6000_cannot_change_mode_class, return %s, from = %s, "
17589 "to = %s, rclass = %s\n",
17590 ret
? "true" : "false",
17591 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
17592 reg_class_names
[rclass
]);
17597 /* Return a string to do a move operation of 128 bits of data. */
17600 rs6000_output_move_128bit (rtx operands
[])
17602 rtx dest
= operands
[0];
17603 rtx src
= operands
[1];
17604 enum machine_mode mode
= GET_MODE (dest
);
17607 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
17608 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
17612 dest_regno
= REGNO (dest
);
17613 dest_gpr_p
= INT_REGNO_P (dest_regno
);
17614 dest_fp_p
= FP_REGNO_P (dest_regno
);
17615 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
17616 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
17621 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
17626 src_regno
= REGNO (src
);
17627 src_gpr_p
= INT_REGNO_P (src_regno
);
17628 src_fp_p
= FP_REGNO_P (src_regno
);
17629 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
17630 src_vsx_p
= src_fp_p
| src_vmx_p
;
17635 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
17638 /* Register moves. */
17639 if (dest_regno
>= 0 && src_regno
>= 0)
17646 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
17650 else if (TARGET_VSX
&& dest_vsx_p
)
17653 return "xxlor %x0,%x1,%x1";
17655 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
17659 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
17660 return "vor %0,%1,%1";
17662 else if (dest_fp_p
&& src_fp_p
)
17667 else if (dest_regno
>= 0 && MEM_P (src
))
17671 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17677 else if (TARGET_ALTIVEC
&& dest_vmx_p
17678 && altivec_indexed_or_indirect_operand (src
, mode
))
17679 return "lvx %0,%y1";
17681 else if (TARGET_VSX
&& dest_vsx_p
)
17683 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17684 return "lxvw4x %x0,%y1";
17686 return "lxvd2x %x0,%y1";
17689 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17690 return "lvx %0,%y1";
17692 else if (dest_fp_p
)
17697 else if (src_regno
>= 0 && MEM_P (dest
))
17701 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17702 return "stq %1,%0";
17707 else if (TARGET_ALTIVEC
&& src_vmx_p
17708 && altivec_indexed_or_indirect_operand (src
, mode
))
17709 return "stvx %1,%y0";
17711 else if (TARGET_VSX
&& src_vsx_p
)
17713 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17714 return "stxvw4x %x1,%y0";
17716 return "stxvd2x %x1,%y0";
17719 else if (TARGET_ALTIVEC
&& src_vmx_p
)
17720 return "stvx %1,%y0";
17727 else if (dest_regno
>= 0
17728 && (GET_CODE (src
) == CONST_INT
17729 || GET_CODE (src
) == CONST_WIDE_INT
17730 || GET_CODE (src
) == CONST_DOUBLE
17731 || GET_CODE (src
) == CONST_VECTOR
))
17736 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
17737 return "xxlxor %x0,%x0,%x0";
17739 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17740 return output_vec_const_move (operands
);
17743 if (TARGET_DEBUG_ADDR
)
17745 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
17746 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
17749 gcc_unreachable ();
17752 /* Validate a 128-bit move. */
17754 rs6000_move_128bit_ok_p (rtx operands
[])
17756 enum machine_mode mode
= GET_MODE (operands
[0]);
17757 return (gpc_reg_operand (operands
[0], mode
)
17758 || gpc_reg_operand (operands
[1], mode
));
17761 /* Return true if a 128-bit move needs to be split. */
17763 rs6000_split_128bit_ok_p (rtx operands
[])
17765 if (!reload_completed
)
17768 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
17771 if (quad_load_store_p (operands
[0], operands
[1]))
17778 /* Given a comparison operation, return the bit number in CCR to test. We
17779 know this is a valid comparison.
17781 SCC_P is 1 if this is for an scc. That means that %D will have been
17782 used instead of %C, so the bits will be in different places.
17784 Return -1 if OP isn't a valid comparison for some reason. */
17787 ccr_bit (rtx op
, int scc_p
)
17789 enum rtx_code code
= GET_CODE (op
);
17790 enum machine_mode cc_mode
;
17795 if (!COMPARISON_P (op
))
17798 reg
= XEXP (op
, 0);
17800 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
17802 cc_mode
= GET_MODE (reg
);
17803 cc_regnum
= REGNO (reg
);
17804 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
17806 validate_condition_mode (code
, cc_mode
);
17808 /* When generating a sCOND operation, only positive conditions are
17811 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
17812 || code
== GTU
|| code
== LTU
);
17817 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
17819 return base_bit
+ 2;
17820 case GT
: case GTU
: case UNLE
:
17821 return base_bit
+ 1;
17822 case LT
: case LTU
: case UNGE
:
17824 case ORDERED
: case UNORDERED
:
17825 return base_bit
+ 3;
17828 /* If scc, we will have done a cror to put the bit in the
17829 unordered position. So test that bit. For integer, this is ! LT
17830 unless this is an scc insn. */
17831 return scc_p
? base_bit
+ 3 : base_bit
;
17834 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
17837 gcc_unreachable ();
17841 /* Return the GOT register. */
17844 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
17846 /* The second flow pass currently (June 1999) can't update
17847 regs_ever_live without disturbing other parts of the compiler, so
17848 update it here to make the prolog/epilogue code happy. */
17849 if (!can_create_pseudo_p ()
17850 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
17851 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
17853 crtl
->uses_pic_offset_table
= 1;
17855 return pic_offset_table_rtx
;
17858 static rs6000_stack_t stack_info
;
17860 /* Function to init struct machine_function.
17861 This will be called, via a pointer variable,
17862 from push_function_context. */
17864 static struct machine_function
*
17865 rs6000_init_machine_status (void)
17867 stack_info
.reload_completed
= 0;
17868 return ggc_cleared_alloc
<machine_function
> ();
17871 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
17874 extract_MB (rtx op
)
17877 unsigned long val
= INTVAL (op
);
17879 /* If the high bit is zero, the value is the first 1 bit we find
17881 if ((val
& 0x80000000) == 0)
17883 gcc_assert (val
& 0xffffffff);
17886 while (((val
<<= 1) & 0x80000000) == 0)
17891 /* If the high bit is set and the low bit is not, or the mask is all
17892 1's, the value is zero. */
17893 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17896 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17899 while (((val
>>= 1) & 1) != 0)
17906 extract_ME (rtx op
)
17909 unsigned long val
= INTVAL (op
);
17911 /* If the low bit is zero, the value is the first 1 bit we find from
17913 if ((val
& 1) == 0)
17915 gcc_assert (val
& 0xffffffff);
17918 while (((val
>>= 1) & 1) == 0)
17924 /* If the low bit is set and the high bit is not, or the mask is all
17925 1's, the value is 31. */
17926 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17929 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17932 while (((val
<<= 1) & 0x80000000) != 0)
17938 /* Write out a function code label. */
17941 rs6000_output_function_entry (FILE *file
, const char *fname
)
17943 if (fname
[0] != '.')
17945 switch (DEFAULT_ABI
)
17948 gcc_unreachable ();
17954 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17964 RS6000_OUTPUT_BASENAME (file
, fname
);
17967 /* Print an operand. Recognize special options, documented below. */
17970 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17971 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17973 #define SMALL_DATA_RELOC "sda21"
17974 #define SMALL_DATA_REG 0
17978 print_operand (FILE *file
, rtx x
, int code
)
17981 unsigned HOST_WIDE_INT uval
;
17985 /* %a is output_address. */
17988 /* If constant, low-order 16 bits of constant, unsigned.
17989 Otherwise, write normally. */
17991 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17993 print_operand (file
, x
, 0);
17997 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17998 for 64-bit mask direction. */
17999 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
18002 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
18006 /* Like 'J' but get to the GT bit only. */
18007 gcc_assert (REG_P (x
));
18009 /* Bit 1 is GT bit. */
18010 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
18012 /* Add one for shift count in rlinm for scc. */
18013 fprintf (file
, "%d", i
+ 1);
18017 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
18020 output_operand_lossage ("invalid %%e value");
18025 if ((uval
& 0xffff) == 0 && uval
!= 0)
18030 /* X is a CR register. Print the number of the EQ bit of the CR */
18031 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18032 output_operand_lossage ("invalid %%E value");
18034 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
18038 /* X is a CR register. Print the shift count needed to move it
18039 to the high-order four bits. */
18040 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18041 output_operand_lossage ("invalid %%f value");
18043 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
18047 /* Similar, but print the count for the rotate in the opposite
18049 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18050 output_operand_lossage ("invalid %%F value");
18052 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
18056 /* X is a constant integer. If it is negative, print "m",
18057 otherwise print "z". This is to make an aze or ame insn. */
18058 if (GET_CODE (x
) != CONST_INT
)
18059 output_operand_lossage ("invalid %%G value");
18060 else if (INTVAL (x
) >= 0)
18067 /* If constant, output low-order five bits. Otherwise, write
18070 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
18072 print_operand (file
, x
, 0);
18076 /* If constant, output low-order six bits. Otherwise, write
18079 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
18081 print_operand (file
, x
, 0);
18085 /* Print `i' if this is a constant, else nothing. */
18091 /* Write the bit number in CCR for jump. */
18092 i
= ccr_bit (x
, 0);
18094 output_operand_lossage ("invalid %%j code");
18096 fprintf (file
, "%d", i
);
18100 /* Similar, but add one for shift count in rlinm for scc and pass
18101 scc flag to `ccr_bit'. */
18102 i
= ccr_bit (x
, 1);
18104 output_operand_lossage ("invalid %%J code");
18106 /* If we want bit 31, write a shift count of zero, not 32. */
18107 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
18111 /* X must be a constant. Write the 1's complement of the
18114 output_operand_lossage ("invalid %%k value");
18116 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
18120 /* X must be a symbolic constant on ELF. Write an
18121 expression suitable for an 'addi' that adds in the low 16
18122 bits of the MEM. */
18123 if (GET_CODE (x
) == CONST
)
18125 if (GET_CODE (XEXP (x
, 0)) != PLUS
18126 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
18127 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
18128 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
18129 output_operand_lossage ("invalid %%K value");
18131 print_operand_address (file
, x
);
18132 fputs ("@l", file
);
18135 /* %l is output_asm_label. */
18138 /* Write second word of DImode or DFmode reference. Works on register
18139 or non-indexed memory only. */
18141 fputs (reg_names
[REGNO (x
) + 1], file
);
18142 else if (MEM_P (x
))
18144 /* Handle possible auto-increment. Since it is pre-increment and
18145 we have already done it, we can just use an offset of word. */
18146 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18147 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18148 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
18150 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18151 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
18154 output_address (XEXP (adjust_address_nv (x
, SImode
,
18158 if (small_data_operand (x
, GET_MODE (x
)))
18159 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18160 reg_names
[SMALL_DATA_REG
]);
18165 /* MB value for a mask operand. */
18166 if (! mask_operand (x
, SImode
))
18167 output_operand_lossage ("invalid %%m value");
18169 fprintf (file
, "%d", extract_MB (x
));
18173 /* ME value for a mask operand. */
18174 if (! mask_operand (x
, SImode
))
18175 output_operand_lossage ("invalid %%M value");
18177 fprintf (file
, "%d", extract_ME (x
));
18180 /* %n outputs the negative of its operand. */
18183 /* Write the number of elements in the vector times 4. */
18184 if (GET_CODE (x
) != PARALLEL
)
18185 output_operand_lossage ("invalid %%N value");
18187 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
18191 /* Similar, but subtract 1 first. */
18192 if (GET_CODE (x
) != PARALLEL
)
18193 output_operand_lossage ("invalid %%O value");
18195 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
18199 /* X is a CONST_INT that is a power of two. Output the logarithm. */
18202 || (i
= exact_log2 (INTVAL (x
))) < 0)
18203 output_operand_lossage ("invalid %%p value");
18205 fprintf (file
, "%d", i
);
18209 /* The operand must be an indirect memory reference. The result
18210 is the register name. */
18211 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
18212 || REGNO (XEXP (x
, 0)) >= 32)
18213 output_operand_lossage ("invalid %%P value");
18215 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
18219 /* This outputs the logical code corresponding to a boolean
18220 expression. The expression may have one or both operands
18221 negated (if one, only the first one). For condition register
18222 logical operations, it will also treat the negated
18223 CR codes as NOTs, but not handle NOTs of them. */
18225 const char *const *t
= 0;
18227 enum rtx_code code
= GET_CODE (x
);
18228 static const char * const tbl
[3][3] = {
18229 { "and", "andc", "nor" },
18230 { "or", "orc", "nand" },
18231 { "xor", "eqv", "xor" } };
18235 else if (code
== IOR
)
18237 else if (code
== XOR
)
18240 output_operand_lossage ("invalid %%q value");
18242 if (GET_CODE (XEXP (x
, 0)) != NOT
)
18246 if (GET_CODE (XEXP (x
, 1)) == NOT
)
18257 if (! TARGET_MFCRF
)
18263 /* X is a CR register. Print the mask for `mtcrf'. */
18264 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18265 output_operand_lossage ("invalid %%R value");
18267 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
18271 /* Low 5 bits of 32 - value */
18273 output_operand_lossage ("invalid %%s value");
18275 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
18279 /* PowerPC64 mask position. All 0's is excluded.
18280 CONST_INT 32-bit mask is considered sign-extended so any
18281 transition must occur within the CONST_INT, not on the boundary. */
18282 if (! mask64_operand (x
, DImode
))
18283 output_operand_lossage ("invalid %%S value");
18287 if (uval
& 1) /* Clear Left */
18289 #if HOST_BITS_PER_WIDE_INT > 64
18290 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18294 else /* Clear Right */
18297 #if HOST_BITS_PER_WIDE_INT > 64
18298 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18304 gcc_assert (i
>= 0);
18305 fprintf (file
, "%d", i
);
18309 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
18310 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
18312 /* Bit 3 is OV bit. */
18313 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
18315 /* If we want bit 31, write a shift count of zero, not 32. */
18316 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
18320 /* Print the symbolic name of a branch target register. */
18321 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
18322 && REGNO (x
) != CTR_REGNO
))
18323 output_operand_lossage ("invalid %%T value");
18324 else if (REGNO (x
) == LR_REGNO
)
18325 fputs ("lr", file
);
18327 fputs ("ctr", file
);
18331 /* High-order or low-order 16 bits of constant, whichever is non-zero,
18332 for use in unsigned operand. */
18335 output_operand_lossage ("invalid %%u value");
18340 if ((uval
& 0xffff) == 0)
18343 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
18347 /* High-order 16 bits of constant for use in signed operand. */
18349 output_operand_lossage ("invalid %%v value");
18351 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18352 (INTVAL (x
) >> 16) & 0xffff);
18356 /* Print `u' if this has an auto-increment or auto-decrement. */
18358 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
18359 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
18360 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
18365 /* Print the trap code for this operand. */
18366 switch (GET_CODE (x
))
18369 fputs ("eq", file
); /* 4 */
18372 fputs ("ne", file
); /* 24 */
18375 fputs ("lt", file
); /* 16 */
18378 fputs ("le", file
); /* 20 */
18381 fputs ("gt", file
); /* 8 */
18384 fputs ("ge", file
); /* 12 */
18387 fputs ("llt", file
); /* 2 */
18390 fputs ("lle", file
); /* 6 */
18393 fputs ("lgt", file
); /* 1 */
18396 fputs ("lge", file
); /* 5 */
18399 gcc_unreachable ();
18404 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
18407 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
18408 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
18410 print_operand (file
, x
, 0);
18414 /* MB value for a PowerPC64 rldic operand. */
18415 i
= clz_hwi (INTVAL (x
));
18417 fprintf (file
, "%d", i
);
18421 /* X is a FPR or Altivec register used in a VSX context. */
18422 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
18423 output_operand_lossage ("invalid %%x value");
18426 int reg
= REGNO (x
);
18427 int vsx_reg
= (FP_REGNO_P (reg
)
18429 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
18431 #ifdef TARGET_REGNAMES
18432 if (TARGET_REGNAMES
)
18433 fprintf (file
, "%%vs%d", vsx_reg
);
18436 fprintf (file
, "%d", vsx_reg
);
18442 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
18443 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
18444 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
18449 /* Like 'L', for third word of TImode/PTImode */
18451 fputs (reg_names
[REGNO (x
) + 2], file
);
18452 else if (MEM_P (x
))
18454 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18455 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18456 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18457 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18458 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18460 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
18461 if (small_data_operand (x
, GET_MODE (x
)))
18462 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18463 reg_names
[SMALL_DATA_REG
]);
18468 /* X is a SYMBOL_REF. Write out the name preceded by a
18469 period and without any trailing data in brackets. Used for function
18470 names. If we are configured for System V (or the embedded ABI) on
18471 the PowerPC, do not emit the period, since those systems do not use
18472 TOCs and the like. */
18473 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
18475 /* For macho, check to see if we need a stub. */
18478 const char *name
= XSTR (x
, 0);
18480 if (darwin_emit_branch_islands
18481 && MACHOPIC_INDIRECT
18482 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
18483 name
= machopic_indirection_name (x
, /*stub_p=*/true);
18485 assemble_name (file
, name
);
18487 else if (!DOT_SYMBOLS
)
18488 assemble_name (file
, XSTR (x
, 0));
18490 rs6000_output_function_entry (file
, XSTR (x
, 0));
18494 /* Like 'L', for last word of TImode/PTImode. */
18496 fputs (reg_names
[REGNO (x
) + 3], file
);
18497 else if (MEM_P (x
))
18499 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18500 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18501 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18502 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18503 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18505 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
18506 if (small_data_operand (x
, GET_MODE (x
)))
18507 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18508 reg_names
[SMALL_DATA_REG
]);
18512 /* Print AltiVec or SPE memory operand. */
18517 gcc_assert (MEM_P (x
));
18521 /* Ugly hack because %y is overloaded. */
18522 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
18523 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
18524 || GET_MODE (x
) == TFmode
18525 || GET_MODE (x
) == TImode
18526 || GET_MODE (x
) == PTImode
))
18528 /* Handle [reg]. */
18531 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
18534 /* Handle [reg+UIMM]. */
18535 else if (GET_CODE (tmp
) == PLUS
&&
18536 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
18540 gcc_assert (REG_P (XEXP (tmp
, 0)));
18542 x
= INTVAL (XEXP (tmp
, 1));
18543 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
18547 /* Fall through. Must be [reg+reg]. */
18549 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
18550 && GET_CODE (tmp
) == AND
18551 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
18552 && INTVAL (XEXP (tmp
, 1)) == -16)
18553 tmp
= XEXP (tmp
, 0);
18554 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
18555 && GET_CODE (tmp
) == PRE_MODIFY
)
18556 tmp
= XEXP (tmp
, 1);
18558 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
18561 if (GET_CODE (tmp
) != PLUS
18562 || !REG_P (XEXP (tmp
, 0))
18563 || !REG_P (XEXP (tmp
, 1)))
18565 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
18569 if (REGNO (XEXP (tmp
, 0)) == 0)
18570 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
18571 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
18573 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
18574 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
18581 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
18582 else if (MEM_P (x
))
18584 /* We need to handle PRE_INC and PRE_DEC here, since we need to
18585 know the width from the mode. */
18586 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
18587 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
18588 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18589 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18590 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
18591 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18592 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18593 output_address (XEXP (XEXP (x
, 0), 1));
18595 output_address (XEXP (x
, 0));
18599 if (toc_relative_expr_p (x
, false))
18600 /* This hack along with a corresponding hack in
18601 rs6000_output_addr_const_extra arranges to output addends
18602 where the assembler expects to find them. eg.
18603 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
18604 without this hack would be output as "x@toc+4". We
18606 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18608 output_addr_const (file
, x
);
18613 if (const char *name
= get_some_local_dynamic_name ())
18614 assemble_name (file
, name
);
18616 output_operand_lossage ("'%%&' used without any "
18617 "local dynamic TLS references");
18621 output_operand_lossage ("invalid %%xn code");
18625 /* Print the address of an operand. */
18628 print_operand_address (FILE *file
, rtx x
)
18631 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
18632 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
18633 || GET_CODE (x
) == LABEL_REF
)
18635 output_addr_const (file
, x
);
18636 if (small_data_operand (x
, GET_MODE (x
)))
18637 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18638 reg_names
[SMALL_DATA_REG
]);
18640 gcc_assert (!TARGET_TOC
);
18642 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18643 && REG_P (XEXP (x
, 1)))
18645 if (REGNO (XEXP (x
, 0)) == 0)
18646 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
18647 reg_names
[ REGNO (XEXP (x
, 0)) ]);
18649 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
18650 reg_names
[ REGNO (XEXP (x
, 1)) ]);
18652 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18653 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
18654 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
18655 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
18657 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18658 && CONSTANT_P (XEXP (x
, 1)))
18660 fprintf (file
, "lo16(");
18661 output_addr_const (file
, XEXP (x
, 1));
18662 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18666 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18667 && CONSTANT_P (XEXP (x
, 1)))
18669 output_addr_const (file
, XEXP (x
, 1));
18670 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18673 else if (toc_relative_expr_p (x
, false))
18675 /* This hack along with a corresponding hack in
18676 rs6000_output_addr_const_extra arranges to output addends
18677 where the assembler expects to find them. eg.
18679 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
18680 without this hack would be output as "x@toc+8@l(9)". We
18681 want "x+8@toc@l(9)". */
18682 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18683 if (GET_CODE (x
) == LO_SUM
)
18684 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
18686 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
18689 gcc_unreachable ();
18692 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
18695 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
18697 if (GET_CODE (x
) == UNSPEC
)
18698 switch (XINT (x
, 1))
18700 case UNSPEC_TOCREL
:
18701 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
18702 && REG_P (XVECEXP (x
, 0, 1))
18703 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
18704 output_addr_const (file
, XVECEXP (x
, 0, 0));
18705 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
18707 if (INTVAL (tocrel_offset
) >= 0)
18708 fprintf (file
, "+");
18709 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
18711 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
18714 assemble_name (file
, toc_label_name
);
18716 else if (TARGET_ELF
)
18717 fputs ("@toc", file
);
18721 case UNSPEC_MACHOPIC_OFFSET
:
18722 output_addr_const (file
, XVECEXP (x
, 0, 0));
18724 machopic_output_function_base_name (file
);
18731 /* Target hook for assembling integer objects. The PowerPC version has
18732 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
18733 is defined. It also needs to handle DI-mode objects on 64-bit
18737 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
18739 #ifdef RELOCATABLE_NEEDS_FIXUP
18740 /* Special handling for SI values. */
18741 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
18743 static int recurse
= 0;
18745 /* For -mrelocatable, we mark all addresses that need to be fixed up in
18746 the .fixup section. Since the TOC section is already relocated, we
18747 don't need to mark it here. We used to skip the text section, but it
18748 should never be valid for relocated addresses to be placed in the text
18750 if (TARGET_RELOCATABLE
18751 && in_section
!= toc_section
18753 && !CONST_SCALAR_INT_P (x
)
18759 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
18761 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
18762 fprintf (asm_out_file
, "\t.long\t(");
18763 output_addr_const (asm_out_file
, x
);
18764 fprintf (asm_out_file
, ")@fixup\n");
18765 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
18766 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
18767 fprintf (asm_out_file
, "\t.long\t");
18768 assemble_name (asm_out_file
, buf
);
18769 fprintf (asm_out_file
, "\n\t.previous\n");
18773 /* Remove initial .'s to turn a -mcall-aixdesc function
18774 address into the address of the descriptor, not the function
18776 else if (GET_CODE (x
) == SYMBOL_REF
18777 && XSTR (x
, 0)[0] == '.'
18778 && DEFAULT_ABI
== ABI_AIX
)
18780 const char *name
= XSTR (x
, 0);
18781 while (*name
== '.')
18784 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
18788 #endif /* RELOCATABLE_NEEDS_FIXUP */
18789 return default_assemble_integer (x
, size
, aligned_p
);
18792 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
18793 /* Emit an assembler directive to set symbol visibility for DECL to
18794 VISIBILITY_TYPE. */
18797 rs6000_assemble_visibility (tree decl
, int vis
)
18802 /* Functions need to have their entry point symbol visibility set as
18803 well as their descriptor symbol visibility. */
18804 if (DEFAULT_ABI
== ABI_AIX
18806 && TREE_CODE (decl
) == FUNCTION_DECL
)
18808 static const char * const visibility_types
[] = {
18809 NULL
, "internal", "hidden", "protected"
18812 const char *name
, *type
;
18814 name
= ((* targetm
.strip_name_encoding
)
18815 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
18816 type
= visibility_types
[vis
];
18818 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
18819 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
18822 default_assemble_visibility (decl
, vis
);
18827 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
18829 /* Reversal of FP compares takes care -- an ordered compare
18830 becomes an unordered compare and vice versa. */
18831 if (mode
== CCFPmode
18832 && (!flag_finite_math_only
18833 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
18834 || code
== UNEQ
|| code
== LTGT
))
18835 return reverse_condition_maybe_unordered (code
);
18837 return reverse_condition (code
);
18840 /* Generate a compare for CODE. Return a brand-new rtx that
18841 represents the result of the compare. */
18844 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
18846 enum machine_mode comp_mode
;
18847 rtx compare_result
;
18848 enum rtx_code code
= GET_CODE (cmp
);
18849 rtx op0
= XEXP (cmp
, 0);
18850 rtx op1
= XEXP (cmp
, 1);
18852 if (FLOAT_MODE_P (mode
))
18853 comp_mode
= CCFPmode
;
18854 else if (code
== GTU
|| code
== LTU
18855 || code
== GEU
|| code
== LEU
)
18856 comp_mode
= CCUNSmode
;
18857 else if ((code
== EQ
|| code
== NE
)
18858 && unsigned_reg_p (op0
)
18859 && (unsigned_reg_p (op1
)
18860 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
18861 /* These are unsigned values, perhaps there will be a later
18862 ordering compare that can be shared with this one. */
18863 comp_mode
= CCUNSmode
;
18865 comp_mode
= CCmode
;
18867 /* If we have an unsigned compare, make sure we don't have a signed value as
18869 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18870 && INTVAL (op1
) < 0)
18872 op0
= copy_rtx_if_shared (op0
);
18873 op1
= force_reg (GET_MODE (op0
), op1
);
18874 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18877 /* First, the compare. */
18878 compare_result
= gen_reg_rtx (comp_mode
);
18880 /* E500 FP compare instructions on the GPRs. Yuck! */
18881 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18882 && FLOAT_MODE_P (mode
))
18884 rtx cmp
, or_result
, compare_result2
;
18885 enum machine_mode op_mode
= GET_MODE (op0
);
18888 if (op_mode
== VOIDmode
)
18889 op_mode
= GET_MODE (op1
);
18891 /* First reverse the condition codes that aren't directly supported. */
18899 code
= reverse_condition_maybe_unordered (code
);
18912 gcc_unreachable ();
18915 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18916 This explains the following mess. */
18924 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18925 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18926 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18930 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18931 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18932 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18936 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18937 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18938 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18942 gcc_unreachable ();
18951 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18952 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18953 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18957 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18958 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18959 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18963 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18964 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18965 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18969 gcc_unreachable ();
18978 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18979 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18980 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18984 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18985 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18986 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18990 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18991 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18992 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18996 gcc_unreachable ();
19001 gcc_unreachable ();
19004 /* Synthesize LE and GE from LT/GT || EQ. */
19005 if (code
== LE
|| code
== GE
)
19009 compare_result2
= gen_reg_rtx (CCFPmode
);
19015 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19016 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
19017 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
19021 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19022 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
19023 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
19027 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19028 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
19029 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
19033 gcc_unreachable ();
19038 /* OR them together. */
19039 or_result
= gen_reg_rtx (CCFPmode
);
19040 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
19042 compare_result
= or_result
;
19045 code
= reverse_p
? NE
: EQ
;
19051 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
19052 CLOBBERs to match cmptf_internal2 pattern. */
19053 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
19054 && GET_MODE (op0
) == TFmode
19055 && !TARGET_IEEEQUAD
19056 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
19057 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
19059 gen_rtx_SET (VOIDmode
,
19061 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
19062 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19063 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19064 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19065 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19066 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19067 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19068 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19069 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19070 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
19071 else if (GET_CODE (op1
) == UNSPEC
19072 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
19074 rtx op1b
= XVECEXP (op1
, 0, 0);
19075 comp_mode
= CCEQmode
;
19076 compare_result
= gen_reg_rtx (CCEQmode
);
19078 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
19080 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
19083 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
19084 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
19087 /* Some kinds of FP comparisons need an OR operation;
19088 under flag_finite_math_only we don't bother. */
19089 if (FLOAT_MODE_P (mode
)
19090 && !flag_finite_math_only
19091 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
19092 && (code
== LE
|| code
== GE
19093 || code
== UNEQ
|| code
== LTGT
19094 || code
== UNGT
|| code
== UNLT
))
19096 enum rtx_code or1
, or2
;
19097 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
19098 rtx or_result
= gen_reg_rtx (CCEQmode
);
19102 case LE
: or1
= LT
; or2
= EQ
; break;
19103 case GE
: or1
= GT
; or2
= EQ
; break;
19104 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
19105 case LTGT
: or1
= LT
; or2
= GT
; break;
19106 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
19107 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
19108 default: gcc_unreachable ();
19110 validate_condition_mode (or1
, comp_mode
);
19111 validate_condition_mode (or2
, comp_mode
);
19112 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
19113 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
19114 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
19115 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
19117 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
19119 compare_result
= or_result
;
19123 validate_condition_mode (code
, GET_MODE (compare_result
));
19125 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
19129 /* Emit the RTL for an sISEL pattern. */
19132 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
19134 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
19138 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
19141 enum machine_mode op_mode
;
19142 enum rtx_code cond_code
;
19143 rtx result
= operands
[0];
19145 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
19147 rs6000_emit_sISEL (mode
, operands
);
19151 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
19152 cond_code
= GET_CODE (condition_rtx
);
19154 if (FLOAT_MODE_P (mode
)
19155 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
19159 PUT_MODE (condition_rtx
, SImode
);
19160 t
= XEXP (condition_rtx
, 0);
19162 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
19164 if (cond_code
== NE
)
19165 emit_insn (gen_e500_flip_gt_bit (t
, t
));
19167 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
19171 if (cond_code
== NE
19172 || cond_code
== GE
|| cond_code
== LE
19173 || cond_code
== GEU
|| cond_code
== LEU
19174 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
19176 rtx not_result
= gen_reg_rtx (CCEQmode
);
19177 rtx not_op
, rev_cond_rtx
;
19178 enum machine_mode cc_mode
;
19180 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
19182 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
19183 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
19184 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
19185 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
19186 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
19189 op_mode
= GET_MODE (XEXP (operands
[1], 0));
19190 if (op_mode
== VOIDmode
)
19191 op_mode
= GET_MODE (XEXP (operands
[1], 1));
19193 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
19195 PUT_MODE (condition_rtx
, DImode
);
19196 convert_move (result
, condition_rtx
, 0);
19200 PUT_MODE (condition_rtx
, SImode
);
19201 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
19205 /* Emit a branch of kind CODE to location LOC. */
19208 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
19210 rtx condition_rtx
, loc_ref
;
19212 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
19213 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
19214 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
19215 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
19216 loc_ref
, pc_rtx
)));
19219 /* Return the string to output a conditional branch to LABEL, which is
19220 the operand template of the label, or NULL if the branch is really a
19221 conditional return.
19223 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
19224 condition code register and its mode specifies what kind of
19225 comparison we made.
19227 REVERSED is nonzero if we should reverse the sense of the comparison.
19229 INSN is the insn. */
19232 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
19234 static char string
[64];
19235 enum rtx_code code
= GET_CODE (op
);
19236 rtx cc_reg
= XEXP (op
, 0);
19237 enum machine_mode mode
= GET_MODE (cc_reg
);
19238 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
19239 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
19240 int really_reversed
= reversed
^ need_longbranch
;
19246 validate_condition_mode (code
, mode
);
19248 /* Work out which way this really branches. We could use
19249 reverse_condition_maybe_unordered here always but this
19250 makes the resulting assembler clearer. */
19251 if (really_reversed
)
19253 /* Reversal of FP compares takes care -- an ordered compare
19254 becomes an unordered compare and vice versa. */
19255 if (mode
== CCFPmode
)
19256 code
= reverse_condition_maybe_unordered (code
);
19258 code
= reverse_condition (code
);
19261 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
19263 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
19268 /* Opposite of GT. */
19277 gcc_unreachable ();
19283 /* Not all of these are actually distinct opcodes, but
19284 we distinguish them for clarity of the resulting assembler. */
19285 case NE
: case LTGT
:
19286 ccode
= "ne"; break;
19287 case EQ
: case UNEQ
:
19288 ccode
= "eq"; break;
19290 ccode
= "ge"; break;
19291 case GT
: case GTU
: case UNGT
:
19292 ccode
= "gt"; break;
19294 ccode
= "le"; break;
19295 case LT
: case LTU
: case UNLT
:
19296 ccode
= "lt"; break;
19297 case UNORDERED
: ccode
= "un"; break;
19298 case ORDERED
: ccode
= "nu"; break;
19299 case UNGE
: ccode
= "nl"; break;
19300 case UNLE
: ccode
= "ng"; break;
19302 gcc_unreachable ();
19305 /* Maybe we have a guess as to how likely the branch is. */
19307 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
19308 if (note
!= NULL_RTX
)
19310 /* PROB is the difference from 50%. */
19311 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
19313 /* Only hint for highly probable/improbable branches on newer
19314 cpus as static prediction overrides processor dynamic
19315 prediction. For older cpus we may as well always hint, but
19316 assume not taken for branches that are very close to 50% as a
19317 mispredicted taken branch is more expensive than a
19318 mispredicted not-taken branch. */
19319 if (rs6000_always_hint
19320 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
19321 && br_prob_note_reliable_p (note
)))
19323 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
19324 && ((prob
> 0) ^ need_longbranch
))
19332 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
19334 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
19336 /* We need to escape any '%' characters in the reg_names string.
19337 Assume they'd only be the first character.... */
19338 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
19340 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
19344 /* If the branch distance was too far, we may have to use an
19345 unconditional branch to go the distance. */
19346 if (need_longbranch
)
19347 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
19349 s
+= sprintf (s
, ",%s", label
);
19355 /* Return the string to flip the GT bit on a CR. */
19357 output_e500_flip_gt_bit (rtx dst
, rtx src
)
19359 static char string
[64];
19362 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
19363 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
19366 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
19367 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
19369 sprintf (string
, "crnot %d,%d", a
, b
);
19373 /* Return insn for VSX or Altivec comparisons. */
19376 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
19379 enum machine_mode mode
= GET_MODE (op0
);
19387 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
19397 mask
= gen_reg_rtx (mode
);
19398 emit_insn (gen_rtx_SET (VOIDmode
,
19400 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19407 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
19408 DMODE is expected destination mode. This is a recursive function. */
19411 rs6000_emit_vector_compare (enum rtx_code rcode
,
19413 enum machine_mode dmode
)
19416 bool swap_operands
= false;
19417 bool try_again
= false;
19419 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
19420 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
19422 /* See if the comparison works as is. */
19423 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19431 swap_operands
= true;
19436 swap_operands
= true;
19444 /* Invert condition and try again.
19445 e.g., A != B becomes ~(A==B). */
19447 enum rtx_code rev_code
;
19448 enum insn_code nor_code
;
19451 rev_code
= reverse_condition_maybe_unordered (rcode
);
19452 if (rev_code
== UNKNOWN
)
19455 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
19456 if (nor_code
== CODE_FOR_nothing
)
19459 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
19463 mask
= gen_reg_rtx (dmode
);
19464 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
19472 /* Try GT/GTU/LT/LTU OR EQ */
19475 enum insn_code ior_code
;
19476 enum rtx_code new_code
;
19497 gcc_unreachable ();
19500 ior_code
= optab_handler (ior_optab
, dmode
);
19501 if (ior_code
== CODE_FOR_nothing
)
19504 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
19508 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
19512 mask
= gen_reg_rtx (dmode
);
19513 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
19531 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19536 /* You only get two chances. */
19540 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
19541 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
19542 operands for the relation operation COND. */
19545 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
19546 rtx cond
, rtx cc_op0
, rtx cc_op1
)
19548 enum machine_mode dest_mode
= GET_MODE (dest
);
19549 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
19550 enum rtx_code rcode
= GET_CODE (cond
);
19551 enum machine_mode cc_mode
= CCmode
;
19555 bool invert_move
= false;
19557 if (VECTOR_UNIT_NONE_P (dest_mode
))
19560 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
19561 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
19565 /* Swap operands if we can, and fall back to doing the operation as
19566 specified, and doing a NOR to invert the test. */
19572 /* Invert condition and try again.
19573 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
19574 invert_move
= true;
19575 rcode
= reverse_condition_maybe_unordered (rcode
);
19576 if (rcode
== UNKNOWN
)
19580 /* Mark unsigned tests with CCUNSmode. */
19585 cc_mode
= CCUNSmode
;
19592 /* Get the vector mask for the given relational operations. */
19593 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
19601 op_true
= op_false
;
19605 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
19606 CONST0_RTX (dest_mode
));
19607 emit_insn (gen_rtx_SET (VOIDmode
,
19609 gen_rtx_IF_THEN_ELSE (dest_mode
,
19616 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
19617 operands of the last comparison is nonzero/true, FALSE_COND if it
19618 is zero/false. Return 0 if the hardware has no such operation. */
19621 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19623 enum rtx_code code
= GET_CODE (op
);
19624 rtx op0
= XEXP (op
, 0);
19625 rtx op1
= XEXP (op
, 1);
19626 REAL_VALUE_TYPE c1
;
19627 enum machine_mode compare_mode
= GET_MODE (op0
);
19628 enum machine_mode result_mode
= GET_MODE (dest
);
19630 bool is_against_zero
;
19632 /* These modes should always match. */
19633 if (GET_MODE (op1
) != compare_mode
19634 /* In the isel case however, we can use a compare immediate, so
19635 op1 may be a small constant. */
19636 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
19638 if (GET_MODE (true_cond
) != result_mode
)
19640 if (GET_MODE (false_cond
) != result_mode
)
19643 /* Don't allow using floating point comparisons for integer results for
19645 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
19648 /* First, work out if the hardware can do this at all, or
19649 if it's too slow.... */
19650 if (!FLOAT_MODE_P (compare_mode
))
19653 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
19656 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
19657 && SCALAR_FLOAT_MODE_P (compare_mode
))
19660 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
19662 /* A floating-point subtract might overflow, underflow, or produce
19663 an inexact result, thus changing the floating-point flags, so it
19664 can't be generated if we care about that. It's safe if one side
19665 of the construct is zero, since then no subtract will be
19667 if (SCALAR_FLOAT_MODE_P (compare_mode
)
19668 && flag_trapping_math
&& ! is_against_zero
)
19671 /* Eliminate half of the comparisons by switching operands, this
19672 makes the remaining code simpler. */
19673 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
19674 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
19676 code
= reverse_condition_maybe_unordered (code
);
19678 true_cond
= false_cond
;
19682 /* UNEQ and LTGT take four instructions for a comparison with zero,
19683 it'll probably be faster to use a branch here too. */
19684 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
19687 if (GET_CODE (op1
) == CONST_DOUBLE
)
19688 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
19690 /* We're going to try to implement comparisons by performing
19691 a subtract, then comparing against zero. Unfortunately,
19692 Inf - Inf is NaN which is not zero, and so if we don't
19693 know that the operand is finite and the comparison
19694 would treat EQ different to UNORDERED, we can't do it. */
19695 if (HONOR_INFINITIES (compare_mode
)
19696 && code
!= GT
&& code
!= UNGE
19697 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
19698 /* Constructs of the form (a OP b ? a : b) are safe. */
19699 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
19700 || (! rtx_equal_p (op0
, true_cond
)
19701 && ! rtx_equal_p (op1
, true_cond
))))
19704 /* At this point we know we can use fsel. */
19706 /* Reduce the comparison to a comparison against zero. */
19707 if (! is_against_zero
)
19709 temp
= gen_reg_rtx (compare_mode
);
19710 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19711 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
19713 op1
= CONST0_RTX (compare_mode
);
19716 /* If we don't care about NaNs we can reduce some of the comparisons
19717 down to faster ones. */
19718 if (! HONOR_NANS (compare_mode
))
19724 true_cond
= false_cond
;
19737 /* Now, reduce everything down to a GE. */
19744 temp
= gen_reg_rtx (compare_mode
);
19745 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19750 temp
= gen_reg_rtx (compare_mode
);
19751 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
19756 temp
= gen_reg_rtx (compare_mode
);
19757 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19758 gen_rtx_NEG (compare_mode
,
19759 gen_rtx_ABS (compare_mode
, op0
))));
19764 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
19765 temp
= gen_reg_rtx (result_mode
);
19766 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19767 gen_rtx_IF_THEN_ELSE (result_mode
,
19768 gen_rtx_GE (VOIDmode
,
19770 true_cond
, false_cond
)));
19771 false_cond
= true_cond
;
19774 temp
= gen_reg_rtx (compare_mode
);
19775 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19780 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
19781 temp
= gen_reg_rtx (result_mode
);
19782 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19783 gen_rtx_IF_THEN_ELSE (result_mode
,
19784 gen_rtx_GE (VOIDmode
,
19786 true_cond
, false_cond
)));
19787 true_cond
= false_cond
;
19790 temp
= gen_reg_rtx (compare_mode
);
19791 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19796 gcc_unreachable ();
19799 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
19800 gen_rtx_IF_THEN_ELSE (result_mode
,
19801 gen_rtx_GE (VOIDmode
,
19803 true_cond
, false_cond
)));
19807 /* Same as above, but for ints (isel). */
19810 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19812 rtx condition_rtx
, cr
;
19813 enum machine_mode mode
= GET_MODE (dest
);
19814 enum rtx_code cond_code
;
19815 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
19818 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
19821 /* We still have to do the compare, because isel doesn't do a
19822 compare, it just looks at the CRx bits set by a previous compare
19824 condition_rtx
= rs6000_generate_compare (op
, mode
);
19825 cond_code
= GET_CODE (condition_rtx
);
19826 cr
= XEXP (condition_rtx
, 0);
19827 signedp
= GET_MODE (cr
) == CCmode
;
19829 isel_func
= (mode
== SImode
19830 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
19831 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
19835 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
19836 /* isel handles these directly. */
19840 /* We need to swap the sense of the comparison. */
19843 true_cond
= false_cond
;
19845 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
19850 false_cond
= force_reg (mode
, false_cond
);
19851 if (true_cond
!= const0_rtx
)
19852 true_cond
= force_reg (mode
, true_cond
);
19854 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
19860 output_isel (rtx
*operands
)
19862 enum rtx_code code
;
19864 code
= GET_CODE (operands
[1]);
19866 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19868 gcc_assert (GET_CODE (operands
[2]) == REG
19869 && GET_CODE (operands
[3]) == REG
);
19870 PUT_CODE (operands
[1], reverse_condition (code
));
19871 return "isel %0,%3,%2,%j1";
19874 return "isel %0,%2,%3,%j1";
19878 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19880 enum machine_mode mode
= GET_MODE (op0
);
19884 /* VSX/altivec have direct min/max insns. */
19885 if ((code
== SMAX
|| code
== SMIN
)
19886 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19887 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19889 emit_insn (gen_rtx_SET (VOIDmode
,
19891 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19895 if (code
== SMAX
|| code
== SMIN
)
19900 if (code
== SMAX
|| code
== UMAX
)
19901 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19902 op0
, op1
, mode
, 0);
19904 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19905 op1
, op0
, mode
, 0);
19906 gcc_assert (target
);
19907 if (target
!= dest
)
19908 emit_move_insn (dest
, target
);
19911 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19912 COND is true. Mark the jump as unlikely to be taken. */
19915 emit_unlikely_jump (rtx cond
, rtx label
)
19917 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19920 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19921 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19922 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19925 /* A subroutine of the atomic operation splitters. Emit a load-locked
19926 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19927 the zero_extend operation. */
19930 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19932 rtx (*fn
) (rtx
, rtx
) = NULL
;
19937 fn
= gen_load_lockedqi
;
19940 fn
= gen_load_lockedhi
;
19943 if (GET_MODE (mem
) == QImode
)
19944 fn
= gen_load_lockedqi_si
;
19945 else if (GET_MODE (mem
) == HImode
)
19946 fn
= gen_load_lockedhi_si
;
19948 fn
= gen_load_lockedsi
;
19951 fn
= gen_load_lockeddi
;
19954 fn
= gen_load_lockedti
;
19957 gcc_unreachable ();
19959 emit_insn (fn (reg
, mem
));
19962 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19963 instruction in MODE. */
19966 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19968 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19973 fn
= gen_store_conditionalqi
;
19976 fn
= gen_store_conditionalhi
;
19979 fn
= gen_store_conditionalsi
;
19982 fn
= gen_store_conditionaldi
;
19985 fn
= gen_store_conditionalti
;
19988 gcc_unreachable ();
19991 /* Emit sync before stwcx. to address PPC405 Erratum. */
19992 if (PPC405_ERRATUM77
)
19993 emit_insn (gen_hwsync ());
19995 emit_insn (fn (res
, mem
, val
));
19998 /* Expand barriers before and after a load_locked/store_cond sequence. */
20001 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
20003 rtx addr
= XEXP (mem
, 0);
20004 int strict_p
= (reload_in_progress
|| reload_completed
);
20006 if (!legitimate_indirect_address_p (addr
, strict_p
)
20007 && !legitimate_indexed_address_p (addr
, strict_p
))
20009 addr
= force_reg (Pmode
, addr
);
20010 mem
= replace_equiv_address_nv (mem
, addr
);
20015 case MEMMODEL_RELAXED
:
20016 case MEMMODEL_CONSUME
:
20017 case MEMMODEL_ACQUIRE
:
20019 case MEMMODEL_RELEASE
:
20020 case MEMMODEL_ACQ_REL
:
20021 emit_insn (gen_lwsync ());
20023 case MEMMODEL_SEQ_CST
:
20024 emit_insn (gen_hwsync ());
20027 gcc_unreachable ();
20033 rs6000_post_atomic_barrier (enum memmodel model
)
20037 case MEMMODEL_RELAXED
:
20038 case MEMMODEL_CONSUME
:
20039 case MEMMODEL_RELEASE
:
20041 case MEMMODEL_ACQUIRE
:
20042 case MEMMODEL_ACQ_REL
:
20043 case MEMMODEL_SEQ_CST
:
20044 emit_insn (gen_isync ());
20047 gcc_unreachable ();
20051 /* A subroutine of the various atomic expanders. For sub-word operations,
20052 we must adjust things to operate on SImode. Given the original MEM,
20053 return a new aligned memory. Also build and return the quantities by
20054 which to shift and mask. */
20057 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
20059 rtx addr
, align
, shift
, mask
, mem
;
20060 HOST_WIDE_INT shift_mask
;
20061 enum machine_mode mode
= GET_MODE (orig_mem
);
20063 /* For smaller modes, we have to implement this via SImode. */
20064 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
20066 addr
= XEXP (orig_mem
, 0);
20067 addr
= force_reg (GET_MODE (addr
), addr
);
20069 /* Aligned memory containing subword. Generate a new memory. We
20070 do not want any of the existing MEM_ATTR data, as we're now
20071 accessing memory outside the original object. */
20072 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
20073 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20074 mem
= gen_rtx_MEM (SImode
, align
);
20075 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
20076 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
20077 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
20079 /* Shift amount for subword relative to aligned word. */
20080 shift
= gen_reg_rtx (SImode
);
20081 addr
= gen_lowpart (SImode
, addr
);
20082 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
20083 if (BYTES_BIG_ENDIAN
)
20084 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
20085 shift
, 1, OPTAB_LIB_WIDEN
);
20088 /* Mask for insertion. */
20089 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
20090 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20096 /* A subroutine of the various atomic expanders. For sub-word operands,
20097 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
20100 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
20104 x
= gen_reg_rtx (SImode
);
20105 emit_insn (gen_rtx_SET (VOIDmode
, x
,
20106 gen_rtx_AND (SImode
,
20107 gen_rtx_NOT (SImode
, mask
),
20110 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
20115 /* A subroutine of the various atomic expanders. For sub-word operands,
20116 extract WIDE to NARROW via SHIFT. */
20119 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
20121 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
20122 wide
, 1, OPTAB_LIB_WIDEN
);
20123 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
20126 /* Expand an atomic compare and swap operation. */
20129 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
20131 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
20132 rtx label1
, label2
, x
, mask
, shift
;
20133 enum machine_mode mode
, orig_mode
;
20134 enum memmodel mod_s
, mod_f
;
20137 boolval
= operands
[0];
20138 retval
= operands
[1];
20140 oldval
= operands
[3];
20141 newval
= operands
[4];
20142 is_weak
= (INTVAL (operands
[5]) != 0);
20143 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
20144 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
20145 orig_mode
= mode
= GET_MODE (mem
);
20147 mask
= shift
= NULL_RTX
;
20148 if (mode
== QImode
|| mode
== HImode
)
20150 /* Before power8, we didn't have access to lbarx/lharx, so generate a
20151 lwarx and shift/mask operations. With power8, we need to do the
20152 comparison in SImode, but the store is still done in QI/HImode. */
20153 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
20155 if (!TARGET_SYNC_HI_QI
)
20157 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20159 /* Shift and mask OLDVAL into position with the word. */
20160 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
20161 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20163 /* Shift and mask NEWVAL into position within the word. */
20164 newval
= convert_modes (SImode
, mode
, newval
, 1);
20165 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
20166 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20169 /* Prepare to adjust the return value. */
20170 retval
= gen_reg_rtx (SImode
);
20173 else if (reg_overlap_mentioned_p (retval
, oldval
))
20174 oldval
= copy_to_reg (oldval
);
20176 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
20181 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20182 emit_label (XEXP (label1
, 0));
20184 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20186 emit_load_locked (mode
, retval
, mem
);
20191 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
20192 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20195 cond
= gen_reg_rtx (CCmode
);
20196 /* If we have TImode, synthesize a comparison. */
20197 if (mode
!= TImode
)
20198 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
20201 rtx xor1_result
= gen_reg_rtx (DImode
);
20202 rtx xor2_result
= gen_reg_rtx (DImode
);
20203 rtx or_result
= gen_reg_rtx (DImode
);
20204 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
20205 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
20206 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
20207 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
20209 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
20210 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
20211 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
20212 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
20215 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
20217 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20218 emit_unlikely_jump (x
, label2
);
20222 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
20224 emit_store_conditional (orig_mode
, cond
, mem
, x
);
20228 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20229 emit_unlikely_jump (x
, label1
);
20232 if (mod_f
!= MEMMODEL_RELAXED
)
20233 emit_label (XEXP (label2
, 0));
20235 rs6000_post_atomic_barrier (mod_s
);
20237 if (mod_f
== MEMMODEL_RELAXED
)
20238 emit_label (XEXP (label2
, 0));
20241 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
20242 else if (mode
!= GET_MODE (operands
[1]))
20243 convert_move (operands
[1], retval
, 1);
20245 /* In all cases, CR0 contains EQ on success, and NE on failure. */
20246 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
20247 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
20250 /* Expand an atomic exchange operation. */
20253 rs6000_expand_atomic_exchange (rtx operands
[])
20255 rtx retval
, mem
, val
, cond
;
20256 enum machine_mode mode
;
20257 enum memmodel model
;
20258 rtx label
, x
, mask
, shift
;
20260 retval
= operands
[0];
20263 model
= (enum memmodel
) INTVAL (operands
[3]);
20264 mode
= GET_MODE (mem
);
20266 mask
= shift
= NULL_RTX
;
20267 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
20269 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20271 /* Shift and mask VAL into position with the word. */
20272 val
= convert_modes (SImode
, mode
, val
, 1);
20273 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20274 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20276 /* Prepare to adjust the return value. */
20277 retval
= gen_reg_rtx (SImode
);
20281 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20283 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20284 emit_label (XEXP (label
, 0));
20286 emit_load_locked (mode
, retval
, mem
);
20290 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
20292 cond
= gen_reg_rtx (CCmode
);
20293 emit_store_conditional (mode
, cond
, mem
, x
);
20295 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20296 emit_unlikely_jump (x
, label
);
20298 rs6000_post_atomic_barrier (model
);
20301 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
20304 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
20305 to perform. MEM is the memory on which to operate. VAL is the second
20306 operand of the binary operator. BEFORE and AFTER are optional locations to
20307 return the value of MEM either before of after the operation. MODEL_RTX
20308 is a CONST_INT containing the memory model to use. */
20311 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
20312 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
20314 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
20315 enum machine_mode mode
= GET_MODE (mem
);
20316 enum machine_mode store_mode
= mode
;
20317 rtx label
, x
, cond
, mask
, shift
;
20318 rtx before
= orig_before
, after
= orig_after
;
20320 mask
= shift
= NULL_RTX
;
20321 /* On power8, we want to use SImode for the operation. On previous systems,
20322 use the operation in a subword and shift/mask to get the proper byte or
20324 if (mode
== QImode
|| mode
== HImode
)
20326 if (TARGET_SYNC_HI_QI
)
20328 val
= convert_modes (SImode
, mode
, val
, 1);
20330 /* Prepare to adjust the return value. */
20331 before
= gen_reg_rtx (SImode
);
20333 after
= gen_reg_rtx (SImode
);
20338 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20340 /* Shift and mask VAL into position with the word. */
20341 val
= convert_modes (SImode
, mode
, val
, 1);
20342 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20343 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20349 /* We've already zero-extended VAL. That is sufficient to
20350 make certain that it does not affect other bits. */
20355 /* If we make certain that all of the other bits in VAL are
20356 set, that will be sufficient to not affect other bits. */
20357 x
= gen_rtx_NOT (SImode
, mask
);
20358 x
= gen_rtx_IOR (SImode
, x
, val
);
20359 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
20366 /* These will all affect bits outside the field and need
20367 adjustment via MASK within the loop. */
20371 gcc_unreachable ();
20374 /* Prepare to adjust the return value. */
20375 before
= gen_reg_rtx (SImode
);
20377 after
= gen_reg_rtx (SImode
);
20378 store_mode
= mode
= SImode
;
20382 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20384 label
= gen_label_rtx ();
20385 emit_label (label
);
20386 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
20388 if (before
== NULL_RTX
)
20389 before
= gen_reg_rtx (mode
);
20391 emit_load_locked (mode
, before
, mem
);
20395 x
= expand_simple_binop (mode
, AND
, before
, val
,
20396 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20397 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
20401 after
= expand_simple_binop (mode
, code
, before
, val
,
20402 after
, 1, OPTAB_LIB_WIDEN
);
20408 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
20409 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20410 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
20412 else if (store_mode
!= mode
)
20413 x
= convert_modes (store_mode
, mode
, x
, 1);
20415 cond
= gen_reg_rtx (CCmode
);
20416 emit_store_conditional (store_mode
, cond
, mem
, x
);
20418 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20419 emit_unlikely_jump (x
, label
);
20421 rs6000_post_atomic_barrier (model
);
20425 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
20426 then do the calcuations in a SImode register. */
20428 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
20430 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
20432 else if (store_mode
!= mode
)
20434 /* QImode/HImode on machines with lbarx/lharx where we do the native
20435 operation and then do the calcuations in a SImode register. */
20437 convert_move (orig_before
, before
, 1);
20439 convert_move (orig_after
, after
, 1);
20441 else if (orig_after
&& after
!= orig_after
)
20442 emit_move_insn (orig_after
, after
);
20445 /* Emit instructions to move SRC to DST. Called by splitters for
20446 multi-register moves. It will emit at most one instruction for
20447 each register that is accessed; that is, it won't emit li/lis pairs
20448 (or equivalent for 64-bit code). One of SRC or DST must be a hard
20452 rs6000_split_multireg_move (rtx dst
, rtx src
)
20454 /* The register number of the first register being moved. */
20456 /* The mode that is to be moved. */
20457 enum machine_mode mode
;
20458 /* The mode that the move is being done in, and its size. */
20459 enum machine_mode reg_mode
;
20461 /* The number of registers that will be moved. */
20464 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
20465 mode
= GET_MODE (dst
);
20466 nregs
= hard_regno_nregs
[reg
][mode
];
20467 if (FP_REGNO_P (reg
))
20468 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
20469 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
20470 else if (ALTIVEC_REGNO_P (reg
))
20471 reg_mode
= V16QImode
;
20472 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
20475 reg_mode
= word_mode
;
20476 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
20478 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
20480 /* TDmode residing in FP registers is special, since the ISA requires that
20481 the lower-numbered word of a register pair is always the most significant
20482 word, even in little-endian mode. This does not match the usual subreg
20483 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
20484 the appropriate constituent registers "by hand" in little-endian mode.
20486 Note we do not need to check for destructive overlap here since TDmode
20487 can only reside in even/odd register pairs. */
20488 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
20493 for (i
= 0; i
< nregs
; i
++)
20495 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
20496 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
20498 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
20499 i
* reg_mode_size
);
20501 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
20502 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
20504 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
20505 i
* reg_mode_size
);
20507 emit_insn (gen_rtx_SET (VOIDmode
, p_dst
, p_src
));
20513 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
20515 /* Move register range backwards, if we might have destructive
20518 for (i
= nregs
- 1; i
>= 0; i
--)
20519 emit_insn (gen_rtx_SET (VOIDmode
,
20520 simplify_gen_subreg (reg_mode
, dst
, mode
,
20521 i
* reg_mode_size
),
20522 simplify_gen_subreg (reg_mode
, src
, mode
,
20523 i
* reg_mode_size
)));
20529 bool used_update
= false;
20530 rtx restore_basereg
= NULL_RTX
;
20532 if (MEM_P (src
) && INT_REGNO_P (reg
))
20536 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
20537 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
20540 breg
= XEXP (XEXP (src
, 0), 0);
20541 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
20542 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
20543 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
20544 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20545 src
= replace_equiv_address (src
, breg
);
20547 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
20549 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
20551 rtx basereg
= XEXP (XEXP (src
, 0), 0);
20554 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
20555 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
20556 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
20557 used_update
= true;
20560 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20561 XEXP (XEXP (src
, 0), 1)));
20562 src
= replace_equiv_address (src
, basereg
);
20566 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
20567 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
20568 src
= replace_equiv_address (src
, basereg
);
20572 breg
= XEXP (src
, 0);
20573 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
20574 breg
= XEXP (breg
, 0);
20576 /* If the base register we are using to address memory is
20577 also a destination reg, then change that register last. */
20579 && REGNO (breg
) >= REGNO (dst
)
20580 && REGNO (breg
) < REGNO (dst
) + nregs
)
20581 j
= REGNO (breg
) - REGNO (dst
);
20583 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
20587 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20588 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
20591 breg
= XEXP (XEXP (dst
, 0), 0);
20592 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20593 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
20594 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
20596 /* We have to update the breg before doing the store.
20597 Use store with update, if available. */
20601 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20602 emit_insn (TARGET_32BIT
20603 ? (TARGET_POWERPC64
20604 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
20605 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
20606 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
20607 used_update
= true;
20610 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20611 dst
= replace_equiv_address (dst
, breg
);
20613 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
20614 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20616 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
20618 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20621 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20622 emit_insn (gen_rtx_SET (VOIDmode
,
20623 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
20624 used_update
= true;
20627 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20628 XEXP (XEXP (dst
, 0), 1)));
20629 dst
= replace_equiv_address (dst
, basereg
);
20633 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20634 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
20635 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
20637 && REG_P (offsetreg
)
20638 && REGNO (basereg
) != REGNO (offsetreg
));
20639 if (REGNO (basereg
) == 0)
20641 rtx tmp
= offsetreg
;
20642 offsetreg
= basereg
;
20645 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
20646 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
20647 dst
= replace_equiv_address (dst
, basereg
);
20650 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20651 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
20654 for (i
= 0; i
< nregs
; i
++)
20656 /* Calculate index to next subword. */
20661 /* If compiler already emitted move of first word by
20662 store with update, no need to do anything. */
20663 if (j
== 0 && used_update
)
20666 emit_insn (gen_rtx_SET (VOIDmode
,
20667 simplify_gen_subreg (reg_mode
, dst
, mode
,
20668 j
* reg_mode_size
),
20669 simplify_gen_subreg (reg_mode
, src
, mode
,
20670 j
* reg_mode_size
)));
20672 if (restore_basereg
!= NULL_RTX
)
20673 emit_insn (restore_basereg
);
20678 /* This page contains routines that are used to determine what the
20679 function prologue and epilogue code will do and write them out. */
20684 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
20687 /* Return the first fixed-point register that is required to be
20688 saved. 32 if none. */
20691 first_reg_to_save (void)
20695 /* Find lowest numbered live register. */
20696 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
20697 if (save_reg_p (first_reg
))
20700 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
20701 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
20702 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
20703 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
20704 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20705 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20709 && crtl
->uses_pic_offset_table
20710 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20711 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
20717 /* Similar, for FP regs. */
20720 first_fp_reg_to_save (void)
20724 /* Find lowest numbered live register. */
20725 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
20726 if (save_reg_p (first_reg
))
20732 /* Similar, for AltiVec regs. */
20735 first_altivec_reg_to_save (void)
20739 /* Stack frame remains as is unless we are in AltiVec ABI. */
20740 if (! TARGET_ALTIVEC_ABI
)
20741 return LAST_ALTIVEC_REGNO
+ 1;
20743 /* On Darwin, the unwind routines are compiled without
20744 TARGET_ALTIVEC, and use save_world to save/restore the
20745 altivec registers when necessary. */
20746 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20747 && ! TARGET_ALTIVEC
)
20748 return FIRST_ALTIVEC_REGNO
+ 20;
20750 /* Find lowest numbered live register. */
20751 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20752 if (save_reg_p (i
))
20758 /* Return a 32-bit mask of the AltiVec registers we need to set in
20759 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
20760 the 32-bit word is 0. */
20762 static unsigned int
20763 compute_vrsave_mask (void)
20765 unsigned int i
, mask
= 0;
20767 /* On Darwin, the unwind routines are compiled without
20768 TARGET_ALTIVEC, and use save_world to save/restore the
20769 call-saved altivec registers when necessary. */
20770 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20771 && ! TARGET_ALTIVEC
)
20774 /* First, find out if we use _any_ altivec registers. */
20775 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20776 if (df_regs_ever_live_p (i
))
20777 mask
|= ALTIVEC_REG_BIT (i
);
20782 /* Next, remove the argument registers from the set. These must
20783 be in the VRSAVE mask set by the caller, so we don't need to add
20784 them in again. More importantly, the mask we compute here is
20785 used to generate CLOBBERs in the set_vrsave insn, and we do not
20786 wish the argument registers to die. */
20787 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
20788 mask
&= ~ALTIVEC_REG_BIT (i
);
20790 /* Similarly, remove the return value from the set. */
20793 diddle_return_value (is_altivec_return_reg
, &yes
);
20795 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
20801 /* For a very restricted set of circumstances, we can cut down the
20802 size of prologues/epilogues by calling our own save/restore-the-world
20806 compute_save_world_info (rs6000_stack_t
*info_ptr
)
20808 info_ptr
->world_save_p
= 1;
20809 info_ptr
->world_save_p
20810 = (WORLD_SAVE_P (info_ptr
)
20811 && DEFAULT_ABI
== ABI_DARWIN
20812 && !cfun
->has_nonlocal_label
20813 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
20814 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
20815 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
20816 && info_ptr
->cr_save_p
);
20818 /* This will not work in conjunction with sibcalls. Make sure there
20819 are none. (This check is expensive, but seldom executed.) */
20820 if (WORLD_SAVE_P (info_ptr
))
20823 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
20824 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
20826 info_ptr
->world_save_p
= 0;
20831 if (WORLD_SAVE_P (info_ptr
))
20833 /* Even if we're not touching VRsave, make sure there's room on the
20834 stack for it, if it looks like we're calling SAVE_WORLD, which
20835 will attempt to save it. */
20836 info_ptr
->vrsave_size
= 4;
20838 /* If we are going to save the world, we need to save the link register too. */
20839 info_ptr
->lr_save_p
= 1;
20841 /* "Save" the VRsave register too if we're saving the world. */
20842 if (info_ptr
->vrsave_mask
== 0)
20843 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20845 /* Because the Darwin register save/restore routines only handle
20846 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
20848 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
20849 && (info_ptr
->first_altivec_reg_save
20850 >= FIRST_SAVED_ALTIVEC_REGNO
));
20857 is_altivec_return_reg (rtx reg
, void *xyes
)
20859 bool *yes
= (bool *) xyes
;
20860 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
20865 /* Look for user-defined global regs in the range FIRST to LAST-1.
20866 We should not restore these, and so cannot use lmw or out-of-line
20867 restore functions if there are any. We also can't save them
20868 (well, emit frame notes for them), because frame unwinding during
20869 exception handling will restore saved registers. */
20872 global_regs_p (unsigned first
, unsigned last
)
20874 while (first
< last
)
20875 if (global_regs
[first
++])
20880 /* Determine the strategy for savings/restoring registers. */
20883 SAVRES_MULTIPLE
= 0x1,
20884 SAVE_INLINE_FPRS
= 0x2,
20885 SAVE_INLINE_GPRS
= 0x4,
20886 REST_INLINE_FPRS
= 0x8,
20887 REST_INLINE_GPRS
= 0x10,
20888 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
20889 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
20890 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
20891 SAVE_INLINE_VRS
= 0x100,
20892 REST_INLINE_VRS
= 0x200
20896 rs6000_savres_strategy (rs6000_stack_t
*info
,
20897 bool using_static_chain_p
)
20902 if (TARGET_MULTIPLE
20903 && !TARGET_POWERPC64
20904 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20905 && info
->first_gp_reg_save
< 31
20906 && !global_regs_p (info
->first_gp_reg_save
, 32))
20907 strategy
|= SAVRES_MULTIPLE
;
20909 if (crtl
->calls_eh_return
20910 || cfun
->machine
->ra_need_lr
)
20911 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20912 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20913 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20915 if (info
->first_fp_reg_save
== 64
20916 /* The out-of-line FP routines use double-precision stores;
20917 we can't use those routines if we don't have such stores. */
20918 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20919 || global_regs_p (info
->first_fp_reg_save
, 64))
20920 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20922 if (info
->first_gp_reg_save
== 32
20923 || (!(strategy
& SAVRES_MULTIPLE
)
20924 && global_regs_p (info
->first_gp_reg_save
, 32)))
20925 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20927 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20928 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20929 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20931 /* Define cutoff for using out-of-line functions to save registers. */
20932 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20934 if (!optimize_size
)
20936 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20937 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20938 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20942 /* Prefer out-of-line restore if it will exit. */
20943 if (info
->first_fp_reg_save
> 61)
20944 strategy
|= SAVE_INLINE_FPRS
;
20945 if (info
->first_gp_reg_save
> 29)
20947 if (info
->first_fp_reg_save
== 64)
20948 strategy
|= SAVE_INLINE_GPRS
;
20950 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20952 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20953 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20956 else if (DEFAULT_ABI
== ABI_DARWIN
)
20958 if (info
->first_fp_reg_save
> 60)
20959 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20960 if (info
->first_gp_reg_save
> 29)
20961 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20962 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20966 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20967 if (info
->first_fp_reg_save
> 61)
20968 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20969 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20970 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20973 /* Don't bother to try to save things out-of-line if r11 is occupied
20974 by the static chain. It would require too much fiddling and the
20975 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20976 pointer on Darwin, and AIX uses r1 or r12. */
20977 if (using_static_chain_p
20978 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20979 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20981 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20983 /* We can only use the out-of-line routines to restore if we've
20984 saved all the registers from first_fp_reg_save in the prologue.
20985 Otherwise, we risk loading garbage. */
20986 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20990 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20991 if (!save_reg_p (i
))
20993 strategy
|= REST_INLINE_FPRS
;
20998 /* If we are going to use store multiple, then don't even bother
20999 with the out-of-line routines, since the store-multiple
21000 instruction will always be smaller. */
21001 if ((strategy
& SAVRES_MULTIPLE
))
21002 strategy
|= SAVE_INLINE_GPRS
;
21004 /* info->lr_save_p isn't yet set if the only reason lr needs to be
21005 saved is an out-of-line save or restore. Set up the value for
21006 the next test (excluding out-of-line gpr restore). */
21007 lr_save_p
= (info
->lr_save_p
21008 || !(strategy
& SAVE_INLINE_GPRS
)
21009 || !(strategy
& SAVE_INLINE_FPRS
)
21010 || !(strategy
& SAVE_INLINE_VRS
)
21011 || !(strategy
& REST_INLINE_FPRS
)
21012 || !(strategy
& REST_INLINE_VRS
));
21014 /* The situation is more complicated with load multiple. We'd
21015 prefer to use the out-of-line routines for restores, since the
21016 "exit" out-of-line routines can handle the restore of LR and the
21017 frame teardown. However if doesn't make sense to use the
21018 out-of-line routine if that is the only reason we'd need to save
21019 LR, and we can't use the "exit" out-of-line gpr restore if we
21020 have saved some fprs; In those cases it is advantageous to use
21021 load multiple when available. */
21022 if ((strategy
& SAVRES_MULTIPLE
)
21024 || info
->first_fp_reg_save
!= 64))
21025 strategy
|= REST_INLINE_GPRS
;
21027 /* Saving CR interferes with the exit routines used on the SPE, so
21030 && info
->spe_64bit_regs_used
21031 && info
->cr_save_p
)
21032 strategy
|= REST_INLINE_GPRS
;
21034 /* We can only use load multiple or the out-of-line routines to
21035 restore if we've used store multiple or out-of-line routines
21036 in the prologue, i.e. if we've saved all the registers from
21037 first_gp_reg_save. Otherwise, we risk loading garbage. */
21038 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
21039 == SAVE_INLINE_GPRS
)
21043 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
21044 if (!save_reg_p (i
))
21046 strategy
|= REST_INLINE_GPRS
;
21051 if (TARGET_ELF
&& TARGET_64BIT
)
21053 if (!(strategy
& SAVE_INLINE_FPRS
))
21054 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
21055 else if (!(strategy
& SAVE_INLINE_GPRS
)
21056 && info
->first_fp_reg_save
== 64)
21057 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
21059 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
21060 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
21062 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
21063 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
21068 /* Calculate the stack information for the current function. This is
21069 complicated by having two separate calling sequences, the AIX calling
21070 sequence and the V.4 calling sequence.
21072 AIX (and Darwin/Mac OS X) stack frames look like:
21074 SP----> +---------------------------------------+
21075 | back chain to caller | 0 0
21076 +---------------------------------------+
21077 | saved CR | 4 8 (8-11)
21078 +---------------------------------------+
21080 +---------------------------------------+
21081 | reserved for compilers | 12 24
21082 +---------------------------------------+
21083 | reserved for binders | 16 32
21084 +---------------------------------------+
21085 | saved TOC pointer | 20 40
21086 +---------------------------------------+
21087 | Parameter save area (P) | 24 48
21088 +---------------------------------------+
21089 | Alloca space (A) | 24+P etc.
21090 +---------------------------------------+
21091 | Local variable space (L) | 24+P+A
21092 +---------------------------------------+
21093 | Float/int conversion temporary (X) | 24+P+A+L
21094 +---------------------------------------+
21095 | Save area for AltiVec registers (W) | 24+P+A+L+X
21096 +---------------------------------------+
21097 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
21098 +---------------------------------------+
21099 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
21100 +---------------------------------------+
21101 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
21102 +---------------------------------------+
21103 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
21104 +---------------------------------------+
21105 old SP->| back chain to caller's caller |
21106 +---------------------------------------+
21108 The required alignment for AIX configurations is two words (i.e., 8
21111 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
21113 SP----> +---------------------------------------+
21114 | Back chain to caller | 0
21115 +---------------------------------------+
21116 | Save area for CR | 8
21117 +---------------------------------------+
21119 +---------------------------------------+
21120 | Saved TOC pointer | 24
21121 +---------------------------------------+
21122 | Parameter save area (P) | 32
21123 +---------------------------------------+
21124 | Alloca space (A) | 32+P
21125 +---------------------------------------+
21126 | Local variable space (L) | 32+P+A
21127 +---------------------------------------+
21128 | Save area for AltiVec registers (W) | 32+P+A+L
21129 +---------------------------------------+
21130 | AltiVec alignment padding (Y) | 32+P+A+L+W
21131 +---------------------------------------+
21132 | Save area for GP registers (G) | 32+P+A+L+W+Y
21133 +---------------------------------------+
21134 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
21135 +---------------------------------------+
21136 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
21137 +---------------------------------------+
21140 V.4 stack frames look like:
21142 SP----> +---------------------------------------+
21143 | back chain to caller | 0
21144 +---------------------------------------+
21145 | caller's saved LR | 4
21146 +---------------------------------------+
21147 | Parameter save area (P) | 8
21148 +---------------------------------------+
21149 | Alloca space (A) | 8+P
21150 +---------------------------------------+
21151 | Varargs save area (V) | 8+P+A
21152 +---------------------------------------+
21153 | Local variable space (L) | 8+P+A+V
21154 +---------------------------------------+
21155 | Float/int conversion temporary (X) | 8+P+A+V+L
21156 +---------------------------------------+
21157 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
21158 +---------------------------------------+
21159 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
21160 +---------------------------------------+
21161 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
21162 +---------------------------------------+
21163 | SPE: area for 64-bit GP registers |
21164 +---------------------------------------+
21165 | SPE alignment padding |
21166 +---------------------------------------+
21167 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
21168 +---------------------------------------+
21169 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
21170 +---------------------------------------+
21171 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
21172 +---------------------------------------+
21173 old SP->| back chain to caller's caller |
21174 +---------------------------------------+
21176 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
21177 given. (But note below and in sysv4.h that we require only 8 and
21178 may round up the size of our stack frame anyways. The historical
21179 reason is early versions of powerpc-linux which didn't properly
21180 align the stack at program startup. A happy side-effect is that
21181 -mno-eabi libraries can be used with -meabi programs.)
21183 The EABI configuration defaults to the V.4 layout. However,
21184 the stack alignment requirements may differ. If -mno-eabi is not
21185 given, the required stack alignment is 8 bytes; if -mno-eabi is
21186 given, the required alignment is 16 bytes. (But see V.4 comment
21189 #ifndef ABI_STACK_BOUNDARY
21190 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
21193 static rs6000_stack_t
*
21194 rs6000_stack_info (void)
21196 rs6000_stack_t
*info_ptr
= &stack_info
;
21197 int reg_size
= TARGET_32BIT
? 4 : 8;
21202 HOST_WIDE_INT non_fixed_size
;
21203 bool using_static_chain_p
;
21205 if (reload_completed
&& info_ptr
->reload_completed
)
21208 memset (info_ptr
, 0, sizeof (*info_ptr
));
21209 info_ptr
->reload_completed
= reload_completed
;
21213 /* Cache value so we don't rescan instruction chain over and over. */
21214 if (cfun
->machine
->insn_chain_scanned_p
== 0)
21215 cfun
->machine
->insn_chain_scanned_p
21216 = spe_func_has_64bit_regs_p () + 1;
21217 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
21220 /* Select which calling sequence. */
21221 info_ptr
->abi
= DEFAULT_ABI
;
21223 /* Calculate which registers need to be saved & save area size. */
21224 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
21225 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
21226 even if it currently looks like we won't. Reload may need it to
21227 get at a constant; if so, it will have already created a constant
21228 pool entry for it. */
21229 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
21230 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
21231 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
21232 && crtl
->uses_const_pool
21233 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
21234 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
21236 first_gp
= info_ptr
->first_gp_reg_save
;
21238 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
21240 /* For the SPE, we have an additional upper 32-bits on each GPR.
21241 Ideally we should save the entire 64-bits only when the upper
21242 half is used in SIMD instructions. Since we only record
21243 registers live (not the size they are used in), this proves
21244 difficult because we'd have to traverse the instruction chain at
21245 the right time, taking reload into account. This is a real pain,
21246 so we opt to save the GPRs in 64-bits always if but one register
21247 gets used in 64-bits. Otherwise, all the registers in the frame
21248 get saved in 32-bits.
21250 So... since when we save all GPRs (except the SP) in 64-bits, the
21251 traditional GP save area will be empty. */
21252 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21253 info_ptr
->gp_size
= 0;
21255 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
21256 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
21258 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
21259 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
21260 - info_ptr
->first_altivec_reg_save
);
21262 /* Does this function call anything? */
21263 info_ptr
->calls_p
= (! crtl
->is_leaf
21264 || cfun
->machine
->ra_needs_full_frame
);
21266 /* Determine if we need to save the condition code registers. */
21267 if (df_regs_ever_live_p (CR2_REGNO
)
21268 || df_regs_ever_live_p (CR3_REGNO
)
21269 || df_regs_ever_live_p (CR4_REGNO
))
21271 info_ptr
->cr_save_p
= 1;
21272 if (DEFAULT_ABI
== ABI_V4
)
21273 info_ptr
->cr_size
= reg_size
;
21276 /* If the current function calls __builtin_eh_return, then we need
21277 to allocate stack space for registers that will hold data for
21278 the exception handler. */
21279 if (crtl
->calls_eh_return
)
21282 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
21285 /* SPE saves EH registers in 64-bits. */
21286 ehrd_size
= i
* (TARGET_SPE_ABI
21287 && info_ptr
->spe_64bit_regs_used
!= 0
21288 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
21293 /* In the ELFv2 ABI, we also need to allocate space for separate
21294 CR field save areas if the function calls __builtin_eh_return. */
21295 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
21297 /* This hard-codes that we have three call-saved CR fields. */
21298 ehcr_size
= 3 * reg_size
;
21299 /* We do *not* use the regular CR save mechanism. */
21300 info_ptr
->cr_save_p
= 0;
21305 /* Determine various sizes. */
21306 info_ptr
->reg_size
= reg_size
;
21307 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
21308 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
21309 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
21310 TARGET_ALTIVEC
? 16 : 8);
21311 if (FRAME_GROWS_DOWNWARD
)
21312 info_ptr
->vars_size
21313 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
21314 + info_ptr
->parm_size
,
21315 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
21316 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
21317 + info_ptr
->parm_size
);
21319 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21320 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
21322 info_ptr
->spe_gp_size
= 0;
21324 if (TARGET_ALTIVEC_ABI
)
21325 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
21327 info_ptr
->vrsave_mask
= 0;
21329 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
21330 info_ptr
->vrsave_size
= 4;
21332 info_ptr
->vrsave_size
= 0;
21334 compute_save_world_info (info_ptr
);
21336 /* Calculate the offsets. */
21337 switch (DEFAULT_ABI
)
21341 gcc_unreachable ();
21346 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21347 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21349 if (TARGET_ALTIVEC_ABI
)
21351 info_ptr
->vrsave_save_offset
21352 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
21354 /* Align stack so vector save area is on a quadword boundary.
21355 The padding goes above the vectors. */
21356 if (info_ptr
->altivec_size
!= 0)
21357 info_ptr
->altivec_padding_size
21358 = info_ptr
->vrsave_save_offset
& 0xF;
21360 info_ptr
->altivec_padding_size
= 0;
21362 info_ptr
->altivec_save_offset
21363 = info_ptr
->vrsave_save_offset
21364 - info_ptr
->altivec_padding_size
21365 - info_ptr
->altivec_size
;
21366 gcc_assert (info_ptr
->altivec_size
== 0
21367 || info_ptr
->altivec_save_offset
% 16 == 0);
21369 /* Adjust for AltiVec case. */
21370 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
21373 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
21375 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
21376 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
21377 info_ptr
->lr_save_offset
= 2*reg_size
;
21381 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21382 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21383 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
21385 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21387 /* Align stack so SPE GPR save area is aligned on a
21388 double-word boundary. */
21389 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
21390 info_ptr
->spe_padding_size
21391 = 8 - (-info_ptr
->cr_save_offset
% 8);
21393 info_ptr
->spe_padding_size
= 0;
21395 info_ptr
->spe_gp_save_offset
21396 = info_ptr
->cr_save_offset
21397 - info_ptr
->spe_padding_size
21398 - info_ptr
->spe_gp_size
;
21400 /* Adjust for SPE case. */
21401 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
21403 else if (TARGET_ALTIVEC_ABI
)
21405 info_ptr
->vrsave_save_offset
21406 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
21408 /* Align stack so vector save area is on a quadword boundary. */
21409 if (info_ptr
->altivec_size
!= 0)
21410 info_ptr
->altivec_padding_size
21411 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
21413 info_ptr
->altivec_padding_size
= 0;
21415 info_ptr
->altivec_save_offset
21416 = info_ptr
->vrsave_save_offset
21417 - info_ptr
->altivec_padding_size
21418 - info_ptr
->altivec_size
;
21420 /* Adjust for AltiVec case. */
21421 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
21424 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
21425 info_ptr
->ehrd_offset
-= ehrd_size
;
21426 info_ptr
->lr_save_offset
= reg_size
;
21430 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
21431 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
21432 + info_ptr
->gp_size
21433 + info_ptr
->altivec_size
21434 + info_ptr
->altivec_padding_size
21435 + info_ptr
->spe_gp_size
21436 + info_ptr
->spe_padding_size
21439 + info_ptr
->cr_size
21440 + info_ptr
->vrsave_size
,
21443 non_fixed_size
= (info_ptr
->vars_size
21444 + info_ptr
->parm_size
21445 + info_ptr
->save_size
);
21447 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
21448 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
21450 /* Determine if we need to save the link register. */
21451 if (info_ptr
->calls_p
21452 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21454 && !TARGET_PROFILE_KERNEL
)
21455 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
21456 #ifdef TARGET_RELOCATABLE
21457 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
21459 || rs6000_ra_ever_killed ())
21460 info_ptr
->lr_save_p
= 1;
21462 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21463 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21464 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21465 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
21466 using_static_chain_p
);
21468 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
21469 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
21470 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
21471 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
21472 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
21473 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
21474 info_ptr
->lr_save_p
= 1;
21476 if (info_ptr
->lr_save_p
)
21477 df_set_regs_ever_live (LR_REGNO
, true);
21479 /* Determine if we need to allocate any stack frame:
21481 For AIX we need to push the stack if a frame pointer is needed
21482 (because the stack might be dynamically adjusted), if we are
21483 debugging, if we make calls, or if the sum of fp_save, gp_save,
21484 and local variables are more than the space needed to save all
21485 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
21486 + 18*8 = 288 (GPR13 reserved).
21488 For V.4 we don't have the stack cushion that AIX uses, but assume
21489 that the debugger can handle stackless frames. */
21491 if (info_ptr
->calls_p
)
21492 info_ptr
->push_p
= 1;
21494 else if (DEFAULT_ABI
== ABI_V4
)
21495 info_ptr
->push_p
= non_fixed_size
!= 0;
21497 else if (frame_pointer_needed
)
21498 info_ptr
->push_p
= 1;
21500 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
21501 info_ptr
->push_p
= 1;
21504 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
21506 /* Zero offsets if we're not saving those registers. */
21507 if (info_ptr
->fp_size
== 0)
21508 info_ptr
->fp_save_offset
= 0;
21510 if (info_ptr
->gp_size
== 0)
21511 info_ptr
->gp_save_offset
= 0;
21513 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
21514 info_ptr
->altivec_save_offset
= 0;
21516 /* Zero VRSAVE offset if not saved and restored. */
21517 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
21518 info_ptr
->vrsave_save_offset
= 0;
21520 if (! TARGET_SPE_ABI
21521 || info_ptr
->spe_64bit_regs_used
== 0
21522 || info_ptr
->spe_gp_size
== 0)
21523 info_ptr
->spe_gp_save_offset
= 0;
21525 if (! info_ptr
->lr_save_p
)
21526 info_ptr
->lr_save_offset
= 0;
21528 if (! info_ptr
->cr_save_p
)
21529 info_ptr
->cr_save_offset
= 0;
21534 /* Return true if the current function uses any GPRs in 64-bit SIMD
21538 spe_func_has_64bit_regs_p (void)
21540 rtx_insn
*insns
, *insn
;
21542 /* Functions that save and restore all the call-saved registers will
21543 need to save/restore the registers in 64-bits. */
21544 if (crtl
->calls_eh_return
21545 || cfun
->calls_setjmp
21546 || crtl
->has_nonlocal_goto
)
21549 insns
= get_insns ();
21551 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21557 /* FIXME: This should be implemented with attributes...
21559 (set_attr "spe64" "true")....then,
21560 if (get_spe64(insn)) return true;
21562 It's the only reliable way to do the stuff below. */
21564 i
= PATTERN (insn
);
21565 if (GET_CODE (i
) == SET
)
21567 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
21569 if (SPE_VECTOR_MODE (mode
))
21571 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
21581 debug_stack_info (rs6000_stack_t
*info
)
21583 const char *abi_string
;
21586 info
= rs6000_stack_info ();
21588 fprintf (stderr
, "\nStack information for function %s:\n",
21589 ((current_function_decl
&& DECL_NAME (current_function_decl
))
21590 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
21595 default: abi_string
= "Unknown"; break;
21596 case ABI_NONE
: abi_string
= "NONE"; break;
21597 case ABI_AIX
: abi_string
= "AIX"; break;
21598 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
21599 case ABI_DARWIN
: abi_string
= "Darwin"; break;
21600 case ABI_V4
: abi_string
= "V.4"; break;
21603 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
21605 if (TARGET_ALTIVEC_ABI
)
21606 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
21608 if (TARGET_SPE_ABI
)
21609 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
21611 if (info
->first_gp_reg_save
!= 32)
21612 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
21614 if (info
->first_fp_reg_save
!= 64)
21615 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
21617 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
21618 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
21619 info
->first_altivec_reg_save
);
21621 if (info
->lr_save_p
)
21622 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
21624 if (info
->cr_save_p
)
21625 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
21627 if (info
->vrsave_mask
)
21628 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
21631 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
21634 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
21636 if (info
->gp_save_offset
)
21637 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
21639 if (info
->fp_save_offset
)
21640 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
21642 if (info
->altivec_save_offset
)
21643 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
21644 info
->altivec_save_offset
);
21646 if (info
->spe_gp_save_offset
)
21647 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
21648 info
->spe_gp_save_offset
);
21650 if (info
->vrsave_save_offset
)
21651 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
21652 info
->vrsave_save_offset
);
21654 if (info
->lr_save_offset
)
21655 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
21657 if (info
->cr_save_offset
)
21658 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
21660 if (info
->varargs_save_offset
)
21661 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
21663 if (info
->total_size
)
21664 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21667 if (info
->vars_size
)
21668 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21671 if (info
->parm_size
)
21672 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
21674 if (info
->fixed_size
)
21675 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
21678 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
21680 if (info
->spe_gp_size
)
21681 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
21684 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
21686 if (info
->altivec_size
)
21687 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
21689 if (info
->vrsave_size
)
21690 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
21692 if (info
->altivec_padding_size
)
21693 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
21694 info
->altivec_padding_size
);
21696 if (info
->spe_padding_size
)
21697 fprintf (stderr
, "\tspe_padding_size = %5d\n",
21698 info
->spe_padding_size
);
21701 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
21703 if (info
->save_size
)
21704 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
21706 if (info
->reg_size
!= 4)
21707 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
21709 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
21711 fprintf (stderr
, "\n");
21715 rs6000_return_addr (int count
, rtx frame
)
21717 /* Currently we don't optimize very well between prolog and body
21718 code and for PIC code the code can be actually quite bad, so
21719 don't try to be too clever here. */
21721 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
21723 cfun
->machine
->ra_needs_full_frame
= 1;
21730 plus_constant (Pmode
,
21732 (gen_rtx_MEM (Pmode
,
21733 memory_address (Pmode
, frame
))),
21734 RETURN_ADDRESS_OFFSET
)));
21737 cfun
->machine
->ra_need_lr
= 1;
21738 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
21741 /* Say whether a function is a candidate for sibcall handling or not. */
21744 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
21749 fntype
= TREE_TYPE (decl
);
21751 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
21753 /* We can't do it if the called function has more vector parameters
21754 than the current function; there's nowhere to put the VRsave code. */
21755 if (TARGET_ALTIVEC_ABI
21756 && TARGET_ALTIVEC_VRSAVE
21757 && !(decl
&& decl
== current_function_decl
))
21759 function_args_iterator args_iter
;
21763 /* Functions with vector parameters are required to have a
21764 prototype, so the argument type info must be available
21766 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
21767 if (TREE_CODE (type
) == VECTOR_TYPE
21768 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21771 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
21772 if (TREE_CODE (type
) == VECTOR_TYPE
21773 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21780 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
21781 functions, because the callee may have a different TOC pointer to
21782 the caller and there's no way to ensure we restore the TOC when
21783 we return. With the secure-plt SYSV ABI we can't make non-local
21784 calls when -fpic/PIC because the plt call stubs use r30. */
21785 if (DEFAULT_ABI
== ABI_DARWIN
21786 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21788 && !DECL_EXTERNAL (decl
)
21789 && (*targetm
.binds_local_p
) (decl
))
21790 || (DEFAULT_ABI
== ABI_V4
21791 && (!TARGET_SECURE_PLT
21794 && (*targetm
.binds_local_p
) (decl
)))))
21796 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
21798 if (!lookup_attribute ("longcall", attr_list
)
21799 || lookup_attribute ("shortcall", attr_list
))
21807 rs6000_ra_ever_killed (void)
21813 if (cfun
->is_thunk
)
21816 if (cfun
->machine
->lr_save_state
)
21817 return cfun
->machine
->lr_save_state
- 1;
21819 /* regs_ever_live has LR marked as used if any sibcalls are present,
21820 but this should not force saving and restoring in the
21821 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
21822 clobbers LR, so that is inappropriate. */
21824 /* Also, the prologue can generate a store into LR that
21825 doesn't really count, like this:
21828 bcl to set PIC register
21832 When we're called from the epilogue, we need to avoid counting
21833 this as a store. */
21835 push_topmost_sequence ();
21836 top
= get_insns ();
21837 pop_topmost_sequence ();
21838 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
21840 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21846 if (!SIBLING_CALL_P (insn
))
21849 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
21851 else if (set_of (reg
, insn
) != NULL_RTX
21852 && !prologue_epilogue_contains (insn
))
21859 /* Emit instructions needed to load the TOC register.
21860 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
21861 a constant pool; or for SVR4 -fpic. */
21864 rs6000_emit_load_toc_table (int fromprolog
)
21867 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
21869 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
21872 rtx lab
, tmp1
, tmp2
, got
;
21874 lab
= gen_label_rtx ();
21875 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
21876 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21878 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21880 got
= rs6000_got_sym ();
21881 tmp1
= tmp2
= dest
;
21884 tmp1
= gen_reg_rtx (Pmode
);
21885 tmp2
= gen_reg_rtx (Pmode
);
21887 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
21888 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
21889 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
21890 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
21892 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
21894 emit_insn (gen_load_toc_v4_pic_si ());
21895 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21897 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
21900 rtx temp0
= (fromprolog
21901 ? gen_rtx_REG (Pmode
, 0)
21902 : gen_reg_rtx (Pmode
));
21908 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21909 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21911 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21912 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21914 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21915 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21916 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21922 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21923 lab
= gen_label_rtx ();
21924 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21925 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21926 if (TARGET_LINK_STACK
)
21927 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21928 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21930 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21932 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21934 /* This is for AIX code running in non-PIC ELF32. */
21937 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21938 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21940 emit_insn (gen_elf_high (dest
, realsym
));
21941 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21945 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21948 emit_insn (gen_load_toc_aix_si (dest
));
21950 emit_insn (gen_load_toc_aix_di (dest
));
21954 /* Emit instructions to restore the link register after determining where
21955 its value has been stored. */
21958 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21960 rs6000_stack_t
*info
= rs6000_stack_info ();
21963 operands
[0] = source
;
21964 operands
[1] = scratch
;
21966 if (info
->lr_save_p
)
21968 rtx frame_rtx
= stack_pointer_rtx
;
21969 HOST_WIDE_INT sp_offset
= 0;
21972 if (frame_pointer_needed
21973 || cfun
->calls_alloca
21974 || info
->total_size
> 32767)
21976 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21977 emit_move_insn (operands
[1], tmp
);
21978 frame_rtx
= operands
[1];
21980 else if (info
->push_p
)
21981 sp_offset
= info
->total_size
;
21983 tmp
= plus_constant (Pmode
, frame_rtx
,
21984 info
->lr_save_offset
+ sp_offset
);
21985 tmp
= gen_frame_mem (Pmode
, tmp
);
21986 emit_move_insn (tmp
, operands
[0]);
21989 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21991 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21992 state of lr_save_p so any change from here on would be a bug. In
21993 particular, stop rs6000_ra_ever_killed from considering the SET
21994 of lr we may have added just above. */
21995 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21998 static GTY(()) alias_set_type set
= -1;
22001 get_TOC_alias_set (void)
22004 set
= new_alias_set ();
22008 /* This returns nonzero if the current function uses the TOC. This is
22009 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
22010 is generated by the ABI_V4 load_toc_* patterns. */
22017 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
22020 rtx pat
= PATTERN (insn
);
22023 if (GET_CODE (pat
) == PARALLEL
)
22024 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
22026 rtx sub
= XVECEXP (pat
, 0, i
);
22027 if (GET_CODE (sub
) == USE
)
22029 sub
= XEXP (sub
, 0);
22030 if (GET_CODE (sub
) == UNSPEC
22031 && XINT (sub
, 1) == UNSPEC_TOC
)
22041 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
22043 rtx tocrel
, tocreg
, hi
;
22045 if (TARGET_DEBUG_ADDR
)
22047 if (GET_CODE (symbol
) == SYMBOL_REF
)
22048 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
22052 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
22053 GET_RTX_NAME (GET_CODE (symbol
)));
22054 debug_rtx (symbol
);
22058 if (!can_create_pseudo_p ())
22059 df_set_regs_ever_live (TOC_REGISTER
, true);
22061 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
22062 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
22063 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
22066 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
22067 if (largetoc_reg
!= NULL
)
22069 emit_move_insn (largetoc_reg
, hi
);
22072 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
22075 /* Issue assembly directives that create a reference to the given DWARF
22076 FRAME_TABLE_LABEL from the current function section. */
22078 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
22080 fprintf (asm_out_file
, "\t.ref %s\n",
22081 (* targetm
.strip_name_encoding
) (frame_table_label
));
22084 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
22085 and the change to the stack pointer. */
22088 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
22095 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22096 if (hard_frame_needed
)
22097 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
22098 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
22099 || (hard_frame_needed
22100 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
22103 p
= rtvec_alloc (i
);
22106 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
22107 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
22110 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
22113 /* Emit the correct code for allocating stack space, as insns.
22114 If COPY_REG, make sure a copy of the old frame is left there.
22115 The generated code may use hard register 0 as a temporary. */
22118 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
22121 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22122 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
22123 rtx todec
= gen_int_mode (-size
, Pmode
);
22126 if (INTVAL (todec
) != -size
)
22128 warning (0, "stack frame too large");
22129 emit_insn (gen_trap ());
22133 if (crtl
->limit_stack
)
22135 if (REG_P (stack_limit_rtx
)
22136 && REGNO (stack_limit_rtx
) > 1
22137 && REGNO (stack_limit_rtx
) <= 31)
22139 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
22140 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
22143 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
22145 && DEFAULT_ABI
== ABI_V4
)
22147 rtx toload
= gen_rtx_CONST (VOIDmode
,
22148 gen_rtx_PLUS (Pmode
,
22152 emit_insn (gen_elf_high (tmp_reg
, toload
));
22153 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
22154 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
22158 warning (0, "stack limit expression is not supported");
22164 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
22166 emit_move_insn (copy_reg
, stack_reg
);
22171 /* Need a note here so that try_split doesn't get confused. */
22172 if (get_last_insn () == NULL_RTX
)
22173 emit_note (NOTE_INSN_DELETED
);
22174 insn
= emit_move_insn (tmp_reg
, todec
);
22175 try_split (PATTERN (insn
), insn
, 0);
22179 insn
= emit_insn (TARGET_32BIT
22180 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
22182 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
22183 todec
, stack_reg
));
22184 /* Since we didn't use gen_frame_mem to generate the MEM, grab
22185 it now and set the alias set/attributes. The above gen_*_update
22186 calls will generate a PARALLEL with the MEM set being the first
22188 par
= PATTERN (insn
);
22189 gcc_assert (GET_CODE (par
) == PARALLEL
);
22190 set
= XVECEXP (par
, 0, 0);
22191 gcc_assert (GET_CODE (set
) == SET
);
22192 mem
= SET_DEST (set
);
22193 gcc_assert (MEM_P (mem
));
22194 MEM_NOTRAP_P (mem
) = 1;
22195 set_mem_alias_set (mem
, get_frame_alias_set ());
22197 RTX_FRAME_RELATED_P (insn
) = 1;
22198 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22199 gen_rtx_SET (VOIDmode
, stack_reg
,
22200 gen_rtx_PLUS (Pmode
, stack_reg
,
22201 GEN_INT (-size
))));
22204 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
22206 #if PROBE_INTERVAL > 32768
22207 #error Cannot use indexed addressing mode for stack probing
22210 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
22211 inclusive. These are offsets from the current stack pointer. */
22214 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
22216 /* See if we have a constant small number of probes to generate. If so,
22217 that's the easy case. */
22218 if (first
+ size
<= 32768)
22222 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
22223 it exceeds SIZE. If only one probe is needed, this will not
22224 generate any code. Then probe at FIRST + SIZE. */
22225 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
22226 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22229 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22233 /* Otherwise, do the same as above, but in a loop. Note that we must be
22234 extra careful with variables wrapping around because we might be at
22235 the very top (or the very bottom) of the address space and we have
22236 to be able to handle this case properly; in particular, we use an
22237 equality test for the loop condition. */
22240 HOST_WIDE_INT rounded_size
;
22241 rtx r12
= gen_rtx_REG (Pmode
, 12);
22242 rtx r0
= gen_rtx_REG (Pmode
, 0);
22244 /* Sanity check for the addressing mode we're going to use. */
22245 gcc_assert (first
<= 32768);
22247 /* Step 1: round SIZE to the previous multiple of the interval. */
22249 rounded_size
= size
& -PROBE_INTERVAL
;
22252 /* Step 2: compute initial and final value of the loop counter. */
22254 /* TEST_ADDR = SP + FIRST. */
22255 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
22256 plus_constant (Pmode
, stack_pointer_rtx
,
22259 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
22260 if (rounded_size
> 32768)
22262 emit_move_insn (r0
, GEN_INT (-rounded_size
));
22263 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
22264 gen_rtx_PLUS (Pmode
, r12
, r0
)));
22267 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
22268 plus_constant (Pmode
, r12
, -rounded_size
)));
22271 /* Step 3: the loop
22273 while (TEST_ADDR != LAST_ADDR)
22275 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
22279 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
22280 until it is equal to ROUNDED_SIZE. */
22283 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
22285 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
22288 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
22289 that SIZE is equal to ROUNDED_SIZE. */
22291 if (size
!= rounded_size
)
22292 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
22296 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
22297 absolute addresses. */
22300 output_probe_stack_range (rtx reg1
, rtx reg2
)
22302 static int labelno
= 0;
22303 char loop_lab
[32], end_lab
[32];
22306 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
22307 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
22309 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
22311 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
22315 output_asm_insn ("cmpd 0,%0,%1", xops
);
22317 output_asm_insn ("cmpw 0,%0,%1", xops
);
22319 fputs ("\tbeq 0,", asm_out_file
);
22320 assemble_name_raw (asm_out_file
, end_lab
);
22321 fputc ('\n', asm_out_file
);
22323 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
22324 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
22325 output_asm_insn ("addi %0,%0,%1", xops
);
22327 /* Probe at TEST_ADDR and branch. */
22328 xops
[1] = gen_rtx_REG (Pmode
, 0);
22329 output_asm_insn ("stw %1,0(%0)", xops
);
22330 fprintf (asm_out_file
, "\tb ");
22331 assemble_name_raw (asm_out_file
, loop_lab
);
22332 fputc ('\n', asm_out_file
);
22334 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
22339 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
22340 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
22341 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
22342 deduce these equivalences by itself so it wasn't necessary to hold
22343 its hand so much. Don't be tempted to always supply d2_f_d_e with
22344 the actual cfa register, ie. r31 when we are using a hard frame
22345 pointer. That fails when saving regs off r1, and sched moves the
22346 r31 setup past the reg saves. */
22349 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
22350 rtx reg2
, rtx rreg
, rtx split_reg
)
22354 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
22356 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
22359 gcc_checking_assert (val
== 0);
22360 real
= PATTERN (insn
);
22361 if (GET_CODE (real
) == PARALLEL
)
22362 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22363 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22365 rtx set
= XVECEXP (real
, 0, i
);
22367 RTX_FRAME_RELATED_P (set
) = 1;
22369 RTX_FRAME_RELATED_P (insn
) = 1;
22373 /* copy_rtx will not make unique copies of registers, so we need to
22374 ensure we don't have unwanted sharing here. */
22376 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22379 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22381 real
= copy_rtx (PATTERN (insn
));
22383 if (reg2
!= NULL_RTX
)
22384 real
= replace_rtx (real
, reg2
, rreg
);
22386 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
22387 gcc_checking_assert (val
== 0);
22389 real
= replace_rtx (real
, reg
,
22390 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
22391 STACK_POINTER_REGNUM
),
22394 /* We expect that 'real' is either a SET or a PARALLEL containing
22395 SETs (and possibly other stuff). In a PARALLEL, all the SETs
22396 are important so they all have to be marked RTX_FRAME_RELATED_P. */
22398 if (GET_CODE (real
) == SET
)
22402 temp
= simplify_rtx (SET_SRC (set
));
22404 SET_SRC (set
) = temp
;
22405 temp
= simplify_rtx (SET_DEST (set
));
22407 SET_DEST (set
) = temp
;
22408 if (GET_CODE (SET_DEST (set
)) == MEM
)
22410 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22412 XEXP (SET_DEST (set
), 0) = temp
;
22419 gcc_assert (GET_CODE (real
) == PARALLEL
);
22420 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22421 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22423 rtx set
= XVECEXP (real
, 0, i
);
22425 temp
= simplify_rtx (SET_SRC (set
));
22427 SET_SRC (set
) = temp
;
22428 temp
= simplify_rtx (SET_DEST (set
));
22430 SET_DEST (set
) = temp
;
22431 if (GET_CODE (SET_DEST (set
)) == MEM
)
22433 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22435 XEXP (SET_DEST (set
), 0) = temp
;
22437 RTX_FRAME_RELATED_P (set
) = 1;
22441 /* If a store insn has been split into multiple insns, the
22442 true source register is given by split_reg. */
22443 if (split_reg
!= NULL_RTX
)
22444 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
22446 RTX_FRAME_RELATED_P (insn
) = 1;
22447 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
22452 /* Returns an insn that has a vrsave set operation with the
22453 appropriate CLOBBERs. */
22456 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
22459 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
22460 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22463 = gen_rtx_SET (VOIDmode
,
22465 gen_rtx_UNSPEC_VOLATILE (SImode
,
22466 gen_rtvec (2, reg
, vrsave
),
22467 UNSPECV_SET_VRSAVE
));
22471 /* We need to clobber the registers in the mask so the scheduler
22472 does not move sets to VRSAVE before sets of AltiVec registers.
22474 However, if the function receives nonlocal gotos, reload will set
22475 all call saved registers live. We will end up with:
22477 (set (reg 999) (mem))
22478 (parallel [ (set (reg vrsave) (unspec blah))
22479 (clobber (reg 999))])
22481 The clobber will cause the store into reg 999 to be dead, and
22482 flow will attempt to delete an epilogue insn. In this case, we
22483 need an unspec use/set of the register. */
22485 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22486 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22488 if (!epiloguep
|| call_used_regs
[i
])
22489 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
22490 gen_rtx_REG (V4SImode
, i
));
22493 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22496 = gen_rtx_SET (VOIDmode
,
22498 gen_rtx_UNSPEC (V4SImode
,
22499 gen_rtvec (1, reg
), 27));
22503 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
22505 for (i
= 0; i
< nclobs
; ++i
)
22506 XVECEXP (insn
, 0, i
) = clobs
[i
];
22512 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
22516 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
22517 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
22518 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
22522 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
22524 return gen_frame_set (reg
, frame_reg
, offset
, false);
22528 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
22530 return gen_frame_set (reg
, frame_reg
, offset
, true);
22533 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
22534 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
22537 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
22538 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
22542 /* Some cases that need register indexed addressing. */
22543 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
22544 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
22545 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
22547 && SPE_VECTOR_MODE (mode
)
22548 && !SPE_CONST_OFFSET_OK (offset
))));
22550 reg
= gen_rtx_REG (mode
, regno
);
22551 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
22552 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
22553 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22556 /* Emit an offset memory reference suitable for a frame store, while
22557 converting to a valid addressing mode. */
22560 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
22562 rtx int_rtx
, offset_rtx
;
22564 int_rtx
= GEN_INT (offset
);
22566 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
22567 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
22569 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
22570 emit_move_insn (offset_rtx
, int_rtx
);
22573 offset_rtx
= int_rtx
;
22575 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
22578 #ifndef TARGET_FIX_AND_CONTINUE
22579 #define TARGET_FIX_AND_CONTINUE 0
22582 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
22583 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
22584 #define LAST_SAVRES_REGISTER 31
22585 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
22596 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
22598 /* Temporary holding space for an out-of-line register save/restore
22600 static char savres_routine_name
[30];
22602 /* Return the name for an out-of-line register save/restore routine.
22603 We are saving/restoring GPRs if GPR is true. */
22606 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
22608 const char *prefix
= "";
22609 const char *suffix
= "";
22611 /* Different targets are supposed to define
22612 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
22613 routine name could be defined with:
22615 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
22617 This is a nice idea in practice, but in reality, things are
22618 complicated in several ways:
22620 - ELF targets have save/restore routines for GPRs.
22622 - SPE targets use different prefixes for 32/64-bit registers, and
22623 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
22625 - PPC64 ELF targets have routines for save/restore of GPRs that
22626 differ in what they do with the link register, so having a set
22627 prefix doesn't work. (We only use one of the save routines at
22628 the moment, though.)
22630 - PPC32 elf targets have "exit" versions of the restore routines
22631 that restore the link register and can save some extra space.
22632 These require an extra suffix. (There are also "tail" versions
22633 of the restore routines and "GOT" versions of the save routines,
22634 but we don't generate those at present. Same problems apply,
22637 We deal with all this by synthesizing our own prefix/suffix and
22638 using that for the simple sprintf call shown above. */
22641 /* No floating point saves on the SPE. */
22642 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
22644 if ((sel
& SAVRES_SAVE
))
22645 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
22647 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
22649 if ((sel
& SAVRES_LR
))
22652 else if (DEFAULT_ABI
== ABI_V4
)
22657 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22658 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
22659 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22660 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
22661 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22662 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22666 if ((sel
& SAVRES_LR
))
22669 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22671 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
22672 /* No out-of-line save/restore routines for GPRs on AIX. */
22673 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
22677 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22678 prefix
= ((sel
& SAVRES_SAVE
)
22679 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
22680 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
22681 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22683 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
22684 if ((sel
& SAVRES_LR
))
22685 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
22689 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
22690 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
22693 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22694 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22699 if (DEFAULT_ABI
== ABI_DARWIN
)
22701 /* The Darwin approach is (slightly) different, in order to be
22702 compatible with code generated by the system toolchain. There is a
22703 single symbol for the start of save sequence, and the code here
22704 embeds an offset into that code on the basis of the first register
22706 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
22707 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22708 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
22709 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
22710 (regno
- 13) * 4, prefix
, regno
);
22711 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22712 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
22713 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
22714 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22715 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
22716 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
22721 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
22723 return savres_routine_name
;
22726 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
22727 We are saving/restoring GPRs if GPR is true. */
22730 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
22732 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22733 ? info
->first_gp_reg_save
22734 : (sel
& SAVRES_REG
) == SAVRES_FPR
22735 ? info
->first_fp_reg_save
- 32
22736 : (sel
& SAVRES_REG
) == SAVRES_VR
22737 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
22742 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
22743 versions of the gpr routines. */
22744 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
22745 && info
->spe_64bit_regs_used
)
22746 select
^= SAVRES_FPR
^ SAVRES_GPR
;
22748 /* Don't generate bogus routine names. */
22749 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
22750 && regno
<= LAST_SAVRES_REGISTER
22751 && select
>= 0 && select
<= 12);
22753 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
22759 name
= rs6000_savres_routine_name (info
, regno
, sel
);
22761 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
22762 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
22763 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
22769 /* Emit a sequence of insns, including a stack tie if needed, for
22770 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
22771 reset the stack pointer, but move the base of the frame into
22772 reg UPDT_REGNO for use by out-of-line register restore routines. */
22775 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
22776 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
22777 unsigned updt_regno
)
22781 /* This blockage is needed so that sched doesn't decide to move
22782 the sp change before the register restores. */
22783 if (DEFAULT_ABI
== ABI_V4
22785 && info
->spe_64bit_regs_used
!= 0
22786 && info
->first_gp_reg_save
!= 32))
22787 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
22789 /* If we are restoring registers out-of-line, we will be using the
22790 "exit" variants of the restore routines, which will reset the
22791 stack for us. But we do need to point updt_reg into the
22792 right place for those routines. */
22793 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
22795 if (frame_off
!= 0)
22796 return emit_insn (gen_add3_insn (updt_reg_rtx
,
22797 frame_reg_rtx
, GEN_INT (frame_off
)));
22798 else if (REGNO (frame_reg_rtx
) != updt_regno
)
22799 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
22804 /* Return the register number used as a pointer by out-of-line
22805 save/restore functions. */
22807 static inline unsigned
22808 ptr_regno_for_savres (int sel
)
22810 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22811 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
22812 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
22815 /* Construct a parallel rtx describing the effect of a call to an
22816 out-of-line register save/restore routine, and emit the insn
22817 or jump_insn as appropriate. */
22820 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
22821 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
22822 enum machine_mode reg_mode
, int sel
)
22825 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
22826 int reg_size
= GET_MODE_SIZE (reg_mode
);
22832 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22833 ? info
->first_gp_reg_save
22834 : (sel
& SAVRES_REG
) == SAVRES_FPR
22835 ? info
->first_fp_reg_save
22836 : (sel
& SAVRES_REG
) == SAVRES_VR
22837 ? info
->first_altivec_reg_save
22839 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22841 : (sel
& SAVRES_REG
) == SAVRES_FPR
22843 : (sel
& SAVRES_REG
) == SAVRES_VR
22844 ? LAST_ALTIVEC_REGNO
+ 1
22846 n_regs
= end_reg
- start_reg
;
22847 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
22848 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
22851 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22852 RTVEC_ELT (p
, offset
++) = ret_rtx
;
22854 RTVEC_ELT (p
, offset
++)
22855 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
22857 sym
= rs6000_savres_routine_sym (info
, sel
);
22858 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
22860 use_reg
= ptr_regno_for_savres (sel
);
22861 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22863 /* Vector regs are saved/restored using [reg+reg] addressing. */
22864 RTVEC_ELT (p
, offset
++)
22865 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22866 RTVEC_ELT (p
, offset
++)
22867 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22870 RTVEC_ELT (p
, offset
++)
22871 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22873 for (i
= 0; i
< end_reg
- start_reg
; i
++)
22874 RTVEC_ELT (p
, i
+ offset
)
22875 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
22876 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
22877 (sel
& SAVRES_SAVE
) != 0);
22879 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22880 RTVEC_ELT (p
, i
+ offset
)
22881 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
22883 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
22885 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22887 insn
= emit_jump_insn (par
);
22888 JUMP_LABEL (insn
) = ret_rtx
;
22891 insn
= emit_insn (par
);
22895 /* Emit code to store CR fields that need to be saved into REG. */
22898 rs6000_emit_move_from_cr (rtx reg
)
22900 /* Only the ELFv2 ABI allows storing only selected fields. */
22901 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22903 int i
, cr_reg
[8], count
= 0;
22905 /* Collect CR fields that must be saved. */
22906 for (i
= 0; i
< 8; i
++)
22907 if (save_reg_p (CR0_REGNO
+ i
))
22908 cr_reg
[count
++] = i
;
22910 /* If it's just a single one, use mfcrf. */
22913 rtvec p
= rtvec_alloc (1);
22914 rtvec r
= rtvec_alloc (2);
22915 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22916 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22918 = gen_rtx_SET (VOIDmode
, reg
,
22919 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22921 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22925 /* ??? It might be better to handle count == 2 / 3 cases here
22926 as well, using logical operations to combine the values. */
22929 emit_insn (gen_movesi_from_cr (reg
));
22932 /* Determine whether the gp REG is really used. */
22935 rs6000_reg_live_or_pic_offset_p (int reg
)
22937 /* If the function calls eh_return, claim used all the registers that would
22938 be checked for liveness otherwise. This is required for the PIC offset
22939 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22940 register allocation purposes in this case. */
22942 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22943 && (!call_used_regs
[reg
]
22944 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22945 && !TARGET_SINGLE_PIC_BASE
22946 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22947 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22948 && !TARGET_SINGLE_PIC_BASE
22949 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22950 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22953 /* Emit function prologue as insns. */
22956 rs6000_emit_prologue (void)
22958 rs6000_stack_t
*info
= rs6000_stack_info ();
22959 enum machine_mode reg_mode
= Pmode
;
22960 int reg_size
= TARGET_32BIT
? 4 : 8;
22961 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22962 rtx frame_reg_rtx
= sp_reg_rtx
;
22963 unsigned int cr_save_regno
;
22964 rtx cr_save_rtx
= NULL_RTX
;
22967 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22968 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22969 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22970 /* Offset to top of frame for frame_reg and sp respectively. */
22971 HOST_WIDE_INT frame_off
= 0;
22972 HOST_WIDE_INT sp_off
= 0;
22974 #ifdef ENABLE_CHECKING
22975 /* Track and check usage of r0, r11, r12. */
22976 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22977 #define START_USE(R) do \
22979 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22980 reg_inuse |= 1 << (R); \
22982 #define END_USE(R) do \
22984 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22985 reg_inuse &= ~(1 << (R)); \
22987 #define NOT_INUSE(R) do \
22989 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22992 #define START_USE(R) do {} while (0)
22993 #define END_USE(R) do {} while (0)
22994 #define NOT_INUSE(R) do {} while (0)
22997 if (DEFAULT_ABI
== ABI_ELFv2
)
22999 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
23001 /* With -mminimal-toc we may generate an extra use of r2 below. */
23002 if (!TARGET_SINGLE_PIC_BASE
23003 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23004 cfun
->machine
->r2_setup_needed
= true;
23008 if (flag_stack_usage_info
)
23009 current_function_static_stack_size
= info
->total_size
;
23011 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
23013 HOST_WIDE_INT size
= info
->total_size
;
23015 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
23017 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
23018 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
23019 size
- STACK_CHECK_PROTECT
);
23022 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
23025 if (TARGET_FIX_AND_CONTINUE
)
23027 /* gdb on darwin arranges to forward a function from the old
23028 address by modifying the first 5 instructions of the function
23029 to branch to the overriding function. This is necessary to
23030 permit function pointers that point to the old function to
23031 actually forward to the new function. */
23032 emit_insn (gen_nop ());
23033 emit_insn (gen_nop ());
23034 emit_insn (gen_nop ());
23035 emit_insn (gen_nop ());
23036 emit_insn (gen_nop ());
23039 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
23041 reg_mode
= V2SImode
;
23045 /* Handle world saves specially here. */
23046 if (WORLD_SAVE_P (info
))
23053 /* save_world expects lr in r0. */
23054 reg0
= gen_rtx_REG (Pmode
, 0);
23055 if (info
->lr_save_p
)
23057 insn
= emit_move_insn (reg0
,
23058 gen_rtx_REG (Pmode
, LR_REGNO
));
23059 RTX_FRAME_RELATED_P (insn
) = 1;
23062 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
23063 assumptions about the offsets of various bits of the stack
23065 gcc_assert (info
->gp_save_offset
== -220
23066 && info
->fp_save_offset
== -144
23067 && info
->lr_save_offset
== 8
23068 && info
->cr_save_offset
== 4
23071 && (!crtl
->calls_eh_return
23072 || info
->ehrd_offset
== -432)
23073 && info
->vrsave_save_offset
== -224
23074 && info
->altivec_save_offset
== -416);
23076 treg
= gen_rtx_REG (SImode
, 11);
23077 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
23079 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
23080 in R11. It also clobbers R12, so beware! */
23082 /* Preserve CR2 for save_world prologues */
23084 sz
+= 32 - info
->first_gp_reg_save
;
23085 sz
+= 64 - info
->first_fp_reg_save
;
23086 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
23087 p
= rtvec_alloc (sz
);
23089 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
23090 gen_rtx_REG (SImode
,
23092 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
23093 gen_rtx_SYMBOL_REF (Pmode
,
23095 /* We do floats first so that the instruction pattern matches
23097 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23099 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23101 info
->first_fp_reg_save
+ i
),
23103 info
->fp_save_offset
+ frame_off
+ 8 * i
);
23104 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
23106 = gen_frame_store (gen_rtx_REG (V4SImode
,
23107 info
->first_altivec_reg_save
+ i
),
23109 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
23110 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23112 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23114 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23116 /* CR register traditionally saved as CR2. */
23118 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
23119 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
23120 /* Explain about use of R0. */
23121 if (info
->lr_save_p
)
23123 = gen_frame_store (reg0
,
23124 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23125 /* Explain what happens to the stack pointer. */
23127 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
23128 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
23131 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23132 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23133 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
23134 sp_off
= frame_off
= info
->total_size
;
23137 strategy
= info
->savres_strategy
;
23139 /* For V.4, update stack before we do any saving and set back pointer. */
23140 if (! WORLD_SAVE_P (info
)
23142 && (DEFAULT_ABI
== ABI_V4
23143 || crtl
->calls_eh_return
))
23145 bool need_r11
= (TARGET_SPE
23146 ? (!(strategy
& SAVE_INLINE_GPRS
)
23147 && info
->spe_64bit_regs_used
== 0)
23148 : (!(strategy
& SAVE_INLINE_FPRS
)
23149 || !(strategy
& SAVE_INLINE_GPRS
)
23150 || !(strategy
& SAVE_INLINE_VRS
)));
23151 int ptr_regno
= -1;
23152 rtx ptr_reg
= NULL_RTX
;
23155 if (info
->total_size
< 32767)
23156 frame_off
= info
->total_size
;
23159 else if (info
->cr_save_p
23161 || info
->first_fp_reg_save
< 64
23162 || info
->first_gp_reg_save
< 32
23163 || info
->altivec_size
!= 0
23164 || info
->vrsave_mask
!= 0
23165 || crtl
->calls_eh_return
)
23169 /* The prologue won't be saving any regs so there is no need
23170 to set up a frame register to access any frame save area.
23171 We also won't be using frame_off anywhere below, but set
23172 the correct value anyway to protect against future
23173 changes to this function. */
23174 frame_off
= info
->total_size
;
23176 if (ptr_regno
!= -1)
23178 /* Set up the frame offset to that needed by the first
23179 out-of-line save function. */
23180 START_USE (ptr_regno
);
23181 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23182 frame_reg_rtx
= ptr_reg
;
23183 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
23184 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
23185 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
23186 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
23187 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
23188 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23189 frame_off
= -ptr_off
;
23191 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23192 sp_off
= info
->total_size
;
23193 if (frame_reg_rtx
!= sp_reg_rtx
)
23194 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23197 /* If we use the link register, get it into r0. */
23198 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
23200 rtx addr
, reg
, mem
;
23202 reg
= gen_rtx_REG (Pmode
, 0);
23204 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23205 RTX_FRAME_RELATED_P (insn
) = 1;
23207 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
23208 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
23210 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23211 GEN_INT (info
->lr_save_offset
+ frame_off
));
23212 mem
= gen_rtx_MEM (Pmode
, addr
);
23213 /* This should not be of rs6000_sr_alias_set, because of
23214 __builtin_return_address. */
23216 insn
= emit_move_insn (mem
, reg
);
23217 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23218 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23223 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
23224 r12 will be needed by out-of-line gpr restore. */
23225 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23226 && !(strategy
& (SAVE_INLINE_GPRS
23227 | SAVE_NOINLINE_GPRS_SAVES_LR
))
23229 if (!WORLD_SAVE_P (info
)
23231 && REGNO (frame_reg_rtx
) != cr_save_regno
23232 && !(using_static_chain_p
&& cr_save_regno
== 11))
23234 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
23235 START_USE (cr_save_regno
);
23236 rs6000_emit_move_from_cr (cr_save_rtx
);
23239 /* Do any required saving of fpr's. If only one or two to save, do
23240 it ourselves. Otherwise, call function. */
23241 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
23244 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23245 if (save_reg_p (info
->first_fp_reg_save
+ i
))
23246 emit_frame_save (frame_reg_rtx
,
23247 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23248 ? DFmode
: SFmode
),
23249 info
->first_fp_reg_save
+ i
,
23250 info
->fp_save_offset
+ frame_off
+ 8 * i
,
23251 sp_off
- frame_off
);
23253 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
23255 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23256 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23257 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23258 rtx ptr_reg
= frame_reg_rtx
;
23260 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23261 gcc_checking_assert (frame_off
== 0);
23264 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23265 NOT_INUSE (ptr_regno
);
23266 emit_insn (gen_add3_insn (ptr_reg
,
23267 frame_reg_rtx
, GEN_INT (frame_off
)));
23269 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23270 info
->fp_save_offset
,
23271 info
->lr_save_offset
,
23273 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
23274 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23279 /* Save GPRs. This is done as a PARALLEL if we are using
23280 the store-multiple instructions. */
23281 if (!WORLD_SAVE_P (info
)
23283 && info
->spe_64bit_regs_used
!= 0
23284 && info
->first_gp_reg_save
!= 32)
23287 rtx spe_save_area_ptr
;
23288 HOST_WIDE_INT save_off
;
23289 int ool_adjust
= 0;
23291 /* Determine whether we can address all of the registers that need
23292 to be saved with an offset from frame_reg_rtx that fits in
23293 the small const field for SPE memory instructions. */
23294 int spe_regs_addressable
23295 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23296 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23297 && (strategy
& SAVE_INLINE_GPRS
));
23299 if (spe_regs_addressable
)
23301 spe_save_area_ptr
= frame_reg_rtx
;
23302 save_off
= frame_off
;
23306 /* Make r11 point to the start of the SPE save area. We need
23307 to be careful here if r11 is holding the static chain. If
23308 it is, then temporarily save it in r0. */
23309 HOST_WIDE_INT offset
;
23311 if (!(strategy
& SAVE_INLINE_GPRS
))
23312 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23313 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
23314 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
23315 save_off
= frame_off
- offset
;
23317 if (using_static_chain_p
)
23319 rtx r0
= gen_rtx_REG (Pmode
, 0);
23322 gcc_assert (info
->first_gp_reg_save
> 11);
23324 emit_move_insn (r0
, spe_save_area_ptr
);
23326 else if (REGNO (frame_reg_rtx
) != 11)
23329 emit_insn (gen_addsi3 (spe_save_area_ptr
,
23330 frame_reg_rtx
, GEN_INT (offset
)));
23331 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
23332 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23335 if ((strategy
& SAVE_INLINE_GPRS
))
23337 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23338 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23339 emit_frame_save (spe_save_area_ptr
, reg_mode
,
23340 info
->first_gp_reg_save
+ i
,
23341 (info
->spe_gp_save_offset
+ save_off
23343 sp_off
- save_off
);
23347 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
23348 info
->spe_gp_save_offset
+ save_off
,
23350 SAVRES_SAVE
| SAVRES_GPR
);
23352 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
23353 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23356 /* Move the static chain pointer back. */
23357 if (!spe_regs_addressable
)
23359 if (using_static_chain_p
)
23361 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
23364 else if (REGNO (frame_reg_rtx
) != 11)
23368 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
23370 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
23371 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23372 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23373 rtx ptr_reg
= frame_reg_rtx
;
23374 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
23375 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23379 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23381 /* Need to adjust r11 (r12) if we saved any FPRs. */
23382 if (end_save
+ frame_off
!= 0)
23384 rtx offset
= GEN_INT (end_save
+ frame_off
);
23387 frame_off
= -end_save
;
23389 NOT_INUSE (ptr_regno
);
23390 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23392 else if (!ptr_set_up
)
23394 NOT_INUSE (ptr_regno
);
23395 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23397 ptr_off
= -end_save
;
23398 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23399 info
->gp_save_offset
+ ptr_off
,
23400 info
->lr_save_offset
+ ptr_off
,
23402 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
23403 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23407 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
23411 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23412 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23414 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23416 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23417 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23418 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23419 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23421 else if (!WORLD_SAVE_P (info
))
23424 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23425 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23426 emit_frame_save (frame_reg_rtx
, reg_mode
,
23427 info
->first_gp_reg_save
+ i
,
23428 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
23429 sp_off
- frame_off
);
23432 if (crtl
->calls_eh_return
)
23439 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23440 if (regno
== INVALID_REGNUM
)
23444 p
= rtvec_alloc (i
);
23448 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23449 if (regno
== INVALID_REGNUM
)
23453 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
23455 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
23456 RTVEC_ELT (p
, i
) = insn
;
23457 RTX_FRAME_RELATED_P (insn
) = 1;
23460 insn
= emit_insn (gen_blockage ());
23461 RTX_FRAME_RELATED_P (insn
) = 1;
23462 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
23465 /* In AIX ABI we need to make sure r2 is really saved. */
23466 if (TARGET_AIX
&& crtl
->calls_eh_return
)
23468 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
23469 rtx save_insn
, join_insn
, note
;
23470 long toc_restore_insn
;
23472 tmp_reg
= gen_rtx_REG (Pmode
, 11);
23473 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
23474 if (using_static_chain_p
)
23477 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
23481 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23482 /* Peek at instruction to which this function returns. If it's
23483 restoring r2, then we know we've already saved r2. We can't
23484 unconditionally save r2 because the value we have will already
23485 be updated if we arrived at this function via a plt call or
23486 toc adjusting stub. */
23487 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
23488 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
23489 + RS6000_TOC_SAVE_SLOT
);
23490 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
23491 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
23492 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
23493 validate_condition_mode (EQ
, CCUNSmode
);
23494 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
23495 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
23496 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
23497 toc_save_done
= gen_label_rtx ();
23498 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
23499 gen_rtx_EQ (VOIDmode
, compare_result
,
23501 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
23503 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
23504 JUMP_LABEL (jump
) = toc_save_done
;
23505 LABEL_NUSES (toc_save_done
) += 1;
23507 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
23508 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
23509 sp_off
- frame_off
);
23511 emit_label (toc_save_done
);
23513 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
23514 have a CFG that has different saves along different paths.
23515 Move the note to a dummy blockage insn, which describes that
23516 R2 is unconditionally saved after the label. */
23517 /* ??? An alternate representation might be a special insn pattern
23518 containing both the branch and the store. That might let the
23519 code that minimizes the number of DW_CFA_advance opcodes better
23520 freedom in placing the annotations. */
23521 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
23523 remove_note (save_insn
, note
);
23525 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
23526 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
23527 RTX_FRAME_RELATED_P (save_insn
) = 0;
23529 join_insn
= emit_insn (gen_blockage ());
23530 REG_NOTES (join_insn
) = note
;
23531 RTX_FRAME_RELATED_P (join_insn
) = 1;
23533 if (using_static_chain_p
)
23535 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
23542 /* Save CR if we use any that must be preserved. */
23543 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
23545 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23546 GEN_INT (info
->cr_save_offset
+ frame_off
));
23547 rtx mem
= gen_frame_mem (SImode
, addr
);
23549 /* If we didn't copy cr before, do so now using r0. */
23550 if (cr_save_rtx
== NULL_RTX
)
23553 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
23554 rs6000_emit_move_from_cr (cr_save_rtx
);
23557 /* Saving CR requires a two-instruction sequence: one instruction
23558 to move the CR to a general-purpose register, and a second
23559 instruction that stores the GPR to memory.
23561 We do not emit any DWARF CFI records for the first of these,
23562 because we cannot properly represent the fact that CR is saved in
23563 a register. One reason is that we cannot express that multiple
23564 CR fields are saved; another reason is that on 64-bit, the size
23565 of the CR register in DWARF (4 bytes) differs from the size of
23566 a general-purpose register.
23568 This means if any intervening instruction were to clobber one of
23569 the call-saved CR fields, we'd have incorrect CFI. To prevent
23570 this from happening, we mark the store to memory as a use of
23571 those CR fields, which prevents any such instruction from being
23572 scheduled in between the two instructions. */
23577 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
23578 for (i
= 0; i
< 8; i
++)
23579 if (save_reg_p (CR0_REGNO
+ i
))
23580 crsave_v
[n_crsave
++]
23581 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23583 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
23584 gen_rtvec_v (n_crsave
, crsave_v
)));
23585 END_USE (REGNO (cr_save_rtx
));
23587 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
23588 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
23589 so we need to construct a frame expression manually. */
23590 RTX_FRAME_RELATED_P (insn
) = 1;
23592 /* Update address to be stack-pointer relative, like
23593 rs6000_frame_related would do. */
23594 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
23595 GEN_INT (info
->cr_save_offset
+ sp_off
));
23596 mem
= gen_frame_mem (SImode
, addr
);
23598 if (DEFAULT_ABI
== ABI_ELFv2
)
23600 /* In the ELFv2 ABI we generate separate CFI records for each
23601 CR field that was actually saved. They all point to the
23602 same 32-bit stack slot. */
23606 for (i
= 0; i
< 8; i
++)
23607 if (save_reg_p (CR0_REGNO
+ i
))
23610 = gen_rtx_SET (VOIDmode
, mem
,
23611 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23613 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
23617 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23618 gen_rtx_PARALLEL (VOIDmode
,
23619 gen_rtvec_v (n_crframe
, crframe
)));
23623 /* In other ABIs, by convention, we use a single CR regnum to
23624 represent the fact that all call-saved CR fields are saved.
23625 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
23626 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
23627 gen_rtx_REG (SImode
, CR2_REGNO
));
23628 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
23632 /* In the ELFv2 ABI we need to save all call-saved CR fields into
23633 *separate* slots if the routine calls __builtin_eh_return, so
23634 that they can be independently restored by the unwinder. */
23635 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23637 int i
, cr_off
= info
->ehcr_offset
;
23640 /* ??? We might get better performance by using multiple mfocrf
23642 crsave
= gen_rtx_REG (SImode
, 0);
23643 emit_insn (gen_movesi_from_cr (crsave
));
23645 for (i
= 0; i
< 8; i
++)
23646 if (!call_used_regs
[CR0_REGNO
+ i
])
23648 rtvec p
= rtvec_alloc (2);
23650 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
23652 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23654 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23656 RTX_FRAME_RELATED_P (insn
) = 1;
23657 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23658 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
23659 sp_reg_rtx
, cr_off
+ sp_off
));
23661 cr_off
+= reg_size
;
23665 /* Update stack and set back pointer unless this is V.4,
23666 for which it was done previously. */
23667 if (!WORLD_SAVE_P (info
) && info
->push_p
23668 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
23670 rtx ptr_reg
= NULL
;
23673 /* If saving altivec regs we need to be able to address all save
23674 locations using a 16-bit offset. */
23675 if ((strategy
& SAVE_INLINE_VRS
) == 0
23676 || (info
->altivec_size
!= 0
23677 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
23678 + info
->total_size
- frame_off
) > 32767)
23679 || (info
->vrsave_size
!= 0
23680 && (info
->vrsave_save_offset
23681 + info
->total_size
- frame_off
) > 32767))
23683 int sel
= SAVRES_SAVE
| SAVRES_VR
;
23684 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23686 if (using_static_chain_p
23687 && ptr_regno
== STATIC_CHAIN_REGNUM
)
23689 if (REGNO (frame_reg_rtx
) != ptr_regno
)
23690 START_USE (ptr_regno
);
23691 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23692 frame_reg_rtx
= ptr_reg
;
23693 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23694 frame_off
= -ptr_off
;
23696 else if (REGNO (frame_reg_rtx
) == 1)
23697 frame_off
= info
->total_size
;
23698 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23699 sp_off
= info
->total_size
;
23700 if (frame_reg_rtx
!= sp_reg_rtx
)
23701 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23704 /* Set frame pointer, if needed. */
23705 if (frame_pointer_needed
)
23707 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
23709 RTX_FRAME_RELATED_P (insn
) = 1;
23712 /* Save AltiVec registers if needed. Save here because the red zone does
23713 not always include AltiVec registers. */
23714 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23715 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
23717 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23719 /* Oddly, the vector save/restore functions point r0 at the end
23720 of the save area, then use r11 or r12 to load offsets for
23721 [reg+reg] addressing. */
23722 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23723 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
23724 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23726 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23728 if (end_save
+ frame_off
!= 0)
23730 rtx offset
= GEN_INT (end_save
+ frame_off
);
23732 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23735 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23737 ptr_off
= -end_save
;
23738 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23739 info
->altivec_save_offset
+ ptr_off
,
23740 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
23741 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
23742 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23743 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23745 /* The oddity mentioned above clobbered our frame reg. */
23746 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23747 frame_off
= ptr_off
;
23750 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23751 && info
->altivec_size
!= 0)
23755 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23756 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23758 rtx areg
, savereg
, mem
, split_reg
;
23761 offset
= (info
->altivec_save_offset
+ frame_off
23762 + 16 * (i
- info
->first_altivec_reg_save
));
23764 savereg
= gen_rtx_REG (V4SImode
, i
);
23767 areg
= gen_rtx_REG (Pmode
, 0);
23768 emit_move_insn (areg
, GEN_INT (offset
));
23770 /* AltiVec addressing mode is [reg+reg]. */
23771 mem
= gen_frame_mem (V4SImode
,
23772 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
23774 insn
= emit_move_insn (mem
, savereg
);
23776 /* When we split a VSX store into two insns, we need to make
23777 sure the DWARF info knows which register we are storing.
23778 Pass it in to be used on the appropriate note. */
23779 if (!BYTES_BIG_ENDIAN
23780 && GET_CODE (PATTERN (insn
)) == SET
23781 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
23782 split_reg
= savereg
;
23784 split_reg
= NULL_RTX
;
23786 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23787 areg
, GEN_INT (offset
), split_reg
);
23791 /* VRSAVE is a bit vector representing which AltiVec registers
23792 are used. The OS uses this to determine which vector
23793 registers to save on a context switch. We need to save
23794 VRSAVE on the stack frame, add whatever AltiVec registers we
23795 used in this function, and do the corresponding magic in the
23798 if (!WORLD_SAVE_P (info
)
23800 && TARGET_ALTIVEC_VRSAVE
23801 && info
->vrsave_mask
!= 0)
23807 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
23808 be using r12 as frame_reg_rtx and r11 as the static chain
23809 pointer for nested functions. */
23811 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23812 && !using_static_chain_p
)
23814 else if (REGNO (frame_reg_rtx
) == 12)
23817 if (using_static_chain_p
)
23821 NOT_INUSE (save_regno
);
23822 reg
= gen_rtx_REG (SImode
, save_regno
);
23823 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
23825 emit_insn (gen_get_vrsave_internal (reg
));
23827 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
23830 offset
= info
->vrsave_save_offset
+ frame_off
;
23831 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
23833 /* Include the registers in the mask. */
23834 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
23836 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
23839 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
23840 if (!TARGET_SINGLE_PIC_BASE
23841 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23842 || (DEFAULT_ABI
== ABI_V4
23843 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
23844 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
23846 /* If emit_load_toc_table will use the link register, we need to save
23847 it. We use R12 for this purpose because emit_load_toc_table
23848 can use register 0. This allows us to use a plain 'blr' to return
23849 from the procedure more often. */
23850 int save_LR_around_toc_setup
= (TARGET_ELF
23851 && DEFAULT_ABI
== ABI_V4
23853 && ! info
->lr_save_p
23854 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
23855 if (save_LR_around_toc_setup
)
23857 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23858 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23860 insn
= emit_move_insn (tmp
, lr
);
23861 RTX_FRAME_RELATED_P (insn
) = 1;
23863 rs6000_emit_load_toc_table (TRUE
);
23865 insn
= emit_move_insn (lr
, tmp
);
23866 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23867 RTX_FRAME_RELATED_P (insn
) = 1;
23870 rs6000_emit_load_toc_table (TRUE
);
23874 if (!TARGET_SINGLE_PIC_BASE
23875 && DEFAULT_ABI
== ABI_DARWIN
23876 && flag_pic
&& crtl
->uses_pic_offset_table
)
23878 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23879 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
23881 /* Save and restore LR locally around this call (in R0). */
23882 if (!info
->lr_save_p
)
23883 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
23885 emit_insn (gen_load_macho_picbase (src
));
23887 emit_move_insn (gen_rtx_REG (Pmode
,
23888 RS6000_PIC_OFFSET_TABLE_REGNUM
),
23891 if (!info
->lr_save_p
)
23892 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
23896 /* If we need to, save the TOC register after doing the stack setup.
23897 Do not emit eh frame info for this save. The unwinder wants info,
23898 conceptually attached to instructions in this function, about
23899 register values in the caller of this function. This R2 may have
23900 already been changed from the value in the caller.
23901 We don't attempt to write accurate DWARF EH frame info for R2
23902 because code emitted by gcc for a (non-pointer) function call
23903 doesn't save and restore R2. Instead, R2 is managed out-of-line
23904 by a linker generated plt call stub when the function resides in
23905 a shared library. This behaviour is costly to describe in DWARF,
23906 both in terms of the size of DWARF info and the time taken in the
23907 unwinder to interpret it. R2 changes, apart from the
23908 calls_eh_return case earlier in this function, are handled by
23909 linux-unwind.h frob_update_context. */
23910 if (rs6000_save_toc_in_prologue_p ())
23912 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23913 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23917 /* Write function prologue. */
23920 rs6000_output_function_prologue (FILE *file
,
23921 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23923 rs6000_stack_t
*info
= rs6000_stack_info ();
23925 if (TARGET_DEBUG_STACK
)
23926 debug_stack_info (info
);
23928 /* Write .extern for any function we will call to save and restore
23930 if (info
->first_fp_reg_save
< 64
23935 int regno
= info
->first_fp_reg_save
- 32;
23937 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23939 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23940 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23941 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23942 fprintf (file
, "\t.extern %s\n", name
);
23944 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23946 bool lr
= (info
->savres_strategy
23947 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23948 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23949 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23950 fprintf (file
, "\t.extern %s\n", name
);
23954 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23955 immediately after the global entry point label. */
23956 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23958 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23960 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23961 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23963 fputs ("\t.localentry\t", file
);
23964 assemble_name (file
, name
);
23965 fputs (",.-", file
);
23966 assemble_name (file
, name
);
23967 fputs ("\n", file
);
23970 /* Output -mprofile-kernel code. This needs to be done here instead of
23971 in output_function_profile since it must go after the ELFv2 ABI
23972 local entry point. */
23973 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
23975 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23976 gcc_assert (!TARGET_32BIT
);
23978 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23979 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23981 /* In the ELFv2 ABI we have no compiler stack word. It must be
23982 the resposibility of _mcount to preserve the static chain
23983 register if required. */
23984 if (DEFAULT_ABI
!= ABI_ELFv2
23985 && cfun
->static_chain_decl
!= NULL
)
23987 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23988 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23989 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23990 asm_fprintf (file
, "\tld %s,24(%s)\n",
23991 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23994 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23997 rs6000_pic_labelno
++;
24000 /* Non-zero if vmx regs are restored before the frame pop, zero if
24001 we restore after the pop when possible. */
24002 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
24004 /* Restoring cr is a two step process: loading a reg from the frame
24005 save, then moving the reg to cr. For ABI_V4 we must let the
24006 unwinder know that the stack location is no longer valid at or
24007 before the stack deallocation, but we can't emit a cfa_restore for
24008 cr at the stack deallocation like we do for other registers.
24009 The trouble is that it is possible for the move to cr to be
24010 scheduled after the stack deallocation. So say exactly where cr
24011 is located on each of the two insns. */
24014 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
24016 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
24017 rtx reg
= gen_rtx_REG (SImode
, regno
);
24018 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
24020 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
24022 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
24023 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
24025 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
24026 RTX_FRAME_RELATED_P (insn
) = 1;
24031 /* Reload CR from REG. */
24034 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
24039 if (using_mfcr_multiple
)
24041 for (i
= 0; i
< 8; i
++)
24042 if (save_reg_p (CR0_REGNO
+ i
))
24044 gcc_assert (count
);
24047 if (using_mfcr_multiple
&& count
> 1)
24053 p
= rtvec_alloc (count
);
24056 for (i
= 0; i
< 8; i
++)
24057 if (save_reg_p (CR0_REGNO
+ i
))
24059 rtvec r
= rtvec_alloc (2);
24060 RTVEC_ELT (r
, 0) = reg
;
24061 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
24062 RTVEC_ELT (p
, ndx
) =
24063 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
24064 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
24067 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24068 gcc_assert (ndx
== count
);
24070 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
24071 CR field separately. */
24072 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
24074 for (i
= 0; i
< 8; i
++)
24075 if (save_reg_p (CR0_REGNO
+ i
))
24076 add_reg_note (insn
, REG_CFA_RESTORE
,
24077 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24079 RTX_FRAME_RELATED_P (insn
) = 1;
24083 for (i
= 0; i
< 8; i
++)
24084 if (save_reg_p (CR0_REGNO
+ i
))
24086 rtx insn
= emit_insn (gen_movsi_to_cr_one
24087 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
24089 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
24090 CR field separately, attached to the insn that in fact
24091 restores this particular CR field. */
24092 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
24094 add_reg_note (insn
, REG_CFA_RESTORE
,
24095 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24097 RTX_FRAME_RELATED_P (insn
) = 1;
24101 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
24102 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
24103 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
24105 rtx_insn
*insn
= get_last_insn ();
24106 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
24108 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
24109 RTX_FRAME_RELATED_P (insn
) = 1;
24113 /* Like cr, the move to lr instruction can be scheduled after the
24114 stack deallocation, but unlike cr, its stack frame save is still
24115 valid. So we only need to emit the cfa_restore on the correct
24119 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
24121 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
24122 rtx reg
= gen_rtx_REG (Pmode
, regno
);
24124 emit_move_insn (reg
, mem
);
24128 restore_saved_lr (int regno
, bool exit_func
)
24130 rtx reg
= gen_rtx_REG (Pmode
, regno
);
24131 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
24132 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
24134 if (!exit_func
&& flag_shrink_wrap
)
24136 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
24137 RTX_FRAME_RELATED_P (insn
) = 1;
24142 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
24144 if (DEFAULT_ABI
== ABI_ELFv2
)
24147 for (i
= 0; i
< 8; i
++)
24148 if (save_reg_p (CR0_REGNO
+ i
))
24150 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
24151 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
24155 else if (info
->cr_save_p
)
24156 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24157 gen_rtx_REG (SImode
, CR2_REGNO
),
24160 if (info
->lr_save_p
)
24161 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24162 gen_rtx_REG (Pmode
, LR_REGNO
),
24164 return cfa_restores
;
24167 /* Return true if OFFSET from stack pointer can be clobbered by signals.
24168 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
24169 below stack pointer not cloberred by signals. */
24172 offset_below_red_zone_p (HOST_WIDE_INT offset
)
24174 return offset
< (DEFAULT_ABI
== ABI_V4
24176 : TARGET_32BIT
? -220 : -288);
24179 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
24182 emit_cfa_restores (rtx cfa_restores
)
24184 rtx_insn
*insn
= get_last_insn ();
24185 rtx
*loc
= ®_NOTES (insn
);
24188 loc
= &XEXP (*loc
, 1);
24189 *loc
= cfa_restores
;
24190 RTX_FRAME_RELATED_P (insn
) = 1;
24193 /* Emit function epilogue as insns. */
24196 rs6000_emit_epilogue (int sibcall
)
24198 rs6000_stack_t
*info
;
24199 int restoring_GPRs_inline
;
24200 int restoring_FPRs_inline
;
24201 int using_load_multiple
;
24202 int using_mtcr_multiple
;
24203 int use_backchain_to_restore_sp
;
24206 HOST_WIDE_INT frame_off
= 0;
24207 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
24208 rtx frame_reg_rtx
= sp_reg_rtx
;
24209 rtx cfa_restores
= NULL_RTX
;
24211 rtx cr_save_reg
= NULL_RTX
;
24212 enum machine_mode reg_mode
= Pmode
;
24213 int reg_size
= TARGET_32BIT
? 4 : 8;
24216 unsigned ptr_regno
;
24218 info
= rs6000_stack_info ();
24220 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
24222 reg_mode
= V2SImode
;
24226 strategy
= info
->savres_strategy
;
24227 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
24228 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
24229 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
24230 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
24231 || rs6000_cpu
== PROCESSOR_PPC603
24232 || rs6000_cpu
== PROCESSOR_PPC750
24234 /* Restore via the backchain when we have a large frame, since this
24235 is more efficient than an addis, addi pair. The second condition
24236 here will not trigger at the moment; We don't actually need a
24237 frame pointer for alloca, but the generic parts of the compiler
24238 give us one anyway. */
24239 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
24240 || (cfun
->calls_alloca
24241 && !frame_pointer_needed
));
24242 restore_lr
= (info
->lr_save_p
24243 && (restoring_FPRs_inline
24244 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
24245 && (restoring_GPRs_inline
24246 || info
->first_fp_reg_save
< 64));
24248 if (WORLD_SAVE_P (info
))
24252 const char *alloc_rname
;
24255 /* eh_rest_world_r10 will return to the location saved in the LR
24256 stack slot (which is not likely to be our caller.)
24257 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
24258 rest_world is similar, except any R10 parameter is ignored.
24259 The exception-handling stuff that was here in 2.95 is no
24260 longer necessary. */
24264 + 32 - info
->first_gp_reg_save
24265 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
24266 + 63 + 1 - info
->first_fp_reg_save
);
24268 strcpy (rname
, ((crtl
->calls_eh_return
) ?
24269 "*eh_rest_world_r10" : "*rest_world"));
24270 alloc_rname
= ggc_strdup (rname
);
24273 RTVEC_ELT (p
, j
++) = ret_rtx
;
24274 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
24275 gen_rtx_REG (Pmode
,
24278 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
24279 /* The instruction pattern requires a clobber here;
24280 it is shared with the restVEC helper. */
24282 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
24285 /* CR register traditionally saved as CR2. */
24286 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
24288 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
24289 if (flag_shrink_wrap
)
24291 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24292 gen_rtx_REG (Pmode
, LR_REGNO
),
24294 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24298 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24300 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24302 = gen_frame_load (reg
,
24303 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
24304 if (flag_shrink_wrap
)
24305 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24307 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
24309 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
24311 = gen_frame_load (reg
,
24312 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
24313 if (flag_shrink_wrap
)
24314 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24316 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
24318 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24319 ? DFmode
: SFmode
),
24320 info
->first_fp_reg_save
+ i
);
24322 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24323 if (flag_shrink_wrap
)
24324 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24327 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
24329 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
24331 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
24333 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
24335 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
24336 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24338 if (flag_shrink_wrap
)
24340 REG_NOTES (insn
) = cfa_restores
;
24341 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24342 RTX_FRAME_RELATED_P (insn
) = 1;
24347 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
24349 frame_off
= info
->total_size
;
24351 /* Restore AltiVec registers if we must do so before adjusting the
24353 if (TARGET_ALTIVEC_ABI
24354 && info
->altivec_size
!= 0
24355 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24356 || (DEFAULT_ABI
!= ABI_V4
24357 && offset_below_red_zone_p (info
->altivec_save_offset
))))
24360 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24362 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24363 if (use_backchain_to_restore_sp
)
24365 int frame_regno
= 11;
24367 if ((strategy
& REST_INLINE_VRS
) == 0)
24369 /* Of r11 and r12, select the one not clobbered by an
24370 out-of-line restore function for the frame register. */
24371 frame_regno
= 11 + 12 - scratch_regno
;
24373 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
24374 emit_move_insn (frame_reg_rtx
,
24375 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24378 else if (frame_pointer_needed
)
24379 frame_reg_rtx
= hard_frame_pointer_rtx
;
24381 if ((strategy
& REST_INLINE_VRS
) == 0)
24383 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24385 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24386 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24388 if (end_save
+ frame_off
!= 0)
24390 rtx offset
= GEN_INT (end_save
+ frame_off
);
24392 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24395 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24397 ptr_off
= -end_save
;
24398 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24399 info
->altivec_save_offset
+ ptr_off
,
24400 0, V4SImode
, SAVRES_VR
);
24404 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24405 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24407 rtx addr
, areg
, mem
, reg
;
24409 areg
= gen_rtx_REG (Pmode
, 0);
24411 (areg
, GEN_INT (info
->altivec_save_offset
24413 + 16 * (i
- info
->first_altivec_reg_save
)));
24415 /* AltiVec addressing mode is [reg+reg]. */
24416 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24417 mem
= gen_frame_mem (V4SImode
, addr
);
24419 reg
= gen_rtx_REG (V4SImode
, i
);
24420 emit_move_insn (reg
, mem
);
24424 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24425 if (((strategy
& REST_INLINE_VRS
) == 0
24426 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24427 && (flag_shrink_wrap
24428 || (offset_below_red_zone_p
24429 (info
->altivec_save_offset
24430 + 16 * (i
- info
->first_altivec_reg_save
)))))
24432 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24433 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24437 /* Restore VRSAVE if we must do so before adjusting the stack. */
24439 && TARGET_ALTIVEC_VRSAVE
24440 && info
->vrsave_mask
!= 0
24441 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24442 || (DEFAULT_ABI
!= ABI_V4
24443 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
24447 if (frame_reg_rtx
== sp_reg_rtx
)
24449 if (use_backchain_to_restore_sp
)
24451 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24452 emit_move_insn (frame_reg_rtx
,
24453 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24456 else if (frame_pointer_needed
)
24457 frame_reg_rtx
= hard_frame_pointer_rtx
;
24460 reg
= gen_rtx_REG (SImode
, 12);
24461 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24462 info
->vrsave_save_offset
+ frame_off
));
24464 emit_insn (generate_set_vrsave (reg
, info
, 1));
24468 /* If we have a large stack frame, restore the old stack pointer
24469 using the backchain. */
24470 if (use_backchain_to_restore_sp
)
24472 if (frame_reg_rtx
== sp_reg_rtx
)
24474 /* Under V.4, don't reset the stack pointer until after we're done
24475 loading the saved registers. */
24476 if (DEFAULT_ABI
== ABI_V4
)
24477 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24479 insn
= emit_move_insn (frame_reg_rtx
,
24480 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24483 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24484 && DEFAULT_ABI
== ABI_V4
)
24485 /* frame_reg_rtx has been set up by the altivec restore. */
24489 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
24490 frame_reg_rtx
= sp_reg_rtx
;
24493 /* If we have a frame pointer, we can restore the old stack pointer
24495 else if (frame_pointer_needed
)
24497 frame_reg_rtx
= sp_reg_rtx
;
24498 if (DEFAULT_ABI
== ABI_V4
)
24499 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24500 /* Prevent reordering memory accesses against stack pointer restore. */
24501 else if (cfun
->calls_alloca
24502 || offset_below_red_zone_p (-info
->total_size
))
24503 rs6000_emit_stack_tie (frame_reg_rtx
, true);
24505 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
24506 GEN_INT (info
->total_size
)));
24509 else if (info
->push_p
24510 && DEFAULT_ABI
!= ABI_V4
24511 && !crtl
->calls_eh_return
)
24513 /* Prevent reordering memory accesses against stack pointer restore. */
24514 if (cfun
->calls_alloca
24515 || offset_below_red_zone_p (-info
->total_size
))
24516 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24517 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
24518 GEN_INT (info
->total_size
)));
24521 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
24525 REG_NOTES (insn
) = cfa_restores
;
24526 cfa_restores
= NULL_RTX
;
24528 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24529 RTX_FRAME_RELATED_P (insn
) = 1;
24532 /* Restore AltiVec registers if we have not done so already. */
24533 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24534 && TARGET_ALTIVEC_ABI
24535 && info
->altivec_size
!= 0
24536 && (DEFAULT_ABI
== ABI_V4
24537 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
24541 if ((strategy
& REST_INLINE_VRS
) == 0)
24543 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24545 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24546 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24547 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24549 if (end_save
+ frame_off
!= 0)
24551 rtx offset
= GEN_INT (end_save
+ frame_off
);
24553 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24556 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24558 ptr_off
= -end_save
;
24559 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24560 info
->altivec_save_offset
+ ptr_off
,
24561 0, V4SImode
, SAVRES_VR
);
24562 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
24564 /* Frame reg was clobbered by out-of-line save. Restore it
24565 from ptr_reg, and if we are calling out-of-line gpr or
24566 fpr restore set up the correct pointer and offset. */
24567 unsigned newptr_regno
= 1;
24568 if (!restoring_GPRs_inline
)
24570 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24571 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24572 newptr_regno
= ptr_regno_for_savres (sel
);
24573 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24575 else if (!restoring_FPRs_inline
)
24577 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
24578 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24579 newptr_regno
= ptr_regno_for_savres (sel
);
24580 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24583 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
24584 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
24586 if (end_save
+ ptr_off
!= 0)
24588 rtx offset
= GEN_INT (end_save
+ ptr_off
);
24590 frame_off
= -end_save
;
24591 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
24595 frame_off
= ptr_off
;
24596 emit_move_insn (frame_reg_rtx
, ptr_reg
);
24602 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24603 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24605 rtx addr
, areg
, mem
, reg
;
24607 areg
= gen_rtx_REG (Pmode
, 0);
24609 (areg
, GEN_INT (info
->altivec_save_offset
24611 + 16 * (i
- info
->first_altivec_reg_save
)));
24613 /* AltiVec addressing mode is [reg+reg]. */
24614 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24615 mem
= gen_frame_mem (V4SImode
, addr
);
24617 reg
= gen_rtx_REG (V4SImode
, i
);
24618 emit_move_insn (reg
, mem
);
24622 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24623 if (((strategy
& REST_INLINE_VRS
) == 0
24624 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24625 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
24627 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24628 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24632 /* Restore VRSAVE if we have not done so already. */
24633 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24635 && TARGET_ALTIVEC_VRSAVE
24636 && info
->vrsave_mask
!= 0
24637 && (DEFAULT_ABI
== ABI_V4
24638 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
24642 reg
= gen_rtx_REG (SImode
, 12);
24643 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24644 info
->vrsave_save_offset
+ frame_off
));
24646 emit_insn (generate_set_vrsave (reg
, info
, 1));
24649 /* If we exit by an out-of-line restore function on ABI_V4 then that
24650 function will deallocate the stack, so we don't need to worry
24651 about the unwinder restoring cr from an invalid stack frame
24653 exit_func
= (!restoring_FPRs_inline
24654 || (!restoring_GPRs_inline
24655 && info
->first_fp_reg_save
== 64));
24657 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
24658 *separate* slots if the routine calls __builtin_eh_return, so
24659 that they can be independently restored by the unwinder. */
24660 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24662 int i
, cr_off
= info
->ehcr_offset
;
24664 for (i
= 0; i
< 8; i
++)
24665 if (!call_used_regs
[CR0_REGNO
+ i
])
24667 rtx reg
= gen_rtx_REG (SImode
, 0);
24668 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24669 cr_off
+ frame_off
));
24671 insn
= emit_insn (gen_movsi_to_cr_one
24672 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
24674 if (!exit_func
&& flag_shrink_wrap
)
24676 add_reg_note (insn
, REG_CFA_RESTORE
,
24677 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24679 RTX_FRAME_RELATED_P (insn
) = 1;
24682 cr_off
+= reg_size
;
24686 /* Get the old lr if we saved it. If we are restoring registers
24687 out-of-line, then the out-of-line routines can do this for us. */
24688 if (restore_lr
&& restoring_GPRs_inline
)
24689 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24691 /* Get the old cr if we saved it. */
24692 if (info
->cr_save_p
)
24694 unsigned cr_save_regno
= 12;
24696 if (!restoring_GPRs_inline
)
24698 /* Ensure we don't use the register used by the out-of-line
24699 gpr register restore below. */
24700 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24701 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24702 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
24704 if (gpr_ptr_regno
== 12)
24705 cr_save_regno
= 11;
24706 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
24708 else if (REGNO (frame_reg_rtx
) == 12)
24709 cr_save_regno
= 11;
24711 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
24712 info
->cr_save_offset
+ frame_off
,
24716 /* Set LR here to try to overlap restores below. */
24717 if (restore_lr
&& restoring_GPRs_inline
)
24718 restore_saved_lr (0, exit_func
);
24720 /* Load exception handler data registers, if needed. */
24721 if (crtl
->calls_eh_return
)
24723 unsigned int i
, regno
;
24727 rtx reg
= gen_rtx_REG (reg_mode
, 2);
24728 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24729 frame_off
+ RS6000_TOC_SAVE_SLOT
));
24736 regno
= EH_RETURN_DATA_REGNO (i
);
24737 if (regno
== INVALID_REGNUM
)
24740 /* Note: possible use of r0 here to address SPE regs. */
24741 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
24742 info
->ehrd_offset
+ frame_off
24743 + reg_size
* (int) i
);
24745 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
24749 /* Restore GPRs. This is done as a PARALLEL if we are using
24750 the load-multiple instructions. */
24752 && info
->spe_64bit_regs_used
24753 && info
->first_gp_reg_save
!= 32)
24755 /* Determine whether we can address all of the registers that need
24756 to be saved with an offset from frame_reg_rtx that fits in
24757 the small const field for SPE memory instructions. */
24758 int spe_regs_addressable
24759 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
24760 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
24761 && restoring_GPRs_inline
);
24763 if (!spe_regs_addressable
)
24765 int ool_adjust
= 0;
24766 rtx old_frame_reg_rtx
= frame_reg_rtx
;
24767 /* Make r11 point to the start of the SPE save area. We worried about
24768 not clobbering it when we were saving registers in the prologue.
24769 There's no need to worry here because the static chain is passed
24770 anew to every function. */
24772 if (!restoring_GPRs_inline
)
24773 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
24774 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24775 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
24776 GEN_INT (info
->spe_gp_save_offset
24779 /* Keep the invariant that frame_reg_rtx + frame_off points
24780 at the top of the stack frame. */
24781 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
24784 if (restoring_GPRs_inline
)
24786 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
24788 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24789 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24791 rtx offset
, addr
, mem
, reg
;
24793 /* We're doing all this to ensure that the immediate offset
24794 fits into the immediate field of 'evldd'. */
24795 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
24797 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
24798 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
24799 mem
= gen_rtx_MEM (V2SImode
, addr
);
24800 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24802 emit_move_insn (reg
, mem
);
24806 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
24807 info
->spe_gp_save_offset
+ frame_off
,
24808 info
->lr_save_offset
+ frame_off
,
24810 SAVRES_GPR
| SAVRES_LR
);
24812 else if (!restoring_GPRs_inline
)
24814 /* We are jumping to an out-of-line function. */
24816 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
24817 bool can_use_exit
= end_save
== 0;
24818 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
24821 /* Emit stack reset code if we need it. */
24822 ptr_regno
= ptr_regno_for_savres (sel
);
24823 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24825 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24826 else if (end_save
+ frame_off
!= 0)
24827 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
24828 GEN_INT (end_save
+ frame_off
)));
24829 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
24830 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24831 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24832 frame_off
= -end_save
;
24834 if (can_use_exit
&& info
->cr_save_p
)
24835 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
24837 ptr_off
= -end_save
;
24838 rs6000_emit_savres_rtx (info
, ptr_reg
,
24839 info
->gp_save_offset
+ ptr_off
,
24840 info
->lr_save_offset
+ ptr_off
,
24843 else if (using_load_multiple
)
24846 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
24847 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24849 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24851 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24852 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24856 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24857 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24858 emit_insn (gen_frame_load
24859 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24861 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
24864 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24866 /* If the frame pointer was used then we can't delay emitting
24867 a REG_CFA_DEF_CFA note. This must happen on the insn that
24868 restores the frame pointer, r31. We may have already emitted
24869 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
24870 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
24871 be harmless if emitted. */
24872 if (frame_pointer_needed
)
24874 insn
= get_last_insn ();
24875 add_reg_note (insn
, REG_CFA_DEF_CFA
,
24876 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
24877 RTX_FRAME_RELATED_P (insn
) = 1;
24880 /* Set up cfa_restores. We always need these when
24881 shrink-wrapping. If not shrink-wrapping then we only need
24882 the cfa_restore when the stack location is no longer valid.
24883 The cfa_restores must be emitted on or before the insn that
24884 invalidates the stack, and of course must not be emitted
24885 before the insn that actually does the restore. The latter
24886 is why it is a bad idea to emit the cfa_restores as a group
24887 on the last instruction here that actually does a restore:
24888 That insn may be reordered with respect to others doing
24890 if (flag_shrink_wrap
24891 && !restoring_GPRs_inline
24892 && info
->first_fp_reg_save
== 64)
24893 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24895 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
24896 if (!restoring_GPRs_inline
24897 || using_load_multiple
24898 || rs6000_reg_live_or_pic_offset_p (i
))
24900 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24902 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24906 if (!restoring_GPRs_inline
24907 && info
->first_fp_reg_save
== 64)
24909 /* We are jumping to an out-of-line function. */
24911 emit_cfa_restores (cfa_restores
);
24915 if (restore_lr
&& !restoring_GPRs_inline
)
24917 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24918 restore_saved_lr (0, exit_func
);
24921 /* Restore fpr's if we need to do it without calling a function. */
24922 if (restoring_FPRs_inline
)
24923 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24924 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24926 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24927 ? DFmode
: SFmode
),
24928 info
->first_fp_reg_save
+ i
);
24929 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24930 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24931 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24932 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24935 /* If we saved cr, restore it here. Just those that were used. */
24936 if (info
->cr_save_p
)
24937 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24939 /* If this is V.4, unwind the stack pointer after all of the loads
24940 have been done, or set up r11 if we are restoring fp out of line. */
24942 if (!restoring_FPRs_inline
)
24944 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24945 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24946 ptr_regno
= ptr_regno_for_savres (sel
);
24949 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24950 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24953 if (insn
&& restoring_FPRs_inline
)
24957 REG_NOTES (insn
) = cfa_restores
;
24958 cfa_restores
= NULL_RTX
;
24960 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24961 RTX_FRAME_RELATED_P (insn
) = 1;
24964 if (crtl
->calls_eh_return
)
24966 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24967 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24973 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24974 if (! restoring_FPRs_inline
)
24976 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24977 RTVEC_ELT (p
, 0) = ret_rtx
;
24983 /* We can't hang the cfa_restores off a simple return,
24984 since the shrink-wrap code sometimes uses an existing
24985 return. This means there might be a path from
24986 pre-prologue code to this return, and dwarf2cfi code
24987 wants the eh_frame unwinder state to be the same on
24988 all paths to any point. So we need to emit the
24989 cfa_restores before the return. For -m64 we really
24990 don't need epilogue cfa_restores at all, except for
24991 this irritating dwarf2cfi with shrink-wrap
24992 requirement; The stack red-zone means eh_frame info
24993 from the prologue telling the unwinder to restore
24994 from the stack is perfectly good right to the end of
24996 emit_insn (gen_blockage ());
24997 emit_cfa_restores (cfa_restores
);
24998 cfa_restores
= NULL_RTX
;
25000 p
= rtvec_alloc (2);
25001 RTVEC_ELT (p
, 0) = simple_return_rtx
;
25004 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
25005 ? gen_rtx_USE (VOIDmode
,
25006 gen_rtx_REG (Pmode
, LR_REGNO
))
25007 : gen_rtx_CLOBBER (VOIDmode
,
25008 gen_rtx_REG (Pmode
, LR_REGNO
)));
25010 /* If we have to restore more than two FP registers, branch to the
25011 restore function. It will return to our caller. */
25012 if (! restoring_FPRs_inline
)
25018 if (flag_shrink_wrap
)
25019 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
25021 sym
= rs6000_savres_routine_sym (info
,
25022 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
25023 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
25024 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
25025 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
25027 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
25029 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
25031 RTVEC_ELT (p
, i
+ 4)
25032 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
25033 if (flag_shrink_wrap
)
25034 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
25039 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25045 /* Ensure the cfa_restores are hung off an insn that won't
25046 be reordered above other restores. */
25047 emit_insn (gen_blockage ());
25049 emit_cfa_restores (cfa_restores
);
25053 /* Write function epilogue. */
25056 rs6000_output_function_epilogue (FILE *file
,
25057 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
25060 macho_branch_islands ();
25061 /* Mach-O doesn't support labels at the end of objects, so if
25062 it looks like we might want one, insert a NOP. */
25064 rtx_insn
*insn
= get_last_insn ();
25065 rtx_insn
*deleted_debug_label
= NULL
;
25068 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
25070 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
25071 notes only, instead set their CODE_LABEL_NUMBER to -1,
25072 otherwise there would be code generation differences
25073 in between -g and -g0. */
25074 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
25075 deleted_debug_label
= insn
;
25076 insn
= PREV_INSN (insn
);
25081 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
25082 fputs ("\tnop\n", file
);
25083 else if (deleted_debug_label
)
25084 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
25085 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
25086 CODE_LABEL_NUMBER (insn
) = -1;
25090 /* Output a traceback table here. See /usr/include/sys/debug.h for info
25093 We don't output a traceback table if -finhibit-size-directive was
25094 used. The documentation for -finhibit-size-directive reads
25095 ``don't output a @code{.size} assembler directive, or anything
25096 else that would cause trouble if the function is split in the
25097 middle, and the two halves are placed at locations far apart in
25098 memory.'' The traceback table has this property, since it
25099 includes the offset from the start of the function to the
25100 traceback table itself.
25102 System V.4 Powerpc's (and the embedded ABI derived from it) use a
25103 different traceback table. */
25104 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25105 && ! flag_inhibit_size_directive
25106 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
25108 const char *fname
= NULL
;
25109 const char *language_string
= lang_hooks
.name
;
25110 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
25112 int optional_tbtab
;
25113 rs6000_stack_t
*info
= rs6000_stack_info ();
25115 if (rs6000_traceback
== traceback_full
)
25116 optional_tbtab
= 1;
25117 else if (rs6000_traceback
== traceback_part
)
25118 optional_tbtab
= 0;
25120 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
25122 if (optional_tbtab
)
25124 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
25125 while (*fname
== '.') /* V.4 encodes . in the name */
25128 /* Need label immediately before tbtab, so we can compute
25129 its offset from the function start. */
25130 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
25131 ASM_OUTPUT_LABEL (file
, fname
);
25134 /* The .tbtab pseudo-op can only be used for the first eight
25135 expressions, since it can't handle the possibly variable
25136 length fields that follow. However, if you omit the optional
25137 fields, the assembler outputs zeros for all optional fields
25138 anyways, giving each variable length field is minimum length
25139 (as defined in sys/debug.h). Thus we can not use the .tbtab
25140 pseudo-op at all. */
25142 /* An all-zero word flags the start of the tbtab, for debuggers
25143 that have to find it by searching forward from the entry
25144 point or from the current pc. */
25145 fputs ("\t.long 0\n", file
);
25147 /* Tbtab format type. Use format type 0. */
25148 fputs ("\t.byte 0,", file
);
25150 /* Language type. Unfortunately, there does not seem to be any
25151 official way to discover the language being compiled, so we
25152 use language_string.
25153 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
25154 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
25155 a number, so for now use 9. LTO and Go aren't assigned numbers
25156 either, so for now use 0. */
25157 if (! strcmp (language_string
, "GNU C")
25158 || ! strcmp (language_string
, "GNU GIMPLE")
25159 || ! strcmp (language_string
, "GNU Go"))
25161 else if (! strcmp (language_string
, "GNU F77")
25162 || ! strcmp (language_string
, "GNU Fortran"))
25164 else if (! strcmp (language_string
, "GNU Pascal"))
25166 else if (! strcmp (language_string
, "GNU Ada"))
25168 else if (! strcmp (language_string
, "GNU C++")
25169 || ! strcmp (language_string
, "GNU Objective-C++"))
25171 else if (! strcmp (language_string
, "GNU Java"))
25173 else if (! strcmp (language_string
, "GNU Objective-C"))
25176 gcc_unreachable ();
25177 fprintf (file
, "%d,", i
);
25179 /* 8 single bit fields: global linkage (not set for C extern linkage,
25180 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
25181 from start of procedure stored in tbtab, internal function, function
25182 has controlled storage, function has no toc, function uses fp,
25183 function logs/aborts fp operations. */
25184 /* Assume that fp operations are used if any fp reg must be saved. */
25185 fprintf (file
, "%d,",
25186 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
25188 /* 6 bitfields: function is interrupt handler, name present in
25189 proc table, function calls alloca, on condition directives
25190 (controls stack walks, 3 bits), saves condition reg, saves
25192 /* The `function calls alloca' bit seems to be set whenever reg 31 is
25193 set up as a frame pointer, even when there is no alloca call. */
25194 fprintf (file
, "%d,",
25195 ((optional_tbtab
<< 6)
25196 | ((optional_tbtab
& frame_pointer_needed
) << 5)
25197 | (info
->cr_save_p
<< 1)
25198 | (info
->lr_save_p
)));
25200 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
25202 fprintf (file
, "%d,",
25203 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
25205 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
25206 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
25208 if (optional_tbtab
)
25210 /* Compute the parameter info from the function decl argument
25213 int next_parm_info_bit
= 31;
25215 for (decl
= DECL_ARGUMENTS (current_function_decl
);
25216 decl
; decl
= DECL_CHAIN (decl
))
25218 rtx parameter
= DECL_INCOMING_RTL (decl
);
25219 enum machine_mode mode
= GET_MODE (parameter
);
25221 if (GET_CODE (parameter
) == REG
)
25223 if (SCALAR_FLOAT_MODE_P (mode
))
25244 gcc_unreachable ();
25247 /* If only one bit will fit, don't or in this entry. */
25248 if (next_parm_info_bit
> 0)
25249 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
25250 next_parm_info_bit
-= 2;
25254 fixed_parms
+= ((GET_MODE_SIZE (mode
)
25255 + (UNITS_PER_WORD
- 1))
25257 next_parm_info_bit
-= 1;
25263 /* Number of fixed point parameters. */
25264 /* This is actually the number of words of fixed point parameters; thus
25265 an 8 byte struct counts as 2; and thus the maximum value is 8. */
25266 fprintf (file
, "%d,", fixed_parms
);
25268 /* 2 bitfields: number of floating point parameters (7 bits), parameters
25270 /* This is actually the number of fp registers that hold parameters;
25271 and thus the maximum value is 13. */
25272 /* Set parameters on stack bit if parameters are not in their original
25273 registers, regardless of whether they are on the stack? Xlc
25274 seems to set the bit when not optimizing. */
25275 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
25277 if (! optional_tbtab
)
25280 /* Optional fields follow. Some are variable length. */
25282 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
25283 11 double float. */
25284 /* There is an entry for each parameter in a register, in the order that
25285 they occur in the parameter list. Any intervening arguments on the
25286 stack are ignored. If the list overflows a long (max possible length
25287 34 bits) then completely leave off all elements that don't fit. */
25288 /* Only emit this long if there was at least one parameter. */
25289 if (fixed_parms
|| float_parms
)
25290 fprintf (file
, "\t.long %d\n", parm_info
);
25292 /* Offset from start of code to tb table. */
25293 fputs ("\t.long ", file
);
25294 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
25295 RS6000_OUTPUT_BASENAME (file
, fname
);
25297 rs6000_output_function_entry (file
, fname
);
25300 /* Interrupt handler mask. */
25301 /* Omit this long, since we never set the interrupt handler bit
25304 /* Number of CTL (controlled storage) anchors. */
25305 /* Omit this long, since the has_ctl bit is never set above. */
25307 /* Displacement into stack of each CTL anchor. */
25308 /* Omit this list of longs, because there are no CTL anchors. */
25310 /* Length of function name. */
25313 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
25315 /* Function name. */
25316 assemble_string (fname
, strlen (fname
));
25318 /* Register for alloca automatic storage; this is always reg 31.
25319 Only emit this if the alloca bit was set above. */
25320 if (frame_pointer_needed
)
25321 fputs ("\t.byte 31\n", file
);
25323 fputs ("\t.align 2\n", file
);
25327 /* A C compound statement that outputs the assembler code for a thunk
25328 function, used to implement C++ virtual function calls with
25329 multiple inheritance. The thunk acts as a wrapper around a virtual
25330 function, adjusting the implicit object parameter before handing
25331 control off to the real function.
25333 First, emit code to add the integer DELTA to the location that
25334 contains the incoming first argument. Assume that this argument
25335 contains a pointer, and is the one used to pass the `this' pointer
25336 in C++. This is the incoming argument *before* the function
25337 prologue, e.g. `%o0' on a sparc. The addition must preserve the
25338 values of all other incoming arguments.
25340 After the addition, emit code to jump to FUNCTION, which is a
25341 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
25342 not touch the return address. Hence returning from FUNCTION will
25343 return to whoever called the current `thunk'.
25345 The effect must be as if FUNCTION had been called directly with the
25346 adjusted first argument. This macro is responsible for emitting
25347 all of the code for a thunk function; output_function_prologue()
25348 and output_function_epilogue() are not invoked.
25350 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
25351 been extracted from it.) It might possibly be useful on some
25352 targets, but probably not.
25354 If you do not define this macro, the target-independent code in the
25355 C++ frontend will generate a less efficient heavyweight thunk that
25356 calls FUNCTION instead of jumping to it. The generic approach does
25357 not support varargs. */
25360 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
25361 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
25364 rtx this_rtx
, funexp
;
25367 reload_completed
= 1;
25368 epilogue_completed
= 1;
25370 /* Mark the end of the (empty) prologue. */
25371 emit_note (NOTE_INSN_PROLOGUE_END
);
25373 /* Find the "this" pointer. If the function returns a structure,
25374 the structure return pointer is in r3. */
25375 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
25376 this_rtx
= gen_rtx_REG (Pmode
, 4);
25378 this_rtx
= gen_rtx_REG (Pmode
, 3);
25380 /* Apply the constant offset, if required. */
25382 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
25384 /* Apply the offset from the vtable, if required. */
25387 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
25388 rtx tmp
= gen_rtx_REG (Pmode
, 12);
25390 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
25391 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
25393 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
25394 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
25398 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
25400 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
25402 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
25405 /* Generate a tail call to the target function. */
25406 if (!TREE_USED (function
))
25408 assemble_external (function
);
25409 TREE_USED (function
) = 1;
25411 funexp
= XEXP (DECL_RTL (function
), 0);
25412 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
25415 if (MACHOPIC_INDIRECT
)
25416 funexp
= machopic_indirect_call_target (funexp
);
25419 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
25420 generate sibcall RTL explicitly. */
25421 insn
= emit_call_insn (
25422 gen_rtx_PARALLEL (VOIDmode
,
25424 gen_rtx_CALL (VOIDmode
,
25425 funexp
, const0_rtx
),
25426 gen_rtx_USE (VOIDmode
, const0_rtx
),
25427 gen_rtx_USE (VOIDmode
,
25428 gen_rtx_REG (SImode
,
25430 simple_return_rtx
)));
25431 SIBLING_CALL_P (insn
) = 1;
25434 /* Ensure we have a global entry point for the thunk. ??? We could
25435 avoid that if the target routine doesn't need a global entry point,
25436 but we do not know whether this is the case at this point. */
25437 if (DEFAULT_ABI
== ABI_ELFv2
)
25438 cfun
->machine
->r2_setup_needed
= true;
25440 /* Run just enough of rest_of_compilation to get the insns emitted.
25441 There's not really enough bulk here to make other passes such as
25442 instruction scheduling worth while. Note that use_thunk calls
25443 assemble_start_function and assemble_end_function. */
25444 insn
= get_insns ();
25445 shorten_branches (insn
);
25446 final_start_function (insn
, file
, 1);
25447 final (insn
, file
, 1);
25448 final_end_function ();
25450 reload_completed
= 0;
25451 epilogue_completed
= 0;
25454 /* A quick summary of the various types of 'constant-pool tables'
25457 Target Flags Name One table per
25458 AIX (none) AIX TOC object file
25459 AIX -mfull-toc AIX TOC object file
25460 AIX -mminimal-toc AIX minimal TOC translation unit
25461 SVR4/EABI (none) SVR4 SDATA object file
25462 SVR4/EABI -fpic SVR4 pic object file
25463 SVR4/EABI -fPIC SVR4 PIC translation unit
25464 SVR4/EABI -mrelocatable EABI TOC function
25465 SVR4/EABI -maix AIX TOC object file
25466 SVR4/EABI -maix -mminimal-toc
25467 AIX minimal TOC translation unit
25469 Name Reg. Set by entries contains:
25470 made by addrs? fp? sum?
25472 AIX TOC 2 crt0 as Y option option
25473 AIX minimal TOC 30 prolog gcc Y Y option
25474 SVR4 SDATA 13 crt0 gcc N Y N
25475 SVR4 pic 30 prolog ld Y not yet N
25476 SVR4 PIC 30 prolog gcc Y option option
25477 EABI TOC 30 prolog gcc Y option option
25481 /* Hash functions for the hash table. */
25484 rs6000_hash_constant (rtx k
)
25486 enum rtx_code code
= GET_CODE (k
);
25487 enum machine_mode mode
= GET_MODE (k
);
25488 unsigned result
= (code
<< 3) ^ mode
;
25489 const char *format
;
25492 format
= GET_RTX_FORMAT (code
);
25493 flen
= strlen (format
);
25499 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
25501 case CONST_WIDE_INT
:
25504 flen
= CONST_WIDE_INT_NUNITS (k
);
25505 for (i
= 0; i
< flen
; i
++)
25506 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
25511 if (mode
!= VOIDmode
)
25512 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
25524 for (; fidx
< flen
; fidx
++)
25525 switch (format
[fidx
])
25530 const char *str
= XSTR (k
, fidx
);
25531 len
= strlen (str
);
25532 result
= result
* 613 + len
;
25533 for (i
= 0; i
< len
; i
++)
25534 result
= result
* 613 + (unsigned) str
[i
];
25539 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
25543 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
25546 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
25547 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
25551 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
25552 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
25559 gcc_unreachable ();
25566 toc_hash_function (const void *hash_entry
)
25568 const struct toc_hash_struct
*thc
=
25569 (const struct toc_hash_struct
*) hash_entry
;
25570 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
25573 /* Compare H1 and H2 for equivalence. */
25576 toc_hash_eq (const void *h1
, const void *h2
)
25578 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
25579 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
25581 if (((const struct toc_hash_struct
*) h1
)->key_mode
25582 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
25585 return rtx_equal_p (r1
, r2
);
25588 /* These are the names given by the C++ front-end to vtables, and
25589 vtable-like objects. Ideally, this logic should not be here;
25590 instead, there should be some programmatic way of inquiring as
25591 to whether or not an object is a vtable. */
25593 #define VTABLE_NAME_P(NAME) \
25594 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
25595 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
25596 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
25597 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
25598 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
25600 #ifdef NO_DOLLAR_IN_LABEL
25601 /* Return a GGC-allocated character string translating dollar signs in
25602 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
25605 rs6000_xcoff_strip_dollar (const char *name
)
25611 q
= (const char *) strchr (name
, '$');
25613 if (q
== 0 || q
== name
)
25616 len
= strlen (name
);
25617 strip
= XALLOCAVEC (char, len
+ 1);
25618 strcpy (strip
, name
);
25619 p
= strip
+ (q
- name
);
25623 p
= strchr (p
+ 1, '$');
25626 return ggc_alloc_string (strip
, len
);
25631 rs6000_output_symbol_ref (FILE *file
, rtx x
)
25633 /* Currently C++ toc references to vtables can be emitted before it
25634 is decided whether the vtable is public or private. If this is
25635 the case, then the linker will eventually complain that there is
25636 a reference to an unknown section. Thus, for vtables only,
25637 we emit the TOC reference to reference the symbol and not the
25639 const char *name
= XSTR (x
, 0);
25641 if (VTABLE_NAME_P (name
))
25643 RS6000_OUTPUT_BASENAME (file
, name
);
25646 assemble_name (file
, name
);
25649 /* Output a TOC entry. We derive the entry name from what is being
25653 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
25656 const char *name
= buf
;
25658 HOST_WIDE_INT offset
= 0;
25660 gcc_assert (!TARGET_NO_TOC
);
25662 /* When the linker won't eliminate them, don't output duplicate
25663 TOC entries (this happens on AIX if there is any kind of TOC,
25664 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
25666 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
25668 struct toc_hash_struct
*h
;
25671 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
25672 time because GGC is not initialized at that point. */
25673 if (toc_hash_table
== NULL
)
25674 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
25675 toc_hash_eq
, NULL
);
25677 h
= ggc_alloc
<toc_hash_struct
> ();
25679 h
->key_mode
= mode
;
25680 h
->labelno
= labelno
;
25682 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
25683 if (*found
== NULL
)
25685 else /* This is indeed a duplicate.
25686 Set this label equal to that label. */
25688 fputs ("\t.set ", file
);
25689 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25690 fprintf (file
, "%d,", labelno
);
25691 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25692 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25696 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
25697 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
25698 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
25700 fputs ("\t.set ", file
);
25701 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25702 fprintf (file
, "%d,", labelno
);
25703 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25704 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25712 /* If we're going to put a double constant in the TOC, make sure it's
25713 aligned properly when strict alignment is on. */
25714 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
25715 && STRICT_ALIGNMENT
25716 && GET_MODE_BITSIZE (mode
) >= 64
25717 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
25718 ASM_OUTPUT_ALIGN (file
, 3);
25721 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
25723 /* Handle FP constants specially. Note that if we have a minimal
25724 TOC, things we put here aren't actually in the TOC, so we can allow
25726 if (GET_CODE (x
) == CONST_DOUBLE
&&
25727 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
25729 REAL_VALUE_TYPE rv
;
25732 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25733 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25734 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
25736 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
25740 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25741 fputs (DOUBLE_INT_ASM_OP
, file
);
25743 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25744 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25745 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25746 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
25747 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25748 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
25749 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
25750 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
25755 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25756 fputs ("\t.long ", file
);
25758 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25759 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25760 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25761 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
25762 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25763 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25767 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25768 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
25770 REAL_VALUE_TYPE rv
;
25773 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25775 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25776 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
25778 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
25782 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25783 fputs (DOUBLE_INT_ASM_OP
, file
);
25785 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25786 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25787 fprintf (file
, "0x%lx%08lx\n",
25788 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25789 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
25794 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25795 fputs ("\t.long ", file
);
25797 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25798 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25799 fprintf (file
, "0x%lx,0x%lx\n",
25800 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25804 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25805 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
25807 REAL_VALUE_TYPE rv
;
25810 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25811 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25812 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
25814 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
25818 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25819 fputs (DOUBLE_INT_ASM_OP
, file
);
25821 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25822 if (WORDS_BIG_ENDIAN
)
25823 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
25825 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25830 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25831 fputs ("\t.long ", file
);
25833 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25834 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25838 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
25840 unsigned HOST_WIDE_INT low
;
25841 HOST_WIDE_INT high
;
25843 low
= INTVAL (x
) & 0xffffffff;
25844 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
25846 /* TOC entries are always Pmode-sized, so when big-endian
25847 smaller integer constants in the TOC need to be padded.
25848 (This is still a win over putting the constants in
25849 a separate constant pool, because then we'd have
25850 to have both a TOC entry _and_ the actual constant.)
25852 For a 32-bit target, CONST_INT values are loaded and shifted
25853 entirely within `low' and can be stored in one TOC entry. */
25855 /* It would be easy to make this work, but it doesn't now. */
25856 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
25858 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
25861 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
25862 high
= (HOST_WIDE_INT
) low
>> 32;
25868 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25869 fputs (DOUBLE_INT_ASM_OP
, file
);
25871 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25872 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25873 fprintf (file
, "0x%lx%08lx\n",
25874 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25879 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
25881 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25882 fputs ("\t.long ", file
);
25884 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25885 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25886 fprintf (file
, "0x%lx,0x%lx\n",
25887 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25891 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25892 fputs ("\t.long ", file
);
25894 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
25895 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
25901 if (GET_CODE (x
) == CONST
)
25903 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25904 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25906 base
= XEXP (XEXP (x
, 0), 0);
25907 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25910 switch (GET_CODE (base
))
25913 name
= XSTR (base
, 0);
25917 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25918 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25922 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25926 gcc_unreachable ();
25929 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25930 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25933 fputs ("\t.tc ", file
);
25934 RS6000_OUTPUT_BASENAME (file
, name
);
25937 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25939 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25941 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25942 after other TOC symbols, reducing overflow of small TOC access
25943 to [TC] symbols. */
25944 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25945 ? "[TE]," : "[TC],", file
);
25948 /* Currently C++ toc references to vtables can be emitted before it
25949 is decided whether the vtable is public or private. If this is
25950 the case, then the linker will eventually complain that there is
25951 a TOC reference to an unknown section. Thus, for vtables only,
25952 we emit the TOC reference to reference the symbol and not the
25954 if (VTABLE_NAME_P (name
))
25956 RS6000_OUTPUT_BASENAME (file
, name
);
25958 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25959 else if (offset
> 0)
25960 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25963 output_addr_const (file
, x
);
25966 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25967 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25969 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25970 fputs ("@le", file
);
25971 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25972 fputs ("@ie", file
);
25973 /* Use global-dynamic for local-dynamic. */
25974 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25975 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25978 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25979 fputs ("\t.tc .", file
);
25980 RS6000_OUTPUT_BASENAME (file
, name
);
25981 fputs ("[TC],", file
);
25982 output_addr_const (file
, x
);
25983 fputs ("@m", file
);
25991 /* Output an assembler pseudo-op to write an ASCII string of N characters
25992 starting at P to FILE.
25994 On the RS/6000, we have to do this using the .byte operation and
25995 write out special characters outside the quoted string.
25996 Also, the assembler is broken; very long strings are truncated,
25997 so we must artificially break them up early. */
26000 output_ascii (FILE *file
, const char *p
, int n
)
26003 int i
, count_string
;
26004 const char *for_string
= "\t.byte \"";
26005 const char *for_decimal
= "\t.byte ";
26006 const char *to_close
= NULL
;
26009 for (i
= 0; i
< n
; i
++)
26012 if (c
>= ' ' && c
< 0177)
26015 fputs (for_string
, file
);
26018 /* Write two quotes to get one. */
26026 for_decimal
= "\"\n\t.byte ";
26030 if (count_string
>= 512)
26032 fputs (to_close
, file
);
26034 for_string
= "\t.byte \"";
26035 for_decimal
= "\t.byte ";
26043 fputs (for_decimal
, file
);
26044 fprintf (file
, "%d", c
);
26046 for_string
= "\n\t.byte \"";
26047 for_decimal
= ", ";
26053 /* Now close the string if we have written one. Then end the line. */
26055 fputs (to_close
, file
);
26058 /* Generate a unique section name for FILENAME for a section type
26059 represented by SECTION_DESC. Output goes into BUF.
26061 SECTION_DESC can be any string, as long as it is different for each
26062 possible section type.
26064 We name the section in the same manner as xlc. The name begins with an
26065 underscore followed by the filename (after stripping any leading directory
26066 names) with the last period replaced by the string SECTION_DESC. If
26067 FILENAME does not contain a period, SECTION_DESC is appended to the end of
26071 rs6000_gen_section_name (char **buf
, const char *filename
,
26072 const char *section_desc
)
26074 const char *q
, *after_last_slash
, *last_period
= 0;
26078 after_last_slash
= filename
;
26079 for (q
= filename
; *q
; q
++)
26082 after_last_slash
= q
+ 1;
26083 else if (*q
== '.')
26087 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
26088 *buf
= (char *) xmalloc (len
);
26093 for (q
= after_last_slash
; *q
; q
++)
26095 if (q
== last_period
)
26097 strcpy (p
, section_desc
);
26098 p
+= strlen (section_desc
);
26102 else if (ISALNUM (*q
))
26106 if (last_period
== 0)
26107 strcpy (p
, section_desc
);
26112 /* Emit profile function. */
26115 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
26117 /* Non-standard profiling for kernels, which just saves LR then calls
26118 _mcount without worrying about arg saves. The idea is to change
26119 the function prologue as little as possible as it isn't easy to
26120 account for arg save/restore code added just for _mcount. */
26121 if (TARGET_PROFILE_KERNEL
)
26124 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26126 #ifndef NO_PROFILE_COUNTERS
26127 # define NO_PROFILE_COUNTERS 0
26129 if (NO_PROFILE_COUNTERS
)
26130 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
26131 LCT_NORMAL
, VOIDmode
, 0);
26135 const char *label_name
;
26138 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
26139 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
26140 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
26142 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
26143 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
26146 else if (DEFAULT_ABI
== ABI_DARWIN
)
26148 const char *mcount_name
= RS6000_MCOUNT
;
26149 int caller_addr_regno
= LR_REGNO
;
26151 /* Be conservative and always set this, at least for now. */
26152 crtl
->uses_pic_offset_table
= 1;
26155 /* For PIC code, set up a stub and collect the caller's address
26156 from r0, which is where the prologue puts it. */
26157 if (MACHOPIC_INDIRECT
26158 && crtl
->uses_pic_offset_table
)
26159 caller_addr_regno
= 0;
26161 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
26162 LCT_NORMAL
, VOIDmode
, 1,
26163 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
26167 /* Write function profiler code. */
26170 output_function_profiler (FILE *file
, int labelno
)
26174 switch (DEFAULT_ABI
)
26177 gcc_unreachable ();
26182 warning (0, "no profiling of 64-bit code for this ABI");
26185 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
26186 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
26187 if (NO_PROFILE_COUNTERS
)
26189 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26190 reg_names
[0], reg_names
[1]);
26192 else if (TARGET_SECURE_PLT
&& flag_pic
)
26194 if (TARGET_LINK_STACK
)
26197 get_ppc476_thunk_name (name
);
26198 asm_fprintf (file
, "\tbl %s\n", name
);
26201 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
26202 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26203 reg_names
[0], reg_names
[1]);
26204 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26205 asm_fprintf (file
, "\taddis %s,%s,",
26206 reg_names
[12], reg_names
[12]);
26207 assemble_name (file
, buf
);
26208 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
26209 assemble_name (file
, buf
);
26210 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
26212 else if (flag_pic
== 1)
26214 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
26215 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26216 reg_names
[0], reg_names
[1]);
26217 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26218 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
26219 assemble_name (file
, buf
);
26220 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
26222 else if (flag_pic
> 1)
26224 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26225 reg_names
[0], reg_names
[1]);
26226 /* Now, we need to get the address of the label. */
26227 if (TARGET_LINK_STACK
)
26230 get_ppc476_thunk_name (name
);
26231 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
26232 assemble_name (file
, buf
);
26233 fputs ("-.\n1:", file
);
26234 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26235 asm_fprintf (file
, "\taddi %s,%s,4\n",
26236 reg_names
[11], reg_names
[11]);
26240 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
26241 assemble_name (file
, buf
);
26242 fputs ("-.\n1:", file
);
26243 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26245 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
26246 reg_names
[0], reg_names
[11]);
26247 asm_fprintf (file
, "\tadd %s,%s,%s\n",
26248 reg_names
[0], reg_names
[0], reg_names
[11]);
26252 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
26253 assemble_name (file
, buf
);
26254 fputs ("@ha\n", file
);
26255 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26256 reg_names
[0], reg_names
[1]);
26257 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
26258 assemble_name (file
, buf
);
26259 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
26262 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
26263 fprintf (file
, "\tbl %s%s\n",
26264 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
26270 /* Don't do anything, done in output_profile_hook (). */
26277 /* The following variable value is the last issued insn. */
26279 static rtx last_scheduled_insn
;
26281 /* The following variable helps to balance issuing of load and
26282 store instructions */
26284 static int load_store_pendulum
;
26286 /* Power4 load update and store update instructions are cracked into a
26287 load or store and an integer insn which are executed in the same cycle.
26288 Branches have their own dispatch slot which does not count against the
26289 GCC issue rate, but it changes the program flow so there are no other
26290 instructions to issue in this cycle. */
26293 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
26295 last_scheduled_insn
= insn
;
26296 if (GET_CODE (PATTERN (insn
)) == USE
26297 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26299 cached_can_issue_more
= more
;
26300 return cached_can_issue_more
;
26303 if (insn_terminates_group_p (insn
, current_group
))
26305 cached_can_issue_more
= 0;
26306 return cached_can_issue_more
;
26309 /* If no reservation, but reach here */
26310 if (recog_memoized (insn
) < 0)
26313 if (rs6000_sched_groups
)
26315 if (is_microcoded_insn (insn
))
26316 cached_can_issue_more
= 0;
26317 else if (is_cracked_insn (insn
))
26318 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
26320 cached_can_issue_more
= more
- 1;
26322 return cached_can_issue_more
;
26325 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
26328 cached_can_issue_more
= more
- 1;
26329 return cached_can_issue_more
;
26333 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
26335 int r
= rs6000_variable_issue_1 (insn
, more
);
26337 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
26341 /* Adjust the cost of a scheduling dependency. Return the new cost of
26342 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
26345 rs6000_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
26347 enum attr_type attr_type
;
26349 if (! recog_memoized (insn
))
26352 switch (REG_NOTE_KIND (link
))
26356 /* Data dependency; DEP_INSN writes a register that INSN reads
26357 some cycles later. */
26359 /* Separate a load from a narrower, dependent store. */
26360 if (rs6000_sched_groups
26361 && GET_CODE (PATTERN (insn
)) == SET
26362 && GET_CODE (PATTERN (dep_insn
)) == SET
26363 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
26364 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
26365 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
26366 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
26369 attr_type
= get_attr_type (insn
);
26374 /* Tell the first scheduling pass about the latency between
26375 a mtctr and bctr (and mtlr and br/blr). The first
26376 scheduling pass will not know about this latency since
26377 the mtctr instruction, which has the latency associated
26378 to it, will be generated by reload. */
26381 /* Leave some extra cycles between a compare and its
26382 dependent branch, to inhibit expensive mispredicts. */
26383 if ((rs6000_cpu_attr
== CPU_PPC603
26384 || rs6000_cpu_attr
== CPU_PPC604
26385 || rs6000_cpu_attr
== CPU_PPC604E
26386 || rs6000_cpu_attr
== CPU_PPC620
26387 || rs6000_cpu_attr
== CPU_PPC630
26388 || rs6000_cpu_attr
== CPU_PPC750
26389 || rs6000_cpu_attr
== CPU_PPC7400
26390 || rs6000_cpu_attr
== CPU_PPC7450
26391 || rs6000_cpu_attr
== CPU_PPCE5500
26392 || rs6000_cpu_attr
== CPU_PPCE6500
26393 || rs6000_cpu_attr
== CPU_POWER4
26394 || rs6000_cpu_attr
== CPU_POWER5
26395 || rs6000_cpu_attr
== CPU_POWER7
26396 || rs6000_cpu_attr
== CPU_POWER8
26397 || rs6000_cpu_attr
== CPU_CELL
)
26398 && recog_memoized (dep_insn
)
26399 && (INSN_CODE (dep_insn
) >= 0))
26401 switch (get_attr_type (dep_insn
))
26405 case TYPE_FPCOMPARE
:
26406 case TYPE_CR_LOGICAL
:
26407 case TYPE_DELAYED_CR
:
26411 if (get_attr_dot (dep_insn
) == DOT_YES
)
26416 if (get_attr_dot (dep_insn
) == DOT_YES
26417 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
26428 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26429 && recog_memoized (dep_insn
)
26430 && (INSN_CODE (dep_insn
) >= 0))
26433 if (GET_CODE (PATTERN (insn
)) != SET
)
26434 /* If this happens, we have to extend this to schedule
26435 optimally. Return default for now. */
26438 /* Adjust the cost for the case where the value written
26439 by a fixed point operation is used as the address
26440 gen value on a store. */
26441 switch (get_attr_type (dep_insn
))
26446 if (! store_data_bypass_p (dep_insn
, insn
))
26447 return get_attr_sign_extend (dep_insn
)
26448 == SIGN_EXTEND_YES
? 6 : 4;
26453 if (! store_data_bypass_p (dep_insn
, insn
))
26454 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
26465 if (! store_data_bypass_p (dep_insn
, insn
))
26473 if (get_attr_update (dep_insn
) == UPDATE_YES
26474 && ! store_data_bypass_p (dep_insn
, insn
))
26480 if (! store_data_bypass_p (dep_insn
, insn
))
26486 if (! store_data_bypass_p (dep_insn
, insn
))
26487 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
26497 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26498 && recog_memoized (dep_insn
)
26499 && (INSN_CODE (dep_insn
) >= 0))
26502 /* Adjust the cost for the case where the value written
26503 by a fixed point instruction is used within the address
26504 gen portion of a subsequent load(u)(x) */
26505 switch (get_attr_type (dep_insn
))
26510 if (set_to_load_agen (dep_insn
, insn
))
26511 return get_attr_sign_extend (dep_insn
)
26512 == SIGN_EXTEND_YES
? 6 : 4;
26517 if (set_to_load_agen (dep_insn
, insn
))
26518 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
26529 if (set_to_load_agen (dep_insn
, insn
))
26537 if (get_attr_update (dep_insn
) == UPDATE_YES
26538 && set_to_load_agen (dep_insn
, insn
))
26544 if (set_to_load_agen (dep_insn
, insn
))
26550 if (set_to_load_agen (dep_insn
, insn
))
26551 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
26561 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26562 && get_attr_update (insn
) == UPDATE_NO
26563 && recog_memoized (dep_insn
)
26564 && (INSN_CODE (dep_insn
) >= 0)
26565 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
26572 /* Fall out to return default cost. */
26576 case REG_DEP_OUTPUT
:
26577 /* Output dependency; DEP_INSN writes a register that INSN writes some
26579 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26580 && recog_memoized (dep_insn
)
26581 && (INSN_CODE (dep_insn
) >= 0))
26583 attr_type
= get_attr_type (insn
);
26588 if (get_attr_type (dep_insn
) == TYPE_FP
)
26592 if (get_attr_update (insn
) == UPDATE_NO
26593 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
26601 /* Anti dependency; DEP_INSN reads a register that INSN writes some
26606 gcc_unreachable ();
26612 /* Debug version of rs6000_adjust_cost. */
26615 rs6000_debug_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
,
26618 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
26624 switch (REG_NOTE_KIND (link
))
26626 default: dep
= "unknown depencency"; break;
26627 case REG_DEP_TRUE
: dep
= "data dependency"; break;
26628 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
26629 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
26633 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
26634 "%s, insn:\n", ret
, cost
, dep
);
26642 /* The function returns a true if INSN is microcoded.
26643 Return false otherwise. */
26646 is_microcoded_insn (rtx_insn
*insn
)
26648 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26649 || GET_CODE (PATTERN (insn
)) == USE
26650 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26653 if (rs6000_cpu_attr
== CPU_CELL
)
26654 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
26656 if (rs6000_sched_groups
26657 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26659 enum attr_type type
= get_attr_type (insn
);
26660 if ((type
== TYPE_LOAD
26661 && get_attr_update (insn
) == UPDATE_YES
26662 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
26663 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
26664 && get_attr_update (insn
) == UPDATE_YES
26665 && get_attr_indexed (insn
) == INDEXED_YES
)
26666 || type
== TYPE_MFCR
)
26673 /* The function returns true if INSN is cracked into 2 instructions
26674 by the processor (and therefore occupies 2 issue slots). */
26677 is_cracked_insn (rtx_insn
*insn
)
26679 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26680 || GET_CODE (PATTERN (insn
)) == USE
26681 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26684 if (rs6000_sched_groups
26685 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26687 enum attr_type type
= get_attr_type (insn
);
26688 if ((type
== TYPE_LOAD
26689 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
26690 && get_attr_update (insn
) == UPDATE_NO
)
26691 || (type
== TYPE_LOAD
26692 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
26693 && get_attr_update (insn
) == UPDATE_YES
26694 && get_attr_indexed (insn
) == INDEXED_NO
)
26695 || (type
== TYPE_STORE
26696 && get_attr_update (insn
) == UPDATE_YES
26697 && get_attr_indexed (insn
) == INDEXED_NO
)
26698 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
26699 && get_attr_update (insn
) == UPDATE_YES
)
26700 || type
== TYPE_DELAYED_CR
26701 || type
== TYPE_COMPARE
26702 || (type
== TYPE_EXTS
26703 && get_attr_dot (insn
) == DOT_YES
)
26704 || (type
== TYPE_SHIFT
26705 && get_attr_dot (insn
) == DOT_YES
26706 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
26707 || (type
== TYPE_MUL
26708 && get_attr_dot (insn
) == DOT_YES
)
26709 || type
== TYPE_DIV
26710 || (type
== TYPE_INSERT
26711 && get_attr_size (insn
) == SIZE_32
))
26718 /* The function returns true if INSN can be issued only from
26719 the branch slot. */
26722 is_branch_slot_insn (rtx_insn
*insn
)
26724 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26725 || GET_CODE (PATTERN (insn
)) == USE
26726 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26729 if (rs6000_sched_groups
)
26731 enum attr_type type
= get_attr_type (insn
);
26732 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
26740 /* The function returns true if out_inst sets a value that is
26741 used in the address generation computation of in_insn */
26743 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
26745 rtx out_set
, in_set
;
26747 /* For performance reasons, only handle the simple case where
26748 both loads are a single_set. */
26749 out_set
= single_set (out_insn
);
26752 in_set
= single_set (in_insn
);
26754 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
26760 /* Try to determine base/offset/size parts of the given MEM.
26761 Return true if successful, false if all the values couldn't
26764 This function only looks for REG or REG+CONST address forms.
26765 REG+REG address form will return false. */
26768 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
26769 HOST_WIDE_INT
*size
)
26772 if MEM_SIZE_KNOWN_P (mem
)
26773 *size
= MEM_SIZE (mem
);
26777 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
26778 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
26780 addr_rtx
= (XEXP (mem
, 0));
26782 if (GET_CODE (addr_rtx
) == REG
)
26787 else if (GET_CODE (addr_rtx
) == PLUS
26788 && CONST_INT_P (XEXP (addr_rtx
, 1)))
26790 *base
= XEXP (addr_rtx
, 0);
26791 *offset
= INTVAL (XEXP (addr_rtx
, 1));
26799 /* The function returns true if the target storage location of
26800 mem1 is adjacent to the target storage location of mem2 */
26801 /* Return 1 if memory locations are adjacent. */
26804 adjacent_mem_locations (rtx mem1
, rtx mem2
)
26807 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26809 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26810 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26811 return ((REGNO (reg1
) == REGNO (reg2
))
26812 && ((off1
+ size1
== off2
)
26813 || (off2
+ size2
== off1
)));
26818 /* This function returns true if it can be determined that the two MEM
26819 locations overlap by at least 1 byte based on base reg/offset/size. */
26822 mem_locations_overlap (rtx mem1
, rtx mem2
)
26825 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26827 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26828 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26829 return ((REGNO (reg1
) == REGNO (reg2
))
26830 && (((off1
<= off2
) && (off1
+ size1
> off2
))
26831 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
26836 /* A C statement (sans semicolon) to update the integer scheduling
26837 priority INSN_PRIORITY (INSN). Increase the priority to execute the
26838 INSN earlier, reduce the priority to execute INSN later. Do not
26839 define this macro if you do not need to adjust the scheduling
26840 priorities of insns. */
26843 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
26845 rtx load_mem
, str_mem
;
26846 /* On machines (like the 750) which have asymmetric integer units,
26847 where one integer unit can do multiply and divides and the other
26848 can't, reduce the priority of multiply/divide so it is scheduled
26849 before other integer operations. */
26852 if (! INSN_P (insn
))
26855 if (GET_CODE (PATTERN (insn
)) == USE
)
26858 switch (rs6000_cpu_attr
) {
26860 switch (get_attr_type (insn
))
26867 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
26868 priority
, priority
);
26869 if (priority
>= 0 && priority
< 0x01000000)
26876 if (insn_must_be_first_in_group (insn
)
26877 && reload_completed
26878 && current_sched_info
->sched_max_insns_priority
26879 && rs6000_sched_restricted_insns_priority
)
26882 /* Prioritize insns that can be dispatched only in the first
26884 if (rs6000_sched_restricted_insns_priority
== 1)
26885 /* Attach highest priority to insn. This means that in
26886 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
26887 precede 'priority' (critical path) considerations. */
26888 return current_sched_info
->sched_max_insns_priority
;
26889 else if (rs6000_sched_restricted_insns_priority
== 2)
26890 /* Increase priority of insn by a minimal amount. This means that in
26891 haifa-sched.c:ready_sort(), only 'priority' (critical path)
26892 considerations precede dispatch-slot restriction considerations. */
26893 return (priority
+ 1);
26896 if (rs6000_cpu
== PROCESSOR_POWER6
26897 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26898 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26899 /* Attach highest priority to insn if the scheduler has just issued two
26900 stores and this instruction is a load, or two loads and this instruction
26901 is a store. Power6 wants loads and stores scheduled alternately
26903 return current_sched_info
->sched_max_insns_priority
;
26908 /* Return true if the instruction is nonpipelined on the Cell. */
26910 is_nonpipeline_insn (rtx_insn
*insn
)
26912 enum attr_type type
;
26913 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26914 || GET_CODE (PATTERN (insn
)) == USE
26915 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26918 type
= get_attr_type (insn
);
26919 if (type
== TYPE_MUL
26920 || type
== TYPE_DIV
26921 || type
== TYPE_SDIV
26922 || type
== TYPE_DDIV
26923 || type
== TYPE_SSQRT
26924 || type
== TYPE_DSQRT
26925 || type
== TYPE_MFCR
26926 || type
== TYPE_MFCRF
26927 || type
== TYPE_MFJMPR
)
26935 /* Return how many instructions the machine can issue per cycle. */
26938 rs6000_issue_rate (void)
26940 /* Unless scheduling for register pressure, use issue rate of 1 for
26941 first scheduling pass to decrease degradation. */
26942 if (!reload_completed
&& !flag_sched_pressure
)
26945 switch (rs6000_cpu_attr
) {
26947 case CPU_PPC601
: /* ? */
26957 case CPU_PPCE300C2
:
26958 case CPU_PPCE300C3
:
26959 case CPU_PPCE500MC
:
26960 case CPU_PPCE500MC64
:
26983 /* Return how many instructions to look ahead for better insn
26987 rs6000_use_sched_lookahead (void)
26989 switch (rs6000_cpu_attr
)
26996 return (reload_completed
? 8 : 0);
27003 /* We are choosing insn from the ready queue. Return zero if INSN can be
27006 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
27008 if (ready_index
== 0)
27011 if (rs6000_cpu_attr
!= CPU_CELL
)
27014 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
27016 if (!reload_completed
27017 || is_nonpipeline_insn (insn
)
27018 || is_microcoded_insn (insn
))
27024 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
27025 and return true. */
27028 find_mem_ref (rtx pat
, rtx
*mem_ref
)
27033 /* stack_tie does not produce any real memory traffic. */
27034 if (tie_operand (pat
, VOIDmode
))
27037 if (GET_CODE (pat
) == MEM
)
27043 /* Recursively process the pattern. */
27044 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
27046 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
27050 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
27053 else if (fmt
[i
] == 'E')
27054 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
27056 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
27064 /* Determine if PAT is a PATTERN of a load insn. */
27067 is_load_insn1 (rtx pat
, rtx
*load_mem
)
27069 if (!pat
|| pat
== NULL_RTX
)
27072 if (GET_CODE (pat
) == SET
)
27073 return find_mem_ref (SET_SRC (pat
), load_mem
);
27075 if (GET_CODE (pat
) == PARALLEL
)
27079 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
27080 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
27087 /* Determine if INSN loads from memory. */
27090 is_load_insn (rtx insn
, rtx
*load_mem
)
27092 if (!insn
|| !INSN_P (insn
))
27098 return is_load_insn1 (PATTERN (insn
), load_mem
);
27101 /* Determine if PAT is a PATTERN of a store insn. */
27104 is_store_insn1 (rtx pat
, rtx
*str_mem
)
27106 if (!pat
|| pat
== NULL_RTX
)
27109 if (GET_CODE (pat
) == SET
)
27110 return find_mem_ref (SET_DEST (pat
), str_mem
);
27112 if (GET_CODE (pat
) == PARALLEL
)
27116 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
27117 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
27124 /* Determine if INSN stores to memory. */
27127 is_store_insn (rtx insn
, rtx
*str_mem
)
27129 if (!insn
|| !INSN_P (insn
))
27132 return is_store_insn1 (PATTERN (insn
), str_mem
);
27135 /* Returns whether the dependence between INSN and NEXT is considered
27136 costly by the given target. */
27139 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
27143 rtx load_mem
, str_mem
;
27145 /* If the flag is not enabled - no dependence is considered costly;
27146 allow all dependent insns in the same group.
27147 This is the most aggressive option. */
27148 if (rs6000_sched_costly_dep
== no_dep_costly
)
27151 /* If the flag is set to 1 - a dependence is always considered costly;
27152 do not allow dependent instructions in the same group.
27153 This is the most conservative option. */
27154 if (rs6000_sched_costly_dep
== all_deps_costly
)
27157 insn
= DEP_PRO (dep
);
27158 next
= DEP_CON (dep
);
27160 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
27161 && is_load_insn (next
, &load_mem
)
27162 && is_store_insn (insn
, &str_mem
))
27163 /* Prevent load after store in the same group. */
27166 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
27167 && is_load_insn (next
, &load_mem
)
27168 && is_store_insn (insn
, &str_mem
)
27169 && DEP_TYPE (dep
) == REG_DEP_TRUE
27170 && mem_locations_overlap(str_mem
, load_mem
))
27171 /* Prevent load after store in the same group if it is a true
27175 /* The flag is set to X; dependences with latency >= X are considered costly,
27176 and will not be scheduled in the same group. */
27177 if (rs6000_sched_costly_dep
<= max_dep_latency
27178 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
27184 /* Return the next insn after INSN that is found before TAIL is reached,
27185 skipping any "non-active" insns - insns that will not actually occupy
27186 an issue slot. Return NULL_RTX if such an insn is not found. */
27189 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
27191 if (insn
== NULL_RTX
|| insn
== tail
)
27196 insn
= NEXT_INSN (insn
);
27197 if (insn
== NULL_RTX
|| insn
== tail
)
27201 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
27202 || (NONJUMP_INSN_P (insn
)
27203 && GET_CODE (PATTERN (insn
)) != USE
27204 && GET_CODE (PATTERN (insn
)) != CLOBBER
27205 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
27211 /* We are about to begin issuing insns for this clock cycle. */
27214 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
27215 rtx_insn
**ready ATTRIBUTE_UNUSED
,
27216 int *pn_ready ATTRIBUTE_UNUSED
,
27217 int clock_var ATTRIBUTE_UNUSED
)
27219 int n_ready
= *pn_ready
;
27222 fprintf (dump
, "// rs6000_sched_reorder :\n");
27224 /* Reorder the ready list, if the second to last ready insn
27225 is a nonepipeline insn. */
27226 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
27228 if (is_nonpipeline_insn (ready
[n_ready
- 1])
27229 && (recog_memoized (ready
[n_ready
- 2]) > 0))
27230 /* Simply swap first two insns. */
27232 rtx_insn
*tmp
= ready
[n_ready
- 1];
27233 ready
[n_ready
- 1] = ready
[n_ready
- 2];
27234 ready
[n_ready
- 2] = tmp
;
27238 if (rs6000_cpu
== PROCESSOR_POWER6
)
27239 load_store_pendulum
= 0;
27241 return rs6000_issue_rate ();
27244 /* Like rs6000_sched_reorder, but called after issuing each insn. */
27247 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
27248 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
27251 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
27253 /* For Power6, we need to handle some special cases to try and keep the
27254 store queue from overflowing and triggering expensive flushes.
27256 This code monitors how load and store instructions are being issued
27257 and skews the ready list one way or the other to increase the likelihood
27258 that a desired instruction is issued at the proper time.
27260 A couple of things are done. First, we maintain a "load_store_pendulum"
27261 to track the current state of load/store issue.
27263 - If the pendulum is at zero, then no loads or stores have been
27264 issued in the current cycle so we do nothing.
27266 - If the pendulum is 1, then a single load has been issued in this
27267 cycle and we attempt to locate another load in the ready list to
27270 - If the pendulum is -2, then two stores have already been
27271 issued in this cycle, so we increase the priority of the first load
27272 in the ready list to increase it's likelihood of being chosen first
27275 - If the pendulum is -1, then a single store has been issued in this
27276 cycle and we attempt to locate another store in the ready list to
27277 issue with it, preferring a store to an adjacent memory location to
27278 facilitate store pairing in the store queue.
27280 - If the pendulum is 2, then two loads have already been
27281 issued in this cycle, so we increase the priority of the first store
27282 in the ready list to increase it's likelihood of being chosen first
27285 - If the pendulum < -2 or > 2, then do nothing.
27287 Note: This code covers the most common scenarios. There exist non
27288 load/store instructions which make use of the LSU and which
27289 would need to be accounted for to strictly model the behavior
27290 of the machine. Those instructions are currently unaccounted
27291 for to help minimize compile time overhead of this code.
27293 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
27298 rtx load_mem
, str_mem
;
27300 if (is_store_insn (last_scheduled_insn
, &str_mem
))
27301 /* Issuing a store, swing the load_store_pendulum to the left */
27302 load_store_pendulum
--;
27303 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
27304 /* Issuing a load, swing the load_store_pendulum to the right */
27305 load_store_pendulum
++;
27307 return cached_can_issue_more
;
27309 /* If the pendulum is balanced, or there is only one instruction on
27310 the ready list, then all is well, so return. */
27311 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
27312 return cached_can_issue_more
;
27314 if (load_store_pendulum
== 1)
27316 /* A load has been issued in this cycle. Scan the ready list
27317 for another load to issue with it */
27322 if (is_load_insn (ready
[pos
], &load_mem
))
27324 /* Found a load. Move it to the head of the ready list,
27325 and adjust it's priority so that it is more likely to
27328 for (i
=pos
; i
<*pn_ready
-1; i
++)
27329 ready
[i
] = ready
[i
+ 1];
27330 ready
[*pn_ready
-1] = tmp
;
27332 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27333 INSN_PRIORITY (tmp
)++;
27339 else if (load_store_pendulum
== -2)
27341 /* Two stores have been issued in this cycle. Increase the
27342 priority of the first load in the ready list to favor it for
27343 issuing in the next cycle. */
27348 if (is_load_insn (ready
[pos
], &load_mem
)
27350 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27352 INSN_PRIORITY (ready
[pos
])++;
27354 /* Adjust the pendulum to account for the fact that a load
27355 was found and increased in priority. This is to prevent
27356 increasing the priority of multiple loads */
27357 load_store_pendulum
--;
27364 else if (load_store_pendulum
== -1)
27366 /* A store has been issued in this cycle. Scan the ready list for
27367 another store to issue with it, preferring a store to an adjacent
27369 int first_store_pos
= -1;
27375 if (is_store_insn (ready
[pos
], &str_mem
))
27378 /* Maintain the index of the first store found on the
27380 if (first_store_pos
== -1)
27381 first_store_pos
= pos
;
27383 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
27384 && adjacent_mem_locations (str_mem
, str_mem2
))
27386 /* Found an adjacent store. Move it to the head of the
27387 ready list, and adjust it's priority so that it is
27388 more likely to stay there */
27390 for (i
=pos
; i
<*pn_ready
-1; i
++)
27391 ready
[i
] = ready
[i
+ 1];
27392 ready
[*pn_ready
-1] = tmp
;
27394 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27395 INSN_PRIORITY (tmp
)++;
27397 first_store_pos
= -1;
27405 if (first_store_pos
>= 0)
27407 /* An adjacent store wasn't found, but a non-adjacent store was,
27408 so move the non-adjacent store to the front of the ready
27409 list, and adjust its priority so that it is more likely to
27411 tmp
= ready
[first_store_pos
];
27412 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
27413 ready
[i
] = ready
[i
+ 1];
27414 ready
[*pn_ready
-1] = tmp
;
27415 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27416 INSN_PRIORITY (tmp
)++;
27419 else if (load_store_pendulum
== 2)
27421 /* Two loads have been issued in this cycle. Increase the priority
27422 of the first store in the ready list to favor it for issuing in
27428 if (is_store_insn (ready
[pos
], &str_mem
)
27430 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27432 INSN_PRIORITY (ready
[pos
])++;
27434 /* Adjust the pendulum to account for the fact that a store
27435 was found and increased in priority. This is to prevent
27436 increasing the priority of multiple stores */
27437 load_store_pendulum
++;
27446 return cached_can_issue_more
;
27449 /* Return whether the presence of INSN causes a dispatch group termination
27450 of group WHICH_GROUP.
27452 If WHICH_GROUP == current_group, this function will return true if INSN
27453 causes the termination of the current group (i.e, the dispatch group to
27454 which INSN belongs). This means that INSN will be the last insn in the
27455 group it belongs to.
27457 If WHICH_GROUP == previous_group, this function will return true if INSN
27458 causes the termination of the previous group (i.e, the dispatch group that
27459 precedes the group to which INSN belongs). This means that INSN will be
27460 the first insn in the group it belongs to). */
27463 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
27470 first
= insn_must_be_first_in_group (insn
);
27471 last
= insn_must_be_last_in_group (insn
);
27476 if (which_group
== current_group
)
27478 else if (which_group
== previous_group
)
27486 insn_must_be_first_in_group (rtx_insn
*insn
)
27488 enum attr_type type
;
27492 || DEBUG_INSN_P (insn
)
27493 || GET_CODE (PATTERN (insn
)) == USE
27494 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27497 switch (rs6000_cpu
)
27499 case PROCESSOR_POWER5
:
27500 if (is_cracked_insn (insn
))
27502 case PROCESSOR_POWER4
:
27503 if (is_microcoded_insn (insn
))
27506 if (!rs6000_sched_groups
)
27509 type
= get_attr_type (insn
);
27516 case TYPE_DELAYED_CR
:
27517 case TYPE_CR_LOGICAL
:
27530 case PROCESSOR_POWER6
:
27531 type
= get_attr_type (insn
);
27540 case TYPE_FPCOMPARE
:
27551 if (get_attr_dot (insn
) == DOT_NO
27552 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
27557 if (get_attr_size (insn
) == SIZE_32
)
27565 if (get_attr_update (insn
) == UPDATE_YES
)
27573 case PROCESSOR_POWER7
:
27574 type
= get_attr_type (insn
);
27578 case TYPE_CR_LOGICAL
:
27593 if (get_attr_dot (insn
) == DOT_YES
)
27598 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27599 || get_attr_update (insn
) == UPDATE_YES
)
27606 if (get_attr_update (insn
) == UPDATE_YES
)
27614 case PROCESSOR_POWER8
:
27615 type
= get_attr_type (insn
);
27619 case TYPE_CR_LOGICAL
:
27620 case TYPE_DELAYED_CR
:
27629 case TYPE_VECSTORE
:
27636 if (get_attr_dot (insn
) == DOT_YES
)
27641 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27642 || get_attr_update (insn
) == UPDATE_YES
)
27647 if (get_attr_update (insn
) == UPDATE_YES
27648 && get_attr_indexed (insn
) == INDEXED_YES
)
27664 insn_must_be_last_in_group (rtx_insn
*insn
)
27666 enum attr_type type
;
27670 || DEBUG_INSN_P (insn
)
27671 || GET_CODE (PATTERN (insn
)) == USE
27672 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27675 switch (rs6000_cpu
) {
27676 case PROCESSOR_POWER4
:
27677 case PROCESSOR_POWER5
:
27678 if (is_microcoded_insn (insn
))
27681 if (is_branch_slot_insn (insn
))
27685 case PROCESSOR_POWER6
:
27686 type
= get_attr_type (insn
);
27694 case TYPE_FPCOMPARE
:
27705 if (get_attr_dot (insn
) == DOT_NO
27706 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
27711 if (get_attr_size (insn
) == SIZE_32
)
27719 case PROCESSOR_POWER7
:
27720 type
= get_attr_type (insn
);
27730 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27731 && get_attr_update (insn
) == UPDATE_YES
)
27736 if (get_attr_update (insn
) == UPDATE_YES
27737 && get_attr_indexed (insn
) == INDEXED_YES
)
27745 case PROCESSOR_POWER8
:
27746 type
= get_attr_type (insn
);
27758 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27759 && get_attr_update (insn
) == UPDATE_YES
)
27764 if (get_attr_update (insn
) == UPDATE_YES
27765 && get_attr_indexed (insn
) == INDEXED_YES
)
27780 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
27781 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
27784 is_costly_group (rtx
*group_insns
, rtx next_insn
)
27787 int issue_rate
= rs6000_issue_rate ();
27789 for (i
= 0; i
< issue_rate
; i
++)
27791 sd_iterator_def sd_it
;
27793 rtx insn
= group_insns
[i
];
27798 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
27800 rtx next
= DEP_CON (dep
);
27802 if (next
== next_insn
27803 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
27811 /* Utility of the function redefine_groups.
27812 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
27813 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
27814 to keep it "far" (in a separate group) from GROUP_INSNS, following
27815 one of the following schemes, depending on the value of the flag
27816 -minsert_sched_nops = X:
27817 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
27818 in order to force NEXT_INSN into a separate group.
27819 (2) X < sched_finish_regroup_exact: insert exactly X nops.
27820 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
27821 insertion (has a group just ended, how many vacant issue slots remain in the
27822 last group, and how many dispatch groups were encountered so far). */
27825 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
27826 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
27831 int issue_rate
= rs6000_issue_rate ();
27832 bool end
= *group_end
;
27835 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
27836 return can_issue_more
;
27838 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
27839 return can_issue_more
;
27841 force
= is_costly_group (group_insns
, next_insn
);
27843 return can_issue_more
;
27845 if (sched_verbose
> 6)
27846 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
27847 *group_count
,can_issue_more
);
27849 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
27852 can_issue_more
= 0;
27854 /* Since only a branch can be issued in the last issue_slot, it is
27855 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
27856 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
27857 in this case the last nop will start a new group and the branch
27858 will be forced to the new group. */
27859 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
27862 /* Do we have a special group ending nop? */
27863 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
27864 || rs6000_cpu_attr
== CPU_POWER8
)
27866 nop
= gen_group_ending_nop ();
27867 emit_insn_before (nop
, next_insn
);
27868 can_issue_more
= 0;
27871 while (can_issue_more
> 0)
27874 emit_insn_before (nop
, next_insn
);
27882 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
27884 int n_nops
= rs6000_sched_insert_nops
;
27886 /* Nops can't be issued from the branch slot, so the effective
27887 issue_rate for nops is 'issue_rate - 1'. */
27888 if (can_issue_more
== 0)
27889 can_issue_more
= issue_rate
;
27891 if (can_issue_more
== 0)
27893 can_issue_more
= issue_rate
- 1;
27896 for (i
= 0; i
< issue_rate
; i
++)
27898 group_insns
[i
] = 0;
27905 emit_insn_before (nop
, next_insn
);
27906 if (can_issue_more
== issue_rate
- 1) /* new group begins */
27909 if (can_issue_more
== 0)
27911 can_issue_more
= issue_rate
- 1;
27914 for (i
= 0; i
< issue_rate
; i
++)
27916 group_insns
[i
] = 0;
27922 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
27925 /* Is next_insn going to start a new group? */
27928 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27929 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27930 || (can_issue_more
< issue_rate
&&
27931 insn_terminates_group_p (next_insn
, previous_group
)));
27932 if (*group_end
&& end
)
27935 if (sched_verbose
> 6)
27936 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27937 *group_count
, can_issue_more
);
27938 return can_issue_more
;
27941 return can_issue_more
;
27944 /* This function tries to synch the dispatch groups that the compiler "sees"
27945 with the dispatch groups that the processor dispatcher is expected to
27946 form in practice. It tries to achieve this synchronization by forcing the
27947 estimated processor grouping on the compiler (as opposed to the function
27948 'pad_goups' which tries to force the scheduler's grouping on the processor).
27950 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27951 examines the (estimated) dispatch groups that will be formed by the processor
27952 dispatcher. It marks these group boundaries to reflect the estimated
27953 processor grouping, overriding the grouping that the scheduler had marked.
27954 Depending on the value of the flag '-minsert-sched-nops' this function can
27955 force certain insns into separate groups or force a certain distance between
27956 them by inserting nops, for example, if there exists a "costly dependence"
27959 The function estimates the group boundaries that the processor will form as
27960 follows: It keeps track of how many vacant issue slots are available after
27961 each insn. A subsequent insn will start a new group if one of the following
27963 - no more vacant issue slots remain in the current dispatch group.
27964 - only the last issue slot, which is the branch slot, is vacant, but the next
27965 insn is not a branch.
27966 - only the last 2 or less issue slots, including the branch slot, are vacant,
27967 which means that a cracked insn (which occupies two issue slots) can't be
27968 issued in this group.
27969 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27970 start a new group. */
27973 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
27976 rtx_insn
*insn
, *next_insn
;
27978 int can_issue_more
;
27981 int group_count
= 0;
27985 issue_rate
= rs6000_issue_rate ();
27986 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27987 for (i
= 0; i
< issue_rate
; i
++)
27989 group_insns
[i
] = 0;
27991 can_issue_more
= issue_rate
;
27993 insn
= get_next_active_insn (prev_head_insn
, tail
);
27996 while (insn
!= NULL_RTX
)
27998 slot
= (issue_rate
- can_issue_more
);
27999 group_insns
[slot
] = insn
;
28001 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
28002 if (insn_terminates_group_p (insn
, current_group
))
28003 can_issue_more
= 0;
28005 next_insn
= get_next_active_insn (insn
, tail
);
28006 if (next_insn
== NULL_RTX
)
28007 return group_count
+ 1;
28009 /* Is next_insn going to start a new group? */
28011 = (can_issue_more
== 0
28012 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
28013 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
28014 || (can_issue_more
< issue_rate
&&
28015 insn_terminates_group_p (next_insn
, previous_group
)));
28017 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
28018 next_insn
, &group_end
, can_issue_more
,
28024 can_issue_more
= 0;
28025 for (i
= 0; i
< issue_rate
; i
++)
28027 group_insns
[i
] = 0;
28031 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
28032 PUT_MODE (next_insn
, VOIDmode
);
28033 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
28034 PUT_MODE (next_insn
, TImode
);
28037 if (can_issue_more
== 0)
28038 can_issue_more
= issue_rate
;
28041 return group_count
;
28044 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
28045 dispatch group boundaries that the scheduler had marked. Pad with nops
28046 any dispatch groups which have vacant issue slots, in order to force the
28047 scheduler's grouping on the processor dispatcher. The function
28048 returns the number of dispatch groups found. */
28051 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
28054 rtx_insn
*insn
, *next_insn
;
28057 int can_issue_more
;
28059 int group_count
= 0;
28061 /* Initialize issue_rate. */
28062 issue_rate
= rs6000_issue_rate ();
28063 can_issue_more
= issue_rate
;
28065 insn
= get_next_active_insn (prev_head_insn
, tail
);
28066 next_insn
= get_next_active_insn (insn
, tail
);
28068 while (insn
!= NULL_RTX
)
28071 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
28073 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
28075 if (next_insn
== NULL_RTX
)
28080 /* If the scheduler had marked group termination at this location
28081 (between insn and next_insn), and neither insn nor next_insn will
28082 force group termination, pad the group with nops to force group
28085 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
28086 && !insn_terminates_group_p (insn
, current_group
)
28087 && !insn_terminates_group_p (next_insn
, previous_group
))
28089 if (!is_branch_slot_insn (next_insn
))
28092 while (can_issue_more
)
28095 emit_insn_before (nop
, next_insn
);
28100 can_issue_more
= issue_rate
;
28105 next_insn
= get_next_active_insn (insn
, tail
);
28108 return group_count
;
28111 /* We're beginning a new block. Initialize data structures as necessary. */
28114 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
28115 int sched_verbose ATTRIBUTE_UNUSED
,
28116 int max_ready ATTRIBUTE_UNUSED
)
28118 last_scheduled_insn
= NULL_RTX
;
28119 load_store_pendulum
= 0;
28122 /* The following function is called at the end of scheduling BB.
28123 After reload, it inserts nops at insn group bundling. */
28126 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
28131 fprintf (dump
, "=== Finishing schedule.\n");
28133 if (reload_completed
&& rs6000_sched_groups
)
28135 /* Do not run sched_finish hook when selective scheduling enabled. */
28136 if (sel_sched_p ())
28139 if (rs6000_sched_insert_nops
== sched_finish_none
)
28142 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
28143 n_groups
= pad_groups (dump
, sched_verbose
,
28144 current_sched_info
->prev_head
,
28145 current_sched_info
->next_tail
);
28147 n_groups
= redefine_groups (dump
, sched_verbose
,
28148 current_sched_info
->prev_head
,
28149 current_sched_info
->next_tail
);
28151 if (sched_verbose
>= 6)
28153 fprintf (dump
, "ngroups = %d\n", n_groups
);
28154 print_rtl (dump
, current_sched_info
->prev_head
);
28155 fprintf (dump
, "Done finish_sched\n");
28160 struct _rs6000_sched_context
28162 short cached_can_issue_more
;
28163 rtx last_scheduled_insn
;
28164 int load_store_pendulum
;
28167 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
28168 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
28170 /* Allocate store for new scheduling context. */
28172 rs6000_alloc_sched_context (void)
28174 return xmalloc (sizeof (rs6000_sched_context_def
));
28177 /* If CLEAN_P is true then initializes _SC with clean data,
28178 and from the global context otherwise. */
28180 rs6000_init_sched_context (void *_sc
, bool clean_p
)
28182 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
28186 sc
->cached_can_issue_more
= 0;
28187 sc
->last_scheduled_insn
= NULL_RTX
;
28188 sc
->load_store_pendulum
= 0;
28192 sc
->cached_can_issue_more
= cached_can_issue_more
;
28193 sc
->last_scheduled_insn
= last_scheduled_insn
;
28194 sc
->load_store_pendulum
= load_store_pendulum
;
28198 /* Sets the global scheduling context to the one pointed to by _SC. */
28200 rs6000_set_sched_context (void *_sc
)
28202 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
28204 gcc_assert (sc
!= NULL
);
28206 cached_can_issue_more
= sc
->cached_can_issue_more
;
28207 last_scheduled_insn
= sc
->last_scheduled_insn
;
28208 load_store_pendulum
= sc
->load_store_pendulum
;
28213 rs6000_free_sched_context (void *_sc
)
28215 gcc_assert (_sc
!= NULL
);
28221 /* Length in units of the trampoline for entering a nested function. */
28224 rs6000_trampoline_size (void)
28228 switch (DEFAULT_ABI
)
28231 gcc_unreachable ();
28234 ret
= (TARGET_32BIT
) ? 12 : 24;
28238 gcc_assert (!TARGET_32BIT
);
28244 ret
= (TARGET_32BIT
) ? 40 : 48;
28251 /* Emit RTL insns to initialize the variable parts of a trampoline.
28252 FNADDR is an RTX for the address of the function's pure code.
28253 CXT is an RTX for the static chain value for the function. */
28256 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
28258 int regsize
= (TARGET_32BIT
) ? 4 : 8;
28259 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
28260 rtx ctx_reg
= force_reg (Pmode
, cxt
);
28261 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
28263 switch (DEFAULT_ABI
)
28266 gcc_unreachable ();
28268 /* Under AIX, just build the 3 word function descriptor */
28271 rtx fnmem
, fn_reg
, toc_reg
;
28273 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28274 error ("You cannot take the address of a nested function if you use "
28275 "the -mno-pointers-to-nested-functions option.");
28277 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
28278 fn_reg
= gen_reg_rtx (Pmode
);
28279 toc_reg
= gen_reg_rtx (Pmode
);
28281 /* Macro to shorten the code expansions below. */
28282 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
28284 m_tramp
= replace_equiv_address (m_tramp
, addr
);
28286 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
28287 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
28288 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
28289 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
28290 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
28296 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
28300 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
28301 LCT_NORMAL
, VOIDmode
, 4,
28303 GEN_INT (rs6000_trampoline_size ()), SImode
,
28311 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
28312 identifier as an argument, so the front end shouldn't look it up. */
28315 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
28317 return is_attribute_p ("altivec", attr_id
);
28320 /* Handle the "altivec" attribute. The attribute may have
28321 arguments as follows:
28323 __attribute__((altivec(vector__)))
28324 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
28325 __attribute__((altivec(bool__))) (always followed by 'unsigned')
28327 and may appear more than once (e.g., 'vector bool char') in a
28328 given declaration. */
28331 rs6000_handle_altivec_attribute (tree
*node
,
28332 tree name ATTRIBUTE_UNUSED
,
28334 int flags ATTRIBUTE_UNUSED
,
28335 bool *no_add_attrs
)
28337 tree type
= *node
, result
= NULL_TREE
;
28338 enum machine_mode mode
;
28341 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
28342 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
28343 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
28346 while (POINTER_TYPE_P (type
)
28347 || TREE_CODE (type
) == FUNCTION_TYPE
28348 || TREE_CODE (type
) == METHOD_TYPE
28349 || TREE_CODE (type
) == ARRAY_TYPE
)
28350 type
= TREE_TYPE (type
);
28352 mode
= TYPE_MODE (type
);
28354 /* Check for invalid AltiVec type qualifiers. */
28355 if (type
== long_double_type_node
)
28356 error ("use of %<long double%> in AltiVec types is invalid");
28357 else if (type
== boolean_type_node
)
28358 error ("use of boolean types in AltiVec types is invalid");
28359 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
28360 error ("use of %<complex%> in AltiVec types is invalid");
28361 else if (DECIMAL_FLOAT_MODE_P (mode
))
28362 error ("use of decimal floating point types in AltiVec types is invalid");
28363 else if (!TARGET_VSX
)
28365 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
28368 error ("use of %<long%> in AltiVec types is invalid for "
28369 "64-bit code without -mvsx");
28370 else if (rs6000_warn_altivec_long
)
28371 warning (0, "use of %<long%> in AltiVec types is deprecated; "
28374 else if (type
== long_long_unsigned_type_node
28375 || type
== long_long_integer_type_node
)
28376 error ("use of %<long long%> in AltiVec types is invalid without "
28378 else if (type
== double_type_node
)
28379 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
28382 switch (altivec_type
)
28385 unsigned_p
= TYPE_UNSIGNED (type
);
28389 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
28392 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
28395 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
28398 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
28401 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
28403 case SFmode
: result
= V4SF_type_node
; break;
28404 case DFmode
: result
= V2DF_type_node
; break;
28405 /* If the user says 'vector int bool', we may be handed the 'bool'
28406 attribute _before_ the 'vector' attribute, and so select the
28407 proper type in the 'b' case below. */
28408 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
28409 case V2DImode
: case V2DFmode
:
28417 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
28418 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
28419 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
28420 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
28427 case V8HImode
: result
= pixel_V8HI_type_node
;
28433 /* Propagate qualifiers attached to the element type
28434 onto the vector type. */
28435 if (result
&& result
!= type
&& TYPE_QUALS (type
))
28436 result
= build_qualified_type (result
, TYPE_QUALS (type
));
28438 *no_add_attrs
= true; /* No need to hang on to the attribute. */
28441 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
28446 /* AltiVec defines four built-in scalar types that serve as vector
28447 elements; we must teach the compiler how to mangle them. */
28449 static const char *
28450 rs6000_mangle_type (const_tree type
)
28452 type
= TYPE_MAIN_VARIANT (type
);
28454 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
28455 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
28458 if (type
== bool_char_type_node
) return "U6__boolc";
28459 if (type
== bool_short_type_node
) return "U6__bools";
28460 if (type
== pixel_type_node
) return "u7__pixel";
28461 if (type
== bool_int_type_node
) return "U6__booli";
28462 if (type
== bool_long_type_node
) return "U6__booll";
28464 /* Mangle IBM extended float long double as `g' (__float128) on
28465 powerpc*-linux where long-double-64 previously was the default. */
28466 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
28468 && TARGET_LONG_DOUBLE_128
28469 && !TARGET_IEEEQUAD
)
28472 /* For all other types, use normal C++ mangling. */
28476 /* Handle a "longcall" or "shortcall" attribute; arguments as in
28477 struct attribute_spec.handler. */
28480 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
28481 tree args ATTRIBUTE_UNUSED
,
28482 int flags ATTRIBUTE_UNUSED
,
28483 bool *no_add_attrs
)
28485 if (TREE_CODE (*node
) != FUNCTION_TYPE
28486 && TREE_CODE (*node
) != FIELD_DECL
28487 && TREE_CODE (*node
) != TYPE_DECL
)
28489 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
28491 *no_add_attrs
= true;
28497 /* Set longcall attributes on all functions declared when
28498 rs6000_default_long_calls is true. */
28500 rs6000_set_default_type_attributes (tree type
)
28502 if (rs6000_default_long_calls
28503 && (TREE_CODE (type
) == FUNCTION_TYPE
28504 || TREE_CODE (type
) == METHOD_TYPE
))
28505 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
28507 TYPE_ATTRIBUTES (type
));
28510 darwin_set_default_type_attributes (type
);
28514 /* Return a reference suitable for calling a function with the
28515 longcall attribute. */
28518 rs6000_longcall_ref (rtx call_ref
)
28520 const char *call_name
;
28523 if (GET_CODE (call_ref
) != SYMBOL_REF
)
28526 /* System V adds '.' to the internal name, so skip them. */
28527 call_name
= XSTR (call_ref
, 0);
28528 if (*call_name
== '.')
28530 while (*call_name
== '.')
28533 node
= get_identifier (call_name
);
28534 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
28537 return force_reg (Pmode
, call_ref
);
28540 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
28541 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
28544 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
28545 struct attribute_spec.handler. */
28547 rs6000_handle_struct_attribute (tree
*node
, tree name
,
28548 tree args ATTRIBUTE_UNUSED
,
28549 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
28552 if (DECL_P (*node
))
28554 if (TREE_CODE (*node
) == TYPE_DECL
)
28555 type
= &TREE_TYPE (*node
);
28560 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
28561 || TREE_CODE (*type
) == UNION_TYPE
)))
28563 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
28564 *no_add_attrs
= true;
28567 else if ((is_attribute_p ("ms_struct", name
)
28568 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
28569 || ((is_attribute_p ("gcc_struct", name
)
28570 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
28572 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
28574 *no_add_attrs
= true;
28581 rs6000_ms_bitfield_layout_p (const_tree record_type
)
28583 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
28584 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
28585 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
28588 #ifdef USING_ELFOS_H
28590 /* A get_unnamed_section callback, used for switching to toc_section. */
28593 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28595 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28596 && TARGET_MINIMAL_TOC
28597 && !TARGET_RELOCATABLE
)
28599 if (!toc_initialized
)
28601 toc_initialized
= 1;
28602 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28603 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
28604 fprintf (asm_out_file
, "\t.tc ");
28605 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
28606 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28607 fprintf (asm_out_file
, "\n");
28609 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28610 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28611 fprintf (asm_out_file
, " = .+32768\n");
28614 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28616 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28617 && !TARGET_RELOCATABLE
)
28618 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28621 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28622 if (!toc_initialized
)
28624 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28625 fprintf (asm_out_file
, " = .+32768\n");
28626 toc_initialized
= 1;
28631 /* Implement TARGET_ASM_INIT_SECTIONS. */
28634 rs6000_elf_asm_init_sections (void)
28637 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
28640 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
28641 SDATA2_SECTION_ASM_OP
);
28644 /* Implement TARGET_SELECT_RTX_SECTION. */
28647 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
28648 unsigned HOST_WIDE_INT align
)
28650 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28651 return toc_section
;
28653 return default_elf_select_rtx_section (mode
, x
, align
);
28656 /* For a SYMBOL_REF, set generic flags and then perform some
28657 target-specific processing.
28659 When the AIX ABI is requested on a non-AIX system, replace the
28660 function name with the real name (with a leading .) rather than the
28661 function descriptor name. This saves a lot of overriding code to
28662 read the prefixes. */
28664 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
28666 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
28668 default_encode_section_info (decl
, rtl
, first
);
28671 && TREE_CODE (decl
) == FUNCTION_DECL
28673 && DEFAULT_ABI
== ABI_AIX
)
28675 rtx sym_ref
= XEXP (rtl
, 0);
28676 size_t len
= strlen (XSTR (sym_ref
, 0));
28677 char *str
= XALLOCAVEC (char, len
+ 2);
28679 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
28680 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
28685 compare_section_name (const char *section
, const char *templ
)
28689 len
= strlen (templ
);
28690 return (strncmp (section
, templ
, len
) == 0
28691 && (section
[len
] == 0 || section
[len
] == '.'));
28695 rs6000_elf_in_small_data_p (const_tree decl
)
28697 if (rs6000_sdata
== SDATA_NONE
)
28700 /* We want to merge strings, so we never consider them small data. */
28701 if (TREE_CODE (decl
) == STRING_CST
)
28704 /* Functions are never in the small data area. */
28705 if (TREE_CODE (decl
) == FUNCTION_DECL
)
28708 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
28710 const char *section
= DECL_SECTION_NAME (decl
);
28711 if (compare_section_name (section
, ".sdata")
28712 || compare_section_name (section
, ".sdata2")
28713 || compare_section_name (section
, ".gnu.linkonce.s")
28714 || compare_section_name (section
, ".sbss")
28715 || compare_section_name (section
, ".sbss2")
28716 || compare_section_name (section
, ".gnu.linkonce.sb")
28717 || strcmp (section
, ".PPC.EMB.sdata0") == 0
28718 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
28723 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
28726 && size
<= g_switch_value
28727 /* If it's not public, and we're not going to reference it there,
28728 there's no need to put it in the small data section. */
28729 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
28736 #endif /* USING_ELFOS_H */
28738 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
28741 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
28743 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
28746 /* Do not place thread-local symbols refs in the object blocks. */
28749 rs6000_use_blocks_for_decl_p (const_tree decl
)
28751 return !DECL_THREAD_LOCAL_P (decl
);
28754 /* Return a REG that occurs in ADDR with coefficient 1.
28755 ADDR can be effectively incremented by incrementing REG.
28757 r0 is special and we must not select it as an address
28758 register by this routine since our caller will try to
28759 increment the returned register via an "la" instruction. */
28762 find_addr_reg (rtx addr
)
28764 while (GET_CODE (addr
) == PLUS
)
28766 if (GET_CODE (XEXP (addr
, 0)) == REG
28767 && REGNO (XEXP (addr
, 0)) != 0)
28768 addr
= XEXP (addr
, 0);
28769 else if (GET_CODE (XEXP (addr
, 1)) == REG
28770 && REGNO (XEXP (addr
, 1)) != 0)
28771 addr
= XEXP (addr
, 1);
28772 else if (CONSTANT_P (XEXP (addr
, 0)))
28773 addr
= XEXP (addr
, 1);
28774 else if (CONSTANT_P (XEXP (addr
, 1)))
28775 addr
= XEXP (addr
, 0);
28777 gcc_unreachable ();
28779 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
28784 rs6000_fatal_bad_address (rtx op
)
28786 fatal_insn ("bad address", op
);
28791 typedef struct branch_island_d
{
28792 tree function_name
;
28798 static vec
<branch_island
, va_gc
> *branch_islands
;
28800 /* Remember to generate a branch island for far calls to the given
28804 add_compiler_branch_island (tree label_name
, tree function_name
,
28807 branch_island bi
= {function_name
, label_name
, line_number
};
28808 vec_safe_push (branch_islands
, bi
);
28811 /* Generate far-jump branch islands for everything recorded in
28812 branch_islands. Invoked immediately after the last instruction of
28813 the epilogue has been emitted; the branch islands must be appended
28814 to, and contiguous with, the function body. Mach-O stubs are
28815 generated in machopic_output_stub(). */
28818 macho_branch_islands (void)
28822 while (!vec_safe_is_empty (branch_islands
))
28824 branch_island
*bi
= &branch_islands
->last ();
28825 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
28826 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
28827 char name_buf
[512];
28828 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
28829 if (name
[0] == '*' || name
[0] == '&')
28830 strcpy (name_buf
, name
+1);
28834 strcpy (name_buf
+1, name
);
28836 strcpy (tmp_buf
, "\n");
28837 strcat (tmp_buf
, label
);
28838 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28839 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28840 dbxout_stabd (N_SLINE
, bi
->line_number
);
28841 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28844 if (TARGET_LINK_STACK
)
28847 get_ppc476_thunk_name (name
);
28848 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
28849 strcat (tmp_buf
, name
);
28850 strcat (tmp_buf
, "\n");
28851 strcat (tmp_buf
, label
);
28852 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28856 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
28857 strcat (tmp_buf
, label
);
28858 strcat (tmp_buf
, "_pic\n");
28859 strcat (tmp_buf
, label
);
28860 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28863 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
28864 strcat (tmp_buf
, name_buf
);
28865 strcat (tmp_buf
, " - ");
28866 strcat (tmp_buf
, label
);
28867 strcat (tmp_buf
, "_pic)\n");
28869 strcat (tmp_buf
, "\tmtlr r0\n");
28871 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
28872 strcat (tmp_buf
, name_buf
);
28873 strcat (tmp_buf
, " - ");
28874 strcat (tmp_buf
, label
);
28875 strcat (tmp_buf
, "_pic)\n");
28877 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
28881 strcat (tmp_buf
, ":\nlis r12,hi16(");
28882 strcat (tmp_buf
, name_buf
);
28883 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
28884 strcat (tmp_buf
, name_buf
);
28885 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
28887 output_asm_insn (tmp_buf
, 0);
28888 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28889 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28890 dbxout_stabd (N_SLINE
, bi
->line_number
);
28891 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28892 branch_islands
->pop ();
28896 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
28897 already there or not. */
28900 no_previous_def (tree function_name
)
28905 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28906 if (function_name
== bi
->function_name
)
28911 /* GET_PREV_LABEL gets the label name from the previous definition of
28915 get_prev_label (tree function_name
)
28920 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28921 if (function_name
== bi
->function_name
)
28922 return bi
->label_name
;
28926 /* INSN is either a function call or a millicode call. It may have an
28927 unconditional jump in its delay slot.
28929 CALL_DEST is the routine we are calling. */
28932 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
28933 int cookie_operand_number
)
28935 static char buf
[256];
28936 if (darwin_emit_branch_islands
28937 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28938 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28941 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28943 if (no_previous_def (funname
))
28945 rtx label_rtx
= gen_label_rtx ();
28946 char *label_buf
, temp_buf
[256];
28947 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28948 CODE_LABEL_NUMBER (label_rtx
));
28949 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28950 labelname
= get_identifier (label_buf
);
28951 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28954 labelname
= get_prev_label (funname
);
28956 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28957 instruction will reach 'foo', otherwise link as 'bl L42'".
28958 "L42" should be a 'branch island', that will do a far jump to
28959 'foo'. Branch islands are generated in
28960 macho_branch_islands(). */
28961 sprintf (buf
, "jbsr %%z%d,%.246s",
28962 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28965 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28969 /* Generate PIC and indirect symbol stubs. */
28972 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28974 unsigned int length
;
28975 char *symbol_name
, *lazy_ptr_name
;
28976 char *local_label_0
;
28977 static int label
= 0;
28979 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28980 symb
= (*targetm
.strip_name_encoding
) (symb
);
28983 length
= strlen (symb
);
28984 symbol_name
= XALLOCAVEC (char, length
+ 32);
28985 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28987 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28988 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28991 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28993 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28997 fprintf (file
, "\t.align 5\n");
28999 fprintf (file
, "%s:\n", stub
);
29000 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
29003 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
29004 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
29006 fprintf (file
, "\tmflr r0\n");
29007 if (TARGET_LINK_STACK
)
29010 get_ppc476_thunk_name (name
);
29011 fprintf (file
, "\tbl %s\n", name
);
29012 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
29016 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
29017 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
29019 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
29020 lazy_ptr_name
, local_label_0
);
29021 fprintf (file
, "\tmtlr r0\n");
29022 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
29023 (TARGET_64BIT
? "ldu" : "lwzu"),
29024 lazy_ptr_name
, local_label_0
);
29025 fprintf (file
, "\tmtctr r12\n");
29026 fprintf (file
, "\tbctr\n");
29030 fprintf (file
, "\t.align 4\n");
29032 fprintf (file
, "%s:\n", stub
);
29033 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
29035 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
29036 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
29037 (TARGET_64BIT
? "ldu" : "lwzu"),
29039 fprintf (file
, "\tmtctr r12\n");
29040 fprintf (file
, "\tbctr\n");
29043 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
29044 fprintf (file
, "%s:\n", lazy_ptr_name
);
29045 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
29046 fprintf (file
, "%sdyld_stub_binding_helper\n",
29047 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
29050 /* Legitimize PIC addresses. If the address is already
29051 position-independent, we return ORIG. Newly generated
29052 position-independent addresses go into a reg. This is REG if non
29053 zero, otherwise we allocate register(s) as necessary. */
29055 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
29058 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
29063 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
29064 reg
= gen_reg_rtx (Pmode
);
29066 if (GET_CODE (orig
) == CONST
)
29070 if (GET_CODE (XEXP (orig
, 0)) == PLUS
29071 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
29074 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
29076 /* Use a different reg for the intermediate value, as
29077 it will be marked UNCHANGING. */
29078 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
29079 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
29082 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
29085 if (GET_CODE (offset
) == CONST_INT
)
29087 if (SMALL_INT (offset
))
29088 return plus_constant (Pmode
, base
, INTVAL (offset
));
29089 else if (! reload_in_progress
&& ! reload_completed
)
29090 offset
= force_reg (Pmode
, offset
);
29093 rtx mem
= force_const_mem (Pmode
, orig
);
29094 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
29097 return gen_rtx_PLUS (Pmode
, base
, offset
);
29100 /* Fall back on generic machopic code. */
29101 return machopic_legitimize_pic_address (orig
, mode
, reg
);
29104 /* Output a .machine directive for the Darwin assembler, and call
29105 the generic start_file routine. */
29108 rs6000_darwin_file_start (void)
29110 static const struct
29114 HOST_WIDE_INT if_set
;
29116 { "ppc64", "ppc64", MASK_64BIT
},
29117 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
29118 { "power4", "ppc970", 0 },
29119 { "G5", "ppc970", 0 },
29120 { "7450", "ppc7450", 0 },
29121 { "7400", "ppc7400", MASK_ALTIVEC
},
29122 { "G4", "ppc7400", 0 },
29123 { "750", "ppc750", 0 },
29124 { "740", "ppc750", 0 },
29125 { "G3", "ppc750", 0 },
29126 { "604e", "ppc604e", 0 },
29127 { "604", "ppc604", 0 },
29128 { "603e", "ppc603", 0 },
29129 { "603", "ppc603", 0 },
29130 { "601", "ppc601", 0 },
29131 { NULL
, "ppc", 0 } };
29132 const char *cpu_id
= "";
29135 rs6000_file_start ();
29136 darwin_file_start ();
29138 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
29140 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
29141 cpu_id
= rs6000_default_cpu
;
29143 if (global_options_set
.x_rs6000_cpu_index
)
29144 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
29146 /* Look through the mapping array. Pick the first name that either
29147 matches the argument, has a bit set in IF_SET that is also set
29148 in the target flags, or has a NULL name. */
29151 while (mapping
[i
].arg
!= NULL
29152 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
29153 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
29156 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
29159 #endif /* TARGET_MACHO */
29163 rs6000_elf_reloc_rw_mask (void)
29167 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29173 /* Record an element in the table of global constructors. SYMBOL is
29174 a SYMBOL_REF of the function to be called; PRIORITY is a number
29175 between 0 and MAX_INIT_PRIORITY.
29177 This differs from default_named_section_asm_out_constructor in
29178 that we have special handling for -mrelocatable. */
29180 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
29182 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
29184 const char *section
= ".ctors";
29187 if (priority
!= DEFAULT_INIT_PRIORITY
)
29189 sprintf (buf
, ".ctors.%.5u",
29190 /* Invert the numbering so the linker puts us in the proper
29191 order; constructors are run from right to left, and the
29192 linker sorts in increasing order. */
29193 MAX_INIT_PRIORITY
- priority
);
29197 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29198 assemble_align (POINTER_SIZE
);
29200 if (TARGET_RELOCATABLE
)
29202 fputs ("\t.long (", asm_out_file
);
29203 output_addr_const (asm_out_file
, symbol
);
29204 fputs (")@fixup\n", asm_out_file
);
29207 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29210 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
29212 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
29214 const char *section
= ".dtors";
29217 if (priority
!= DEFAULT_INIT_PRIORITY
)
29219 sprintf (buf
, ".dtors.%.5u",
29220 /* Invert the numbering so the linker puts us in the proper
29221 order; constructors are run from right to left, and the
29222 linker sorts in increasing order. */
29223 MAX_INIT_PRIORITY
- priority
);
29227 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29228 assemble_align (POINTER_SIZE
);
29230 if (TARGET_RELOCATABLE
)
29232 fputs ("\t.long (", asm_out_file
);
29233 output_addr_const (asm_out_file
, symbol
);
29234 fputs (")@fixup\n", asm_out_file
);
29237 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29241 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
29243 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
29245 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
29246 ASM_OUTPUT_LABEL (file
, name
);
29247 fputs (DOUBLE_INT_ASM_OP
, file
);
29248 rs6000_output_function_entry (file
, name
);
29249 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
29252 fputs ("\t.size\t", file
);
29253 assemble_name (file
, name
);
29254 fputs (",24\n\t.type\t.", file
);
29255 assemble_name (file
, name
);
29256 fputs (",@function\n", file
);
29257 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
29259 fputs ("\t.globl\t.", file
);
29260 assemble_name (file
, name
);
29265 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29266 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29267 rs6000_output_function_entry (file
, name
);
29268 fputs (":\n", file
);
29272 if (TARGET_RELOCATABLE
29273 && !TARGET_SECURE_PLT
29274 && (get_pool_size () != 0 || crtl
->profile
)
29279 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
29281 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
29282 fprintf (file
, "\t.long ");
29283 assemble_name (file
, buf
);
29285 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
29286 assemble_name (file
, buf
);
29290 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29291 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29293 if (DEFAULT_ABI
== ABI_AIX
)
29295 const char *desc_name
, *orig_name
;
29297 orig_name
= (*targetm
.strip_name_encoding
) (name
);
29298 desc_name
= orig_name
;
29299 while (*desc_name
== '.')
29302 if (TREE_PUBLIC (decl
))
29303 fprintf (file
, "\t.globl %s\n", desc_name
);
29305 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29306 fprintf (file
, "%s:\n", desc_name
);
29307 fprintf (file
, "\t.long %s\n", orig_name
);
29308 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
29309 fputs ("\t.long 0\n", file
);
29310 fprintf (file
, "\t.previous\n");
29312 ASM_OUTPUT_LABEL (file
, name
);
29315 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
29317 rs6000_elf_file_end (void)
29319 #ifdef HAVE_AS_GNU_ATTRIBUTE
29320 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
29322 if (rs6000_passes_float
)
29323 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
29324 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
29325 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
29327 if (rs6000_passes_vector
)
29328 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
29329 (TARGET_ALTIVEC_ABI
? 2
29330 : TARGET_SPE_ABI
? 3
29332 if (rs6000_returns_struct
)
29333 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
29334 aix_struct_return
? 2 : 1);
29337 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
29338 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
29339 file_end_indicate_exec_stack ();
29346 rs6000_xcoff_asm_output_anchor (rtx symbol
)
29350 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
29351 SYMBOL_REF_BLOCK_OFFSET (symbol
));
29352 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
29353 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
29354 fprintf (asm_out_file
, ",");
29355 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
29356 fprintf (asm_out_file
, "\n");
29360 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
29362 fputs (GLOBAL_ASM_OP
, stream
);
29363 RS6000_OUTPUT_BASENAME (stream
, name
);
29364 putc ('\n', stream
);
29367 /* A get_unnamed_decl callback, used for read-only sections. PTR
29368 points to the section string variable. */
29371 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
29373 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
29374 *(const char *const *) directive
,
29375 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29378 /* Likewise for read-write sections. */
29381 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
29383 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
29384 *(const char *const *) directive
,
29385 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29389 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
29391 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
29392 *(const char *const *) directive
,
29393 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29396 /* A get_unnamed_section callback, used for switching to toc_section. */
29399 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29401 if (TARGET_MINIMAL_TOC
)
29403 /* toc_section is always selected at least once from
29404 rs6000_xcoff_file_start, so this is guaranteed to
29405 always be defined once and only once in each file. */
29406 if (!toc_initialized
)
29408 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
29409 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
29410 toc_initialized
= 1;
29412 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
29413 (TARGET_32BIT
? "" : ",3"));
29416 fputs ("\t.toc\n", asm_out_file
);
29419 /* Implement TARGET_ASM_INIT_SECTIONS. */
29422 rs6000_xcoff_asm_init_sections (void)
29424 read_only_data_section
29425 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29426 &xcoff_read_only_section_name
);
29428 private_data_section
29429 = get_unnamed_section (SECTION_WRITE
,
29430 rs6000_xcoff_output_readwrite_section_asm_op
,
29431 &xcoff_private_data_section_name
);
29434 = get_unnamed_section (SECTION_TLS
,
29435 rs6000_xcoff_output_tls_section_asm_op
,
29436 &xcoff_tls_data_section_name
);
29438 tls_private_data_section
29439 = get_unnamed_section (SECTION_TLS
,
29440 rs6000_xcoff_output_tls_section_asm_op
,
29441 &xcoff_private_data_section_name
);
29443 read_only_private_data_section
29444 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29445 &xcoff_private_data_section_name
);
29448 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
29450 readonly_data_section
= read_only_data_section
;
29451 exception_section
= data_section
;
29455 rs6000_xcoff_reloc_rw_mask (void)
29461 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
29462 tree decl ATTRIBUTE_UNUSED
)
29465 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
29467 if (flags
& SECTION_CODE
)
29469 else if (flags
& SECTION_TLS
)
29471 else if (flags
& SECTION_WRITE
)
29476 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
29477 (flags
& SECTION_CODE
) ? "." : "",
29478 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
29481 #define IN_NAMED_SECTION(DECL) \
29482 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
29483 && DECL_SECTION_NAME (DECL) != NULL)
29486 rs6000_xcoff_select_section (tree decl
, int reloc
,
29487 unsigned HOST_WIDE_INT align
)
29489 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
29491 if (align
> BIGGEST_ALIGNMENT
)
29493 resolve_unique_section (decl
, reloc
, true);
29494 if (IN_NAMED_SECTION (decl
))
29495 return get_named_section (decl
, NULL
, reloc
);
29498 if (decl_readonly_section (decl
, reloc
))
29500 if (TREE_PUBLIC (decl
))
29501 return read_only_data_section
;
29503 return read_only_private_data_section
;
29508 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29510 if (TREE_PUBLIC (decl
))
29511 return tls_data_section
;
29512 else if (bss_initializer_p (decl
))
29514 /* Convert to COMMON to emit in BSS. */
29515 DECL_COMMON (decl
) = 1;
29516 return tls_comm_section
;
29519 return tls_private_data_section
;
29523 if (TREE_PUBLIC (decl
))
29524 return data_section
;
29526 return private_data_section
;
29531 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
29535 /* Use select_section for private data and uninitialized data with
29536 alignment <= BIGGEST_ALIGNMENT. */
29537 if (!TREE_PUBLIC (decl
)
29538 || DECL_COMMON (decl
)
29539 || (DECL_INITIAL (decl
) == NULL_TREE
29540 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
29541 || DECL_INITIAL (decl
) == error_mark_node
29542 || (flag_zero_initialized_in_bss
29543 && initializer_zerop (DECL_INITIAL (decl
))))
29546 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
29547 name
= (*targetm
.strip_name_encoding
) (name
);
29548 set_decl_section_name (decl
, name
);
29551 /* Select section for constant in constant pool.
29553 On RS/6000, all constants are in the private read-only data area.
29554 However, if this is being placed in the TOC it must be output as a
29558 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
29559 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
29561 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
29562 return toc_section
;
29564 return read_only_private_data_section
;
29567 /* Remove any trailing [DS] or the like from the symbol name. */
29569 static const char *
29570 rs6000_xcoff_strip_name_encoding (const char *name
)
29575 len
= strlen (name
);
29576 if (name
[len
- 1] == ']')
29577 return ggc_alloc_string (name
, len
- 4);
29582 /* Section attributes. AIX is always PIC. */
29584 static unsigned int
29585 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
29587 unsigned int align
;
29588 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
29590 /* Align to at least UNIT size. */
29591 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
29592 align
= MIN_UNITS_PER_WORD
;
29594 /* Increase alignment of large objects if not already stricter. */
29595 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
29596 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
29597 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
29599 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
29602 /* Output at beginning of assembler file.
29604 Initialize the section names for the RS/6000 at this point.
29606 Specify filename, including full path, to assembler.
29608 We want to go into the TOC section so at least one .toc will be emitted.
29609 Also, in order to output proper .bs/.es pairs, we need at least one static
29610 [RW] section emitted.
29612 Finally, declare mcount when profiling to make the assembler happy. */
29615 rs6000_xcoff_file_start (void)
29617 rs6000_gen_section_name (&xcoff_bss_section_name
,
29618 main_input_filename
, ".bss_");
29619 rs6000_gen_section_name (&xcoff_private_data_section_name
,
29620 main_input_filename
, ".rw_");
29621 rs6000_gen_section_name (&xcoff_read_only_section_name
,
29622 main_input_filename
, ".ro_");
29623 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
29624 main_input_filename
, ".tls_");
29625 rs6000_gen_section_name (&xcoff_tbss_section_name
,
29626 main_input_filename
, ".tbss_[UL]");
29628 fputs ("\t.file\t", asm_out_file
);
29629 output_quoted_string (asm_out_file
, main_input_filename
);
29630 fputc ('\n', asm_out_file
);
29631 if (write_symbols
!= NO_DEBUG
)
29632 switch_to_section (private_data_section
);
29633 switch_to_section (text_section
);
29635 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
29636 rs6000_file_start ();
29639 /* Output at end of assembler file.
29640 On the RS/6000, referencing data should automatically pull in text. */
29643 rs6000_xcoff_file_end (void)
29645 switch_to_section (text_section
);
29646 fputs ("_section_.text:\n", asm_out_file
);
29647 switch_to_section (data_section
);
29648 fputs (TARGET_32BIT
29649 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
29653 struct declare_alias_data
29656 bool function_descriptor
;
29659 /* Declare alias N. A helper function for for_node_and_aliases. */
29662 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
29664 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
29665 /* Main symbol is output specially, because varasm machinery does part of
29666 the job for us - we do not need to declare .globl/lglobs and such. */
29667 if (!n
->alias
|| n
->weakref
)
29670 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
29673 /* Prevent assemble_alias from trying to use .set pseudo operation
29674 that does not behave as expected by the middle-end. */
29675 TREE_ASM_WRITTEN (n
->decl
) = true;
29677 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
29678 char *buffer
= (char *) alloca (strlen (name
) + 2);
29680 int dollar_inside
= 0;
29682 strcpy (buffer
, name
);
29683 p
= strchr (buffer
, '$');
29687 p
= strchr (p
+ 1, '$');
29689 if (TREE_PUBLIC (n
->decl
))
29691 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
29693 if (dollar_inside
) {
29694 if (data
->function_descriptor
)
29695 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
29697 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
29699 if (data
->function_descriptor
)
29700 fputs ("\t.globl .", data
->file
);
29702 fputs ("\t.globl ", data
->file
);
29703 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
29704 putc ('\n', data
->file
);
29706 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
29707 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
29713 if (data
->function_descriptor
)
29714 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
29716 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
29718 if (data
->function_descriptor
)
29719 fputs ("\t.lglobl .", data
->file
);
29721 fputs ("\t.lglobl ", data
->file
);
29722 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
29723 putc ('\n', data
->file
);
29725 if (data
->function_descriptor
)
29726 fputs (".", data
->file
);
29727 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
29728 fputs (":\n", data
->file
);
29732 /* This macro produces the initial definition of a function name.
29733 On the RS/6000, we need to place an extra '.' in the function name and
29734 output the function descriptor.
29735 Dollar signs are converted to underscores.
29737 The csect for the function will have already been created when
29738 text_section was selected. We do have to go back to that csect, however.
29740 The third and fourth parameters to the .function pseudo-op (16 and 044)
29741 are placeholders which no longer have any use.
29743 Because AIX assembler's .set command has unexpected semantics, we output
29744 all aliases as alternative labels in front of the definition. */
29747 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
29749 char *buffer
= (char *) alloca (strlen (name
) + 1);
29751 int dollar_inside
= 0;
29752 struct declare_alias_data data
= {file
, false};
29754 strcpy (buffer
, name
);
29755 p
= strchr (buffer
, '$');
29759 p
= strchr (p
+ 1, '$');
29761 if (TREE_PUBLIC (decl
))
29763 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
29765 if (dollar_inside
) {
29766 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
29767 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
29769 fputs ("\t.globl .", file
);
29770 RS6000_OUTPUT_BASENAME (file
, buffer
);
29776 if (dollar_inside
) {
29777 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
29778 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
29780 fputs ("\t.lglobl .", file
);
29781 RS6000_OUTPUT_BASENAME (file
, buffer
);
29784 fputs ("\t.csect ", file
);
29785 RS6000_OUTPUT_BASENAME (file
, buffer
);
29786 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
29787 RS6000_OUTPUT_BASENAME (file
, buffer
);
29788 fputs (":\n", file
);
29789 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
29790 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
29791 RS6000_OUTPUT_BASENAME (file
, buffer
);
29792 fputs (", TOC[tc0], 0\n", file
);
29794 switch_to_section (function_section (decl
));
29796 RS6000_OUTPUT_BASENAME (file
, buffer
);
29797 fputs (":\n", file
);
29798 data
.function_descriptor
= true;
29799 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
29800 if (write_symbols
!= NO_DEBUG
&& !DECL_IGNORED_P (decl
))
29801 xcoffout_declare_function (file
, decl
, buffer
);
29805 /* This macro produces the initial definition of a object (variable) name.
29806 Because AIX assembler's .set command has unexpected semantics, we output
29807 all aliases as alternative labels in front of the definition. */
29810 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
29812 struct declare_alias_data data
= {file
, false};
29813 RS6000_OUTPUT_BASENAME (file
, name
);
29814 fputs (":\n", file
);
29815 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
29820 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
29825 default_encode_section_info (decl
, rtl
, first
);
29827 /* Careful not to prod global register variables. */
29830 symbol
= XEXP (rtl
, 0);
29831 if (GET_CODE (symbol
) != SYMBOL_REF
)
29834 flags
= SYMBOL_REF_FLAGS (symbol
);
29836 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29837 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
29839 SYMBOL_REF_FLAGS (symbol
) = flags
;
29841 #endif /* HAVE_AS_TLS */
29842 #endif /* TARGET_XCOFF */
29844 /* Compute a (partial) cost for rtx X. Return true if the complete
29845 cost has been computed, and false if subexpressions should be
29846 scanned. In either case, *TOTAL contains the cost result. */
29849 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
29850 int *total
, bool speed
)
29852 enum machine_mode mode
= GET_MODE (x
);
29856 /* On the RS/6000, if it is valid in the insn, it is free. */
29858 if (((outer_code
== SET
29859 || outer_code
== PLUS
29860 || outer_code
== MINUS
)
29861 && (satisfies_constraint_I (x
)
29862 || satisfies_constraint_L (x
)))
29863 || (outer_code
== AND
29864 && (satisfies_constraint_K (x
)
29866 ? satisfies_constraint_L (x
)
29867 : satisfies_constraint_J (x
))
29868 || mask_operand (x
, mode
)
29870 && mask64_operand (x
, DImode
))))
29871 || ((outer_code
== IOR
|| outer_code
== XOR
)
29872 && (satisfies_constraint_K (x
)
29874 ? satisfies_constraint_L (x
)
29875 : satisfies_constraint_J (x
))))
29876 || outer_code
== ASHIFT
29877 || outer_code
== ASHIFTRT
29878 || outer_code
== LSHIFTRT
29879 || outer_code
== ROTATE
29880 || outer_code
== ROTATERT
29881 || outer_code
== ZERO_EXTRACT
29882 || (outer_code
== MULT
29883 && satisfies_constraint_I (x
))
29884 || ((outer_code
== DIV
|| outer_code
== UDIV
29885 || outer_code
== MOD
|| outer_code
== UMOD
)
29886 && exact_log2 (INTVAL (x
)) >= 0)
29887 || (outer_code
== COMPARE
29888 && (satisfies_constraint_I (x
)
29889 || satisfies_constraint_K (x
)))
29890 || ((outer_code
== EQ
|| outer_code
== NE
)
29891 && (satisfies_constraint_I (x
)
29892 || satisfies_constraint_K (x
)
29894 ? satisfies_constraint_L (x
)
29895 : satisfies_constraint_J (x
))))
29896 || (outer_code
== GTU
29897 && satisfies_constraint_I (x
))
29898 || (outer_code
== LTU
29899 && satisfies_constraint_P (x
)))
29904 else if ((outer_code
== PLUS
29905 && reg_or_add_cint_operand (x
, VOIDmode
))
29906 || (outer_code
== MINUS
29907 && reg_or_sub_cint_operand (x
, VOIDmode
))
29908 || ((outer_code
== SET
29909 || outer_code
== IOR
29910 || outer_code
== XOR
)
29912 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
29914 *total
= COSTS_N_INSNS (1);
29920 case CONST_WIDE_INT
:
29925 /* When optimizing for size, MEM should be slightly more expensive
29926 than generating address, e.g., (plus (reg) (const)).
29927 L1 cache latency is about two instructions. */
29928 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
29937 if (FLOAT_MODE_P (mode
))
29938 *total
= rs6000_cost
->fp
;
29940 *total
= COSTS_N_INSNS (1);
29944 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29945 && satisfies_constraint_I (XEXP (x
, 1)))
29947 if (INTVAL (XEXP (x
, 1)) >= -256
29948 && INTVAL (XEXP (x
, 1)) <= 255)
29949 *total
= rs6000_cost
->mulsi_const9
;
29951 *total
= rs6000_cost
->mulsi_const
;
29953 else if (mode
== SFmode
)
29954 *total
= rs6000_cost
->fp
;
29955 else if (FLOAT_MODE_P (mode
))
29956 *total
= rs6000_cost
->dmul
;
29957 else if (mode
== DImode
)
29958 *total
= rs6000_cost
->muldi
;
29960 *total
= rs6000_cost
->mulsi
;
29964 if (mode
== SFmode
)
29965 *total
= rs6000_cost
->fp
;
29967 *total
= rs6000_cost
->dmul
;
29972 if (FLOAT_MODE_P (mode
))
29974 *total
= mode
== DFmode
? rs6000_cost
->ddiv
29975 : rs6000_cost
->sdiv
;
29982 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29983 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
29985 if (code
== DIV
|| code
== MOD
)
29987 *total
= COSTS_N_INSNS (2);
29990 *total
= COSTS_N_INSNS (1);
29994 if (GET_MODE (XEXP (x
, 1)) == DImode
)
29995 *total
= rs6000_cost
->divdi
;
29997 *total
= rs6000_cost
->divsi
;
29999 /* Add in shift and subtract for MOD. */
30000 if (code
== MOD
|| code
== UMOD
)
30001 *total
+= COSTS_N_INSNS (2);
30006 *total
= COSTS_N_INSNS (4);
30010 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
30014 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
30018 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
30030 *total
= COSTS_N_INSNS (1);
30038 /* Handle mul_highpart. */
30039 if (outer_code
== TRUNCATE
30040 && GET_CODE (XEXP (x
, 0)) == MULT
)
30042 if (mode
== DImode
)
30043 *total
= rs6000_cost
->muldi
;
30045 *total
= rs6000_cost
->mulsi
;
30048 else if (outer_code
== AND
)
30051 *total
= COSTS_N_INSNS (1);
30056 if (GET_CODE (XEXP (x
, 0)) == MEM
)
30059 *total
= COSTS_N_INSNS (1);
30065 if (!FLOAT_MODE_P (mode
))
30067 *total
= COSTS_N_INSNS (1);
30073 case UNSIGNED_FLOAT
:
30076 case FLOAT_TRUNCATE
:
30077 *total
= rs6000_cost
->fp
;
30081 if (mode
== DFmode
)
30084 *total
= rs6000_cost
->fp
;
30088 switch (XINT (x
, 1))
30091 *total
= rs6000_cost
->fp
;
30103 *total
= COSTS_N_INSNS (1);
30106 else if (FLOAT_MODE_P (mode
)
30107 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30109 *total
= rs6000_cost
->fp
;
30118 /* Carry bit requires mode == Pmode.
30119 NEG or PLUS already counted so only add one. */
30121 && (outer_code
== NEG
|| outer_code
== PLUS
))
30123 *total
= COSTS_N_INSNS (1);
30126 if (outer_code
== SET
)
30128 if (XEXP (x
, 1) == const0_rtx
)
30130 if (TARGET_ISEL
&& !TARGET_MFCRF
)
30131 *total
= COSTS_N_INSNS (8);
30133 *total
= COSTS_N_INSNS (2);
30136 else if (mode
== Pmode
)
30138 *total
= COSTS_N_INSNS (3);
30147 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
30149 if (TARGET_ISEL
&& !TARGET_MFCRF
)
30150 *total
= COSTS_N_INSNS (8);
30152 *total
= COSTS_N_INSNS (2);
30156 if (outer_code
== COMPARE
)
30170 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
30173 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
30176 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
30179 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
30180 "opno = %d, total = %d, speed = %s, x:\n",
30181 ret
? "complete" : "scan inner",
30182 GET_RTX_NAME (code
),
30183 GET_RTX_NAME (outer_code
),
30186 speed
? "true" : "false");
30193 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
30196 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
30197 addr_space_t as
, bool speed
)
30199 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
30201 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
30202 ret
, speed
? "true" : "false");
30209 /* A C expression returning the cost of moving data from a register of class
30210 CLASS1 to one of CLASS2. */
30213 rs6000_register_move_cost (enum machine_mode mode
,
30214 reg_class_t from
, reg_class_t to
)
30218 if (TARGET_DEBUG_COST
)
30221 /* Moves from/to GENERAL_REGS. */
30222 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
30223 || reg_classes_intersect_p (from
, GENERAL_REGS
))
30225 reg_class_t rclass
= from
;
30227 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
30230 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
30231 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
30232 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
30234 /* It's more expensive to move CR_REGS than CR0_REGS because of the
30236 else if (rclass
== CR_REGS
)
30239 /* For those processors that have slow LR/CTR moves, make them more
30240 expensive than memory in order to bias spills to memory .*/
30241 else if ((rs6000_cpu
== PROCESSOR_POWER6
30242 || rs6000_cpu
== PROCESSOR_POWER7
30243 || rs6000_cpu
== PROCESSOR_POWER8
)
30244 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
30245 ret
= 6 * hard_regno_nregs
[0][mode
];
30248 /* A move will cost one instruction per GPR moved. */
30249 ret
= 2 * hard_regno_nregs
[0][mode
];
30252 /* If we have VSX, we can easily move between FPR or Altivec registers. */
30253 else if (VECTOR_MEM_VSX_P (mode
)
30254 && reg_classes_intersect_p (to
, VSX_REGS
)
30255 && reg_classes_intersect_p (from
, VSX_REGS
))
30256 ret
= 2 * hard_regno_nregs
[32][mode
];
30258 /* Moving between two similar registers is just one instruction. */
30259 else if (reg_classes_intersect_p (to
, from
))
30260 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
30262 /* Everything else has to go through GENERAL_REGS. */
30264 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
30265 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
30267 if (TARGET_DEBUG_COST
)
30269 if (dbg_cost_ctrl
== 1)
30271 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
30272 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
30273 reg_class_names
[to
]);
30280 /* A C expressions returning the cost of moving data of MODE from a register to
30284 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
30285 bool in ATTRIBUTE_UNUSED
)
30289 if (TARGET_DEBUG_COST
)
30292 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
30293 ret
= 4 * hard_regno_nregs
[0][mode
];
30294 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
30295 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
30296 ret
= 4 * hard_regno_nregs
[32][mode
];
30297 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
30298 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
30300 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
30302 if (TARGET_DEBUG_COST
)
30304 if (dbg_cost_ctrl
== 1)
30306 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
30307 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
30314 /* Returns a code for a target-specific builtin that implements
30315 reciprocal of the function, or NULL_TREE if not available. */
30318 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
30319 bool sqrt ATTRIBUTE_UNUSED
)
30321 if (optimize_insn_for_size_p ())
30327 case VSX_BUILTIN_XVSQRTDP
:
30328 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
30331 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
30333 case VSX_BUILTIN_XVSQRTSP
:
30334 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
30337 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
30346 case BUILT_IN_SQRT
:
30347 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
30350 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
30352 case BUILT_IN_SQRTF
:
30353 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
30356 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
30363 /* Load up a constant. If the mode is a vector mode, splat the value across
30364 all of the vector elements. */
30367 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
30371 if (mode
== SFmode
|| mode
== DFmode
)
30373 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
30374 reg
= force_reg (mode
, d
);
30376 else if (mode
== V4SFmode
)
30378 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
30379 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
30380 reg
= gen_reg_rtx (mode
);
30381 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30383 else if (mode
== V2DFmode
)
30385 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
30386 rtvec v
= gen_rtvec (2, d
, d
);
30387 reg
= gen_reg_rtx (mode
);
30388 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30391 gcc_unreachable ();
30396 /* Generate an FMA instruction. */
30399 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
30401 enum machine_mode mode
= GET_MODE (target
);
30404 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30405 gcc_assert (dst
!= NULL
);
30408 emit_move_insn (target
, dst
);
30411 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
30414 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
30416 enum machine_mode mode
= GET_MODE (target
);
30419 /* Altivec does not support fms directly;
30420 generate in terms of fma in that case. */
30421 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
30422 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
30425 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
30426 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30428 gcc_assert (dst
!= NULL
);
30431 emit_move_insn (target
, dst
);
30434 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
30437 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
30439 enum machine_mode mode
= GET_MODE (dst
);
30442 /* This is a tad more complicated, since the fnma_optab is for
30443 a different expression: fma(-m1, m2, a), which is the same
30444 thing except in the case of signed zeros.
30446 Fortunately we know that if FMA is supported that FNMSUB is
30447 also supported in the ISA. Just expand it directly. */
30449 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
30451 r
= gen_rtx_NEG (mode
, a
);
30452 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
30453 r
= gen_rtx_NEG (mode
, r
);
30454 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
30457 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
30458 add a reg_note saying that this was a division. Support both scalar and
30459 vector divide. Assumes no trapping math and finite arguments. */
30462 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
30464 enum machine_mode mode
= GET_MODE (dst
);
30465 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
30468 /* Low precision estimates guarantee 5 bits of accuracy. High
30469 precision estimates guarantee 14 bits of accuracy. SFmode
30470 requires 23 bits of accuracy. DFmode requires 52 bits of
30471 accuracy. Each pass at least doubles the accuracy, leading
30472 to the following. */
30473 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30474 if (mode
== DFmode
|| mode
== V2DFmode
)
30477 enum insn_code code
= optab_handler (smul_optab
, mode
);
30478 insn_gen_fn gen_mul
= GEN_FCN (code
);
30480 gcc_assert (code
!= CODE_FOR_nothing
);
30482 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
30484 /* x0 = 1./d estimate */
30485 x0
= gen_reg_rtx (mode
);
30486 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30487 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
30490 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
30493 /* e0 = 1. - d * x0 */
30494 e0
= gen_reg_rtx (mode
);
30495 rs6000_emit_nmsub (e0
, d
, x0
, one
);
30497 /* x1 = x0 + e0 * x0 */
30498 x1
= gen_reg_rtx (mode
);
30499 rs6000_emit_madd (x1
, e0
, x0
, x0
);
30501 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
30502 ++i
, xprev
= xnext
, eprev
= enext
) {
30504 /* enext = eprev * eprev */
30505 enext
= gen_reg_rtx (mode
);
30506 emit_insn (gen_mul (enext
, eprev
, eprev
));
30508 /* xnext = xprev + enext * xprev */
30509 xnext
= gen_reg_rtx (mode
);
30510 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
30516 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
30518 /* u = n * xprev */
30519 u
= gen_reg_rtx (mode
);
30520 emit_insn (gen_mul (u
, n
, xprev
));
30522 /* v = n - (d * u) */
30523 v
= gen_reg_rtx (mode
);
30524 rs6000_emit_nmsub (v
, d
, u
, n
);
30526 /* dst = (v * xprev) + u */
30527 rs6000_emit_madd (dst
, v
, xprev
, u
);
30530 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
30533 /* Newton-Raphson approximation of single/double-precision floating point
30534 rsqrt. Assumes no trapping math and finite arguments. */
30537 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
30539 enum machine_mode mode
= GET_MODE (src
);
30540 rtx x0
= gen_reg_rtx (mode
);
30541 rtx y
= gen_reg_rtx (mode
);
30543 /* Low precision estimates guarantee 5 bits of accuracy. High
30544 precision estimates guarantee 14 bits of accuracy. SFmode
30545 requires 23 bits of accuracy. DFmode requires 52 bits of
30546 accuracy. Each pass at least doubles the accuracy, leading
30547 to the following. */
30548 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30549 if (mode
== DFmode
|| mode
== V2DFmode
)
30552 REAL_VALUE_TYPE dconst3_2
;
30555 enum insn_code code
= optab_handler (smul_optab
, mode
);
30556 insn_gen_fn gen_mul
= GEN_FCN (code
);
30558 gcc_assert (code
!= CODE_FOR_nothing
);
30560 /* Load up the constant 1.5 either as a scalar, or as a vector. */
30561 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
30562 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
30564 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
30566 /* x0 = rsqrt estimate */
30567 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30568 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
30571 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
30572 rs6000_emit_msub (y
, src
, halfthree
, src
);
30574 for (i
= 0; i
< passes
; i
++)
30576 rtx x1
= gen_reg_rtx (mode
);
30577 rtx u
= gen_reg_rtx (mode
);
30578 rtx v
= gen_reg_rtx (mode
);
30580 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
30581 emit_insn (gen_mul (u
, x0
, x0
));
30582 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
30583 emit_insn (gen_mul (x1
, x0
, v
));
30587 emit_move_insn (dst
, x0
);
30591 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
30592 (Power7) targets. DST is the target, and SRC is the argument operand. */
30595 rs6000_emit_popcount (rtx dst
, rtx src
)
30597 enum machine_mode mode
= GET_MODE (dst
);
30600 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
30601 if (TARGET_POPCNTD
)
30603 if (mode
== SImode
)
30604 emit_insn (gen_popcntdsi2 (dst
, src
));
30606 emit_insn (gen_popcntddi2 (dst
, src
));
30610 tmp1
= gen_reg_rtx (mode
);
30612 if (mode
== SImode
)
30614 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30615 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
30617 tmp2
= force_reg (SImode
, tmp2
);
30618 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
30622 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30623 tmp2
= expand_mult (DImode
, tmp1
,
30624 GEN_INT ((HOST_WIDE_INT
)
30625 0x01010101 << 32 | 0x01010101),
30627 tmp2
= force_reg (DImode
, tmp2
);
30628 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
30633 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
30634 target, and SRC is the argument operand. */
30637 rs6000_emit_parity (rtx dst
, rtx src
)
30639 enum machine_mode mode
= GET_MODE (dst
);
30642 tmp
= gen_reg_rtx (mode
);
30644 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
30647 if (mode
== SImode
)
30649 emit_insn (gen_popcntbsi2 (tmp
, src
));
30650 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
30654 emit_insn (gen_popcntbdi2 (tmp
, src
));
30655 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
30660 if (mode
== SImode
)
30662 /* Is mult+shift >= shift+xor+shift+xor? */
30663 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
30665 rtx tmp1
, tmp2
, tmp3
, tmp4
;
30667 tmp1
= gen_reg_rtx (SImode
);
30668 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30670 tmp2
= gen_reg_rtx (SImode
);
30671 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
30672 tmp3
= gen_reg_rtx (SImode
);
30673 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
30675 tmp4
= gen_reg_rtx (SImode
);
30676 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
30677 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
30680 rs6000_emit_popcount (tmp
, src
);
30681 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
30685 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
30686 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
30688 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
30690 tmp1
= gen_reg_rtx (DImode
);
30691 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30693 tmp2
= gen_reg_rtx (DImode
);
30694 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
30695 tmp3
= gen_reg_rtx (DImode
);
30696 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
30698 tmp4
= gen_reg_rtx (DImode
);
30699 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
30700 tmp5
= gen_reg_rtx (DImode
);
30701 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
30703 tmp6
= gen_reg_rtx (DImode
);
30704 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
30705 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
30708 rs6000_emit_popcount (tmp
, src
);
30709 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
30713 /* Expand an Altivec constant permutation for little endian mode.
30714 There are two issues: First, the two input operands must be
30715 swapped so that together they form a double-wide array in LE
30716 order. Second, the vperm instruction has surprising behavior
30717 in LE mode: it interprets the elements of the source vectors
30718 in BE mode ("left to right") and interprets the elements of
30719 the destination vector in LE mode ("right to left"). To
30720 correct for this, we must subtract each element of the permute
30721 control vector from 31.
30723 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
30724 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
30725 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
30726 serve as the permute control vector. Then, in BE mode,
30730 places the desired result in vr9. However, in LE mode the
30731 vector contents will be
30733 vr10 = 00000003 00000002 00000001 00000000
30734 vr11 = 00000007 00000006 00000005 00000004
30736 The result of the vperm using the same permute control vector is
30738 vr9 = 05000000 07000000 01000000 03000000
30740 That is, the leftmost 4 bytes of vr10 are interpreted as the
30741 source for the rightmost 4 bytes of vr9, and so on.
30743 If we change the permute control vector to
30745 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
30753 vr9 = 00000006 00000004 00000002 00000000. */
30756 altivec_expand_vec_perm_const_le (rtx operands
[4])
30760 rtx constv
, unspec
;
30761 rtx target
= operands
[0];
30762 rtx op0
= operands
[1];
30763 rtx op1
= operands
[2];
30764 rtx sel
= operands
[3];
30766 /* Unpack and adjust the constant selector. */
30767 for (i
= 0; i
< 16; ++i
)
30769 rtx e
= XVECEXP (sel
, 0, i
);
30770 unsigned int elt
= 31 - (INTVAL (e
) & 31);
30771 perm
[i
] = GEN_INT (elt
);
30774 /* Expand to a permute, swapping the inputs and using the
30775 adjusted selector. */
30777 op0
= force_reg (V16QImode
, op0
);
30779 op1
= force_reg (V16QImode
, op1
);
30781 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
30782 constv
= force_reg (V16QImode
, constv
);
30783 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
30785 if (!REG_P (target
))
30787 rtx tmp
= gen_reg_rtx (V16QImode
);
30788 emit_move_insn (tmp
, unspec
);
30792 emit_move_insn (target
, unspec
);
30795 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
30796 permute control vector. But here it's not a constant, so we must
30797 generate a vector NAND or NOR to do the adjustment. */
30800 altivec_expand_vec_perm_le (rtx operands
[4])
30802 rtx notx
, iorx
, unspec
;
30803 rtx target
= operands
[0];
30804 rtx op0
= operands
[1];
30805 rtx op1
= operands
[2];
30806 rtx sel
= operands
[3];
30808 rtx norreg
= gen_reg_rtx (V16QImode
);
30809 enum machine_mode mode
= GET_MODE (target
);
30811 /* Get everything in regs so the pattern matches. */
30813 op0
= force_reg (mode
, op0
);
30815 op1
= force_reg (mode
, op1
);
30817 sel
= force_reg (V16QImode
, sel
);
30818 if (!REG_P (target
))
30819 tmp
= gen_reg_rtx (mode
);
30821 /* Invert the selector with a VNAND if available, else a VNOR.
30822 The VNAND is preferred for future fusion opportunities. */
30823 notx
= gen_rtx_NOT (V16QImode
, sel
);
30824 iorx
= (TARGET_P8_VECTOR
30825 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
30826 : gen_rtx_AND (V16QImode
, notx
, notx
));
30827 emit_insn (gen_rtx_SET (VOIDmode
, norreg
, iorx
));
30829 /* Permute with operands reversed and adjusted selector. */
30830 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
30833 /* Copy into target, possibly by way of a register. */
30834 if (!REG_P (target
))
30836 emit_move_insn (tmp
, unspec
);
30840 emit_move_insn (target
, unspec
);
30843 /* Expand an Altivec constant permutation. Return true if we match
30844 an efficient implementation; false to fall back to VPERM. */
30847 altivec_expand_vec_perm_const (rtx operands
[4])
30849 struct altivec_perm_insn
{
30850 HOST_WIDE_INT mask
;
30851 enum insn_code impl
;
30852 unsigned char perm
[16];
30854 static const struct altivec_perm_insn patterns
[] = {
30855 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
30856 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
30857 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
30858 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
30859 { OPTION_MASK_ALTIVEC
,
30860 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
30861 : CODE_FOR_altivec_vmrglb_direct
),
30862 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
30863 { OPTION_MASK_ALTIVEC
,
30864 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
30865 : CODE_FOR_altivec_vmrglh_direct
),
30866 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
30867 { OPTION_MASK_ALTIVEC
,
30868 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
30869 : CODE_FOR_altivec_vmrglw_direct
),
30870 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
30871 { OPTION_MASK_ALTIVEC
,
30872 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
30873 : CODE_FOR_altivec_vmrghb_direct
),
30874 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
30875 { OPTION_MASK_ALTIVEC
,
30876 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
30877 : CODE_FOR_altivec_vmrghh_direct
),
30878 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
30879 { OPTION_MASK_ALTIVEC
,
30880 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
30881 : CODE_FOR_altivec_vmrghw_direct
),
30882 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
30883 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
30884 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
30885 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
30886 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
30889 unsigned int i
, j
, elt
, which
;
30890 unsigned char perm
[16];
30891 rtx target
, op0
, op1
, sel
, x
;
30894 target
= operands
[0];
30899 /* Unpack the constant selector. */
30900 for (i
= which
= 0; i
< 16; ++i
)
30902 rtx e
= XVECEXP (sel
, 0, i
);
30903 elt
= INTVAL (e
) & 31;
30904 which
|= (elt
< 16 ? 1 : 2);
30908 /* Simplify the constant selector based on operands. */
30912 gcc_unreachable ();
30916 if (!rtx_equal_p (op0
, op1
))
30921 for (i
= 0; i
< 16; ++i
)
30933 /* Look for splat patterns. */
30938 for (i
= 0; i
< 16; ++i
)
30939 if (perm
[i
] != elt
)
30943 if (!BYTES_BIG_ENDIAN
)
30945 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
30951 for (i
= 0; i
< 16; i
+= 2)
30952 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
30956 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
30957 x
= gen_reg_rtx (V8HImode
);
30958 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
30960 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30967 for (i
= 0; i
< 16; i
+= 4)
30969 || perm
[i
+ 1] != elt
+ 1
30970 || perm
[i
+ 2] != elt
+ 2
30971 || perm
[i
+ 3] != elt
+ 3)
30975 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
30976 x
= gen_reg_rtx (V4SImode
);
30977 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
30979 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30985 /* Look for merge and pack patterns. */
30986 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
30990 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
30993 elt
= patterns
[j
].perm
[0];
30994 if (perm
[0] == elt
)
30996 else if (perm
[0] == elt
+ 16)
31000 for (i
= 1; i
< 16; ++i
)
31002 elt
= patterns
[j
].perm
[i
];
31004 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
31005 else if (one_vec
&& elt
>= 16)
31007 if (perm
[i
] != elt
)
31012 enum insn_code icode
= patterns
[j
].impl
;
31013 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
31014 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
31016 /* For little-endian, don't use vpkuwum and vpkuhum if the
31017 underlying vector type is not V4SI and V8HI, respectively.
31018 For example, using vpkuwum with a V8HI picks up the even
31019 halfwords (BE numbering) when the even halfwords (LE
31020 numbering) are what we need. */
31021 if (!BYTES_BIG_ENDIAN
31022 && icode
== CODE_FOR_altivec_vpkuwum_direct
31023 && ((GET_CODE (op0
) == REG
31024 && GET_MODE (op0
) != V4SImode
)
31025 || (GET_CODE (op0
) == SUBREG
31026 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
31028 if (!BYTES_BIG_ENDIAN
31029 && icode
== CODE_FOR_altivec_vpkuhum_direct
31030 && ((GET_CODE (op0
) == REG
31031 && GET_MODE (op0
) != V8HImode
)
31032 || (GET_CODE (op0
) == SUBREG
31033 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
31036 /* For little-endian, the two input operands must be swapped
31037 (or swapped back) to ensure proper right-to-left numbering
31039 if (swapped
^ !BYTES_BIG_ENDIAN
)
31040 x
= op0
, op0
= op1
, op1
= x
;
31041 if (imode
!= V16QImode
)
31043 op0
= gen_lowpart (imode
, op0
);
31044 op1
= gen_lowpart (imode
, op1
);
31046 if (omode
== V16QImode
)
31049 x
= gen_reg_rtx (omode
);
31050 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
31051 if (omode
!= V16QImode
)
31052 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
31057 if (!BYTES_BIG_ENDIAN
)
31059 altivec_expand_vec_perm_const_le (operands
);
31066 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
31067 Return true if we match an efficient implementation. */
31070 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
31071 unsigned char perm0
, unsigned char perm1
)
31075 /* If both selectors come from the same operand, fold to single op. */
31076 if ((perm0
& 2) == (perm1
& 2))
31083 /* If both operands are equal, fold to simpler permutation. */
31084 if (rtx_equal_p (op0
, op1
))
31087 perm1
= (perm1
& 1) + 2;
31089 /* If the first selector comes from the second operand, swap. */
31090 else if (perm0
& 2)
31096 x
= op0
, op0
= op1
, op1
= x
;
31098 /* If the second selector does not come from the second operand, fail. */
31099 else if ((perm1
& 2) == 0)
31103 if (target
!= NULL
)
31105 enum machine_mode vmode
, dmode
;
31108 vmode
= GET_MODE (target
);
31109 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
31110 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
31111 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
31112 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
31113 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
31114 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
31120 rs6000_expand_vec_perm_const (rtx operands
[4])
31122 rtx target
, op0
, op1
, sel
;
31123 unsigned char perm0
, perm1
;
31125 target
= operands
[0];
31130 /* Unpack the constant selector. */
31131 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
31132 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
31134 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
31137 /* Test whether a constant permutation is supported. */
31140 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
31141 const unsigned char *sel
)
31143 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
31144 if (TARGET_ALTIVEC
)
31147 /* Check for ps_merge* or evmerge* insns. */
31148 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
31149 || (TARGET_SPE
&& vmode
== V2SImode
))
31151 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
31152 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
31153 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
31159 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
31162 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
31163 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
31165 enum machine_mode imode
;
31169 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
31171 imode
= GET_MODE_INNER (vmode
);
31172 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
31173 imode
= mode_for_vector (imode
, nelt
);
31176 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
31177 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
31179 emit_move_insn (target
, x
);
31182 /* Expand an extract even operation. */
31185 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
31187 enum machine_mode vmode
= GET_MODE (target
);
31188 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
31191 for (i
= 0; i
< nelt
; i
++)
31192 perm
[i
] = GEN_INT (i
* 2);
31194 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
31197 /* Expand a vector interleave operation. */
31200 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
31202 enum machine_mode vmode
= GET_MODE (target
);
31203 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
31206 high
= (highp
? 0 : nelt
/ 2);
31207 for (i
= 0; i
< nelt
/ 2; i
++)
31209 perm
[i
* 2] = GEN_INT (i
+ high
);
31210 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
31213 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
31216 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
31218 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
31220 HOST_WIDE_INT
hwi_scale (scale
);
31221 REAL_VALUE_TYPE r_pow
;
31222 rtvec v
= rtvec_alloc (2);
31224 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
31225 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
31226 elt
= CONST_DOUBLE_FROM_REAL_VALUE (r_pow
, DFmode
);
31227 RTVEC_ELT (v
, 0) = elt
;
31228 RTVEC_ELT (v
, 1) = elt
;
31229 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
31230 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
31233 /* Return an RTX representing where to find the function value of a
31234 function returning MODE. */
31236 rs6000_complex_function_value (enum machine_mode mode
)
31238 unsigned int regno
;
31240 enum machine_mode inner
= GET_MODE_INNER (mode
);
31241 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
31243 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31244 regno
= FP_ARG_RETURN
;
31247 regno
= GP_ARG_RETURN
;
31249 /* 32-bit is OK since it'll go in r3/r4. */
31250 if (TARGET_32BIT
&& inner_bytes
>= 4)
31251 return gen_rtx_REG (mode
, regno
);
31254 if (inner_bytes
>= 8)
31255 return gen_rtx_REG (mode
, regno
);
31257 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
31259 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
31260 GEN_INT (inner_bytes
));
31261 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
31264 /* Target hook for TARGET_FUNCTION_VALUE.
31266 On the SPE, both FPs and vectors are returned in r3.
31268 On RS/6000 an integer value is in r3 and a floating-point value is in
31269 fp1, unless -msoft-float. */
31272 rs6000_function_value (const_tree valtype
,
31273 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
31274 bool outgoing ATTRIBUTE_UNUSED
)
31276 enum machine_mode mode
;
31277 unsigned int regno
;
31278 enum machine_mode elt_mode
;
31281 /* Special handling for structs in darwin64. */
31283 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
31285 CUMULATIVE_ARGS valcum
;
31289 valcum
.fregno
= FP_ARG_MIN_REG
;
31290 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
31291 /* Do a trial code generation as if this were going to be passed as
31292 an argument; if any part goes in memory, we return NULL. */
31293 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
31296 /* Otherwise fall through to standard ABI rules. */
31299 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
31300 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
31301 &elt_mode
, &n_elts
))
31303 int first_reg
, n_regs
, i
;
31306 if (SCALAR_FLOAT_MODE_P (elt_mode
))
31308 /* _Decimal128 must use even/odd register pairs. */
31309 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31310 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
31314 first_reg
= ALTIVEC_ARG_RETURN
;
31318 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
31319 for (i
= 0; i
< n_elts
; i
++)
31321 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
31322 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
31323 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
31329 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
31331 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31332 return gen_rtx_PARALLEL (DImode
,
31334 gen_rtx_EXPR_LIST (VOIDmode
,
31335 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31337 gen_rtx_EXPR_LIST (VOIDmode
,
31338 gen_rtx_REG (SImode
,
31339 GP_ARG_RETURN
+ 1),
31342 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
31344 return gen_rtx_PARALLEL (DCmode
,
31346 gen_rtx_EXPR_LIST (VOIDmode
,
31347 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31349 gen_rtx_EXPR_LIST (VOIDmode
,
31350 gen_rtx_REG (SImode
,
31351 GP_ARG_RETURN
+ 1),
31353 gen_rtx_EXPR_LIST (VOIDmode
,
31354 gen_rtx_REG (SImode
,
31355 GP_ARG_RETURN
+ 2),
31357 gen_rtx_EXPR_LIST (VOIDmode
,
31358 gen_rtx_REG (SImode
,
31359 GP_ARG_RETURN
+ 3),
31363 mode
= TYPE_MODE (valtype
);
31364 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
31365 || POINTER_TYPE_P (valtype
))
31366 mode
= TARGET_32BIT
? SImode
: DImode
;
31368 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31369 /* _Decimal128 must use an even/odd register pair. */
31370 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31371 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
31372 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
31373 regno
= FP_ARG_RETURN
;
31374 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
31375 && targetm
.calls
.split_complex_arg
)
31376 return rs6000_complex_function_value (mode
);
31377 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31378 return register is used in both cases, and we won't see V2DImode/V2DFmode
31379 for pure altivec, combine the two cases. */
31380 else if (TREE_CODE (valtype
) == VECTOR_TYPE
31381 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
31382 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
31383 regno
= ALTIVEC_ARG_RETURN
;
31384 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31385 && (mode
== DFmode
|| mode
== DCmode
31386 || mode
== TFmode
|| mode
== TCmode
))
31387 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31389 regno
= GP_ARG_RETURN
;
31391 return gen_rtx_REG (mode
, regno
);
31394 /* Define how to find the value returned by a library function
31395 assuming the value has mode MODE. */
31397 rs6000_libcall_value (enum machine_mode mode
)
31399 unsigned int regno
;
31401 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
31403 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31404 return gen_rtx_PARALLEL (DImode
,
31406 gen_rtx_EXPR_LIST (VOIDmode
,
31407 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31409 gen_rtx_EXPR_LIST (VOIDmode
,
31410 gen_rtx_REG (SImode
,
31411 GP_ARG_RETURN
+ 1),
31415 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31416 /* _Decimal128 must use an even/odd register pair. */
31417 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31418 else if (SCALAR_FLOAT_MODE_P (mode
)
31419 && TARGET_HARD_FLOAT
&& TARGET_FPRS
31420 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
31421 regno
= FP_ARG_RETURN
;
31422 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31423 return register is used in both cases, and we won't see V2DImode/V2DFmode
31424 for pure altivec, combine the two cases. */
31425 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
31426 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
31427 regno
= ALTIVEC_ARG_RETURN
;
31428 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
31429 return rs6000_complex_function_value (mode
);
31430 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31431 && (mode
== DFmode
|| mode
== DCmode
31432 || mode
== TFmode
|| mode
== TCmode
))
31433 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31435 regno
= GP_ARG_RETURN
;
31437 return gen_rtx_REG (mode
, regno
);
31441 /* Return true if we use LRA instead of reload pass. */
31443 rs6000_lra_p (void)
31445 return rs6000_lra_flag
;
31448 /* Given FROM and TO register numbers, say whether this elimination is allowed.
31449 Frame pointer elimination is automatically handled.
31451 For the RS/6000, if frame pointer elimination is being done, we would like
31452 to convert ap into fp, not sp.
31454 We need r30 if -mminimal-toc was specified, and there are constant pool
31458 rs6000_can_eliminate (const int from
, const int to
)
31460 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
31461 ? ! frame_pointer_needed
31462 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
31463 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
31467 /* Define the offset between two registers, FROM to be eliminated and its
31468 replacement TO, at the start of a routine. */
31470 rs6000_initial_elimination_offset (int from
, int to
)
31472 rs6000_stack_t
*info
= rs6000_stack_info ();
31473 HOST_WIDE_INT offset
;
31475 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31476 offset
= info
->push_p
? 0 : -info
->total_size
;
31477 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31479 offset
= info
->push_p
? 0 : -info
->total_size
;
31480 if (FRAME_GROWS_DOWNWARD
)
31481 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
31483 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31484 offset
= FRAME_GROWS_DOWNWARD
31485 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
31487 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31488 offset
= info
->total_size
;
31489 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31490 offset
= info
->push_p
? info
->total_size
: 0;
31491 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
31494 gcc_unreachable ();
31500 rs6000_dwarf_register_span (rtx reg
)
31504 unsigned regno
= REGNO (reg
);
31505 enum machine_mode mode
= GET_MODE (reg
);
31509 && (SPE_VECTOR_MODE (GET_MODE (reg
))
31510 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
31511 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
31516 regno
= REGNO (reg
);
31518 /* The duality of the SPE register size wreaks all kinds of havoc.
31519 This is a way of distinguishing r0 in 32-bits from r0 in
31521 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
31522 gcc_assert (words
<= 4);
31523 for (i
= 0; i
< words
; i
++, regno
++)
31525 if (BYTES_BIG_ENDIAN
)
31527 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
31528 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
31532 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
31533 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
31537 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
31540 /* Fill in sizes for SPE register high parts in table used by unwinder. */
31543 rs6000_init_dwarf_reg_sizes_extra (tree address
)
31548 enum machine_mode mode
= TYPE_MODE (char_type_node
);
31549 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
31550 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
31551 rtx value
= gen_int_mode (4, mode
);
31553 for (i
= FIRST_SPE_HIGH_REGNO
; i
< LAST_SPE_HIGH_REGNO
+1; i
++)
31555 int column
= DWARF_REG_TO_UNWIND_COLUMN
31556 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
31557 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
31559 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31563 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
31566 enum machine_mode mode
= TYPE_MODE (char_type_node
);
31567 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
31568 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
31569 rtx value
= gen_int_mode (16, mode
);
31571 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
31572 The unwinder still needs to know the size of Altivec registers. */
31574 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
31576 int column
= DWARF_REG_TO_UNWIND_COLUMN
31577 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
31578 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
31580 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31585 /* Map internal gcc register numbers to DWARF2 register numbers. */
31588 rs6000_dbx_register_number (unsigned int regno
)
31590 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
31592 if (regno
== LR_REGNO
)
31594 if (regno
== CTR_REGNO
)
31596 if (CR_REGNO_P (regno
))
31597 return regno
- CR0_REGNO
+ 86;
31598 if (regno
== CA_REGNO
)
31599 return 101; /* XER */
31600 if (ALTIVEC_REGNO_P (regno
))
31601 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
31602 if (regno
== VRSAVE_REGNO
)
31604 if (regno
== VSCR_REGNO
)
31606 if (regno
== SPE_ACC_REGNO
)
31608 if (regno
== SPEFSCR_REGNO
)
31610 if (SPE_HIGH_REGNO_P (regno
))
31611 return regno
- FIRST_SPE_HIGH_REGNO
+ 1200;
31615 /* target hook eh_return_filter_mode */
31616 static enum machine_mode
31617 rs6000_eh_return_filter_mode (void)
31619 return TARGET_32BIT
? SImode
: word_mode
;
31622 /* Target hook for scalar_mode_supported_p. */
31624 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
31626 if (DECIMAL_FLOAT_MODE_P (mode
))
31627 return default_decimal_float_supported_p ();
31629 return default_scalar_mode_supported_p (mode
);
31632 /* Target hook for vector_mode_supported_p. */
31634 rs6000_vector_mode_supported_p (enum machine_mode mode
)
31637 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
31640 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
31643 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
31650 /* Target hook for invalid_arg_for_unprototyped_fn. */
31651 static const char *
31652 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
31654 return (!rs6000_darwin64_abi
31656 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
31657 && (funcdecl
== NULL_TREE
31658 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
31659 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
31660 ? N_("AltiVec argument passed to unprototyped function")
31664 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
31665 setup by using __stack_chk_fail_local hidden function instead of
31666 calling __stack_chk_fail directly. Otherwise it is better to call
31667 __stack_chk_fail directly. */
31669 static tree ATTRIBUTE_UNUSED
31670 rs6000_stack_protect_fail (void)
31672 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
31673 ? default_hidden_stack_protect_fail ()
31674 : default_external_stack_protect_fail ();
31678 rs6000_final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
31679 int num_operands ATTRIBUTE_UNUSED
)
31681 if (rs6000_warn_cell_microcode
)
31684 int insn_code_number
= recog_memoized (insn
);
31685 location_t location
= INSN_LOCATION (insn
);
31687 /* Punt on insns we cannot recognize. */
31688 if (insn_code_number
< 0)
31691 temp
= get_insn_template (insn_code_number
, insn
);
31693 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
31694 warning_at (location
, OPT_mwarn_cell_microcode
,
31695 "emitting microcode insn %s\t[%s] #%d",
31696 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31697 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
31698 warning_at (location
, OPT_mwarn_cell_microcode
,
31699 "emitting conditional microcode insn %s\t[%s] #%d",
31700 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31704 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
31707 static unsigned HOST_WIDE_INT
31708 rs6000_asan_shadow_offset (void)
31710 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
31714 /* Mask options that we want to support inside of attribute((target)) and
31715 #pragma GCC target operations. Note, we do not include things like
31716 64/32-bit, endianess, hard/soft floating point, etc. that would have
31717 different calling sequences. */
31719 struct rs6000_opt_mask
{
31720 const char *name
; /* option name */
31721 HOST_WIDE_INT mask
; /* mask to set */
31722 bool invert
; /* invert sense of mask */
31723 bool valid_target
; /* option is a target option */
31726 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
31728 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
31729 { "cmpb", OPTION_MASK_CMPB
, false, true },
31730 { "crypto", OPTION_MASK_CRYPTO
, false, true },
31731 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
31732 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
31733 { "fprnd", OPTION_MASK_FPRND
, false, true },
31734 { "hard-dfp", OPTION_MASK_DFP
, false, true },
31735 { "htm", OPTION_MASK_HTM
, false, true },
31736 { "isel", OPTION_MASK_ISEL
, false, true },
31737 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
31738 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
31739 { "mulhw", OPTION_MASK_MULHW
, false, true },
31740 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
31741 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
31742 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
31743 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
31744 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
31745 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
31746 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
31747 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
31748 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
31749 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
31750 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
31751 { "string", OPTION_MASK_STRING
, false, true },
31752 { "update", OPTION_MASK_NO_UPDATE
, true , true },
31753 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
31754 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
31755 { "vsx", OPTION_MASK_VSX
, false, true },
31756 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
31757 #ifdef OPTION_MASK_64BIT
31759 { "aix64", OPTION_MASK_64BIT
, false, false },
31760 { "aix32", OPTION_MASK_64BIT
, true, false },
31762 { "64", OPTION_MASK_64BIT
, false, false },
31763 { "32", OPTION_MASK_64BIT
, true, false },
31766 #ifdef OPTION_MASK_EABI
31767 { "eabi", OPTION_MASK_EABI
, false, false },
31769 #ifdef OPTION_MASK_LITTLE_ENDIAN
31770 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
31771 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
31773 #ifdef OPTION_MASK_RELOCATABLE
31774 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
31776 #ifdef OPTION_MASK_STRICT_ALIGN
31777 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
31779 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
31780 { "string", OPTION_MASK_STRING
, false, false },
31783 /* Builtin mask mapping for printing the flags. */
31784 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
31786 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
31787 { "vsx", RS6000_BTM_VSX
, false, false },
31788 { "spe", RS6000_BTM_SPE
, false, false },
31789 { "paired", RS6000_BTM_PAIRED
, false, false },
31790 { "fre", RS6000_BTM_FRE
, false, false },
31791 { "fres", RS6000_BTM_FRES
, false, false },
31792 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
31793 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
31794 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
31795 { "cell", RS6000_BTM_CELL
, false, false },
31796 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
31797 { "crypto", RS6000_BTM_CRYPTO
, false, false },
31798 { "htm", RS6000_BTM_HTM
, false, false },
31799 { "hard-dfp", RS6000_BTM_DFP
, false, false },
31800 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
31801 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
31804 /* Option variables that we want to support inside attribute((target)) and
31805 #pragma GCC target operations. */
31807 struct rs6000_opt_var
{
31808 const char *name
; /* option name */
31809 size_t global_offset
; /* offset of the option in global_options. */
31810 size_t target_offset
; /* offset of the option in target optiosn. */
31813 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
31816 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
31817 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
31818 { "avoid-indexed-addresses",
31819 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
31820 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
31822 offsetof (struct gcc_options
, x_rs6000_paired_float
),
31823 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
31825 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
31826 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
31829 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
31830 parsing. Return true if there were no errors. */
31833 rs6000_inner_target_options (tree args
, bool attr_p
)
31837 if (args
== NULL_TREE
)
31840 else if (TREE_CODE (args
) == STRING_CST
)
31842 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31845 while ((q
= strtok (p
, ",")) != NULL
)
31847 bool error_p
= false;
31848 bool not_valid_p
= false;
31849 const char *cpu_opt
= NULL
;
31852 if (strncmp (q
, "cpu=", 4) == 0)
31854 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
31855 if (cpu_index
>= 0)
31856 rs6000_cpu_index
= cpu_index
;
31863 else if (strncmp (q
, "tune=", 5) == 0)
31865 int tune_index
= rs6000_cpu_name_lookup (q
+5);
31866 if (tune_index
>= 0)
31867 rs6000_tune_index
= tune_index
;
31877 bool invert
= false;
31881 if (strncmp (r
, "no-", 3) == 0)
31887 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
31888 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
31890 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
31892 if (!rs6000_opt_masks
[i
].valid_target
)
31893 not_valid_p
= true;
31897 rs6000_isa_flags_explicit
|= mask
;
31899 /* VSX needs altivec, so -mvsx automagically sets
31901 if (mask
== OPTION_MASK_VSX
&& !invert
)
31902 mask
|= OPTION_MASK_ALTIVEC
;
31904 if (rs6000_opt_masks
[i
].invert
)
31908 rs6000_isa_flags
&= ~mask
;
31910 rs6000_isa_flags
|= mask
;
31915 if (error_p
&& !not_valid_p
)
31917 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
31918 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
31920 size_t j
= rs6000_opt_vars
[i
].global_offset
;
31921 *((int *) ((char *)&global_options
+ j
)) = !invert
;
31930 const char *eprefix
, *esuffix
;
31935 eprefix
= "__attribute__((__target__(";
31940 eprefix
= "#pragma GCC target ";
31945 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
31947 else if (not_valid_p
)
31948 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
31950 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
31955 else if (TREE_CODE (args
) == TREE_LIST
)
31959 tree value
= TREE_VALUE (args
);
31962 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
31966 args
= TREE_CHAIN (args
);
31968 while (args
!= NULL_TREE
);
31972 gcc_unreachable ();
31977 /* Print out the target options as a list for -mdebug=target. */
31980 rs6000_debug_target_options (tree args
, const char *prefix
)
31982 if (args
== NULL_TREE
)
31983 fprintf (stderr
, "%s<NULL>", prefix
);
31985 else if (TREE_CODE (args
) == STRING_CST
)
31987 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31990 while ((q
= strtok (p
, ",")) != NULL
)
31993 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
31998 else if (TREE_CODE (args
) == TREE_LIST
)
32002 tree value
= TREE_VALUE (args
);
32005 rs6000_debug_target_options (value
, prefix
);
32008 args
= TREE_CHAIN (args
);
32010 while (args
!= NULL_TREE
);
32014 gcc_unreachable ();
32020 /* Hook to validate attribute((target("..."))). */
32023 rs6000_valid_attribute_p (tree fndecl
,
32024 tree
ARG_UNUSED (name
),
32028 struct cl_target_option cur_target
;
32030 tree old_optimize
= build_optimization_node (&global_options
);
32031 tree new_target
, new_optimize
;
32032 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
32034 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
32036 if (TARGET_DEBUG_TARGET
)
32038 tree tname
= DECL_NAME (fndecl
);
32039 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
32041 fprintf (stderr
, "function: %.*s\n",
32042 (int) IDENTIFIER_LENGTH (tname
),
32043 IDENTIFIER_POINTER (tname
));
32045 fprintf (stderr
, "function: unknown\n");
32047 fprintf (stderr
, "args:");
32048 rs6000_debug_target_options (args
, " ");
32049 fprintf (stderr
, "\n");
32052 fprintf (stderr
, "flags: 0x%x\n", flags
);
32054 fprintf (stderr
, "--------------------\n");
32057 old_optimize
= build_optimization_node (&global_options
);
32058 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
32060 /* If the function changed the optimization levels as well as setting target
32061 options, start with the optimizations specified. */
32062 if (func_optimize
&& func_optimize
!= old_optimize
)
32063 cl_optimization_restore (&global_options
,
32064 TREE_OPTIMIZATION (func_optimize
));
32066 /* The target attributes may also change some optimization flags, so update
32067 the optimization options if necessary. */
32068 cl_target_option_save (&cur_target
, &global_options
);
32069 rs6000_cpu_index
= rs6000_tune_index
= -1;
32070 ret
= rs6000_inner_target_options (args
, true);
32072 /* Set up any additional state. */
32075 ret
= rs6000_option_override_internal (false);
32076 new_target
= build_target_option_node (&global_options
);
32081 new_optimize
= build_optimization_node (&global_options
);
32088 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
32090 if (old_optimize
!= new_optimize
)
32091 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
32094 cl_target_option_restore (&global_options
, &cur_target
);
32096 if (old_optimize
!= new_optimize
)
32097 cl_optimization_restore (&global_options
,
32098 TREE_OPTIMIZATION (old_optimize
));
32104 /* Hook to validate the current #pragma GCC target and set the state, and
32105 update the macros based on what was changed. If ARGS is NULL, then
32106 POP_TARGET is used to reset the options. */
32109 rs6000_pragma_target_parse (tree args
, tree pop_target
)
32111 tree prev_tree
= build_target_option_node (&global_options
);
32113 struct cl_target_option
*prev_opt
, *cur_opt
;
32114 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
32115 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
32117 if (TARGET_DEBUG_TARGET
)
32119 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
32120 fprintf (stderr
, "args:");
32121 rs6000_debug_target_options (args
, " ");
32122 fprintf (stderr
, "\n");
32126 fprintf (stderr
, "pop_target:\n");
32127 debug_tree (pop_target
);
32130 fprintf (stderr
, "pop_target: <NULL>\n");
32132 fprintf (stderr
, "--------------------\n");
32137 cur_tree
= ((pop_target
)
32139 : target_option_default_node
);
32140 cl_target_option_restore (&global_options
,
32141 TREE_TARGET_OPTION (cur_tree
));
32145 rs6000_cpu_index
= rs6000_tune_index
= -1;
32146 if (!rs6000_inner_target_options (args
, false)
32147 || !rs6000_option_override_internal (false)
32148 || (cur_tree
= build_target_option_node (&global_options
))
32151 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
32152 fprintf (stderr
, "invalid pragma\n");
32158 target_option_current_node
= cur_tree
;
32160 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
32161 change the macros that are defined. */
32162 if (rs6000_target_modify_macros_ptr
)
32164 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
32165 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
32166 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
32168 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
32169 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
32170 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
32172 diff_bumask
= (prev_bumask
^ cur_bumask
);
32173 diff_flags
= (prev_flags
^ cur_flags
);
32175 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
32177 /* Delete old macros. */
32178 rs6000_target_modify_macros_ptr (false,
32179 prev_flags
& diff_flags
,
32180 prev_bumask
& diff_bumask
);
32182 /* Define new macros. */
32183 rs6000_target_modify_macros_ptr (true,
32184 cur_flags
& diff_flags
,
32185 cur_bumask
& diff_bumask
);
32193 /* Remember the last target of rs6000_set_current_function. */
32194 static GTY(()) tree rs6000_previous_fndecl
;
32196 /* Establish appropriate back-end context for processing the function
32197 FNDECL. The argument might be NULL to indicate processing at top
32198 level, outside of any function scope. */
32200 rs6000_set_current_function (tree fndecl
)
32202 tree old_tree
= (rs6000_previous_fndecl
32203 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
32206 tree new_tree
= (fndecl
32207 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
32210 if (TARGET_DEBUG_TARGET
)
32212 bool print_final
= false;
32213 fprintf (stderr
, "\n==================== rs6000_set_current_function");
32216 fprintf (stderr
, ", fndecl %s (%p)",
32217 (DECL_NAME (fndecl
)
32218 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
32219 : "<unknown>"), (void *)fndecl
);
32221 if (rs6000_previous_fndecl
)
32222 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
32224 fprintf (stderr
, "\n");
32227 fprintf (stderr
, "\nnew fndecl target specific options:\n");
32228 debug_tree (new_tree
);
32229 print_final
= true;
32234 fprintf (stderr
, "\nold fndecl target specific options:\n");
32235 debug_tree (old_tree
);
32236 print_final
= true;
32240 fprintf (stderr
, "--------------------\n");
32243 /* Only change the context if the function changes. This hook is called
32244 several times in the course of compiling a function, and we don't want to
32245 slow things down too much or call target_reinit when it isn't safe. */
32246 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
32248 rs6000_previous_fndecl
= fndecl
;
32249 if (old_tree
== new_tree
)
32254 cl_target_option_restore (&global_options
,
32255 TREE_TARGET_OPTION (new_tree
));
32256 if (TREE_TARGET_GLOBALS (new_tree
))
32257 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
32259 TREE_TARGET_GLOBALS (new_tree
)
32260 = save_target_globals_default_opts ();
32265 new_tree
= target_option_current_node
;
32266 cl_target_option_restore (&global_options
,
32267 TREE_TARGET_OPTION (new_tree
));
32268 if (TREE_TARGET_GLOBALS (new_tree
))
32269 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
32270 else if (new_tree
== target_option_default_node
)
32271 restore_target_globals (&default_target_globals
);
32273 TREE_TARGET_GLOBALS (new_tree
)
32274 = save_target_globals_default_opts ();
32280 /* Save the current options */
32283 rs6000_function_specific_save (struct cl_target_option
*ptr
,
32284 struct gcc_options
*opts
)
32286 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
32287 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
32290 /* Restore the current options */
32293 rs6000_function_specific_restore (struct gcc_options
*opts
,
32294 struct cl_target_option
*ptr
)
32297 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
32298 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
32299 (void) rs6000_option_override_internal (false);
32302 /* Print the current options */
32305 rs6000_function_specific_print (FILE *file
, int indent
,
32306 struct cl_target_option
*ptr
)
32308 rs6000_print_isa_options (file
, indent
, "Isa options set",
32309 ptr
->x_rs6000_isa_flags
);
32311 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
32312 ptr
->x_rs6000_isa_flags_explicit
);
32315 /* Helper function to print the current isa or misc options on a line. */
32318 rs6000_print_options_internal (FILE *file
,
32320 const char *string
,
32321 HOST_WIDE_INT flags
,
32322 const char *prefix
,
32323 const struct rs6000_opt_mask
*opts
,
32324 size_t num_elements
)
32327 size_t start_column
= 0;
32329 size_t max_column
= 76;
32330 const char *comma
= "";
32333 start_column
+= fprintf (file
, "%*s", indent
, "");
32337 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
32341 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
32343 /* Print the various mask options. */
32344 cur_column
= start_column
;
32345 for (i
= 0; i
< num_elements
; i
++)
32347 if ((flags
& opts
[i
].mask
) != 0)
32349 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
32350 size_t len
= (strlen (comma
)
32353 + strlen (rs6000_opt_masks
[i
].name
));
32356 if (cur_column
> max_column
)
32358 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
32359 cur_column
= start_column
+ len
;
32363 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
32364 rs6000_opt_masks
[i
].name
);
32365 flags
&= ~ opts
[i
].mask
;
32370 fputs ("\n", file
);
32373 /* Helper function to print the current isa options on a line. */
32376 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
32377 HOST_WIDE_INT flags
)
32379 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
32380 &rs6000_opt_masks
[0],
32381 ARRAY_SIZE (rs6000_opt_masks
));
32385 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
32386 HOST_WIDE_INT flags
)
32388 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
32389 &rs6000_builtin_mask_names
[0],
32390 ARRAY_SIZE (rs6000_builtin_mask_names
));
32394 /* Hook to determine if one function can safely inline another. */
32397 rs6000_can_inline_p (tree caller
, tree callee
)
32400 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
32401 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
32403 /* If callee has no option attributes, then it is ok to inline. */
32407 /* If caller has no option attributes, but callee does then it is not ok to
32409 else if (!caller_tree
)
32414 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
32415 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
32417 /* Callee's options should a subset of the caller's, i.e. a vsx function
32418 can inline an altivec function but a non-vsx function can't inline a
32420 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
32421 == callee_opts
->x_rs6000_isa_flags
)
32425 if (TARGET_DEBUG_TARGET
)
32426 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
32427 (DECL_NAME (caller
)
32428 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
32430 (DECL_NAME (callee
)
32431 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
32433 (ret
? "can" : "cannot"));
32438 /* Allocate a stack temp and fixup the address so it meets the particular
32439 memory requirements (either offetable or REG+REG addressing). */
32442 rs6000_allocate_stack_temp (enum machine_mode mode
,
32443 bool offsettable_p
,
32446 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
32447 rtx addr
= XEXP (stack
, 0);
32448 int strict_p
= (reload_in_progress
|| reload_completed
);
32450 if (!legitimate_indirect_address_p (addr
, strict_p
))
32453 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
32454 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
32456 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
32457 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
32463 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
32464 to such a form to deal with memory reference instructions like STFIWX that
32465 only take reg+reg addressing. */
32468 rs6000_address_for_fpconvert (rtx x
)
32470 int strict_p
= (reload_in_progress
|| reload_completed
);
32473 gcc_assert (MEM_P (x
));
32474 addr
= XEXP (x
, 0);
32475 if (! legitimate_indirect_address_p (addr
, strict_p
)
32476 && ! legitimate_indexed_address_p (addr
, strict_p
))
32478 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
32480 rtx reg
= XEXP (addr
, 0);
32481 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
32482 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
32483 gcc_assert (REG_P (reg
));
32484 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
32487 else if (GET_CODE (addr
) == PRE_MODIFY
)
32489 rtx reg
= XEXP (addr
, 0);
32490 rtx expr
= XEXP (addr
, 1);
32491 gcc_assert (REG_P (reg
));
32492 gcc_assert (GET_CODE (expr
) == PLUS
);
32493 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
32497 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
32503 /* Given a memory reference, if it is not in the form for altivec memory
32504 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
32505 convert to the altivec format. */
32508 rs6000_address_for_altivec (rtx x
)
32510 gcc_assert (MEM_P (x
));
32511 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
32513 rtx addr
= XEXP (x
, 0);
32514 int strict_p
= (reload_in_progress
|| reload_completed
);
32516 if (!legitimate_indexed_address_p (addr
, strict_p
)
32517 && !legitimate_indirect_address_p (addr
, strict_p
))
32518 addr
= copy_to_mode_reg (Pmode
, addr
);
32520 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
32521 x
= change_address (x
, GET_MODE (x
), addr
);
32527 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
32529 On the RS/6000, all integer constants are acceptable, most won't be valid
32530 for particular insns, though. Only easy FP constants are acceptable. */
32533 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
32535 if (TARGET_ELF
&& tls_referenced_p (x
))
32538 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
32539 || GET_MODE (x
) == VOIDmode
32540 || (TARGET_POWERPC64
&& mode
== DImode
)
32541 || easy_fp_constant (x
, mode
)
32542 || easy_vector_constant (x
, mode
));
32547 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
32550 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32552 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
32553 rtx toc_load
= NULL_RTX
;
32554 rtx toc_restore
= NULL_RTX
;
32556 rtx abi_reg
= NULL_RTX
;
32561 /* Handle longcall attributes. */
32562 if (INTVAL (cookie
) & CALL_LONG
)
32563 func_desc
= rs6000_longcall_ref (func_desc
);
32565 /* Handle indirect calls. */
32566 if (GET_CODE (func_desc
) != SYMBOL_REF
32567 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
32569 /* Save the TOC into its reserved slot before the call,
32570 and prepare to restore it after the call. */
32571 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
32572 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
32573 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
32574 gen_rtx_PLUS (Pmode
, stack_ptr
,
32575 stack_toc_offset
));
32576 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
32578 /* Can we optimize saving the TOC in the prologue or
32579 do we need to do it at every call? */
32580 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
32581 cfun
->machine
->save_toc_in_prologue
= true;
32584 MEM_VOLATILE_P (stack_toc_mem
) = 1;
32585 emit_move_insn (stack_toc_mem
, toc_reg
);
32588 if (DEFAULT_ABI
== ABI_ELFv2
)
32590 /* A function pointer in the ELFv2 ABI is just a plain address, but
32591 the ABI requires it to be loaded into r12 before the call. */
32592 func_addr
= gen_rtx_REG (Pmode
, 12);
32593 emit_move_insn (func_addr
, func_desc
);
32594 abi_reg
= func_addr
;
32598 /* A function pointer under AIX is a pointer to a data area whose
32599 first word contains the actual address of the function, whose
32600 second word contains a pointer to its TOC, and whose third word
32601 contains a value to place in the static chain register (r11).
32602 Note that if we load the static chain, our "trampoline" need
32603 not have any executable code. */
32605 /* Load up address of the actual function. */
32606 func_desc
= force_reg (Pmode
, func_desc
);
32607 func_addr
= gen_reg_rtx (Pmode
);
32608 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
32610 /* Prepare to load the TOC of the called function. Note that the
32611 TOC load must happen immediately before the actual call so
32612 that unwinding the TOC registers works correctly. See the
32613 comment in frob_update_context. */
32614 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
32615 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
32616 gen_rtx_PLUS (Pmode
, func_desc
,
32618 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
32620 /* If we have a static chain, load it up. */
32621 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32623 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
32624 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
32625 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
32626 gen_rtx_PLUS (Pmode
, func_desc
,
32628 emit_move_insn (sc_reg
, func_sc_mem
);
32635 /* Direct calls use the TOC: for local calls, the callee will
32636 assume the TOC register is set; for non-local calls, the
32637 PLT stub needs the TOC register. */
32639 func_addr
= func_desc
;
32642 /* Create the call. */
32643 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
32644 if (value
!= NULL_RTX
)
32645 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32649 call
[n_call
++] = toc_load
;
32651 call
[n_call
++] = toc_restore
;
32653 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
32655 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
32656 insn
= emit_call_insn (insn
);
32658 /* Mention all registers defined by the ABI to hold information
32659 as uses in CALL_INSN_FUNCTION_USAGE. */
32661 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
32664 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
32667 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32672 gcc_assert (INTVAL (cookie
) == 0);
32674 /* Create the call. */
32675 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
32676 if (value
!= NULL_RTX
)
32677 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32679 call
[1] = simple_return_rtx
;
32681 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
32682 insn
= emit_call_insn (insn
);
32684 /* Note use of the TOC register. */
32685 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
32686 /* We need to also mark a use of the link register since the function we
32687 sibling-call to will use it to return to our caller. */
32688 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
32691 /* Return whether we need to always update the saved TOC pointer when we update
32692 the stack pointer. */
32695 rs6000_save_toc_in_prologue_p (void)
32697 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
32700 #ifdef HAVE_GAS_HIDDEN
32701 # define USE_HIDDEN_LINKONCE 1
32703 # define USE_HIDDEN_LINKONCE 0
32706 /* Fills in the label name that should be used for a 476 link stack thunk. */
32709 get_ppc476_thunk_name (char name
[32])
32711 gcc_assert (TARGET_LINK_STACK
);
32713 if (USE_HIDDEN_LINKONCE
)
32714 sprintf (name
, "__ppc476.get_thunk");
32716 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
32719 /* This function emits the simple thunk routine that is used to preserve
32720 the link stack on the 476 cpu. */
32722 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
32724 rs6000_code_end (void)
32729 if (!TARGET_LINK_STACK
)
32732 get_ppc476_thunk_name (name
);
32734 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
32735 build_function_type_list (void_type_node
, NULL_TREE
));
32736 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
32737 NULL_TREE
, void_type_node
);
32738 TREE_PUBLIC (decl
) = 1;
32739 TREE_STATIC (decl
) = 1;
32742 if (USE_HIDDEN_LINKONCE
)
32744 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
32745 targetm
.asm_out
.unique_section (decl
, 0);
32746 switch_to_section (get_named_section (decl
, NULL
, 0));
32747 DECL_WEAK (decl
) = 1;
32748 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
32749 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
32750 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
32751 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
32756 switch_to_section (text_section
);
32757 ASM_OUTPUT_LABEL (asm_out_file
, name
);
32760 DECL_INITIAL (decl
) = make_node (BLOCK
);
32761 current_function_decl
= decl
;
32762 init_function_start (decl
);
32763 first_function_block_is_cold
= false;
32764 /* Make sure unwind info is emitted for the thunk if needed. */
32765 final_start_function (emit_barrier (), asm_out_file
, 1);
32767 fputs ("\tblr\n", asm_out_file
);
32769 final_end_function ();
32770 init_insn_lengths ();
32771 free_after_compilation (cfun
);
32773 current_function_decl
= NULL
;
32776 /* Add r30 to hard reg set if the prologue sets it up and it is not
32777 pic_offset_table_rtx. */
32780 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
32782 if (!TARGET_SINGLE_PIC_BASE
32784 && TARGET_MINIMAL_TOC
32785 && get_pool_size () != 0)
32786 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
32790 /* Helper function for rs6000_split_logical to emit a logical instruction after
32791 spliting the operation to single GPR registers.
32793 DEST is the destination register.
32794 OP1 and OP2 are the input source registers.
32795 CODE is the base operation (AND, IOR, XOR, NOT).
32796 MODE is the machine mode.
32797 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32798 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32799 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
32802 rs6000_split_logical_inner (rtx dest
,
32805 enum rtx_code code
,
32806 enum machine_mode mode
,
32807 bool complement_final_p
,
32808 bool complement_op1_p
,
32809 bool complement_op2_p
)
32813 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
32814 if (op2
&& GET_CODE (op2
) == CONST_INT
32815 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
32816 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
32818 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
32819 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
32821 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
32826 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
32830 else if (value
== mask
)
32832 if (!rtx_equal_p (dest
, op1
))
32833 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32838 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
32839 into separate ORI/ORIS or XORI/XORIS instrucitons. */
32840 else if (code
== IOR
|| code
== XOR
)
32844 if (!rtx_equal_p (dest
, op1
))
32845 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32851 if (code
== AND
&& mode
== SImode
32852 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
32854 emit_insn (gen_andsi3 (dest
, op1
, op2
));
32858 if (complement_op1_p
)
32859 op1
= gen_rtx_NOT (mode
, op1
);
32861 if (complement_op2_p
)
32862 op2
= gen_rtx_NOT (mode
, op2
);
32864 bool_rtx
= ((code
== NOT
)
32865 ? gen_rtx_NOT (mode
, op1
)
32866 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
32868 if (complement_final_p
)
32869 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
32871 emit_insn (gen_rtx_SET (VOIDmode
, dest
, bool_rtx
));
32874 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
32875 operations are split immediately during RTL generation to allow for more
32876 optimizations of the AND/IOR/XOR.
32878 OPERANDS is an array containing the destination and two input operands.
32879 CODE is the base operation (AND, IOR, XOR, NOT).
32880 MODE is the machine mode.
32881 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32882 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32883 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32884 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32885 formation of the AND instructions. */
32888 rs6000_split_logical_di (rtx operands
[3],
32889 enum rtx_code code
,
32890 bool complement_final_p
,
32891 bool complement_op1_p
,
32892 bool complement_op2_p
)
32894 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
32895 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
32896 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
32897 enum hi_lo
{ hi
= 0, lo
= 1 };
32898 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
32901 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
32902 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
32903 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
32904 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
32907 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
32910 if (GET_CODE (operands
[2]) != CONST_INT
)
32912 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
32913 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
32917 HOST_WIDE_INT value
= INTVAL (operands
[2]);
32918 HOST_WIDE_INT value_hi_lo
[2];
32920 gcc_assert (!complement_final_p
);
32921 gcc_assert (!complement_op1_p
);
32922 gcc_assert (!complement_op2_p
);
32924 value_hi_lo
[hi
] = value
>> 32;
32925 value_hi_lo
[lo
] = value
& lower_32bits
;
32927 for (i
= 0; i
< 2; i
++)
32929 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
32931 if (sub_value
& sign_bit
)
32932 sub_value
|= upper_32bits
;
32934 op2_hi_lo
[i
] = GEN_INT (sub_value
);
32936 /* If this is an AND instruction, check to see if we need to load
32937 the value in a register. */
32938 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
32939 && !and_operand (op2_hi_lo
[i
], SImode
))
32940 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
32945 for (i
= 0; i
< 2; i
++)
32947 /* Split large IOR/XOR operations. */
32948 if ((code
== IOR
|| code
== XOR
)
32949 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
32950 && !complement_final_p
32951 && !complement_op1_p
32952 && !complement_op2_p
32953 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
32955 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
32956 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
32957 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
32958 rtx tmp
= gen_reg_rtx (SImode
);
32960 /* Make sure the constant is sign extended. */
32961 if ((hi_16bits
& sign_bit
) != 0)
32962 hi_16bits
|= upper_32bits
;
32964 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
32965 code
, SImode
, false, false, false);
32967 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
32968 code
, SImode
, false, false, false);
32971 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
32972 code
, SImode
, complement_final_p
,
32973 complement_op1_p
, complement_op2_p
);
32979 /* Split the insns that make up boolean operations operating on multiple GPR
32980 registers. The boolean MD patterns ensure that the inputs either are
32981 exactly the same as the output registers, or there is no overlap.
32983 OPERANDS is an array containing the destination and two input operands.
32984 CODE is the base operation (AND, IOR, XOR, NOT).
32985 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32986 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32987 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
32990 rs6000_split_logical (rtx operands
[3],
32991 enum rtx_code code
,
32992 bool complement_final_p
,
32993 bool complement_op1_p
,
32994 bool complement_op2_p
)
32996 enum machine_mode mode
= GET_MODE (operands
[0]);
32997 enum machine_mode sub_mode
;
32999 int sub_size
, regno0
, regno1
, nregs
, i
;
33001 /* If this is DImode, use the specialized version that can run before
33002 register allocation. */
33003 if (mode
== DImode
&& !TARGET_POWERPC64
)
33005 rs6000_split_logical_di (operands
, code
, complement_final_p
,
33006 complement_op1_p
, complement_op2_p
);
33012 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
33013 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
33014 sub_size
= GET_MODE_SIZE (sub_mode
);
33015 regno0
= REGNO (op0
);
33016 regno1
= REGNO (op1
);
33018 gcc_assert (reload_completed
);
33019 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
33020 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
33022 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
33023 gcc_assert (nregs
> 1);
33025 if (op2
&& REG_P (op2
))
33026 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
33028 for (i
= 0; i
< nregs
; i
++)
33030 int offset
= i
* sub_size
;
33031 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
33032 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
33033 rtx sub_op2
= ((code
== NOT
)
33035 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
33037 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
33038 complement_final_p
, complement_op1_p
,
33046 /* Return true if the peephole2 can combine a load involving a combination of
33047 an addis instruction and a load with an offset that can be fused together on
33051 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
33052 rtx addis_value
, /* addis value. */
33053 rtx target
, /* target register that is loaded. */
33054 rtx mem
) /* bottom part of the memory addr. */
33059 /* Validate arguments. */
33060 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
33063 if (!base_reg_operand (target
, GET_MODE (target
)))
33066 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
33069 /* Allow sign/zero extension. */
33070 if (GET_CODE (mem
) == ZERO_EXTEND
33071 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
33072 mem
= XEXP (mem
, 0);
33077 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
33080 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
33081 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
33084 /* Validate that the register used to load the high value is either the
33085 register being loaded, or we can safely replace its use.
33087 This function is only called from the peephole2 pass and we assume that
33088 there are 2 instructions in the peephole (addis and load), so we want to
33089 check if the target register was not used in the memory address and the
33090 register to hold the addis result is dead after the peephole. */
33091 if (REGNO (addis_reg
) != REGNO (target
))
33093 if (reg_mentioned_p (target
, mem
))
33096 if (!peep2_reg_dead_p (2, addis_reg
))
33099 /* If the target register being loaded is the stack pointer, we must
33100 avoid loading any other value into it, even temporarily. */
33101 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
33105 base_reg
= XEXP (addr
, 0);
33106 return REGNO (addis_reg
) == REGNO (base_reg
);
33109 /* During the peephole2 pass, adjust and expand the insns for a load fusion
33110 sequence. We adjust the addis register to use the target register. If the
33111 load sign extends, we adjust the code to do the zero extending load, and an
33112 explicit sign extension later since the fusion only covers zero extending
33116 operands[0] register set with addis (to be replaced with target)
33117 operands[1] value set via addis
33118 operands[2] target register being loaded
33119 operands[3] D-form memory reference using operands[0]. */
33122 expand_fusion_gpr_load (rtx
*operands
)
33124 rtx addis_value
= operands
[1];
33125 rtx target
= operands
[2];
33126 rtx orig_mem
= operands
[3];
33127 rtx new_addr
, new_mem
, orig_addr
, offset
;
33128 enum rtx_code plus_or_lo_sum
;
33129 enum machine_mode target_mode
= GET_MODE (target
);
33130 enum machine_mode extend_mode
= target_mode
;
33131 enum machine_mode ptr_mode
= Pmode
;
33132 enum rtx_code extend
= UNKNOWN
;
33134 if (GET_CODE (orig_mem
) == ZERO_EXTEND
33135 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
33137 extend
= GET_CODE (orig_mem
);
33138 orig_mem
= XEXP (orig_mem
, 0);
33139 target_mode
= GET_MODE (orig_mem
);
33142 gcc_assert (MEM_P (orig_mem
));
33144 orig_addr
= XEXP (orig_mem
, 0);
33145 plus_or_lo_sum
= GET_CODE (orig_addr
);
33146 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
33148 offset
= XEXP (orig_addr
, 1);
33149 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
33150 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
33152 if (extend
!= UNKNOWN
)
33153 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
33155 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
33156 UNSPEC_FUSION_GPR
);
33157 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
33159 if (extend
== SIGN_EXTEND
)
33161 int sub_off
= ((BYTES_BIG_ENDIAN
)
33162 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
33165 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
33167 emit_insn (gen_rtx_SET (VOIDmode
, target
,
33168 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
33174 /* Return a string to fuse an addis instruction with a gpr load to the same
33175 register that we loaded up the addis instruction. The address that is used
33176 is the logical address that was formed during peephole2:
33177 (lo_sum (high) (low-part))
33179 The code is complicated, so we call output_asm_insn directly, and just
33183 emit_fusion_gpr_load (rtx target
, rtx mem
)
33189 const char *addis_str
= NULL
;
33190 const char *load_str
= NULL
;
33191 const char *mode_name
= NULL
;
33192 char insn_template
[80];
33193 enum machine_mode mode
;
33194 const char *comment_str
= ASM_COMMENT_START
;
33196 if (GET_CODE (mem
) == ZERO_EXTEND
)
33197 mem
= XEXP (mem
, 0);
33199 gcc_assert (REG_P (target
) && MEM_P (mem
));
33201 if (*comment_str
== ' ')
33204 addr
= XEXP (mem
, 0);
33205 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
33206 gcc_unreachable ();
33208 addis_value
= XEXP (addr
, 0);
33209 load_offset
= XEXP (addr
, 1);
33211 /* Now emit the load instruction to the same register. */
33212 mode
= GET_MODE (mem
);
33216 mode_name
= "char";
33221 mode_name
= "short";
33231 gcc_assert (TARGET_POWERPC64
);
33232 mode_name
= "long";
33237 gcc_unreachable ();
33240 /* Emit the addis instruction. */
33241 fuse_ops
[0] = target
;
33242 if (satisfies_constraint_L (addis_value
))
33244 fuse_ops
[1] = addis_value
;
33245 addis_str
= "lis %0,%v1";
33248 else if (GET_CODE (addis_value
) == PLUS
)
33250 rtx op0
= XEXP (addis_value
, 0);
33251 rtx op1
= XEXP (addis_value
, 1);
33253 if (REG_P (op0
) && CONST_INT_P (op1
)
33254 && satisfies_constraint_L (op1
))
33258 addis_str
= "addis %0,%1,%v2";
33262 else if (GET_CODE (addis_value
) == HIGH
)
33264 rtx value
= XEXP (addis_value
, 0);
33265 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
33267 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
33268 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
33270 addis_str
= "addis %0,%2,%1@toc@ha";
33272 else if (TARGET_XCOFF
)
33273 addis_str
= "addis %0,%1@u(%2)";
33276 gcc_unreachable ();
33279 else if (GET_CODE (value
) == PLUS
)
33281 rtx op0
= XEXP (value
, 0);
33282 rtx op1
= XEXP (value
, 1);
33284 if (GET_CODE (op0
) == UNSPEC
33285 && XINT (op0
, 1) == UNSPEC_TOCREL
33286 && CONST_INT_P (op1
))
33288 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
33289 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
33292 addis_str
= "addis %0,%2,%1+%3@toc@ha";
33294 else if (TARGET_XCOFF
)
33295 addis_str
= "addis %0,%1+%3@u(%2)";
33298 gcc_unreachable ();
33302 else if (satisfies_constraint_L (value
))
33304 fuse_ops
[1] = value
;
33305 addis_str
= "lis %0,%v1";
33308 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
33310 fuse_ops
[1] = value
;
33311 addis_str
= "lis %0,%1@ha";
33316 fatal_insn ("Could not generate addis value for fusion", addis_value
);
33318 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
33319 comment_str
, mode_name
);
33320 output_asm_insn (insn_template
, fuse_ops
);
33322 /* Emit the D-form load instruction. */
33323 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
33325 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
33326 fuse_ops
[1] = load_offset
;
33327 output_asm_insn (insn_template
, fuse_ops
);
33330 else if (GET_CODE (load_offset
) == UNSPEC
33331 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
33334 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
33336 else if (TARGET_XCOFF
)
33337 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33340 gcc_unreachable ();
33342 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
33343 output_asm_insn (insn_template
, fuse_ops
);
33346 else if (GET_CODE (load_offset
) == PLUS
33347 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
33348 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
33349 && CONST_INT_P (XEXP (load_offset
, 1)))
33351 rtx tocrel_unspec
= XEXP (load_offset
, 0);
33353 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
33355 else if (TARGET_XCOFF
)
33356 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
33359 gcc_unreachable ();
33361 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
33362 fuse_ops
[2] = XEXP (load_offset
, 1);
33363 output_asm_insn (insn_template
, fuse_ops
);
33366 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
33368 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33370 fuse_ops
[1] = load_offset
;
33371 output_asm_insn (insn_template
, fuse_ops
);
33375 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
33380 /* Analyze vector computations and remove unnecessary doubleword
33381 swaps (xxswapdi instructions). This pass is performed only
33382 for little-endian VSX code generation.
33384 For this specific case, loads and stores of 4x32 and 2x64 vectors
33385 are inefficient. These are implemented using the lvx2dx and
33386 stvx2dx instructions, which invert the order of doublewords in
33387 a vector register. Thus the code generation inserts an xxswapdi
33388 after each such load, and prior to each such store. (For spill
33389 code after register assignment, an additional xxswapdi is inserted
33390 following each store in order to return a hard register to its
33393 The extra xxswapdi instructions reduce performance. This can be
33394 particularly bad for vectorized code. The purpose of this pass
33395 is to reduce the number of xxswapdi instructions required for
33398 The primary insight is that much code that operates on vectors
33399 does not care about the relative order of elements in a register,
33400 so long as the correct memory order is preserved. If we have
33401 a computation where all input values are provided by lvxd2x/xxswapdi
33402 sequences, all outputs are stored using xxswapdi/stvxd2x sequences,
33403 and all intermediate computations are pure SIMD (independent of
33404 element order), then all the xxswapdi's associated with the loads
33405 and stores may be removed.
33407 This pass uses some of the infrastructure and logical ideas from
33408 the "web" pass in web.c. We create maximal webs of computations
33409 fitting the description above using union-find. Each such web is
33410 then optimized by removing its unnecessary xxswapdi instructions.
33412 The pass is placed prior to global optimization so that we can
33413 perform the optimization in the safest and simplest way possible;
33414 that is, by replacing each xxswapdi insn with a register copy insn.
33415 Subsequent forward propagation will remove copies where possible.
33417 There are some operations sensitive to element order for which we
33418 can still allow the operation, provided we modify those operations.
33419 These include CONST_VECTORs, for which we must swap the first and
33420 second halves of the constant vector; and SUBREGs, for which we
33421 must adjust the byte offset to account for the swapped doublewords.
33422 A remaining opportunity would be non-immediate-form splats, for
33423 which we should adjust the selected lane of the input. We should
33424 also make code generation adjustments for sum-across operations,
33425 since this is a common vectorizer reduction.
33427 Because we run prior to the first split, we can see loads and stores
33428 here that match *vsx_le_perm_{load,store}_<mode>. These are vanilla
33429 vector loads and stores that have not yet been split into a permuting
33430 load/store and a swap. (One way this can happen is with a builtin
33431 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
33432 than deleting a swap, we convert the load/store into a permuting
33433 load/store (which effectively removes the swap). */
33435 /* This is based on the union-find logic in web.c. web_entry_base is
33436 defined in df.h. */
33437 class swap_web_entry
: public web_entry_base
33440 /* Pointer to the insn. */
33442 /* Set if insn contains a mention of a vector register. All other
33443 fields are undefined if this field is unset. */
33444 unsigned int is_relevant
: 1;
33445 /* Set if insn is a load. */
33446 unsigned int is_load
: 1;
33447 /* Set if insn is a store. */
33448 unsigned int is_store
: 1;
33449 /* Set if insn is a doubleword swap. This can either be a register swap
33450 or a permuting load or store (test is_load and is_store for this). */
33451 unsigned int is_swap
: 1;
33452 /* Set if the insn has a live-in use of a parameter register. */
33453 unsigned int is_live_in
: 1;
33454 /* Set if the insn has a live-out def of a return register. */
33455 unsigned int is_live_out
: 1;
33456 /* Set if the insn contains a subreg reference of a vector register. */
33457 unsigned int contains_subreg
: 1;
33458 /* Set if the insn contains a 128-bit integer operand. */
33459 unsigned int is_128_int
: 1;
33460 /* Set if this is a call-insn. */
33461 unsigned int is_call
: 1;
33462 /* Set if this insn does not perform a vector operation for which
33463 element order matters, or if we know how to fix it up if it does.
33464 Undefined if is_swap is set. */
33465 unsigned int is_swappable
: 1;
33466 /* A nonzero value indicates what kind of special handling for this
33467 insn is required if doublewords are swapped. Undefined if
33468 is_swappable is not set. */
33469 unsigned int special_handling
: 3;
33470 /* Set if the web represented by this entry cannot be optimized. */
33471 unsigned int web_not_optimizable
: 1;
33472 /* Set if this insn should be deleted. */
33473 unsigned int will_delete
: 1;
33476 enum special_handling_values
{
33486 /* Union INSN with all insns containing definitions that reach USE.
33487 Detect whether USE is live-in to the current function. */
33489 union_defs (swap_web_entry
*insn_entry
, rtx insn
, df_ref use
)
33491 struct df_link
*link
= DF_REF_CHAIN (use
);
33494 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
33498 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
33499 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
33501 if (DF_REF_INSN_INFO (link
->ref
))
33503 rtx def_insn
= DF_REF_INSN (link
->ref
);
33504 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
33505 insn_entry
+ INSN_UID (def_insn
));
33512 /* Union INSN with all insns containing uses reached from DEF.
33513 Detect whether DEF is live-out from the current function. */
33515 union_uses (swap_web_entry
*insn_entry
, rtx insn
, df_ref def
)
33517 struct df_link
*link
= DF_REF_CHAIN (def
);
33520 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
33524 /* This could be an eh use or some other artificial use;
33525 we treat these all the same (killing the optimization). */
33526 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
33527 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
33529 if (DF_REF_INSN_INFO (link
->ref
))
33531 rtx use_insn
= DF_REF_INSN (link
->ref
);
33532 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
33533 insn_entry
+ INSN_UID (use_insn
));
33540 /* Return 1 iff INSN is a load insn, including permuting loads that
33541 represent an lvxd2x instruction; else return 0. */
33542 static unsigned int
33543 insn_is_load_p (rtx insn
)
33545 rtx body
= PATTERN (insn
);
33547 if (GET_CODE (body
) == SET
)
33549 if (GET_CODE (SET_SRC (body
)) == MEM
)
33552 if (GET_CODE (SET_SRC (body
)) == VEC_SELECT
33553 && GET_CODE (XEXP (SET_SRC (body
), 0)) == MEM
)
33559 if (GET_CODE (body
) != PARALLEL
)
33562 rtx set
= XVECEXP (body
, 0, 0);
33564 if (GET_CODE (set
) == SET
&& GET_CODE (SET_SRC (set
)) == MEM
)
33570 /* Return 1 iff INSN is a store insn, including permuting stores that
33571 represent an stvxd2x instruction; else return 0. */
33572 static unsigned int
33573 insn_is_store_p (rtx insn
)
33575 rtx body
= PATTERN (insn
);
33576 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == MEM
)
33578 if (GET_CODE (body
) != PARALLEL
)
33580 rtx set
= XVECEXP (body
, 0, 0);
33581 if (GET_CODE (set
) == SET
&& GET_CODE (SET_DEST (set
)) == MEM
)
33586 /* Return 1 iff INSN swaps doublewords. This may be a reg-reg swap,
33587 a permuting load, or a permuting store. */
33588 static unsigned int
33589 insn_is_swap_p (rtx insn
)
33591 rtx body
= PATTERN (insn
);
33592 if (GET_CODE (body
) != SET
)
33594 rtx rhs
= SET_SRC (body
);
33595 if (GET_CODE (rhs
) != VEC_SELECT
)
33597 rtx parallel
= XEXP (rhs
, 1);
33598 if (GET_CODE (parallel
) != PARALLEL
)
33600 unsigned int len
= XVECLEN (parallel
, 0);
33601 if (len
!= 2 && len
!= 4 && len
!= 8 && len
!= 16)
33603 for (unsigned int i
= 0; i
< len
/ 2; ++i
)
33605 rtx op
= XVECEXP (parallel
, 0, i
);
33606 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != len
/ 2 + i
)
33609 for (unsigned int i
= len
/ 2; i
< len
; ++i
)
33611 rtx op
= XVECEXP (parallel
, 0, i
);
33612 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != i
- len
/ 2)
33618 /* Return 1 iff OP is an operand that will not be affected by having
33619 vector doublewords swapped in memory. */
33620 static unsigned int
33621 rtx_is_swappable_p (rtx op
, unsigned int *special
)
33623 enum rtx_code code
= GET_CODE (op
);
33642 *special
= SH_CONST_VECTOR
;
33646 case VEC_DUPLICATE
:
33647 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
33648 and XEXP (op, 1) is a PARALLEL with a single QImode const int,
33649 it represents a vector splat for which we can do special
33651 if (GET_CODE (XEXP (op
, 0)) == CONST_INT
)
33653 else if (GET_CODE (XEXP (op
, 0)) == REG
33654 && GET_MODE_INNER (GET_MODE (op
)) == GET_MODE (XEXP (op
, 0)))
33655 /* This catches V2DF and V2DI splat, at a minimum. */
33657 else if (GET_CODE (XEXP (op
, 0)) == VEC_SELECT
)
33658 /* If the duplicated item is from a select, defer to the select
33659 processing to see if we can change the lane for the splat. */
33660 return rtx_is_swappable_p (XEXP (op
, 0), special
);
33665 /* A vec_extract operation is ok if we change the lane. */
33666 if (GET_CODE (XEXP (op
, 0)) == REG
33667 && GET_MODE_INNER (GET_MODE (XEXP (op
, 0))) == GET_MODE (op
)
33668 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
33669 && XVECLEN (parallel
, 0) == 1
33670 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
)
33672 *special
= SH_EXTRACT
;
33680 /* Various operations are unsafe for this optimization, at least
33681 without significant additional work. Permutes are obviously
33682 problematic, as both the permute control vector and the ordering
33683 of the target values are invalidated by doubleword swapping.
33684 Vector pack and unpack modify the number of vector lanes.
33685 Merge-high/low will not operate correctly on swapped operands.
33686 Vector shifts across element boundaries are clearly uncool,
33687 as are vector select and concatenate operations. Vector
33688 sum-across instructions define one operand with a specific
33689 order-dependent element, so additional fixup code would be
33690 needed to make those work. Vector set and non-immediate-form
33691 vector splat are element-order sensitive. A few of these
33692 cases might be workable with special handling if required. */
33693 int val
= XINT (op
, 1);
33698 case UNSPEC_VMRGH_DIRECT
:
33699 case UNSPEC_VMRGL_DIRECT
:
33700 case UNSPEC_VPACK_SIGN_SIGN_SAT
:
33701 case UNSPEC_VPACK_SIGN_UNS_SAT
:
33702 case UNSPEC_VPACK_UNS_UNS_MOD
:
33703 case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
:
33704 case UNSPEC_VPACK_UNS_UNS_SAT
:
33706 case UNSPEC_VPERM_UNS
:
33707 case UNSPEC_VPERMHI
:
33708 case UNSPEC_VPERMSI
:
33710 case UNSPEC_VSLDOI
:
33713 case UNSPEC_VSUM2SWS
:
33714 case UNSPEC_VSUM4S
:
33715 case UNSPEC_VSUM4UBS
:
33716 case UNSPEC_VSUMSWS
:
33717 case UNSPEC_VSUMSWS_DIRECT
:
33718 case UNSPEC_VSX_CONCAT
:
33719 case UNSPEC_VSX_SET
:
33720 case UNSPEC_VSX_SLDWI
:
33721 case UNSPEC_VUNPACK_HI_SIGN
:
33722 case UNSPEC_VUNPACK_HI_SIGN_DIRECT
:
33723 case UNSPEC_VUNPACK_LO_SIGN
:
33724 case UNSPEC_VUNPACK_LO_SIGN_DIRECT
:
33725 case UNSPEC_VUPKHPX
:
33726 case UNSPEC_VUPKHS_V4SF
:
33727 case UNSPEC_VUPKHU_V4SF
:
33728 case UNSPEC_VUPKLPX
:
33729 case UNSPEC_VUPKLS_V4SF
:
33730 case UNSPEC_VUPKLU_V4SF
:
33731 /* The following could be handled as an idiom with XXSPLTW.
33732 These place a scalar in BE element zero, but the XXSPLTW
33733 will currently expect it in BE element 2 in a swapped
33734 region. When one of these feeds an XXSPLTW with no other
33735 defs/uses either way, we can avoid the lane change for
33736 XXSPLTW and things will be correct. TBD. */
33737 case UNSPEC_VSX_CVDPSPN
:
33738 case UNSPEC_VSX_CVSPDP
:
33739 case UNSPEC_VSX_CVSPDPN
:
33741 case UNSPEC_VSPLT_DIRECT
:
33742 *special
= SH_SPLAT
;
33751 const char *fmt
= GET_RTX_FORMAT (code
);
33754 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
33755 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
33757 unsigned int special_op
= SH_NONE
;
33758 ok
&= rtx_is_swappable_p (XEXP (op
, i
), &special_op
);
33759 /* Ensure we never have two kinds of special handling
33760 for the same insn. */
33761 if (*special
!= SH_NONE
&& special_op
!= SH_NONE
33762 && *special
!= special_op
)
33764 *special
= special_op
;
33766 else if (fmt
[i
] == 'E')
33767 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
33769 unsigned int special_op
= SH_NONE
;
33770 ok
&= rtx_is_swappable_p (XVECEXP (op
, i
, j
), &special_op
);
33771 /* Ensure we never have two kinds of special handling
33772 for the same insn. */
33773 if (*special
!= SH_NONE
&& special_op
!= SH_NONE
33774 && *special
!= special_op
)
33776 *special
= special_op
;
33782 /* Return 1 iff INSN is an operand that will not be affected by
33783 having vector doublewords swapped in memory (in which case
33784 *SPECIAL is unchanged), or that can be modified to be correct
33785 if vector doublewords are swapped in memory (in which case
33786 *SPECIAL is changed to a value indicating how). */
33787 static unsigned int
33788 insn_is_swappable_p (swap_web_entry
*insn_entry
, rtx insn
,
33789 unsigned int *special
)
33791 /* Calls are always bad. */
33792 if (GET_CODE (insn
) == CALL_INSN
)
33795 /* Loads and stores seen here are not permuting, but we can still
33796 fix them up by converting them to permuting ones. Exception:
33797 UNSPEC_LVX and UNSPEC_STVX, which have a PARALLEL body instead
33799 rtx body
= PATTERN (insn
);
33800 int i
= INSN_UID (insn
);
33802 if (insn_entry
[i
].is_load
)
33804 if (GET_CODE (body
) == SET
)
33806 *special
= SH_NOSWAP_LD
;
33813 if (insn_entry
[i
].is_store
)
33815 if (GET_CODE (body
) == SET
)
33817 *special
= SH_NOSWAP_ST
;
33824 /* Otherwise check the operands for vector lane violations. */
33825 return rtx_is_swappable_p (body
, special
);
33828 enum chain_purpose
{ FOR_LOADS
, FOR_STORES
};
33830 /* Return true if the UD or DU chain headed by LINK is non-empty,
33831 and every entry on the chain references an insn that is a
33832 register swap. Furthermore, if PURPOSE is FOR_LOADS, each such
33833 register swap must have only permuting loads as reaching defs.
33834 If PURPOSE is FOR_STORES, each such register swap must have only
33835 register swaps or permuting stores as reached uses. */
33837 chain_contains_only_swaps (swap_web_entry
*insn_entry
, struct df_link
*link
,
33838 enum chain_purpose purpose
)
33843 for (; link
; link
= link
->next
)
33845 if (!VECTOR_MODE_P (GET_MODE (DF_REF_REG (link
->ref
))))
33848 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
33851 rtx reached_insn
= DF_REF_INSN (link
->ref
);
33852 unsigned uid
= INSN_UID (reached_insn
);
33853 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (reached_insn
);
33855 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
33856 || insn_entry
[uid
].is_store
)
33859 if (purpose
== FOR_LOADS
)
33862 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
33864 struct df_link
*swap_link
= DF_REF_CHAIN (use
);
33868 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
33871 rtx swap_def_insn
= DF_REF_INSN (swap_link
->ref
);
33872 unsigned uid2
= INSN_UID (swap_def_insn
);
33874 /* Only permuting loads are allowed. */
33875 if (!insn_entry
[uid2
].is_swap
|| !insn_entry
[uid2
].is_load
)
33878 swap_link
= swap_link
->next
;
33882 else if (purpose
== FOR_STORES
)
33885 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
33887 struct df_link
*swap_link
= DF_REF_CHAIN (def
);
33891 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
33894 rtx swap_use_insn
= DF_REF_INSN (swap_link
->ref
);
33895 unsigned uid2
= INSN_UID (swap_use_insn
);
33897 /* Permuting stores or register swaps are allowed. */
33898 if (!insn_entry
[uid2
].is_swap
|| insn_entry
[uid2
].is_load
)
33901 swap_link
= swap_link
->next
;
33910 /* Mark the xxswapdi instructions associated with permuting loads and
33911 stores for removal. Note that we only flag them for deletion here,
33912 as there is a possibility of a swap being reached from multiple
33915 mark_swaps_for_removal (swap_web_entry
*insn_entry
, unsigned int i
)
33917 rtx insn
= insn_entry
[i
].insn
;
33918 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
33920 if (insn_entry
[i
].is_load
)
33923 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
33925 struct df_link
*link
= DF_REF_CHAIN (def
);
33927 /* We know by now that these are swaps, so we can delete
33928 them confidently. */
33931 rtx use_insn
= DF_REF_INSN (link
->ref
);
33932 insn_entry
[INSN_UID (use_insn
)].will_delete
= 1;
33937 else if (insn_entry
[i
].is_store
)
33940 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
33942 /* Ignore uses for addressability. */
33943 enum machine_mode mode
= GET_MODE (DF_REF_REG (use
));
33944 if (!VECTOR_MODE_P (mode
))
33947 struct df_link
*link
= DF_REF_CHAIN (use
);
33949 /* We know by now that these are swaps, so we can delete
33950 them confidently. */
33953 rtx def_insn
= DF_REF_INSN (link
->ref
);
33954 insn_entry
[INSN_UID (def_insn
)].will_delete
= 1;
33961 /* OP is either a CONST_VECTOR or an expression containing one.
33962 Swap the first half of the vector with the second in the first
33963 case. Recurse to find it in the second. */
33965 swap_const_vector_halves (rtx op
)
33968 enum rtx_code code
= GET_CODE (op
);
33969 if (GET_CODE (op
) == CONST_VECTOR
)
33971 int half_units
= GET_MODE_NUNITS (GET_MODE (op
)) / 2;
33972 for (i
= 0; i
< half_units
; ++i
)
33974 rtx temp
= CONST_VECTOR_ELT (op
, i
);
33975 CONST_VECTOR_ELT (op
, i
) = CONST_VECTOR_ELT (op
, i
+ half_units
);
33976 CONST_VECTOR_ELT (op
, i
+ half_units
) = temp
;
33982 const char *fmt
= GET_RTX_FORMAT (code
);
33983 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
33984 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
33985 swap_const_vector_halves (XEXP (op
, i
));
33986 else if (fmt
[i
] == 'E')
33987 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
33988 swap_const_vector_halves (XVECEXP (op
, i
, j
));
33992 /* Find all subregs of a vector expression that perform a narrowing,
33993 and adjust the subreg index to account for doubleword swapping. */
33995 adjust_subreg_index (rtx op
)
33997 enum rtx_code code
= GET_CODE (op
);
33999 && (GET_MODE_SIZE (GET_MODE (op
))
34000 < GET_MODE_SIZE (GET_MODE (XEXP (op
, 0)))))
34002 unsigned int index
= SUBREG_BYTE (op
);
34007 SUBREG_BYTE (op
) = index
;
34010 const char *fmt
= GET_RTX_FORMAT (code
);
34012 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
34013 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
34014 adjust_subreg_index (XEXP (op
, i
));
34015 else if (fmt
[i
] == 'E')
34016 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
34017 adjust_subreg_index (XVECEXP (op
, i
, j
));
34020 /* Convert the non-permuting load INSN to a permuting one. */
34022 permute_load (rtx_insn
*insn
)
34024 rtx body
= PATTERN (insn
);
34025 rtx mem_op
= SET_SRC (body
);
34026 rtx tgt_reg
= SET_DEST (body
);
34027 enum machine_mode mode
= GET_MODE (tgt_reg
);
34028 int n_elts
= GET_MODE_NUNITS (mode
);
34029 int half_elts
= n_elts
/ 2;
34030 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
34032 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
34033 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34034 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
34035 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34036 rtx sel
= gen_rtx_VEC_SELECT (mode
, mem_op
, par
);
34037 SET_SRC (body
) = sel
;
34038 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34039 df_insn_rescan (insn
);
34042 fprintf (dump_file
, "Replacing load %d with permuted load\n",
34046 /* Convert the non-permuting store INSN to a permuting one. */
34048 permute_store (rtx_insn
*insn
)
34050 rtx body
= PATTERN (insn
);
34051 rtx src_reg
= SET_SRC (body
);
34052 enum machine_mode mode
= GET_MODE (src_reg
);
34053 int n_elts
= GET_MODE_NUNITS (mode
);
34054 int half_elts
= n_elts
/ 2;
34055 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
34057 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
34058 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34059 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
34060 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34061 rtx sel
= gen_rtx_VEC_SELECT (mode
, src_reg
, par
);
34062 SET_SRC (body
) = sel
;
34063 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34064 df_insn_rescan (insn
);
34067 fprintf (dump_file
, "Replacing store %d with permuted store\n",
34071 /* Given OP that contains a vector extract operation, adjust the index
34072 of the extracted lane to account for the doubleword swap. */
34074 adjust_extract (rtx_insn
*insn
)
34076 rtx src
= SET_SRC (PATTERN (insn
));
34077 /* The vec_select may be wrapped in a vec_duplicate for a splat, so
34078 account for that. */
34079 rtx sel
= GET_CODE (src
) == VEC_DUPLICATE
? XEXP (src
, 0) : src
;
34080 rtx par
= XEXP (sel
, 1);
34081 int half_elts
= GET_MODE_NUNITS (GET_MODE (XEXP (sel
, 0))) >> 1;
34082 int lane
= INTVAL (XVECEXP (par
, 0, 0));
34083 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
34084 XVECEXP (par
, 0, 0) = GEN_INT (lane
);
34085 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34086 df_insn_rescan (insn
);
34089 fprintf (dump_file
, "Changing lane for extract %d\n", INSN_UID (insn
));
34092 /* Given OP that contains a vector direct-splat operation, adjust the index
34093 of the source lane to account for the doubleword swap. */
34095 adjust_splat (rtx_insn
*insn
)
34097 rtx body
= PATTERN (insn
);
34098 rtx unspec
= XEXP (body
, 1);
34099 int half_elts
= GET_MODE_NUNITS (GET_MODE (unspec
)) >> 1;
34100 int lane
= INTVAL (XVECEXP (unspec
, 0, 1));
34101 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
34102 XVECEXP (unspec
, 0, 1) = GEN_INT (lane
);
34103 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34104 df_insn_rescan (insn
);
34107 fprintf (dump_file
, "Changing lane for splat %d\n", INSN_UID (insn
));
34110 /* The insn described by INSN_ENTRY[I] can be swapped, but only
34111 with special handling. Take care of that here. */
34113 handle_special_swappables (swap_web_entry
*insn_entry
, unsigned i
)
34115 rtx_insn
*insn
= insn_entry
[i
].insn
;
34116 rtx body
= PATTERN (insn
);
34118 switch (insn_entry
[i
].special_handling
)
34121 gcc_unreachable ();
34122 case SH_CONST_VECTOR
:
34124 /* A CONST_VECTOR will only show up somewhere in the RHS of a SET. */
34125 gcc_assert (GET_CODE (body
) == SET
);
34126 rtx rhs
= SET_SRC (body
);
34127 swap_const_vector_halves (rhs
);
34129 fprintf (dump_file
, "Swapping constant halves in insn %d\n", i
);
34133 /* A subreg of the same size is already safe. For subregs that
34134 select a smaller portion of a reg, adjust the index for
34135 swapped doublewords. */
34136 adjust_subreg_index (body
);
34138 fprintf (dump_file
, "Adjusting subreg in insn %d\n", i
);
34141 /* Convert a non-permuting load to a permuting one. */
34142 permute_load (insn
);
34145 /* Convert a non-permuting store to a permuting one. */
34146 permute_store (insn
);
34149 /* Change the lane on an extract operation. */
34150 adjust_extract (insn
);
34153 /* Change the lane on a direct-splat operation. */
34154 adjust_splat (insn
);
34159 /* Find the insn from the Ith table entry, which is known to be a
34160 register swap Y = SWAP(X). Replace it with a copy Y = X. */
34162 replace_swap_with_copy (swap_web_entry
*insn_entry
, unsigned i
)
34164 rtx_insn
*insn
= insn_entry
[i
].insn
;
34165 rtx body
= PATTERN (insn
);
34166 rtx src_reg
= XEXP (SET_SRC (body
), 0);
34167 rtx copy
= gen_rtx_SET (VOIDmode
, SET_DEST (body
), src_reg
);
34168 rtx_insn
*new_insn
= emit_insn_before (copy
, insn
);
34169 set_block_for_insn (new_insn
, BLOCK_FOR_INSN (insn
));
34170 df_insn_rescan (new_insn
);
34174 unsigned int new_uid
= INSN_UID (new_insn
);
34175 fprintf (dump_file
, "Replacing swap %d with copy %d\n", i
, new_uid
);
34178 df_insn_delete (insn
);
34179 remove_insn (insn
);
34180 insn
->set_deleted ();
34183 /* Dump the swap table to DUMP_FILE. */
34185 dump_swap_insn_table (swap_web_entry
*insn_entry
)
34187 int e
= get_max_uid ();
34188 fprintf (dump_file
, "\nRelevant insns with their flag settings\n\n");
34190 for (int i
= 0; i
< e
; ++i
)
34191 if (insn_entry
[i
].is_relevant
)
34193 swap_web_entry
*pred_entry
= (swap_web_entry
*)insn_entry
[i
].pred ();
34194 fprintf (dump_file
, "%6d %6d ", i
,
34195 pred_entry
&& pred_entry
->insn
34196 ? INSN_UID (pred_entry
->insn
) : 0);
34197 if (insn_entry
[i
].is_load
)
34198 fputs ("load ", dump_file
);
34199 if (insn_entry
[i
].is_store
)
34200 fputs ("store ", dump_file
);
34201 if (insn_entry
[i
].is_swap
)
34202 fputs ("swap ", dump_file
);
34203 if (insn_entry
[i
].is_live_in
)
34204 fputs ("live-in ", dump_file
);
34205 if (insn_entry
[i
].is_live_out
)
34206 fputs ("live-out ", dump_file
);
34207 if (insn_entry
[i
].contains_subreg
)
34208 fputs ("subreg ", dump_file
);
34209 if (insn_entry
[i
].is_128_int
)
34210 fputs ("int128 ", dump_file
);
34211 if (insn_entry
[i
].is_call
)
34212 fputs ("call ", dump_file
);
34213 if (insn_entry
[i
].is_swappable
)
34215 fputs ("swappable ", dump_file
);
34216 if (insn_entry
[i
].special_handling
== SH_CONST_VECTOR
)
34217 fputs ("special:constvec ", dump_file
);
34218 else if (insn_entry
[i
].special_handling
== SH_SUBREG
)
34219 fputs ("special:subreg ", dump_file
);
34220 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_LD
)
34221 fputs ("special:load ", dump_file
);
34222 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_ST
)
34223 fputs ("special:store ", dump_file
);
34224 else if (insn_entry
[i
].special_handling
== SH_EXTRACT
)
34225 fputs ("special:extract ", dump_file
);
34226 else if (insn_entry
[i
].special_handling
== SH_SPLAT
)
34227 fputs ("special:splat ", dump_file
);
34229 if (insn_entry
[i
].web_not_optimizable
)
34230 fputs ("unoptimizable ", dump_file
);
34231 if (insn_entry
[i
].will_delete
)
34232 fputs ("delete ", dump_file
);
34233 fputs ("\n", dump_file
);
34235 fputs ("\n", dump_file
);
34238 /* Main entry point for this pass. */
34240 rs6000_analyze_swaps (function
*fun
)
34242 swap_web_entry
*insn_entry
;
34246 /* Dataflow analysis for use-def chains. */
34247 df_set_flags (DF_RD_PRUNE_DEAD_DEFS
);
34248 df_chain_add_problem (DF_DU_CHAIN
| DF_UD_CHAIN
);
34250 df_set_flags (DF_DEFER_INSN_RESCAN
);
34252 /* Allocate structure to represent webs of insns. */
34253 insn_entry
= XCNEWVEC (swap_web_entry
, get_max_uid ());
34255 /* Walk the insns to gather basic data. */
34256 FOR_ALL_BB_FN (bb
, fun
)
34257 FOR_BB_INSNS (bb
, insn
)
34259 unsigned int uid
= INSN_UID (insn
);
34260 if (NONDEBUG_INSN_P (insn
))
34262 insn_entry
[uid
].insn
= insn
;
34264 if (GET_CODE (insn
) == CALL_INSN
)
34265 insn_entry
[uid
].is_call
= 1;
34267 /* Walk the uses and defs to see if we mention vector regs.
34268 Record any constraints on optimization of such mentions. */
34269 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
34271 FOR_EACH_INSN_INFO_USE (mention
, insn_info
)
34273 /* We use DF_REF_REAL_REG here to get inside any subregs. */
34274 enum machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
34276 /* If a use gets its value from a call insn, it will be
34277 a hard register and will look like (reg:V4SI 3 3).
34278 The df analysis creates two mentions for GPR3 and GPR4,
34279 both DImode. We must recognize this and treat it as a
34280 vector mention to ensure the call is unioned with this
34282 if (mode
== DImode
&& DF_REF_INSN_INFO (mention
))
34284 rtx feeder
= DF_REF_INSN (mention
);
34285 /* FIXME: It is pretty hard to get from the df mention
34286 to the mode of the use in the insn. We arbitrarily
34287 pick a vector mode here, even though the use might
34288 be a real DImode. We can be too conservative
34289 (create a web larger than necessary) because of
34290 this, so consider eventually fixing this. */
34291 if (GET_CODE (feeder
) == CALL_INSN
)
34295 if (VECTOR_MODE_P (mode
))
34297 insn_entry
[uid
].is_relevant
= 1;
34298 if (mode
== TImode
|| mode
== V1TImode
)
34299 insn_entry
[uid
].is_128_int
= 1;
34300 if (DF_REF_INSN_INFO (mention
))
34301 insn_entry
[uid
].contains_subreg
34302 = !rtx_equal_p (DF_REF_REG (mention
),
34303 DF_REF_REAL_REG (mention
));
34304 union_defs (insn_entry
, insn
, mention
);
34307 FOR_EACH_INSN_INFO_DEF (mention
, insn_info
)
34309 /* We use DF_REF_REAL_REG here to get inside any subregs. */
34310 enum machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
34312 /* If we're loading up a hard vector register for a call,
34313 it looks like (set (reg:V4SI 9 9) (...)). The df
34314 analysis creates two mentions for GPR9 and GPR10, both
34315 DImode. So relying on the mode from the mentions
34316 isn't sufficient to ensure we union the call into the
34317 web with the parameter setup code. */
34318 if (mode
== DImode
&& GET_CODE (insn
) == SET
34319 && VECTOR_MODE_P (GET_MODE (SET_DEST (insn
))))
34320 mode
= GET_MODE (SET_DEST (insn
));
34322 if (VECTOR_MODE_P (mode
))
34324 insn_entry
[uid
].is_relevant
= 1;
34325 if (mode
== TImode
|| mode
== V1TImode
)
34326 insn_entry
[uid
].is_128_int
= 1;
34327 if (DF_REF_INSN_INFO (mention
))
34328 insn_entry
[uid
].contains_subreg
34329 = !rtx_equal_p (DF_REF_REG (mention
),
34330 DF_REF_REAL_REG (mention
));
34331 /* REG_FUNCTION_VALUE_P is not valid for subregs. */
34332 else if (REG_FUNCTION_VALUE_P (DF_REF_REG (mention
)))
34333 insn_entry
[uid
].is_live_out
= 1;
34334 union_uses (insn_entry
, insn
, mention
);
34338 if (insn_entry
[uid
].is_relevant
)
34340 /* Determine if this is a load or store. */
34341 insn_entry
[uid
].is_load
= insn_is_load_p (insn
);
34342 insn_entry
[uid
].is_store
= insn_is_store_p (insn
);
34344 /* Determine if this is a doubleword swap. If not,
34345 determine whether it can legally be swapped. */
34346 if (insn_is_swap_p (insn
))
34347 insn_entry
[uid
].is_swap
= 1;
34350 unsigned int special
= SH_NONE
;
34351 insn_entry
[uid
].is_swappable
34352 = insn_is_swappable_p (insn_entry
, insn
, &special
);
34353 if (special
!= SH_NONE
&& insn_entry
[uid
].contains_subreg
)
34354 insn_entry
[uid
].is_swappable
= 0;
34355 else if (special
!= SH_NONE
)
34356 insn_entry
[uid
].special_handling
= special
;
34357 else if (insn_entry
[uid
].contains_subreg
)
34358 insn_entry
[uid
].special_handling
= SH_SUBREG
;
34366 fprintf (dump_file
, "\nSwap insn entry table when first built\n");
34367 dump_swap_insn_table (insn_entry
);
34370 /* Record unoptimizable webs. */
34371 unsigned e
= get_max_uid (), i
;
34372 for (i
= 0; i
< e
; ++i
)
34374 if (!insn_entry
[i
].is_relevant
)
34377 swap_web_entry
*root
34378 = (swap_web_entry
*)(&insn_entry
[i
])->unionfind_root ();
34380 if (insn_entry
[i
].is_live_in
|| insn_entry
[i
].is_live_out
34381 || (insn_entry
[i
].contains_subreg
34382 && insn_entry
[i
].special_handling
!= SH_SUBREG
)
34383 || insn_entry
[i
].is_128_int
|| insn_entry
[i
].is_call
34384 || !(insn_entry
[i
].is_swappable
|| insn_entry
[i
].is_swap
))
34385 root
->web_not_optimizable
= 1;
34387 /* If we have loads or stores that aren't permuting then the
34388 optimization isn't appropriate. */
34389 else if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
34390 && !insn_entry
[i
].is_swap
&& !insn_entry
[i
].is_swappable
)
34391 root
->web_not_optimizable
= 1;
34393 /* If we have permuting loads or stores that are not accompanied
34394 by a register swap, the optimization isn't appropriate. */
34395 else if (insn_entry
[i
].is_load
&& insn_entry
[i
].is_swap
)
34397 rtx insn
= insn_entry
[i
].insn
;
34398 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
34401 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
34403 struct df_link
*link
= DF_REF_CHAIN (def
);
34405 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_LOADS
))
34407 root
->web_not_optimizable
= 1;
34412 else if (insn_entry
[i
].is_store
&& insn_entry
[i
].is_swap
)
34414 rtx insn
= insn_entry
[i
].insn
;
34415 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
34418 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
34420 struct df_link
*link
= DF_REF_CHAIN (use
);
34422 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_STORES
))
34424 root
->web_not_optimizable
= 1;
34433 fprintf (dump_file
, "\nSwap insn entry table after web analysis\n");
34434 dump_swap_insn_table (insn_entry
);
34437 /* For each load and store in an optimizable web (which implies
34438 the loads and stores are permuting), find the associated
34439 register swaps and mark them for removal. Due to various
34440 optimizations we may mark the same swap more than once. Also
34441 perform special handling for swappable insns that require it. */
34442 for (i
= 0; i
< e
; ++i
)
34443 if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
34444 && insn_entry
[i
].is_swap
)
34446 swap_web_entry
* root_entry
34447 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
34448 if (!root_entry
->web_not_optimizable
)
34449 mark_swaps_for_removal (insn_entry
, i
);
34451 else if (insn_entry
[i
].is_swappable
&& insn_entry
[i
].special_handling
)
34453 swap_web_entry
* root_entry
34454 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
34455 if (!root_entry
->web_not_optimizable
)
34456 handle_special_swappables (insn_entry
, i
);
34459 /* Now delete the swaps marked for removal. */
34460 for (i
= 0; i
< e
; ++i
)
34461 if (insn_entry
[i
].will_delete
)
34462 replace_swap_with_copy (insn_entry
, i
);
34469 const pass_data pass_data_analyze_swaps
=
34471 RTL_PASS
, /* type */
34472 "swaps", /* name */
34473 OPTGROUP_NONE
, /* optinfo_flags */
34474 TV_NONE
, /* tv_id */
34475 0, /* properties_required */
34476 0, /* properties_provided */
34477 0, /* properties_destroyed */
34478 0, /* todo_flags_start */
34479 TODO_df_finish
, /* todo_flags_finish */
34482 class pass_analyze_swaps
: public rtl_opt_pass
34485 pass_analyze_swaps(gcc::context
*ctxt
)
34486 : rtl_opt_pass(pass_data_analyze_swaps
, ctxt
)
34489 /* opt_pass methods: */
34490 virtual bool gate (function
*)
34492 return (optimize
> 0 && !BYTES_BIG_ENDIAN
&& TARGET_VSX
34493 && rs6000_optimize_swaps
);
34496 virtual unsigned int execute (function
*fun
)
34498 return rs6000_analyze_swaps (fun
);
34501 }; // class pass_analyze_swaps
34504 make_pass_analyze_swaps (gcc::context
*ctxt
)
34506 return new pass_analyze_swaps (ctxt
);
34509 struct gcc_target targetm
= TARGET_INITIALIZER
;
34511 #include "gt-rs6000.h"