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FSF GCC merge 02/23/03
[official-gcc.git] / gcc / config / s390 / s390.h
blobdc8775704459b87d4ca5b89354c15f1a99359ce1
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com).
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #ifndef _S390_H
23 #define _S390_H
24
25 /* Override the __fixdfdi etc. routines when building libgcc2.
26 ??? This should be done in a cleaner way ... */
27 #ifdef IN_LIBGCC2
28 #include <s390/fixdfdi.h>
29 #endif
30
31 /* Which processor to generate code or schedule for. The cpu attribute
32 defines a list that mirrors this list, so changes to s390.md must be
33 made at the same time. */
34
35 enum processor_type
36 {
37 PROCESSOR_9672_G5,
38 PROCESSOR_9672_G6,
39 PROCESSOR_2064_Z900,
40 PROCESSOR_max
41 };
42
43 extern enum processor_type s390_cpu;
44 extern const char *s390_tune_string;
45
46 extern enum processor_type s390_arch;
47 extern const char *s390_arch_string;
48
49 #define TARGET_CPU_DEFAULT_9672 0
50 #define TARGET_CPU_DEFAULT_2064 2
51
52 #define TARGET_CPU_DEFAULT_NAMES {"g5", "g6", "z900"}
53
54 /* Run-time target specification. */
55
56 /* Target CPU builtins. */
57 #define TARGET_CPU_CPP_BUILTINS() \
58 do \
59 { \
60 builtin_assert ("cpu=s390"); \
61 builtin_assert ("machine=s390"); \
62 builtin_define ("__s390__"); \
63 if (TARGET_64BIT) \
64 builtin_define ("__s390x__"); \
65 } \
66 while (0)
67
68 /* Optional target features. */
69 extern int target_flags;
70
71 #define MASK_HARD_FLOAT 0x01
72 #define MASK_BACKCHAIN 0x02
73 #define MASK_SMALL_EXEC 0x04
74 #define MASK_DEBUG_ARG 0x08
75 #define MASK_64BIT 0x10
76 #define MASK_ZARCH 0x20
77 #define MASK_MVCLE 0x40
78
79 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
80 #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
81 #define TARGET_BACKCHAIN (target_flags & MASK_BACKCHAIN)
82 #define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC)
83 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
84 #define TARGET_64BIT (target_flags & MASK_64BIT)
85 #define TARGET_ZARCH (target_flags & MASK_ZARCH)
86 #define TARGET_MVCLE (target_flags & MASK_MVCLE)
87
88 /* ??? Once this actually works, it could be made a runtime option. */
89 #define TARGET_IBM_FLOAT 0
90 #define TARGET_IEEE_FLOAT 1
91
92 #ifdef DEFAULT_TARGET_64BIT
93 #define TARGET_DEFAULT 0x33
94 #else
95 #define TARGET_DEFAULT 0x3
96 #endif
97
98 #define TARGET_SWITCHES \
99 { { "hard-float", 1, N_("Use hardware fp")}, \
100 { "soft-float", -1, N_("Don't use hardware fp")}, \
101 { "backchain", 2, N_("Set backchain")}, \
102 { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \
103 { "small-exec", 4, N_("Use bras for execucable < 64k")}, \
104 { "no-small-exec",-4, N_("Don't use bras")}, \
105 { "debug", 8, N_("Additional debug prints")}, \
106 { "no-debug", -8, N_("Don't print additional debug prints")}, \
107 { "64", 16, N_("64 bit ABI")}, \
108 { "31", -16, N_("31 bit ABI")}, \
109 { "zarch", 32, N_("z/Architecture")}, \
110 { "esa", -32, N_("ESA/390 architecture")}, \
111 { "mvcle", 64, N_("mvcle use")}, \
112 { "no-mvcle", -64, N_("mvc&ex")}, \
113 { "", TARGET_DEFAULT, 0 } }
114
115 #define TARGET_OPTIONS \
116 { { "tune=", &s390_tune_string, \
117 N_("Schedule code for given CPU")}, \
118 { "arch=", &s390_arch_string, \
119 N_("Generate code for given CPU")}, \
120 }
121
122 /* Target version string. Overridden by the OS header. */
123 #ifdef DEFAULT_TARGET_64BIT
124 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
125 #else
126 #define TARGET_VERSION fprintf (stderr, " (S/390)");
127 #endif
128
129 /* Hooks to override options. */
130 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
131 #define OVERRIDE_OPTIONS override_options ()
132
133 /* Frame pointer is not used for debugging. */
134 #define CAN_DEBUG_WITHOUT_FP
135
136
137 /* Target machine storage layout. */
138
139 /* Everything is big-endian. */
140 #define BITS_BIG_ENDIAN 1
141 #define BYTES_BIG_ENDIAN 1
142 #define WORDS_BIG_ENDIAN 1
143
144 /* Width of a word, in units (bytes). */
145 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
146 #define MIN_UNITS_PER_WORD 4
147 #define MAX_BITS_PER_WORD 64
148
149 /* Function arguments and return values are promoted to word size. */
150 #define PROMOTE_FUNCTION_ARGS
151 #define PROMOTE_FUNCTION_RETURN
152 #define PROMOTE_FOR_CALL_ONLY
153
154 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
155 if (INTEGRAL_MODE_P (MODE) && \
156 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
157 (MODE) = Pmode; \
158 }
159
160 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
161 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
162
163 /* Boundary (in *bits*) on which stack pointer should be aligned. */
164 #define STACK_BOUNDARY 64
165
166 /* Allocation boundary (in *bits*) for the code of a function. */
167 #define FUNCTION_BOUNDARY 32
168
169 /* There is no point aligning anything to a rounder boundary than this. */
170 #define BIGGEST_ALIGNMENT 64
171
172 /* Alignment of field after `int : 0' in a structure. */
173 #define EMPTY_FIELD_BOUNDARY 32
174
175 /* Alignment on even addresses for LARL instruction. */
176 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
177 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
178
179 /* Alignment is not required by the hardware. */
180 #define STRICT_ALIGNMENT 0
181
182 /* Mode of stack savearea.
183 FUNCTION is VOIDmode because calling convention maintains SP.
184 BLOCK needs Pmode for SP.
185 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
186 #define STACK_SAVEAREA_MODE(LEVEL) \
187 (LEVEL == SAVE_FUNCTION ? VOIDmode \
188 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
189
190 /* Define target floating point format. */
191 #define TARGET_FLOAT_FORMAT \
192 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
193
194
195 /* Type layout. */
196
197 /* Sizes in bits of the source language data types. */
198 #define SHORT_TYPE_SIZE 16
199 #define INT_TYPE_SIZE 32
200 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
201 #define MAX_LONG_TYPE_SIZE 64
202 #define LONG_LONG_TYPE_SIZE 64
203 #define FLOAT_TYPE_SIZE 32
204 #define DOUBLE_TYPE_SIZE 64
205 #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */
206
207 /* We use "unsigned char" as default. */
208 #define DEFAULT_SIGNED_CHAR 0
209
210
211 /* Register usage. */
212
213 /* We have 16 general purpose registers (registers 0-15),
214 and 16 floating point registers (registers 16-31).
215 (On non-IEEE machines, we have only 4 fp registers.)
216
217 Amongst the general purpose registers, some are used
218 for specific purposes:
219 GPR 11: Hard frame pointer (if needed)
220 GPR 12: Global offset table pointer (if needed)
221 GPR 13: Literal pool base register
222 GPR 14: Return address register
223 GPR 15: Stack pointer
224
225 Registers 32-34 are 'fake' hard registers that do not
226 correspond to actual hardware:
227 Reg 32: Argument pointer
228 Reg 33: Condition code
229 Reg 34: Frame pointer */
230
231 #define FIRST_PSEUDO_REGISTER 35
232
233 /* Standard register usage. */
234 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
235 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
236 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
237 #define CC_REGNO_P(N) ((N) == 33)
238 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34)
239
240 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
241 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
242 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
243 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
244 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
245
246 #define BASE_REGISTER 13
247 #define RETURN_REGNUM 14
248 #define CC_REGNUM 33
249
250 /* Set up fixed registers and calling convention:
251
252 GPRs 0-5 are always call-clobbered,
253 GPRs 6-15 are always call-saved.
254 GPR 12 is fixed if used as GOT pointer.
255 GPR 13 is always fixed (as literal pool pointer).
256 GPR 14 is always fixed (as return address).
257 GPR 15 is always fixed (as stack pointer).
258 The 'fake' hard registers are call-clobbered and fixed.
259
260 On 31-bit, FPRs 18-19 are call-clobbered;
261 on 64-bit, FPRs 24-31 are call-clobbered.
262 The remaining FPRs are call-saved. */
263
264 #define FIXED_REGISTERS \
265 { 0, 0, 0, 0, \
266 0, 0, 0, 0, \
267 0, 0, 0, 0, \
268 0, 1, 1, 1, \
269 0, 0, 0, 0, \
270 0, 0, 0, 0, \
271 0, 0, 0, 0, \
272 0, 0, 0, 0, \
273 1, 1, 1 }
274
275 #define CALL_USED_REGISTERS \
276 { 1, 1, 1, 1, \
277 1, 1, 0, 0, \
278 0, 0, 0, 0, \
279 0, 1, 1, 1, \
280 1, 1, 1, 1, \
281 1, 1, 1, 1, \
282 1, 1, 1, 1, \
283 1, 1, 1, 1, \
284 1, 1, 1 }
285
286 #define CALL_REALLY_USED_REGISTERS \
287 { 1, 1, 1, 1, \
288 1, 1, 0, 0, \
289 0, 0, 0, 0, \
290 0, 0, 0, 0, \
291 1, 1, 1, 1, \
292 1, 1, 1, 1, \
293 1, 1, 1, 1, \
294 1, 1, 1, 1, \
295 1, 1, 1 }
296
297 #define CONDITIONAL_REGISTER_USAGE \
298 do \
299 { \
300 int i; \
301 \
302 if (flag_pic) \
303 { \
304 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
305 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
306 } \
307 if (TARGET_64BIT) \
308 { \
309 for (i = 24; i < 32; i++) \
310 call_used_regs[i] = call_really_used_regs[i] = 0; \
311 } \
312 else \
313 { \
314 for (i = 18; i < 20; i++) \
315 call_used_regs[i] = call_really_used_regs[i] = 0; \
316 } \
317 } while (0)
318
319 /* Preferred register allocation order. */
320 #define REG_ALLOC_ORDER \
321 { 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \
322 16, 17, 18, 19, 20, 21, 22, 23, \
323 24, 25, 26, 27, 28, 29, 30, 31, \
324 15, 32, 33, 34 }
325
326
327 /* Fitting values into registers. */
328
329 /* Integer modes <= word size fit into any GPR.
330 Integer modes > word size fit into successive GPRs, starting with
331 an even-numbered register.
332 SImode and DImode fit into FPRs as well.
333
334 Floating point modes <= word size fit into any FPR or GPR.
335 Floating point modes > word size (i.e. DFmode on 32-bit) fit
336 into any FPR, or an even-odd GPR pair.
337
338 Complex floating point modes fit either into two FPRs, or into
339 successive GPRs (again starting with an even number).
340
341 Condition code modes fit only into the CC register. */
342
343 #define HARD_REGNO_NREGS(REGNO, MODE) \
344 (FP_REGNO_P(REGNO)? \
345 (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
346 GENERAL_REGNO_P(REGNO)? \
347 ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
348 1)
349
350 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
351 (FP_REGNO_P(REGNO)? \
352 ((MODE) == SImode || (MODE) == DImode || \
353 GET_MODE_CLASS(MODE) == MODE_FLOAT || \
354 GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \
355 GENERAL_REGNO_P(REGNO)? \
356 (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \
357 CC_REGNO_P(REGNO)? \
358 GET_MODE_CLASS (MODE) == MODE_CC : \
359 FRAME_REGNO_P(REGNO)? \
360 (enum machine_mode) (MODE) == Pmode : \
361 0)
362
363 #define MODES_TIEABLE_P(MODE1, MODE2) \
364 (((MODE1) == SFmode || (MODE1) == DFmode) \
365 == ((MODE2) == SFmode || (MODE2) == DFmode))
366
367 /* Maximum number of registers to represent a value of mode MODE
368 in a register of class CLASS. */
369 #define CLASS_MAX_NREGS(CLASS, MODE) \
370 ((CLASS) == FP_REGS ? \
371 (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
372 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
373
374 /* If a 4-byte value is loaded into a FPR, it is placed into the
375 *upper* half of the register, not the lower. Therefore, we
376 cannot use SUBREGs to switch between modes in FP registers. */
377 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
378 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
379 ? reg_classes_intersect_p (FP_REGS, CLASS) : 0)
380
381 /* Register classes. */
382
383 /* We use the following register classes:
384 GENERAL_REGS All general purpose registers
385 ADDR_REGS All general purpose registers except %r0
386 (These registers can be used in address generation)
387 FP_REGS All floating point registers
388
389 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
390 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
391
392 NO_REGS No registers
393 ALL_REGS All registers
394
395 Note that the 'fake' frame pointer and argument pointer registers
396 are included amongst the address registers here. The condition
397 code register is only included in ALL_REGS. */
398
399 enum reg_class
400 {
401 NO_REGS, ADDR_REGS, GENERAL_REGS,
402 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
403 ALL_REGS, LIM_REG_CLASSES
404 };
405 #define N_REG_CLASSES (int) LIM_REG_CLASSES
406
407 #define REG_CLASS_NAMES \
408 { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \
409 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
410
411 /* Class -> register mapping. */
412 #define REG_CLASS_CONTENTS \
413 { \
414 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
415 { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \
416 { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \
417 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
418 { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \
419 { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \
420 { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \
421 }
422
423 /* Register -> class mapping. */
424 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
425 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
426
427 /* ADDR_REGS can be used as base or index register. */
428 #define INDEX_REG_CLASS ADDR_REGS
429 #define BASE_REG_CLASS ADDR_REGS
430
431 /* Check whether REGNO is a hard register of the suitable class
432 or a pseudo register currently allocated to one such. */
433 #define REGNO_OK_FOR_INDEX_P(REGNO) \
434 (((REGNO) < FIRST_PSEUDO_REGISTER \
435 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
436 || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
437 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
438
439
440 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
441 return the class of reg to actually use. */
442 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
443 s390_preferred_reload_class ((X), (CLASS))
444
445 /* We need a secondary reload when loading a PLUS which is
446 not a valid operand for LOAD ADDRESS. */
447 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
448 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
449
450 /* We need secondary memory to move data between GPRs and FPRs. */
451 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
452 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
453
454 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
455 because the movsi and movsf patterns don't handle r/f moves. */
456 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
457 (GET_MODE_BITSIZE (MODE) < 32 \
458 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
459 : MODE)
460
461
462 /* Define various machine-dependent constraint letters. */
463
464 #define REG_CLASS_FROM_LETTER(C) \
465 ((C) == 'a' ? ADDR_REGS : \
466 (C) == 'd' ? GENERAL_REGS : \
467 (C) == 'f' ? FP_REGS : NO_REGS)
468
469 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
470 ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \
471 (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \
472 (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \
473 (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0)
474
475 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
476
477 #define EXTRA_CONSTRAINT(OP, C) \
478 ((C) == 'Q' ? q_constraint (OP) : \
479 (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0)
480
481 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'Q')
482
483
484 /* Stack layout and calling conventions. */
485
486 /* Our stack grows from higher to lower addresses. However, local variables
487 are accessed by positive offsets, and function arguments are stored at
488 increasing addresses. */
489 #define STACK_GROWS_DOWNWARD
490 /* #undef FRAME_GROWS_DOWNWARD */
491 /* #undef ARGS_GROW_DOWNWARD */
492
493 /* The basic stack layout looks like this: the stack pointer points
494 to the register save area for called functions. Above that area
495 is the location to place outgoing arguments. Above those follow
496 dynamic allocations (alloca), and finally the local variables. */
497
498 /* Offset from stack-pointer to first location of outgoing args. */
499 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
500
501 /* Offset within stack frame to start allocating local variables at. */
502 extern int current_function_outgoing_args_size;
503 #define STARTING_FRAME_OFFSET \
504 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
505
506 /* Offset from the stack pointer register to an item dynamically
507 allocated on the stack, e.g., by `alloca'. */
508 #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET)
509
510 /* Offset of first parameter from the argument pointer register value.
511 We have a fake argument pointer register that points directly to
512 the argument area. */
513 #define FIRST_PARM_OFFSET(FNDECL) 0
514
515 /* The return address of the current frame is retrieved
516 from the initial value of register RETURN_REGNUM.
517 For frames farther back, we use the stack slot where
518 the corresponding RETURN_REGNUM register was saved. */
519
520 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
521 ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \
522 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
523
524 #define RETURN_ADDR_RTX(COUNT, FRAME) \
525 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
526
527 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
528 #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff))
529
530
531 /* Exception handling. */
532
533 /* Describe calling conventions for DWARF-2 exception handling. */
534 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
535 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
536 #define DWARF_FRAME_RETURN_COLUMN 14
537
538 /* Describe how we implement __builtin_eh_return. */
539 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
540 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
541 #define EH_RETURN_HANDLER_RTX \
542 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \
543 TARGET_64BIT? -48 : -40))
544
545 /* Select a format to encode pointers in exception handling data. */
546 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
547 (flag_pic \
548 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
549 : DW_EH_PE_absptr)
550
551
552 /* Frame registers. */
553
554 #define STACK_POINTER_REGNUM 15
555 #define FRAME_POINTER_REGNUM 34
556 #define HARD_FRAME_POINTER_REGNUM 11
557 #define ARG_POINTER_REGNUM 32
558
559 /* The static chain must be call-clobbered, but not used for
560 function argument passing. As register 1 is clobbered by
561 the trampoline code, we only have one option. */
562 #define STATIC_CHAIN_REGNUM 0
563
564 /* Number of hardware registers that go into the DWARF-2 unwind info.
565 To avoid ABI incompatibility, this number must not change even as
566 'fake' hard registers are added or removed. */
567 #define DWARF_FRAME_REGISTERS 34
568
569
570 /* Frame pointer and argument pointer elimination. */
571
572 #define FRAME_POINTER_REQUIRED 0
573
574 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
575
576 #define ELIMINABLE_REGS \
577 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
578 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
579 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
580 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
581
582 #define CAN_ELIMINATE(FROM, TO) (1)
583
584 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
585 { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
586 { (OFFSET) = 0; } \
587 else if ((FROM) == FRAME_POINTER_REGNUM \
588 && (TO) == HARD_FRAME_POINTER_REGNUM) \
589 { (OFFSET) = 0; } \
590 else if ((FROM) == ARG_POINTER_REGNUM \
591 && (TO) == HARD_FRAME_POINTER_REGNUM) \
592 { (OFFSET) = s390_arg_frame_offset (); } \
593 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
594 { (OFFSET) = s390_arg_frame_offset (); } \
595 else \
596 abort(); \
597 }
598
599
600 /* Stack arguments. */
601
602 /* We need current_function_outgoing_args to be valid. */
603 #define ACCUMULATE_OUTGOING_ARGS 1
604
605 /* Return doesn't modify the stack. */
606 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
607
608
609 /* Register arguments. */
610
611 typedef struct s390_arg_structure
612 {
613 int gprs; /* gpr so far */
614 int fprs; /* fpr so far */
615 }
616 CUMULATIVE_ARGS;
617
618 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \
619 ((CUM).gprs=0, (CUM).fprs=0)
620
621 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
622 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
623
624 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
625 s390_function_arg (&CUM, MODE, TYPE, NAMED)
626
627 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
628 s390_function_arg_pass_by_reference (MODE, TYPE)
629
630 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
631
632 /* Arguments can be placed in general registers 2 to 6,
633 or in floating point registers 0 and 2. */
634 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
635 (N) == 16 || (N) == 17)
636
637
638 /* Scalar return values. */
639
640 /* We return scalars in general purpose register 2 for integral values,
641 and floating point register 0 for fp values. */
642 #define FUNCTION_VALUE(VALTYPE, FUNC) \
643 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
644 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
645 || POINTER_TYPE_P (VALTYPE) \
646 ? word_mode : TYPE_MODE (VALTYPE), \
647 TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 16 : 2)
648
649 /* Define how to find the value returned by a library function assuming
650 the value has mode MODE. */
651 #define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \
652 || TARGET_SOFT_FLOAT ) ? 2 : 16)
653 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE))
654
655 /* Only gpr 2 and fpr 0 are ever used as return registers. */
656 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
657
658
659 /* Aggregate return values. */
660
661 /* The definition of this macro implies that there are cases where
662 a scalar value cannot be returned in registers. */
663 #define RETURN_IN_MEMORY(type) \
664 (TYPE_MODE (type) == BLKmode || \
665 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \
666 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT)
667
668 /* Structure value address is passed as invisible first argument (gpr 2). */
669 #define STRUCT_VALUE 0
670
671
672 /* Function entry and exit. */
673
674 /* When returning from a function, the stack pointer does not matter. */
675 #define EXIT_IGNORE_STACK 1
676
677
678 /* Profiling. */
679
680 #define FUNCTION_PROFILER(FILE, LABELNO) \
681 s390_function_profiler ((FILE), ((LABELNO)))
682
683 #define PROFILE_BEFORE_PROLOGUE 1
684
685
686 /* Implementing the varargs macros. */
687
688 #define BUILD_VA_LIST_TYPE(VALIST) \
689 (VALIST) = s390_build_va_list ()
690
691 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
692 s390_va_start (valist, nextarg)
693
694 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
695 s390_va_arg (valist, type)
696
697
698 /* Trampolines for nested functions. */
699
700 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20)
701
702 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
703 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
704
705 #define TRAMPOLINE_TEMPLATE(FILE) \
706 s390_trampoline_template (FILE)
707
708
709 /* Library calls. */
710
711 /* We should use memcpy, not bcopy. */
712 #define TARGET_MEM_FUNCTIONS
713
714
715 /* Addressing modes, and classification of registers for them. */
716
717 /* Recognize any constant value that is a valid address. */
718 #define CONSTANT_ADDRESS_P(X) 0
719
720 /* Maximum number of registers that can appear in a valid memory address. */
721 #define MAX_REGS_PER_ADDRESS 2
722
723 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
724 its validity for a certain class. We have two alternate definitions
725 for each of them. The usual definition accepts all pseudo regs; the
726 other rejects them all. The symbol REG_OK_STRICT causes the latter
727 definition to be used.
728
729 Most source files want to accept pseudo regs in the hope that they will
730 get allocated to the class that the insn wants them to be in.
731 Some source files that are used after register allocation
732 need to be strict. */
733
734 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
735 ((GET_MODE (X) == Pmode) && \
736 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
737 || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
738
739 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
740
741 #define REG_OK_FOR_INDEX_STRICT_P(X) \
742 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X))))
743
744 #define REG_OK_FOR_BASE_STRICT_P(X) \
745 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X))))
746
747 #ifndef REG_OK_STRICT
748 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
749 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
750 #else
751 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
752 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
753 #endif
754
755 /* S/390 has no mode dependent addresses. */
756 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
757
758 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
759 valid memory address for an instruction.
760 The MODE argument is the machine mode for the MEM expression
761 that wants to use this address. */
762 #ifdef REG_OK_STRICT
763 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
764 { \
765 if (legitimate_address_p (MODE, X, 1)) \
766 goto ADDR; \
767 }
768 #else
769 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
770 { \
771 if (legitimate_address_p (MODE, X, 0)) \
772 goto ADDR; \
773 }
774 #endif
775
776 /* Try machine-dependent ways of modifying an illegitimate address
777 to be legitimate. If we find one, return the new, valid address.
778 This macro is used in only one place: `memory_address' in explow.c. */
779 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
780 { \
781 (X) = legitimize_address (X, OLDX, MODE); \
782 if (memory_address_p (MODE, X)) \
783 goto WIN; \
784 }
785
786 /* Nonzero if the constant value X is a legitimate general operand.
787 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
788 #define LEGITIMATE_CONSTANT_P(X) \
789 legitimate_constant_p (X)
790
791 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
792 #define SYMBOLIC_CONST(X) \
793 (GET_CODE (X) == SYMBOL_REF \
794 || GET_CODE (X) == LABEL_REF \
795 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
796
797 #define TLS_SYMBOLIC_CONST(X) \
798 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
799 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
800
801
802 /* Condition codes. */
803
804 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
805 return the mode to be used for the comparison. */
806 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
807
808 /* Define the information needed to generate branch and scc insns. This is
809 stored from the compare operation. Note that we can't use "rtx" here
810 since it hasn't been defined! */
811 extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
812
813
814 /* Relative costs of operations. */
815
816 /* On s390, copy between fprs and gprs is expensive. */
817 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
818 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
819 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
820 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
821 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
822
823 /* A C expression for the cost of moving data of mode M between a
824 register and memory. A value of 2 is the default; this cost is
825 relative to those in `REGISTER_MOVE_COST'. */
826 #define MEMORY_MOVE_COST(M, C, I) 1
827
828 /* A C expression for the cost of a branch instruction. A value of 1
829 is the default; other values are interpreted relative to that. */
830 #define BRANCH_COST 1
831
832 /* Nonzero if access to memory by bytes is slow and undesirable. */
833 #define SLOW_BYTE_ACCESS 1
834
835 /* The maximum number of bytes that a single instruction can move quickly
836 between memory and registers or between two memory locations. */
837 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
838 #define MAX_MOVE_MAX 16
839
840 /* Determine whether to use move_by_pieces or block move insn. */
841 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
842 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
843 || (TARGET_64BIT && (SIZE) == 8) )
844
845 /* Determine whether to use clear_by_pieces or block clear insn. */
846 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
847 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
848 || (TARGET_64BIT && (SIZE) == 8) )
849
850 /* Don't perform CSE on function addresses. */
851 #define NO_FUNCTION_CSE
852
853
854 /* Sections. */
855
856 /* Output before read-only data. */
857 #define TEXT_SECTION_ASM_OP ".text"
858
859 /* Output before writable (initialized) data. */
860 #define DATA_SECTION_ASM_OP ".data"
861
862 /* Output before writable (uninitialized) data. */
863 #define BSS_SECTION_ASM_OP ".bss"
864
865 /* S/390 constant pool breaks the devices in crtstuff.c to control section
866 in where code resides. We have to write it as asm code. */
867 #ifndef __s390x__
868 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
869 asm (SECTION_OP "\n\
870 bras\t%r2,1f\n\
871 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
872 1: l\t%r3,0(%r2)\n\
873 bas\t%r14,0(%r3,%r2)\n\
874 .previous");
875 #endif
876
877
878 /* Position independent code. */
879
880 extern int flag_pic;
881
882 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
883
884 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
885
886
887 /* Assembler file format. */
888
889 /* Character to start a comment. */
890 #define ASM_COMMENT_START "#"
891
892 /* Declare an uninitialized external linkage data object. */
893 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
894 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
895
896 /* Globalizing directive for a label. */
897 #define GLOBAL_ASM_OP ".globl "
898
899 /* Advance the location counter to a multiple of 2**LOG bytes. */
900 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
901 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
902
903 /* Advance the location counter by SIZE bytes. */
904 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
905 fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE))
906
907 /* Output a reference to a user-level label named NAME. */
908 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
909 asm_fprintf ((FILE), "%U%s", (*targetm.strip_name_encoding) (NAME))
910
911 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
912 #define LOCAL_LABEL_PREFIX "."
913
914 /* How to refer to registers in assembler output. This sequence is
915 indexed by compiler's hard-register-number (see above). */
916 #define REGISTER_NAMES \
917 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
918 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
919 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
920 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
921 "%ap", "%cc", "%fp" \
922 }
923
924 /* Print operand X (an rtx) in assembler syntax to file FILE. */
925 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
926 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
927
928 /* Output an element of a case-vector that is absolute. */
929 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
930 do { \
931 char buf[32]; \
932 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
933 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
934 assemble_name ((FILE), buf); \
935 fputc ('\n', (FILE)); \
936 } while (0)
937
938 /* Output an element of a case-vector that is relative. */
939 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
940 do { \
941 char buf[32]; \
942 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
943 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
944 assemble_name ((FILE), buf); \
945 fputc ('-', (FILE)); \
946 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
947 assemble_name ((FILE), buf); \
948 fputc ('\n', (FILE)); \
949 } while (0)
950
951
952 /* Constant Pool for all symbols operands which are changed with
953 force_const_mem during insn generation (expand_insn). */
954
955 extern int s390_pool_count;
956 extern int s390_nr_constants;
957
958 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \
959 { \
960 struct pool_constant *pool; \
961 \
962 if (s390_pool_count == -1) \
963 { \
964 s390_nr_constants = 0; \
965 for (pool = first_pool; pool; pool = pool->next) \
966 if (pool->mark) s390_nr_constants++; \
967 return; \
968 } \
969 }
970
971 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \
972 { \
973 fprintf (FILE, ".LC%d:\n", LABELNO); \
974 \
975 /* Output the value of the constant itself. */ \
976 switch (GET_MODE_CLASS (MODE)) \
977 { \
978 case MODE_FLOAT: \
979 if (GET_CODE (EXP) != CONST_DOUBLE) \
980 abort (); \
981 \
982 REAL_VALUE_FROM_CONST_DOUBLE (r, EXP); \
983 assemble_real (r, MODE, ALIGN); \
984 break; \
985 \
986 case MODE_INT: \
987 case MODE_PARTIAL_INT: \
988 if (GET_CODE (EXP) == CONST \
989 || GET_CODE (EXP) == SYMBOL_REF \
990 || GET_CODE (EXP) == LABEL_REF) \
991 { \
992 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE); \
993 s390_output_symbolic_const (FILE, EXP); \
994 fputc ('\n', (FILE)); \
995 } \
996 else \
997 { \
998 assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1); \
999 if (GET_MODE_SIZE (MODE) == 1) \
1000 ASM_OUTPUT_SKIP ((FILE), 1); \
1001 } \
1002 break; \
1003 \
1004 default: \
1005 abort (); \
1006 } \
1007 goto WIN; \
1008 }
1009
1010
1011 /* Miscellaneous parameters. */
1012
1013 /* Define the codes that are matched by predicates in aux-output.c. */
1014 #define PREDICATE_CODES \
1015 {"s_operand", { SUBREG, MEM }}, \
1016 {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
1017 {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
1018 {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
1019 {"load_multiple_operation", {PARALLEL}}, \
1020 {"store_multiple_operation", {PARALLEL}}, \
1021 {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
1022 {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
1023 CONST_INT, CONST_DOUBLE }}, \
1024 {"s390_plus_operand", { PLUS }},
1025
1026 /* Specify the machine mode that this machine uses for the index in the
1027 tablejump instruction. */
1028 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
1029
1030 /* Load from integral MODE < SI from memory into register makes sign_extend
1031 or zero_extend
1032 In our case sign_extension happens for Halfwords, other no extension. */
1033 #define LOAD_EXTEND_OP(MODE) \
1034 (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \
1035 (MODE) == HImode ? SIGN_EXTEND : NIL) \
1036 : ((MODE) == HImode ? SIGN_EXTEND : NIL))
1037
1038 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1039 is done just by pretending it is already truncated. */
1040 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1041
1042 /* Specify the machine mode that pointers have.
1043 After generation of rtl, the compiler makes no further distinction
1044 between pointers and any other objects of this machine mode. */
1045 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
1046
1047 /* A function address in a call instruction is a byte address (for
1048 indexing purposes) so give the MEM rtx a byte's mode. */
1049 #define FUNCTION_MODE QImode
1050
1051 /* This macro definition sets up a default value for `main' to return. */
1052 #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node)
1053
1054 /* In rare cases, correct code generation requires extra machine dependent
1055 processing between the second jump optimization pass and delayed branch
1056 scheduling. On those machines, define this macro as a C statement to act on
1057 the code starting at INSN. */
1058 #define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN)
1059
1060 #endif
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