| blob | d60b9ac172f7b2a51f11e2942edf729b07ab29c0 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; `unspec' values used in rs6000.md:
26 ;; Number Use
27 ;; 0 frsp for POWER machines
28 ;; 0/v blockage
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
32 ;; 8 movsi_got
33 ;; 9/v eh_reg_restore
34 ;; 10 fctiwz
35 ;; 15 load_macho_picbase
36 ;; 16 macho_correct_pic
37 ;; 19 movesi_from_cr
38 ;; 20 movsi_to_cr
39 \f
40 ;; Define an insn type attribute. This is used in function unit delay
41 ;; computations.
42 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat"
43 (const_string "integer"))
45 ;; Length (in bytes).
46 ; '(pc)' in the following doesn't include the instruction itself; it is
47 ; calculated as if the instruction had zero size.
48 (define_attr "length" ""
49 (if_then_else (eq_attr "type" "branch")
50 (if_then_else (and (ge (minus (match_dup 0) (pc))
51 (const_int -32768))
52 (lt (minus (match_dup 0) (pc))
53 (const_int 32764)))
54 (const_int 4)
55 (const_int 8))
56 (const_int 4)))
58 ;; Processor type -- this attribute must exactly match the processor_type
59 ;; enumeration in rs6000.h.
61 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
62 (const (symbol_ref "rs6000_cpu_attr")))
64 (automata_option "ndfa")
66 (include "rios1.md")
67 (include "rios2.md")
68 (include "rs64.md")
69 (include "mpc.md")
70 (include "40x.md")
71 (include "603.md")
72 (include "6xx.md")
73 (include "7xx.md")
74 (include "7450.md")
75 (include "power4.md")
77 \f
78 ;; Start with fixed-point load and store insns. Here we put only the more
79 ;; complex forms. Basic data transfer is done later.
81 (define_expand "zero_extendqidi2"
82 [(set (match_operand:DI 0 "gpc_reg_operand" "")
83 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
84 "TARGET_POWERPC64"
85 "")
87 (define_insn ""
88 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
89 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
90 "TARGET_POWERPC64"
91 "@
92 lbz%U1%X1 %0,%1
93 rldicl %0,%1,0,56"
94 [(set_attr "type" "load,*")])
96 (define_insn ""
97 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
98 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
99 (const_int 0)))
100 (clobber (match_scratch:DI 2 "=r,r"))]
101 "TARGET_POWERPC64"
102 "@
103 rldicl. %2,%1,0,56
104 #"
105 [(set_attr "type" "compare")
106 (set_attr "length" "4,8")])
108 (define_split
109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
110 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
111 (const_int 0)))
112 (clobber (match_scratch:DI 2 ""))]
113 "TARGET_POWERPC64 && reload_completed"
114 [(set (match_dup 2)
115 (zero_extend:DI (match_dup 1)))
116 (set (match_dup 0)
117 (compare:CC (match_dup 2)
118 (const_int 0)))]
119 "")
121 (define_insn ""
122 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
123 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
124 (const_int 0)))
125 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
126 (zero_extend:DI (match_dup 1)))]
127 "TARGET_POWERPC64"
128 "@
129 rldicl. %0,%1,0,56
130 #"
131 [(set_attr "type" "compare")
132 (set_attr "length" "4,8")])
134 (define_split
135 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
136 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
137 (const_int 0)))
138 (set (match_operand:DI 0 "gpc_reg_operand" "")
139 (zero_extend:DI (match_dup 1)))]
140 "TARGET_POWERPC64 && reload_completed"
141 [(set (match_dup 0)
142 (zero_extend:DI (match_dup 1)))
143 (set (match_dup 2)
144 (compare:CC (match_dup 0)
145 (const_int 0)))]
146 "")
148 (define_insn "extendqidi2"
149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
150 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
151 "TARGET_POWERPC64"
152 "extsb %0,%1")
154 (define_insn ""
155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
156 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
157 (const_int 0)))
158 (clobber (match_scratch:DI 2 "=r,r"))]
159 "TARGET_POWERPC64"
160 "@
161 extsb. %2,%1
162 #"
163 [(set_attr "type" "compare")
164 (set_attr "length" "4,8")])
166 (define_split
167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
168 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
169 (const_int 0)))
170 (clobber (match_scratch:DI 2 ""))]
171 "TARGET_POWERPC64 && reload_completed"
172 [(set (match_dup 2)
173 (sign_extend:DI (match_dup 1)))
174 (set (match_dup 0)
175 (compare:CC (match_dup 2)
176 (const_int 0)))]
177 "")
179 (define_insn ""
180 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
181 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
182 (const_int 0)))
183 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
184 (sign_extend:DI (match_dup 1)))]
185 "TARGET_POWERPC64"
186 "@
187 extsb. %0,%1
188 #"
189 [(set_attr "type" "compare")
190 (set_attr "length" "4,8")])
192 (define_split
193 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
194 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
195 (const_int 0)))
196 (set (match_operand:DI 0 "gpc_reg_operand" "")
197 (sign_extend:DI (match_dup 1)))]
198 "TARGET_POWERPC64 && reload_completed"
199 [(set (match_dup 0)
200 (sign_extend:DI (match_dup 1)))
201 (set (match_dup 2)
202 (compare:CC (match_dup 0)
203 (const_int 0)))]
204 "")
206 (define_expand "zero_extendhidi2"
207 [(set (match_operand:DI 0 "gpc_reg_operand" "")
208 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
209 "TARGET_POWERPC64"
210 "")
212 (define_insn ""
213 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
214 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
215 "TARGET_POWERPC64"
216 "@
217 lhz%U1%X1 %0,%1
218 rldicl %0,%1,0,48"
219 [(set_attr "type" "load,*")])
221 (define_insn ""
222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
223 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
224 (const_int 0)))
225 (clobber (match_scratch:DI 2 "=r,r"))]
226 "TARGET_POWERPC64"
227 "@
228 rldicl. %2,%1,0,48
229 #"
230 [(set_attr "type" "compare")
231 (set_attr "length" "4,8")])
233 (define_split
234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
235 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
236 (const_int 0)))
237 (clobber (match_scratch:DI 2 ""))]
238 "TARGET_POWERPC64 && reload_completed"
239 [(set (match_dup 2)
240 (zero_extend:DI (match_dup 1)))
241 (set (match_dup 0)
242 (compare:CC (match_dup 2)
243 (const_int 0)))]
244 "")
246 (define_insn ""
247 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
248 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
249 (const_int 0)))
250 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
251 (zero_extend:DI (match_dup 1)))]
252 "TARGET_POWERPC64"
253 "@
254 rldicl. %0,%1,0,48
255 #"
256 [(set_attr "type" "compare")
257 (set_attr "length" "4,8")])
259 (define_split
260 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
261 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
262 (const_int 0)))
263 (set (match_operand:DI 0 "gpc_reg_operand" "")
264 (zero_extend:DI (match_dup 1)))]
265 "TARGET_POWERPC64 && reload_completed"
266 [(set (match_dup 0)
267 (zero_extend:DI (match_dup 1)))
268 (set (match_dup 2)
269 (compare:CC (match_dup 0)
270 (const_int 0)))]
271 "")
273 (define_expand "extendhidi2"
274 [(set (match_operand:DI 0 "gpc_reg_operand" "")
275 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
276 "TARGET_POWERPC64"
277 "")
279 (define_insn ""
280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
281 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
282 "TARGET_POWERPC64"
283 "@
284 lha%U1%X1 %0,%1
285 extsh %0,%1"
286 [(set_attr "type" "load_ext,*")])
288 (define_insn ""
289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
290 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
291 (const_int 0)))
292 (clobber (match_scratch:DI 2 "=r,r"))]
293 "TARGET_POWERPC64"
294 "@
295 extsh. %2,%1
296 #"
297 [(set_attr "type" "compare")
298 (set_attr "length" "4,8")])
300 (define_split
301 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
302 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
303 (const_int 0)))
304 (clobber (match_scratch:DI 2 ""))]
305 "TARGET_POWERPC64 && reload_completed"
306 [(set (match_dup 2)
307 (sign_extend:DI (match_dup 1)))
308 (set (match_dup 0)
309 (compare:CC (match_dup 2)
310 (const_int 0)))]
311 "")
313 (define_insn ""
314 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
315 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
316 (const_int 0)))
317 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
318 (sign_extend:DI (match_dup 1)))]
319 "TARGET_POWERPC64"
320 "@
321 extsh. %0,%1
322 #"
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
326 (define_split
327 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (const_int 0)))
330 (set (match_operand:DI 0 "gpc_reg_operand" "")
331 (sign_extend:DI (match_dup 1)))]
332 "TARGET_POWERPC64 && reload_completed"
333 [(set (match_dup 0)
334 (sign_extend:DI (match_dup 1)))
335 (set (match_dup 2)
336 (compare:CC (match_dup 0)
337 (const_int 0)))]
338 "")
340 (define_expand "zero_extendsidi2"
341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
342 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
343 "TARGET_POWERPC64"
344 "")
346 (define_insn ""
347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
348 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
349 "TARGET_POWERPC64"
350 "@
351 lwz%U1%X1 %0,%1
352 rldicl %0,%1,0,32"
353 [(set_attr "type" "load,*")])
355 (define_insn ""
356 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (clobber (match_scratch:DI 2 "=r,r"))]
360 "TARGET_POWERPC64"
361 "@
362 rldicl. %2,%1,0,32
363 #"
364 [(set_attr "type" "compare")
365 (set_attr "length" "4,8")])
367 (define_split
368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
369 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
370 (const_int 0)))
371 (clobber (match_scratch:DI 2 ""))]
372 "TARGET_POWERPC64 && reload_completed"
373 [(set (match_dup 2)
374 (zero_extend:DI (match_dup 1)))
375 (set (match_dup 0)
376 (compare:CC (match_dup 2)
377 (const_int 0)))]
378 "")
380 (define_insn ""
381 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
382 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
383 (const_int 0)))
384 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
385 (zero_extend:DI (match_dup 1)))]
386 "TARGET_POWERPC64"
387 "@
388 rldicl. %0,%1,0,32
389 #"
390 [(set_attr "type" "compare")
391 (set_attr "length" "4,8")])
393 (define_split
394 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
395 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (const_int 0)))
397 (set (match_operand:DI 0 "gpc_reg_operand" "")
398 (zero_extend:DI (match_dup 1)))]
399 "TARGET_POWERPC64 && reload_completed"
400 [(set (match_dup 0)
401 (zero_extend:DI (match_dup 1)))
402 (set (match_dup 2)
403 (compare:CC (match_dup 0)
404 (const_int 0)))]
405 "")
407 (define_expand "extendsidi2"
408 [(set (match_operand:DI 0 "gpc_reg_operand" "")
409 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
410 "TARGET_POWERPC64"
411 "")
413 (define_insn ""
414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
415 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
416 "TARGET_POWERPC64"
417 "@
418 lwa%U1%X1 %0,%1
419 extsw %0,%1"
420 [(set_attr "type" "load_ext,*")])
422 (define_insn ""
423 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
424 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
425 (const_int 0)))
426 (clobber (match_scratch:DI 2 "=r,r"))]
427 "TARGET_POWERPC64"
428 "@
429 extsw. %2,%1
430 #"
431 [(set_attr "type" "compare")
432 (set_attr "length" "4,8")])
434 (define_split
435 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
436 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
437 (const_int 0)))
438 (clobber (match_scratch:DI 2 ""))]
439 "TARGET_POWERPC64 && reload_completed"
440 [(set (match_dup 2)
441 (sign_extend:DI (match_dup 1)))
442 (set (match_dup 0)
443 (compare:CC (match_dup 2)
444 (const_int 0)))]
445 "")
447 (define_insn ""
448 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
449 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
450 (const_int 0)))
451 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
452 (sign_extend:DI (match_dup 1)))]
453 "TARGET_POWERPC64"
454 "@
455 extsw. %0,%1
456 #"
457 [(set_attr "type" "compare")
458 (set_attr "length" "4,8")])
460 (define_split
461 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (const_int 0)))
464 (set (match_operand:DI 0 "gpc_reg_operand" "")
465 (sign_extend:DI (match_dup 1)))]
466 "TARGET_POWERPC64 && reload_completed"
467 [(set (match_dup 0)
468 (sign_extend:DI (match_dup 1)))
469 (set (match_dup 2)
470 (compare:CC (match_dup 0)
471 (const_int 0)))]
472 "")
474 (define_expand "zero_extendqisi2"
475 [(set (match_operand:SI 0 "gpc_reg_operand" "")
476 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
477 ""
478 "")
480 (define_insn ""
481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
482 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
483 ""
484 "@
485 lbz%U1%X1 %0,%1
486 {rlinm|rlwinm} %0,%1,0,0xff"
487 [(set_attr "type" "load,*")])
489 (define_insn ""
490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
491 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
492 (const_int 0)))
493 (clobber (match_scratch:SI 2 "=r,r"))]
494 ""
495 "@
496 {andil.|andi.} %2,%1,0xff
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
501 (define_split
502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
503 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (clobber (match_scratch:SI 2 ""))]
506 "reload_completed"
507 [(set (match_dup 2)
508 (zero_extend:SI (match_dup 1)))
509 (set (match_dup 0)
510 (compare:CC (match_dup 2)
511 (const_int 0)))]
512 "")
514 (define_insn ""
515 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
516 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
517 (const_int 0)))
518 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
519 (zero_extend:SI (match_dup 1)))]
520 ""
521 "@
522 {andil.|andi.} %0,%1,0xff
523 #"
524 [(set_attr "type" "compare")
525 (set_attr "length" "4,8")])
527 (define_split
528 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (const_int 0)))
531 (set (match_operand:SI 0 "gpc_reg_operand" "")
532 (zero_extend:SI (match_dup 1)))]
533 "reload_completed"
534 [(set (match_dup 0)
535 (zero_extend:SI (match_dup 1)))
536 (set (match_dup 2)
537 (compare:CC (match_dup 0)
538 (const_int 0)))]
539 "")
541 (define_expand "extendqisi2"
542 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
543 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
544 ""
545 "
546 {
547 if (TARGET_POWERPC)
548 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
549 else if (TARGET_POWER)
550 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
551 else
552 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
553 DONE;
554 }")
556 (define_insn "extendqisi2_ppc"
557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
558 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
559 "TARGET_POWERPC"
560 "extsb %0,%1")
562 (define_insn ""
563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (clobber (match_scratch:SI 2 "=r,r"))]
567 "TARGET_POWERPC"
568 "@
569 extsb. %2,%1
570 #"
571 [(set_attr "type" "compare")
572 (set_attr "length" "4,8")])
574 (define_split
575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
576 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
577 (const_int 0)))
578 (clobber (match_scratch:SI 2 ""))]
579 "TARGET_POWERPC && reload_completed"
580 [(set (match_dup 2)
581 (sign_extend:SI (match_dup 1)))
582 (set (match_dup 0)
583 (compare:CC (match_dup 2)
584 (const_int 0)))]
585 "")
587 (define_insn ""
588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
589 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
590 (const_int 0)))
591 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
592 (sign_extend:SI (match_dup 1)))]
593 "TARGET_POWERPC"
594 "@
595 extsb. %0,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
600 (define_split
601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (set (match_operand:SI 0 "gpc_reg_operand" "")
605 (sign_extend:SI (match_dup 1)))]
606 "TARGET_POWERPC && reload_completed"
607 [(set (match_dup 0)
608 (sign_extend:SI (match_dup 1)))
609 (set (match_dup 2)
610 (compare:CC (match_dup 0)
611 (const_int 0)))]
612 "")
614 (define_expand "extendqisi2_power"
615 [(parallel [(set (match_dup 2)
616 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
617 (const_int 24)))
618 (clobber (scratch:SI))])
619 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
620 (ashiftrt:SI (match_dup 2)
621 (const_int 24)))
622 (clobber (scratch:SI))])]
623 "TARGET_POWER"
624 "
625 { operands[1] = gen_lowpart (SImode, operands[1]);
626 operands[2] = gen_reg_rtx (SImode); }")
628 (define_expand "extendqisi2_no_power"
629 [(set (match_dup 2)
630 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
631 (const_int 24)))
632 (set (match_operand:SI 0 "gpc_reg_operand" "")
633 (ashiftrt:SI (match_dup 2)
634 (const_int 24)))]
635 "! TARGET_POWER && ! TARGET_POWERPC"
636 "
637 { operands[1] = gen_lowpart (SImode, operands[1]);
638 operands[2] = gen_reg_rtx (SImode); }")
640 (define_expand "zero_extendqihi2"
641 [(set (match_operand:HI 0 "gpc_reg_operand" "")
642 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
643 ""
644 "")
646 (define_insn ""
647 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
648 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
649 ""
650 "@
651 lbz%U1%X1 %0,%1
652 {rlinm|rlwinm} %0,%1,0,0xff"
653 [(set_attr "type" "load,*")])
655 (define_insn ""
656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
657 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
658 (const_int 0)))
659 (clobber (match_scratch:HI 2 "=r,r"))]
660 ""
661 "@
662 {andil.|andi.} %2,%1,0xff
663 #"
664 [(set_attr "type" "compare")
665 (set_attr "length" "4,8")])
667 (define_split
668 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
669 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
670 (const_int 0)))
671 (clobber (match_scratch:HI 2 ""))]
672 "reload_completed"
673 [(set (match_dup 2)
674 (zero_extend:HI (match_dup 1)))
675 (set (match_dup 0)
676 (compare:CC (match_dup 2)
677 (const_int 0)))]
678 "")
680 (define_insn ""
681 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
682 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
683 (const_int 0)))
684 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
685 (zero_extend:HI (match_dup 1)))]
686 ""
687 "@
688 {andil.|andi.} %0,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
693 (define_split
694 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (set (match_operand:HI 0 "gpc_reg_operand" "")
698 (zero_extend:HI (match_dup 1)))]
699 "reload_completed"
700 [(set (match_dup 0)
701 (zero_extend:HI (match_dup 1)))
702 (set (match_dup 2)
703 (compare:CC (match_dup 0)
704 (const_int 0)))]
705 "")
707 (define_expand "extendqihi2"
708 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
709 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
710 ""
711 "
712 {
713 if (TARGET_POWERPC)
714 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
715 else if (TARGET_POWER)
716 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
717 else
718 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
719 DONE;
720 }")
722 (define_insn "extendqihi2_ppc"
723 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
724 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
725 "TARGET_POWERPC"
726 "extsb %0,%1")
728 (define_insn ""
729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
730 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
731 (const_int 0)))
732 (clobber (match_scratch:HI 2 "=r,r"))]
733 "TARGET_POWERPC"
734 "@
735 extsb. %2,%1
736 #"
737 [(set_attr "type" "compare")
738 (set_attr "length" "4,8")])
740 (define_split
741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
742 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
743 (const_int 0)))
744 (clobber (match_scratch:HI 2 ""))]
745 "TARGET_POWERPC && reload_completed"
746 [(set (match_dup 2)
747 (sign_extend:HI (match_dup 1)))
748 (set (match_dup 0)
749 (compare:CC (match_dup 2)
750 (const_int 0)))]
751 "")
753 (define_insn ""
754 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
755 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
756 (const_int 0)))
757 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
758 (sign_extend:HI (match_dup 1)))]
759 "TARGET_POWERPC"
760 "@
761 extsb. %0,%1
762 #"
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
766 (define_split
767 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
769 (const_int 0)))
770 (set (match_operand:HI 0 "gpc_reg_operand" "")
771 (sign_extend:HI (match_dup 1)))]
772 "TARGET_POWERPC && reload_completed"
773 [(set (match_dup 0)
774 (sign_extend:HI (match_dup 1)))
775 (set (match_dup 2)
776 (compare:CC (match_dup 0)
777 (const_int 0)))]
778 "")
780 (define_expand "extendqihi2_power"
781 [(parallel [(set (match_dup 2)
782 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
783 (const_int 24)))
784 (clobber (scratch:SI))])
785 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
786 (ashiftrt:SI (match_dup 2)
787 (const_int 24)))
788 (clobber (scratch:SI))])]
789 "TARGET_POWER"
790 "
791 { operands[0] = gen_lowpart (SImode, operands[0]);
792 operands[1] = gen_lowpart (SImode, operands[1]);
793 operands[2] = gen_reg_rtx (SImode); }")
795 (define_expand "extendqihi2_no_power"
796 [(set (match_dup 2)
797 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
798 (const_int 24)))
799 (set (match_operand:HI 0 "gpc_reg_operand" "")
800 (ashiftrt:SI (match_dup 2)
801 (const_int 24)))]
802 "! TARGET_POWER && ! TARGET_POWERPC"
803 "
804 { operands[0] = gen_lowpart (SImode, operands[0]);
805 operands[1] = gen_lowpart (SImode, operands[1]);
806 operands[2] = gen_reg_rtx (SImode); }")
808 (define_expand "zero_extendhisi2"
809 [(set (match_operand:SI 0 "gpc_reg_operand" "")
810 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
811 ""
812 "")
814 (define_insn ""
815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
816 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
817 ""
818 "@
819 lhz%U1%X1 %0,%1
820 {rlinm|rlwinm} %0,%1,0,0xffff"
821 [(set_attr "type" "load,*")])
823 (define_insn ""
824 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
825 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
826 (const_int 0)))
827 (clobber (match_scratch:SI 2 "=r,r"))]
828 ""
829 "@
830 {andil.|andi.} %2,%1,0xffff
831 #"
832 [(set_attr "type" "compare")
833 (set_attr "length" "4,8")])
835 (define_split
836 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
837 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
838 (const_int 0)))
839 (clobber (match_scratch:SI 2 ""))]
840 "reload_completed"
841 [(set (match_dup 2)
842 (zero_extend:SI (match_dup 1)))
843 (set (match_dup 0)
844 (compare:CC (match_dup 2)
845 (const_int 0)))]
846 "")
848 (define_insn ""
849 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
850 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
851 (const_int 0)))
852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
853 (zero_extend:SI (match_dup 1)))]
854 ""
855 "@
856 {andil.|andi.} %0,%1,0xffff
857 #"
858 [(set_attr "type" "compare")
859 (set_attr "length" "4,8")])
861 (define_split
862 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (const_int 0)))
865 (set (match_operand:SI 0 "gpc_reg_operand" "")
866 (zero_extend:SI (match_dup 1)))]
867 "reload_completed"
868 [(set (match_dup 0)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 2)
871 (compare:CC (match_dup 0)
872 (const_int 0)))]
873 "")
875 (define_expand "extendhisi2"
876 [(set (match_operand:SI 0 "gpc_reg_operand" "")
877 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
878 ""
879 "")
881 (define_insn ""
882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
883 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
884 ""
885 "@
886 lha%U1%X1 %0,%1
887 {exts|extsh} %0,%1"
888 [(set_attr "type" "load_ext,*")])
890 (define_insn ""
891 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
892 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
893 (const_int 0)))
894 (clobber (match_scratch:SI 2 "=r,r"))]
895 ""
896 "@
897 {exts.|extsh.} %2,%1
898 #"
899 [(set_attr "type" "compare")
900 (set_attr "length" "4,8")])
902 (define_split
903 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
904 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
905 (const_int 0)))
906 (clobber (match_scratch:SI 2 ""))]
907 "reload_completed"
908 [(set (match_dup 2)
909 (sign_extend:SI (match_dup 1)))
910 (set (match_dup 0)
911 (compare:CC (match_dup 2)
912 (const_int 0)))]
913 "")
915 (define_insn ""
916 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
917 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
918 (const_int 0)))
919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
920 (sign_extend:SI (match_dup 1)))]
921 ""
922 "@
923 {exts.|extsh.} %0,%1
924 #"
925 [(set_attr "type" "compare")
926 (set_attr "length" "4,8")])
927 \f
928 (define_split
929 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
931 (const_int 0)))
932 (set (match_operand:SI 0 "gpc_reg_operand" "")
933 (sign_extend:SI (match_dup 1)))]
934 "reload_completed"
935 [(set (match_dup 0)
936 (sign_extend:SI (match_dup 1)))
937 (set (match_dup 2)
938 (compare:CC (match_dup 0)
939 (const_int 0)))]
940 "")
942 ;; Fixed-point arithmetic insns.
944 ;; Discourage ai/addic because of carry but provide it in an alternative
945 ;; allowing register zero as source.
946 (define_expand "addsi3"
947 [(set (match_operand:SI 0 "gpc_reg_operand" "")
948 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
949 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
950 ""
951 "
952 {
953 if (GET_CODE (operands[2]) == CONST_INT
954 && ! add_operand (operands[2], SImode))
955 {
956 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
957 ? operands[0] : gen_reg_rtx (SImode));
959 HOST_WIDE_INT val = INTVAL (operands[2]);
960 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
961 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
963 /* The ordering here is important for the prolog expander.
964 When space is allocated from the stack, adding 'low' first may
965 produce a temporary deallocation (which would be bad). */
966 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
967 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
968 DONE;
969 }
970 }")
972 (define_insn "*addsi3_internal1"
973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
974 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
975 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
976 ""
977 "@
978 {cax|add} %0,%1,%2
979 {cal %0,%2(%1)|addi %0,%1,%2}
980 {ai|addic} %0,%1,%2
981 {cau|addis} %0,%1,%v2"
982 [(set_attr "length" "4,4,4,4")])
984 (define_insn "addsi3_high"
985 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
986 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
987 (high:SI (match_operand 2 "" ""))))]
988 "TARGET_MACHO && !TARGET_64BIT"
989 "{cau|addis} %0,%1,ha16(%2)"
990 [(set_attr "length" "4")])
992 (define_insn "*addsi3_internal2"
993 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
994 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
995 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
996 (const_int 0)))
997 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
998 "! TARGET_POWERPC64"
999 "@
1000 {cax.|add.} %3,%1,%2
1001 {ai.|addic.} %3,%1,%2
1002 #
1003 #"
1004 [(set_attr "type" "fast_compare,compare,compare,compare")
1005 (set_attr "length" "4,4,8,8")])
1007 (define_split
1008 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1009 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1010 (match_operand:SI 2 "reg_or_short_operand" ""))
1011 (const_int 0)))
1012 (clobber (match_scratch:SI 3 ""))]
1013 "! TARGET_POWERPC64 && reload_completed"
1014 [(set (match_dup 3)
1015 (plus:SI (match_dup 1)
1016 (match_dup 2)))
1017 (set (match_dup 0)
1018 (compare:CC (match_dup 3)
1019 (const_int 0)))]
1020 "")
1022 (define_insn "*addsi3_internal3"
1023 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1024 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1025 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1026 (const_int 0)))
1027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1028 (plus:SI (match_dup 1)
1029 (match_dup 2)))]
1030 "! TARGET_POWERPC64"
1031 "@
1032 {cax.|add.} %0,%1,%2
1033 {ai.|addic.} %0,%1,%2
1034 #
1035 #"
1036 [(set_attr "type" "fast_compare,compare,compare,compare")
1037 (set_attr "length" "4,4,8,8")])
1039 (define_split
1040 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1041 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1042 (match_operand:SI 2 "reg_or_short_operand" ""))
1043 (const_int 0)))
1044 (set (match_operand:SI 0 "gpc_reg_operand" "")
1045 (plus:SI (match_dup 1) (match_dup 2)))]
1046 "! TARGET_POWERPC64 && reload_completed"
1047 [(set (match_dup 0)
1048 (plus:SI (match_dup 1)
1049 (match_dup 2)))
1050 (set (match_dup 3)
1051 (compare:CC (match_dup 0)
1052 (const_int 0)))]
1053 "")
1055 ;; Split an add that we can't do in one insn into two insns, each of which
1056 ;; does one 16-bit part. This is used by combine. Note that the low-order
1057 ;; add should be last in case the result gets used in an address.
1059 (define_split
1060 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1061 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1062 (match_operand:SI 2 "non_add_cint_operand" "")))]
1063 ""
1064 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1065 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1066 "
1067 {
1068 HOST_WIDE_INT val = INTVAL (operands[2]);
1069 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1070 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1072 operands[3] = GEN_INT (rest);
1073 operands[4] = GEN_INT (low);
1074 }")
1076 (define_insn "one_cmplsi2"
1077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1078 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1079 ""
1080 "nor %0,%1,%1")
1082 (define_insn ""
1083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1084 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1085 (const_int 0)))
1086 (clobber (match_scratch:SI 2 "=r,r"))]
1087 "! TARGET_POWERPC64"
1088 "@
1089 nor. %2,%1,%1
1090 #"
1091 [(set_attr "type" "compare")
1092 (set_attr "length" "4,8")])
1094 (define_split
1095 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1096 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1097 (const_int 0)))
1098 (clobber (match_scratch:SI 2 ""))]
1099 "! TARGET_POWERPC64 && reload_completed"
1100 [(set (match_dup 2)
1101 (not:SI (match_dup 1)))
1102 (set (match_dup 0)
1103 (compare:CC (match_dup 2)
1104 (const_int 0)))]
1105 "")
1107 (define_insn ""
1108 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1109 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1110 (const_int 0)))
1111 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1112 (not:SI (match_dup 1)))]
1113 "! TARGET_POWERPC64"
1114 "@
1115 nor. %0,%1,%1
1116 #"
1117 [(set_attr "type" "compare")
1118 (set_attr "length" "4,8")])
1120 (define_split
1121 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1122 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1123 (const_int 0)))
1124 (set (match_operand:SI 0 "gpc_reg_operand" "")
1125 (not:SI (match_dup 1)))]
1126 "! TARGET_POWERPC64 && reload_completed"
1127 [(set (match_dup 0)
1128 (not:SI (match_dup 1)))
1129 (set (match_dup 2)
1130 (compare:CC (match_dup 0)
1131 (const_int 0)))]
1132 "")
1134 (define_insn ""
1135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1137 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1138 "! TARGET_POWERPC"
1139 "{sf%I1|subf%I1c} %0,%2,%1")
1141 (define_insn ""
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1143 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1144 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1145 "TARGET_POWERPC"
1146 "@
1147 subf %0,%2,%1
1148 subfic %0,%2,%1")
1150 (define_insn ""
1151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1152 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1153 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1154 (const_int 0)))
1155 (clobber (match_scratch:SI 3 "=r,r"))]
1156 "! TARGET_POWERPC"
1157 "@
1158 {sf.|subfc.} %3,%2,%1
1159 #"
1160 [(set_attr "type" "compare")
1161 (set_attr "length" "4,8")])
1163 (define_insn ""
1164 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1165 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1166 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1167 (const_int 0)))
1168 (clobber (match_scratch:SI 3 "=r,r"))]
1169 "TARGET_POWERPC && ! TARGET_POWERPC64"
1170 "@
1171 subf. %3,%2,%1
1172 #"
1173 [(set_attr "type" "fast_compare")
1174 (set_attr "length" "4,8")])
1176 (define_split
1177 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1178 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1179 (match_operand:SI 2 "gpc_reg_operand" ""))
1180 (const_int 0)))
1181 (clobber (match_scratch:SI 3 ""))]
1182 "! TARGET_POWERPC64 && reload_completed"
1183 [(set (match_dup 3)
1184 (minus:SI (match_dup 1)
1185 (match_dup 2)))
1186 (set (match_dup 0)
1187 (compare:CC (match_dup 3)
1188 (const_int 0)))]
1189 "")
1191 (define_insn ""
1192 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1193 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1194 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1195 (const_int 0)))
1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1197 (minus:SI (match_dup 1) (match_dup 2)))]
1198 "! TARGET_POWERPC"
1199 "@
1200 {sf.|subfc.} %0,%2,%1
1201 #"
1202 [(set_attr "type" "compare")
1203 (set_attr "length" "4,8")])
1205 (define_insn ""
1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1207 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1208 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1209 (const_int 0)))
1210 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1211 (minus:SI (match_dup 1)
1212 (match_dup 2)))]
1213 "TARGET_POWERPC && ! TARGET_POWERPC64"
1214 "@
1215 subf. %0,%2,%1
1216 #"
1217 [(set_attr "type" "fast_compare")
1218 (set_attr "length" "4,8")])
1220 (define_split
1221 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1222 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1223 (match_operand:SI 2 "gpc_reg_operand" ""))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "")
1226 (minus:SI (match_dup 1)
1227 (match_dup 2)))]
1228 "! TARGET_POWERPC64 && reload_completed"
1229 [(set (match_dup 0)
1230 (minus:SI (match_dup 1)
1231 (match_dup 2)))
1232 (set (match_dup 3)
1233 (compare:CC (match_dup 0)
1234 (const_int 0)))]
1235 "")
1237 (define_expand "subsi3"
1238 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1239 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1240 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1241 ""
1242 "
1243 {
1244 if (GET_CODE (operands[2]) == CONST_INT)
1245 {
1246 emit_insn (gen_addsi3 (operands[0], operands[1],
1247 negate_rtx (SImode, operands[2])));
1248 DONE;
1249 }
1250 }")
1252 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1253 ;; instruction and some auxiliary computations. Then we just have a single
1254 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1255 ;; combine.
1257 (define_expand "sminsi3"
1258 [(set (match_dup 3)
1259 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1260 (match_operand:SI 2 "reg_or_short_operand" ""))
1261 (const_int 0)
1262 (minus:SI (match_dup 2) (match_dup 1))))
1263 (set (match_operand:SI 0 "gpc_reg_operand" "")
1264 (minus:SI (match_dup 2) (match_dup 3)))]
1265 "TARGET_POWER || TARGET_ISEL"
1266 "
1267 {
1268 if (TARGET_ISEL)
1269 {
1270 operands[2] = force_reg (SImode, operands[2]);
1271 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1272 DONE;
1273 }
1275 operands[3] = gen_reg_rtx (SImode);
1276 }")
1278 (define_split
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1280 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1281 (match_operand:SI 2 "reg_or_short_operand" "")))
1282 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1283 "TARGET_POWER"
1284 [(set (match_dup 3)
1285 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1286 (const_int 0)
1287 (minus:SI (match_dup 2) (match_dup 1))))
1288 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1289 "")
1291 (define_expand "smaxsi3"
1292 [(set (match_dup 3)
1293 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1294 (match_operand:SI 2 "reg_or_short_operand" ""))
1295 (const_int 0)
1296 (minus:SI (match_dup 2) (match_dup 1))))
1297 (set (match_operand:SI 0 "gpc_reg_operand" "")
1298 (plus:SI (match_dup 3) (match_dup 1)))]
1299 "TARGET_POWER || TARGET_ISEL"
1300 "
1301 {
1302 if (TARGET_ISEL)
1303 {
1304 operands[2] = force_reg (SImode, operands[2]);
1305 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1306 DONE;
1307 }
1308 operands[3] = gen_reg_rtx (SImode);
1309 }")
1311 (define_split
1312 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1313 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1314 (match_operand:SI 2 "reg_or_short_operand" "")))
1315 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1316 "TARGET_POWER"
1317 [(set (match_dup 3)
1318 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1319 (const_int 0)
1320 (minus:SI (match_dup 2) (match_dup 1))))
1321 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1322 "")
1324 (define_expand "uminsi3"
1325 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1326 (match_dup 5)))
1327 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1328 (match_dup 5)))
1329 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1330 (const_int 0)
1331 (minus:SI (match_dup 4) (match_dup 3))))
1332 (set (match_operand:SI 0 "gpc_reg_operand" "")
1333 (minus:SI (match_dup 2) (match_dup 3)))]
1334 "TARGET_POWER || TARGET_ISEL"
1335 "
1336 {
1337 if (TARGET_ISEL)
1338 {
1339 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1340 DONE;
1341 }
1342 operands[3] = gen_reg_rtx (SImode);
1343 operands[4] = gen_reg_rtx (SImode);
1344 operands[5] = GEN_INT (-2147483647 - 1);
1345 }")
1347 (define_expand "umaxsi3"
1348 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1349 (match_dup 5)))
1350 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1351 (match_dup 5)))
1352 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1353 (const_int 0)
1354 (minus:SI (match_dup 4) (match_dup 3))))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "")
1356 (plus:SI (match_dup 3) (match_dup 1)))]
1357 "TARGET_POWER || TARGET_ISEL"
1358 "
1359 {
1360 if (TARGET_ISEL)
1361 {
1362 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1363 DONE;
1364 }
1365 operands[3] = gen_reg_rtx (SImode);
1366 operands[4] = gen_reg_rtx (SImode);
1367 operands[5] = GEN_INT (-2147483647 - 1);
1368 }")
1370 (define_insn ""
1371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1372 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1373 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1374 (const_int 0)
1375 (minus:SI (match_dup 2) (match_dup 1))))]
1376 "TARGET_POWER"
1377 "doz%I2 %0,%1,%2")
1379 (define_insn ""
1380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1381 (compare:CC
1382 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1383 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1384 (const_int 0)
1385 (minus:SI (match_dup 2) (match_dup 1)))
1386 (const_int 0)))
1387 (clobber (match_scratch:SI 3 "=r,r"))]
1388 "TARGET_POWER"
1389 "@
1390 doz%I2. %3,%1,%2
1391 #"
1392 [(set_attr "type" "delayed_compare")
1393 (set_attr "length" "4,8")])
1395 (define_split
1396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1397 (compare:CC
1398 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1399 (match_operand:SI 2 "reg_or_short_operand" ""))
1400 (const_int 0)
1401 (minus:SI (match_dup 2) (match_dup 1)))
1402 (const_int 0)))
1403 (clobber (match_scratch:SI 3 ""))]
1404 "TARGET_POWER && reload_completed"
1405 [(set (match_dup 3)
1406 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1407 (const_int 0)
1408 (minus:SI (match_dup 2) (match_dup 1))))
1409 (set (match_dup 0)
1410 (compare:CC (match_dup 3)
1411 (const_int 0)))]
1412 "")
1414 (define_insn ""
1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1416 (compare:CC
1417 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1418 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1419 (const_int 0)
1420 (minus:SI (match_dup 2) (match_dup 1)))
1421 (const_int 0)))
1422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1423 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1424 (const_int 0)
1425 (minus:SI (match_dup 2) (match_dup 1))))]
1426 "TARGET_POWER"
1427 "@
1428 doz%I2. %0,%1,%2
1429 #"
1430 [(set_attr "type" "delayed_compare")
1431 (set_attr "length" "4,8")])
1433 (define_split
1434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1435 (compare:CC
1436 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1437 (match_operand:SI 2 "reg_or_short_operand" ""))
1438 (const_int 0)
1439 (minus:SI (match_dup 2) (match_dup 1)))
1440 (const_int 0)))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "")
1442 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1443 (const_int 0)
1444 (minus:SI (match_dup 2) (match_dup 1))))]
1445 "TARGET_POWER && reload_completed"
1446 [(set (match_dup 0)
1447 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1448 (const_int 0)
1449 (minus:SI (match_dup 2) (match_dup 1))))
1450 (set (match_dup 3)
1451 (compare:CC (match_dup 0)
1452 (const_int 0)))]
1453 "")
1455 ;; We don't need abs with condition code because such comparisons should
1456 ;; never be done.
1457 (define_expand "abssi2"
1458 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1459 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1460 ""
1461 "
1462 {
1463 if (TARGET_ISEL)
1464 {
1465 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1466 DONE;
1467 }
1468 else if (! TARGET_POWER)
1469 {
1470 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1471 DONE;
1472 }
1473 }")
1475 (define_insn "*abssi2_power"
1476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1477 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1478 "TARGET_POWER"
1479 "abs %0,%1")
1481 (define_insn_and_split "abssi2_isel"
1482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1483 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1484 (clobber (match_scratch:SI 2 "=b"))
1485 (clobber (match_scratch:CC 3 "=y"))]
1486 "TARGET_ISEL"
1487 "#"
1488 "&& reload_completed"
1489 [(set (match_dup 2) (neg:SI (match_dup 1)))
1490 (set (match_dup 3)
1491 (compare:CC (match_dup 1)
1492 (const_int 0)))
1493 (set (match_dup 0)
1494 (if_then_else:SI (ge (match_dup 3)
1495 (const_int 0))
1496 (match_dup 1)
1497 (match_dup 2)))]
1498 "")
1500 (define_insn_and_split "abssi2_nopower"
1501 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1502 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1503 (clobber (match_scratch:SI 2 "=&r,&r"))]
1504 "! TARGET_POWER && ! TARGET_ISEL"
1505 "#"
1506 "&& reload_completed"
1507 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1508 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1509 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1510 "")
1512 (define_insn "*nabs_power"
1513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1514 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1515 "TARGET_POWER"
1516 "nabs %0,%1")
1518 (define_insn_and_split "*nabs_nopower"
1519 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1520 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1521 (clobber (match_scratch:SI 2 "=&r,&r"))]
1522 "! TARGET_POWER"
1523 "#"
1524 "&& reload_completed"
1525 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1526 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1527 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1528 "")
1530 (define_insn "negsi2"
1531 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1532 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1533 ""
1534 "neg %0,%1")
1536 (define_insn ""
1537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1538 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1539 (const_int 0)))
1540 (clobber (match_scratch:SI 2 "=r,r"))]
1541 "! TARGET_POWERPC64"
1542 "@
1543 neg. %2,%1
1544 #"
1545 [(set_attr "type" "fast_compare")
1546 (set_attr "length" "4,8")])
1548 (define_split
1549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1550 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1551 (const_int 0)))
1552 (clobber (match_scratch:SI 2 ""))]
1553 "! TARGET_POWERPC64 && reload_completed"
1554 [(set (match_dup 2)
1555 (neg:SI (match_dup 1)))
1556 (set (match_dup 0)
1557 (compare:CC (match_dup 2)
1558 (const_int 0)))]
1559 "")
1561 (define_insn ""
1562 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1563 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1564 (const_int 0)))
1565 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1566 (neg:SI (match_dup 1)))]
1567 "! TARGET_POWERPC64"
1568 "@
1569 neg. %0,%1
1570 #"
1571 [(set_attr "type" "fast_compare")
1572 (set_attr "length" "4,8")])
1574 (define_split
1575 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1576 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1577 (const_int 0)))
1578 (set (match_operand:SI 0 "gpc_reg_operand" "")
1579 (neg:SI (match_dup 1)))]
1580 "! TARGET_POWERPC64 && reload_completed"
1581 [(set (match_dup 0)
1582 (neg:SI (match_dup 1)))
1583 (set (match_dup 2)
1584 (compare:CC (match_dup 0)
1585 (const_int 0)))]
1586 "")
1588 (define_insn "clzsi2"
1589 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1590 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1591 ""
1592 "{cntlz|cntlzw} %0,%1")
1594 (define_expand "ctzsi2"
1595 [(set (match_dup 2)
1596 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1597 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1598 (match_dup 2)))
1599 (clobber (scratch:CC))])
1600 (set (match_dup 4) (clz:SI (match_dup 3)))
1601 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1602 (minus:SI (const_int 31) (match_dup 4)))]
1603 ""
1604 {
1605 operands[2] = gen_reg_rtx (SImode);
1606 operands[3] = gen_reg_rtx (SImode);
1607 operands[4] = gen_reg_rtx (SImode);
1608 })
1610 (define_expand "ffssi2"
1611 [(set (match_dup 2)
1612 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1613 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1614 (match_dup 2)))
1615 (clobber (scratch:CC))])
1616 (set (match_dup 4) (clz:SI (match_dup 3)))
1617 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1618 (minus:SI (const_int 32) (match_dup 4)))]
1619 ""
1620 {
1621 operands[2] = gen_reg_rtx (SImode);
1622 operands[3] = gen_reg_rtx (SImode);
1623 operands[4] = gen_reg_rtx (SImode);
1624 })
1626 (define_expand "mulsi3"
1627 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1628 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1629 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1630 ""
1631 "
1632 {
1633 if (TARGET_POWER)
1634 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1635 else
1636 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1637 DONE;
1638 }")
1640 (define_insn "mulsi3_mq"
1641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1642 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1643 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1644 (clobber (match_scratch:SI 3 "=q,q"))]
1645 "TARGET_POWER"
1646 "@
1647 {muls|mullw} %0,%1,%2
1648 {muli|mulli} %0,%1,%2"
1649 [(set (attr "type")
1650 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1651 (const_string "imul3")
1652 (match_operand:SI 2 "short_cint_operand" "")
1653 (const_string "imul2")]
1654 (const_string "imul")))])
1656 (define_insn "mulsi3_no_mq"
1657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1658 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1659 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1660 "! TARGET_POWER"
1661 "@
1662 {muls|mullw} %0,%1,%2
1663 {muli|mulli} %0,%1,%2"
1664 [(set (attr "type")
1665 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1666 (const_string "imul3")
1667 (match_operand:SI 2 "short_cint_operand" "")
1668 (const_string "imul2")]
1669 (const_string "imul")))])
1671 (define_insn ""
1672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1673 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1674 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1675 (const_int 0)))
1676 (clobber (match_scratch:SI 3 "=r,r"))
1677 (clobber (match_scratch:SI 4 "=q,q"))]
1678 "TARGET_POWER"
1679 "@
1680 {muls.|mullw.} %3,%1,%2
1681 #"
1682 [(set_attr "type" "delayed_compare")
1683 (set_attr "length" "4,8")])
1685 (define_split
1686 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1687 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1688 (match_operand:SI 2 "gpc_reg_operand" ""))
1689 (const_int 0)))
1690 (clobber (match_scratch:SI 3 ""))
1691 (clobber (match_scratch:SI 4 ""))]
1692 "TARGET_POWER && reload_completed"
1693 [(parallel [(set (match_dup 3)
1694 (mult:SI (match_dup 1) (match_dup 2)))
1695 (clobber (match_dup 4))])
1696 (set (match_dup 0)
1697 (compare:CC (match_dup 3)
1698 (const_int 0)))]
1699 "")
1701 (define_insn ""
1702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1703 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1704 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1705 (const_int 0)))
1706 (clobber (match_scratch:SI 3 "=r,r"))]
1707 "! TARGET_POWER"
1708 "@
1709 {muls.|mullw.} %3,%1,%2
1710 #"
1711 [(set_attr "type" "delayed_compare")
1712 (set_attr "length" "4,8")])
1714 (define_split
1715 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1716 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1717 (match_operand:SI 2 "gpc_reg_operand" ""))
1718 (const_int 0)))
1719 (clobber (match_scratch:SI 3 ""))]
1720 "! TARGET_POWER && reload_completed"
1721 [(set (match_dup 3)
1722 (mult:SI (match_dup 1) (match_dup 2)))
1723 (set (match_dup 0)
1724 (compare:CC (match_dup 3)
1725 (const_int 0)))]
1726 "")
1728 (define_insn ""
1729 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1730 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1731 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1732 (const_int 0)))
1733 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1734 (mult:SI (match_dup 1) (match_dup 2)))
1735 (clobber (match_scratch:SI 4 "=q,q"))]
1736 "TARGET_POWER"
1737 "@
1738 {muls.|mullw.} %0,%1,%2
1739 #"
1740 [(set_attr "type" "delayed_compare")
1741 (set_attr "length" "4,8")])
1743 (define_split
1744 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1745 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1746 (match_operand:SI 2 "gpc_reg_operand" ""))
1747 (const_int 0)))
1748 (set (match_operand:SI 0 "gpc_reg_operand" "")
1749 (mult:SI (match_dup 1) (match_dup 2)))
1750 (clobber (match_scratch:SI 4 ""))]
1751 "TARGET_POWER && reload_completed"
1752 [(parallel [(set (match_dup 0)
1753 (mult:SI (match_dup 1) (match_dup 2)))
1754 (clobber (match_dup 4))])
1755 (set (match_dup 3)
1756 (compare:CC (match_dup 0)
1757 (const_int 0)))]
1758 "")
1760 (define_insn ""
1761 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1762 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1763 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1764 (const_int 0)))
1765 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1766 (mult:SI (match_dup 1) (match_dup 2)))]
1767 "! TARGET_POWER"
1768 "@
1769 {muls.|mullw.} %0,%1,%2
1770 #"
1771 [(set_attr "type" "delayed_compare")
1772 (set_attr "length" "4,8")])
1774 (define_split
1775 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1776 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1777 (match_operand:SI 2 "gpc_reg_operand" ""))
1778 (const_int 0)))
1779 (set (match_operand:SI 0 "gpc_reg_operand" "")
1780 (mult:SI (match_dup 1) (match_dup 2)))]
1781 "! TARGET_POWER && reload_completed"
1782 [(set (match_dup 0)
1783 (mult:SI (match_dup 1) (match_dup 2)))
1784 (set (match_dup 3)
1785 (compare:CC (match_dup 0)
1786 (const_int 0)))]
1787 "")
1789 ;; Operand 1 is divided by operand 2; quotient goes to operand
1790 ;; 0 and remainder to operand 3.
1791 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1793 (define_expand "divmodsi4"
1794 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1795 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1796 (match_operand:SI 2 "gpc_reg_operand" "")))
1797 (set (match_operand:SI 3 "register_operand" "")
1798 (mod:SI (match_dup 1) (match_dup 2)))])]
1799 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1800 "
1801 {
1802 if (! TARGET_POWER && ! TARGET_POWERPC)
1803 {
1804 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1805 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1806 emit_insn (gen_divss_call ());
1807 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1808 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1809 DONE;
1810 }
1811 }")
1813 (define_insn "*divmodsi4_internal"
1814 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1815 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1816 (match_operand:SI 2 "gpc_reg_operand" "r")))
1817 (set (match_operand:SI 3 "register_operand" "=q")
1818 (mod:SI (match_dup 1) (match_dup 2)))]
1819 "TARGET_POWER"
1820 "divs %0,%1,%2"
1821 [(set_attr "type" "idiv")])
1823 (define_expand "udivsi3"
1824 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1825 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1826 (match_operand:SI 2 "gpc_reg_operand" "")))]
1827 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1828 "
1829 {
1830 if (! TARGET_POWER && ! TARGET_POWERPC)
1831 {
1832 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1833 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1834 emit_insn (gen_quous_call ());
1835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1836 DONE;
1837 }
1838 else if (TARGET_POWER)
1839 {
1840 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1841 DONE;
1842 }
1843 }")
1845 (define_insn "udivsi3_mq"
1846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1847 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1848 (match_operand:SI 2 "gpc_reg_operand" "r")))
1849 (clobber (match_scratch:SI 3 "=q"))]
1850 "TARGET_POWERPC && TARGET_POWER"
1851 "divwu %0,%1,%2"
1852 [(set_attr "type" "idiv")])
1854 (define_insn "*udivsi3_no_mq"
1855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1856 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1857 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1858 "TARGET_POWERPC && ! TARGET_POWER"
1859 "divwu %0,%1,%2"
1860 [(set_attr "type" "idiv")])
1862 ;; For powers of two we can do srai/aze for divide and then adjust for
1863 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1864 ;; used; for PowerPC, force operands into register and do a normal divide;
1865 ;; for AIX common-mode, use quoss call on register operands.
1866 (define_expand "divsi3"
1867 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1868 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1869 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1870 ""
1871 "
1872 {
1873 if (GET_CODE (operands[2]) == CONST_INT
1874 && INTVAL (operands[2]) > 0
1875 && exact_log2 (INTVAL (operands[2])) >= 0)
1876 ;
1877 else if (TARGET_POWERPC)
1878 {
1879 operands[2] = force_reg (SImode, operands[2]);
1880 if (TARGET_POWER)
1881 {
1882 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1883 DONE;
1884 }
1885 }
1886 else if (TARGET_POWER)
1887 FAIL;
1888 else
1889 {
1890 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1891 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1892 emit_insn (gen_quoss_call ());
1893 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1894 DONE;
1895 }
1896 }")
1898 (define_insn "divsi3_mq"
1899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1900 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1901 (match_operand:SI 2 "gpc_reg_operand" "r")))
1902 (clobber (match_scratch:SI 3 "=q"))]
1903 "TARGET_POWERPC && TARGET_POWER"
1904 "divw %0,%1,%2"
1905 [(set_attr "type" "idiv")])
1907 (define_insn "*divsi3_no_mq"
1908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1909 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1910 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1911 "TARGET_POWERPC && ! TARGET_POWER"
1912 "divw %0,%1,%2"
1913 [(set_attr "type" "idiv")])
1915 (define_expand "modsi3"
1916 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1917 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1918 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1919 ""
1920 "
1921 {
1922 int i;
1923 rtx temp1;
1924 rtx temp2;
1926 if (GET_CODE (operands[2]) != CONST_INT
1927 || INTVAL (operands[2]) <= 0
1928 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1929 FAIL;
1931 temp1 = gen_reg_rtx (SImode);
1932 temp2 = gen_reg_rtx (SImode);
1934 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1935 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1936 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1937 DONE;
1938 }")
1940 (define_insn ""
1941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1942 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1943 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1944 ""
1945 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1946 [(set_attr "length" "8")])
1948 (define_insn ""
1949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1950 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1951 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1952 (const_int 0)))
1953 (clobber (match_scratch:SI 3 "=r,r"))]
1954 ""
1955 "@
1956 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1957 #"
1958 [(set_attr "type" "compare")
1959 (set_attr "length" "8,12")])
1961 (define_split
1962 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1963 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1964 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1965 (const_int 0)))
1966 (clobber (match_scratch:SI 3 ""))]
1967 "reload_completed"
1968 [(set (match_dup 3)
1969 (div:SI (match_dup 1) (match_dup 2)))
1970 (set (match_dup 0)
1971 (compare:CC (match_dup 3)
1972 (const_int 0)))]
1973 "")
1975 (define_insn ""
1976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1977 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1979 (const_int 0)))
1980 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1981 (div:SI (match_dup 1) (match_dup 2)))]
1982 ""
1983 "@
1984 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
1985 #"
1986 [(set_attr "type" "compare")
1987 (set_attr "length" "8,12")])
1989 (define_split
1990 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1991 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1992 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1993 (const_int 0)))
1994 (set (match_operand:SI 0 "gpc_reg_operand" "")
1995 (div:SI (match_dup 1) (match_dup 2)))]
1996 "reload_completed"
1997 [(set (match_dup 0)
1998 (div:SI (match_dup 1) (match_dup 2)))
1999 (set (match_dup 3)
2000 (compare:CC (match_dup 0)
2001 (const_int 0)))]
2002 "")
2004 (define_insn ""
2005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2006 (udiv:SI
2007 (plus:DI (ashift:DI
2008 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2009 (const_int 32))
2010 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2011 (match_operand:SI 3 "gpc_reg_operand" "r")))
2012 (set (match_operand:SI 2 "register_operand" "=*q")
2013 (umod:SI
2014 (plus:DI (ashift:DI
2015 (zero_extend:DI (match_dup 1)) (const_int 32))
2016 (zero_extend:DI (match_dup 4)))
2017 (match_dup 3)))]
2018 "TARGET_POWER"
2019 "div %0,%1,%3"
2020 [(set_attr "type" "idiv")])
2022 ;; To do unsigned divide we handle the cases of the divisor looking like a
2023 ;; negative number. If it is a constant that is less than 2**31, we don't
2024 ;; have to worry about the branches. So make a few subroutines here.
2025 ;;
2026 ;; First comes the normal case.
2027 (define_expand "udivmodsi4_normal"
2028 [(set (match_dup 4) (const_int 0))
2029 (parallel [(set (match_operand:SI 0 "" "")
2030 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2031 (const_int 32))
2032 (zero_extend:DI (match_operand:SI 1 "" "")))
2033 (match_operand:SI 2 "" "")))
2034 (set (match_operand:SI 3 "" "")
2035 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2036 (const_int 32))
2037 (zero_extend:DI (match_dup 1)))
2038 (match_dup 2)))])]
2039 "TARGET_POWER"
2040 "
2041 { operands[4] = gen_reg_rtx (SImode); }")
2043 ;; This handles the branches.
2044 (define_expand "udivmodsi4_tests"
2045 [(set (match_operand:SI 0 "" "") (const_int 0))
2046 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2047 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2048 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2049 (label_ref (match_operand:SI 4 "" "")) (pc)))
2050 (set (match_dup 0) (const_int 1))
2051 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2052 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2053 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2054 (label_ref (match_dup 4)) (pc)))]
2055 "TARGET_POWER"
2056 "
2057 { operands[5] = gen_reg_rtx (CCUNSmode);
2058 operands[6] = gen_reg_rtx (CCmode);
2059 }")
2061 (define_expand "udivmodsi4"
2062 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2063 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2064 (match_operand:SI 2 "reg_or_cint_operand" "")))
2065 (set (match_operand:SI 3 "gpc_reg_operand" "")
2066 (umod:SI (match_dup 1) (match_dup 2)))])]
2067 ""
2068 "
2069 {
2070 rtx label = 0;
2072 if (! TARGET_POWER)
2073 {
2074 if (! TARGET_POWERPC)
2075 {
2076 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2077 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2078 emit_insn (gen_divus_call ());
2079 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2080 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2081 DONE;
2082 }
2083 else
2084 FAIL;
2085 }
2087 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2088 {
2089 operands[2] = force_reg (SImode, operands[2]);
2090 label = gen_label_rtx ();
2091 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2092 operands[3], label));
2093 }
2094 else
2095 operands[2] = force_reg (SImode, operands[2]);
2097 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2098 operands[3]));
2099 if (label)
2100 emit_label (label);
2102 DONE;
2103 }")
2105 ;; AIX architecture-independent common-mode multiply (DImode),
2106 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2107 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2108 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2109 ;; assumed unused if generating common-mode, so ignore.
2110 (define_insn "mulh_call"
2111 [(set (reg:SI 3)
2112 (truncate:SI
2113 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2114 (sign_extend:DI (reg:SI 4)))
2115 (const_int 32))))
2116 (clobber (match_scratch:SI 0 "=l"))]
2117 "! TARGET_POWER && ! TARGET_POWERPC"
2118 "bla __mulh"
2119 [(set_attr "type" "imul")])
2121 (define_insn "mull_call"
2122 [(set (reg:DI 3)
2123 (mult:DI (sign_extend:DI (reg:SI 3))
2124 (sign_extend:DI (reg:SI 4))))
2125 (clobber (match_scratch:SI 0 "=l"))
2126 (clobber (reg:SI 0))]
2127 "! TARGET_POWER && ! TARGET_POWERPC"
2128 "bla __mull"
2129 [(set_attr "type" "imul")])
2131 (define_insn "divss_call"
2132 [(set (reg:SI 3)
2133 (div:SI (reg:SI 3) (reg:SI 4)))
2134 (set (reg:SI 4)
2135 (mod:SI (reg:SI 3) (reg:SI 4)))
2136 (clobber (match_scratch:SI 0 "=l"))
2137 (clobber (reg:SI 0))]
2138 "! TARGET_POWER && ! TARGET_POWERPC"
2139 "bla __divss"
2140 [(set_attr "type" "idiv")])
2142 (define_insn "divus_call"
2143 [(set (reg:SI 3)
2144 (udiv:SI (reg:SI 3) (reg:SI 4)))
2145 (set (reg:SI 4)
2146 (umod:SI (reg:SI 3) (reg:SI 4)))
2147 (clobber (match_scratch:SI 0 "=l"))
2148 (clobber (reg:SI 0))
2149 (clobber (match_scratch:CC 1 "=x"))
2150 (clobber (reg:CC 69))]
2151 "! TARGET_POWER && ! TARGET_POWERPC"
2152 "bla __divus"
2153 [(set_attr "type" "idiv")])
2155 (define_insn "quoss_call"
2156 [(set (reg:SI 3)
2157 (div:SI (reg:SI 3) (reg:SI 4)))
2158 (clobber (match_scratch:SI 0 "=l"))]
2159 "! TARGET_POWER && ! TARGET_POWERPC"
2160 "bla __quoss"
2161 [(set_attr "type" "idiv")])
2163 (define_insn "quous_call"
2164 [(set (reg:SI 3)
2165 (udiv:SI (reg:SI 3) (reg:SI 4)))
2166 (clobber (match_scratch:SI 0 "=l"))
2167 (clobber (reg:SI 0))
2168 (clobber (match_scratch:CC 1 "=x"))
2169 (clobber (reg:CC 69))]
2170 "! TARGET_POWER && ! TARGET_POWERPC"
2171 "bla __quous"
2172 [(set_attr "type" "idiv")])
2173 \f
2174 ;; Logical instructions
2175 ;; The logical instructions are mostly combined by using match_operator,
2176 ;; but the plain AND insns are somewhat different because there is no
2177 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2178 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2180 (define_insn "andsi3"
2181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2182 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2183 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2184 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2185 ""
2186 "@
2187 and %0,%1,%2
2188 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2189 {andil.|andi.} %0,%1,%b2
2190 {andiu.|andis.} %0,%1,%u2")
2192 ;; Note to set cr's other than cr0 we do the and immediate and then
2193 ;; the test again -- this avoids a mfcr which on the higher end
2194 ;; machines causes an execution serialization
2196 (define_insn "*andsi3_internal2"
2197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2198 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2199 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2200 (const_int 0)))
2201 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2202 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2203 "! TARGET_POWERPC64"
2204 "@
2205 and. %3,%1,%2
2206 {andil.|andi.} %3,%1,%b2
2207 {andiu.|andis.} %3,%1,%u2
2208 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2209 #
2210 #
2211 #
2212 #"
2213 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2214 (set_attr "length" "4,4,4,4,8,8,8,8")])
2216 (define_insn "*andsi3_internal3"
2217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2218 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2219 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2220 (const_int 0)))
2221 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2222 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2223 "TARGET_POWERPC64"
2224 "@
2225 #
2226 {andil.|andi.} %3,%1,%b2
2227 {andiu.|andis.} %3,%1,%u2
2228 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2229 #
2230 #
2231 #
2232 #"
2233 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2234 (set_attr "length" "8,4,4,4,8,8,8,8")])
2236 (define_split
2237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2238 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2239 (match_operand:SI 2 "and_operand" ""))
2240 (const_int 0)))
2241 (clobber (match_scratch:SI 3 ""))
2242 (clobber (match_scratch:CC 4 ""))]
2243 "reload_completed"
2244 [(parallel [(set (match_dup 3)
2245 (and:SI (match_dup 1)
2246 (match_dup 2)))
2247 (clobber (match_dup 4))])
2248 (set (match_dup 0)
2249 (compare:CC (match_dup 3)
2250 (const_int 0)))]
2251 "")
2253 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2254 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2256 (define_split
2257 [(set (match_operand:CC 0 "cc_reg_operand" "")
2258 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2259 (match_operand:SI 2 "gpc_reg_operand" ""))
2260 (const_int 0)))
2261 (clobber (match_scratch:SI 3 ""))
2262 (clobber (match_scratch:CC 4 ""))]
2263 "TARGET_POWERPC64 && reload_completed"
2264 [(parallel [(set (match_dup 3)
2265 (and:SI (match_dup 1)
2266 (match_dup 2)))
2267 (clobber (match_dup 4))])
2268 (set (match_dup 0)
2269 (compare:CC (match_dup 3)
2270 (const_int 0)))]
2271 "")
2273 (define_insn "*andsi3_internal4"
2274 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2275 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2276 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2277 (const_int 0)))
2278 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2279 (and:SI (match_dup 1)
2280 (match_dup 2)))
2281 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2282 "! TARGET_POWERPC64"
2283 "@
2284 and. %0,%1,%2
2285 {andil.|andi.} %0,%1,%b2
2286 {andiu.|andis.} %0,%1,%u2
2287 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2288 #
2289 #
2290 #
2291 #"
2292 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2293 (set_attr "length" "4,4,4,4,8,8,8,8")])
2295 (define_insn "*andsi3_internal5"
2296 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2297 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2298 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2299 (const_int 0)))
2300 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2301 (and:SI (match_dup 1)
2302 (match_dup 2)))
2303 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2304 "TARGET_POWERPC64"
2305 "@
2306 #
2307 {andil.|andi.} %0,%1,%b2
2308 {andiu.|andis.} %0,%1,%u2
2309 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2310 #
2311 #
2312 #
2313 #"
2314 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2315 (set_attr "length" "8,4,4,4,8,8,8,8")])
2317 (define_split
2318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2319 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2320 (match_operand:SI 2 "and_operand" ""))
2321 (const_int 0)))
2322 (set (match_operand:SI 0 "gpc_reg_operand" "")
2323 (and:SI (match_dup 1)
2324 (match_dup 2)))
2325 (clobber (match_scratch:CC 4 ""))]
2326 "reload_completed"
2327 [(parallel [(set (match_dup 0)
2328 (and:SI (match_dup 1)
2329 (match_dup 2)))
2330 (clobber (match_dup 4))])
2331 (set (match_dup 3)
2332 (compare:CC (match_dup 0)
2333 (const_int 0)))]
2334 "")
2336 (define_split
2337 [(set (match_operand:CC 3 "cc_reg_operand" "")
2338 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2339 (match_operand:SI 2 "gpc_reg_operand" ""))
2340 (const_int 0)))
2341 (set (match_operand:SI 0 "gpc_reg_operand" "")
2342 (and:SI (match_dup 1)
2343 (match_dup 2)))
2344 (clobber (match_scratch:CC 4 ""))]
2345 "TARGET_POWERPC64 && reload_completed"
2346 [(parallel [(set (match_dup 0)
2347 (and:SI (match_dup 1)
2348 (match_dup 2)))
2349 (clobber (match_dup 4))])
2350 (set (match_dup 3)
2351 (compare:CC (match_dup 0)
2352 (const_int 0)))]
2353 "")
2355 ;; Handle the PowerPC64 rlwinm corner case
2357 (define_insn_and_split "*andsi3_internal6"
2358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2359 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2360 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2361 "TARGET_POWERPC64"
2362 "#"
2363 "TARGET_POWERPC64"
2364 [(set (match_dup 0)
2365 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2366 (match_dup 4)))
2367 (set (match_dup 0)
2368 (rotate:SI (match_dup 0) (match_dup 5)))]
2369 "
2370 {
2371 int mb = extract_MB (operands[2]);
2372 int me = extract_ME (operands[2]);
2373 operands[3] = GEN_INT (me + 1);
2374 operands[5] = GEN_INT (32 - (me + 1));
2375 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2376 }"
2377 [(set_attr "length" "8")])
2379 (define_insn_and_split "*andsi3_internal7"
2380 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2381 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2382 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2383 (const_int 0)))
2384 (clobber (match_scratch:SI 3 "=r,r"))]
2385 "TARGET_POWERPC64"
2386 "#"
2387 "TARGET_POWERPC64"
2388 [(parallel [(set (match_dup 2)
2389 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2390 (match_dup 5))
2391 (const_int 0)))
2392 (clobber (match_dup 3))])]
2393 "
2394 {
2395 int mb = extract_MB (operands[1]);
2396 int me = extract_ME (operands[1]);
2397 operands[4] = GEN_INT (me + 1);
2398 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2399 }"
2400 [(set_attr "type" "delayed_compare,compare")
2401 (set_attr "length" "4,8")])
2403 (define_insn_and_split "*andsi3_internal8"
2404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2405 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2406 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2407 (const_int 0)))
2408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2409 (and:SI (match_dup 1)
2410 (match_dup 2)))]
2411 "TARGET_POWERPC64"
2412 "#"
2413 "TARGET_POWERPC64"
2414 [(parallel [(set (match_dup 3)
2415 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2416 (match_dup 5))
2417 (const_int 0)))
2418 (set (match_dup 0)
2419 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2420 (match_dup 5)))])
2421 (set (match_dup 0)
2422 (rotate:SI (match_dup 0) (match_dup 6)))]
2423 "
2424 {
2425 int mb = extract_MB (operands[2]);
2426 int me = extract_ME (operands[2]);
2427 operands[4] = GEN_INT (me + 1);
2428 operands[6] = GEN_INT (32 - (me + 1));
2429 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2430 }"
2431 [(set_attr "type" "delayed_compare,compare")
2432 (set_attr "length" "8,12")])
2434 (define_expand "iorsi3"
2435 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2436 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2437 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2438 ""
2439 "
2440 {
2441 if (GET_CODE (operands[2]) == CONST_INT
2442 && ! logical_operand (operands[2], SImode))
2443 {
2444 HOST_WIDE_INT value = INTVAL (operands[2]);
2445 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2446 ? operands[0] : gen_reg_rtx (SImode));
2448 emit_insn (gen_iorsi3 (tmp, operands[1],
2449 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2450 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2451 DONE;
2452 }
2453 }")
2455 (define_expand "xorsi3"
2456 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2457 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2458 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2459 ""
2460 "
2461 {
2462 if (GET_CODE (operands[2]) == CONST_INT
2463 && ! logical_operand (operands[2], SImode))
2464 {
2465 HOST_WIDE_INT value = INTVAL (operands[2]);
2466 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2467 ? operands[0] : gen_reg_rtx (SImode));
2469 emit_insn (gen_xorsi3 (tmp, operands[1],
2470 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2471 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2472 DONE;
2473 }
2474 }")
2476 (define_insn "*boolsi3_internal1"
2477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2478 (match_operator:SI 3 "boolean_or_operator"
2479 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2480 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2481 ""
2482 "@
2483 %q3 %0,%1,%2
2484 {%q3il|%q3i} %0,%1,%b2
2485 {%q3iu|%q3is} %0,%1,%u2")
2487 (define_insn "*boolsi3_internal2"
2488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2489 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2490 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2491 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2492 (const_int 0)))
2493 (clobber (match_scratch:SI 3 "=r,r"))]
2494 "! TARGET_POWERPC64"
2495 "@
2496 %q4. %3,%1,%2
2497 #"
2498 [(set_attr "type" "compare")
2499 (set_attr "length" "4,8")])
2501 (define_split
2502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2503 (compare:CC (match_operator:SI 4 "boolean_operator"
2504 [(match_operand:SI 1 "gpc_reg_operand" "")
2505 (match_operand:SI 2 "gpc_reg_operand" "")])
2506 (const_int 0)))
2507 (clobber (match_scratch:SI 3 ""))]
2508 "! TARGET_POWERPC64 && reload_completed"
2509 [(set (match_dup 3) (match_dup 4))
2510 (set (match_dup 0)
2511 (compare:CC (match_dup 3)
2512 (const_int 0)))]
2513 "")
2515 (define_insn "*boolsi3_internal3"
2516 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2517 (compare:CC (match_operator:SI 4 "boolean_operator"
2518 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2519 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2520 (const_int 0)))
2521 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2522 (match_dup 4))]
2523 "! TARGET_POWERPC64"
2524 "@
2525 %q4. %0,%1,%2
2526 #"
2527 [(set_attr "type" "compare")
2528 (set_attr "length" "4,8")])
2530 (define_split
2531 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2532 (compare:CC (match_operator:SI 4 "boolean_operator"
2533 [(match_operand:SI 1 "gpc_reg_operand" "")
2534 (match_operand:SI 2 "gpc_reg_operand" "")])
2535 (const_int 0)))
2536 (set (match_operand:SI 0 "gpc_reg_operand" "")
2537 (match_dup 4))]
2538 "! TARGET_POWERPC64 && reload_completed"
2539 [(set (match_dup 0) (match_dup 4))
2540 (set (match_dup 3)
2541 (compare:CC (match_dup 0)
2542 (const_int 0)))]
2543 "")
2545 ;; Split a logical operation that we can't do in one insn into two insns,
2546 ;; each of which does one 16-bit part. This is used by combine.
2548 (define_split
2549 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2550 (match_operator:SI 3 "boolean_or_operator"
2551 [(match_operand:SI 1 "gpc_reg_operand" "")
2552 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2553 ""
2554 [(set (match_dup 0) (match_dup 4))
2555 (set (match_dup 0) (match_dup 5))]
2556 "
2557 {
2558 rtx i;
2559 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2560 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2561 operands[1], i);
2562 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2563 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2564 operands[0], i);
2565 }")
2567 (define_insn "*boolcsi3_internal1"
2568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2569 (match_operator:SI 3 "boolean_operator"
2570 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2571 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2572 ""
2573 "%q3 %0,%2,%1")
2575 (define_insn "*boolcsi3_internal2"
2576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2577 (compare:CC (match_operator:SI 4 "boolean_operator"
2578 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2579 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2580 (const_int 0)))
2581 (clobber (match_scratch:SI 3 "=r,r"))]
2582 "! TARGET_POWERPC64"
2583 "@
2584 %q4. %3,%2,%1
2585 #"
2586 [(set_attr "type" "compare")
2587 (set_attr "length" "4,8")])
2589 (define_split
2590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2591 (compare:CC (match_operator:SI 4 "boolean_operator"
2592 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2593 (match_operand:SI 2 "gpc_reg_operand" "")])
2594 (const_int 0)))
2595 (clobber (match_scratch:SI 3 ""))]
2596 "! TARGET_POWERPC64 && reload_completed"
2597 [(set (match_dup 3) (match_dup 4))
2598 (set (match_dup 0)
2599 (compare:CC (match_dup 3)
2600 (const_int 0)))]
2601 "")
2603 (define_insn "*boolcsi3_internal3"
2604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2605 (compare:CC (match_operator:SI 4 "boolean_operator"
2606 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2607 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2608 (const_int 0)))
2609 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2610 (match_dup 4))]
2611 "! TARGET_POWERPC64"
2612 "@
2613 %q4. %0,%2,%1
2614 #"
2615 [(set_attr "type" "compare")
2616 (set_attr "length" "4,8")])
2618 (define_split
2619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2620 (compare:CC (match_operator:SI 4 "boolean_operator"
2621 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2622 (match_operand:SI 2 "gpc_reg_operand" "")])
2623 (const_int 0)))
2624 (set (match_operand:SI 0 "gpc_reg_operand" "")
2625 (match_dup 4))]
2626 "! TARGET_POWERPC64 && reload_completed"
2627 [(set (match_dup 0) (match_dup 4))
2628 (set (match_dup 3)
2629 (compare:CC (match_dup 0)
2630 (const_int 0)))]
2631 "")
2633 (define_insn "*boolccsi3_internal1"
2634 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2635 (match_operator:SI 3 "boolean_operator"
2636 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2637 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2638 ""
2639 "%q3 %0,%1,%2")
2641 (define_insn "*boolccsi3_internal2"
2642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2643 (compare:CC (match_operator:SI 4 "boolean_operator"
2644 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2645 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2646 (const_int 0)))
2647 (clobber (match_scratch:SI 3 "=r,r"))]
2648 "! TARGET_POWERPC64"
2649 "@
2650 %q4. %3,%1,%2
2651 #"
2652 [(set_attr "type" "compare")
2653 (set_attr "length" "4,8")])
2655 (define_split
2656 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2657 (compare:CC (match_operator:SI 4 "boolean_operator"
2658 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2659 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2660 (const_int 0)))
2661 (clobber (match_scratch:SI 3 ""))]
2662 "! TARGET_POWERPC64 && reload_completed"
2663 [(set (match_dup 3) (match_dup 4))
2664 (set (match_dup 0)
2665 (compare:CC (match_dup 3)
2666 (const_int 0)))]
2667 "")
2669 (define_insn "*boolccsi3_internal3"
2670 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2671 (compare:CC (match_operator:SI 4 "boolean_operator"
2672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2673 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2674 (const_int 0)))
2675 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2676 (match_dup 4))]
2677 "! TARGET_POWERPC64"
2678 "@
2679 %q4. %0,%1,%2
2680 #"
2681 [(set_attr "type" "compare")
2682 (set_attr "length" "4,8")])
2684 (define_split
2685 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2686 (compare:CC (match_operator:SI 4 "boolean_operator"
2687 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2688 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2689 (const_int 0)))
2690 (set (match_operand:SI 0 "gpc_reg_operand" "")
2691 (match_dup 4))]
2692 "! TARGET_POWERPC64 && reload_completed"
2693 [(set (match_dup 0) (match_dup 4))
2694 (set (match_dup 3)
2695 (compare:CC (match_dup 0)
2696 (const_int 0)))]
2697 "")
2699 ;; maskir insn. We need four forms because things might be in arbitrary
2700 ;; orders. Don't define forms that only set CR fields because these
2701 ;; would modify an input register.
2703 (define_insn "*maskir_internal1"
2704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2705 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2706 (match_operand:SI 1 "gpc_reg_operand" "0"))
2707 (and:SI (match_dup 2)
2708 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2709 "TARGET_POWER"
2710 "maskir %0,%3,%2")
2712 (define_insn "*maskir_internal2"
2713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2714 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2715 (match_operand:SI 1 "gpc_reg_operand" "0"))
2716 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2717 (match_dup 2))))]
2718 "TARGET_POWER"
2719 "maskir %0,%3,%2")
2721 (define_insn "*maskir_internal3"
2722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2723 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2724 (match_operand:SI 3 "gpc_reg_operand" "r"))
2725 (and:SI (not:SI (match_dup 2))
2726 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2727 "TARGET_POWER"
2728 "maskir %0,%3,%2")
2730 (define_insn "*maskir_internal4"
2731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2732 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2733 (match_operand:SI 2 "gpc_reg_operand" "r"))
2734 (and:SI (not:SI (match_dup 2))
2735 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2736 "TARGET_POWER"
2737 "maskir %0,%3,%2")
2739 (define_insn "*maskir_internal5"
2740 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2741 (compare:CC
2742 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2743 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2744 (and:SI (match_dup 2)
2745 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2746 (const_int 0)))
2747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2748 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2749 (and:SI (match_dup 2) (match_dup 3))))]
2750 "TARGET_POWER"
2751 "@
2752 maskir. %0,%3,%2
2753 #"
2754 [(set_attr "type" "compare")
2755 (set_attr "length" "4,8")])
2757 (define_split
2758 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2759 (compare:CC
2760 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2761 (match_operand:SI 1 "gpc_reg_operand" ""))
2762 (and:SI (match_dup 2)
2763 (match_operand:SI 3 "gpc_reg_operand" "")))
2764 (const_int 0)))
2765 (set (match_operand:SI 0 "gpc_reg_operand" "")
2766 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2767 (and:SI (match_dup 2) (match_dup 3))))]
2768 "TARGET_POWER && reload_completed"
2769 [(set (match_dup 0)
2770 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2771 (and:SI (match_dup 2) (match_dup 3))))
2772 (set (match_dup 4)
2773 (compare:CC (match_dup 0)
2774 (const_int 0)))]
2775 "")
2777 (define_insn "*maskir_internal6"
2778 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2779 (compare:CC
2780 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2781 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2782 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2783 (match_dup 2)))
2784 (const_int 0)))
2785 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2786 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2787 (and:SI (match_dup 3) (match_dup 2))))]
2788 "TARGET_POWER"
2789 "@
2790 maskir. %0,%3,%2
2791 #"
2792 [(set_attr "type" "compare")
2793 (set_attr "length" "4,8")])
2795 (define_split
2796 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2797 (compare:CC
2798 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2799 (match_operand:SI 1 "gpc_reg_operand" ""))
2800 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2801 (match_dup 2)))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "")
2804 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2805 (and:SI (match_dup 3) (match_dup 2))))]
2806 "TARGET_POWER && reload_completed"
2807 [(set (match_dup 0)
2808 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2809 (and:SI (match_dup 3) (match_dup 2))))
2810 (set (match_dup 4)
2811 (compare:CC (match_dup 0)
2812 (const_int 0)))]
2813 "")
2815 (define_insn "*maskir_internal7"
2816 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2817 (compare:CC
2818 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2819 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2820 (and:SI (not:SI (match_dup 2))
2821 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2822 (const_int 0)))
2823 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2824 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2825 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2826 "TARGET_POWER"
2827 "@
2828 maskir. %0,%3,%2
2829 #"
2830 [(set_attr "type" "compare")
2831 (set_attr "length" "4,8")])
2833 (define_split
2834 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2835 (compare:CC
2836 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2837 (match_operand:SI 3 "gpc_reg_operand" ""))
2838 (and:SI (not:SI (match_dup 2))
2839 (match_operand:SI 1 "gpc_reg_operand" "")))
2840 (const_int 0)))
2841 (set (match_operand:SI 0 "gpc_reg_operand" "")
2842 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2843 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2844 "TARGET_POWER && reload_completed"
2845 [(set (match_dup 0)
2846 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2847 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2848 (set (match_dup 4)
2849 (compare:CC (match_dup 0)
2850 (const_int 0)))]
2851 "")
2853 (define_insn "*maskir_internal8"
2854 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2855 (compare:CC
2856 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2857 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2858 (and:SI (not:SI (match_dup 2))
2859 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2860 (const_int 0)))
2861 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2862 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2863 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2864 "TARGET_POWER"
2865 "@
2866 maskir. %0,%3,%2
2867 #"
2868 [(set_attr "type" "compare")
2869 (set_attr "length" "4,8")])
2871 (define_split
2872 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2873 (compare:CC
2874 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2875 (match_operand:SI 2 "gpc_reg_operand" ""))
2876 (and:SI (not:SI (match_dup 2))
2877 (match_operand:SI 1 "gpc_reg_operand" "")))
2878 (const_int 0)))
2879 (set (match_operand:SI 0 "gpc_reg_operand" "")
2880 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2881 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2882 "TARGET_POWER && reload_completed"
2883 [(set (match_dup 0)
2884 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2885 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2886 (set (match_dup 4)
2887 (compare:CC (match_dup 0)
2888 (const_int 0)))]
2889 "")
2890 \f
2891 ;; Rotate and shift insns, in all their variants. These support shifts,
2892 ;; field inserts and extracts, and various combinations thereof.
2893 (define_expand "insv"
2894 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2895 (match_operand:SI 1 "const_int_operand" "")
2896 (match_operand:SI 2 "const_int_operand" ""))
2897 (match_operand 3 "gpc_reg_operand" ""))]
2898 ""
2899 "
2900 {
2901 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2902 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2903 compiler if the address of the structure is taken later. */
2904 if (GET_CODE (operands[0]) == SUBREG
2905 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2906 FAIL;
2908 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2909 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2910 else
2911 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2912 DONE;
2913 }")
2915 (define_insn "insvsi"
2916 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2917 (match_operand:SI 1 "const_int_operand" "i")
2918 (match_operand:SI 2 "const_int_operand" "i"))
2919 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2920 ""
2921 "*
2922 {
2923 int start = INTVAL (operands[2]) & 31;
2924 int size = INTVAL (operands[1]) & 31;
2926 operands[4] = GEN_INT (32 - start - size);
2927 operands[1] = GEN_INT (start + size - 1);
2928 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2929 }")
2931 (define_insn "*insvsi_internal1"
2932 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2933 (match_operand:SI 1 "const_int_operand" "i")
2934 (match_operand:SI 2 "const_int_operand" "i"))
2935 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2936 (match_operand:SI 4 "const_int_operand" "i")))]
2937 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2938 "*
2939 {
2940 int shift = INTVAL (operands[4]) & 31;
2941 int start = INTVAL (operands[2]) & 31;
2942 int size = INTVAL (operands[1]) & 31;
2944 operands[4] = GEN_INT (shift - start - size);
2945 operands[1] = GEN_INT (start + size - 1);
2946 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2947 }")
2949 (define_insn "*insvsi_internal2"
2950 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2951 (match_operand:SI 1 "const_int_operand" "i")
2952 (match_operand:SI 2 "const_int_operand" "i"))
2953 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2954 (match_operand:SI 4 "const_int_operand" "i")))]
2955 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2956 "*
2957 {
2958 int shift = INTVAL (operands[4]) & 31;
2959 int start = INTVAL (operands[2]) & 31;
2960 int size = INTVAL (operands[1]) & 31;
2962 operands[4] = GEN_INT (32 - shift - start - size);
2963 operands[1] = GEN_INT (start + size - 1);
2964 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2965 }")
2967 (define_insn "*insvsi_internal3"
2968 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2969 (match_operand:SI 1 "const_int_operand" "i")
2970 (match_operand:SI 2 "const_int_operand" "i"))
2971 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2972 (match_operand:SI 4 "const_int_operand" "i")))]
2973 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2974 "*
2975 {
2976 int shift = INTVAL (operands[4]) & 31;
2977 int start = INTVAL (operands[2]) & 31;
2978 int size = INTVAL (operands[1]) & 31;
2980 operands[4] = GEN_INT (32 - shift - start - size);
2981 operands[1] = GEN_INT (start + size - 1);
2982 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2983 }")
2985 (define_insn "*insvsi_internal4"
2986 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2987 (match_operand:SI 1 "const_int_operand" "i")
2988 (match_operand:SI 2 "const_int_operand" "i"))
2989 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2990 (match_operand:SI 4 "const_int_operand" "i")
2991 (match_operand:SI 5 "const_int_operand" "i")))]
2992 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2993 "*
2994 {
2995 int extract_start = INTVAL (operands[5]) & 31;
2996 int extract_size = INTVAL (operands[4]) & 31;
2997 int insert_start = INTVAL (operands[2]) & 31;
2998 int insert_size = INTVAL (operands[1]) & 31;
3000 /* Align extract field with insert field */
3001 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3002 operands[1] = GEN_INT (insert_start + insert_size - 1);
3003 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3004 }")
3006 (define_insn "insvdi"
3007 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3008 (match_operand:SI 1 "const_int_operand" "i")
3009 (match_operand:SI 2 "const_int_operand" "i"))
3010 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3011 "TARGET_POWERPC64"
3012 "*
3013 {
3014 int start = INTVAL (operands[2]) & 63;
3015 int size = INTVAL (operands[1]) & 63;
3017 operands[1] = GEN_INT (64 - start - size);
3018 return \"rldimi %0,%3,%H1,%H2\";
3019 }")
3021 (define_expand "extzv"
3022 [(set (match_operand 0 "gpc_reg_operand" "")
3023 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "const_int_operand" "")
3025 (match_operand:SI 3 "const_int_operand" "")))]
3026 ""
3027 "
3028 {
3029 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3030 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3031 compiler if the address of the structure is taken later. */
3032 if (GET_CODE (operands[0]) == SUBREG
3033 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3034 FAIL;
3036 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3037 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3038 else
3039 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3040 DONE;
3041 }")
3043 (define_insn "extzvsi"
3044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3045 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3046 (match_operand:SI 2 "const_int_operand" "i")
3047 (match_operand:SI 3 "const_int_operand" "i")))]
3048 ""
3049 "*
3050 {
3051 int start = INTVAL (operands[3]) & 31;
3052 int size = INTVAL (operands[2]) & 31;
3054 if (start + size >= 32)
3055 operands[3] = const0_rtx;
3056 else
3057 operands[3] = GEN_INT (start + size);
3058 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3059 }")
3061 (define_insn "*extzvsi_internal1"
3062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3063 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3064 (match_operand:SI 2 "const_int_operand" "i,i")
3065 (match_operand:SI 3 "const_int_operand" "i,i"))
3066 (const_int 0)))
3067 (clobber (match_scratch:SI 4 "=r,r"))]
3068 ""
3069 "*
3070 {
3071 int start = INTVAL (operands[3]) & 31;
3072 int size = INTVAL (operands[2]) & 31;
3074 /* Force split for non-cc0 compare. */
3075 if (which_alternative == 1)
3076 return \"#\";
3078 /* If the bit-field being tested fits in the upper or lower half of a
3079 word, it is possible to use andiu. or andil. to test it. This is
3080 useful because the condition register set-use delay is smaller for
3081 andi[ul]. than for rlinm. This doesn't work when the starting bit
3082 position is 0 because the LT and GT bits may be set wrong. */
3084 if ((start > 0 && start + size <= 16) || start >= 16)
3085 {
3086 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3087 - (1 << (16 - (start & 15) - size))));
3088 if (start < 16)
3089 return \"{andiu.|andis.} %4,%1,%3\";
3090 else
3091 return \"{andil.|andi.} %4,%1,%3\";
3092 }
3094 if (start + size >= 32)
3095 operands[3] = const0_rtx;
3096 else
3097 operands[3] = GEN_INT (start + size);
3098 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3099 }"
3100 [(set_attr "type" "compare")
3101 (set_attr "length" "4,8")])
3103 (define_split
3104 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3105 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3106 (match_operand:SI 2 "const_int_operand" "")
3107 (match_operand:SI 3 "const_int_operand" ""))
3108 (const_int 0)))
3109 (clobber (match_scratch:SI 4 ""))]
3110 "reload_completed"
3111 [(set (match_dup 4)
3112 (zero_extract:SI (match_dup 1) (match_dup 2)
3113 (match_dup 3)))
3114 (set (match_dup 0)
3115 (compare:CC (match_dup 4)
3116 (const_int 0)))]
3117 "")
3119 (define_insn "*extzvsi_internal2"
3120 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3121 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3122 (match_operand:SI 2 "const_int_operand" "i,i")
3123 (match_operand:SI 3 "const_int_operand" "i,i"))
3124 (const_int 0)))
3125 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3126 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3127 ""
3128 "*
3129 {
3130 int start = INTVAL (operands[3]) & 31;
3131 int size = INTVAL (operands[2]) & 31;
3133 /* Force split for non-cc0 compare. */
3134 if (which_alternative == 1)
3135 return \"#\";
3137 /* Since we are using the output value, we can't ignore any need for
3138 a shift. The bit-field must end at the LSB. */
3139 if (start >= 16 && start + size == 32)
3140 {
3141 operands[3] = GEN_INT ((1 << size) - 1);
3142 return \"{andil.|andi.} %0,%1,%3\";
3143 }
3145 if (start + size >= 32)
3146 operands[3] = const0_rtx;
3147 else
3148 operands[3] = GEN_INT (start + size);
3149 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3150 }"
3151 [(set_attr "type" "compare")
3152 (set_attr "length" "4,8")])
3154 (define_split
3155 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3156 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3157 (match_operand:SI 2 "const_int_operand" "")
3158 (match_operand:SI 3 "const_int_operand" ""))
3159 (const_int 0)))
3160 (set (match_operand:SI 0 "gpc_reg_operand" "")
3161 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3162 "reload_completed"
3163 [(set (match_dup 0)
3164 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3165 (set (match_dup 4)
3166 (compare:CC (match_dup 0)
3167 (const_int 0)))]
3168 "")
3170 (define_insn "extzvdi"
3171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3172 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3173 (match_operand:SI 2 "const_int_operand" "i")
3174 (match_operand:SI 3 "const_int_operand" "i")))]
3175 "TARGET_POWERPC64"
3176 "*
3177 {
3178 int start = INTVAL (operands[3]) & 63;
3179 int size = INTVAL (operands[2]) & 63;
3181 if (start + size >= 64)
3182 operands[3] = const0_rtx;
3183 else
3184 operands[3] = GEN_INT (start + size);
3185 operands[2] = GEN_INT (64 - size);
3186 return \"rldicl %0,%1,%3,%2\";
3187 }")
3189 (define_insn "*extzvdi_internal1"
3190 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3191 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3192 (match_operand:SI 2 "const_int_operand" "i")
3193 (match_operand:SI 3 "const_int_operand" "i"))
3194 (const_int 0)))
3195 (clobber (match_scratch:DI 4 "=r"))]
3196 "TARGET_POWERPC64"
3197 "*
3198 {
3199 int start = INTVAL (operands[3]) & 63;
3200 int size = INTVAL (operands[2]) & 63;
3202 if (start + size >= 64)
3203 operands[3] = const0_rtx;
3204 else
3205 operands[3] = GEN_INT (start + size);
3206 operands[2] = GEN_INT (64 - size);
3207 return \"rldicl. %4,%1,%3,%2\";
3208 }")
3210 (define_insn "*extzvdi_internal2"
3211 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3212 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3213 (match_operand:SI 2 "const_int_operand" "i")
3214 (match_operand:SI 3 "const_int_operand" "i"))
3215 (const_int 0)))
3216 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3217 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3218 "TARGET_POWERPC64"
3219 "*
3220 {
3221 int start = INTVAL (operands[3]) & 63;
3222 int size = INTVAL (operands[2]) & 63;
3224 if (start + size >= 64)
3225 operands[3] = const0_rtx;
3226 else
3227 operands[3] = GEN_INT (start + size);
3228 operands[2] = GEN_INT (64 - size);
3229 return \"rldicl. %0,%1,%3,%2\";
3230 }")
3232 (define_insn "rotlsi3"
3233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3234 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3235 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3236 ""
3237 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3239 (define_insn "*rotlsi3_internal2"
3240 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3241 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3242 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3243 (const_int 0)))
3244 (clobber (match_scratch:SI 3 "=r,r"))]
3245 ""
3246 "@
3247 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3248 #"
3249 [(set_attr "type" "delayed_compare")
3250 (set_attr "length" "4,8")])
3252 (define_split
3253 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3254 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3255 (match_operand:SI 2 "reg_or_cint_operand" ""))
3256 (const_int 0)))
3257 (clobber (match_scratch:SI 3 ""))]
3258 "reload_completed"
3259 [(set (match_dup 3)
3260 (rotate:SI (match_dup 1) (match_dup 2)))
3261 (set (match_dup 0)
3262 (compare:CC (match_dup 3)
3263 (const_int 0)))]
3264 "")
3266 (define_insn "*rotlsi3_internal3"
3267 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3268 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3269 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3270 (const_int 0)))
3271 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3272 (rotate:SI (match_dup 1) (match_dup 2)))]
3273 ""
3274 "@
3275 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3276 #"
3277 [(set_attr "type" "delayed_compare")
3278 (set_attr "length" "4,8")])
3280 (define_split
3281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3282 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3283 (match_operand:SI 2 "reg_or_cint_operand" ""))
3284 (const_int 0)))
3285 (set (match_operand:SI 0 "gpc_reg_operand" "")
3286 (rotate:SI (match_dup 1) (match_dup 2)))]
3287 "reload_completed"
3288 [(set (match_dup 0)
3289 (rotate:SI (match_dup 1) (match_dup 2)))
3290 (set (match_dup 3)
3291 (compare:CC (match_dup 0)
3292 (const_int 0)))]
3293 "")
3295 (define_insn "*rotlsi3_internal4"
3296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3297 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3298 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3299 (match_operand:SI 3 "mask_operand" "n")))]
3300 ""
3301 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3303 (define_insn "*rotlsi3_internal5"
3304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3305 (compare:CC (and:SI
3306 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3307 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3308 (match_operand:SI 3 "mask_operand" "n,n"))
3309 (const_int 0)))
3310 (clobber (match_scratch:SI 4 "=r,r"))]
3311 ""
3312 "@
3313 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3314 #"
3315 [(set_attr "type" "delayed_compare")
3316 (set_attr "length" "4,8")])
3318 (define_split
3319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3320 (compare:CC (and:SI
3321 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3322 (match_operand:SI 2 "reg_or_cint_operand" ""))
3323 (match_operand:SI 3 "mask_operand" ""))
3324 (const_int 0)))
3325 (clobber (match_scratch:SI 4 ""))]
3326 "reload_completed"
3327 [(set (match_dup 4)
3328 (and:SI (rotate:SI (match_dup 1)
3329 (match_dup 2))
3330 (match_dup 3)))
3331 (set (match_dup 0)
3332 (compare:CC (match_dup 4)
3333 (const_int 0)))]
3334 "")
3336 (define_insn "*rotlsi3_internal6"
3337 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3338 (compare:CC (and:SI
3339 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3340 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3341 (match_operand:SI 3 "mask_operand" "n,n"))
3342 (const_int 0)))
3343 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3344 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3345 ""
3346 "@
3347 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3348 #"
3349 [(set_attr "type" "delayed_compare")
3350 (set_attr "length" "4,8")])
3352 (define_split
3353 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3354 (compare:CC (and:SI
3355 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3356 (match_operand:SI 2 "reg_or_cint_operand" ""))
3357 (match_operand:SI 3 "mask_operand" ""))
3358 (const_int 0)))
3359 (set (match_operand:SI 0 "gpc_reg_operand" "")
3360 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3361 "reload_completed"
3362 [(set (match_dup 0)
3363 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3364 (set (match_dup 4)
3365 (compare:CC (match_dup 0)
3366 (const_int 0)))]
3367 "")
3369 (define_insn "*rotlsi3_internal7"
3370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3371 (zero_extend:SI
3372 (subreg:QI
3373 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3374 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3375 ""
3376 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3378 (define_insn "*rotlsi3_internal8"
3379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3380 (compare:CC (zero_extend:SI
3381 (subreg:QI
3382 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3383 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3384 (const_int 0)))
3385 (clobber (match_scratch:SI 3 "=r,r"))]
3386 ""
3387 "@
3388 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3389 #"
3390 [(set_attr "type" "delayed_compare")
3391 (set_attr "length" "4,8")])
3393 (define_split
3394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3395 (compare:CC (zero_extend:SI
3396 (subreg:QI
3397 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3398 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3399 (const_int 0)))
3400 (clobber (match_scratch:SI 3 ""))]
3401 "reload_completed"
3402 [(set (match_dup 3)
3403 (zero_extend:SI (subreg:QI
3404 (rotate:SI (match_dup 1)
3405 (match_dup 2)) 0)))
3406 (set (match_dup 0)
3407 (compare:CC (match_dup 3)
3408 (const_int 0)))]
3409 "")
3411 (define_insn "*rotlsi3_internal9"
3412 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3413 (compare:CC (zero_extend:SI
3414 (subreg:QI
3415 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3416 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3417 (const_int 0)))
3418 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3419 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3420 ""
3421 "@
3422 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3423 #"
3424 [(set_attr "type" "delayed_compare")
3425 (set_attr "length" "4,8")])
3427 (define_split
3428 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3429 (compare:CC (zero_extend:SI
3430 (subreg:QI
3431 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3432 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3433 (const_int 0)))
3434 (set (match_operand:SI 0 "gpc_reg_operand" "")
3435 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3436 "reload_completed"
3437 [(set (match_dup 0)
3438 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3439 (set (match_dup 3)
3440 (compare:CC (match_dup 0)
3441 (const_int 0)))]
3442 "")
3444 (define_insn "*rotlsi3_internal10"
3445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3446 (zero_extend:SI
3447 (subreg:HI
3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3449 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3450 ""
3451 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3453 (define_insn "*rotlsi3_internal11"
3454 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3455 (compare:CC (zero_extend:SI
3456 (subreg:HI
3457 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3458 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3459 (const_int 0)))
3460 (clobber (match_scratch:SI 3 "=r,r"))]
3461 ""
3462 "@
3463 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3464 #"
3465 [(set_attr "type" "delayed_compare")
3466 (set_attr "length" "4,8")])
3468 (define_split
3469 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3470 (compare:CC (zero_extend:SI
3471 (subreg:HI
3472 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3473 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3474 (const_int 0)))
3475 (clobber (match_scratch:SI 3 ""))]
3476 "reload_completed"
3477 [(set (match_dup 3)
3478 (zero_extend:SI (subreg:HI
3479 (rotate:SI (match_dup 1)
3480 (match_dup 2)) 0)))
3481 (set (match_dup 0)
3482 (compare:CC (match_dup 3)
3483 (const_int 0)))]
3484 "")
3486 (define_insn "*rotlsi3_internal12"
3487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3488 (compare:CC (zero_extend:SI
3489 (subreg:HI
3490 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3491 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3492 (const_int 0)))
3493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3494 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3495 ""
3496 "@
3497 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3498 #"
3499 [(set_attr "type" "delayed_compare")
3500 (set_attr "length" "4,8")])
3502 (define_split
3503 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3504 (compare:CC (zero_extend:SI
3505 (subreg:HI
3506 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3507 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3508 (const_int 0)))
3509 (set (match_operand:SI 0 "gpc_reg_operand" "")
3510 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3511 "reload_completed"
3512 [(set (match_dup 0)
3513 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3514 (set (match_dup 3)
3515 (compare:CC (match_dup 0)
3516 (const_int 0)))]
3517 "")
3519 ;; Note that we use "sle." instead of "sl." so that we can set
3520 ;; SHIFT_COUNT_TRUNCATED.
3522 (define_expand "ashlsi3"
3523 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3524 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3525 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3526 ""
3527 "
3528 {
3529 if (TARGET_POWER)
3530 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3531 else
3532 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3533 DONE;
3534 }")
3536 (define_insn "ashlsi3_power"
3537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3538 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3539 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3540 (clobber (match_scratch:SI 3 "=q,X"))]
3541 "TARGET_POWER"
3542 "@
3543 sle %0,%1,%2
3544 {sli|slwi} %0,%1,%h2")
3546 (define_insn "ashlsi3_no_power"
3547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3548 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3549 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3550 "! TARGET_POWER"
3551 "{sl|slw}%I2 %0,%1,%h2")
3553 (define_insn ""
3554 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3555 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3556 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3557 (const_int 0)))
3558 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3559 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3560 "TARGET_POWER"
3561 "@
3562 sle. %3,%1,%2
3563 {sli.|slwi.} %3,%1,%h2
3564 #
3565 #"
3566 [(set_attr "type" "delayed_compare")
3567 (set_attr "length" "4,4,8,8")])
3569 (define_split
3570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3571 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3572 (match_operand:SI 2 "reg_or_cint_operand" ""))
3573 (const_int 0)))
3574 (clobber (match_scratch:SI 3 ""))
3575 (clobber (match_scratch:SI 4 ""))]
3576 "TARGET_POWER && reload_completed"
3577 [(parallel [(set (match_dup 3)
3578 (ashift:SI (match_dup 1) (match_dup 2)))
3579 (clobber (match_dup 4))])
3580 (set (match_dup 0)
3581 (compare:CC (match_dup 3)
3582 (const_int 0)))]
3583 "")
3585 (define_insn ""
3586 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3587 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3588 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3589 (const_int 0)))
3590 (clobber (match_scratch:SI 3 "=r,r"))]
3591 "! TARGET_POWER && ! TARGET_POWERPC64"
3592 "@
3593 {sl|slw}%I2. %3,%1,%h2
3594 #"
3595 [(set_attr "type" "delayed_compare")
3596 (set_attr "length" "4,8")])
3598 (define_split
3599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3600 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3601 (match_operand:SI 2 "reg_or_cint_operand" ""))
3602 (const_int 0)))
3603 (clobber (match_scratch:SI 3 ""))]
3604 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3605 [(set (match_dup 3)
3606 (ashift:SI (match_dup 1) (match_dup 2)))
3607 (set (match_dup 0)
3608 (compare:CC (match_dup 3)
3609 (const_int 0)))]
3610 "")
3612 (define_insn ""
3613 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3614 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3616 (const_int 0)))
3617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3618 (ashift:SI (match_dup 1) (match_dup 2)))
3619 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3620 "TARGET_POWER"
3621 "@
3622 sle. %0,%1,%2
3623 {sli.|slwi.} %0,%1,%h2
3624 #
3625 #"
3626 [(set_attr "type" "delayed_compare")
3627 (set_attr "length" "4,4,8,8")])
3629 (define_split
3630 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3631 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "reg_or_cint_operand" ""))
3633 (const_int 0)))
3634 (set (match_operand:SI 0 "gpc_reg_operand" "")
3635 (ashift:SI (match_dup 1) (match_dup 2)))
3636 (clobber (match_scratch:SI 4 ""))]
3637 "TARGET_POWER && reload_completed"
3638 [(parallel [(set (match_dup 0)
3639 (ashift:SI (match_dup 1) (match_dup 2)))
3640 (clobber (match_dup 4))])
3641 (set (match_dup 3)
3642 (compare:CC (match_dup 0)
3643 (const_int 0)))]
3644 "")
3646 (define_insn ""
3647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3648 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3649 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3650 (const_int 0)))
3651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3652 (ashift:SI (match_dup 1) (match_dup 2)))]
3653 "! TARGET_POWER && ! TARGET_POWERPC64"
3654 "@
3655 {sl|slw}%I2. %0,%1,%h2
3656 #"
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,8")])
3660 (define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3663 (match_operand:SI 2 "reg_or_cint_operand" ""))
3664 (const_int 0)))
3665 (set (match_operand:SI 0 "gpc_reg_operand" "")
3666 (ashift:SI (match_dup 1) (match_dup 2)))]
3667 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3668 [(set (match_dup 0)
3669 (ashift:SI (match_dup 1) (match_dup 2)))
3670 (set (match_dup 3)
3671 (compare:CC (match_dup 0)
3672 (const_int 0)))]
3673 "")
3675 (define_insn ""
3676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3677 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3678 (match_operand:SI 2 "const_int_operand" "i"))
3679 (match_operand:SI 3 "mask_operand" "n")))]
3680 "includes_lshift_p (operands[2], operands[3])"
3681 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3683 (define_insn ""
3684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3685 (compare:CC
3686 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3687 (match_operand:SI 2 "const_int_operand" "i,i"))
3688 (match_operand:SI 3 "mask_operand" "n,n"))
3689 (const_int 0)))
3690 (clobber (match_scratch:SI 4 "=r,r"))]
3691 "includes_lshift_p (operands[2], operands[3])"
3692 "@
3693 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3694 #"
3695 [(set_attr "type" "delayed_compare")
3696 (set_attr "length" "4,8")])
3698 (define_split
3699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3700 (compare:CC
3701 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3702 (match_operand:SI 2 "const_int_operand" ""))
3703 (match_operand:SI 3 "mask_operand" ""))
3704 (const_int 0)))
3705 (clobber (match_scratch:SI 4 ""))]
3706 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3707 [(set (match_dup 4)
3708 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3709 (match_dup 3)))
3710 (set (match_dup 0)
3711 (compare:CC (match_dup 4)
3712 (const_int 0)))]
3713 "")
3715 (define_insn ""
3716 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3717 (compare:CC
3718 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3719 (match_operand:SI 2 "const_int_operand" "i,i"))
3720 (match_operand:SI 3 "mask_operand" "n,n"))
3721 (const_int 0)))
3722 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3723 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3724 "includes_lshift_p (operands[2], operands[3])"
3725 "@
3726 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3727 #"
3728 [(set_attr "type" "delayed_compare")
3729 (set_attr "length" "4,8")])
3731 (define_split
3732 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3733 (compare:CC
3734 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3735 (match_operand:SI 2 "const_int_operand" ""))
3736 (match_operand:SI 3 "mask_operand" ""))
3737 (const_int 0)))
3738 (set (match_operand:SI 0 "gpc_reg_operand" "")
3739 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3740 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3741 [(set (match_dup 0)
3742 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3743 (set (match_dup 4)
3744 (compare:CC (match_dup 0)
3745 (const_int 0)))]
3746 "")
3748 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3749 ;; "sli x,x,0".
3750 (define_expand "lshrsi3"
3751 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3752 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3753 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3754 ""
3755 "
3756 {
3757 if (TARGET_POWER)
3758 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3759 else
3760 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3761 DONE;
3762 }")
3764 (define_insn "lshrsi3_power"
3765 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3766 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3767 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3768 (clobber (match_scratch:SI 3 "=q,X,X"))]
3769 "TARGET_POWER"
3770 "@
3771 sre %0,%1,%2
3772 mr %0,%1
3773 {s%A2i|s%A2wi} %0,%1,%h2")
3775 (define_insn "lshrsi3_no_power"
3776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3777 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3778 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3779 "! TARGET_POWER"
3780 "@
3781 mr %0,%1
3782 {sr|srw}%I2 %0,%1,%h2")
3784 (define_insn ""
3785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3786 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3787 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3788 (const_int 0)))
3789 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3790 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3791 "TARGET_POWER"
3792 "@
3793 sre. %3,%1,%2
3794 mr. %1,%1
3795 {s%A2i.|s%A2wi.} %3,%1,%h2
3796 #
3797 #
3798 #"
3799 [(set_attr "type" "delayed_compare")
3800 (set_attr "length" "4,4,4,8,8,8")])
3802 (define_split
3803 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3804 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3805 (match_operand:SI 2 "reg_or_cint_operand" ""))
3806 (const_int 0)))
3807 (clobber (match_scratch:SI 3 ""))
3808 (clobber (match_scratch:SI 4 ""))]
3809 "TARGET_POWER && reload_completed"
3810 [(parallel [(set (match_dup 3)
3811 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3812 (clobber (match_dup 4))])
3813 (set (match_dup 0)
3814 (compare:CC (match_dup 3)
3815 (const_int 0)))]
3816 "")
3818 (define_insn ""
3819 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3820 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3821 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3822 (const_int 0)))
3823 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3824 "! TARGET_POWER && ! TARGET_POWERPC64"
3825 "@
3826 mr. %1,%1
3827 {sr|srw}%I2. %3,%1,%h2
3828 #
3829 #"
3830 [(set_attr "type" "delayed_compare")
3831 (set_attr "length" "4,4,8,8")])
3833 (define_split
3834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3835 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3836 (match_operand:SI 2 "reg_or_cint_operand" ""))
3837 (const_int 0)))
3838 (clobber (match_scratch:SI 3 ""))]
3839 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3840 [(set (match_dup 3)
3841 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3842 (set (match_dup 0)
3843 (compare:CC (match_dup 3)
3844 (const_int 0)))]
3845 "")
3847 (define_insn ""
3848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3849 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3850 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3851 (const_int 0)))
3852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3853 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3854 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3855 "TARGET_POWER"
3856 "@
3857 sre. %0,%1,%2
3858 mr. %0,%1
3859 {s%A2i.|s%A2wi.} %0,%1,%h2
3860 #
3861 #
3862 #"
3863 [(set_attr "type" "delayed_compare")
3864 (set_attr "length" "4,4,4,8,8,8")])
3866 (define_split
3867 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3868 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3869 (match_operand:SI 2 "reg_or_cint_operand" ""))
3870 (const_int 0)))
3871 (set (match_operand:SI 0 "gpc_reg_operand" "")
3872 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3873 (clobber (match_scratch:SI 4 ""))]
3874 "TARGET_POWER && reload_completed"
3875 [(parallel [(set (match_dup 0)
3876 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3877 (clobber (match_dup 4))])
3878 (set (match_dup 3)
3879 (compare:CC (match_dup 0)
3880 (const_int 0)))]
3881 "")
3883 (define_insn ""
3884 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3885 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3886 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3887 (const_int 0)))
3888 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3889 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3890 "! TARGET_POWER && ! TARGET_POWERPC64"
3891 "@
3892 mr. %0,%1
3893 {sr|srw}%I2. %0,%1,%h2
3894 #
3895 #"
3896 [(set_attr "type" "delayed_compare")
3897 (set_attr "length" "4,4,8,8")])
3899 (define_split
3900 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3901 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3902 (match_operand:SI 2 "reg_or_cint_operand" ""))
3903 (const_int 0)))
3904 (set (match_operand:SI 0 "gpc_reg_operand" "")
3905 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3906 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3907 [(set (match_dup 0)
3908 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3909 (set (match_dup 3)
3910 (compare:CC (match_dup 0)
3911 (const_int 0)))]
3912 "")
3914 (define_insn ""
3915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3916 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3917 (match_operand:SI 2 "const_int_operand" "i"))
3918 (match_operand:SI 3 "mask_operand" "n")))]
3919 "includes_rshift_p (operands[2], operands[3])"
3920 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3922 (define_insn ""
3923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3924 (compare:CC
3925 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3926 (match_operand:SI 2 "const_int_operand" "i,i"))
3927 (match_operand:SI 3 "mask_operand" "n,n"))
3928 (const_int 0)))
3929 (clobber (match_scratch:SI 4 "=r,r"))]
3930 "includes_rshift_p (operands[2], operands[3])"
3931 "@
3932 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3933 #"
3934 [(set_attr "type" "delayed_compare")
3935 (set_attr "length" "4,8")])
3937 (define_split
3938 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3939 (compare:CC
3940 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3941 (match_operand:SI 2 "const_int_operand" ""))
3942 (match_operand:SI 3 "mask_operand" ""))
3943 (const_int 0)))
3944 (clobber (match_scratch:SI 4 ""))]
3945 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3946 [(set (match_dup 4)
3947 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3948 (match_dup 3)))
3949 (set (match_dup 0)
3950 (compare:CC (match_dup 4)
3951 (const_int 0)))]
3952 "")
3954 (define_insn ""
3955 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3956 (compare:CC
3957 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "const_int_operand" "i,i"))
3959 (match_operand:SI 3 "mask_operand" "n,n"))
3960 (const_int 0)))
3961 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3962 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3963 "includes_rshift_p (operands[2], operands[3])"
3964 "@
3965 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3966 #"
3967 [(set_attr "type" "delayed_compare")
3968 (set_attr "length" "4,8")])
3970 (define_split
3971 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3972 (compare:CC
3973 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3974 (match_operand:SI 2 "const_int_operand" ""))
3975 (match_operand:SI 3 "mask_operand" ""))
3976 (const_int 0)))
3977 (set (match_operand:SI 0 "gpc_reg_operand" "")
3978 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3979 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3980 [(set (match_dup 0)
3981 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3982 (set (match_dup 4)
3983 (compare:CC (match_dup 0)
3984 (const_int 0)))]
3985 "")
3987 (define_insn ""
3988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3989 (zero_extend:SI
3990 (subreg:QI
3991 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3992 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
3993 "includes_rshift_p (operands[2], GEN_INT (255))"
3994 "{rlinm|rlwinm} %0,%1,%s2,0xff")
3996 (define_insn ""
3997 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3998 (compare:CC
3999 (zero_extend:SI
4000 (subreg:QI
4001 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4002 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4003 (const_int 0)))
4004 (clobber (match_scratch:SI 3 "=r,r"))]
4005 "includes_rshift_p (operands[2], GEN_INT (255))"
4006 "@
4007 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4008 #"
4009 [(set_attr "type" "delayed_compare")
4010 (set_attr "length" "4,8")])
4012 (define_split
4013 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4014 (compare:CC
4015 (zero_extend:SI
4016 (subreg:QI
4017 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4018 (match_operand:SI 2 "const_int_operand" "")) 0))
4019 (const_int 0)))
4020 (clobber (match_scratch:SI 3 ""))]
4021 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4022 [(set (match_dup 3)
4023 (zero_extend:SI (subreg:QI
4024 (lshiftrt:SI (match_dup 1)
4025 (match_dup 2)) 0)))
4026 (set (match_dup 0)
4027 (compare:CC (match_dup 3)
4028 (const_int 0)))]
4029 "")
4031 (define_insn ""
4032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4033 (compare:CC
4034 (zero_extend:SI
4035 (subreg:QI
4036 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4037 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4038 (const_int 0)))
4039 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4040 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4041 "includes_rshift_p (operands[2], GEN_INT (255))"
4042 "@
4043 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4044 #"
4045 [(set_attr "type" "delayed_compare")
4046 (set_attr "length" "4,8")])
4048 (define_split
4049 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4050 (compare:CC
4051 (zero_extend:SI
4052 (subreg:QI
4053 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4054 (match_operand:SI 2 "const_int_operand" "")) 0))
4055 (const_int 0)))
4056 (set (match_operand:SI 0 "gpc_reg_operand" "")
4057 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4058 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4059 [(set (match_dup 0)
4060 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4061 (set (match_dup 3)
4062 (compare:CC (match_dup 0)
4063 (const_int 0)))]
4064 "")
4066 (define_insn ""
4067 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4068 (zero_extend:SI
4069 (subreg:HI
4070 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4071 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4072 "includes_rshift_p (operands[2], GEN_INT (65535))"
4073 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4075 (define_insn ""
4076 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4077 (compare:CC
4078 (zero_extend:SI
4079 (subreg:HI
4080 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4081 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4082 (const_int 0)))
4083 (clobber (match_scratch:SI 3 "=r,r"))]
4084 "includes_rshift_p (operands[2], GEN_INT (65535))"
4085 "@
4086 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4087 #"
4088 [(set_attr "type" "delayed_compare")
4089 (set_attr "length" "4,8")])
4091 (define_split
4092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4093 (compare:CC
4094 (zero_extend:SI
4095 (subreg:HI
4096 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4097 (match_operand:SI 2 "const_int_operand" "")) 0))
4098 (const_int 0)))
4099 (clobber (match_scratch:SI 3 ""))]
4100 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4101 [(set (match_dup 3)
4102 (zero_extend:SI (subreg:HI
4103 (lshiftrt:SI (match_dup 1)
4104 (match_dup 2)) 0)))
4105 (set (match_dup 0)
4106 (compare:CC (match_dup 3)
4107 (const_int 0)))]
4108 "")
4110 (define_insn ""
4111 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4112 (compare:CC
4113 (zero_extend:SI
4114 (subreg:HI
4115 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4116 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4117 (const_int 0)))
4118 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4119 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4120 "includes_rshift_p (operands[2], GEN_INT (65535))"
4121 "@
4122 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4123 #"
4124 [(set_attr "type" "delayed_compare")
4125 (set_attr "length" "4,8")])
4127 (define_split
4128 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4129 (compare:CC
4130 (zero_extend:SI
4131 (subreg:HI
4132 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4133 (match_operand:SI 2 "const_int_operand" "")) 0))
4134 (const_int 0)))
4135 (set (match_operand:SI 0 "gpc_reg_operand" "")
4136 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4137 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4138 [(set (match_dup 0)
4139 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4140 (set (match_dup 3)
4141 (compare:CC (match_dup 0)
4142 (const_int 0)))]
4143 "")
4145 (define_insn ""
4146 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4147 (const_int 1)
4148 (match_operand:SI 1 "gpc_reg_operand" "r"))
4149 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4150 (const_int 31)))]
4151 "TARGET_POWER"
4152 "rrib %0,%1,%2")
4154 (define_insn ""
4155 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4156 (const_int 1)
4157 (match_operand:SI 1 "gpc_reg_operand" "r"))
4158 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4159 (const_int 31)))]
4160 "TARGET_POWER"
4161 "rrib %0,%1,%2")
4163 (define_insn ""
4164 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4165 (const_int 1)
4166 (match_operand:SI 1 "gpc_reg_operand" "r"))
4167 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4168 (const_int 1)
4169 (const_int 0)))]
4170 "TARGET_POWER"
4171 "rrib %0,%1,%2")
4173 (define_expand "ashrsi3"
4174 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4175 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4177 ""
4178 "
4179 {
4180 if (TARGET_POWER)
4181 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4182 else
4183 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4184 DONE;
4185 }")
4187 (define_insn "ashrsi3_power"
4188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4189 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4190 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4191 (clobber (match_scratch:SI 3 "=q,X"))]
4192 "TARGET_POWER"
4193 "@
4194 srea %0,%1,%2
4195 {srai|srawi} %0,%1,%h2")
4197 (define_insn "ashrsi3_no_power"
4198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4199 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4200 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4201 "! TARGET_POWER"
4202 "{sra|sraw}%I2 %0,%1,%h2")
4204 (define_insn ""
4205 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4206 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4207 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4208 (const_int 0)))
4209 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4210 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4211 "TARGET_POWER"
4212 "@
4213 srea. %3,%1,%2
4214 {srai.|srawi.} %3,%1,%h2
4215 #
4216 #"
4217 [(set_attr "type" "delayed_compare")
4218 (set_attr "length" "4,4,8,8")])
4220 (define_split
4221 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4222 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4223 (match_operand:SI 2 "reg_or_cint_operand" ""))
4224 (const_int 0)))
4225 (clobber (match_scratch:SI 3 ""))
4226 (clobber (match_scratch:SI 4 ""))]
4227 "TARGET_POWER && reload_completed"
4228 [(parallel [(set (match_dup 3)
4229 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4230 (clobber (match_dup 4))])
4231 (set (match_dup 0)
4232 (compare:CC (match_dup 3)
4233 (const_int 0)))]
4234 "")
4236 (define_insn ""
4237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4238 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4239 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4240 (const_int 0)))
4241 (clobber (match_scratch:SI 3 "=r,r"))]
4242 "! TARGET_POWER"
4243 "@
4244 {sra|sraw}%I2. %3,%1,%h2
4245 #"
4246 [(set_attr "type" "delayed_compare")
4247 (set_attr "length" "4,8")])
4249 (define_split
4250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4251 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4252 (match_operand:SI 2 "reg_or_cint_operand" ""))
4253 (const_int 0)))
4254 (clobber (match_scratch:SI 3 ""))]
4255 "! TARGET_POWER && reload_completed"
4256 [(set (match_dup 3)
4257 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4258 (set (match_dup 0)
4259 (compare:CC (match_dup 3)
4260 (const_int 0)))]
4261 "")
4263 (define_insn ""
4264 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4265 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4266 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4267 (const_int 0)))
4268 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4269 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4270 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4271 "TARGET_POWER"
4272 "@
4273 srea. %0,%1,%2
4274 {srai.|srawi.} %0,%1,%h2
4275 #
4276 #"
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,4,8,8")])
4280 (define_split
4281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4282 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4283 (match_operand:SI 2 "reg_or_cint_operand" ""))
4284 (const_int 0)))
4285 (set (match_operand:SI 0 "gpc_reg_operand" "")
4286 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4287 (clobber (match_scratch:SI 4 ""))]
4288 "TARGET_POWER && reload_completed"
4289 [(parallel [(set (match_dup 0)
4290 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4291 (clobber (match_dup 4))])
4292 (set (match_dup 3)
4293 (compare:CC (match_dup 0)
4294 (const_int 0)))]
4295 "")
4297 (define_insn ""
4298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4299 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4301 (const_int 0)))
4302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4303 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4304 "! TARGET_POWER"
4305 "@
4306 {sra|sraw}%I2. %0,%1,%h2
4307 #"
4308 [(set_attr "type" "delayed_compare")
4309 (set_attr "length" "4,8")])
4310 \f
4311 (define_split
4312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4313 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4314 (match_operand:SI 2 "reg_or_cint_operand" ""))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4318 "! TARGET_POWER && reload_completed"
4319 [(set (match_dup 0)
4320 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4321 (set (match_dup 3)
4322 (compare:CC (match_dup 0)
4323 (const_int 0)))]
4324 "")
4326 ;; Floating-point insns, excluding normal data motion.
4327 ;;
4328 ;; PowerPC has a full set of single-precision floating point instructions.
4329 ;;
4330 ;; For the POWER architecture, we pretend that we have both SFmode and
4331 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4332 ;; The only conversions we will do will be when storing to memory. In that
4333 ;; case, we will use the "frsp" instruction before storing.
4334 ;;
4335 ;; Note that when we store into a single-precision memory location, we need to
4336 ;; use the frsp insn first. If the register being stored isn't dead, we
4337 ;; need a scratch register for the frsp. But this is difficult when the store
4338 ;; is done by reload. It is not incorrect to do the frsp on the register in
4339 ;; this case, we just lose precision that we would have otherwise gotten but
4340 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4342 (define_insn "extendsfdf2"
4343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4344 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4345 "TARGET_HARD_FLOAT && TARGET_FPRS"
4346 "*
4347 {
4348 if (REGNO (operands[0]) == REGNO (operands[1]))
4349 return \"\";
4350 else
4351 return \"fmr %0,%1\";
4352 }"
4353 [(set_attr "type" "fp")])
4355 (define_insn "truncdfsf2"
4356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4357 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4358 "TARGET_HARD_FLOAT && TARGET_FPRS"
4359 "frsp %0,%1"
4360 [(set_attr "type" "fp")])
4362 (define_insn "aux_truncdfsf2"
4363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4364 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4365 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4366 "frsp %0,%1"
4367 [(set_attr "type" "fp")])
4369 (define_expand "negsf2"
4370 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4371 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4372 "TARGET_HARD_FLOAT"
4373 "")
4375 (define_insn "*negsf2"
4376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4377 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4378 "TARGET_HARD_FLOAT && TARGET_FPRS"
4379 "fneg %0,%1"
4380 [(set_attr "type" "fp")])
4382 (define_expand "abssf2"
4383 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4384 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4385 "TARGET_HARD_FLOAT"
4386 "")
4388 (define_insn "*abssf2"
4389 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4390 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4391 "TARGET_HARD_FLOAT && TARGET_FPRS"
4392 "fabs %0,%1"
4393 [(set_attr "type" "fp")])
4395 (define_insn ""
4396 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4397 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4398 "TARGET_HARD_FLOAT && TARGET_FPRS"
4399 "fnabs %0,%1"
4400 [(set_attr "type" "fp")])
4402 (define_expand "addsf3"
4403 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4404 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4405 (match_operand:SF 2 "gpc_reg_operand" "")))]
4406 "TARGET_HARD_FLOAT"
4407 "")
4409 (define_insn ""
4410 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4411 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4412 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4413 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4414 "fadds %0,%1,%2"
4415 [(set_attr "type" "fp")])
4417 (define_insn ""
4418 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4419 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4420 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4421 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4422 "{fa|fadd} %0,%1,%2"
4423 [(set_attr "type" "fp")])
4425 (define_expand "subsf3"
4426 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4427 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4428 (match_operand:SF 2 "gpc_reg_operand" "")))]
4429 "TARGET_HARD_FLOAT"
4430 "")
4432 (define_insn ""
4433 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4434 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4435 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4436 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4437 "fsubs %0,%1,%2"
4438 [(set_attr "type" "fp")])
4440 (define_insn ""
4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4443 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4444 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4445 "{fs|fsub} %0,%1,%2"
4446 [(set_attr "type" "fp")])
4448 (define_expand "mulsf3"
4449 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4450 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4451 (match_operand:SF 2 "gpc_reg_operand" "")))]
4452 "TARGET_HARD_FLOAT"
4453 "")
4455 (define_insn ""
4456 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4457 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4458 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4459 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4460 "fmuls %0,%1,%2"
4461 [(set_attr "type" "fp")])
4463 (define_insn ""
4464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4465 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4466 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4467 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4468 "{fm|fmul} %0,%1,%2"
4469 [(set_attr "type" "dmul")])
4471 (define_expand "divsf3"
4472 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4473 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4474 (match_operand:SF 2 "gpc_reg_operand" "")))]
4475 "TARGET_HARD_FLOAT"
4476 "")
4478 (define_insn ""
4479 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4480 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4481 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4482 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4483 "fdivs %0,%1,%2"
4484 [(set_attr "type" "sdiv")])
4486 (define_insn ""
4487 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4488 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4489 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4490 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4491 "{fd|fdiv} %0,%1,%2"
4492 [(set_attr "type" "ddiv")])
4494 (define_insn ""
4495 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4496 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4497 (match_operand:SF 2 "gpc_reg_operand" "f"))
4498 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4499 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4500 "fmadds %0,%1,%2,%3"
4501 [(set_attr "type" "fp")])
4503 (define_insn ""
4504 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4505 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4506 (match_operand:SF 2 "gpc_reg_operand" "f"))
4507 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4508 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4509 "{fma|fmadd} %0,%1,%2,%3"
4510 [(set_attr "type" "dmul")])
4512 (define_insn ""
4513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4514 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4515 (match_operand:SF 2 "gpc_reg_operand" "f"))
4516 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4517 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4518 "fmsubs %0,%1,%2,%3"
4519 [(set_attr "type" "fp")])
4521 (define_insn ""
4522 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4523 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4524 (match_operand:SF 2 "gpc_reg_operand" "f"))
4525 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4526 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4527 "{fms|fmsub} %0,%1,%2,%3"
4528 [(set_attr "type" "dmul")])
4530 (define_insn ""
4531 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4532 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4533 (match_operand:SF 2 "gpc_reg_operand" "f"))
4534 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4535 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4536 && HONOR_SIGNED_ZEROS (SFmode)"
4537 "fnmadds %0,%1,%2,%3"
4538 [(set_attr "type" "fp")])
4540 (define_insn ""
4541 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4542 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4543 (match_operand:SF 2 "gpc_reg_operand" "f"))
4544 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4545 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4546 && ! HONOR_SIGNED_ZEROS (SFmode)"
4547 "fnmadds %0,%1,%2,%3"
4548 [(set_attr "type" "fp")])
4550 (define_insn ""
4551 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4552 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4553 (match_operand:SF 2 "gpc_reg_operand" "f"))
4554 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4555 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4556 "{fnma|fnmadd} %0,%1,%2,%3"
4557 [(set_attr "type" "dmul")])
4559 (define_insn ""
4560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4561 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4562 (match_operand:SF 2 "gpc_reg_operand" "f"))
4563 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4564 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4565 && ! HONOR_SIGNED_ZEROS (SFmode)"
4566 "{fnma|fnmadd} %0,%1,%2,%3"
4567 [(set_attr "type" "dmul")])
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f"))
4573 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4574 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4575 && HONOR_SIGNED_ZEROS (SFmode)"
4576 "fnmsubs %0,%1,%2,%3"
4577 [(set_attr "type" "fp")])
4579 (define_insn ""
4580 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4581 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4582 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4583 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4584 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4585 && ! HONOR_SIGNED_ZEROS (SFmode)"
4586 "fnmsubs %0,%1,%2,%3"
4587 [(set_attr "type" "fp")])
4589 (define_insn ""
4590 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4591 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4592 (match_operand:SF 2 "gpc_reg_operand" "f"))
4593 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4594 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4595 "{fnms|fnmsub} %0,%1,%2,%3"
4596 [(set_attr "type" "dmul")])
4598 (define_insn ""
4599 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4600 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4601 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4602 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4603 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4604 && ! HONOR_SIGNED_ZEROS (SFmode)"
4605 "{fnms|fnmsub} %0,%1,%2,%3"
4606 [(set_attr "type" "fp")])
4608 (define_expand "sqrtsf2"
4609 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4610 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4611 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4612 "")
4614 (define_insn ""
4615 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4616 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4617 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4618 "fsqrts %0,%1"
4619 [(set_attr "type" "ssqrt")])
4621 (define_insn ""
4622 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4623 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4624 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4625 "fsqrt %0,%1"
4626 [(set_attr "type" "dsqrt")])
4628 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4629 ;; fsel instruction and some auxiliary computations. Then we just have a
4630 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4631 ;; combine.
4632 (define_expand "maxsf3"
4633 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4634 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4635 (match_operand:SF 2 "gpc_reg_operand" ""))
4636 (match_dup 1)
4637 (match_dup 2)))]
4638 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4639 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4641 (define_expand "minsf3"
4642 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4643 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4644 (match_operand:SF 2 "gpc_reg_operand" ""))
4645 (match_dup 2)
4646 (match_dup 1)))]
4647 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4648 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4650 (define_split
4651 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4652 (match_operator:SF 3 "min_max_operator"
4653 [(match_operand:SF 1 "gpc_reg_operand" "")
4654 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4655 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4656 [(const_int 0)]
4657 "
4658 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4659 operands[1], operands[2]);
4660 DONE;
4661 }")
4663 (define_expand "movsicc"
4664 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4665 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4666 (match_operand:SI 2 "gpc_reg_operand" "")
4667 (match_operand:SI 3 "gpc_reg_operand" "")))]
4668 "TARGET_ISEL"
4669 "
4670 {
4671 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4672 DONE;
4673 else
4674 FAIL;
4675 }")
4677 ;; We use the BASE_REGS for the isel input operands because, if rA is
4678 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4679 ;; because we may switch the operands and rB may end up being rA.
4680 ;;
4681 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4682 ;; leave out the mode in operand 4 and use one pattern, but reload can
4683 ;; change the mode underneath our feet and then gets confused trying
4684 ;; to reload the value.
4685 (define_insn "isel_signed"
4686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4687 (if_then_else:SI
4688 (match_operator 1 "comparison_operator"
4689 [(match_operand:CC 4 "cc_reg_operand" "y")
4690 (const_int 0)])
4691 (match_operand:SI 2 "gpc_reg_operand" "b")
4692 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4693 "TARGET_ISEL"
4694 "*
4695 { return output_isel (operands); }"
4696 [(set_attr "length" "4")])
4698 (define_insn "isel_unsigned"
4699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4700 (if_then_else:SI
4701 (match_operator 1 "comparison_operator"
4702 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4703 (const_int 0)])
4704 (match_operand:SI 2 "gpc_reg_operand" "b")
4705 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4706 "TARGET_ISEL"
4707 "*
4708 { return output_isel (operands); }"
4709 [(set_attr "length" "4")])
4711 (define_expand "movsfcc"
4712 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4713 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4714 (match_operand:SF 2 "gpc_reg_operand" "")
4715 (match_operand:SF 3 "gpc_reg_operand" "")))]
4716 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4717 "
4718 {
4719 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4720 DONE;
4721 else
4722 FAIL;
4723 }")
4725 (define_insn "*fselsfsf4"
4726 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4727 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4728 (match_operand:SF 4 "zero_fp_constant" "F"))
4729 (match_operand:SF 2 "gpc_reg_operand" "f")
4730 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4731 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4732 "fsel %0,%1,%2,%3"
4733 [(set_attr "type" "fp")])
4735 (define_insn "*fseldfsf4"
4736 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4737 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4738 (match_operand:DF 4 "zero_fp_constant" "F"))
4739 (match_operand:SF 2 "gpc_reg_operand" "f")
4740 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4741 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4742 "fsel %0,%1,%2,%3"
4743 [(set_attr "type" "fp")])
4745 (define_insn "negdf2"
4746 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4747 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4748 "TARGET_HARD_FLOAT && TARGET_FPRS"
4749 "fneg %0,%1"
4750 [(set_attr "type" "fp")])
4752 (define_insn "absdf2"
4753 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4754 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4755 "TARGET_HARD_FLOAT && TARGET_FPRS"
4756 "fabs %0,%1"
4757 [(set_attr "type" "fp")])
4759 (define_insn ""
4760 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4761 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4762 "TARGET_HARD_FLOAT && TARGET_FPRS"
4763 "fnabs %0,%1"
4764 [(set_attr "type" "fp")])
4766 (define_insn "adddf3"
4767 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4768 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4769 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4770 "TARGET_HARD_FLOAT && TARGET_FPRS"
4771 "{fa|fadd} %0,%1,%2"
4772 [(set_attr "type" "fp")])
4774 (define_insn "subdf3"
4775 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4776 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4777 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4778 "TARGET_HARD_FLOAT && TARGET_FPRS"
4779 "{fs|fsub} %0,%1,%2"
4780 [(set_attr "type" "fp")])
4782 (define_insn "muldf3"
4783 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4784 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4785 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4786 "TARGET_HARD_FLOAT && TARGET_FPRS"
4787 "{fm|fmul} %0,%1,%2"
4788 [(set_attr "type" "dmul")])
4790 (define_insn "divdf3"
4791 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4792 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4793 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4794 "TARGET_HARD_FLOAT && TARGET_FPRS"
4795 "{fd|fdiv} %0,%1,%2"
4796 [(set_attr "type" "ddiv")])
4798 (define_insn ""
4799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4800 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4801 (match_operand:DF 2 "gpc_reg_operand" "f"))
4802 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4803 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4804 "{fma|fmadd} %0,%1,%2,%3"
4805 [(set_attr "type" "dmul")])
4807 (define_insn ""
4808 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4809 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4810 (match_operand:DF 2 "gpc_reg_operand" "f"))
4811 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4812 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4813 "{fms|fmsub} %0,%1,%2,%3"
4814 [(set_attr "type" "dmul")])
4816 (define_insn ""
4817 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4818 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4819 (match_operand:DF 2 "gpc_reg_operand" "f"))
4820 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4821 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4822 && HONOR_SIGNED_ZEROS (DFmode)"
4823 "{fnma|fnmadd} %0,%1,%2,%3"
4824 [(set_attr "type" "dmul")])
4826 (define_insn ""
4827 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4828 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4829 (match_operand:DF 2 "gpc_reg_operand" "f"))
4830 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4831 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4832 && ! HONOR_SIGNED_ZEROS (DFmode)"
4833 "{fnma|fnmadd} %0,%1,%2,%3"
4834 [(set_attr "type" "dmul")])
4836 (define_insn ""
4837 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4838 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4839 (match_operand:DF 2 "gpc_reg_operand" "f"))
4840 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4841 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4842 && HONOR_SIGNED_ZEROS (DFmode)"
4843 "{fnms|fnmsub} %0,%1,%2,%3"
4844 [(set_attr "type" "dmul")])
4846 (define_insn ""
4847 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4848 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4849 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4850 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4851 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4852 && ! HONOR_SIGNED_ZEROS (DFmode)"
4853 "{fnms|fnmsub} %0,%1,%2,%3"
4854 [(set_attr "type" "dmul")])
4856 (define_insn "sqrtdf2"
4857 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4858 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4859 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4860 "fsqrt %0,%1"
4861 [(set_attr "type" "dsqrt")])
4863 ;; The conditional move instructions allow us to perform max and min
4864 ;; operations even when
4866 (define_expand "maxdf3"
4867 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4868 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4869 (match_operand:DF 2 "gpc_reg_operand" ""))
4870 (match_dup 1)
4871 (match_dup 2)))]
4872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4873 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4875 (define_expand "mindf3"
4876 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4877 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4878 (match_operand:DF 2 "gpc_reg_operand" ""))
4879 (match_dup 2)
4880 (match_dup 1)))]
4881 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4882 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4884 (define_split
4885 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4886 (match_operator:DF 3 "min_max_operator"
4887 [(match_operand:DF 1 "gpc_reg_operand" "")
4888 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4889 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4890 [(const_int 0)]
4891 "
4892 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4893 operands[1], operands[2]);
4894 DONE;
4895 }")
4897 (define_expand "movdfcc"
4898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4899 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4900 (match_operand:DF 2 "gpc_reg_operand" "")
4901 (match_operand:DF 3 "gpc_reg_operand" "")))]
4902 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4903 "
4904 {
4905 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4906 DONE;
4907 else
4908 FAIL;
4909 }")
4911 (define_insn "*fseldfdf4"
4912 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4913 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4914 (match_operand:DF 4 "zero_fp_constant" "F"))
4915 (match_operand:DF 2 "gpc_reg_operand" "f")
4916 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4917 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4918 "fsel %0,%1,%2,%3"
4919 [(set_attr "type" "fp")])
4921 (define_insn "*fselsfdf4"
4922 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4923 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4924 (match_operand:SF 4 "zero_fp_constant" "F"))
4925 (match_operand:DF 2 "gpc_reg_operand" "f")
4926 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4927 "TARGET_PPC_GFXOPT"
4928 "fsel %0,%1,%2,%3"
4929 [(set_attr "type" "fp")])
4930 \f
4931 ;; Conversions to and from floating-point.
4933 (define_expand "fixunssfsi2"
4934 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4935 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))]
4936 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4937 "")
4939 (define_expand "fix_truncsfsi2"
4940 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4941 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4942 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4943 "")
4945 ; For each of these conversions, there is a define_expand, a define_insn
4946 ; with a '#' template, and a define_split (with C code). The idea is
4947 ; to allow constant folding with the template of the define_insn,
4948 ; then to have the insns split later (between sched1 and final).
4950 (define_expand "floatsidf2"
4951 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4952 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4953 (use (match_dup 2))
4954 (use (match_dup 3))
4955 (clobber (match_dup 4))
4956 (clobber (match_dup 5))
4957 (clobber (match_dup 6))])]
4958 "TARGET_HARD_FLOAT && TARGET_FPRS"
4959 "
4960 {
4961 if (TARGET_POWERPC64)
4962 {
4963 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4964 rtx t1 = gen_reg_rtx (DImode);
4965 rtx t2 = gen_reg_rtx (DImode);
4966 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4967 DONE;
4968 }
4970 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
4971 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
4972 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
4973 operands[5] = gen_reg_rtx (DFmode);
4974 operands[6] = gen_reg_rtx (SImode);
4975 }")
4977 (define_insn "*floatsidf2_internal"
4978 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
4979 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
4980 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
4981 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
4982 (clobber (match_operand:DF 4 "memory_operand" "=o"))
4983 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
4984 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
4985 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
4986 "#"
4987 [(set_attr "length" "24")])
4989 (define_split
4990 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4991 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4992 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4993 (use (match_operand:DF 3 "gpc_reg_operand" ""))
4994 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
4995 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
4996 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
4997 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
4998 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4999 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5000 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5001 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5002 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5003 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5004 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5005 "
5006 {
5007 rtx lowword, highword;
5008 if (GET_CODE (operands[4]) != MEM)
5009 abort();
5010 highword = XEXP (operands[4], 0);
5011 lowword = plus_constant (highword, 4);
5012 if (! WORDS_BIG_ENDIAN)
5013 {
5014 rtx tmp;
5015 tmp = highword; highword = lowword; lowword = tmp;
5016 }
5018 emit_insn (gen_xorsi3 (operands[6], operands[1],
5019 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5020 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5021 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5022 emit_move_insn (operands[5], operands[4]);
5023 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5024 DONE;
5025 }")
5027 (define_expand "floatunssisf2"
5028 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5029 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5030 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5031 "")
5033 (define_expand "floatunssidf2"
5034 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5035 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5036 (use (match_dup 2))
5037 (use (match_dup 3))
5038 (clobber (match_dup 4))
5039 (clobber (match_dup 5))])]
5040 "TARGET_HARD_FLOAT && TARGET_FPRS"
5041 "
5042 {
5043 if (TARGET_POWERPC64)
5044 {
5045 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5046 rtx t1 = gen_reg_rtx (DImode);
5047 rtx t2 = gen_reg_rtx (DImode);
5048 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5049 t1, t2));
5050 DONE;
5051 }
5053 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5054 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5055 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5056 operands[5] = gen_reg_rtx (DFmode);
5057 }")
5059 (define_insn "*floatunssidf2_internal"
5060 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5061 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5062 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5063 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5064 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5065 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5066 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5067 "#"
5068 [(set_attr "length" "20")])
5070 (define_split
5071 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5073 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5074 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5075 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5076 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5077 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5078 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5079 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5080 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5081 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5082 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5083 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5084 "
5085 {
5086 rtx lowword, highword;
5087 if (GET_CODE (operands[4]) != MEM)
5088 abort();
5089 highword = XEXP (operands[4], 0);
5090 lowword = plus_constant (highword, 4);
5091 if (! WORDS_BIG_ENDIAN)
5092 {
5093 rtx tmp;
5094 tmp = highword; highword = lowword; lowword = tmp;
5095 }
5097 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5098 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5099 emit_move_insn (operands[5], operands[4]);
5100 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5101 DONE;
5102 }")
5104 (define_expand "fix_truncdfsi2"
5105 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5106 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5107 (clobber (match_dup 2))
5108 (clobber (match_dup 3))])]
5109 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5110 "
5111 {
5112 operands[2] = gen_reg_rtx (DImode);
5113 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5114 }")
5116 (define_insn "*fix_truncdfsi2_internal"
5117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5118 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5119 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5120 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5121 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5122 "#"
5123 [(set_attr "length" "16")])
5125 (define_split
5126 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5127 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5128 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5129 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5130 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5131 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5132 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5133 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5134 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5135 "
5136 {
5137 rtx lowword;
5138 if (GET_CODE (operands[3]) != MEM)
5139 abort();
5140 lowword = XEXP (operands[3], 0);
5141 if (WORDS_BIG_ENDIAN)
5142 lowword = plus_constant (lowword, 4);
5144 emit_insn (gen_fctiwz (operands[2], operands[1]));
5145 emit_move_insn (operands[3], operands[2]);
5146 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5147 DONE;
5148 }")
5150 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5151 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5152 ; because the first makes it clear that operand 0 is not live
5153 ; before the instruction.
5154 (define_insn "fctiwz"
5155 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5156 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5157 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5158 "{fcirz|fctiwz} %0,%1"
5159 [(set_attr "type" "fp")])
5161 (define_expand "floatsisf2"
5162 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5163 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5164 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5165 "")
5167 (define_insn "floatdidf2"
5168 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5169 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5170 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5171 "fcfid %0,%1"
5172 [(set_attr "type" "fp")])
5174 (define_insn_and_split "floatsidf_ppc64"
5175 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5176 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5177 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5178 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5179 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5180 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5181 "#"
5182 ""
5183 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5184 (set (match_dup 2) (match_dup 3))
5185 (set (match_dup 4) (match_dup 2))
5186 (set (match_dup 0) (float:DF (match_dup 4)))]
5187 "")
5189 (define_insn_and_split "floatunssidf_ppc64"
5190 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5191 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5192 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5193 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5194 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5195 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5196 "#"
5197 ""
5198 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5199 (set (match_dup 2) (match_dup 3))
5200 (set (match_dup 4) (match_dup 2))
5201 (set (match_dup 0) (float:DF (match_dup 4)))]
5202 "")
5204 (define_insn "fix_truncdfdi2"
5205 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5206 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5207 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5208 "fctidz %0,%1"
5209 [(set_attr "type" "fp")])
5211 (define_expand "floatdisf2"
5212 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5213 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5214 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5215 "
5216 {
5217 if (!flag_unsafe_math_optimizations)
5218 {
5219 rtx label = gen_label_rtx ();
5220 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5221 emit_label (label);
5222 }
5223 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5224 DONE;
5225 }")
5227 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5228 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5229 ;; from double rounding.
5230 (define_insn_and_split "floatdisf2_internal1"
5231 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5232 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5233 (clobber (match_scratch:DF 2 "=f"))]
5234 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5235 "#"
5236 "&& reload_completed"
5237 [(set (match_dup 2)
5238 (float:DF (match_dup 1)))
5239 (set (match_dup 0)
5240 (float_truncate:SF (match_dup 2)))]
5241 "")
5243 ;; Twiddles bits to avoid double rounding.
5244 ;; Bits that might be truncated when converting to DFmode are replaced
5245 ;; by a bit that won't be lost at that stage, but is below the SFmode
5246 ;; rounding position.
5247 (define_expand "floatdisf2_internal2"
5248 [(parallel [(set (match_dup 4)
5249 (compare:CC (and:DI (match_operand:DI 0 "" "")
5250 (const_int 2047))
5251 (const_int 0)))
5252 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5253 (clobber (match_scratch:CC 7 ""))])
5254 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5255 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5256 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5257 (label_ref (match_operand:DI 1 "" ""))
5258 (pc)))
5259 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5260 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5261 (label_ref (match_dup 1))
5262 (pc)))
5263 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5264 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5265 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5266 "
5267 {
5268 operands[2] = gen_reg_rtx (DImode);
5269 operands[3] = gen_reg_rtx (DImode);
5270 operands[4] = gen_reg_rtx (CCmode);
5271 operands[5] = gen_reg_rtx (CCUNSmode);
5272 }")
5273 \f
5274 ;; Define the DImode operations that can be done in a small number
5275 ;; of instructions. The & constraints are to prevent the register
5276 ;; allocator from allocating registers that overlap with the inputs
5277 ;; (for example, having an input in 7,8 and an output in 6,7). We
5278 ;; also allow for the output being the same as one of the inputs.
5280 (define_insn "*adddi3_noppc64"
5281 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5282 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5283 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5284 "! TARGET_POWERPC64"
5285 "*
5286 {
5287 if (WORDS_BIG_ENDIAN)
5288 return (GET_CODE (operands[2])) != CONST_INT
5289 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5290 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5291 else
5292 return (GET_CODE (operands[2])) != CONST_INT
5293 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5294 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5295 }"
5296 [(set_attr "length" "8")])
5298 (define_insn "*subdi3_noppc64"
5299 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5300 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5301 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5302 "! TARGET_POWERPC64"
5303 "*
5304 {
5305 if (WORDS_BIG_ENDIAN)
5306 return (GET_CODE (operands[1]) != CONST_INT)
5307 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5308 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5309 else
5310 return (GET_CODE (operands[1]) != CONST_INT)
5311 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5312 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5313 }"
5314 [(set_attr "length" "8")])
5316 (define_insn "*negdi2_noppc64"
5317 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5318 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5319 "! TARGET_POWERPC64"
5320 "*
5321 {
5322 return (WORDS_BIG_ENDIAN)
5323 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5324 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5325 }"
5326 [(set_attr "length" "8")])
5328 (define_expand "mulsidi3"
5329 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5330 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5331 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5332 "! TARGET_POWERPC64"
5333 "
5334 {
5335 if (! TARGET_POWER && ! TARGET_POWERPC)
5336 {
5337 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5338 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5339 emit_insn (gen_mull_call ());
5340 if (WORDS_BIG_ENDIAN)
5341 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5342 else
5343 {
5344 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5345 gen_rtx_REG (SImode, 3));
5346 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5347 gen_rtx_REG (SImode, 4));
5348 }
5349 DONE;
5350 }
5351 else if (TARGET_POWER)
5352 {
5353 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5354 DONE;
5355 }
5356 }")
5358 (define_insn "mulsidi3_mq"
5359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5360 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5361 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5362 (clobber (match_scratch:SI 3 "=q"))]
5363 "TARGET_POWER"
5364 "mul %0,%1,%2\;mfmq %L0"
5365 [(set_attr "type" "imul")
5366 (set_attr "length" "8")])
5368 (define_insn "*mulsidi3_no_mq"
5369 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5370 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5371 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5372 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5373 "*
5374 {
5375 return (WORDS_BIG_ENDIAN)
5376 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5377 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5378 }"
5379 [(set_attr "type" "imul")
5380 (set_attr "length" "8")])
5382 (define_split
5383 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5384 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5385 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5386 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5387 [(set (match_dup 3)
5388 (truncate:SI
5389 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5390 (sign_extend:DI (match_dup 2)))
5391 (const_int 32))))
5392 (set (match_dup 4)
5393 (mult:SI (match_dup 1)
5394 (match_dup 2)))]
5395 "
5396 {
5397 int endian = (WORDS_BIG_ENDIAN == 0);
5398 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5399 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5400 }")
5402 (define_expand "umulsidi3"
5403 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5404 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5405 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5406 "TARGET_POWERPC && ! TARGET_POWERPC64"
5407 "
5408 {
5409 if (TARGET_POWER)
5410 {
5411 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5412 DONE;
5413 }
5414 }")
5416 (define_insn "umulsidi3_mq"
5417 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5418 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5419 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5420 (clobber (match_scratch:SI 3 "=q"))]
5421 "TARGET_POWERPC && TARGET_POWER"
5422 "*
5423 {
5424 return (WORDS_BIG_ENDIAN)
5425 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5426 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5427 }"
5428 [(set_attr "type" "imul")
5429 (set_attr "length" "8")])
5431 (define_insn "*umulsidi3_no_mq"
5432 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5433 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5434 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5435 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5436 "*
5437 {
5438 return (WORDS_BIG_ENDIAN)
5439 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5440 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5441 }"
5442 [(set_attr "type" "imul")
5443 (set_attr "length" "8")])
5445 (define_split
5446 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5447 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5448 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5449 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5450 [(set (match_dup 3)
5451 (truncate:SI
5452 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5453 (zero_extend:DI (match_dup 2)))
5454 (const_int 32))))
5455 (set (match_dup 4)
5456 (mult:SI (match_dup 1)
5457 (match_dup 2)))]
5458 "
5459 {
5460 int endian = (WORDS_BIG_ENDIAN == 0);
5461 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5462 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5463 }")
5465 (define_expand "smulsi3_highpart"
5466 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5467 (truncate:SI
5468 (lshiftrt:DI (mult:DI (sign_extend:DI
5469 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5470 (sign_extend:DI
5471 (match_operand:SI 2 "gpc_reg_operand" "r")))
5472 (const_int 32))))]
5473 ""
5474 "
5475 {
5476 if (! TARGET_POWER && ! TARGET_POWERPC)
5477 {
5478 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5479 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5480 emit_insn (gen_mulh_call ());
5481 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5482 DONE;
5483 }
5484 else if (TARGET_POWER)
5485 {
5486 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5487 DONE;
5488 }
5489 }")
5491 (define_insn "smulsi3_highpart_mq"
5492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5493 (truncate:SI
5494 (lshiftrt:DI (mult:DI (sign_extend:DI
5495 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5496 (sign_extend:DI
5497 (match_operand:SI 2 "gpc_reg_operand" "r")))
5498 (const_int 32))))
5499 (clobber (match_scratch:SI 3 "=q"))]
5500 "TARGET_POWER"
5501 "mul %0,%1,%2"
5502 [(set_attr "type" "imul")])
5504 (define_insn "*smulsi3_highpart_no_mq"
5505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5506 (truncate:SI
5507 (lshiftrt:DI (mult:DI (sign_extend:DI
5508 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5509 (sign_extend:DI
5510 (match_operand:SI 2 "gpc_reg_operand" "r")))
5511 (const_int 32))))]
5512 "TARGET_POWERPC && ! TARGET_POWER"
5513 "mulhw %0,%1,%2"
5514 [(set_attr "type" "imul")])
5516 (define_expand "umulsi3_highpart"
5517 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5518 (truncate:SI
5519 (lshiftrt:DI (mult:DI (zero_extend:DI
5520 (match_operand:SI 1 "gpc_reg_operand" ""))
5521 (zero_extend:DI
5522 (match_operand:SI 2 "gpc_reg_operand" "")))
5523 (const_int 32))))]
5524 "TARGET_POWERPC"
5525 "
5526 {
5527 if (TARGET_POWER)
5528 {
5529 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5530 DONE;
5531 }
5532 }")
5534 (define_insn "umulsi3_highpart_mq"
5535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5536 (truncate:SI
5537 (lshiftrt:DI (mult:DI (zero_extend:DI
5538 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5539 (zero_extend:DI
5540 (match_operand:SI 2 "gpc_reg_operand" "r")))
5541 (const_int 32))))
5542 (clobber (match_scratch:SI 3 "=q"))]
5543 "TARGET_POWERPC && TARGET_POWER"
5544 "mulhwu %0,%1,%2"
5545 [(set_attr "type" "imul")])
5547 (define_insn "*umulsi3_highpart_no_mq"
5548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5549 (truncate:SI
5550 (lshiftrt:DI (mult:DI (zero_extend:DI
5551 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5552 (zero_extend:DI
5553 (match_operand:SI 2 "gpc_reg_operand" "r")))
5554 (const_int 32))))]
5555 "TARGET_POWERPC && ! TARGET_POWER"
5556 "mulhwu %0,%1,%2"
5557 [(set_attr "type" "imul")])
5559 ;; If operands 0 and 2 are in the same register, we have a problem. But
5560 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5561 ;; why we have the strange constraints below.
5562 (define_insn "ashldi3_power"
5563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5564 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5565 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5566 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5567 "TARGET_POWER"
5568 "@
5569 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5570 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5571 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5572 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5573 [(set_attr "length" "8")])
5575 (define_insn "lshrdi3_power"
5576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5577 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5578 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5579 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5580 "TARGET_POWER"
5581 "@
5582 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5583 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5584 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5585 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5586 [(set_attr "length" "8")])
5588 ;; Shift by a variable amount is too complex to be worth open-coding. We
5589 ;; just handle shifts by constants.
5590 (define_insn "ashrdi3_power"
5591 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5592 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5593 (match_operand:SI 2 "const_int_operand" "M,i")))
5594 (clobber (match_scratch:SI 3 "=X,q"))]
5595 "TARGET_POWER"
5596 "@
5597 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5598 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5599 [(set_attr "length" "8")])
5601 (define_insn "ashrdi3_no_power"
5602 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5603 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5604 (match_operand:SI 2 "const_int_operand" "M,i")))]
5605 "TARGET_32BIT && !TARGET_POWER"
5606 "@
5607 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5608 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5609 [(set_attr "length" "8,12")])
5610 \f
5611 ;; PowerPC64 DImode operations.
5613 (define_expand "adddi3"
5614 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5615 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5616 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5617 ""
5618 "
5619 {
5620 if (! TARGET_POWERPC64)
5621 {
5622 if (non_short_cint_operand (operands[2], DImode))
5623 FAIL;
5624 }
5625 else
5626 if (GET_CODE (operands[2]) == CONST_INT
5627 && ! add_operand (operands[2], DImode))
5628 {
5629 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5630 ? operands[0] : gen_reg_rtx (DImode));
5632 HOST_WIDE_INT val = INTVAL (operands[2]);
5633 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5634 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5636 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5637 FAIL;
5639 /* The ordering here is important for the prolog expander.
5640 When space is allocated from the stack, adding 'low' first may
5641 produce a temporary deallocation (which would be bad). */
5642 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5643 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5644 DONE;
5645 }
5646 }")
5648 ;; Discourage ai/addic because of carry but provide it in an alternative
5649 ;; allowing register zero as source.
5651 (define_insn "*adddi3_internal1"
5652 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5653 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5654 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5655 "TARGET_POWERPC64"
5656 "@
5657 add %0,%1,%2
5658 addi %0,%1,%2
5659 addic %0,%1,%2
5660 addis %0,%1,%v2")
5662 (define_insn "*adddi3_internal2"
5663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5664 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5665 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5666 (const_int 0)))
5667 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5668 "TARGET_POWERPC64"
5669 "@
5670 add. %3,%1,%2
5671 addic. %3,%1,%2
5672 #
5673 #"
5674 [(set_attr "type" "fast_compare,compare,compare,compare")
5675 (set_attr "length" "4,4,8,8")])
5677 (define_split
5678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5679 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5680 (match_operand:DI 2 "reg_or_short_operand" ""))
5681 (const_int 0)))
5682 (clobber (match_scratch:DI 3 ""))]
5683 "TARGET_POWERPC64 && reload_completed"
5684 [(set (match_dup 3)
5685 (plus:DI (match_dup 1) (match_dup 2)))
5686 (set (match_dup 0)
5687 (compare:CC (match_dup 3)
5688 (const_int 0)))]
5689 "")
5691 (define_insn "*adddi3_internal3"
5692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5693 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5694 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5695 (const_int 0)))
5696 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5697 (plus:DI (match_dup 1) (match_dup 2)))]
5698 "TARGET_POWERPC64"
5699 "@
5700 add. %0,%1,%2
5701 addic. %0,%1,%2
5702 #
5703 #"
5704 [(set_attr "type" "fast_compare,compare,compare,compare")
5705 (set_attr "length" "4,4,8,8")])
5707 (define_split
5708 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5709 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5710 (match_operand:DI 2 "reg_or_short_operand" ""))
5711 (const_int 0)))
5712 (set (match_operand:DI 0 "gpc_reg_operand" "")
5713 (plus:DI (match_dup 1) (match_dup 2)))]
5714 "TARGET_POWERPC64 && reload_completed"
5715 [(set (match_dup 0)
5716 (plus:DI (match_dup 1) (match_dup 2)))
5717 (set (match_dup 3)
5718 (compare:CC (match_dup 0)
5719 (const_int 0)))]
5720 "")
5722 ;; Split an add that we can't do in one insn into two insns, each of which
5723 ;; does one 16-bit part. This is used by combine. Note that the low-order
5724 ;; add should be last in case the result gets used in an address.
5726 (define_split
5727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5728 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5729 (match_operand:DI 2 "non_add_cint_operand" "")))]
5730 "TARGET_POWERPC64"
5731 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5732 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5733 "
5734 {
5735 HOST_WIDE_INT val = INTVAL (operands[2]);
5736 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5737 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5739 operands[4] = GEN_INT (low);
5740 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5741 operands[3] = GEN_INT (rest);
5742 else if (! no_new_pseudos)
5743 {
5744 operands[3] = gen_reg_rtx (DImode);
5745 emit_move_insn (operands[3], operands[2]);
5746 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5747 DONE;
5748 }
5749 else
5750 FAIL;
5751 }")
5753 (define_insn "one_cmpldi2"
5754 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5755 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5756 "TARGET_POWERPC64"
5757 "nor %0,%1,%1")
5759 (define_insn ""
5760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5761 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5762 (const_int 0)))
5763 (clobber (match_scratch:DI 2 "=r,r"))]
5764 "TARGET_POWERPC64"
5765 "@
5766 nor. %2,%1,%1
5767 #"
5768 [(set_attr "type" "compare")
5769 (set_attr "length" "4,8")])
5771 (define_split
5772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5773 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5774 (const_int 0)))
5775 (clobber (match_scratch:DI 2 ""))]
5776 "TARGET_POWERPC64 && reload_completed"
5777 [(set (match_dup 2)
5778 (not:DI (match_dup 1)))
5779 (set (match_dup 0)
5780 (compare:CC (match_dup 2)
5781 (const_int 0)))]
5782 "")
5784 (define_insn ""
5785 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5786 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5787 (const_int 0)))
5788 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5789 (not:DI (match_dup 1)))]
5790 "TARGET_POWERPC64"
5791 "@
5792 nor. %0,%1,%1
5793 #"
5794 [(set_attr "type" "compare")
5795 (set_attr "length" "4,8")])
5797 (define_split
5798 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5799 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5800 (const_int 0)))
5801 (set (match_operand:DI 0 "gpc_reg_operand" "")
5802 (not:DI (match_dup 1)))]
5803 "TARGET_POWERPC64 && reload_completed"
5804 [(set (match_dup 0)
5805 (not:DI (match_dup 1)))
5806 (set (match_dup 2)
5807 (compare:CC (match_dup 0)
5808 (const_int 0)))]
5809 "")
5811 (define_insn ""
5812 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5813 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5814 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5815 "TARGET_POWERPC64"
5816 "@
5817 subf %0,%2,%1
5818 subfic %0,%2,%1")
5820 (define_insn ""
5821 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5822 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5823 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5824 (const_int 0)))
5825 (clobber (match_scratch:DI 3 "=r,r"))]
5826 "TARGET_POWERPC64"
5827 "@
5828 subf. %3,%2,%1
5829 #"
5830 [(set_attr "type" "fast_compare")
5831 (set_attr "length" "4,8")])
5833 (define_split
5834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5835 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5836 (match_operand:DI 2 "gpc_reg_operand" ""))
5837 (const_int 0)))
5838 (clobber (match_scratch:DI 3 ""))]
5839 "TARGET_POWERPC64 && reload_completed"
5840 [(set (match_dup 3)
5841 (minus:DI (match_dup 1) (match_dup 2)))
5842 (set (match_dup 0)
5843 (compare:CC (match_dup 3)
5844 (const_int 0)))]
5845 "")
5847 (define_insn ""
5848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5849 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5850 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5851 (const_int 0)))
5852 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5853 (minus:DI (match_dup 1) (match_dup 2)))]
5854 "TARGET_POWERPC64"
5855 "@
5856 subf. %0,%2,%1
5857 #"
5858 [(set_attr "type" "fast_compare")
5859 (set_attr "length" "4,8")])
5861 (define_split
5862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5863 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5864 (match_operand:DI 2 "gpc_reg_operand" ""))
5865 (const_int 0)))
5866 (set (match_operand:DI 0 "gpc_reg_operand" "")
5867 (minus:DI (match_dup 1) (match_dup 2)))]
5868 "TARGET_POWERPC64 && reload_completed"
5869 [(set (match_dup 0)
5870 (minus:DI (match_dup 1) (match_dup 2)))
5871 (set (match_dup 3)
5872 (compare:CC (match_dup 0)
5873 (const_int 0)))]
5874 "")
5876 (define_expand "subdi3"
5877 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5878 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5879 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5880 ""
5881 "
5882 {
5883 if (GET_CODE (operands[2]) == CONST_INT)
5884 {
5885 emit_insn (gen_adddi3 (operands[0], operands[1],
5886 negate_rtx (DImode, operands[2])));
5887 DONE;
5888 }
5889 }")
5891 (define_insn_and_split "absdi2"
5892 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5893 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5894 (clobber (match_scratch:DI 2 "=&r,&r"))]
5895 "TARGET_POWERPC64"
5896 "#"
5897 "&& reload_completed"
5898 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5899 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5900 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5901 "")
5903 (define_insn_and_split "*nabsdi2"
5904 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5905 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5906 (clobber (match_scratch:DI 2 "=&r,&r"))]
5907 "TARGET_POWERPC64"
5908 "#"
5909 "&& reload_completed"
5910 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5911 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5912 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5913 "")
5915 (define_expand "negdi2"
5916 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5917 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5918 ""
5919 "")
5921 (define_insn ""
5922 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5923 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5924 "TARGET_POWERPC64"
5925 "neg %0,%1")
5927 (define_insn ""
5928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5929 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5930 (const_int 0)))
5931 (clobber (match_scratch:DI 2 "=r,r"))]
5932 "TARGET_POWERPC64"
5933 "@
5934 neg. %2,%1
5935 #"
5936 [(set_attr "type" "fast_compare")
5937 (set_attr "length" "4,8")])
5939 (define_split
5940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5941 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5942 (const_int 0)))
5943 (clobber (match_scratch:DI 2 ""))]
5944 "TARGET_POWERPC64 && reload_completed"
5945 [(set (match_dup 2)
5946 (neg:DI (match_dup 1)))
5947 (set (match_dup 0)
5948 (compare:CC (match_dup 2)
5949 (const_int 0)))]
5950 "")
5952 (define_insn ""
5953 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5954 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5955 (const_int 0)))
5956 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5957 (neg:DI (match_dup 1)))]
5958 "TARGET_POWERPC64"
5959 "@
5960 neg. %0,%1
5961 #"
5962 [(set_attr "type" "fast_compare")
5963 (set_attr "length" "4,8")])
5965 (define_split
5966 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5967 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5968 (const_int 0)))
5969 (set (match_operand:DI 0 "gpc_reg_operand" "")
5970 (neg:DI (match_dup 1)))]
5971 "TARGET_POWERPC64 && reload_completed"
5972 [(set (match_dup 0)
5973 (neg:DI (match_dup 1)))
5974 (set (match_dup 2)
5975 (compare:CC (match_dup 0)
5976 (const_int 0)))]
5977 "")
5979 (define_insn "clzdi2"
5980 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5981 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5982 "TARGET_POWERPC64"
5983 "cntlzd %0,%1")
5985 (define_expand "ctzdi2"
5986 [(set (match_dup 2)
5987 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
5988 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
5989 (match_dup 2)))
5990 (clobber (scratch:CC))])
5991 (set (match_dup 4) (clz:DI (match_dup 3)))
5992 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5993 (minus:DI (const_int 63) (match_dup 4)))]
5994 "TARGET_POWERPC64"
5995 {
5996 operands[2] = gen_reg_rtx (DImode);
5997 operands[3] = gen_reg_rtx (DImode);
5998 operands[4] = gen_reg_rtx (DImode);
5999 })
6001 (define_expand "ffsdi2"
6002 [(set (match_dup 2)
6003 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6004 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6005 (match_dup 2)))
6006 (clobber (scratch:CC))])
6007 (set (match_dup 4) (clz:DI (match_dup 3)))
6008 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6009 (minus:DI (const_int 64) (match_dup 4)))]
6010 "TARGET_POWERPC64"
6011 {
6012 operands[2] = gen_reg_rtx (DImode);
6013 operands[3] = gen_reg_rtx (DImode);
6014 operands[4] = gen_reg_rtx (DImode);
6015 })
6017 (define_insn "muldi3"
6018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6019 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6020 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6021 "TARGET_POWERPC64"
6022 "mulld %0,%1,%2"
6023 [(set_attr "type" "lmul")])
6025 (define_insn "smuldi3_highpart"
6026 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6027 (truncate:DI
6028 (lshiftrt:TI (mult:TI (sign_extend:TI
6029 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6030 (sign_extend:TI
6031 (match_operand:DI 2 "gpc_reg_operand" "r")))
6032 (const_int 64))))]
6033 "TARGET_POWERPC64"
6034 "mulhd %0,%1,%2"
6035 [(set_attr "type" "lmul")])
6037 (define_insn "umuldi3_highpart"
6038 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6039 (truncate:DI
6040 (lshiftrt:TI (mult:TI (zero_extend:TI
6041 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6042 (zero_extend:TI
6043 (match_operand:DI 2 "gpc_reg_operand" "r")))
6044 (const_int 64))))]
6045 "TARGET_POWERPC64"
6046 "mulhdu %0,%1,%2"
6047 [(set_attr "type" "lmul")])
6049 (define_expand "divdi3"
6050 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6051 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6052 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6053 "TARGET_POWERPC64"
6054 "
6055 {
6056 if (GET_CODE (operands[2]) == CONST_INT
6057 && INTVAL (operands[2]) > 0
6058 && exact_log2 (INTVAL (operands[2])) >= 0)
6059 ;
6060 else
6061 operands[2] = force_reg (DImode, operands[2]);
6062 }")
6064 (define_expand "moddi3"
6065 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6066 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6067 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6068 "TARGET_POWERPC64"
6069 "
6070 {
6071 int i;
6072 rtx temp1;
6073 rtx temp2;
6075 if (GET_CODE (operands[2]) != CONST_INT
6076 || INTVAL (operands[2]) <= 0
6077 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6078 FAIL;
6080 temp1 = gen_reg_rtx (DImode);
6081 temp2 = gen_reg_rtx (DImode);
6083 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6084 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6085 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6086 DONE;
6087 }")
6089 (define_insn ""
6090 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6091 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6092 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6093 "TARGET_POWERPC64"
6094 "sradi %0,%1,%p2\;addze %0,%0"
6095 [(set_attr "length" "8")])
6097 (define_insn ""
6098 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6099 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6100 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6101 (const_int 0)))
6102 (clobber (match_scratch:DI 3 "=r,r"))]
6103 "TARGET_POWERPC64"
6104 "@
6105 sradi %3,%1,%p2\;addze. %3,%3
6106 #"
6107 [(set_attr "type" "compare")
6108 (set_attr "length" "8,12")])
6110 (define_split
6111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6112 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6113 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6114 (const_int 0)))
6115 (clobber (match_scratch:DI 3 ""))]
6116 "TARGET_POWERPC64 && reload_completed"
6117 [(set (match_dup 3)
6118 (div:DI (match_dup 1) (match_dup 2)))
6119 (set (match_dup 0)
6120 (compare:CC (match_dup 3)
6121 (const_int 0)))]
6122 "")
6124 (define_insn ""
6125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6126 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6127 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6128 (const_int 0)))
6129 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6130 (div:DI (match_dup 1) (match_dup 2)))]
6131 "TARGET_POWERPC64"
6132 "@
6133 sradi %0,%1,%p2\;addze. %0,%0
6134 #"
6135 [(set_attr "type" "compare")
6136 (set_attr "length" "8,12")])
6138 (define_split
6139 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6140 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6141 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6142 (const_int 0)))
6143 (set (match_operand:DI 0 "gpc_reg_operand" "")
6144 (div:DI (match_dup 1) (match_dup 2)))]
6145 "TARGET_POWERPC64 && reload_completed"
6146 [(set (match_dup 0)
6147 (div:DI (match_dup 1) (match_dup 2)))
6148 (set (match_dup 3)
6149 (compare:CC (match_dup 0)
6150 (const_int 0)))]
6151 "")
6153 (define_insn ""
6154 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6155 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6156 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6157 "TARGET_POWERPC64"
6158 "divd %0,%1,%2"
6159 [(set_attr "type" "ldiv")])
6161 (define_insn "udivdi3"
6162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6163 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6164 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6165 "TARGET_POWERPC64"
6166 "divdu %0,%1,%2"
6167 [(set_attr "type" "ldiv")])
6169 (define_insn "rotldi3"
6170 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6171 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6172 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6173 "TARGET_POWERPC64"
6174 "rld%I2cl %0,%1,%H2,0")
6176 (define_insn "*rotldi3_internal2"
6177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6178 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6179 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6180 (const_int 0)))
6181 (clobber (match_scratch:DI 3 "=r,r"))]
6182 "TARGET_POWERPC64"
6183 "@
6184 rld%I2cl. %3,%1,%H2,0
6185 #"
6186 [(set_attr "type" "delayed_compare")
6187 (set_attr "length" "4,8")])
6189 (define_split
6190 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6191 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6192 (match_operand:DI 2 "reg_or_cint_operand" ""))
6193 (const_int 0)))
6194 (clobber (match_scratch:DI 3 ""))]
6195 "TARGET_POWERPC64 && reload_completed"
6196 [(set (match_dup 3)
6197 (rotate:DI (match_dup 1) (match_dup 2)))
6198 (set (match_dup 0)
6199 (compare:CC (match_dup 3)
6200 (const_int 0)))]
6201 "")
6203 (define_insn "*rotldi3_internal3"
6204 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6205 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6206 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6207 (const_int 0)))
6208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6209 (rotate:DI (match_dup 1) (match_dup 2)))]
6210 "TARGET_POWERPC64"
6211 "@
6212 rld%I2cl. %0,%1,%H2,0
6213 #"
6214 [(set_attr "type" "delayed_compare")
6215 (set_attr "length" "4,8")])
6217 (define_split
6218 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6219 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6220 (match_operand:DI 2 "reg_or_cint_operand" ""))
6221 (const_int 0)))
6222 (set (match_operand:DI 0 "gpc_reg_operand" "")
6223 (rotate:DI (match_dup 1) (match_dup 2)))]
6224 "TARGET_POWERPC64 && reload_completed"
6225 [(set (match_dup 0)
6226 (rotate:DI (match_dup 1) (match_dup 2)))
6227 (set (match_dup 3)
6228 (compare:CC (match_dup 0)
6229 (const_int 0)))]
6230 "")
6232 (define_insn "*rotldi3_internal4"
6233 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6234 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6235 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6236 (match_operand:DI 3 "mask64_operand" "n")))]
6237 "TARGET_POWERPC64"
6238 "rld%I2c%B3 %0,%1,%H2,%S3")
6240 (define_insn "*rotldi3_internal5"
6241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6242 (compare:CC (and:DI
6243 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6244 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6245 (match_operand:DI 3 "mask64_operand" "n,n"))
6246 (const_int 0)))
6247 (clobber (match_scratch:DI 4 "=r,r"))]
6248 "TARGET_POWERPC64"
6249 "@
6250 rld%I2c%B3. %4,%1,%H2,%S3
6251 #"
6252 [(set_attr "type" "delayed_compare")
6253 (set_attr "length" "4,8")])
6255 (define_split
6256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6257 (compare:CC (and:DI
6258 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6259 (match_operand:DI 2 "reg_or_cint_operand" ""))
6260 (match_operand:DI 3 "mask64_operand" ""))
6261 (const_int 0)))
6262 (clobber (match_scratch:DI 4 ""))]
6263 "TARGET_POWERPC64 && reload_completed"
6264 [(set (match_dup 4)
6265 (and:DI (rotate:DI (match_dup 1)
6266 (match_dup 2))
6267 (match_dup 3)))
6268 (set (match_dup 0)
6269 (compare:CC (match_dup 4)
6270 (const_int 0)))]
6271 "")
6273 (define_insn "*rotldi3_internal6"
6274 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6275 (compare:CC (and:DI
6276 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6277 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6278 (match_operand:DI 3 "mask64_operand" "n,n"))
6279 (const_int 0)))
6280 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6281 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6282 "TARGET_POWERPC64"
6283 "@
6284 rld%I2c%B3. %0,%1,%H2,%S3
6285 #"
6286 [(set_attr "type" "delayed_compare")
6287 (set_attr "length" "4,8")])
6289 (define_split
6290 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6291 (compare:CC (and:DI
6292 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6293 (match_operand:DI 2 "reg_or_cint_operand" ""))
6294 (match_operand:DI 3 "mask64_operand" ""))
6295 (const_int 0)))
6296 (set (match_operand:DI 0 "gpc_reg_operand" "")
6297 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6298 "TARGET_POWERPC64 && reload_completed"
6299 [(set (match_dup 0)
6300 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6301 (set (match_dup 4)
6302 (compare:CC (match_dup 0)
6303 (const_int 0)))]
6304 "")
6306 (define_insn "*rotldi3_internal7"
6307 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6308 (zero_extend:DI
6309 (subreg:QI
6310 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6311 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6312 "TARGET_POWERPC64"
6313 "rld%I2cl %0,%1,%H2,56")
6315 (define_insn "*rotldi3_internal8"
6316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6317 (compare:CC (zero_extend:DI
6318 (subreg:QI
6319 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6320 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6321 (const_int 0)))
6322 (clobber (match_scratch:DI 3 "=r,r"))]
6323 "TARGET_POWERPC64"
6324 "@
6325 rld%I2cl. %3,%1,%H2,56
6326 #"
6327 [(set_attr "type" "delayed_compare")
6328 (set_attr "length" "4,8")])
6330 (define_split
6331 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6332 (compare:CC (zero_extend:DI
6333 (subreg:QI
6334 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6335 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6336 (const_int 0)))
6337 (clobber (match_scratch:DI 3 ""))]
6338 "TARGET_POWERPC64 && reload_completed"
6339 [(set (match_dup 3)
6340 (zero_extend:DI (subreg:QI
6341 (rotate:DI (match_dup 1)
6342 (match_dup 2)) 0)))
6343 (set (match_dup 0)
6344 (compare:CC (match_dup 3)
6345 (const_int 0)))]
6346 "")
6348 (define_insn "*rotldi3_internal9"
6349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6350 (compare:CC (zero_extend:DI
6351 (subreg:QI
6352 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6353 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6354 (const_int 0)))
6355 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6356 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6357 "TARGET_POWERPC64"
6358 "@
6359 rld%I2cl. %0,%1,%H2,56
6360 #"
6361 [(set_attr "type" "delayed_compare")
6362 (set_attr "length" "4,8")])
6364 (define_split
6365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6366 (compare:CC (zero_extend:DI
6367 (subreg:QI
6368 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6369 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6370 (const_int 0)))
6371 (set (match_operand:DI 0 "gpc_reg_operand" "")
6372 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6373 "TARGET_POWERPC64 && reload_completed"
6374 [(set (match_dup 0)
6375 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6376 (set (match_dup 3)
6377 (compare:CC (match_dup 0)
6378 (const_int 0)))]
6379 "")
6381 (define_insn "*rotldi3_internal10"
6382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6383 (zero_extend:DI
6384 (subreg:HI
6385 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6386 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6387 "TARGET_POWERPC64"
6388 "rld%I2cl %0,%1,%H2,48")
6390 (define_insn "*rotldi3_internal11"
6391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6392 (compare:CC (zero_extend:DI
6393 (subreg:HI
6394 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6395 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6396 (const_int 0)))
6397 (clobber (match_scratch:DI 3 "=r,r"))]
6398 "TARGET_POWERPC64"
6399 "@
6400 rld%I2cl. %3,%1,%H2,48
6401 #"
6402 [(set_attr "type" "delayed_compare")
6403 (set_attr "length" "4,8")])
6405 (define_split
6406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6407 (compare:CC (zero_extend:DI
6408 (subreg:HI
6409 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6410 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6411 (const_int 0)))
6412 (clobber (match_scratch:DI 3 ""))]
6413 "TARGET_POWERPC64 && reload_completed"
6414 [(set (match_dup 3)
6415 (zero_extend:DI (subreg:HI
6416 (rotate:DI (match_dup 1)
6417 (match_dup 2)) 0)))
6418 (set (match_dup 0)
6419 (compare:CC (match_dup 3)
6420 (const_int 0)))]
6421 "")
6423 (define_insn "*rotldi3_internal12"
6424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6425 (compare:CC (zero_extend:DI
6426 (subreg:HI
6427 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6428 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6429 (const_int 0)))
6430 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6431 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6432 "TARGET_POWERPC64"
6433 "@
6434 rld%I2cl. %0,%1,%H2,48
6435 #"
6436 [(set_attr "type" "delayed_compare")
6437 (set_attr "length" "4,8")])
6439 (define_split
6440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6441 (compare:CC (zero_extend:DI
6442 (subreg:HI
6443 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6444 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6445 (const_int 0)))
6446 (set (match_operand:DI 0 "gpc_reg_operand" "")
6447 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6448 "TARGET_POWERPC64 && reload_completed"
6449 [(set (match_dup 0)
6450 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6451 (set (match_dup 3)
6452 (compare:CC (match_dup 0)
6453 (const_int 0)))]
6454 "")
6456 (define_insn "*rotldi3_internal13"
6457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6458 (zero_extend:DI
6459 (subreg:SI
6460 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6461 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6462 "TARGET_POWERPC64"
6463 "rld%I2cl %0,%1,%H2,32")
6465 (define_insn "*rotldi3_internal14"
6466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6467 (compare:CC (zero_extend:DI
6468 (subreg:SI
6469 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6470 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6471 (const_int 0)))
6472 (clobber (match_scratch:DI 3 "=r,r"))]
6473 "TARGET_POWERPC64"
6474 "@
6475 rld%I2cl. %3,%1,%H2,32
6476 #"
6477 [(set_attr "type" "delayed_compare")
6478 (set_attr "length" "4,8")])
6480 (define_split
6481 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6482 (compare:CC (zero_extend:DI
6483 (subreg:SI
6484 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6485 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6486 (const_int 0)))
6487 (clobber (match_scratch:DI 3 ""))]
6488 "TARGET_POWERPC64 && reload_completed"
6489 [(set (match_dup 3)
6490 (zero_extend:DI (subreg:SI
6491 (rotate:DI (match_dup 1)
6492 (match_dup 2)) 0)))
6493 (set (match_dup 0)
6494 (compare:CC (match_dup 3)
6495 (const_int 0)))]
6496 "")
6498 (define_insn "*rotldi3_internal15"
6499 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6500 (compare:CC (zero_extend:DI
6501 (subreg:SI
6502 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6503 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6504 (const_int 0)))
6505 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6506 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6507 "TARGET_POWERPC64"
6508 "@
6509 rld%I2cl. %0,%1,%H2,32
6510 #"
6511 [(set_attr "type" "delayed_compare")
6512 (set_attr "length" "4,8")])
6514 (define_split
6515 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6516 (compare:CC (zero_extend:DI
6517 (subreg:SI
6518 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6519 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6520 (const_int 0)))
6521 (set (match_operand:DI 0 "gpc_reg_operand" "")
6522 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6523 "TARGET_POWERPC64 && reload_completed"
6524 [(set (match_dup 0)
6525 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6526 (set (match_dup 3)
6527 (compare:CC (match_dup 0)
6528 (const_int 0)))]
6529 "")
6531 (define_expand "ashldi3"
6532 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6533 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6534 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6535 "TARGET_POWERPC64 || TARGET_POWER"
6536 "
6537 {
6538 if (TARGET_POWERPC64)
6539 ;
6540 else if (TARGET_POWER)
6541 {
6542 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6543 DONE;
6544 }
6545 else
6546 FAIL;
6547 }")
6549 (define_insn "*ashldi3_internal1"
6550 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6551 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6552 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6553 "TARGET_POWERPC64"
6554 "sld%I2 %0,%1,%H2"
6555 [(set_attr "length" "8")])
6557 (define_insn "*ashldi3_internal2"
6558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6559 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6560 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6561 (const_int 0)))
6562 (clobber (match_scratch:DI 3 "=r,r"))]
6563 "TARGET_POWERPC64"
6564 "@
6565 sld%I2. %3,%1,%H2
6566 #"
6567 [(set_attr "type" "delayed_compare")
6568 (set_attr "length" "4,8")])
6570 (define_split
6571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6572 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6573 (match_operand:SI 2 "reg_or_cint_operand" ""))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 ""))]
6576 "TARGET_POWERPC64 && reload_completed"
6577 [(set (match_dup 3)
6578 (ashift:DI (match_dup 1) (match_dup 2)))
6579 (set (match_dup 0)
6580 (compare:CC (match_dup 3)
6581 (const_int 0)))]
6582 "")
6584 (define_insn "*ashldi3_internal3"
6585 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6586 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6587 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6588 (const_int 0)))
6589 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6590 (ashift:DI (match_dup 1) (match_dup 2)))]
6591 "TARGET_POWERPC64"
6592 "@
6593 sld%I2. %0,%1,%H2
6594 #"
6595 [(set_attr "type" "delayed_compare")
6596 (set_attr "length" "4,8")])
6598 (define_split
6599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6600 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6601 (match_operand:SI 2 "reg_or_cint_operand" ""))
6602 (const_int 0)))
6603 (set (match_operand:DI 0 "gpc_reg_operand" "")
6604 (ashift:DI (match_dup 1) (match_dup 2)))]
6605 "TARGET_POWERPC64 && reload_completed"
6606 [(set (match_dup 0)
6607 (ashift:DI (match_dup 1) (match_dup 2)))
6608 (set (match_dup 3)
6609 (compare:CC (match_dup 0)
6610 (const_int 0)))]
6611 "")
6613 (define_insn "*ashldi3_internal4"
6614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6615 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6616 (match_operand:SI 2 "const_int_operand" "i"))
6617 (match_operand:DI 3 "const_int_operand" "n")))]
6618 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6619 "rldic %0,%1,%H2,%W3")
6621 (define_insn "ashldi3_internal5"
6622 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6623 (compare:CC
6624 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6625 (match_operand:SI 2 "const_int_operand" "i,i"))
6626 (match_operand:DI 3 "const_int_operand" "n,n"))
6627 (const_int 0)))
6628 (clobber (match_scratch:DI 4 "=r,r"))]
6629 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6630 "@
6631 rldic. %4,%1,%H2,%W3
6632 #"
6633 [(set_attr "type" "delayed_compare")
6634 (set_attr "length" "4,8")])
6636 (define_split
6637 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6638 (compare:CC
6639 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6640 (match_operand:SI 2 "const_int_operand" ""))
6641 (match_operand:DI 3 "const_int_operand" ""))
6642 (const_int 0)))
6643 (clobber (match_scratch:DI 4 ""))]
6644 "TARGET_POWERPC64 && reload_completed
6645 && includes_rldic_lshift_p (operands[2], operands[3])"
6646 [(set (match_dup 4)
6647 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6648 (match_dup 3)))
6649 (set (match_dup 0)
6650 (compare:CC (match_dup 4)
6651 (const_int 0)))]
6652 "")
6654 (define_insn "*ashldi3_internal6"
6655 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6656 (compare:CC
6657 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6658 (match_operand:SI 2 "const_int_operand" "i,i"))
6659 (match_operand:DI 3 "const_int_operand" "n,n"))
6660 (const_int 0)))
6661 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6662 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6663 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6664 "@
6665 rldic. %0,%1,%H2,%W3
6666 #"
6667 [(set_attr "type" "delayed_compare")
6668 (set_attr "length" "4,8")])
6670 (define_split
6671 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6672 (compare:CC
6673 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:SI 2 "const_int_operand" ""))
6675 (match_operand:DI 3 "const_int_operand" ""))
6676 (const_int 0)))
6677 (set (match_operand:DI 0 "gpc_reg_operand" "")
6678 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6679 "TARGET_POWERPC64 && reload_completed
6680 && includes_rldic_lshift_p (operands[2], operands[3])"
6681 [(set (match_dup 0)
6682 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6683 (match_dup 3)))
6684 (set (match_dup 4)
6685 (compare:CC (match_dup 0)
6686 (const_int 0)))]
6687 "")
6689 (define_insn "*ashldi3_internal7"
6690 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6691 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6692 (match_operand:SI 2 "const_int_operand" "i"))
6693 (match_operand:DI 3 "mask64_operand" "n")))]
6694 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6695 "rldicr %0,%1,%H2,%S3")
6697 (define_insn "ashldi3_internal8"
6698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6699 (compare:CC
6700 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6701 (match_operand:SI 2 "const_int_operand" "i,i"))
6702 (match_operand:DI 3 "mask64_operand" "n,n"))
6703 (const_int 0)))
6704 (clobber (match_scratch:DI 4 "=r,r"))]
6705 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6706 "@
6707 rldicr. %4,%1,%H2,%S3
6708 #"
6709 [(set_attr "type" "delayed_compare")
6710 (set_attr "length" "4,8")])
6712 (define_split
6713 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6714 (compare:CC
6715 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6716 (match_operand:SI 2 "const_int_operand" ""))
6717 (match_operand:DI 3 "mask64_operand" ""))
6718 (const_int 0)))
6719 (clobber (match_scratch:DI 4 ""))]
6720 "TARGET_POWERPC64 && reload_completed
6721 && includes_rldicr_lshift_p (operands[2], operands[3])"
6722 [(set (match_dup 4)
6723 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6724 (match_dup 3)))
6725 (set (match_dup 0)
6726 (compare:CC (match_dup 4)
6727 (const_int 0)))]
6728 "")
6730 (define_insn "*ashldi3_internal9"
6731 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6732 (compare:CC
6733 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6734 (match_operand:SI 2 "const_int_operand" "i,i"))
6735 (match_operand:DI 3 "mask64_operand" "n,n"))
6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6738 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6739 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6740 "@
6741 rldicr. %0,%1,%H2,%S3
6742 #"
6743 [(set_attr "type" "delayed_compare")
6744 (set_attr "length" "4,8")])
6746 (define_split
6747 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6748 (compare:CC
6749 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6750 (match_operand:SI 2 "const_int_operand" ""))
6751 (match_operand:DI 3 "mask64_operand" ""))
6752 (const_int 0)))
6753 (set (match_operand:DI 0 "gpc_reg_operand" "")
6754 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6755 "TARGET_POWERPC64 && reload_completed
6756 && includes_rldicr_lshift_p (operands[2], operands[3])"
6757 [(set (match_dup 0)
6758 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6759 (match_dup 3)))
6760 (set (match_dup 4)
6761 (compare:CC (match_dup 0)
6762 (const_int 0)))]
6763 "")
6765 (define_expand "lshrdi3"
6766 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6767 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6768 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6769 "TARGET_POWERPC64 || TARGET_POWER"
6770 "
6771 {
6772 if (TARGET_POWERPC64)
6773 ;
6774 else if (TARGET_POWER)
6775 {
6776 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6777 DONE;
6778 }
6779 else
6780 FAIL;
6781 }")
6783 (define_insn "*lshrdi3_internal1"
6784 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6785 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6786 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6787 "TARGET_POWERPC64"
6788 "srd%I2 %0,%1,%H2")
6790 (define_insn "*lshrdi3_internal2"
6791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6792 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6793 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6794 (const_int 0)))
6795 (clobber (match_scratch:DI 3 "=r,r"))]
6796 "TARGET_POWERPC64"
6797 "@
6798 srd%I2. %3,%1,%H2
6799 #"
6800 [(set_attr "type" "delayed_compare")
6801 (set_attr "length" "4,8")])
6803 (define_split
6804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6805 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6806 (match_operand:SI 2 "reg_or_cint_operand" ""))
6807 (const_int 0)))
6808 (clobber (match_scratch:DI 3 ""))]
6809 "TARGET_POWERPC64 && reload_completed"
6810 [(set (match_dup 3)
6811 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6812 (set (match_dup 0)
6813 (compare:CC (match_dup 3)
6814 (const_int 0)))]
6815 "")
6817 (define_insn "*lshrdi3_internal3"
6818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6819 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6820 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6821 (const_int 0)))
6822 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6823 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6824 "TARGET_POWERPC64"
6825 "@
6826 srd%I2. %0,%1,%H2
6827 #"
6828 [(set_attr "type" "delayed_compare")
6829 (set_attr "length" "4,8")])
6831 (define_split
6832 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6833 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6834 (match_operand:SI 2 "reg_or_cint_operand" ""))
6835 (const_int 0)))
6836 (set (match_operand:DI 0 "gpc_reg_operand" "")
6837 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6838 "TARGET_POWERPC64 && reload_completed"
6839 [(set (match_dup 0)
6840 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6841 (set (match_dup 3)
6842 (compare:CC (match_dup 0)
6843 (const_int 0)))]
6844 "")
6846 (define_expand "ashrdi3"
6847 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6848 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6849 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6850 ""
6851 "
6852 {
6853 if (TARGET_POWERPC64)
6854 ;
6855 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6856 {
6857 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6858 DONE;
6859 }
6860 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
6861 {
6862 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6863 DONE;
6864 }
6865 else
6866 FAIL;
6867 }")
6869 (define_insn "*ashrdi3_internal1"
6870 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6871 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6872 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6873 "TARGET_POWERPC64"
6874 "srad%I2 %0,%1,%H2")
6876 (define_insn "*ashrdi3_internal2"
6877 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6878 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6879 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6880 (const_int 0)))
6881 (clobber (match_scratch:DI 3 "=r,r"))]
6882 "TARGET_POWERPC64"
6883 "@
6884 srad%I2. %3,%1,%H2
6885 #"
6886 [(set_attr "type" "delayed_compare")
6887 (set_attr "length" "4,8")])
6889 (define_split
6890 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6891 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6892 (match_operand:SI 2 "reg_or_cint_operand" ""))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 3 ""))]
6895 "TARGET_POWERPC64 && reload_completed"
6896 [(set (match_dup 3)
6897 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6898 (set (match_dup 0)
6899 (compare:CC (match_dup 3)
6900 (const_int 0)))]
6901 "")
6903 (define_insn "*ashrdi3_internal3"
6904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6905 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6906 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6907 (const_int 0)))
6908 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6909 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6910 "TARGET_POWERPC64"
6911 "@
6912 srad%I2. %0,%1,%H2
6913 #"
6914 [(set_attr "type" "delayed_compare")
6915 (set_attr "length" "4,8")])
6917 (define_split
6918 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6919 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6920 (match_operand:SI 2 "reg_or_cint_operand" ""))
6921 (const_int 0)))
6922 (set (match_operand:DI 0 "gpc_reg_operand" "")
6923 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6924 "TARGET_POWERPC64 && reload_completed"
6925 [(set (match_dup 0)
6926 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6927 (set (match_dup 3)
6928 (compare:CC (match_dup 0)
6929 (const_int 0)))]
6930 "")
6932 (define_insn "anddi3"
6933 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
6934 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
6935 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
6936 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
6937 "TARGET_POWERPC64"
6938 "@
6939 and %0,%1,%2
6940 rldic%B2 %0,%1,0,%S2
6941 andi. %0,%1,%b2
6942 andis. %0,%1,%u2
6943 #"
6944 [(set_attr "length" "4,4,4,4,8")])
6946 (define_split
6947 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6949 (match_operand:DI 2 "mask64_2_operand" "")))
6950 (clobber (match_scratch:CC 3 ""))]
6951 "TARGET_POWERPC64
6952 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6953 && !mask64_operand (operands[2], DImode)"
6954 [(set (match_dup 0)
6955 (and:DI (rotate:DI (match_dup 1)
6956 (match_dup 4))
6957 (match_dup 5)))
6958 (set (match_dup 0)
6959 (and:DI (rotate:DI (match_dup 0)
6960 (match_dup 6))
6961 (match_dup 7)))]
6962 "
6963 {
6964 build_mask64_2_operands (operands[2], &operands[4]);
6965 }")
6967 (define_insn "*anddi3_internal2"
6968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6969 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6970 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6971 (const_int 0)))
6972 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6973 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6974 "TARGET_POWERPC64"
6975 "@
6976 and. %3,%1,%2
6977 rldic%B2. %3,%1,0,%S2
6978 andi. %3,%1,%b2
6979 andis. %3,%1,%u2
6980 #
6981 #
6982 #
6983 #
6984 #
6985 #"
6986 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6987 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6989 (define_split
6990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6991 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "and64_operand" ""))
6993 (const_int 0)))
6994 (clobber (match_scratch:DI 3 ""))
6995 (clobber (match_scratch:CC 4 ""))]
6996 "TARGET_POWERPC64 && reload_completed"
6997 [(parallel [(set (match_dup 3)
6998 (and:DI (match_dup 1)
6999 (match_dup 2)))
7000 (clobber (match_dup 4))])
7001 (set (match_dup 0)
7002 (compare:CC (match_dup 3)
7003 (const_int 0)))]
7004 "")
7006 (define_split
7007 [(set (match_operand:CC 0 "cc_reg_operand" "")
7008 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7009 (match_operand:DI 2 "mask64_2_operand" ""))
7010 (const_int 0)))
7011 (clobber (match_scratch:DI 3 ""))
7012 (clobber (match_scratch:CC 4 ""))]
7013 "TARGET_POWERPC64 && reload_completed
7014 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7015 && !mask64_operand (operands[2], DImode)"
7016 [(set (match_dup 3)
7017 (and:DI (rotate:DI (match_dup 1)
7018 (match_dup 5))
7019 (match_dup 6)))
7020 (parallel [(set (match_dup 0)
7021 (compare:CC (and:DI (rotate:DI (match_dup 3)
7022 (match_dup 7))
7023 (match_dup 8))
7024 (const_int 0)))
7025 (clobber (match_dup 3))])]
7026 "
7027 {
7028 build_mask64_2_operands (operands[2], &operands[5]);
7029 }")
7031 (define_insn "*anddi3_internal3"
7032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7033 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7034 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7035 (const_int 0)))
7036 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7037 (and:DI (match_dup 1) (match_dup 2)))
7038 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7039 "TARGET_POWERPC64"
7040 "@
7041 and. %0,%1,%2
7042 rldic%B2. %0,%1,0,%S2
7043 andi. %0,%1,%b2
7044 andis. %0,%1,%u2
7045 #
7046 #
7047 #
7048 #
7049 #
7050 #"
7051 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7052 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7054 (define_split
7055 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7056 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7057 (match_operand:DI 2 "and64_operand" ""))
7058 (const_int 0)))
7059 (set (match_operand:DI 0 "gpc_reg_operand" "")
7060 (and:DI (match_dup 1) (match_dup 2)))
7061 (clobber (match_scratch:CC 4 ""))]
7062 "TARGET_POWERPC64 && reload_completed"
7063 [(parallel [(set (match_dup 0)
7064 (and:DI (match_dup 1) (match_dup 2)))
7065 (clobber (match_dup 4))])
7066 (set (match_dup 3)
7067 (compare:CC (match_dup 0)
7068 (const_int 0)))]
7069 "")
7071 (define_split
7072 [(set (match_operand:CC 3 "cc_reg_operand" "")
7073 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "mask64_2_operand" ""))
7075 (const_int 0)))
7076 (set (match_operand:DI 0 "gpc_reg_operand" "")
7077 (and:DI (match_dup 1) (match_dup 2)))
7078 (clobber (match_scratch:CC 4 ""))]
7079 "TARGET_POWERPC64 && reload_completed
7080 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7081 && !mask64_operand (operands[2], DImode)"
7082 [(set (match_dup 0)
7083 (and:DI (rotate:DI (match_dup 1)
7084 (match_dup 5))
7085 (match_dup 6)))
7086 (parallel [(set (match_dup 3)
7087 (compare:CC (and:DI (rotate:DI (match_dup 0)
7088 (match_dup 7))
7089 (match_dup 8))
7090 (const_int 0)))
7091 (set (match_dup 0)
7092 (and:DI (rotate:DI (match_dup 0)
7093 (match_dup 7))
7094 (match_dup 8)))])]
7095 "
7096 {
7097 build_mask64_2_operands (operands[2], &operands[5]);
7098 }")
7100 (define_expand "iordi3"
7101 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7102 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7103 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7104 "TARGET_POWERPC64"
7105 "
7106 {
7107 if (non_logical_cint_operand (operands[2], DImode))
7108 {
7109 HOST_WIDE_INT value;
7110 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7111 ? operands[0] : gen_reg_rtx (DImode));
7113 if (GET_CODE (operands[2]) == CONST_INT)
7114 {
7115 value = INTVAL (operands[2]);
7116 emit_insn (gen_iordi3 (tmp, operands[1],
7117 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7118 }
7119 else
7120 {
7121 value = CONST_DOUBLE_LOW (operands[2]);
7122 emit_insn (gen_iordi3 (tmp, operands[1],
7123 immed_double_const (value
7124 & (~ (HOST_WIDE_INT) 0xffff),
7125 0, DImode)));
7126 }
7128 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7129 DONE;
7130 }
7131 }")
7133 (define_expand "xordi3"
7134 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7135 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7136 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7137 "TARGET_POWERPC64"
7138 "
7139 {
7140 if (non_logical_cint_operand (operands[2], DImode))
7141 {
7142 HOST_WIDE_INT value;
7143 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7144 ? operands[0] : gen_reg_rtx (DImode));
7146 if (GET_CODE (operands[2]) == CONST_INT)
7147 {
7148 value = INTVAL (operands[2]);
7149 emit_insn (gen_xordi3 (tmp, operands[1],
7150 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7151 }
7152 else
7153 {
7154 value = CONST_DOUBLE_LOW (operands[2]);
7155 emit_insn (gen_xordi3 (tmp, operands[1],
7156 immed_double_const (value
7157 & (~ (HOST_WIDE_INT) 0xffff),
7158 0, DImode)));
7159 }
7161 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7162 DONE;
7163 }
7164 }")
7166 (define_insn "*booldi3_internal1"
7167 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7168 (match_operator:DI 3 "boolean_or_operator"
7169 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7170 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7171 "TARGET_POWERPC64"
7172 "@
7173 %q3 %0,%1,%2
7174 %q3i %0,%1,%b2
7175 %q3is %0,%1,%u2")
7177 (define_insn "*booldi3_internal2"
7178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7179 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7180 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7181 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7182 (const_int 0)))
7183 (clobber (match_scratch:DI 3 "=r,r"))]
7184 "TARGET_POWERPC64"
7185 "@
7186 %q4. %3,%1,%2
7187 #"
7188 [(set_attr "type" "compare")
7189 (set_attr "length" "4,8")])
7191 (define_split
7192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7193 (compare:CC (match_operator:DI 4 "boolean_operator"
7194 [(match_operand:DI 1 "gpc_reg_operand" "")
7195 (match_operand:DI 2 "gpc_reg_operand" "")])
7196 (const_int 0)))
7197 (clobber (match_scratch:DI 3 ""))]
7198 "TARGET_POWERPC64 && reload_completed"
7199 [(set (match_dup 3) (match_dup 4))
7200 (set (match_dup 0)
7201 (compare:CC (match_dup 3)
7202 (const_int 0)))]
7203 "")
7205 (define_insn "*booldi3_internal3"
7206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7207 (compare:CC (match_operator:DI 4 "boolean_operator"
7208 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7209 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7210 (const_int 0)))
7211 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7212 (match_dup 4))]
7213 "TARGET_POWERPC64"
7214 "@
7215 %q4. %0,%1,%2
7216 #"
7217 [(set_attr "type" "compare")
7218 (set_attr "length" "4,8")])
7220 (define_split
7221 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7222 (compare:CC (match_operator:DI 4 "boolean_operator"
7223 [(match_operand:DI 1 "gpc_reg_operand" "")
7224 (match_operand:DI 2 "gpc_reg_operand" "")])
7225 (const_int 0)))
7226 (set (match_operand:DI 0 "gpc_reg_operand" "")
7227 (match_dup 4))]
7228 "TARGET_POWERPC64 && reload_completed"
7229 [(set (match_dup 0) (match_dup 4))
7230 (set (match_dup 3)
7231 (compare:CC (match_dup 0)
7232 (const_int 0)))]
7233 "")
7235 ;; Split a logical operation that we can't do in one insn into two insns,
7236 ;; each of which does one 16-bit part. This is used by combine.
7238 (define_split
7239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7240 (match_operator:DI 3 "boolean_or_operator"
7241 [(match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7243 "TARGET_POWERPC64"
7244 [(set (match_dup 0) (match_dup 4))
7245 (set (match_dup 0) (match_dup 5))]
7246 "
7247 {
7248 rtx i3,i4;
7250 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7251 {
7252 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7253 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7254 0, DImode);
7255 i4 = GEN_INT (value & 0xffff);
7256 }
7257 else
7258 {
7259 i3 = GEN_INT (INTVAL (operands[2])
7260 & (~ (HOST_WIDE_INT) 0xffff));
7261 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7262 }
7263 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7264 operands[1], i3);
7265 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7266 operands[0], i4);
7267 }")
7269 (define_insn "*boolcdi3_internal1"
7270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7271 (match_operator:DI 3 "boolean_operator"
7272 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7273 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7274 "TARGET_POWERPC64"
7275 "%q3 %0,%2,%1")
7277 (define_insn "*boolcdi3_internal2"
7278 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7279 (compare:CC (match_operator:DI 4 "boolean_operator"
7280 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7281 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7282 (const_int 0)))
7283 (clobber (match_scratch:DI 3 "=r,r"))]
7284 "TARGET_POWERPC64"
7285 "@
7286 %q4. %3,%2,%1
7287 #"
7288 [(set_attr "type" "compare")
7289 (set_attr "length" "4,8")])
7291 (define_split
7292 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7293 (compare:CC (match_operator:DI 4 "boolean_operator"
7294 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7295 (match_operand:DI 2 "gpc_reg_operand" "")])
7296 (const_int 0)))
7297 (clobber (match_scratch:DI 3 ""))]
7298 "TARGET_POWERPC64 && reload_completed"
7299 [(set (match_dup 3) (match_dup 4))
7300 (set (match_dup 0)
7301 (compare:CC (match_dup 3)
7302 (const_int 0)))]
7303 "")
7305 (define_insn "*boolcdi3_internal3"
7306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7307 (compare:CC (match_operator:DI 4 "boolean_operator"
7308 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7309 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7310 (const_int 0)))
7311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7312 (match_dup 4))]
7313 "TARGET_POWERPC64"
7314 "@
7315 %q4. %0,%2,%1
7316 #"
7317 [(set_attr "type" "compare")
7318 (set_attr "length" "4,8")])
7320 (define_split
7321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7322 (compare:CC (match_operator:DI 4 "boolean_operator"
7323 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7324 (match_operand:DI 2 "gpc_reg_operand" "")])
7325 (const_int 0)))
7326 (set (match_operand:DI 0 "gpc_reg_operand" "")
7327 (match_dup 4))]
7328 "TARGET_POWERPC64 && reload_completed"
7329 [(set (match_dup 0) (match_dup 4))
7330 (set (match_dup 3)
7331 (compare:CC (match_dup 0)
7332 (const_int 0)))]
7333 "")
7335 (define_insn "*boolccdi3_internal1"
7336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7337 (match_operator:DI 3 "boolean_operator"
7338 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7339 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7340 "TARGET_POWERPC64"
7341 "%q3 %0,%1,%2")
7343 (define_insn "*boolccdi3_internal2"
7344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7345 (compare:CC (match_operator:DI 4 "boolean_operator"
7346 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7347 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7348 (const_int 0)))
7349 (clobber (match_scratch:DI 3 "=r,r"))]
7350 "TARGET_POWERPC64"
7351 "@
7352 %q4. %3,%1,%2
7353 #"
7354 [(set_attr "type" "compare")
7355 (set_attr "length" "4,8")])
7357 (define_split
7358 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7359 (compare:CC (match_operator:DI 4 "boolean_operator"
7360 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7361 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7362 (const_int 0)))
7363 (clobber (match_scratch:DI 3 ""))]
7364 "TARGET_POWERPC64 && reload_completed"
7365 [(set (match_dup 3) (match_dup 4))
7366 (set (match_dup 0)
7367 (compare:CC (match_dup 3)
7368 (const_int 0)))]
7369 "")
7371 (define_insn "*boolccdi3_internal3"
7372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7373 (compare:CC (match_operator:DI 4 "boolean_operator"
7374 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7375 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7376 (const_int 0)))
7377 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7378 (match_dup 4))]
7379 "TARGET_POWERPC64"
7380 "@
7381 %q4. %0,%1,%2
7382 #"
7383 [(set_attr "type" "compare")
7384 (set_attr "length" "4,8")])
7386 (define_split
7387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7388 (compare:CC (match_operator:DI 4 "boolean_operator"
7389 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7390 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7391 (const_int 0)))
7392 (set (match_operand:DI 0 "gpc_reg_operand" "")
7393 (match_dup 4))]
7394 "TARGET_POWERPC64 && reload_completed"
7395 [(set (match_dup 0) (match_dup 4))
7396 (set (match_dup 3)
7397 (compare:CC (match_dup 0)
7398 (const_int 0)))]
7399 "")
7400 \f
7401 ;; Now define ways of moving data around.
7403 ;; Elf specific ways of loading addresses for non-PIC code.
7404 ;; The output of this could be r0, but we make a very strong
7405 ;; preference for a base register because it will usually
7406 ;; be needed there.
7407 (define_insn "elf_high"
7408 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7409 (high:SI (match_operand 1 "" "")))]
7410 "TARGET_ELF && ! TARGET_64BIT"
7411 "{liu|lis} %0,%1@ha")
7413 (define_insn "elf_low"
7414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7415 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7416 (match_operand 2 "" "")))]
7417 "TARGET_ELF && ! TARGET_64BIT"
7418 "@
7419 {cal|la} %0,%2@l(%1)
7420 {ai|addic} %0,%1,%K2")
7422 ;; Mach-O PIC trickery.
7423 (define_insn "macho_high"
7424 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7425 (high:SI (match_operand 1 "" "")))]
7426 "TARGET_MACHO && ! TARGET_64BIT"
7427 "{liu|lis} %0,ha16(%1)")
7429 (define_insn "macho_low"
7430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7431 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7432 (match_operand 2 "" "")))]
7433 "TARGET_MACHO && ! TARGET_64BIT"
7434 "@
7435 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7436 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7438 ;; Set up a register with a value from the GOT table
7440 (define_expand "movsi_got"
7441 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7442 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7443 (match_dup 2)] 8))]
7444 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7445 "
7446 {
7447 if (GET_CODE (operands[1]) == CONST)
7448 {
7449 rtx offset = const0_rtx;
7450 HOST_WIDE_INT value;
7452 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7453 value = INTVAL (offset);
7454 if (value != 0)
7455 {
7456 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7457 emit_insn (gen_movsi_got (tmp, operands[1]));
7458 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7459 DONE;
7460 }
7461 }
7463 operands[2] = rs6000_got_register (operands[1]);
7464 }")
7466 (define_insn "*movsi_got_internal"
7467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7468 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7469 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
7470 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7471 "{l|lwz} %0,%a1@got(%2)"
7472 [(set_attr "type" "load")])
7474 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7475 ;; didn't get allocated to a hard register.
7476 (define_split
7477 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7478 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7479 (match_operand:SI 2 "memory_operand" "")] 8))]
7480 "DEFAULT_ABI == ABI_V4
7481 && flag_pic == 1
7482 && (reload_in_progress || reload_completed)"
7483 [(set (match_dup 0) (match_dup 2))
7484 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
7485 "")
7487 ;; For SI, we special-case integers that can't be loaded in one insn. We
7488 ;; do the load 16-bits at a time. We could do this by loading from memory,
7489 ;; and this is even supposed to be faster, but it is simpler not to get
7490 ;; integers in the TOC.
7491 (define_expand "movsi"
7492 [(set (match_operand:SI 0 "general_operand" "")
7493 (match_operand:SI 1 "any_operand" ""))]
7494 ""
7495 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7497 (define_insn "movsi_low"
7498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7499 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7500 (match_operand 2 "" ""))))]
7501 "TARGET_MACHO && ! TARGET_64BIT"
7502 "{l|lwz} %0,lo16(%2)(%1)"
7503 [(set_attr "type" "load")
7504 (set_attr "length" "4")])
7506 (define_insn "movsi_low_st"
7507 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7508 (match_operand 2 "" "")))
7509 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7510 "TARGET_MACHO && ! TARGET_64BIT"
7511 "{st|stw} %0,lo16(%2)(%1)"
7512 [(set_attr "type" "store")
7513 (set_attr "length" "4")])
7515 (define_insn "movdf_low"
7516 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7517 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7518 (match_operand 2 "" ""))))]
7519 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7520 "*
7521 {
7522 switch (which_alternative)
7523 {
7524 case 0:
7525 return \"lfd %0,lo16(%2)(%1)\";
7526 case 1:
7527 {
7528 rtx operands2[4];
7529 operands2[0] = operands[0];
7530 operands2[1] = operands[1];
7531 operands2[2] = operands[2];
7532 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7533 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7534 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7535 although in practice it almost always is. */
7536 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7537 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7538 }
7539 default:
7540 abort();
7541 }
7542 }"
7543 [(set_attr "type" "load")
7544 (set_attr "length" "4,12")])
7546 (define_insn "movdf_low_st"
7547 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7548 (match_operand 2 "" "")))
7549 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7550 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7551 "stfd %0,lo16(%2)(%1)"
7552 [(set_attr "type" "store")
7553 (set_attr "length" "4")])
7555 (define_insn "movsf_low"
7556 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7557 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7558 (match_operand 2 "" ""))))]
7559 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7560 "@
7561 lfs %0,lo16(%2)(%1)
7562 {l|lwz} %0,lo16(%2)(%1)"
7563 [(set_attr "type" "load")
7564 (set_attr "length" "4")])
7566 (define_insn "movsf_low_st"
7567 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7568 (match_operand 2 "" "")))
7569 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7570 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7571 "@
7572 stfs %0,lo16(%2)(%1)
7573 {st|stw} %0,lo16(%2)(%1)"
7574 [(set_attr "type" "store")
7575 (set_attr "length" "4")])
7577 (define_insn "*movsi_internal1"
7578 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7579 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7580 "gpc_reg_operand (operands[0], SImode)
7581 || gpc_reg_operand (operands[1], SImode)"
7582 "@
7583 mr %0,%1
7584 {cal|la} %0,%a1
7585 {l%U1%X1|lwz%U1%X1} %0,%1
7586 {st%U0%X0|stw%U0%X0} %1,%0
7587 {lil|li} %0,%1
7588 {liu|lis} %0,%v1
7589 #
7590 {cal|la} %0,%a1
7591 mf%1 %0
7592 mt%0 %1
7593 mt%0 %1
7594 mt%0 %1
7595 {cror 0,0,0|nop}"
7596 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
7597 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7599 ;; Split a load of a large constant into the appropriate two-insn
7600 ;; sequence.
7602 (define_split
7603 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7604 (match_operand:SI 1 "const_int_operand" ""))]
7605 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7606 && (INTVAL (operands[1]) & 0xffff) != 0"
7607 [(set (match_dup 0)
7608 (match_dup 2))
7609 (set (match_dup 0)
7610 (ior:SI (match_dup 0)
7611 (match_dup 3)))]
7612 "
7613 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7615 if (tem == operands[0])
7616 DONE;
7617 else
7618 FAIL;
7619 }")
7621 (define_insn "*movsi_internal2"
7622 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7623 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
7624 (const_int 0)))
7625 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
7626 "! TARGET_POWERPC64"
7627 "@
7628 mr. %0,%1
7629 #"
7630 [(set_attr "type" "compare")
7631 (set_attr "length" "4,8")])
7632 \f
7633 (define_split
7634 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7635 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7636 (const_int 0)))
7637 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7638 "! TARGET_POWERPC64 && reload_completed"
7639 [(set (match_dup 0) (match_dup 1))
7640 (set (match_dup 2)
7641 (compare:CC (match_dup 0)
7642 (const_int 0)))]
7643 "")
7645 (define_expand "movhi"
7646 [(set (match_operand:HI 0 "general_operand" "")
7647 (match_operand:HI 1 "any_operand" ""))]
7648 ""
7649 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7651 (define_insn "*movhi_internal"
7652 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7653 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7654 "gpc_reg_operand (operands[0], HImode)
7655 || gpc_reg_operand (operands[1], HImode)"
7656 "@
7657 mr %0,%1
7658 lhz%U1%X1 %0,%1
7659 sth%U0%X0 %1,%0
7660 {lil|li} %0,%w1
7661 mf%1 %0
7662 mt%0 %1
7663 mt%0 %1
7664 {cror 0,0,0|nop}"
7665 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7667 (define_expand "movqi"
7668 [(set (match_operand:QI 0 "general_operand" "")
7669 (match_operand:QI 1 "any_operand" ""))]
7670 ""
7671 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7673 (define_insn "*movqi_internal"
7674 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7675 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7676 "gpc_reg_operand (operands[0], QImode)
7677 || gpc_reg_operand (operands[1], QImode)"
7678 "@
7679 mr %0,%1
7680 lbz%U1%X1 %0,%1
7681 stb%U0%X0 %1,%0
7682 {lil|li} %0,%1
7683 mf%1 %0
7684 mt%0 %1
7685 mt%0 %1
7686 {cror 0,0,0|nop}"
7687 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7688 \f
7689 ;; Here is how to move condition codes around. When we store CC data in
7690 ;; an integer register or memory, we store just the high-order 4 bits.
7691 ;; This lets us not shift in the most common case of CR0.
7692 (define_expand "movcc"
7693 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7694 (match_operand:CC 1 "nonimmediate_operand" ""))]
7695 ""
7696 "")
7698 (define_insn "*movcc_internal1"
7699 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7700 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7701 "register_operand (operands[0], CCmode)
7702 || register_operand (operands[1], CCmode)"
7703 "@
7704 mcrf %0,%1
7705 mtcrf 128,%1
7706 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7707 mfcr %0
7708 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7709 mr %0,%1
7710 mf%1 %0
7711 mt%0 %1
7712 mt%0 %1
7713 {l%U1%X1|lwz%U1%X1} %0,%1
7714 {st%U0%U1|stw%U0%U1} %1,%0"
7715 [(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,*,*,mtjmpr,load,store")
7716 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7717 \f
7718 ;; For floating-point, we normally deal with the floating-point registers
7719 ;; unless -msoft-float is used. The sole exception is that parameter passing
7720 ;; can produce floating-point values in fixed-point registers. Unless the
7721 ;; value is a simple constant or already in memory, we deal with this by
7722 ;; allocating memory and copying the value explicitly via that memory location.
7723 (define_expand "movsf"
7724 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7725 (match_operand:SF 1 "any_operand" ""))]
7726 ""
7727 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7729 (define_split
7730 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7731 (match_operand:SF 1 "const_double_operand" ""))]
7732 "reload_completed
7733 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7734 || (GET_CODE (operands[0]) == SUBREG
7735 && GET_CODE (SUBREG_REG (operands[0])) == REG
7736 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7737 [(set (match_dup 2) (match_dup 3))]
7738 "
7739 {
7740 long l;
7741 REAL_VALUE_TYPE rv;
7743 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7744 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7746 if (! TARGET_POWERPC64)
7747 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7748 else
7749 operands[2] = gen_lowpart (SImode, operands[0]);
7751 operands[3] = gen_int_mode (l, SImode);
7752 }")
7754 (define_insn "*movsf_hardfloat"
7755 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7756 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
7757 "(gpc_reg_operand (operands[0], SFmode)
7758 || gpc_reg_operand (operands[1], SFmode))
7759 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7760 "@
7761 mr %0,%1
7762 {l%U1%X1|lwz%U1%X1} %0,%1
7763 {st%U0%X0|stw%U0%X0} %1,%0
7764 fmr %0,%1
7765 lfs%U1%X1 %0,%1
7766 stfs%U0%X0 %1,%0
7767 mt%0 %1
7768 mt%0 %1
7769 mf%1 %0
7770 #
7771 #"
7772 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7773 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7775 (define_insn "*movsf_softfloat"
7776 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r")
7777 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))]
7778 "(gpc_reg_operand (operands[0], SFmode)
7779 || gpc_reg_operand (operands[1], SFmode))
7780 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7781 "@
7782 mr %0,%1
7783 mt%0 %1
7784 mt%0 %1
7785 mf%1 %0
7786 {l%U1%X1|lwz%U1%X1} %0,%1
7787 {st%U0%X0|stw%U0%X0} %1,%0
7788 {lil|li} %0,%1
7789 {liu|lis} %0,%v1
7790 {cal|la} %0,%a1
7791 #
7792 #"
7793 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*")
7794 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7796 \f
7797 (define_expand "movdf"
7798 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7799 (match_operand:DF 1 "any_operand" ""))]
7800 ""
7801 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7803 (define_split
7804 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7805 (match_operand:DF 1 "const_int_operand" ""))]
7806 "! TARGET_POWERPC64 && reload_completed
7807 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7808 || (GET_CODE (operands[0]) == SUBREG
7809 && GET_CODE (SUBREG_REG (operands[0])) == REG
7810 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7811 [(set (match_dup 2) (match_dup 4))
7812 (set (match_dup 3) (match_dup 1))]
7813 "
7814 {
7815 int endian = (WORDS_BIG_ENDIAN == 0);
7816 HOST_WIDE_INT value = INTVAL (operands[1]);
7818 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7819 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7820 #if HOST_BITS_PER_WIDE_INT == 32
7821 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7822 #else
7823 operands[4] = GEN_INT (value >> 32);
7824 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7825 #endif
7826 }")
7828 (define_split
7829 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7830 (match_operand:DF 1 "const_double_operand" ""))]
7831 "! TARGET_POWERPC64 && reload_completed
7832 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7833 || (GET_CODE (operands[0]) == SUBREG
7834 && GET_CODE (SUBREG_REG (operands[0])) == REG
7835 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7836 [(set (match_dup 2) (match_dup 4))
7837 (set (match_dup 3) (match_dup 5))]
7838 "
7839 {
7840 int endian = (WORDS_BIG_ENDIAN == 0);
7841 long l[2];
7842 REAL_VALUE_TYPE rv;
7844 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7845 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7847 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7848 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7849 operands[4] = gen_int_mode (l[endian], SImode);
7850 operands[5] = gen_int_mode (l[1 - endian], SImode);
7851 }")
7853 (define_split
7854 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7855 (match_operand:DF 1 "easy_fp_constant" ""))]
7856 "TARGET_POWERPC64 && reload_completed
7857 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7858 || (GET_CODE (operands[0]) == SUBREG
7859 && GET_CODE (SUBREG_REG (operands[0])) == REG
7860 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7861 [(set (match_dup 2) (match_dup 3))]
7862 "
7863 {
7864 int endian = (WORDS_BIG_ENDIAN == 0);
7865 long l[2];
7866 REAL_VALUE_TYPE rv;
7867 #if HOST_BITS_PER_WIDE_INT >= 64
7868 HOST_WIDE_INT val;
7869 #endif
7871 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7872 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7874 operands[2] = gen_lowpart (DImode, operands[0]);
7875 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7876 #if HOST_BITS_PER_WIDE_INT >= 64
7877 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7878 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7880 operands[3] = gen_int_mode (val, DImode);
7881 #else
7882 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7883 #endif
7884 }")
7886 ;; Don't have reload use general registers to load a constant. First,
7887 ;; it might not work if the output operand is the equivalent of
7888 ;; a non-offsettable memref, but also it is less efficient than loading
7889 ;; the constant into an FP register, since it will probably be used there.
7890 ;; The "??" is a kludge until we can figure out a more reasonable way
7891 ;; of handling these non-offsettable values.
7892 (define_insn "*movdf_hardfloat32"
7893 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7894 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7895 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7896 && (gpc_reg_operand (operands[0], DFmode)
7897 || gpc_reg_operand (operands[1], DFmode))"
7898 "*
7899 {
7900 switch (which_alternative)
7901 {
7902 default:
7903 abort ();
7904 case 0:
7905 /* We normally copy the low-numbered register first. However, if
7906 the first register operand 0 is the same as the second register
7907 of operand 1, we must copy in the opposite order. */
7908 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7909 return \"mr %L0,%L1\;mr %0,%1\";
7910 else
7911 return \"mr %0,%1\;mr %L0,%L1\";
7912 case 1:
7913 if (offsettable_memref_p (operands[1])
7914 || (GET_CODE (operands[1]) == MEM
7915 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7916 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7917 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
7918 {
7919 /* If the low-address word is used in the address, we must load
7920 it last. Otherwise, load it first. Note that we cannot have
7921 auto-increment in that case since the address register is
7922 known to be dead. */
7923 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7924 operands[1], 0))
7925 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7926 else
7927 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7928 }
7929 else
7930 {
7931 rtx addreg;
7933 addreg = find_addr_reg (XEXP (operands[1], 0));
7934 if (refers_to_regno_p (REGNO (operands[0]),
7935 REGNO (operands[0]) + 1,
7936 operands[1], 0))
7937 {
7938 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7939 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7940 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7941 return \"{lx|lwzx} %0,%1\";
7942 }
7943 else
7944 {
7945 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7946 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7947 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7948 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7949 return \"\";
7950 }
7951 }
7952 case 2:
7953 if (offsettable_memref_p (operands[0])
7954 || (GET_CODE (operands[0]) == MEM
7955 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7956 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7957 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
7958 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7959 else
7960 {
7961 rtx addreg;
7963 addreg = find_addr_reg (XEXP (operands[0], 0));
7964 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7965 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7966 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7967 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7968 return \"\";
7969 }
7970 case 3:
7971 return \"fmr %0,%1\";
7972 case 4:
7973 return \"lfd%U1%X1 %0,%1\";
7974 case 5:
7975 return \"stfd%U0%X0 %1,%0\";
7976 case 6:
7977 case 7:
7978 case 8:
7979 return \"#\";
7980 }
7981 }"
7982 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
7983 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7985 (define_insn "*movdf_softfloat32"
7986 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7987 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7988 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7989 && (gpc_reg_operand (operands[0], DFmode)
7990 || gpc_reg_operand (operands[1], DFmode))"
7991 "*
7992 {
7993 switch (which_alternative)
7994 {
7995 default:
7996 abort ();
7997 case 0:
7998 /* We normally copy the low-numbered register first. However, if
7999 the first register operand 0 is the same as the second register of
8000 operand 1, we must copy in the opposite order. */
8001 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8002 return \"mr %L0,%L1\;mr %0,%1\";
8003 else
8004 return \"mr %0,%1\;mr %L0,%L1\";
8005 case 1:
8006 /* If the low-address word is used in the address, we must load
8007 it last. Otherwise, load it first. Note that we cannot have
8008 auto-increment in that case since the address register is
8009 known to be dead. */
8010 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8011 operands[1], 0))
8012 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8013 else
8014 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8015 case 2:
8016 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8017 case 3:
8018 case 4:
8019 case 5:
8020 return \"#\";
8021 }
8022 }"
8023 [(set_attr "type" "*,load,store,*,*,*")
8024 (set_attr "length" "8,8,8,8,12,16")])
8026 (define_insn "*movdf_hardfloat64"
8027 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
8028 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
8029 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8030 && (gpc_reg_operand (operands[0], DFmode)
8031 || gpc_reg_operand (operands[1], DFmode))"
8032 "@
8033 mr %0,%1
8034 ld%U1%X1 %0,%1
8035 std%U0%X0 %1,%0
8036 fmr %0,%1
8037 lfd%U1%X1 %0,%1
8038 stfd%U0%X0 %1,%0
8039 mt%0 %1
8040 mf%1 %0
8041 #
8042 #
8043 #"
8044 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8045 (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
8047 (define_insn "*movdf_softfloat64"
8048 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r")
8049 (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))]
8050 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8051 && (gpc_reg_operand (operands[0], DFmode)
8052 || gpc_reg_operand (operands[1], DFmode))"
8053 "@
8054 mr %0,%1
8055 mt%0 %1
8056 mf%1 %0
8057 ld%U1%X1 %0,%1
8058 std%U0%X0 %1,%0
8059 #
8060 #
8061 #"
8062 [(set_attr "type" "*,*,*,load,store,*,*,*")
8063 (set_attr "length" "4,4,4,4,4,8,12,16")])
8064 \f
8065 (define_expand "movtf"
8066 [(set (match_operand:TF 0 "general_operand" "")
8067 (match_operand:TF 1 "any_operand" ""))]
8068 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8069 && TARGET_LONG_DOUBLE_128"
8070 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8072 (define_insn "*movtf_internal"
8073 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r")
8074 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))]
8075 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8076 && TARGET_LONG_DOUBLE_128
8077 && (gpc_reg_operand (operands[0], TFmode)
8078 || gpc_reg_operand (operands[1], TFmode))"
8079 "*
8080 {
8081 switch (which_alternative)
8082 {
8083 default:
8084 abort ();
8085 case 0:
8086 /* We normally copy the low-numbered register first. However, if
8087 the first register operand 0 is the same as the second register of
8088 operand 1, we must copy in the opposite order. */
8089 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8090 return \"fmr %L0,%L1\;fmr %0,%1\";
8091 else
8092 return \"fmr %0,%1\;fmr %L0,%L1\";
8093 case 1:
8094 return \"lfd %0,%1\;lfd %L0,%Y1\";
8095 case 2:
8096 return \"stfd %1,%0\;stfd %L1,%Y0\";
8097 case 3:
8098 case 4:
8099 case 5:
8100 return \"#\";
8101 }
8102 }"
8103 [(set_attr "type" "fp,fpload,fpstore,*,*,*")
8104 (set_attr "length" "8,8,8,12,16,20")])
8106 (define_split
8107 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8108 (match_operand:TF 1 "easy_fp_constant" ""))]
8109 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8110 && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64
8111 && TARGET_LONG_DOUBLE_128 && reload_completed
8112 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8113 || (GET_CODE (operands[0]) == SUBREG
8114 && GET_CODE (SUBREG_REG (operands[0])) == REG
8115 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8116 [(set (match_dup 2) (match_dup 6))
8117 (set (match_dup 3) (match_dup 7))
8118 (set (match_dup 4) (match_dup 8))
8119 (set (match_dup 5) (match_dup 9))]
8120 "
8121 {
8122 long l[4];
8123 REAL_VALUE_TYPE rv;
8125 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8126 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8128 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
8129 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
8130 operands[4] = operand_subword (operands[0], 2, 0, TFmode);
8131 operands[5] = operand_subword (operands[0], 3, 0, TFmode);
8132 operands[6] = gen_int_mode (l[0], SImode);
8133 operands[7] = gen_int_mode (l[1], SImode);
8134 operands[8] = gen_int_mode (l[2], SImode);
8135 operands[9] = gen_int_mode (l[3], SImode);
8136 }")
8138 (define_split
8139 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8140 (match_operand:TF 1 "easy_fp_constant" ""))]
8141 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8142 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8143 && TARGET_LONG_DOUBLE_128 && reload_completed
8144 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8145 || (GET_CODE (operands[0]) == SUBREG
8146 && GET_CODE (SUBREG_REG (operands[0])) == REG
8147 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8148 [(set (match_dup 2) (match_dup 4))
8149 (set (match_dup 3) (match_dup 5))]
8150 "
8151 {
8152 long l[4];
8153 REAL_VALUE_TYPE rv;
8154 #if HOST_BITS_PER_WIDE_INT >= 64
8155 HOST_WIDE_INT val;
8156 #endif
8158 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8159 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8161 operands[2] = gen_lowpart (DImode, operands[0]);
8162 operands[3] = gen_highpart (DImode, operands[0]);
8163 #if HOST_BITS_PER_WIDE_INT >= 64
8164 val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
8165 | ((HOST_WIDE_INT)(unsigned long)l[1]));
8166 operands[4] = gen_int_mode (val, DImode);
8168 val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
8169 | ((HOST_WIDE_INT)(unsigned long)l[3]));
8170 operands[5] = gen_int_mode (val, DImode);
8171 #else
8172 operands[4] = immed_double_const (l[1], l[0], DImode);
8173 operands[5] = immed_double_const (l[3], l[2], DImode);
8174 #endif
8175 }")
8177 (define_insn "extenddftf2"
8178 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8179 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
8180 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8181 && TARGET_LONG_DOUBLE_128"
8182 "*
8183 {
8184 if (REGNO (operands[0]) == REGNO (operands[1]))
8185 return \"fsub %L0,%L0,%L0\";
8186 else
8187 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8188 }"
8189 [(set_attr "type" "fp")])
8191 (define_insn "extendsftf2"
8192 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8193 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
8194 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8195 && TARGET_LONG_DOUBLE_128"
8196 "*
8197 {
8198 if (REGNO (operands[0]) == REGNO (operands[1]))
8199 return \"fsub %L0,%L0,%L0\";
8200 else
8201 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8202 }"
8203 [(set_attr "type" "fp")])
8205 (define_insn "trunctfdf2"
8206 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8207 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8208 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8209 && TARGET_LONG_DOUBLE_128"
8210 "fadd %0,%1,%L1"
8211 [(set_attr "type" "fp")
8212 (set_attr "length" "8")])
8214 (define_insn_and_split "trunctfsf2"
8215 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8216 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8217 (clobber (match_scratch:DF 2 "=f"))]
8218 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
8219 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8220 "#"
8221 "&& reload_completed"
8222 [(set (match_dup 2)
8223 (float_truncate:DF (match_dup 1)))
8224 (set (match_dup 0)
8225 (float_truncate:SF (match_dup 2)))]
8226 "")
8228 (define_insn_and_split "floatditf2"
8229 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8230 (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
8231 (clobber (match_scratch:DF 2 "=f"))]
8232 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8234 "#"
8235 "&& reload_completed"
8236 [(set (match_dup 2)
8237 (float:DF (match_dup 1)))
8238 (set (match_dup 0)
8239 (float_extend:TF (match_dup 2)))]
8240 "")
8242 (define_insn_and_split "floatsitf2"
8243 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8244 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
8245 (clobber (match_scratch:DF 2 "=f"))]
8246 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8247 && TARGET_LONG_DOUBLE_128"
8248 "#"
8249 "&& reload_completed"
8250 [(set (match_dup 2)
8251 (float:DF (match_dup 1)))
8252 (set (match_dup 0)
8253 (float_extend:TF (match_dup 2)))]
8254 "")
8256 (define_insn_and_split "fix_trunctfdi2"
8257 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
8258 (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
8259 (clobber (match_scratch:DF 2 "=f"))]
8260 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8261 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8262 "#"
8263 "&& reload_completed"
8264 [(set (match_dup 2)
8265 (float_truncate:DF (match_dup 1)))
8266 (set (match_dup 0)
8267 (fix:DI (match_dup 2)))]
8268 "")
8270 (define_insn_and_split "fix_trunctfsi2"
8271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8272 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8273 (clobber (match_scratch:DF 2 "=f"))]
8274 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8275 && TARGET_LONG_DOUBLE_128"
8276 "#"
8277 "&& reload_completed"
8278 [(set (match_dup 2)
8279 (float_truncate:DF (match_dup 1)))
8280 (set (match_dup 0)
8281 (fix:SI (match_dup 2)))]
8282 "")
8284 (define_insn "negtf2"
8285 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8286 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8287 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8288 && TARGET_LONG_DOUBLE_128"
8289 "*
8290 {
8291 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8292 return \"fneg %L0,%L1\;fneg %0,%1\";
8293 else
8294 return \"fneg %0,%1\;fneg %L0,%L1\";
8295 }"
8296 [(set_attr "type" "fp")
8297 (set_attr "length" "8")])
8299 (define_insn "abstf2"
8300 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8301 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8302 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8303 && TARGET_LONG_DOUBLE_128"
8304 "*
8305 {
8306 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8307 return \"fabs %L0,%L1\;fabs %0,%1\";
8308 else
8309 return \"fabs %0,%1\;fabs %L0,%L1\";
8310 }"
8311 [(set_attr "type" "fp")
8312 (set_attr "length" "8")])
8314 (define_insn ""
8315 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8316 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
8317 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8318 && TARGET_LONG_DOUBLE_128"
8319 "*
8320 {
8321 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8322 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8323 else
8324 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8325 }"
8326 [(set_attr "type" "fp")
8327 (set_attr "length" "8")])
8328 \f
8329 ;; Next come the multi-word integer load and store and the load and store
8330 ;; multiple insns.
8331 (define_expand "movdi"
8332 [(set (match_operand:DI 0 "general_operand" "")
8333 (match_operand:DI 1 "any_operand" ""))]
8334 ""
8335 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8337 (define_insn "*movdi_internal32"
8338 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8339 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8340 "! TARGET_POWERPC64
8341 && (gpc_reg_operand (operands[0], DImode)
8342 || gpc_reg_operand (operands[1], DImode))"
8343 "*
8344 {
8345 switch (which_alternative)
8346 {
8347 default:
8348 abort ();
8349 case 0:
8350 /* We normally copy the low-numbered register first. However, if
8351 the first register operand 0 is the same as the second register of
8352 operand 1, we must copy in the opposite order. */
8353 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8354 return \"mr %L0,%L1\;mr %0,%1\";
8355 else
8356 return \"mr %0,%1\;mr %L0,%L1\";
8357 case 1:
8358 /* If the low-address word is used in the address, we must load it
8359 last. Otherwise, load it first. Note that we cannot have
8360 auto-increment in that case since the address register is known to be
8361 dead. */
8362 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8363 operands[1], 0))
8364 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8365 else
8366 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8367 case 2:
8368 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8369 case 3:
8370 return \"fmr %0,%1\";
8371 case 4:
8372 return \"lfd%U1%X1 %0,%1\";
8373 case 5:
8374 return \"stfd%U0%X0 %1,%0\";
8375 case 6:
8376 case 7:
8377 case 8:
8378 case 9:
8379 case 10:
8380 return \"#\";
8381 }
8382 }"
8383 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
8384 (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")])
8386 (define_split
8387 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8388 (match_operand:DI 1 "const_int_operand" ""))]
8389 "! TARGET_POWERPC64 && reload_completed"
8390 [(set (match_dup 2) (match_dup 4))
8391 (set (match_dup 3) (match_dup 1))]
8392 "
8393 {
8394 HOST_WIDE_INT value = INTVAL (operands[1]);
8395 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8396 DImode);
8397 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8398 DImode);
8399 #if HOST_BITS_PER_WIDE_INT == 32
8400 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8401 #else
8402 operands[4] = GEN_INT (value >> 32);
8403 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8404 #endif
8405 }")
8407 (define_split
8408 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8409 (match_operand:DI 1 "const_double_operand" ""))]
8410 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
8411 [(set (match_dup 2) (match_dup 4))
8412 (set (match_dup 3) (match_dup 5))]
8413 "
8414 {
8415 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8416 DImode);
8417 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8418 DImode);
8419 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8420 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8421 }")
8423 (define_insn "*movdi_internal64"
8424 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
8425 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8426 "TARGET_POWERPC64
8427 && (gpc_reg_operand (operands[0], DImode)
8428 || gpc_reg_operand (operands[1], DImode))"
8429 "@
8430 mr %0,%1
8431 ld%U1%X1 %0,%1
8432 std%U0%X0 %1,%0
8433 li %0,%1
8434 lis %0,%v1
8435 #
8436 {cal|la} %0,%a1
8437 fmr %0,%1
8438 lfd%U1%X1 %0,%1
8439 stfd%U0%X0 %1,%0
8440 mf%1 %0
8441 mt%0 %1
8442 {cror 0,0,0|nop}"
8443 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
8444 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8446 ;; immediate value valid for a single instruction hiding in a const_double
8447 (define_insn ""
8448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8449 (match_operand:DI 1 "const_double_operand" "F"))]
8450 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8451 && GET_CODE (operands[1]) == CONST_DOUBLE
8452 && num_insns_constant (operands[1], DImode) == 1"
8453 "*
8454 {
8455 return ((unsigned HOST_WIDE_INT)
8456 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8457 ? \"li %0,%1\" : \"lis %0,%v1\";
8458 }")
8460 ;; Generate all one-bits and clear left or right.
8461 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8462 (define_split
8463 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8464 (match_operand:DI 1 "mask64_operand" ""))]
8465 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8466 [(set (match_dup 0) (const_int -1))
8467 (set (match_dup 0)
8468 (and:DI (rotate:DI (match_dup 0)
8469 (const_int 0))
8470 (match_dup 1)))]
8471 "")
8473 ;; Split a load of a large constant into the appropriate five-instruction
8474 ;; sequence. Handle anything in a constant number of insns.
8475 ;; When non-easy constants can go in the TOC, this should use
8476 ;; easy_fp_constant predicate.
8477 (define_split
8478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8479 (match_operand:DI 1 "const_int_operand" ""))]
8480 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8481 [(set (match_dup 0) (match_dup 2))
8482 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8483 "
8484 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8486 if (tem == operands[0])
8487 DONE;
8488 else
8489 FAIL;
8490 }")
8492 (define_split
8493 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8494 (match_operand:DI 1 "const_double_operand" ""))]
8495 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8496 [(set (match_dup 0) (match_dup 2))
8497 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8498 "
8499 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8501 if (tem == operands[0])
8502 DONE;
8503 else
8504 FAIL;
8505 }")
8507 ;; Split a load of a large constant into the appropriate five-instruction
8508 (define_insn "*movdi_internal2"
8509 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8510 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
8511 (const_int 0)))
8512 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8513 "TARGET_POWERPC64"
8514 "@
8515 mr. %0,%1
8516 #"
8517 [(set_attr "type" "compare")
8518 (set_attr "length" "4,8")])
8520 (define_split
8521 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8522 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8523 (const_int 0)))
8524 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8525 "TARGET_POWERPC64 && reload_completed"
8526 [(set (match_dup 0) (match_dup 1))
8527 (set (match_dup 2)
8528 (compare:CC (match_dup 0)
8529 (const_int 0)))]
8530 "")
8531 \f
8532 ;; TImode is similar, except that we usually want to compute the address into
8533 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8534 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8535 (define_expand "movti"
8536 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8537 (match_operand:TI 1 "general_operand" ""))
8538 (clobber (scratch:SI))])]
8539 "TARGET_STRING || TARGET_POWERPC64"
8540 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8542 ;; We say that MQ is clobbered in the last alternative because the first
8543 ;; alternative would never get used otherwise since it would need a reload
8544 ;; while the 2nd alternative would not. We put memory cases first so they
8545 ;; are preferred. Otherwise, we'd try to reload the output instead of
8546 ;; giving the SCRATCH mq.
8547 (define_insn "*movti_power"
8548 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8549 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8550 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8551 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8552 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8553 "*
8554 {
8555 switch (which_alternative)
8556 {
8557 default:
8558 abort ();
8560 case 0:
8561 return \"{stsi|stswi} %1,%P0,16\";
8562 case 1:
8563 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8564 case 2:
8565 /* Normally copy registers with lowest numbered register copied first.
8566 But copy in the other order if the first register of the output
8567 is the second, third, or fourth register in the input. */
8568 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8569 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8570 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8571 else
8572 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8573 case 3:
8574 /* If the address is not used in the output, we can use lsi. Otherwise,
8575 fall through to generating four loads. */
8576 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8577 return \"{lsi|lswi} %0,%P1,16\";
8578 /* ... fall through ... */
8579 case 4:
8580 /* If the address register is the same as the register for the lowest-
8581 addressed word, load it last. Similarly for the next two words.
8582 Otherwise load lowest address to highest. */
8583 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8584 operands[1], 0))
8585 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8586 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8587 REGNO (operands[0]) + 2, operands[1], 0))
8588 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8589 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8590 REGNO (operands[0]) + 3, operands[1], 0))
8591 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8592 else
8593 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8594 }
8595 }"
8596 [(set_attr "type" "store,store,*,load,load")
8597 (set_attr "length" "4,16,16,4,16")])
8599 (define_insn "*movti_string"
8600 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8601 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8602 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8603 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8604 "*
8605 {
8606 switch (which_alternative)
8607 {
8608 default:
8609 abort ();
8611 case 0:
8612 return \"{stsi|stswi} %1,%P0,16\";
8613 case 1:
8614 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8615 case 2:
8616 /* Normally copy registers with lowest numbered register copied first.
8617 But copy in the other order if the first register of the output
8618 is the second, third, or fourth register in the input. */
8619 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8620 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8621 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8622 else
8623 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8624 case 3:
8625 /* If the address is not used in the output, we can use lsi. Otherwise,
8626 fall through to generating four loads. */
8627 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8628 return \"{lsi|lswi} %0,%P1,16\";
8629 /* ... fall through ... */
8630 case 4:
8631 /* If the address register is the same as the register for the lowest-
8632 addressed word, load it last. Similarly for the next two words.
8633 Otherwise load lowest address to highest. */
8634 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8635 operands[1], 0))
8636 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8637 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8638 REGNO (operands[0]) + 2, operands[1], 0))
8639 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8640 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8641 REGNO (operands[0]) + 3, operands[1], 0))
8642 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8643 else
8644 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8645 }
8646 }"
8647 [(set_attr "type" "store,store,*,load,load")
8648 (set_attr "length" "4,16,16,4,16")])
8650 (define_insn "*movti_ppc64"
8651 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8652 (match_operand:TI 1 "input_operand" "r,m,r"))]
8653 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8654 || gpc_reg_operand (operands[1], TImode))"
8655 "*
8656 {
8657 switch (which_alternative)
8658 {
8659 default:
8660 abort ();
8661 case 0:
8662 /* We normally copy the low-numbered register first. However, if
8663 the first register operand 0 is the same as the second register of
8664 operand 1, we must copy in the opposite order. */
8665 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8666 return \"mr %L0,%L1\;mr %0,%1\";
8667 else
8668 return \"mr %0,%1\;mr %L0,%L1\";
8669 case 1:
8670 /* If the low-address word is used in the address, we must load it
8671 last. Otherwise, load it first. Note that we cannot have
8672 auto-increment in that case since the address register is known to be
8673 dead. */
8674 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8675 operands[1], 0))
8676 return \"ld %L0,%L1\;ld %0,%1\";
8677 else
8678 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8679 case 2:
8680 return \"std%U0 %1,%0\;std %L1,%L0\";
8681 }
8682 }"
8683 [(set_attr "type" "*,load,store")
8684 (set_attr "length" "8,8,8")])
8685 \f
8686 (define_expand "load_multiple"
8687 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8688 (match_operand:SI 1 "" ""))
8689 (use (match_operand:SI 2 "" ""))])]
8690 "TARGET_STRING && !TARGET_POWERPC64"
8691 "
8692 {
8693 int regno;
8694 int count;
8695 rtx op1;
8696 int i;
8698 /* Support only loading a constant number of fixed-point registers from
8699 memory and only bother with this if more than two; the machine
8700 doesn't support more than eight. */
8701 if (GET_CODE (operands[2]) != CONST_INT
8702 || INTVAL (operands[2]) <= 2
8703 || INTVAL (operands[2]) > 8
8704 || GET_CODE (operands[1]) != MEM
8705 || GET_CODE (operands[0]) != REG
8706 || REGNO (operands[0]) >= 32)
8707 FAIL;
8709 count = INTVAL (operands[2]);
8710 regno = REGNO (operands[0]);
8712 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8713 op1 = replace_equiv_address (operands[1],
8714 force_reg (SImode, XEXP (operands[1], 0)));
8716 for (i = 0; i < count; i++)
8717 XVECEXP (operands[3], 0, i)
8718 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8719 adjust_address_nv (op1, SImode, i * 4));
8720 }")
8722 (define_insn "*ldmsi8"
8723 [(match_parallel 0 "load_multiple_operation"
8724 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8725 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8726 (set (match_operand:SI 3 "gpc_reg_operand" "")
8727 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8728 (set (match_operand:SI 4 "gpc_reg_operand" "")
8729 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8730 (set (match_operand:SI 5 "gpc_reg_operand" "")
8731 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8732 (set (match_operand:SI 6 "gpc_reg_operand" "")
8733 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8734 (set (match_operand:SI 7 "gpc_reg_operand" "")
8735 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8736 (set (match_operand:SI 8 "gpc_reg_operand" "")
8737 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8738 (set (match_operand:SI 9 "gpc_reg_operand" "")
8739 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8740 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8741 "*
8742 { return rs6000_output_load_multiple (operands); }"
8743 [(set_attr "type" "load")
8744 (set_attr "length" "32")])
8746 (define_insn "*ldmsi7"
8747 [(match_parallel 0 "load_multiple_operation"
8748 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8749 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8750 (set (match_operand:SI 3 "gpc_reg_operand" "")
8751 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8752 (set (match_operand:SI 4 "gpc_reg_operand" "")
8753 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8754 (set (match_operand:SI 5 "gpc_reg_operand" "")
8755 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8756 (set (match_operand:SI 6 "gpc_reg_operand" "")
8757 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8758 (set (match_operand:SI 7 "gpc_reg_operand" "")
8759 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8760 (set (match_operand:SI 8 "gpc_reg_operand" "")
8761 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8762 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8763 "*
8764 { return rs6000_output_load_multiple (operands); }"
8765 [(set_attr "type" "load")
8766 (set_attr "length" "32")])
8768 (define_insn "*ldmsi6"
8769 [(match_parallel 0 "load_multiple_operation"
8770 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8771 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8772 (set (match_operand:SI 3 "gpc_reg_operand" "")
8773 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8774 (set (match_operand:SI 4 "gpc_reg_operand" "")
8775 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8776 (set (match_operand:SI 5 "gpc_reg_operand" "")
8777 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8778 (set (match_operand:SI 6 "gpc_reg_operand" "")
8779 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8780 (set (match_operand:SI 7 "gpc_reg_operand" "")
8781 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8782 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8783 "*
8784 { return rs6000_output_load_multiple (operands); }"
8785 [(set_attr "type" "load")
8786 (set_attr "length" "32")])
8788 (define_insn "*ldmsi5"
8789 [(match_parallel 0 "load_multiple_operation"
8790 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8791 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8792 (set (match_operand:SI 3 "gpc_reg_operand" "")
8793 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8794 (set (match_operand:SI 4 "gpc_reg_operand" "")
8795 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8796 (set (match_operand:SI 5 "gpc_reg_operand" "")
8797 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8798 (set (match_operand:SI 6 "gpc_reg_operand" "")
8799 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8800 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8801 "*
8802 { return rs6000_output_load_multiple (operands); }"
8803 [(set_attr "type" "load")
8804 (set_attr "length" "32")])
8806 (define_insn "*ldmsi4"
8807 [(match_parallel 0 "load_multiple_operation"
8808 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8809 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8810 (set (match_operand:SI 3 "gpc_reg_operand" "")
8811 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8812 (set (match_operand:SI 4 "gpc_reg_operand" "")
8813 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8814 (set (match_operand:SI 5 "gpc_reg_operand" "")
8815 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8816 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8817 "*
8818 { return rs6000_output_load_multiple (operands); }"
8819 [(set_attr "type" "load")
8820 (set_attr "length" "32")])
8822 (define_insn "*ldmsi3"
8823 [(match_parallel 0 "load_multiple_operation"
8824 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8825 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8826 (set (match_operand:SI 3 "gpc_reg_operand" "")
8827 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8828 (set (match_operand:SI 4 "gpc_reg_operand" "")
8829 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8830 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8831 "*
8832 { return rs6000_output_load_multiple (operands); }"
8833 [(set_attr "type" "load")
8834 (set_attr "length" "32")])
8836 (define_expand "store_multiple"
8837 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8838 (match_operand:SI 1 "" ""))
8839 (clobber (scratch:SI))
8840 (use (match_operand:SI 2 "" ""))])]
8841 "TARGET_STRING && !TARGET_POWERPC64"
8842 "
8843 {
8844 int regno;
8845 int count;
8846 rtx to;
8847 rtx op0;
8848 int i;
8850 /* Support only storing a constant number of fixed-point registers to
8851 memory and only bother with this if more than two; the machine
8852 doesn't support more than eight. */
8853 if (GET_CODE (operands[2]) != CONST_INT
8854 || INTVAL (operands[2]) <= 2
8855 || INTVAL (operands[2]) > 8
8856 || GET_CODE (operands[0]) != MEM
8857 || GET_CODE (operands[1]) != REG
8858 || REGNO (operands[1]) >= 32)
8859 FAIL;
8861 count = INTVAL (operands[2]);
8862 regno = REGNO (operands[1]);
8864 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8865 to = force_reg (SImode, XEXP (operands[0], 0));
8866 op0 = replace_equiv_address (operands[0], to);
8868 XVECEXP (operands[3], 0, 0)
8869 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8870 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8871 gen_rtx_SCRATCH (SImode));
8873 for (i = 1; i < count; i++)
8874 XVECEXP (operands[3], 0, i + 1)
8875 = gen_rtx_SET (VOIDmode,
8876 adjust_address_nv (op0, SImode, i * 4),
8877 gen_rtx_REG (SImode, regno + i));
8878 }")
8880 (define_insn "*store_multiple_power"
8881 [(match_parallel 0 "store_multiple_operation"
8882 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8883 (match_operand:SI 2 "gpc_reg_operand" "r"))
8884 (clobber (match_scratch:SI 3 "=q"))])]
8885 "TARGET_STRING && TARGET_POWER"
8886 "{stsi|stswi} %2,%P1,%O0"
8887 [(set_attr "type" "store")])
8889 (define_insn "*stmsi8"
8890 [(match_parallel 0 "store_multiple_operation"
8891 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8892 (match_operand:SI 2 "gpc_reg_operand" "r"))
8893 (clobber (match_scratch:SI 3 "X"))
8894 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8895 (match_operand:SI 4 "gpc_reg_operand" "r"))
8896 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8897 (match_operand:SI 5 "gpc_reg_operand" "r"))
8898 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8899 (match_operand:SI 6 "gpc_reg_operand" "r"))
8900 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8901 (match_operand:SI 7 "gpc_reg_operand" "r"))
8902 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8903 (match_operand:SI 8 "gpc_reg_operand" "r"))
8904 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8905 (match_operand:SI 9 "gpc_reg_operand" "r"))
8906 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8907 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8908 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8909 "{stsi|stswi} %2,%1,%O0"
8910 [(set_attr "type" "store")])
8912 (define_insn "*stmsi7"
8913 [(match_parallel 0 "store_multiple_operation"
8914 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8915 (match_operand:SI 2 "gpc_reg_operand" "r"))
8916 (clobber (match_scratch:SI 3 "X"))
8917 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8918 (match_operand:SI 4 "gpc_reg_operand" "r"))
8919 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8920 (match_operand:SI 5 "gpc_reg_operand" "r"))
8921 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8922 (match_operand:SI 6 "gpc_reg_operand" "r"))
8923 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8924 (match_operand:SI 7 "gpc_reg_operand" "r"))
8925 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8926 (match_operand:SI 8 "gpc_reg_operand" "r"))
8927 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8928 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8929 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8930 "{stsi|stswi} %2,%1,%O0"
8931 [(set_attr "type" "store")])
8933 (define_insn "*stmsi6"
8934 [(match_parallel 0 "store_multiple_operation"
8935 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8936 (match_operand:SI 2 "gpc_reg_operand" "r"))
8937 (clobber (match_scratch:SI 3 "X"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8939 (match_operand:SI 4 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8941 (match_operand:SI 5 "gpc_reg_operand" "r"))
8942 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8943 (match_operand:SI 6 "gpc_reg_operand" "r"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8945 (match_operand:SI 7 "gpc_reg_operand" "r"))
8946 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8947 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8948 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8949 "{stsi|stswi} %2,%1,%O0"
8950 [(set_attr "type" "store")])
8952 (define_insn "*stmsi5"
8953 [(match_parallel 0 "store_multiple_operation"
8954 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8955 (match_operand:SI 2 "gpc_reg_operand" "r"))
8956 (clobber (match_scratch:SI 3 "X"))
8957 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8958 (match_operand:SI 4 "gpc_reg_operand" "r"))
8959 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8960 (match_operand:SI 5 "gpc_reg_operand" "r"))
8961 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8962 (match_operand:SI 6 "gpc_reg_operand" "r"))
8963 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8964 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8965 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8966 "{stsi|stswi} %2,%1,%O0"
8967 [(set_attr "type" "store")])
8969 (define_insn "*stmsi4"
8970 [(match_parallel 0 "store_multiple_operation"
8971 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8972 (match_operand:SI 2 "gpc_reg_operand" "r"))
8973 (clobber (match_scratch:SI 3 "X"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8975 (match_operand:SI 4 "gpc_reg_operand" "r"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8977 (match_operand:SI 5 "gpc_reg_operand" "r"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8979 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8980 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8981 "{stsi|stswi} %2,%1,%O0"
8982 [(set_attr "type" "store")])
8984 (define_insn "*stmsi3"
8985 [(match_parallel 0 "store_multiple_operation"
8986 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8987 (match_operand:SI 2 "gpc_reg_operand" "r"))
8988 (clobber (match_scratch:SI 3 "X"))
8989 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8990 (match_operand:SI 4 "gpc_reg_operand" "r"))
8991 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8992 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8993 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8994 "{stsi|stswi} %2,%1,%O0"
8995 [(set_attr "type" "store")])
8996 \f
8997 ;; String/block move insn.
8998 ;; Argument 0 is the destination
8999 ;; Argument 1 is the source
9000 ;; Argument 2 is the length
9001 ;; Argument 3 is the alignment
9003 (define_expand "movstrsi"
9004 [(parallel [(set (match_operand:BLK 0 "" "")
9005 (match_operand:BLK 1 "" ""))
9006 (use (match_operand:SI 2 "" ""))
9007 (use (match_operand:SI 3 "" ""))])]
9008 ""
9009 "
9010 {
9011 if (expand_block_move (operands))
9012 DONE;
9013 else
9014 FAIL;
9015 }")
9017 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9018 ;; register allocator doesn't have a clue about allocating 8 word registers.
9019 ;; rD/rS = r5 is preferred, efficient form.
9020 (define_expand "movstrsi_8reg"
9021 [(parallel [(set (match_operand 0 "" "")
9022 (match_operand 1 "" ""))
9023 (use (match_operand 2 "" ""))
9024 (use (match_operand 3 "" ""))
9025 (clobber (reg:SI 5))
9026 (clobber (reg:SI 6))
9027 (clobber (reg:SI 7))
9028 (clobber (reg:SI 8))
9029 (clobber (reg:SI 9))
9030 (clobber (reg:SI 10))
9031 (clobber (reg:SI 11))
9032 (clobber (reg:SI 12))
9033 (clobber (match_scratch:SI 4 ""))])]
9034 "TARGET_STRING"
9035 "")
9037 (define_insn ""
9038 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9039 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9040 (use (match_operand:SI 2 "immediate_operand" "i"))
9041 (use (match_operand:SI 3 "immediate_operand" "i"))
9042 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9043 (clobber (reg:SI 6))
9044 (clobber (reg:SI 7))
9045 (clobber (reg:SI 8))
9046 (clobber (reg:SI 9))
9047 (clobber (reg:SI 10))
9048 (clobber (reg:SI 11))
9049 (clobber (reg:SI 12))
9050 (clobber (match_scratch:SI 5 "=q"))]
9051 "TARGET_STRING && TARGET_POWER
9052 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9053 || INTVAL (operands[2]) == 0)
9054 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9055 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9056 && REGNO (operands[4]) == 5"
9057 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9058 [(set_attr "type" "load")
9059 (set_attr "length" "8")])
9061 (define_insn ""
9062 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9063 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9064 (use (match_operand:SI 2 "immediate_operand" "i"))
9065 (use (match_operand:SI 3 "immediate_operand" "i"))
9066 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9067 (clobber (reg:SI 6))
9068 (clobber (reg:SI 7))
9069 (clobber (reg:SI 8))
9070 (clobber (reg:SI 9))
9071 (clobber (reg:SI 10))
9072 (clobber (reg:SI 11))
9073 (clobber (reg:SI 12))
9074 (clobber (match_scratch:SI 5 "X"))]
9075 "TARGET_STRING && ! TARGET_POWER
9076 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9077 || INTVAL (operands[2]) == 0)
9078 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9079 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9080 && REGNO (operands[4]) == 5"
9081 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9082 [(set_attr "type" "load")
9083 (set_attr "length" "8")])
9085 (define_insn ""
9086 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9087 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9088 (use (match_operand:SI 2 "immediate_operand" "i"))
9089 (use (match_operand:SI 3 "immediate_operand" "i"))
9090 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9091 (clobber (reg:SI 6))
9092 (clobber (reg:SI 7))
9093 (clobber (reg:SI 8))
9094 (clobber (reg:SI 9))
9095 (clobber (reg:SI 10))
9096 (clobber (reg:SI 11))
9097 (clobber (reg:SI 12))
9098 (clobber (match_scratch:SI 5 "X"))]
9099 "TARGET_STRING && TARGET_POWERPC64
9100 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9101 || INTVAL (operands[2]) == 0)
9102 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9103 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9104 && REGNO (operands[4]) == 5"
9105 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9106 [(set_attr "type" "load")
9107 (set_attr "length" "8")])
9109 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9110 ;; register allocator doesn't have a clue about allocating 6 word registers.
9111 ;; rD/rS = r5 is preferred, efficient form.
9112 (define_expand "movstrsi_6reg"
9113 [(parallel [(set (match_operand 0 "" "")
9114 (match_operand 1 "" ""))
9115 (use (match_operand 2 "" ""))
9116 (use (match_operand 3 "" ""))
9117 (clobber (reg:SI 5))
9118 (clobber (reg:SI 6))
9119 (clobber (reg:SI 7))
9120 (clobber (reg:SI 8))
9121 (clobber (reg:SI 9))
9122 (clobber (reg:SI 10))
9123 (clobber (match_scratch:SI 4 ""))])]
9124 "TARGET_STRING"
9125 "")
9127 (define_insn ""
9128 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9129 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9130 (use (match_operand:SI 2 "immediate_operand" "i"))
9131 (use (match_operand:SI 3 "immediate_operand" "i"))
9132 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9133 (clobber (reg:SI 6))
9134 (clobber (reg:SI 7))
9135 (clobber (reg:SI 8))
9136 (clobber (reg:SI 9))
9137 (clobber (reg:SI 10))
9138 (clobber (match_scratch:SI 5 "=q"))]
9139 "TARGET_STRING && TARGET_POWER
9140 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9141 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9142 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9143 && REGNO (operands[4]) == 5"
9144 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9145 [(set_attr "type" "load")
9146 (set_attr "length" "8")])
9148 (define_insn ""
9149 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9150 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9151 (use (match_operand:SI 2 "immediate_operand" "i"))
9152 (use (match_operand:SI 3 "immediate_operand" "i"))
9153 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9154 (clobber (reg:SI 6))
9155 (clobber (reg:SI 7))
9156 (clobber (reg:SI 8))
9157 (clobber (reg:SI 9))
9158 (clobber (reg:SI 10))
9159 (clobber (match_scratch:SI 5 "X"))]
9160 "TARGET_STRING && ! TARGET_POWER
9161 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9162 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9163 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9164 && REGNO (operands[4]) == 5"
9165 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9166 [(set_attr "type" "load")
9167 (set_attr "length" "8")])
9169 (define_insn ""
9170 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9171 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9172 (use (match_operand:SI 2 "immediate_operand" "i"))
9173 (use (match_operand:SI 3 "immediate_operand" "i"))
9174 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9175 (clobber (reg:SI 6))
9176 (clobber (reg:SI 7))
9177 (clobber (reg:SI 8))
9178 (clobber (reg:SI 9))
9179 (clobber (reg:SI 10))
9180 (clobber (match_scratch:SI 5 "X"))]
9181 "TARGET_STRING && TARGET_POWERPC64
9182 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9183 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9184 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9185 && REGNO (operands[4]) == 5"
9186 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9187 [(set_attr "type" "load")
9188 (set_attr "length" "8")])
9190 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9191 ;; problems with TImode.
9192 ;; rD/rS = r5 is preferred, efficient form.
9193 (define_expand "movstrsi_4reg"
9194 [(parallel [(set (match_operand 0 "" "")
9195 (match_operand 1 "" ""))
9196 (use (match_operand 2 "" ""))
9197 (use (match_operand 3 "" ""))
9198 (clobber (reg:SI 5))
9199 (clobber (reg:SI 6))
9200 (clobber (reg:SI 7))
9201 (clobber (reg:SI 8))
9202 (clobber (match_scratch:SI 4 ""))])]
9203 "TARGET_STRING"
9204 "")
9206 (define_insn ""
9207 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9208 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9209 (use (match_operand:SI 2 "immediate_operand" "i"))
9210 (use (match_operand:SI 3 "immediate_operand" "i"))
9211 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9212 (clobber (reg:SI 6))
9213 (clobber (reg:SI 7))
9214 (clobber (reg:SI 8))
9215 (clobber (match_scratch:SI 5 "=q"))]
9216 "TARGET_STRING && TARGET_POWER
9217 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9218 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9219 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9220 && REGNO (operands[4]) == 5"
9221 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9222 [(set_attr "type" "load")
9223 (set_attr "length" "8")])
9225 (define_insn ""
9226 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9227 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9228 (use (match_operand:SI 2 "immediate_operand" "i"))
9229 (use (match_operand:SI 3 "immediate_operand" "i"))
9230 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9231 (clobber (reg:SI 6))
9232 (clobber (reg:SI 7))
9233 (clobber (reg:SI 8))
9234 (clobber (match_scratch:SI 5 "X"))]
9235 "TARGET_STRING && ! TARGET_POWER
9236 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9237 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9238 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9239 && REGNO (operands[4]) == 5"
9240 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9241 [(set_attr "type" "load")
9242 (set_attr "length" "8")])
9244 (define_insn ""
9245 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9246 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9247 (use (match_operand:SI 2 "immediate_operand" "i"))
9248 (use (match_operand:SI 3 "immediate_operand" "i"))
9249 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9250 (clobber (reg:SI 6))
9251 (clobber (reg:SI 7))
9252 (clobber (reg:SI 8))
9253 (clobber (match_scratch:SI 5 "X"))]
9254 "TARGET_STRING && TARGET_POWERPC64
9255 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9256 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9257 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9258 && REGNO (operands[4]) == 5"
9259 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9260 [(set_attr "type" "load")
9261 (set_attr "length" "8")])
9263 ;; Move up to 8 bytes at a time.
9264 (define_expand "movstrsi_2reg"
9265 [(parallel [(set (match_operand 0 "" "")
9266 (match_operand 1 "" ""))
9267 (use (match_operand 2 "" ""))
9268 (use (match_operand 3 "" ""))
9269 (clobber (match_scratch:DI 4 ""))
9270 (clobber (match_scratch:SI 5 ""))])]
9271 "TARGET_STRING && ! TARGET_POWERPC64"
9272 "")
9274 (define_insn ""
9275 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9276 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9277 (use (match_operand:SI 2 "immediate_operand" "i"))
9278 (use (match_operand:SI 3 "immediate_operand" "i"))
9279 (clobber (match_scratch:DI 4 "=&r"))
9280 (clobber (match_scratch:SI 5 "=q"))]
9281 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9282 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9283 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9284 [(set_attr "type" "load")
9285 (set_attr "length" "8")])
9287 (define_insn ""
9288 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9289 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9290 (use (match_operand:SI 2 "immediate_operand" "i"))
9291 (use (match_operand:SI 3 "immediate_operand" "i"))
9292 (clobber (match_scratch:DI 4 "=&r"))
9293 (clobber (match_scratch:SI 5 "X"))]
9294 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9295 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9296 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9297 [(set_attr "type" "load")
9298 (set_attr "length" "8")])
9300 ;; Move up to 4 bytes at a time.
9301 (define_expand "movstrsi_1reg"
9302 [(parallel [(set (match_operand 0 "" "")
9303 (match_operand 1 "" ""))
9304 (use (match_operand 2 "" ""))
9305 (use (match_operand 3 "" ""))
9306 (clobber (match_scratch:SI 4 ""))
9307 (clobber (match_scratch:SI 5 ""))])]
9308 "TARGET_STRING"
9309 "")
9311 (define_insn ""
9312 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9313 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9314 (use (match_operand:SI 2 "immediate_operand" "i"))
9315 (use (match_operand:SI 3 "immediate_operand" "i"))
9316 (clobber (match_scratch:SI 4 "=&r"))
9317 (clobber (match_scratch:SI 5 "=q"))]
9318 "TARGET_STRING && TARGET_POWER
9319 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9320 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9321 [(set_attr "type" "load")
9322 (set_attr "length" "8")])
9324 (define_insn ""
9325 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9326 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9327 (use (match_operand:SI 2 "immediate_operand" "i"))
9328 (use (match_operand:SI 3 "immediate_operand" "i"))
9329 (clobber (match_scratch:SI 4 "=&r"))
9330 (clobber (match_scratch:SI 5 "X"))]
9331 "TARGET_STRING && ! TARGET_POWER
9332 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9333 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9334 [(set_attr "type" "load")
9335 (set_attr "length" "8")])
9337 (define_insn ""
9338 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9339 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9340 (use (match_operand:SI 2 "immediate_operand" "i"))
9341 (use (match_operand:SI 3 "immediate_operand" "i"))
9342 (clobber (match_scratch:SI 4 "=&r"))
9343 (clobber (match_scratch:SI 5 "X"))]
9344 "TARGET_STRING && TARGET_POWERPC64
9345 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9346 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9347 [(set_attr "type" "load")
9348 (set_attr "length" "8")])
9350 \f
9351 ;; Define insns that do load or store with update. Some of these we can
9352 ;; get by using pre-decrement or pre-increment, but the hardware can also
9353 ;; do cases where the increment is not the size of the object.
9354 ;;
9355 ;; In all these cases, we use operands 0 and 1 for the register being
9356 ;; incremented because those are the operands that local-alloc will
9357 ;; tie and these are the pair most likely to be tieable (and the ones
9358 ;; that will benefit the most).
9360 (define_insn "*movdi_update1"
9361 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9362 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9363 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9364 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9365 (plus:DI (match_dup 1) (match_dup 2)))]
9366 "TARGET_POWERPC64 && TARGET_UPDATE"
9367 "@
9368 ldux %3,%0,%2
9369 ldu %3,%2(%0)"
9370 [(set_attr "type" "load_ux,load_u")])
9372 (define_insn "movdi_update"
9373 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9374 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9375 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9376 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9377 (plus:DI (match_dup 1) (match_dup 2)))]
9378 "TARGET_POWERPC64 && TARGET_UPDATE"
9379 "@
9380 stdux %3,%0,%2
9381 stdu %3,%2(%0)"
9382 [(set_attr "type" "store_ux,store_u")])
9384 (define_insn "*movsi_update1"
9385 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9386 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9387 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9388 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9389 (plus:SI (match_dup 1) (match_dup 2)))]
9390 ""
9391 "@
9392 {lux|lwzux} %3,%0,%2
9393 {lu|lwzu} %3,%2(%0)"
9394 [(set_attr "type" "load_ux,load_u")])
9396 (define_insn "*movsi_update2"
9397 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9398 (sign_extend:DI
9399 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9400 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9401 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9402 (plus:DI (match_dup 1) (match_dup 2)))]
9403 "TARGET_POWERPC64"
9404 "lwaux %3,%0,%2"
9405 [(set_attr "type" "load_ext_ux")])
9407 (define_insn "movsi_update"
9408 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9409 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9410 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9411 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9412 (plus:SI (match_dup 1) (match_dup 2)))]
9413 "TARGET_UPDATE"
9414 "@
9415 {stux|stwux} %3,%0,%2
9416 {stu|stwu} %3,%2(%0)"
9417 [(set_attr "type" "store_ux,store_u")])
9419 (define_insn "*movhi_update1"
9420 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9421 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9422 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9423 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9424 (plus:SI (match_dup 1) (match_dup 2)))]
9425 "TARGET_UPDATE"
9426 "@
9427 lhzux %3,%0,%2
9428 lhzu %3,%2(%0)"
9429 [(set_attr "type" "load_ux,load_u")])
9431 (define_insn "*movhi_update2"
9432 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9433 (zero_extend:SI
9434 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9435 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9436 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9437 (plus:SI (match_dup 1) (match_dup 2)))]
9438 "TARGET_UPDATE"
9439 "@
9440 lhzux %3,%0,%2
9441 lhzu %3,%2(%0)"
9442 [(set_attr "type" "load_ux,load_u")])
9444 (define_insn "*movhi_update3"
9445 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9446 (sign_extend:SI
9447 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9448 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9449 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9450 (plus:SI (match_dup 1) (match_dup 2)))]
9451 "TARGET_UPDATE"
9452 "@
9453 lhaux %3,%0,%2
9454 lhau %3,%2(%0)"
9455 [(set_attr "type" "load_ext_ux,load_ext_u")])
9457 (define_insn "*movhi_update4"
9458 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9459 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9460 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9461 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9462 (plus:SI (match_dup 1) (match_dup 2)))]
9463 "TARGET_UPDATE"
9464 "@
9465 sthux %3,%0,%2
9466 sthu %3,%2(%0)"
9467 [(set_attr "type" "store_ux,store_u")])
9469 (define_insn "*movqi_update1"
9470 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9471 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9472 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9473 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9474 (plus:SI (match_dup 1) (match_dup 2)))]
9475 "TARGET_UPDATE"
9476 "@
9477 lbzux %3,%0,%2
9478 lbzu %3,%2(%0)"
9479 [(set_attr "type" "load_ux,load_u")])
9481 (define_insn "*movqi_update2"
9482 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9483 (zero_extend:SI
9484 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9485 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9486 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9487 (plus:SI (match_dup 1) (match_dup 2)))]
9488 "TARGET_UPDATE"
9489 "@
9490 lbzux %3,%0,%2
9491 lbzu %3,%2(%0)"
9492 [(set_attr "type" "load_ux,load_u")])
9494 (define_insn "*movqi_update3"
9495 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9496 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9497 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9498 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9499 (plus:SI (match_dup 1) (match_dup 2)))]
9500 "TARGET_UPDATE"
9501 "@
9502 stbux %3,%0,%2
9503 stbu %3,%2(%0)"
9504 [(set_attr "type" "store_ux,store_u")])
9506 (define_insn "*movsf_update1"
9507 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9508 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9509 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9510 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9511 (plus:SI (match_dup 1) (match_dup 2)))]
9512 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9513 "@
9514 lfsux %3,%0,%2
9515 lfsu %3,%2(%0)"
9516 [(set_attr "type" "fpload_ux,fpload_u")])
9518 (define_insn "*movsf_update2"
9519 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9520 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9521 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9522 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9523 (plus:SI (match_dup 1) (match_dup 2)))]
9524 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9525 "@
9526 stfsux %3,%0,%2
9527 stfsu %3,%2(%0)"
9528 [(set_attr "type" "fpstore_ux,fpstore_u")])
9530 (define_insn "*movsf_update3"
9531 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9532 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9533 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9534 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9535 (plus:SI (match_dup 1) (match_dup 2)))]
9536 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9537 "@
9538 {lux|lwzux} %3,%0,%2
9539 {lu|lwzu} %3,%2(%0)"
9540 [(set_attr "type" "load_ux,load_u")])
9542 (define_insn "*movsf_update4"
9543 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9544 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9545 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9546 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9547 (plus:SI (match_dup 1) (match_dup 2)))]
9548 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9549 "@
9550 {stux|stwux} %3,%0,%2
9551 {stu|stwu} %3,%2(%0)"
9552 [(set_attr "type" "store_ux,store_u")])
9554 (define_insn "*movdf_update1"
9555 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9556 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9557 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9558 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9559 (plus:SI (match_dup 1) (match_dup 2)))]
9560 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9561 "@
9562 lfdux %3,%0,%2
9563 lfdu %3,%2(%0)"
9564 [(set_attr "type" "fpload_ux,fpload_u")])
9566 (define_insn "*movdf_update2"
9567 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9568 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9569 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9570 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9571 (plus:SI (match_dup 1) (match_dup 2)))]
9572 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9573 "@
9574 stfdux %3,%0,%2
9575 stfdu %3,%2(%0)"
9576 [(set_attr "type" "fpstore_ux,fpstore_u")])
9578 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9580 (define_peephole
9581 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9582 (match_operand:DF 1 "memory_operand" ""))
9583 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9584 (match_operand:DF 3 "memory_operand" ""))]
9585 "TARGET_POWER2
9586 && TARGET_HARD_FLOAT && TARGET_FPRS
9587 && registers_ok_for_quad_peep (operands[0], operands[2])
9588 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9589 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9590 "lfq%U1%X1 %0,%1")
9592 (define_peephole
9593 [(set (match_operand:DF 0 "memory_operand" "")
9594 (match_operand:DF 1 "gpc_reg_operand" "f"))
9595 (set (match_operand:DF 2 "memory_operand" "")
9596 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9597 "TARGET_POWER2
9598 && TARGET_HARD_FLOAT && TARGET_FPRS
9599 && registers_ok_for_quad_peep (operands[1], operands[3])
9600 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9601 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9602 "stfq%U0%X0 %1,%0")
9603 \f
9604 ;; Next come insns related to the calling sequence.
9605 ;;
9606 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9607 ;; We move the back-chain and decrement the stack pointer.
9609 (define_expand "allocate_stack"
9610 [(set (match_operand 0 "gpc_reg_operand" "=r")
9611 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9612 (set (reg 1)
9613 (minus (reg 1) (match_dup 1)))]
9614 ""
9615 "
9616 { rtx chain = gen_reg_rtx (Pmode);
9617 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9618 rtx neg_op0;
9620 emit_move_insn (chain, stack_bot);
9622 /* Check stack bounds if necessary. */
9623 if (current_function_limit_stack)
9624 {
9625 rtx available;
9626 available = expand_binop (Pmode, sub_optab,
9627 stack_pointer_rtx, stack_limit_rtx,
9628 NULL_RTX, 1, OPTAB_WIDEN);
9629 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9630 }
9632 if (GET_CODE (operands[1]) != CONST_INT
9633 || INTVAL (operands[1]) < -32767
9634 || INTVAL (operands[1]) > 32768)
9635 {
9636 neg_op0 = gen_reg_rtx (Pmode);
9637 if (TARGET_32BIT)
9638 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9639 else
9640 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9641 }
9642 else
9643 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9645 if (TARGET_UPDATE)
9646 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9647 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9649 else
9650 {
9651 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9652 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9653 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9654 }
9656 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9657 DONE;
9658 }")
9660 ;; These patterns say how to save and restore the stack pointer. We need not
9661 ;; save the stack pointer at function level since we are careful to
9662 ;; preserve the backchain. At block level, we have to restore the backchain
9663 ;; when we restore the stack pointer.
9664 ;;
9665 ;; For nonlocal gotos, we must save both the stack pointer and its
9666 ;; backchain and restore both. Note that in the nonlocal case, the
9667 ;; save area is a memory location.
9669 (define_expand "save_stack_function"
9670 [(match_operand 0 "any_operand" "")
9671 (match_operand 1 "any_operand" "")]
9672 ""
9673 "DONE;")
9675 (define_expand "restore_stack_function"
9676 [(match_operand 0 "any_operand" "")
9677 (match_operand 1 "any_operand" "")]
9678 ""
9679 "DONE;")
9681 (define_expand "restore_stack_block"
9682 [(use (match_operand 0 "register_operand" ""))
9683 (set (match_dup 2) (match_dup 3))
9684 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9685 (set (match_dup 3) (match_dup 2))]
9686 ""
9687 "
9688 {
9689 operands[2] = gen_reg_rtx (Pmode);
9690 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9691 }")
9693 (define_expand "save_stack_nonlocal"
9694 [(match_operand 0 "memory_operand" "")
9695 (match_operand 1 "register_operand" "")]
9696 ""
9697 "
9698 {
9699 rtx temp = gen_reg_rtx (Pmode);
9701 /* Copy the backchain to the first word, sp to the second. */
9702 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9703 emit_move_insn (operand_subword (operands[0], 0, 0,
9704 (TARGET_32BIT ? DImode : TImode)),
9705 temp);
9706 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9707 operands[1]);
9708 DONE;
9709 }")
9711 (define_expand "restore_stack_nonlocal"
9712 [(match_operand 0 "register_operand" "")
9713 (match_operand 1 "memory_operand" "")]
9714 ""
9715 "
9716 {
9717 rtx temp = gen_reg_rtx (Pmode);
9719 /* Restore the backchain from the first word, sp from the second. */
9720 emit_move_insn (temp,
9721 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9722 emit_move_insn (operands[0],
9723 operand_subword (operands[1], 1, 0,
9724 (TARGET_32BIT ? DImode : TImode)));
9725 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9726 DONE;
9727 }")
9728 \f
9729 ;; TOC register handling.
9731 ;; Code to initialize the TOC register...
9733 (define_insn "load_toc_aix_si"
9734 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9735 (unspec:SI [(const_int 0)] 7))
9736 (use (reg:SI 2))])]
9737 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9738 "*
9739 {
9740 char buf[30];
9741 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9742 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9743 operands[2] = gen_rtx_REG (Pmode, 2);
9744 return \"{l|lwz} %0,%1(%2)\";
9745 }"
9746 [(set_attr "type" "load")])
9748 (define_insn "load_toc_aix_di"
9749 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9750 (unspec:DI [(const_int 0)] 7))
9751 (use (reg:DI 2))])]
9752 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9753 "*
9754 {
9755 char buf[30];
9756 #ifdef TARGET_RELOCATABLE
9757 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9758 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9759 #else
9760 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9761 #endif
9762 if (TARGET_ELF)
9763 strcat (buf, \"@toc\");
9764 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9765 operands[2] = gen_rtx_REG (Pmode, 2);
9766 return \"ld %0,%1(%2)\";
9767 }"
9768 [(set_attr "type" "load")])
9770 (define_insn "load_toc_v4_pic_si"
9771 [(set (match_operand:SI 0 "register_operand" "=l")
9772 (unspec:SI [(const_int 0)] 7))]
9773 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9774 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9775 [(set_attr "type" "branch")
9776 (set_attr "length" "4")])
9778 (define_insn "load_toc_v4_PIC_1"
9779 [(set (match_operand:SI 0 "register_operand" "=l")
9780 (match_operand:SI 1 "immediate_operand" "s"))
9781 (unspec [(match_dup 1)] 7)]
9782 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9783 "bcl 20,31,%1\\n%1:"
9784 [(set_attr "type" "branch")
9785 (set_attr "length" "4")])
9787 (define_insn "load_toc_v4_PIC_1b"
9788 [(set (match_operand:SI 0 "register_operand" "=l")
9789 (match_operand:SI 1 "immediate_operand" "s"))
9790 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
9791 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9792 "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
9793 [(set_attr "type" "branch")
9794 (set_attr "length" "8")])
9796 (define_insn "load_toc_v4_PIC_2"
9797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9798 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9799 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9800 (match_operand:SI 3 "immediate_operand" "s")))))]
9801 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9802 "{l|lwz} %0,%2-%3(%1)"
9803 [(set_attr "type" "load")])
9805 (define_insn "load_macho_picbase"
9806 [(set (match_operand:SI 0 "register_operand" "=l")
9807 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))]
9808 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
9809 "bcl 20,31,%1\\n%1:"
9810 [(set_attr "type" "branch")
9811 (set_attr "length" "4")])
9813 (define_insn "macho_correct_pic"
9814 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9815 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "=r")
9816 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
9817 (match_operand:SI 3 "immediate_operand" "s")]
9818 16)))]
9819 "DEFAULT_ABI == ABI_DARWIN"
9820 "addis %0,%1,ha16(%2-%3)\n\taddi %1,%1,lo16(%2-%3)"
9821 [(set_attr "length" "8")])
9823 ;; If the TOC is shared over a translation unit, as happens with all
9824 ;; the kinds of PIC that we support, we need to restore the TOC
9825 ;; pointer only when jumping over units of translation.
9826 ;; On Darwin, we need to reload the picbase.
9828 (define_expand "builtin_setjmp_receiver"
9829 [(use (label_ref (match_operand 0 "" "")))]
9830 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9831 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9832 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9833 "
9834 {
9835 #if TARGET_MACHO
9836 if (DEFAULT_ABI == ABI_DARWIN)
9837 {
9838 const char *picbase = machopic_function_base_name ();
9839 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
9840 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9841 rtx tmplabrtx;
9842 char tmplab[20];
9844 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9845 CODE_LABEL_NUMBER (operands[0]));
9846 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1));
9848 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9849 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9850 }
9851 else
9852 #endif
9853 rs6000_emit_load_toc_table (FALSE);
9854 DONE;
9855 }")
9856 \f
9857 ;; A function pointer under AIX is a pointer to a data area whose first word
9858 ;; contains the actual address of the function, whose second word contains a
9859 ;; pointer to its TOC, and whose third word contains a value to place in the
9860 ;; static chain register (r11). Note that if we load the static chain, our
9861 ;; "trampoline" need not have any executable code.
9863 (define_expand "call_indirect_aix32"
9864 [(set (match_dup 2)
9865 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9866 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9867 (reg:SI 2))
9868 (set (reg:SI 2)
9869 (mem:SI (plus:SI (match_dup 0)
9870 (const_int 4))))
9871 (set (reg:SI 11)
9872 (mem:SI (plus:SI (match_dup 0)
9873 (const_int 8))))
9874 (parallel [(call (mem:SI (match_dup 2))
9875 (match_operand 1 "" ""))
9876 (use (reg:SI 2))
9877 (use (reg:SI 11))
9878 (set (reg:SI 2)
9879 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9880 (clobber (scratch:SI))])]
9881 "TARGET_32BIT"
9882 "
9883 { operands[2] = gen_reg_rtx (SImode); }")
9885 (define_expand "call_indirect_aix64"
9886 [(set (match_dup 2)
9887 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9888 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9889 (reg:DI 2))
9890 (set (reg:DI 2)
9891 (mem:DI (plus:DI (match_dup 0)
9892 (const_int 8))))
9893 (set (reg:DI 11)
9894 (mem:DI (plus:DI (match_dup 0)
9895 (const_int 16))))
9896 (parallel [(call (mem:SI (match_dup 2))
9897 (match_operand 1 "" ""))
9898 (use (reg:DI 2))
9899 (use (reg:DI 11))
9900 (set (reg:DI 2)
9901 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9902 (clobber (scratch:SI))])]
9903 "TARGET_64BIT"
9904 "
9905 { operands[2] = gen_reg_rtx (DImode); }")
9907 (define_expand "call_value_indirect_aix32"
9908 [(set (match_dup 3)
9909 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9910 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9911 (reg:SI 2))
9912 (set (reg:SI 2)
9913 (mem:SI (plus:SI (match_dup 1)
9914 (const_int 4))))
9915 (set (reg:SI 11)
9916 (mem:SI (plus:SI (match_dup 1)
9917 (const_int 8))))
9918 (parallel [(set (match_operand 0 "" "")
9919 (call (mem:SI (match_dup 3))
9920 (match_operand 2 "" "")))
9921 (use (reg:SI 2))
9922 (use (reg:SI 11))
9923 (set (reg:SI 2)
9924 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9925 (clobber (scratch:SI))])]
9926 "TARGET_32BIT"
9927 "
9928 { operands[3] = gen_reg_rtx (SImode); }")
9930 (define_expand "call_value_indirect_aix64"
9931 [(set (match_dup 3)
9932 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9933 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9934 (reg:DI 2))
9935 (set (reg:DI 2)
9936 (mem:DI (plus:DI (match_dup 1)
9937 (const_int 8))))
9938 (set (reg:DI 11)
9939 (mem:DI (plus:DI (match_dup 1)
9940 (const_int 16))))
9941 (parallel [(set (match_operand 0 "" "")
9942 (call (mem:SI (match_dup 3))
9943 (match_operand 2 "" "")))
9944 (use (reg:DI 2))
9945 (use (reg:DI 11))
9946 (set (reg:DI 2)
9947 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9948 (clobber (scratch:SI))])]
9949 "TARGET_64BIT"
9950 "
9951 { operands[3] = gen_reg_rtx (DImode); }")
9953 ;; Now the definitions for the call and call_value insns
9954 (define_expand "call"
9955 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9956 (match_operand 1 "" ""))
9957 (use (match_operand 2 "" ""))
9958 (clobber (scratch:SI))])]
9959 ""
9960 "
9961 {
9962 #if TARGET_MACHO
9963 if (flag_pic)
9964 operands[0] = machopic_indirect_call_target (operands[0]);
9965 #endif
9967 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
9968 abort ();
9970 operands[0] = XEXP (operands[0], 0);
9972 if (GET_CODE (operands[0]) != SYMBOL_REF
9973 || (INTVAL (operands[2]) & CALL_LONG) != 0)
9974 {
9975 if (INTVAL (operands[2]) & CALL_LONG)
9976 operands[0] = rs6000_longcall_ref (operands[0]);
9978 if (DEFAULT_ABI == ABI_V4
9979 || DEFAULT_ABI == ABI_AIX_NODESC
9980 || DEFAULT_ABI == ABI_DARWIN)
9981 operands[0] = force_reg (Pmode, operands[0]);
9983 else if (DEFAULT_ABI == ABI_AIX)
9984 {
9985 /* AIX function pointers are really pointers to a three word
9986 area. */
9987 emit_call_insn (TARGET_32BIT
9988 ? gen_call_indirect_aix32 (force_reg (SImode,
9989 operands[0]),
9990 operands[1])
9991 : gen_call_indirect_aix64 (force_reg (DImode,
9992 operands[0]),
9993 operands[1]));
9994 DONE;
9995 }
9996 else
9997 abort ();
9998 }
9999 }")
10001 (define_expand "call_value"
10002 [(parallel [(set (match_operand 0 "" "")
10003 (call (mem:SI (match_operand 1 "address_operand" ""))
10004 (match_operand 2 "" "")))
10005 (use (match_operand 3 "" ""))
10006 (clobber (scratch:SI))])]
10007 ""
10008 "
10009 {
10010 #if TARGET_MACHO
10011 if (flag_pic)
10012 operands[1] = machopic_indirect_call_target (operands[1]);
10013 #endif
10015 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10016 abort ();
10018 operands[1] = XEXP (operands[1], 0);
10020 if (GET_CODE (operands[1]) != SYMBOL_REF
10021 || (INTVAL (operands[3]) & CALL_LONG) != 0)
10022 {
10023 if (INTVAL (operands[3]) & CALL_LONG)
10024 operands[1] = rs6000_longcall_ref (operands[1]);
10026 if (DEFAULT_ABI == ABI_V4
10027 || DEFAULT_ABI == ABI_AIX_NODESC
10028 || DEFAULT_ABI == ABI_DARWIN)
10029 operands[0] = force_reg (Pmode, operands[0]);
10031 else if (DEFAULT_ABI == ABI_AIX)
10032 {
10033 /* AIX function pointers are really pointers to a three word
10034 area. */
10035 emit_call_insn (TARGET_32BIT
10036 ? gen_call_value_indirect_aix32 (operands[0],
10037 force_reg (SImode,
10038 operands[1]),
10039 operands[2])
10040 : gen_call_value_indirect_aix64 (operands[0],
10041 force_reg (DImode,
10042 operands[1]),
10043 operands[2]));
10044 DONE;
10045 }
10046 else
10047 abort ();
10048 }
10049 }")
10051 ;; Call to function in current module. No TOC pointer reload needed.
10052 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10053 ;; either the function was not prototyped, or it was prototyped as a
10054 ;; variable argument function. It is > 0 if FP registers were passed
10055 ;; and < 0 if they were not.
10057 (define_insn "*call_local32"
10058 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10059 (match_operand 1 "" "g,g"))
10060 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10061 (clobber (match_scratch:SI 3 "=l,l"))]
10062 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10063 "*
10064 {
10065 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10066 output_asm_insn (\"crxor 6,6,6\", operands);
10068 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10069 output_asm_insn (\"creqv 6,6,6\", operands);
10071 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10072 }"
10073 [(set_attr "type" "branch")
10074 (set_attr "length" "4,8")])
10076 (define_insn "*call_local64"
10077 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10078 (match_operand 1 "" "g,g"))
10079 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10080 (clobber (match_scratch:SI 3 "=l,l"))]
10081 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10082 "*
10083 {
10084 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10085 output_asm_insn (\"crxor 6,6,6\", operands);
10087 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10088 output_asm_insn (\"creqv 6,6,6\", operands);
10090 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10091 }"
10092 [(set_attr "type" "branch")
10093 (set_attr "length" "4,8")])
10095 (define_insn "*call_value_local32"
10096 [(set (match_operand 0 "" "")
10097 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10098 (match_operand 2 "" "g,g")))
10099 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10100 (clobber (match_scratch:SI 4 "=l,l"))]
10101 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10102 "*
10103 {
10104 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10105 output_asm_insn (\"crxor 6,6,6\", operands);
10107 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10108 output_asm_insn (\"creqv 6,6,6\", operands);
10110 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10111 }"
10112 [(set_attr "type" "branch")
10113 (set_attr "length" "4,8")])
10116 (define_insn "*call_value_local64"
10117 [(set (match_operand 0 "" "")
10118 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10119 (match_operand 2 "" "g,g")))
10120 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10121 (clobber (match_scratch:SI 4 "=l,l"))]
10122 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10123 "*
10124 {
10125 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10126 output_asm_insn (\"crxor 6,6,6\", operands);
10128 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10129 output_asm_insn (\"creqv 6,6,6\", operands);
10131 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10132 }"
10133 [(set_attr "type" "branch")
10134 (set_attr "length" "4,8")])
10136 ;; Call to function which may be in another module. Restore the TOC
10137 ;; pointer (r2) after the call unless this is System V.
10138 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10139 ;; either the function was not prototyped, or it was prototyped as a
10140 ;; variable argument function. It is > 0 if FP registers were passed
10141 ;; and < 0 if they were not.
10143 (define_insn "*call_indirect_nonlocal_aix32"
10144 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10145 (match_operand 1 "" "g"))
10146 (use (reg:SI 2))
10147 (use (reg:SI 11))
10148 (set (reg:SI 2)
10149 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10150 (clobber (match_scratch:SI 2 "=l"))]
10151 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10152 "b%T0l\;{l|lwz} 2,20(1)"
10153 [(set_attr "type" "jmpreg")
10154 (set_attr "length" "8")])
10156 (define_insn "*call_nonlocal_aix32"
10157 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10158 (match_operand 1 "" "g"))
10159 (use (match_operand:SI 2 "immediate_operand" "O"))
10160 (clobber (match_scratch:SI 3 "=l"))]
10161 "TARGET_32BIT
10162 && DEFAULT_ABI == ABI_AIX
10163 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10164 "bl %z0\;%."
10165 [(set_attr "type" "branch")
10166 (set_attr "length" "8")])
10168 (define_insn "*call_indirect_nonlocal_aix64"
10169 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10170 (match_operand 1 "" "g"))
10171 (use (reg:DI 2))
10172 (use (reg:DI 11))
10173 (set (reg:DI 2)
10174 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10175 (clobber (match_scratch:SI 2 "=l"))]
10176 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10177 "b%T0l\;ld 2,40(1)"
10178 [(set_attr "type" "jmpreg")
10179 (set_attr "length" "8")])
10181 (define_insn "*call_nonlocal_aix64"
10182 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10183 (match_operand 1 "" "g"))
10184 (use (match_operand:SI 2 "immediate_operand" "O"))
10185 (clobber (match_scratch:SI 3 "=l"))]
10186 "TARGET_64BIT
10187 && DEFAULT_ABI == ABI_AIX
10188 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10189 "bl %z0\;%."
10190 [(set_attr "type" "branch")
10191 (set_attr "length" "8")])
10193 (define_insn "*call_value_indirect_nonlocal_aix32"
10194 [(set (match_operand 0 "" "")
10195 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10196 (match_operand 2 "" "g")))
10197 (use (reg:SI 2))
10198 (use (reg:SI 11))
10199 (set (reg:SI 2)
10200 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10201 (clobber (match_scratch:SI 3 "=l"))]
10202 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10203 "b%T1l\;{l|lwz} 2,20(1)"
10204 [(set_attr "type" "jmpreg")
10205 (set_attr "length" "8")])
10207 (define_insn "*call_value_nonlocal_aix32"
10208 [(set (match_operand 0 "" "")
10209 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10210 (match_operand 2 "" "g")))
10211 (use (match_operand:SI 3 "immediate_operand" "O"))
10212 (clobber (match_scratch:SI 4 "=l"))]
10213 "TARGET_32BIT
10214 && DEFAULT_ABI == ABI_AIX
10215 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10216 "bl %z1\;%."
10217 [(set_attr "type" "branch")
10218 (set_attr "length" "8")])
10220 (define_insn "*call_value_indirect_nonlocal_aix64"
10221 [(set (match_operand 0 "" "")
10222 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10223 (match_operand 2 "" "g")))
10224 (use (reg:DI 2))
10225 (use (reg:DI 11))
10226 (set (reg:DI 2)
10227 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10228 (clobber (match_scratch:SI 3 "=l"))]
10229 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10230 "b%T1l\;ld 2,40(1)"
10231 [(set_attr "type" "jmpreg")
10232 (set_attr "length" "8")])
10234 (define_insn "*call_value_nonlocal_aix64"
10235 [(set (match_operand 0 "" "")
10236 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10237 (match_operand 2 "" "g")))
10238 (use (match_operand:SI 3 "immediate_operand" "O"))
10239 (clobber (match_scratch:SI 4 "=l"))]
10240 "TARGET_64BIT
10241 && DEFAULT_ABI == ABI_AIX
10242 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10243 "bl %z1\;%."
10244 [(set_attr "type" "branch")
10245 (set_attr "length" "8")])
10247 ;; A function pointer under System V is just a normal pointer
10248 ;; operands[0] is the function pointer
10249 ;; operands[1] is the stack size to clean up
10250 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10251 ;; which indicates how to set cr1
10253 (define_insn "*call_indirect_nonlocal_sysv"
10254 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10255 (match_operand 1 "" "g,g"))
10256 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10257 (clobber (match_scratch:SI 3 "=l,l"))]
10258 "DEFAULT_ABI == ABI_AIX_NODESC
10259 || DEFAULT_ABI == ABI_V4
10260 || DEFAULT_ABI == ABI_DARWIN"
10261 {
10262 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10263 output_asm_insn ("crxor 6,6,6", operands);
10265 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10266 output_asm_insn ("creqv 6,6,6", operands);
10268 return "b%T0l";
10269 }
10270 [(set_attr "type" "jmpreg,jmpreg")
10271 (set_attr "length" "4,8")])
10273 (define_insn "*call_nonlocal_sysv"
10274 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10275 (match_operand 1 "" "g,g"))
10276 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10277 (clobber (match_scratch:SI 3 "=l,l"))]
10278 "(DEFAULT_ABI == ABI_AIX_NODESC
10279 || DEFAULT_ABI == ABI_V4
10280 || DEFAULT_ABI == ABI_DARWIN)
10281 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10282 {
10283 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10284 output_asm_insn ("crxor 6,6,6", operands);
10286 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10287 output_asm_insn ("creqv 6,6,6", operands);
10289 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10290 }
10291 [(set_attr "type" "branch,branch")
10292 (set_attr "length" "4,8")])
10294 (define_insn "*call_value_indirect_nonlocal_sysv"
10295 [(set (match_operand 0 "" "")
10296 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10297 (match_operand 2 "" "g,g")))
10298 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10299 (clobber (match_scratch:SI 4 "=l,l"))]
10300 "DEFAULT_ABI == ABI_AIX_NODESC
10301 || DEFAULT_ABI == ABI_V4
10302 || DEFAULT_ABI == ABI_DARWIN"
10303 {
10304 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10305 output_asm_insn ("crxor 6,6,6", operands);
10307 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10308 output_asm_insn ("creqv 6,6,6", operands);
10310 return "b%T1l";
10311 }
10312 [(set_attr "type" "jmpreg,jmpreg")
10313 (set_attr "length" "4,8")])
10315 (define_insn "*call_value_nonlocal_sysv"
10316 [(set (match_operand 0 "" "")
10317 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10318 (match_operand 2 "" "g,g")))
10319 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10320 (clobber (match_scratch:SI 4 "=l,l"))]
10321 "(DEFAULT_ABI == ABI_AIX_NODESC
10322 || DEFAULT_ABI == ABI_V4
10323 || DEFAULT_ABI == ABI_DARWIN)
10324 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10325 {
10326 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10327 output_asm_insn ("crxor 6,6,6", operands);
10329 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10330 output_asm_insn ("creqv 6,6,6", operands);
10332 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10333 }
10334 [(set_attr "type" "branch,branch")
10335 (set_attr "length" "4,8")])
10337 ;; Call subroutine returning any type.
10338 (define_expand "untyped_call"
10339 [(parallel [(call (match_operand 0 "" "")
10340 (const_int 0))
10341 (match_operand 1 "" "")
10342 (match_operand 2 "" "")])]
10343 ""
10344 "
10345 {
10346 int i;
10348 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10350 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10351 {
10352 rtx set = XVECEXP (operands[2], 0, i);
10353 emit_move_insn (SET_DEST (set), SET_SRC (set));
10354 }
10356 /* The optimizer does not know that the call sets the function value
10357 registers we stored in the result block. We avoid problems by
10358 claiming that all hard registers are used and clobbered at this
10359 point. */
10360 emit_insn (gen_blockage ());
10362 DONE;
10363 }")
10365 ;; sibling call patterns
10366 (define_expand "sibcall"
10367 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10368 (match_operand 1 "" ""))
10369 (use (match_operand 2 "" ""))
10370 (use (match_operand 3 "" ""))
10371 (return)])]
10372 ""
10373 "
10374 {
10375 #if TARGET_MACHO
10376 if (flag_pic)
10377 operands[0] = machopic_indirect_call_target (operands[0]);
10378 #endif
10380 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10381 abort ();
10383 operands[0] = XEXP (operands[0], 0);
10384 operands[3] = gen_reg_rtx (SImode);
10386 }")
10388 ;; this and similar patterns must be marked as using LR, otherwise
10389 ;; dataflow will try to delete the store into it. This is true
10390 ;; even when the actual reg to jump to is in CTR, when LR was
10391 ;; saved and restored around the PIC-setting BCL.
10392 (define_insn "*sibcall_local32"
10393 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10394 (match_operand 1 "" "g,g"))
10395 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10396 (use (match_operand:SI 3 "register_operand" "l,l"))
10397 (return)]
10398 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10399 "*
10400 {
10401 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10402 output_asm_insn (\"crxor 6,6,6\", operands);
10404 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10405 output_asm_insn (\"creqv 6,6,6\", operands);
10407 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10408 }"
10409 [(set_attr "type" "branch")
10410 (set_attr "length" "4,8")])
10412 (define_insn "*sibcall_local64"
10413 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10414 (match_operand 1 "" "g,g"))
10415 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10416 (use (match_operand:SI 3 "register_operand" "l,l"))
10417 (return)]
10418 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10419 "*
10420 {
10421 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10422 output_asm_insn (\"crxor 6,6,6\", operands);
10424 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10425 output_asm_insn (\"creqv 6,6,6\", operands);
10427 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10428 }"
10429 [(set_attr "type" "branch")
10430 (set_attr "length" "4,8")])
10432 (define_insn "*sibcall_value_local32"
10433 [(set (match_operand 0 "" "")
10434 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10435 (match_operand 2 "" "g,g")))
10436 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10437 (use (match_operand:SI 4 "register_operand" "l,l"))
10438 (return)]
10439 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10440 "*
10441 {
10442 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10443 output_asm_insn (\"crxor 6,6,6\", operands);
10445 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10446 output_asm_insn (\"creqv 6,6,6\", operands);
10448 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10449 }"
10450 [(set_attr "type" "branch")
10451 (set_attr "length" "4,8")])
10454 (define_insn "*sibcall_value_local64"
10455 [(set (match_operand 0 "" "")
10456 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10457 (match_operand 2 "" "g,g")))
10458 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10459 (use (match_operand:SI 4 "register_operand" "l,l"))
10460 (return)]
10461 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10462 "*
10463 {
10464 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10465 output_asm_insn (\"crxor 6,6,6\", operands);
10467 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10468 output_asm_insn (\"creqv 6,6,6\", operands);
10470 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10471 }"
10472 [(set_attr "type" "branch")
10473 (set_attr "length" "4,8")])
10475 (define_insn "*sibcall_nonlocal_aix32"
10476 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10477 (match_operand 1 "" "g"))
10478 (use (match_operand:SI 2 "immediate_operand" "O"))
10479 (use (match_operand:SI 3 "register_operand" "l"))
10480 (return)]
10481 "TARGET_32BIT
10482 && DEFAULT_ABI == ABI_AIX
10483 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10484 "b %z0"
10485 [(set_attr "type" "branch")
10486 (set_attr "length" "4")])
10488 (define_insn "*sibcall_nonlocal_aix64"
10489 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10490 (match_operand 1 "" "g"))
10491 (use (match_operand:SI 2 "immediate_operand" "O"))
10492 (use (match_operand:SI 3 "register_operand" "l"))
10493 (return)]
10494 "TARGET_64BIT
10495 && DEFAULT_ABI == ABI_AIX
10496 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10497 "b %z0"
10498 [(set_attr "type" "branch")
10499 (set_attr "length" "4")])
10501 (define_insn "*sibcall_value_nonlocal_aix32"
10502 [(set (match_operand 0 "" "")
10503 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10504 (match_operand 2 "" "g")))
10505 (use (match_operand:SI 3 "immediate_operand" "O"))
10506 (use (match_operand:SI 4 "register_operand" "l"))
10507 (return)]
10508 "TARGET_32BIT
10509 && DEFAULT_ABI == ABI_AIX
10510 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10511 "b %z1"
10512 [(set_attr "type" "branch")
10513 (set_attr "length" "4")])
10515 (define_insn "*sibcall_value_nonlocal_aix64"
10516 [(set (match_operand 0 "" "")
10517 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10518 (match_operand 2 "" "g")))
10519 (use (match_operand:SI 3 "immediate_operand" "O"))
10520 (use (match_operand:SI 4 "register_operand" "l"))
10521 (return)]
10522 "TARGET_64BIT
10523 && DEFAULT_ABI == ABI_AIX
10524 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10525 "b %z1"
10526 [(set_attr "type" "branch")
10527 (set_attr "length" "4")])
10529 (define_insn "*sibcall_nonlocal_sysv"
10530 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10531 (match_operand 1 "" ""))
10532 (use (match_operand 2 "immediate_operand" "O,n"))
10533 (use (match_operand:SI 3 "register_operand" "l,l"))
10534 (return)]
10535 "(DEFAULT_ABI == ABI_DARWIN
10536 || DEFAULT_ABI == ABI_V4
10537 || DEFAULT_ABI == ABI_AIX_NODESC)
10538 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10539 "*
10540 {
10541 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10542 output_asm_insn (\"crxor 6,6,6\", operands);
10544 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10545 output_asm_insn (\"creqv 6,6,6\", operands);
10547 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10548 }"
10549 [(set_attr "type" "branch,branch")
10550 (set_attr "length" "4,8")])
10552 (define_expand "sibcall_value"
10553 [(parallel [(set (match_operand 0 "register_operand" "")
10554 (call (mem:SI (match_operand 1 "address_operand" ""))
10555 (match_operand 2 "" "")))
10556 (use (match_operand 3 "" ""))
10557 (use (match_operand 4 "" ""))
10558 (return)])]
10559 ""
10560 "
10561 {
10562 #if TARGET_MACHO
10563 if (flag_pic)
10564 operands[1] = machopic_indirect_call_target (operands[1]);
10565 #endif
10567 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10568 abort ();
10570 operands[1] = XEXP (operands[1], 0);
10571 operands[4] = gen_reg_rtx (SImode);
10573 }")
10575 (define_insn "*sibcall_value_nonlocal_sysv"
10576 [(set (match_operand 0 "" "")
10577 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10578 (match_operand 2 "" "")))
10579 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10580 (use (match_operand:SI 4 "register_operand" "l,l"))
10581 (return)]
10582 "(DEFAULT_ABI == ABI_DARWIN
10583 || DEFAULT_ABI == ABI_V4
10584 || DEFAULT_ABI == ABI_AIX_NODESC)
10585 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10586 "*
10587 {
10588 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10589 output_asm_insn (\"crxor 6,6,6\", operands);
10591 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10592 output_asm_insn (\"creqv 6,6,6\", operands);
10594 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10595 }"
10596 [(set_attr "type" "branch,branch")
10597 (set_attr "length" "4,8")])
10599 (define_expand "sibcall_epilogue"
10600 [(use (const_int 0))]
10601 "TARGET_SCHED_PROLOG"
10602 "
10603 {
10604 rs6000_emit_epilogue (TRUE);
10605 DONE;
10606 }")
10608 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10609 ;; all of memory. This blocks insns from being moved across this point.
10611 (define_insn "blockage"
10612 [(unspec_volatile [(const_int 0)] 0)]
10613 ""
10614 "")
10615 \f
10616 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10617 ;; signed & unsigned, and one type of branch.
10618 ;;
10619 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10620 ;; insns, and branches. We store the operands of compares until we see
10621 ;; how it is used.
10622 (define_expand "cmpsi"
10623 [(set (cc0)
10624 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10625 (match_operand:SI 1 "reg_or_short_operand" "")))]
10626 ""
10627 "
10628 {
10629 /* Take care of the possibility that operands[1] might be negative but
10630 this might be a logical operation. That insn doesn't exist. */
10631 if (GET_CODE (operands[1]) == CONST_INT
10632 && INTVAL (operands[1]) < 0)
10633 operands[1] = force_reg (SImode, operands[1]);
10635 rs6000_compare_op0 = operands[0];
10636 rs6000_compare_op1 = operands[1];
10637 rs6000_compare_fp_p = 0;
10638 DONE;
10639 }")
10641 (define_expand "cmpdi"
10642 [(set (cc0)
10643 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10644 (match_operand:DI 1 "reg_or_short_operand" "")))]
10645 "TARGET_POWERPC64"
10646 "
10647 {
10648 /* Take care of the possibility that operands[1] might be negative but
10649 this might be a logical operation. That insn doesn't exist. */
10650 if (GET_CODE (operands[1]) == CONST_INT
10651 && INTVAL (operands[1]) < 0)
10652 operands[1] = force_reg (DImode, operands[1]);
10654 rs6000_compare_op0 = operands[0];
10655 rs6000_compare_op1 = operands[1];
10656 rs6000_compare_fp_p = 0;
10657 DONE;
10658 }")
10660 (define_expand "cmpsf"
10661 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10662 (match_operand:SF 1 "gpc_reg_operand" "")))]
10663 "TARGET_HARD_FLOAT"
10664 "
10665 {
10666 rs6000_compare_op0 = operands[0];
10667 rs6000_compare_op1 = operands[1];
10668 rs6000_compare_fp_p = 1;
10669 DONE;
10670 }")
10672 (define_expand "cmpdf"
10673 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10674 (match_operand:DF 1 "gpc_reg_operand" "")))]
10675 "TARGET_HARD_FLOAT && TARGET_FPRS"
10676 "
10677 {
10678 rs6000_compare_op0 = operands[0];
10679 rs6000_compare_op1 = operands[1];
10680 rs6000_compare_fp_p = 1;
10681 DONE;
10682 }")
10684 (define_expand "cmptf"
10685 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10686 (match_operand:TF 1 "gpc_reg_operand" "")))]
10687 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
10688 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10689 "
10690 {
10691 rs6000_compare_op0 = operands[0];
10692 rs6000_compare_op1 = operands[1];
10693 rs6000_compare_fp_p = 1;
10694 DONE;
10695 }")
10697 (define_expand "beq"
10698 [(use (match_operand 0 "" ""))]
10699 ""
10700 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10702 (define_expand "bne"
10703 [(use (match_operand 0 "" ""))]
10704 ""
10705 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10707 (define_expand "bge"
10708 [(use (match_operand 0 "" ""))]
10709 ""
10710 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10712 (define_expand "bgt"
10713 [(use (match_operand 0 "" ""))]
10714 ""
10715 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10717 (define_expand "ble"
10718 [(use (match_operand 0 "" ""))]
10719 ""
10720 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10722 (define_expand "blt"
10723 [(use (match_operand 0 "" ""))]
10724 ""
10725 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10727 (define_expand "bgeu"
10728 [(use (match_operand 0 "" ""))]
10729 ""
10730 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10732 (define_expand "bgtu"
10733 [(use (match_operand 0 "" ""))]
10734 ""
10735 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10737 (define_expand "bleu"
10738 [(use (match_operand 0 "" ""))]
10739 ""
10740 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10742 (define_expand "bltu"
10743 [(use (match_operand 0 "" ""))]
10744 ""
10745 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10747 (define_expand "bunordered"
10748 [(use (match_operand 0 "" ""))]
10749 ""
10750 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10752 (define_expand "bordered"
10753 [(use (match_operand 0 "" ""))]
10754 ""
10755 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10757 (define_expand "buneq"
10758 [(use (match_operand 0 "" ""))]
10759 ""
10760 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10762 (define_expand "bunge"
10763 [(use (match_operand 0 "" ""))]
10764 ""
10765 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10767 (define_expand "bungt"
10768 [(use (match_operand 0 "" ""))]
10769 ""
10770 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10772 (define_expand "bunle"
10773 [(use (match_operand 0 "" ""))]
10774 ""
10775 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10777 (define_expand "bunlt"
10778 [(use (match_operand 0 "" ""))]
10779 ""
10780 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10782 (define_expand "bltgt"
10783 [(use (match_operand 0 "" ""))]
10784 ""
10785 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10787 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10788 ;; For SEQ, likewise, except that comparisons with zero should be done
10789 ;; with an scc insns. However, due to the order that combine see the
10790 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10791 ;; the cases we don't want to handle.
10792 (define_expand "seq"
10793 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10794 ""
10795 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10797 (define_expand "sne"
10798 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10799 ""
10800 "
10801 {
10802 if (! rs6000_compare_fp_p)
10803 FAIL;
10805 rs6000_emit_sCOND (NE, operands[0]);
10806 DONE;
10807 }")
10809 ;; A > 0 is best done using the portable sequence, so fail in that case.
10810 (define_expand "sgt"
10811 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10812 ""
10813 "
10814 {
10815 if (! rs6000_compare_fp_p
10816 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10817 FAIL;
10819 rs6000_emit_sCOND (GT, operands[0]);
10820 DONE;
10821 }")
10823 ;; A < 0 is best done in the portable way for A an integer.
10824 (define_expand "slt"
10825 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10826 ""
10827 "
10828 {
10829 if (! rs6000_compare_fp_p
10830 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10831 FAIL;
10833 rs6000_emit_sCOND (LT, operands[0]);
10834 DONE;
10835 }")
10837 ;; A >= 0 is best done the portable way for A an integer.
10838 (define_expand "sge"
10839 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10840 ""
10841 "
10842 {
10843 if (! rs6000_compare_fp_p
10844 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10845 FAIL;
10847 rs6000_emit_sCOND (GE, operands[0]);
10848 DONE;
10849 }")
10851 ;; A <= 0 is best done the portable way for A an integer.
10852 (define_expand "sle"
10853 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10854 ""
10855 "
10856 {
10857 if (! rs6000_compare_fp_p
10858 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10859 FAIL;
10861 rs6000_emit_sCOND (LE, operands[0]);
10862 DONE;
10863 }")
10865 (define_expand "sgtu"
10866 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10867 ""
10868 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10870 (define_expand "sltu"
10871 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10872 ""
10873 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10875 (define_expand "sgeu"
10876 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10877 ""
10878 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10880 (define_expand "sleu"
10881 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10882 ""
10883 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10884 \f
10885 ;; Here are the actual compare insns.
10886 (define_insn "*cmpsi_internal1"
10887 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10888 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10889 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10890 ""
10891 "{cmp%I2|cmpw%I2} %0,%1,%2"
10892 [(set_attr "type" "cmp")])
10894 (define_insn "*cmpdi_internal1"
10895 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10896 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
10897 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10898 "TARGET_POWERPC64"
10899 "cmpd%I2 %0,%1,%2"
10900 [(set_attr "type" "cmp")])
10902 ;; If we are comparing a register for equality with a large constant,
10903 ;; we can do this with an XOR followed by a compare. But we need a scratch
10904 ;; register for the result of the XOR.
10906 (define_split
10907 [(set (match_operand:CC 0 "cc_reg_operand" "")
10908 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10909 (match_operand:SI 2 "non_short_cint_operand" "")))
10910 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10911 "find_single_use (operands[0], insn, 0)
10912 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10913 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10914 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10915 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10916 "
10917 {
10918 /* Get the constant we are comparing against, C, and see what it looks like
10919 sign-extended to 16 bits. Then see what constant could be XOR'ed
10920 with C to get the sign-extended value. */
10922 HOST_WIDE_INT c = INTVAL (operands[2]);
10923 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10924 HOST_WIDE_INT xorv = c ^ sextc;
10926 operands[4] = GEN_INT (xorv);
10927 operands[5] = GEN_INT (sextc);
10928 }")
10930 (define_insn "*cmpsi_internal2"
10931 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10932 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10933 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10934 ""
10935 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10936 [(set_attr "type" "cmp")])
10938 (define_insn "*cmpdi_internal2"
10939 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10940 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10941 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10942 ""
10943 "cmpld%I2 %0,%1,%b2"
10944 [(set_attr "type" "cmp")])
10946 ;; The following two insns don't exist as single insns, but if we provide
10947 ;; them, we can swap an add and compare, which will enable us to overlap more
10948 ;; of the required delay between a compare and branch. We generate code for
10949 ;; them by splitting.
10951 (define_insn ""
10952 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10953 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10954 (match_operand:SI 2 "short_cint_operand" "i")))
10955 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10956 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10957 ""
10958 "#"
10959 [(set_attr "length" "8")])
10961 (define_insn ""
10962 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10963 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10964 (match_operand:SI 2 "u_short_cint_operand" "i")))
10965 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10966 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10967 ""
10968 "#"
10969 [(set_attr "length" "8")])
10971 (define_split
10972 [(set (match_operand:CC 3 "cc_reg_operand" "")
10973 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10974 (match_operand:SI 2 "short_cint_operand" "")))
10975 (set (match_operand:SI 0 "gpc_reg_operand" "")
10976 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10977 ""
10978 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10979 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10981 (define_split
10982 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10983 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10984 (match_operand:SI 2 "u_short_cint_operand" "")))
10985 (set (match_operand:SI 0 "gpc_reg_operand" "")
10986 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10987 ""
10988 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10989 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10991 (define_insn "*cmpsf_internal1"
10992 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10993 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10994 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10995 "TARGET_HARD_FLOAT && TARGET_FPRS"
10996 "fcmpu %0,%1,%2"
10997 [(set_attr "type" "fpcompare")])
10999 (define_insn "*cmpdf_internal1"
11000 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11001 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11002 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11003 "TARGET_HARD_FLOAT && TARGET_FPRS"
11004 "fcmpu %0,%1,%2"
11005 [(set_attr "type" "fpcompare")])
11007 ;; Only need to compare second words if first words equal
11008 (define_insn "*cmptf_internal1"
11009 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11010 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11011 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11012 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
11013 && TARGET_LONG_DOUBLE_128"
11014 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2"
11015 [(set_attr "type" "fpcompare")
11016 (set_attr "length" "12")])
11017 \f
11018 ;; Now we have the scc insns. We can do some combinations because of the
11019 ;; way the machine works.
11020 ;;
11021 ;; Note that this is probably faster if we can put an insn between the
11022 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11023 ;; cases the insns below which don't use an intermediate CR field will
11024 ;; be used instead.
11025 (define_insn ""
11026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11027 (match_operator:SI 1 "scc_comparison_operator"
11028 [(match_operand 2 "cc_reg_operand" "y")
11029 (const_int 0)]))]
11030 ""
11031 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11032 [(set_attr "type" "mfcr")
11033 (set_attr "length" "12")])
11035 ;; Same as above, but get the OV/ORDERED bit.
11036 (define_insn "move_from_CR_ov_bit"
11037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11038 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))]
11039 "TARGET_ISEL"
11040 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11041 [(set_attr "type" "mfcr")
11042 (set_attr "length" "12")])
11044 (define_insn ""
11045 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11046 (match_operator:DI 1 "scc_comparison_operator"
11047 [(match_operand 2 "cc_reg_operand" "y")
11048 (const_int 0)]))]
11049 "TARGET_POWERPC64"
11050 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11051 [(set_attr "type" "mfcr")
11052 (set_attr "length" "12")])
11054 (define_insn ""
11055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11056 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11057 [(match_operand 2 "cc_reg_operand" "y,y")
11058 (const_int 0)])
11059 (const_int 0)))
11060 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11061 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11062 "! TARGET_POWERPC64"
11063 "@
11064 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
11065 #"
11066 [(set_attr "type" "delayed_compare")
11067 (set_attr "length" "12,16")])
11069 (define_split
11070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11071 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11072 [(match_operand 2 "cc_reg_operand" "")
11073 (const_int 0)])
11074 (const_int 0)))
11075 (set (match_operand:SI 3 "gpc_reg_operand" "")
11076 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11077 "! TARGET_POWERPC64 && reload_completed"
11078 [(set (match_dup 3)
11079 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11080 (set (match_dup 0)
11081 (compare:CC (match_dup 3)
11082 (const_int 0)))]
11083 "")
11085 (define_insn ""
11086 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11087 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11088 [(match_operand 2 "cc_reg_operand" "y")
11089 (const_int 0)])
11090 (match_operand:SI 3 "const_int_operand" "n")))]
11091 ""
11092 "*
11093 {
11094 int is_bit = ccr_bit (operands[1], 1);
11095 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11096 int count;
11098 if (is_bit >= put_bit)
11099 count = is_bit - put_bit;
11100 else
11101 count = 32 - (put_bit - is_bit);
11103 operands[4] = GEN_INT (count);
11104 operands[5] = GEN_INT (put_bit);
11106 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11107 }"
11108 [(set_attr "type" "mfcr")
11109 (set_attr "length" "12")])
11111 (define_insn ""
11112 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11113 (compare:CC
11114 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11115 [(match_operand 2 "cc_reg_operand" "y,y")
11116 (const_int 0)])
11117 (match_operand:SI 3 "const_int_operand" "n,n"))
11118 (const_int 0)))
11119 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11120 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11121 (match_dup 3)))]
11122 ""
11123 "*
11124 {
11125 int is_bit = ccr_bit (operands[1], 1);
11126 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11127 int count;
11129 /* Force split for non-cc0 compare. */
11130 if (which_alternative == 1)
11131 return \"#\";
11133 if (is_bit >= put_bit)
11134 count = is_bit - put_bit;
11135 else
11136 count = 32 - (put_bit - is_bit);
11138 operands[5] = GEN_INT (count);
11139 operands[6] = GEN_INT (put_bit);
11141 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11142 }"
11143 [(set_attr "type" "delayed_compare")
11144 (set_attr "length" "12,16")])
11146 (define_split
11147 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11148 (compare:CC
11149 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11150 [(match_operand 2 "cc_reg_operand" "")
11151 (const_int 0)])
11152 (match_operand:SI 3 "const_int_operand" ""))
11153 (const_int 0)))
11154 (set (match_operand:SI 4 "gpc_reg_operand" "")
11155 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11156 (match_dup 3)))]
11157 "reload_completed"
11158 [(set (match_dup 4)
11159 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11160 (match_dup 3)))
11161 (set (match_dup 0)
11162 (compare:CC (match_dup 4)
11163 (const_int 0)))]
11164 "")
11166 ;; There is a 3 cycle delay between consecutive mfcr instructions
11167 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11169 (define_peephole
11170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11171 (match_operator:SI 1 "scc_comparison_operator"
11172 [(match_operand 2 "cc_reg_operand" "y")
11173 (const_int 0)]))
11174 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11175 (match_operator:SI 4 "scc_comparison_operator"
11176 [(match_operand 5 "cc_reg_operand" "y")
11177 (const_int 0)]))]
11178 "REGNO (operands[2]) != REGNO (operands[5])"
11179 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11180 [(set_attr "type" "mfcr")
11181 (set_attr "length" "20")])
11183 (define_peephole
11184 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11185 (match_operator:DI 1 "scc_comparison_operator"
11186 [(match_operand 2 "cc_reg_operand" "y")
11187 (const_int 0)]))
11188 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11189 (match_operator:DI 4 "scc_comparison_operator"
11190 [(match_operand 5 "cc_reg_operand" "y")
11191 (const_int 0)]))]
11192 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11193 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11194 [(set_attr "type" "mfcr")
11195 (set_attr "length" "20")])
11197 ;; There are some scc insns that can be done directly, without a compare.
11198 ;; These are faster because they don't involve the communications between
11199 ;; the FXU and branch units. In fact, we will be replacing all of the
11200 ;; integer scc insns here or in the portable methods in emit_store_flag.
11201 ;;
11202 ;; Also support (neg (scc ..)) since that construct is used to replace
11203 ;; branches, (plus (scc ..) ..) since that construct is common and
11204 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11205 ;; cases where it is no more expensive than (neg (scc ..)).
11207 ;; Have reload force a constant into a register for the simple insns that
11208 ;; otherwise won't accept constants. We do this because it is faster than
11209 ;; the cmp/mfcr sequence we would otherwise generate.
11211 (define_insn ""
11212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11213 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11214 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11215 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11216 "! TARGET_POWERPC64"
11217 "@
11218 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11219 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11220 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11221 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11222 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11223 [(set_attr "length" "12,8,12,12,12")])
11225 (define_insn ""
11226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11227 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11228 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11229 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11230 "TARGET_POWERPC64"
11231 "@
11232 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11233 subfic %3,%1,0\;adde %0,%3,%1
11234 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11235 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11236 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11237 [(set_attr "length" "12,8,12,12,12")])
11239 (define_insn ""
11240 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11241 (compare:CC
11242 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11243 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11244 (const_int 0)))
11245 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11246 (eq:SI (match_dup 1) (match_dup 2)))
11247 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11248 "! TARGET_POWERPC64"
11249 "@
11250 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11251 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11252 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11253 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11254 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11255 #
11256 #
11257 #
11258 #
11259 #"
11260 [(set_attr "type" "compare")
11261 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11263 (define_split
11264 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11265 (compare:CC
11266 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11267 (match_operand:SI 2 "reg_or_cint_operand" ""))
11268 (const_int 0)))
11269 (set (match_operand:SI 0 "gpc_reg_operand" "")
11270 (eq:SI (match_dup 1) (match_dup 2)))
11271 (clobber (match_scratch:SI 3 ""))]
11272 "! TARGET_POWERPC64 && reload_completed"
11273 [(parallel [(set (match_dup 0)
11274 (eq:SI (match_dup 1) (match_dup 2)))
11275 (clobber (match_dup 3))])
11276 (set (match_dup 4)
11277 (compare:CC (match_dup 0)
11278 (const_int 0)))]
11279 "")
11281 (define_insn ""
11282 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11283 (compare:CC
11284 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11285 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11286 (const_int 0)))
11287 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11288 (eq:DI (match_dup 1) (match_dup 2)))
11289 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11290 "TARGET_POWERPC64"
11291 "@
11292 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11293 subfic %3,%1,0\;adde. %0,%3,%1
11294 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11295 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11296 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11297 #
11298 #
11299 #
11300 #
11301 #"
11302 [(set_attr "type" "compare")
11303 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11305 (define_split
11306 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11307 (compare:CC
11308 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11309 (match_operand:DI 2 "reg_or_cint_operand" ""))
11310 (const_int 0)))
11311 (set (match_operand:DI 0 "gpc_reg_operand" "")
11312 (eq:DI (match_dup 1) (match_dup 2)))
11313 (clobber (match_scratch:DI 3 ""))]
11314 "TARGET_POWERPC64 && reload_completed"
11315 [(parallel [(set (match_dup 0)
11316 (eq:DI (match_dup 1) (match_dup 2)))
11317 (clobber (match_dup 3))])
11318 (set (match_dup 4)
11319 (compare:CC (match_dup 0)
11320 (const_int 0)))]
11321 "")
11323 ;; We have insns of the form shown by the first define_insn below. If
11324 ;; there is something inside the comparison operation, we must split it.
11325 (define_split
11326 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11327 (plus:SI (match_operator 1 "comparison_operator"
11328 [(match_operand:SI 2 "" "")
11329 (match_operand:SI 3
11330 "reg_or_cint_operand" "")])
11331 (match_operand:SI 4 "gpc_reg_operand" "")))
11332 (clobber (match_operand:SI 5 "register_operand" ""))]
11333 "! gpc_reg_operand (operands[2], SImode)"
11334 [(set (match_dup 5) (match_dup 2))
11335 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11336 (match_dup 4)))])
11338 (define_insn ""
11339 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11340 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11341 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11342 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11343 "! TARGET_POWERPC64"
11344 "@
11345 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11346 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11347 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11348 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11349 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11350 [(set_attr "length" "12,8,12,12,12")])
11352 (define_insn ""
11353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11354 (compare:CC
11355 (plus:SI
11356 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11357 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11358 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11359 (const_int 0)))
11360 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11361 "! TARGET_POWERPC64"
11362 "@
11363 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11364 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11365 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11366 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11367 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11368 #
11369 #
11370 #
11371 #
11372 #"
11373 [(set_attr "type" "compare")
11374 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11376 (define_split
11377 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11378 (compare:CC
11379 (plus:SI
11380 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11381 (match_operand:SI 2 "reg_or_cint_operand" ""))
11382 (match_operand:SI 3 "gpc_reg_operand" ""))
11383 (const_int 0)))
11384 (clobber (match_scratch:SI 4 ""))]
11385 "! TARGET_POWERPC64 && reload_completed"
11386 [(set (match_dup 4)
11387 (plus:SI (eq:SI (match_dup 1)
11388 (match_dup 2))
11389 (match_dup 3)))
11390 (set (match_dup 0)
11391 (compare:CC (match_dup 4)
11392 (const_int 0)))]
11393 "")
11395 (define_insn ""
11396 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11397 (compare:CC
11398 (plus:SI
11399 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11400 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11401 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11402 (const_int 0)))
11403 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11404 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11405 "! TARGET_POWERPC64"
11406 "@
11407 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11408 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11409 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11410 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11411 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11412 #
11413 #
11414 #
11415 #
11416 #"
11417 [(set_attr "type" "compare")
11418 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11420 (define_split
11421 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11422 (compare:CC
11423 (plus:SI
11424 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11425 (match_operand:SI 2 "reg_or_cint_operand" ""))
11426 (match_operand:SI 3 "gpc_reg_operand" ""))
11427 (const_int 0)))
11428 (set (match_operand:SI 0 "gpc_reg_operand" "")
11429 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11430 "! TARGET_POWERPC64 && reload_completed"
11431 [(set (match_dup 0)
11432 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11433 (set (match_dup 4)
11434 (compare:CC (match_dup 0)
11435 (const_int 0)))]
11436 "")
11438 (define_insn ""
11439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11440 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11441 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11442 "! TARGET_POWERPC64"
11443 "@
11444 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11445 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11446 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11447 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11448 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11449 [(set_attr "length" "12,8,12,12,12")])
11451 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11452 ;; since it nabs/sr is just as fast.
11453 (define_insn "*ne0"
11454 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11455 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11456 (const_int 31)))
11457 (clobber (match_scratch:SI 2 "=&r"))]
11458 "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL"
11459 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11460 [(set_attr "length" "8")])
11462 (define_insn ""
11463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11464 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11465 (const_int 63)))
11466 (clobber (match_scratch:DI 2 "=&r"))]
11467 "TARGET_POWERPC64"
11468 "addic %2,%1,-1\;subfe %0,%2,%1"
11469 [(set_attr "length" "8")])
11471 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11472 (define_insn ""
11473 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11474 (plus:SI (lshiftrt:SI
11475 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11476 (const_int 31))
11477 (match_operand:SI 2 "gpc_reg_operand" "r")))
11478 (clobber (match_scratch:SI 3 "=&r"))]
11479 "! TARGET_POWERPC64"
11480 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11481 [(set_attr "length" "8")])
11483 (define_insn ""
11484 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11485 (plus:DI (lshiftrt:DI
11486 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11487 (const_int 63))
11488 (match_operand:DI 2 "gpc_reg_operand" "r")))
11489 (clobber (match_scratch:DI 3 "=&r"))]
11490 "TARGET_POWERPC64"
11491 "addic %3,%1,-1\;addze %0,%2"
11492 [(set_attr "length" "8")])
11494 (define_insn ""
11495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11496 (compare:CC
11497 (plus:SI (lshiftrt:SI
11498 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11499 (const_int 31))
11500 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11501 (const_int 0)))
11502 (clobber (match_scratch:SI 3 "=&r,&r"))
11503 (clobber (match_scratch:SI 4 "=X,&r"))]
11504 "! TARGET_POWERPC64"
11505 "@
11506 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11507 #"
11508 [(set_attr "type" "compare")
11509 (set_attr "length" "8,12")])
11511 (define_split
11512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11513 (compare:CC
11514 (plus:SI (lshiftrt:SI
11515 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11516 (const_int 31))
11517 (match_operand:SI 2 "gpc_reg_operand" ""))
11518 (const_int 0)))
11519 (clobber (match_scratch:SI 3 ""))
11520 (clobber (match_scratch:SI 4 ""))]
11521 "! TARGET_POWERPC64 && reload_completed"
11522 [(parallel [(set (match_dup 3)
11523 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11524 (const_int 31))
11525 (match_dup 2)))
11526 (clobber (match_dup 4))])
11527 (set (match_dup 0)
11528 (compare:CC (match_dup 3)
11529 (const_int 0)))]
11530 "")
11532 (define_insn ""
11533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11534 (compare:CC
11535 (plus:DI (lshiftrt:DI
11536 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11537 (const_int 63))
11538 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11539 (const_int 0)))
11540 (clobber (match_scratch:DI 3 "=&r,&r"))]
11541 "TARGET_POWERPC64"
11542 "@
11543 addic %3,%1,-1\;addze. %3,%2
11544 #"
11545 [(set_attr "type" "compare")
11546 (set_attr "length" "8,12")])
11548 (define_split
11549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11550 (compare:CC
11551 (plus:DI (lshiftrt:DI
11552 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11553 (const_int 63))
11554 (match_operand:DI 2 "gpc_reg_operand" ""))
11555 (const_int 0)))
11556 (clobber (match_scratch:DI 3 ""))]
11557 "TARGET_POWERPC64 && reload_completed"
11558 [(set (match_dup 3)
11559 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11560 (const_int 63))
11561 (match_dup 2)))
11562 (set (match_dup 0)
11563 (compare:CC (match_dup 3)
11564 (const_int 0)))]
11565 "")
11567 (define_insn ""
11568 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11569 (compare:CC
11570 (plus:SI (lshiftrt:SI
11571 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11572 (const_int 31))
11573 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11574 (const_int 0)))
11575 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11576 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11577 (match_dup 2)))
11578 (clobber (match_scratch:SI 3 "=&r,&r"))]
11579 "! TARGET_POWERPC64"
11580 "@
11581 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11582 #"
11583 [(set_attr "type" "compare")
11584 (set_attr "length" "8,12")])
11586 (define_split
11587 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11588 (compare:CC
11589 (plus:SI (lshiftrt:SI
11590 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11591 (const_int 31))
11592 (match_operand:SI 2 "gpc_reg_operand" ""))
11593 (const_int 0)))
11594 (set (match_operand:SI 0 "gpc_reg_operand" "")
11595 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11596 (match_dup 2)))
11597 (clobber (match_scratch:SI 3 ""))]
11598 "! TARGET_POWERPC64 && reload_completed"
11599 [(parallel [(set (match_dup 0)
11600 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11601 (match_dup 2)))
11602 (clobber (match_dup 3))])
11603 (set (match_dup 4)
11604 (compare:CC (match_dup 0)
11605 (const_int 0)))]
11606 "")
11608 (define_insn ""
11609 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11610 (compare:CC
11611 (plus:DI (lshiftrt:DI
11612 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11613 (const_int 63))
11614 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11615 (const_int 0)))
11616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11617 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11618 (match_dup 2)))
11619 (clobber (match_scratch:DI 3 "=&r,&r"))]
11620 "TARGET_POWERPC64"
11621 "@
11622 addic %3,%1,-1\;addze. %0,%2
11623 #"
11624 [(set_attr "type" "compare")
11625 (set_attr "length" "8,12")])
11627 (define_split
11628 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11629 (compare:CC
11630 (plus:DI (lshiftrt:DI
11631 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11632 (const_int 63))
11633 (match_operand:DI 2 "gpc_reg_operand" ""))
11634 (const_int 0)))
11635 (set (match_operand:DI 0 "gpc_reg_operand" "")
11636 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11637 (match_dup 2)))
11638 (clobber (match_scratch:DI 3 ""))]
11639 "TARGET_POWERPC64 && reload_completed"
11640 [(parallel [(set (match_dup 0)
11641 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11642 (match_dup 2)))
11643 (clobber (match_dup 3))])
11644 (set (match_dup 4)
11645 (compare:CC (match_dup 0)
11646 (const_int 0)))]
11647 "")
11649 (define_insn ""
11650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11651 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11652 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11653 (clobber (match_scratch:SI 3 "=r,X"))]
11654 "TARGET_POWER"
11655 "@
11656 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11657 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11658 [(set_attr "length" "12")])
11660 (define_insn ""
11661 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11662 (compare:CC
11663 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11664 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11665 (const_int 0)))
11666 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11667 (le:SI (match_dup 1) (match_dup 2)))
11668 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11669 "TARGET_POWER"
11670 "@
11671 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11672 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11673 #
11674 #"
11675 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11676 (set_attr "length" "12,12,16,16")])
11678 (define_split
11679 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11680 (compare:CC
11681 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11682 (match_operand:SI 2 "reg_or_short_operand" ""))
11683 (const_int 0)))
11684 (set (match_operand:SI 0 "gpc_reg_operand" "")
11685 (le:SI (match_dup 1) (match_dup 2)))
11686 (clobber (match_scratch:SI 3 ""))]
11687 "TARGET_POWER && reload_completed"
11688 [(parallel [(set (match_dup 0)
11689 (le:SI (match_dup 1) (match_dup 2)))
11690 (clobber (match_dup 3))])
11691 (set (match_dup 4)
11692 (compare:CC (match_dup 0)
11693 (const_int 0)))]
11694 "")
11696 (define_insn ""
11697 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11698 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11699 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11700 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11701 "TARGET_POWER"
11702 "@
11703 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11704 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11705 [(set_attr "length" "12")])
11707 (define_insn ""
11708 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11709 (compare:CC
11710 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11711 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11712 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11713 (const_int 0)))
11714 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11715 "TARGET_POWER"
11716 "@
11717 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11718 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11719 #
11720 #"
11721 [(set_attr "type" "compare")
11722 (set_attr "length" "12,12,16,16")])
11724 (define_split
11725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11726 (compare:CC
11727 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11728 (match_operand:SI 2 "reg_or_short_operand" ""))
11729 (match_operand:SI 3 "gpc_reg_operand" ""))
11730 (const_int 0)))
11731 (clobber (match_scratch:SI 4 ""))]
11732 "TARGET_POWER && reload_completed"
11733 [(set (match_dup 4)
11734 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11735 (match_dup 3)))
11736 (set (match_dup 0)
11737 (compare:CC (match_dup 4)
11738 (const_int 0)))]
11739 "")
11741 (define_insn ""
11742 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11743 (compare:CC
11744 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11745 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11746 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11747 (const_int 0)))
11748 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11749 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11750 "TARGET_POWER"
11751 "@
11752 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11753 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11754 #
11755 #"
11756 [(set_attr "type" "compare")
11757 (set_attr "length" "12,12,16,16")])
11759 (define_split
11760 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11761 (compare:CC
11762 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11763 (match_operand:SI 2 "reg_or_short_operand" ""))
11764 (match_operand:SI 3 "gpc_reg_operand" ""))
11765 (const_int 0)))
11766 (set (match_operand:SI 0 "gpc_reg_operand" "")
11767 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11768 "TARGET_POWER && reload_completed"
11769 [(set (match_dup 0)
11770 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11771 (set (match_dup 4)
11772 (compare:CC (match_dup 0)
11773 (const_int 0)))]
11774 "")
11776 (define_insn ""
11777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11778 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11779 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11780 "TARGET_POWER"
11781 "@
11782 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11783 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11784 [(set_attr "length" "12")])
11786 (define_insn ""
11787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11788 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11789 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11790 "! TARGET_POWERPC64"
11791 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11792 [(set_attr "length" "12")])
11794 (define_insn ""
11795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11796 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11797 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11798 "TARGET_POWERPC64"
11799 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11800 [(set_attr "length" "12")])
11802 (define_insn ""
11803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11804 (compare:CC
11805 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11806 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11807 (const_int 0)))
11808 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11809 (leu:DI (match_dup 1) (match_dup 2)))]
11810 "TARGET_POWERPC64"
11811 "@
11812 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11813 #"
11814 [(set_attr "type" "compare")
11815 (set_attr "length" "12,16")])
11817 (define_split
11818 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11819 (compare:CC
11820 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11821 (match_operand:DI 2 "reg_or_short_operand" ""))
11822 (const_int 0)))
11823 (set (match_operand:DI 0 "gpc_reg_operand" "")
11824 (leu:DI (match_dup 1) (match_dup 2)))]
11825 "TARGET_POWERPC64 && reload_completed"
11826 [(set (match_dup 0)
11827 (leu:DI (match_dup 1) (match_dup 2)))
11828 (set (match_dup 3)
11829 (compare:CC (match_dup 0)
11830 (const_int 0)))]
11831 "")
11833 (define_insn ""
11834 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11835 (compare:CC
11836 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11837 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11838 (const_int 0)))
11839 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11840 (leu:SI (match_dup 1) (match_dup 2)))]
11841 "! TARGET_POWERPC64"
11842 "@
11843 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11844 #"
11845 [(set_attr "type" "compare")
11846 (set_attr "length" "12,16")])
11848 (define_split
11849 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11850 (compare:CC
11851 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11852 (match_operand:SI 2 "reg_or_short_operand" ""))
11853 (const_int 0)))
11854 (set (match_operand:SI 0 "gpc_reg_operand" "")
11855 (leu:SI (match_dup 1) (match_dup 2)))]
11856 "! TARGET_POWERPC64 && reload_completed"
11857 [(set (match_dup 0)
11858 (leu:SI (match_dup 1) (match_dup 2)))
11859 (set (match_dup 3)
11860 (compare:CC (match_dup 0)
11861 (const_int 0)))]
11862 "")
11864 (define_insn ""
11865 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11866 (compare:CC
11867 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11868 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11869 (const_int 0)))
11870 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11871 (leu:DI (match_dup 1) (match_dup 2)))]
11872 "TARGET_POWERPC64"
11873 "@
11874 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11875 #"
11876 [(set_attr "type" "compare")
11877 (set_attr "length" "12,16")])
11879 (define_insn ""
11880 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11881 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11882 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11883 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11884 "! TARGET_POWERPC64"
11885 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11886 [(set_attr "length" "8")])
11888 (define_insn ""
11889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11890 (compare:CC
11891 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11892 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11893 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11894 (const_int 0)))
11895 (clobber (match_scratch:SI 4 "=&r,&r"))]
11896 "! TARGET_POWERPC64"
11897 "@
11898 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11899 #"
11900 [(set_attr "type" "compare")
11901 (set_attr "length" "8,12")])
11903 (define_split
11904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11905 (compare:CC
11906 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11907 (match_operand:SI 2 "reg_or_short_operand" ""))
11908 (match_operand:SI 3 "gpc_reg_operand" ""))
11909 (const_int 0)))
11910 (clobber (match_scratch:SI 4 ""))]
11911 "! TARGET_POWERPC64 && reload_completed"
11912 [(set (match_dup 4)
11913 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11914 (match_dup 3)))
11915 (set (match_dup 0)
11916 (compare:CC (match_dup 4)
11917 (const_int 0)))]
11918 "")
11920 (define_insn ""
11921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11922 (compare:CC
11923 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11924 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11925 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11926 (const_int 0)))
11927 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11928 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11929 "! TARGET_POWERPC64"
11930 "@
11931 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11932 #"
11933 [(set_attr "type" "compare")
11934 (set_attr "length" "8,12")])
11936 (define_split
11937 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11938 (compare:CC
11939 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11940 (match_operand:SI 2 "reg_or_short_operand" ""))
11941 (match_operand:SI 3 "gpc_reg_operand" ""))
11942 (const_int 0)))
11943 (set (match_operand:SI 0 "gpc_reg_operand" "")
11944 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11945 "! TARGET_POWERPC64 && reload_completed"
11946 [(set (match_dup 0)
11947 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11948 (set (match_dup 4)
11949 (compare:CC (match_dup 0)
11950 (const_int 0)))]
11951 "")
11953 (define_insn ""
11954 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11955 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11956 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11957 "! TARGET_POWERPC64"
11958 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11959 [(set_attr "length" "12")])
11961 (define_insn ""
11962 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11963 (and:SI (neg:SI
11964 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11965 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11966 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11967 "! TARGET_POWERPC64"
11968 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11969 [(set_attr "length" "12")])
11971 (define_insn ""
11972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11973 (compare:CC
11974 (and:SI (neg:SI
11975 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11976 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11977 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11978 (const_int 0)))
11979 (clobber (match_scratch:SI 4 "=&r,&r"))]
11980 "! TARGET_POWERPC64"
11981 "@
11982 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11983 #"
11984 [(set_attr "type" "compare")
11985 (set_attr "length" "12,16")])
11987 (define_split
11988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11989 (compare:CC
11990 (and:SI (neg:SI
11991 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11992 (match_operand:SI 2 "reg_or_short_operand" "")))
11993 (match_operand:SI 3 "gpc_reg_operand" ""))
11994 (const_int 0)))
11995 (clobber (match_scratch:SI 4 ""))]
11996 "! TARGET_POWERPC64 && reload_completed"
11997 [(set (match_dup 4)
11998 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11999 (match_dup 3)))
12000 (set (match_dup 0)
12001 (compare:CC (match_dup 4)
12002 (const_int 0)))]
12003 "")
12005 (define_insn ""
12006 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12007 (compare:CC
12008 (and:SI (neg:SI
12009 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12010 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12011 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12012 (const_int 0)))
12013 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12014 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12015 "! TARGET_POWERPC64"
12016 "@
12017 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12018 #"
12019 [(set_attr "type" "compare")
12020 (set_attr "length" "12,16")])
12022 (define_split
12023 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12024 (compare:CC
12025 (and:SI (neg:SI
12026 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12027 (match_operand:SI 2 "reg_or_short_operand" "")))
12028 (match_operand:SI 3 "gpc_reg_operand" ""))
12029 (const_int 0)))
12030 (set (match_operand:SI 0 "gpc_reg_operand" "")
12031 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12032 "! TARGET_POWERPC64 && reload_completed"
12033 [(set (match_dup 0)
12034 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12035 (match_dup 3)))
12036 (set (match_dup 4)
12037 (compare:CC (match_dup 0)
12038 (const_int 0)))]
12039 "")
12041 (define_insn ""
12042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12043 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12044 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12045 "TARGET_POWER"
12046 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12047 [(set_attr "length" "12")])
12049 (define_insn ""
12050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12051 (compare:CC
12052 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12053 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12054 (const_int 0)))
12055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12056 (lt:SI (match_dup 1) (match_dup 2)))]
12057 "TARGET_POWER"
12058 "@
12059 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12060 #"
12061 [(set_attr "type" "delayed_compare")
12062 (set_attr "length" "12,16")])
12064 (define_split
12065 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12066 (compare:CC
12067 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12068 (match_operand:SI 2 "reg_or_short_operand" ""))
12069 (const_int 0)))
12070 (set (match_operand:SI 0 "gpc_reg_operand" "")
12071 (lt:SI (match_dup 1) (match_dup 2)))]
12072 "TARGET_POWER && reload_completed"
12073 [(set (match_dup 0)
12074 (lt:SI (match_dup 1) (match_dup 2)))
12075 (set (match_dup 3)
12076 (compare:CC (match_dup 0)
12077 (const_int 0)))]
12078 "")
12080 (define_insn ""
12081 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12082 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12083 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12084 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12085 "TARGET_POWER"
12086 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12087 [(set_attr "length" "12")])
12089 (define_insn ""
12090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12091 (compare:CC
12092 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12093 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12094 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12095 (const_int 0)))
12096 (clobber (match_scratch:SI 4 "=&r,&r"))]
12097 "TARGET_POWER"
12098 "@
12099 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12100 #"
12101 [(set_attr "type" "compare")
12102 (set_attr "length" "12,16")])
12104 (define_split
12105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12106 (compare:CC
12107 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12108 (match_operand:SI 2 "reg_or_short_operand" ""))
12109 (match_operand:SI 3 "gpc_reg_operand" ""))
12110 (const_int 0)))
12111 (clobber (match_scratch:SI 4 ""))]
12112 "TARGET_POWER && reload_completed"
12113 [(set (match_dup 4)
12114 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12115 (match_dup 3)))
12116 (set (match_dup 0)
12117 (compare:CC (match_dup 4)
12118 (const_int 0)))]
12119 "")
12121 (define_insn ""
12122 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12123 (compare:CC
12124 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12125 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12126 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12127 (const_int 0)))
12128 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12129 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12130 "TARGET_POWER"
12131 "@
12132 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12133 #"
12134 [(set_attr "type" "compare")
12135 (set_attr "length" "12,16")])
12137 (define_split
12138 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12139 (compare:CC
12140 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12141 (match_operand:SI 2 "reg_or_short_operand" ""))
12142 (match_operand:SI 3 "gpc_reg_operand" ""))
12143 (const_int 0)))
12144 (set (match_operand:SI 0 "gpc_reg_operand" "")
12145 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12146 "TARGET_POWER && reload_completed"
12147 [(set (match_dup 0)
12148 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12149 (set (match_dup 4)
12150 (compare:CC (match_dup 0)
12151 (const_int 0)))]
12152 "")
12154 (define_insn ""
12155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12156 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12157 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12158 "TARGET_POWER"
12159 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12160 [(set_attr "length" "12")])
12162 (define_insn ""
12163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12164 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12165 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12166 "! TARGET_POWERPC64"
12167 "@
12168 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12169 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12170 [(set_attr "length" "12")])
12172 (define_insn ""
12173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12174 (compare:CC
12175 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12176 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12177 (const_int 0)))
12178 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12179 (ltu:SI (match_dup 1) (match_dup 2)))]
12180 "! TARGET_POWERPC64"
12181 "@
12182 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12183 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12184 #
12185 #"
12186 [(set_attr "type" "compare")
12187 (set_attr "length" "12,12,16,16")])
12189 (define_split
12190 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12191 (compare:CC
12192 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12193 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12194 (const_int 0)))
12195 (set (match_operand:SI 0 "gpc_reg_operand" "")
12196 (ltu:SI (match_dup 1) (match_dup 2)))]
12197 "! TARGET_POWERPC64 && reload_completed"
12198 [(set (match_dup 0)
12199 (ltu:SI (match_dup 1) (match_dup 2)))
12200 (set (match_dup 3)
12201 (compare:CC (match_dup 0)
12202 (const_int 0)))]
12203 "")
12205 (define_insn ""
12206 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12207 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12208 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12209 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12210 "! TARGET_POWERPC64"
12211 "@
12212 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12213 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12214 [(set_attr "length" "12")])
12216 (define_insn ""
12217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12218 (compare:CC
12219 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12220 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12221 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12222 (const_int 0)))
12223 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12224 "! TARGET_POWERPC64"
12225 "@
12226 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12227 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12228 #
12229 #"
12230 [(set_attr "type" "compare")
12231 (set_attr "length" "12,12,16,16")])
12233 (define_split
12234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12235 (compare:CC
12236 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12237 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12238 (match_operand:SI 3 "gpc_reg_operand" ""))
12239 (const_int 0)))
12240 (clobber (match_scratch:SI 4 ""))]
12241 "! TARGET_POWERPC64 && reload_completed"
12242 [(set (match_dup 4)
12243 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12244 (match_dup 3)))
12245 (set (match_dup 0)
12246 (compare:CC (match_dup 4)
12247 (const_int 0)))]
12248 "")
12250 (define_insn ""
12251 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12252 (compare:CC
12253 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12254 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12255 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12256 (const_int 0)))
12257 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12258 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12259 "! TARGET_POWERPC64"
12260 "@
12261 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12262 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12263 #
12264 #"
12265 [(set_attr "type" "compare")
12266 (set_attr "length" "12,12,16,16")])
12268 (define_split
12269 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12270 (compare:CC
12271 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12272 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12273 (match_operand:SI 3 "gpc_reg_operand" ""))
12274 (const_int 0)))
12275 (set (match_operand:SI 0 "gpc_reg_operand" "")
12276 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12277 "! TARGET_POWERPC64 && reload_completed"
12278 [(set (match_dup 0)
12279 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12280 (set (match_dup 4)
12281 (compare:CC (match_dup 0)
12282 (const_int 0)))]
12283 "")
12285 (define_insn ""
12286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12287 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12288 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12289 "! TARGET_POWERPC64"
12290 "@
12291 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12292 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12293 [(set_attr "length" "8")])
12295 (define_insn ""
12296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12297 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12298 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12299 (clobber (match_scratch:SI 3 "=r"))]
12300 "TARGET_POWER"
12301 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12302 [(set_attr "length" "12")])
12304 (define_insn ""
12305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12306 (compare:CC
12307 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12308 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12309 (const_int 0)))
12310 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12311 (ge:SI (match_dup 1) (match_dup 2)))
12312 (clobber (match_scratch:SI 3 "=r,r"))]
12313 "TARGET_POWER"
12314 "@
12315 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12316 #"
12317 [(set_attr "type" "compare")
12318 (set_attr "length" "12,16")])
12320 (define_split
12321 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12322 (compare:CC
12323 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12324 (match_operand:SI 2 "reg_or_short_operand" ""))
12325 (const_int 0)))
12326 (set (match_operand:SI 0 "gpc_reg_operand" "")
12327 (ge:SI (match_dup 1) (match_dup 2)))
12328 (clobber (match_scratch:SI 3 ""))]
12329 "TARGET_POWER && reload_completed"
12330 [(parallel [(set (match_dup 0)
12331 (ge:SI (match_dup 1) (match_dup 2)))
12332 (clobber (match_dup 3))])
12333 (set (match_dup 4)
12334 (compare:CC (match_dup 0)
12335 (const_int 0)))]
12336 "")
12338 (define_insn ""
12339 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12340 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12341 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12342 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12343 "TARGET_POWER"
12344 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12345 [(set_attr "length" "12")])
12347 (define_insn ""
12348 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12349 (compare:CC
12350 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12351 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12352 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12353 (const_int 0)))
12354 (clobber (match_scratch:SI 4 "=&r,&r"))]
12355 "TARGET_POWER"
12356 "@
12357 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12358 #"
12359 [(set_attr "type" "compare")
12360 (set_attr "length" "12,16")])
12362 (define_split
12363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12364 (compare:CC
12365 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12366 (match_operand:SI 2 "reg_or_short_operand" ""))
12367 (match_operand:SI 3 "gpc_reg_operand" ""))
12368 (const_int 0)))
12369 (clobber (match_scratch:SI 4 ""))]
12370 "TARGET_POWER && reload_completed"
12371 [(set (match_dup 4)
12372 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12373 (match_dup 3)))
12374 (set (match_dup 0)
12375 (compare:CC (match_dup 4)
12376 (const_int 0)))]
12377 "")
12379 (define_insn ""
12380 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12381 (compare:CC
12382 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12383 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12384 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12385 (const_int 0)))
12386 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12387 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12388 "TARGET_POWER"
12389 "@
12390 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12391 #"
12392 [(set_attr "type" "compare")
12393 (set_attr "length" "12,16")])
12395 (define_split
12396 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12397 (compare:CC
12398 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12399 (match_operand:SI 2 "reg_or_short_operand" ""))
12400 (match_operand:SI 3 "gpc_reg_operand" ""))
12401 (const_int 0)))
12402 (set (match_operand:SI 0 "gpc_reg_operand" "")
12403 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12404 "TARGET_POWER && reload_completed"
12405 [(set (match_dup 0)
12406 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12407 (set (match_dup 4)
12408 (compare:CC (match_dup 0)
12409 (const_int 0)))]
12410 "")
12412 (define_insn ""
12413 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12414 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12415 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12416 "TARGET_POWER"
12417 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12418 [(set_attr "length" "12")])
12420 (define_insn ""
12421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12422 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12423 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12424 "! TARGET_POWERPC64"
12425 "@
12426 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12427 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12428 [(set_attr "length" "12")])
12430 (define_insn ""
12431 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12432 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12433 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12434 "TARGET_POWERPC64"
12435 "@
12436 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12437 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12438 [(set_attr "length" "12")])
12440 (define_insn ""
12441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12442 (compare:CC
12443 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12444 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12445 (const_int 0)))
12446 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12447 (geu:SI (match_dup 1) (match_dup 2)))]
12448 "! TARGET_POWERPC64"
12449 "@
12450 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12451 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12452 #
12453 #"
12454 [(set_attr "type" "compare")
12455 (set_attr "length" "12,12,16,16")])
12457 (define_split
12458 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12459 (compare:CC
12460 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12461 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12462 (const_int 0)))
12463 (set (match_operand:SI 0 "gpc_reg_operand" "")
12464 (geu:SI (match_dup 1) (match_dup 2)))]
12465 "! TARGET_POWERPC64 && reload_completed"
12466 [(set (match_dup 0)
12467 (geu:SI (match_dup 1) (match_dup 2)))
12468 (set (match_dup 3)
12469 (compare:CC (match_dup 0)
12470 (const_int 0)))]
12471 "")
12473 (define_insn ""
12474 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12475 (compare:CC
12476 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12477 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12478 (const_int 0)))
12479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12480 (geu:DI (match_dup 1) (match_dup 2)))]
12481 "TARGET_POWERPC64"
12482 "@
12483 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12484 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12485 #
12486 #"
12487 [(set_attr "type" "compare")
12488 (set_attr "length" "12,12,16,16")])
12490 (define_split
12491 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12492 (compare:CC
12493 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12494 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12495 (const_int 0)))
12496 (set (match_operand:DI 0 "gpc_reg_operand" "")
12497 (geu:DI (match_dup 1) (match_dup 2)))]
12498 "TARGET_POWERPC64 && reload_completed"
12499 [(set (match_dup 0)
12500 (geu:DI (match_dup 1) (match_dup 2)))
12501 (set (match_dup 3)
12502 (compare:CC (match_dup 0)
12503 (const_int 0)))]
12504 "")
12506 (define_insn ""
12507 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12508 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12509 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12510 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12511 "! TARGET_POWERPC64"
12512 "@
12513 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12514 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12515 [(set_attr "length" "8")])
12517 (define_insn ""
12518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12519 (compare:CC
12520 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12521 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12522 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12523 (const_int 0)))
12524 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12525 "! TARGET_POWERPC64"
12526 "@
12527 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12528 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12529 #
12530 #"
12531 [(set_attr "type" "compare")
12532 (set_attr "length" "8,8,12,12")])
12534 (define_split
12535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12536 (compare:CC
12537 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12538 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12539 (match_operand:SI 3 "gpc_reg_operand" ""))
12540 (const_int 0)))
12541 (clobber (match_scratch:SI 4 ""))]
12542 "! TARGET_POWERPC64 && reload_completed"
12543 [(set (match_dup 4)
12544 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12545 (match_dup 3)))
12546 (set (match_dup 0)
12547 (compare:CC (match_dup 4)
12548 (const_int 0)))]
12549 "")
12551 (define_insn ""
12552 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12553 (compare:CC
12554 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12555 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12556 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12557 (const_int 0)))
12558 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12559 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12560 "! TARGET_POWERPC64"
12561 "@
12562 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12563 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12564 #
12565 #"
12566 [(set_attr "type" "compare")
12567 (set_attr "length" "8,8,12,12")])
12569 (define_split
12570 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12571 (compare:CC
12572 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12573 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12574 (match_operand:SI 3 "gpc_reg_operand" ""))
12575 (const_int 0)))
12576 (set (match_operand:SI 0 "gpc_reg_operand" "")
12577 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12578 "! TARGET_POWERPC64 && reload_completed"
12579 [(set (match_dup 0)
12580 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12581 (set (match_dup 4)
12582 (compare:CC (match_dup 0)
12583 (const_int 0)))]
12584 "")
12586 (define_insn ""
12587 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12588 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12589 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12590 "! TARGET_POWERPC64"
12591 "@
12592 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12593 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12594 [(set_attr "length" "12")])
12596 (define_insn ""
12597 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12598 (and:SI (neg:SI
12599 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12600 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12601 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12602 "! TARGET_POWERPC64"
12603 "@
12604 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12605 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12606 [(set_attr "length" "12")])
12608 (define_insn ""
12609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12610 (compare:CC
12611 (and:SI (neg:SI
12612 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12613 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12614 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12615 (const_int 0)))
12616 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12617 "! TARGET_POWERPC64"
12618 "@
12619 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12620 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12621 #
12622 #"
12623 [(set_attr "type" "compare")
12624 (set_attr "length" "12,12,16,16")])
12626 (define_split
12627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12628 (compare:CC
12629 (and:SI (neg:SI
12630 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12631 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12632 (match_operand:SI 3 "gpc_reg_operand" ""))
12633 (const_int 0)))
12634 (clobber (match_scratch:SI 4 ""))]
12635 "! TARGET_POWERPC64 && reload_completed"
12636 [(set (match_dup 4)
12637 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12638 (match_dup 3)))
12639 (set (match_dup 0)
12640 (compare:CC (match_dup 4)
12641 (const_int 0)))]
12642 "")
12644 (define_insn ""
12645 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12646 (compare:CC
12647 (and:SI (neg:SI
12648 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12649 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12650 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12651 (const_int 0)))
12652 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12653 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12654 "! TARGET_POWERPC64"
12655 "@
12656 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12657 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12658 #
12659 #"
12660 [(set_attr "type" "compare")
12661 (set_attr "length" "12,12,16,16")])
12663 (define_split
12664 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12665 (compare:CC
12666 (and:SI (neg:SI
12667 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12668 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12669 (match_operand:SI 3 "gpc_reg_operand" ""))
12670 (const_int 0)))
12671 (set (match_operand:SI 0 "gpc_reg_operand" "")
12672 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12673 "! TARGET_POWERPC64 && reload_completed"
12674 [(set (match_dup 0)
12675 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12676 (set (match_dup 4)
12677 (compare:CC (match_dup 0)
12678 (const_int 0)))]
12679 "")
12681 (define_insn ""
12682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12683 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12684 (const_int 0)))]
12685 "! TARGET_POWERPC64"
12686 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12687 [(set_attr "length" "12")])
12689 (define_insn ""
12690 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12691 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12692 (const_int 0)))]
12693 "TARGET_POWERPC64"
12694 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12695 [(set_attr "length" "12")])
12697 (define_insn ""
12698 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12699 (compare:CC
12700 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12701 (const_int 0))
12702 (const_int 0)))
12703 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12704 (gt:SI (match_dup 1) (const_int 0)))]
12705 "! TARGET_POWERPC64"
12706 "@
12707 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12708 #"
12709 [(set_attr "type" "delayed_compare")
12710 (set_attr "length" "12,16")])
12712 (define_split
12713 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12714 (compare:CC
12715 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12716 (const_int 0))
12717 (const_int 0)))
12718 (set (match_operand:SI 0 "gpc_reg_operand" "")
12719 (gt:SI (match_dup 1) (const_int 0)))]
12720 "! TARGET_POWERPC64 && reload_completed"
12721 [(set (match_dup 0)
12722 (gt:SI (match_dup 1) (const_int 0)))
12723 (set (match_dup 2)
12724 (compare:CC (match_dup 0)
12725 (const_int 0)))]
12726 "")
12728 (define_insn ""
12729 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12730 (compare:CC
12731 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12732 (const_int 0))
12733 (const_int 0)))
12734 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12735 (gt:DI (match_dup 1) (const_int 0)))]
12736 "TARGET_POWERPC64"
12737 "@
12738 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12739 #"
12740 [(set_attr "type" "delayed_compare")
12741 (set_attr "length" "12,16")])
12743 (define_split
12744 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12745 (compare:CC
12746 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12747 (const_int 0))
12748 (const_int 0)))
12749 (set (match_operand:DI 0 "gpc_reg_operand" "")
12750 (gt:DI (match_dup 1) (const_int 0)))]
12751 "TARGET_POWERPC64 && reload_completed"
12752 [(set (match_dup 0)
12753 (gt:DI (match_dup 1) (const_int 0)))
12754 (set (match_dup 2)
12755 (compare:CC (match_dup 0)
12756 (const_int 0)))]
12757 "")
12759 (define_insn ""
12760 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12761 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12762 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12763 "TARGET_POWER"
12764 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12765 [(set_attr "length" "12")])
12767 (define_insn ""
12768 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12769 (compare:CC
12770 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12771 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12772 (const_int 0)))
12773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12774 (gt:SI (match_dup 1) (match_dup 2)))]
12775 "TARGET_POWER"
12776 "@
12777 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12778 #"
12779 [(set_attr "type" "delayed_compare")
12780 (set_attr "length" "12,16")])
12782 (define_split
12783 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12784 (compare:CC
12785 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12786 (match_operand:SI 2 "reg_or_short_operand" ""))
12787 (const_int 0)))
12788 (set (match_operand:SI 0 "gpc_reg_operand" "")
12789 (gt:SI (match_dup 1) (match_dup 2)))]
12790 "TARGET_POWER && reload_completed"
12791 [(set (match_dup 0)
12792 (gt:SI (match_dup 1) (match_dup 2)))
12793 (set (match_dup 3)
12794 (compare:CC (match_dup 0)
12795 (const_int 0)))]
12796 "")
12798 (define_insn ""
12799 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12800 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12801 (const_int 0))
12802 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12803 "! TARGET_POWERPC64"
12804 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12805 [(set_attr "length" "12")])
12807 (define_insn ""
12808 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
12809 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12810 (const_int 0))
12811 (match_operand:DI 2 "gpc_reg_operand" "r")))]
12812 "TARGET_POWERPC64"
12813 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12814 [(set_attr "length" "12")])
12816 (define_insn ""
12817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12818 (compare:CC
12819 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12820 (const_int 0))
12821 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12822 (const_int 0)))
12823 (clobber (match_scratch:SI 3 "=&r,&r"))]
12824 "! TARGET_POWERPC64"
12825 "@
12826 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12827 #"
12828 [(set_attr "type" "compare")
12829 (set_attr "length" "12,16")])
12831 (define_split
12832 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12833 (compare:CC
12834 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12835 (const_int 0))
12836 (match_operand:SI 2 "gpc_reg_operand" ""))
12837 (const_int 0)))
12838 (clobber (match_scratch:SI 3 ""))]
12839 "! TARGET_POWERPC64 && reload_completed"
12840 [(set (match_dup 3)
12841 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12842 (match_dup 2)))
12843 (set (match_dup 0)
12844 (compare:CC (match_dup 3)
12845 (const_int 0)))]
12846 "")
12848 (define_insn ""
12849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12850 (compare:CC
12851 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12852 (const_int 0))
12853 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12854 (const_int 0)))
12855 (clobber (match_scratch:DI 3 "=&r,&r"))]
12856 "TARGET_POWERPC64"
12857 "@
12858 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12859 #"
12860 [(set_attr "type" "compare")
12861 (set_attr "length" "12,16")])
12863 (define_split
12864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12865 (compare:CC
12866 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12867 (const_int 0))
12868 (match_operand:DI 2 "gpc_reg_operand" ""))
12869 (const_int 0)))
12870 (clobber (match_scratch:DI 3 ""))]
12871 "TARGET_POWERPC64 && reload_completed"
12872 [(set (match_dup 3)
12873 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12874 (match_dup 2)))
12875 (set (match_dup 0)
12876 (compare:CC (match_dup 3)
12877 (const_int 0)))]
12878 "")
12880 (define_insn ""
12881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12882 (compare:CC
12883 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12884 (const_int 0))
12885 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12886 (const_int 0)))
12887 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12888 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12889 "! TARGET_POWERPC64"
12890 "@
12891 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12892 #"
12893 [(set_attr "type" "compare")
12894 (set_attr "length" "12,16")])
12896 (define_split
12897 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12898 (compare:CC
12899 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12900 (const_int 0))
12901 (match_operand:SI 2 "gpc_reg_operand" ""))
12902 (const_int 0)))
12903 (set (match_operand:SI 0 "gpc_reg_operand" "")
12904 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12905 "! TARGET_POWERPC64 && reload_completed"
12906 [(set (match_dup 0)
12907 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12908 (set (match_dup 3)
12909 (compare:CC (match_dup 0)
12910 (const_int 0)))]
12911 "")
12913 (define_insn ""
12914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12915 (compare:CC
12916 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12917 (const_int 0))
12918 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12919 (const_int 0)))
12920 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12921 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12922 "TARGET_POWERPC64"
12923 "@
12924 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12925 #"
12926 [(set_attr "type" "compare")
12927 (set_attr "length" "12,16")])
12929 (define_split
12930 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12931 (compare:CC
12932 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12933 (const_int 0))
12934 (match_operand:DI 2 "gpc_reg_operand" ""))
12935 (const_int 0)))
12936 (set (match_operand:DI 0 "gpc_reg_operand" "")
12937 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12938 "TARGET_POWERPC64 && reload_completed"
12939 [(set (match_dup 0)
12940 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12941 (set (match_dup 3)
12942 (compare:CC (match_dup 0)
12943 (const_int 0)))]
12944 "")
12946 (define_insn ""
12947 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12948 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12949 (match_operand:SI 2 "reg_or_short_operand" "r"))
12950 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12951 "TARGET_POWER"
12952 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12953 [(set_attr "length" "12")])
12955 (define_insn ""
12956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12957 (compare:CC
12958 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12959 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12960 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12961 (const_int 0)))
12962 (clobber (match_scratch:SI 4 "=&r,&r"))]
12963 "TARGET_POWER"
12964 "@
12965 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12966 #"
12967 [(set_attr "type" "compare")
12968 (set_attr "length" "12,16")])
12970 (define_split
12971 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12972 (compare:CC
12973 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12974 (match_operand:SI 2 "reg_or_short_operand" ""))
12975 (match_operand:SI 3 "gpc_reg_operand" ""))
12976 (const_int 0)))
12977 (clobber (match_scratch:SI 4 ""))]
12978 "TARGET_POWER && reload_completed"
12979 [(set (match_dup 4)
12980 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12981 (set (match_dup 0)
12982 (compare:CC (match_dup 4)
12983 (const_int 0)))]
12984 "")
12986 (define_insn ""
12987 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12988 (compare:CC
12989 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12990 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12991 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12992 (const_int 0)))
12993 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12994 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12995 "TARGET_POWER"
12996 "@
12997 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12998 #"
12999 [(set_attr "type" "compare")
13000 (set_attr "length" "12,16")])
13002 (define_split
13003 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13004 (compare:CC
13005 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13006 (match_operand:SI 2 "reg_or_short_operand" ""))
13007 (match_operand:SI 3 "gpc_reg_operand" ""))
13008 (const_int 0)))
13009 (set (match_operand:SI 0 "gpc_reg_operand" "")
13010 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13011 "TARGET_POWER && reload_completed"
13012 [(set (match_dup 0)
13013 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13014 (set (match_dup 4)
13015 (compare:CC (match_dup 0)
13016 (const_int 0)))]
13017 "")
13019 (define_insn ""
13020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13021 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13022 (const_int 0))))]
13023 "! TARGET_POWERPC64"
13024 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13025 [(set_attr "length" "12")])
13027 (define_insn ""
13028 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13029 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13030 (const_int 0))))]
13031 "TARGET_POWERPC64"
13032 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13033 [(set_attr "length" "12")])
13035 (define_insn ""
13036 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13037 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13038 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13039 "TARGET_POWER"
13040 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13041 [(set_attr "length" "12")])
13043 (define_insn ""
13044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13045 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13046 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13047 "! TARGET_POWERPC64"
13048 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13049 [(set_attr "length" "12")])
13051 (define_insn ""
13052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13053 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13054 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13055 "TARGET_POWERPC64"
13056 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13057 [(set_attr "length" "12")])
13059 (define_insn ""
13060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13061 (compare:CC
13062 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13063 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13064 (const_int 0)))
13065 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13066 (gtu:SI (match_dup 1) (match_dup 2)))]
13067 "! TARGET_POWERPC64"
13068 "@
13069 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13070 #"
13071 [(set_attr "type" "compare")
13072 (set_attr "length" "12,16")])
13074 (define_split
13075 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13076 (compare:CC
13077 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13078 (match_operand:SI 2 "reg_or_short_operand" ""))
13079 (const_int 0)))
13080 (set (match_operand:SI 0 "gpc_reg_operand" "")
13081 (gtu:SI (match_dup 1) (match_dup 2)))]
13082 "! TARGET_POWERPC64 && reload_completed"
13083 [(set (match_dup 0)
13084 (gtu:SI (match_dup 1) (match_dup 2)))
13085 (set (match_dup 3)
13086 (compare:CC (match_dup 0)
13087 (const_int 0)))]
13088 "")
13090 (define_insn ""
13091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13092 (compare:CC
13093 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13094 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13095 (const_int 0)))
13096 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13097 (gtu:DI (match_dup 1) (match_dup 2)))]
13098 "TARGET_POWERPC64"
13099 "@
13100 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13101 #"
13102 [(set_attr "type" "compare")
13103 (set_attr "length" "12,16")])
13105 (define_split
13106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13107 (compare:CC
13108 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13109 (match_operand:DI 2 "reg_or_short_operand" ""))
13110 (const_int 0)))
13111 (set (match_operand:DI 0 "gpc_reg_operand" "")
13112 (gtu:DI (match_dup 1) (match_dup 2)))]
13113 "TARGET_POWERPC64 && reload_completed"
13114 [(set (match_dup 0)
13115 (gtu:DI (match_dup 1) (match_dup 2)))
13116 (set (match_dup 3)
13117 (compare:CC (match_dup 0)
13118 (const_int 0)))]
13119 "")
13121 (define_insn ""
13122 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13123 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13124 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13125 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13126 "! TARGET_POWERPC64"
13127 "@
13128 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13129 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13130 [(set_attr "length" "8,12")])
13132 (define_insn ""
13133 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13134 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13135 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13136 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13137 "TARGET_POWERPC64"
13138 "@
13139 addic %0,%1,%k2\;addze %0,%3
13140 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13141 [(set_attr "length" "8,12")])
13143 (define_insn ""
13144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13145 (compare:CC
13146 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13147 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13148 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13149 (const_int 0)))
13150 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13151 "! TARGET_POWERPC64"
13152 "@
13153 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13154 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13155 #
13156 #"
13157 [(set_attr "type" "compare")
13158 (set_attr "length" "8,12,12,16")])
13160 (define_split
13161 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13162 (compare:CC
13163 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13164 (match_operand:SI 2 "reg_or_short_operand" ""))
13165 (match_operand:SI 3 "gpc_reg_operand" ""))
13166 (const_int 0)))
13167 (clobber (match_scratch:SI 4 ""))]
13168 "! TARGET_POWERPC64 && reload_completed"
13169 [(set (match_dup 4)
13170 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13171 (match_dup 3)))
13172 (set (match_dup 0)
13173 (compare:CC (match_dup 4)
13174 (const_int 0)))]
13175 "")
13177 (define_insn ""
13178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13179 (compare:CC
13180 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13181 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13182 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13183 (const_int 0)))
13184 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13185 "TARGET_POWERPC64"
13186 "@
13187 addic %4,%1,%k2\;addze. %4,%3
13188 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13189 #
13190 #"
13191 [(set_attr "type" "compare")
13192 (set_attr "length" "8,12,12,16")])
13194 (define_split
13195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13196 (compare:CC
13197 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13198 (match_operand:DI 2 "reg_or_short_operand" ""))
13199 (match_operand:DI 3 "gpc_reg_operand" ""))
13200 (const_int 0)))
13201 (clobber (match_scratch:DI 4 ""))]
13202 "TARGET_POWERPC64 && reload_completed"
13203 [(set (match_dup 4)
13204 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13205 (match_dup 3)))
13206 (set (match_dup 0)
13207 (compare:CC (match_dup 4)
13208 (const_int 0)))]
13209 "")
13211 (define_insn ""
13212 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13213 (compare:CC
13214 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13215 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13216 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13217 (const_int 0)))
13218 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13219 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13220 "! TARGET_POWERPC64"
13221 "@
13222 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13223 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13224 #
13225 #"
13226 [(set_attr "type" "compare")
13227 (set_attr "length" "8,12,12,16")])
13229 (define_split
13230 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13231 (compare:CC
13232 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13233 (match_operand:SI 2 "reg_or_short_operand" ""))
13234 (match_operand:SI 3 "gpc_reg_operand" ""))
13235 (const_int 0)))
13236 (set (match_operand:SI 0 "gpc_reg_operand" "")
13237 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13238 "! TARGET_POWERPC64 && reload_completed"
13239 [(set (match_dup 0)
13240 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13241 (set (match_dup 4)
13242 (compare:CC (match_dup 0)
13243 (const_int 0)))]
13244 "")
13246 (define_insn ""
13247 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13248 (compare:CC
13249 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13250 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13251 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13252 (const_int 0)))
13253 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13254 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13255 "TARGET_POWERPC64"
13256 "@
13257 addic %0,%1,%k2\;addze. %0,%3
13258 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13259 #
13260 #"
13261 [(set_attr "type" "compare")
13262 (set_attr "length" "8,12,12,16")])
13264 (define_split
13265 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13266 (compare:CC
13267 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13268 (match_operand:DI 2 "reg_or_short_operand" ""))
13269 (match_operand:DI 3 "gpc_reg_operand" ""))
13270 (const_int 0)))
13271 (set (match_operand:DI 0 "gpc_reg_operand" "")
13272 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13273 "TARGET_POWERPC64 && reload_completed"
13274 [(set (match_dup 0)
13275 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13276 (set (match_dup 4)
13277 (compare:CC (match_dup 0)
13278 (const_int 0)))]
13279 "")
13281 (define_insn ""
13282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13283 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13284 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13285 "! TARGET_POWERPC64"
13286 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13287 [(set_attr "length" "8")])
13289 (define_insn ""
13290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13291 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13292 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13293 "TARGET_POWERPC64"
13294 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13295 [(set_attr "length" "8")])
13296 \f
13297 ;; Define both directions of branch and return. If we need a reload
13298 ;; register, we'd rather use CR0 since it is much easier to copy a
13299 ;; register CC value to there.
13301 (define_insn ""
13302 [(set (pc)
13303 (if_then_else (match_operator 1 "branch_comparison_operator"
13304 [(match_operand 2
13305 "cc_reg_operand" "y")
13306 (const_int 0)])
13307 (label_ref (match_operand 0 "" ""))
13308 (pc)))]
13309 ""
13310 "*
13311 {
13312 return output_cbranch (operands[1], \"%l0\", 0, insn);
13313 }"
13314 [(set_attr "type" "branch")])
13316 (define_insn ""
13317 [(set (pc)
13318 (if_then_else (match_operator 0 "branch_comparison_operator"
13319 [(match_operand 1
13320 "cc_reg_operand" "y")
13321 (const_int 0)])
13322 (return)
13323 (pc)))]
13324 "direct_return ()"
13325 "*
13326 {
13327 return output_cbranch (operands[0], NULL, 0, insn);
13328 }"
13329 [(set_attr "type" "branch")
13330 (set_attr "length" "4")])
13332 (define_insn ""
13333 [(set (pc)
13334 (if_then_else (match_operator 1 "branch_comparison_operator"
13335 [(match_operand 2
13336 "cc_reg_operand" "y")
13337 (const_int 0)])
13338 (pc)
13339 (label_ref (match_operand 0 "" ""))))]
13340 ""
13341 "*
13342 {
13343 return output_cbranch (operands[1], \"%l0\", 1, insn);
13344 }"
13345 [(set_attr "type" "branch")])
13347 (define_insn ""
13348 [(set (pc)
13349 (if_then_else (match_operator 0 "branch_comparison_operator"
13350 [(match_operand 1
13351 "cc_reg_operand" "y")
13352 (const_int 0)])
13353 (pc)
13354 (return)))]
13355 "direct_return ()"
13356 "*
13357 {
13358 return output_cbranch (operands[0], NULL, 1, insn);
13359 }"
13360 [(set_attr "type" "branch")
13361 (set_attr "length" "4")])
13363 ;; Logic on condition register values.
13365 ; This pattern matches things like
13366 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13367 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13368 ; (const_int 1)))
13369 ; which are generated by the branch logic.
13370 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13372 (define_insn ""
13373 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13374 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13375 [(match_operator:SI 2
13376 "branch_positive_comparison_operator"
13377 [(match_operand 3
13378 "cc_reg_operand" "y,y")
13379 (const_int 0)])
13380 (match_operator:SI 4
13381 "branch_positive_comparison_operator"
13382 [(match_operand 5
13383 "cc_reg_operand" "0,y")
13384 (const_int 0)])])
13385 (const_int 1)))]
13386 ""
13387 "cr%q1 %E0,%j2,%j4"
13388 [(set_attr "type" "cr_logical,delayed_cr")])
13390 ; Why is the constant -1 here, but 1 in the previous pattern?
13391 ; Because ~1 has all but the low bit set.
13392 (define_insn ""
13393 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13394 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13395 [(not:SI (match_operator:SI 2
13396 "branch_positive_comparison_operator"
13397 [(match_operand 3
13398 "cc_reg_operand" "y,y")
13399 (const_int 0)]))
13400 (match_operator:SI 4
13401 "branch_positive_comparison_operator"
13402 [(match_operand 5
13403 "cc_reg_operand" "0,y")
13404 (const_int 0)])])
13405 (const_int -1)))]
13406 ""
13407 "cr%q1 %E0,%j2,%j4"
13408 [(set_attr "type" "cr_logical,delayed_cr")])
13410 (define_insn ""
13411 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13412 (compare:CCEQ (match_operator:SI 1
13413 "branch_positive_comparison_operator"
13414 [(match_operand 2
13415 "cc_reg_operand" "0,y")
13416 (const_int 0)])
13417 (const_int 0)))]
13418 "!TARGET_SPE"
13419 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13420 [(set_attr "type" "cr_logical,delayed_cr")])
13422 ;; If we are comparing the result of two comparisons, this can be done
13423 ;; using creqv or crxor.
13425 (define_insn_and_split ""
13426 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13427 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13428 [(match_operand 2 "cc_reg_operand" "y")
13429 (const_int 0)])
13430 (match_operator 3 "branch_comparison_operator"
13431 [(match_operand 4 "cc_reg_operand" "y")
13432 (const_int 0)])))]
13433 ""
13434 "#"
13435 ""
13436 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13437 (match_dup 5)))]
13438 "
13439 {
13440 int positive_1, positive_2;
13442 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13443 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13445 if (! positive_1)
13446 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
13447 GET_CODE (operands[1])),
13448 SImode,
13449 operands[2], const0_rtx);
13450 else if (GET_MODE (operands[1]) != SImode)
13451 operands[1] = gen_rtx (GET_CODE (operands[1]),
13452 SImode,
13453 operands[2], const0_rtx);
13455 if (! positive_2)
13456 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
13457 GET_CODE (operands[3])),
13458 SImode,
13459 operands[4], const0_rtx);
13460 else if (GET_MODE (operands[3]) != SImode)
13461 operands[3] = gen_rtx (GET_CODE (operands[3]),
13462 SImode,
13463 operands[4], const0_rtx);
13465 if (positive_1 == positive_2)
13466 {
13467 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13468 operands[5] = constm1_rtx;
13469 }
13470 else
13471 {
13472 operands[5] = const1_rtx;
13473 }
13474 }")
13476 ;; Unconditional branch and return.
13478 (define_insn "jump"
13479 [(set (pc)
13480 (label_ref (match_operand 0 "" "")))]
13481 ""
13482 "b %l0"
13483 [(set_attr "type" "branch")])
13485 (define_insn "return"
13486 [(return)]
13487 "direct_return ()"
13488 "{br|blr}"
13489 [(set_attr "type" "jmpreg")])
13491 (define_expand "indirect_jump"
13492 [(set (pc) (match_operand 0 "register_operand" ""))]
13493 ""
13494 "
13495 {
13496 if (TARGET_32BIT)
13497 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13498 else
13499 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13500 DONE;
13501 }")
13503 (define_insn "indirect_jumpsi"
13504 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13505 "TARGET_32BIT"
13506 "@
13507 bctr
13508 {br|blr}"
13509 [(set_attr "type" "jmpreg")])
13511 (define_insn "indirect_jumpdi"
13512 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13513 "TARGET_64BIT"
13514 "@
13515 bctr
13516 blr"
13517 [(set_attr "type" "jmpreg")])
13519 ;; Table jump for switch statements:
13520 (define_expand "tablejump"
13521 [(use (match_operand 0 "" ""))
13522 (use (label_ref (match_operand 1 "" "")))]
13523 ""
13524 "
13525 {
13526 if (TARGET_32BIT)
13527 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13528 else
13529 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13530 DONE;
13531 }")
13533 (define_expand "tablejumpsi"
13534 [(set (match_dup 3)
13535 (plus:SI (match_operand:SI 0 "" "")
13536 (match_dup 2)))
13537 (parallel [(set (pc) (match_dup 3))
13538 (use (label_ref (match_operand 1 "" "")))])]
13539 "TARGET_32BIT"
13540 "
13541 { operands[0] = force_reg (SImode, operands[0]);
13542 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13543 operands[3] = gen_reg_rtx (SImode);
13544 }")
13546 (define_expand "tablejumpdi"
13547 [(set (match_dup 4)
13548 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13549 (set (match_dup 3)
13550 (plus:DI (match_dup 4)
13551 (match_dup 2)))
13552 (parallel [(set (pc) (match_dup 3))
13553 (use (label_ref (match_operand 1 "" "")))])]
13554 "TARGET_64BIT"
13555 "
13556 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13557 operands[3] = gen_reg_rtx (DImode);
13558 operands[4] = gen_reg_rtx (DImode);
13559 }")
13561 (define_insn ""
13562 [(set (pc)
13563 (match_operand:SI 0 "register_operand" "c,*l"))
13564 (use (label_ref (match_operand 1 "" "")))]
13565 "TARGET_32BIT"
13566 "@
13567 bctr
13568 {br|blr}"
13569 [(set_attr "type" "jmpreg")])
13571 (define_insn ""
13572 [(set (pc)
13573 (match_operand:DI 0 "register_operand" "c,*l"))
13574 (use (label_ref (match_operand 1 "" "")))]
13575 "TARGET_64BIT"
13576 "@
13577 bctr
13578 blr"
13579 [(set_attr "type" "jmpreg")])
13581 (define_insn "nop"
13582 [(const_int 0)]
13583 ""
13584 "{cror 0,0,0|nop}")
13585 \f
13586 ;; Define the subtract-one-and-jump insns, starting with the template
13587 ;; so loop.c knows what to generate.
13589 (define_expand "doloop_end"
13590 [(use (match_operand 0 "" "")) ; loop pseudo
13591 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13592 (use (match_operand 2 "" "")) ; max iterations
13593 (use (match_operand 3 "" "")) ; loop level
13594 (use (match_operand 4 "" ""))] ; label
13595 ""
13596 "
13597 {
13598 /* Only use this on innermost loops. */
13599 if (INTVAL (operands[3]) > 1)
13600 FAIL;
13601 if (TARGET_POWERPC64)
13602 {
13603 if (GET_MODE (operands[0]) != DImode)
13604 FAIL;
13605 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13606 }
13607 else
13608 {
13609 if (GET_MODE (operands[0]) != SImode)
13610 FAIL;
13611 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13612 }
13613 DONE;
13614 }")
13616 (define_expand "ctrsi"
13617 [(parallel [(set (pc)
13618 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13619 (const_int 1))
13620 (label_ref (match_operand 1 "" ""))
13621 (pc)))
13622 (set (match_dup 0)
13623 (plus:SI (match_dup 0)
13624 (const_int -1)))
13625 (clobber (match_scratch:CC 2 ""))
13626 (clobber (match_scratch:SI 3 ""))])]
13627 "! TARGET_POWERPC64"
13628 "")
13630 (define_expand "ctrdi"
13631 [(parallel [(set (pc)
13632 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13633 (const_int 1))
13634 (label_ref (match_operand 1 "" ""))
13635 (pc)))
13636 (set (match_dup 0)
13637 (plus:DI (match_dup 0)
13638 (const_int -1)))
13639 (clobber (match_scratch:CC 2 ""))
13640 (clobber (match_scratch:DI 3 ""))])]
13641 "TARGET_POWERPC64"
13642 "")
13644 ;; We need to be able to do this for any operand, including MEM, or we
13645 ;; will cause reload to blow up since we don't allow output reloads on
13646 ;; JUMP_INSNs.
13647 ;; For the length attribute to be calculated correctly, the
13648 ;; label MUST be operand 0.
13650 (define_insn "*ctrsi_internal1"
13651 [(set (pc)
13652 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13653 (const_int 1))
13654 (label_ref (match_operand 0 "" ""))
13655 (pc)))
13656 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13657 (plus:SI (match_dup 1)
13658 (const_int -1)))
13659 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13660 (clobber (match_scratch:SI 4 "=X,X,r"))]
13661 "! TARGET_POWERPC64"
13662 "*
13663 {
13664 if (which_alternative != 0)
13665 return \"#\";
13666 else if (get_attr_length (insn) == 4)
13667 return \"{bdn|bdnz} %l0\";
13668 else
13669 return \"bdz $+8\;b %l0\";
13670 }"
13671 [(set_attr "type" "branch")
13672 (set_attr "length" "4,12,16")])
13674 (define_insn "*ctrsi_internal2"
13675 [(set (pc)
13676 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13677 (const_int 1))
13678 (pc)
13679 (label_ref (match_operand 0 "" ""))))
13680 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13681 (plus:SI (match_dup 1)
13682 (const_int -1)))
13683 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13684 (clobber (match_scratch:SI 4 "=X,X,r"))]
13685 "! TARGET_POWERPC64"
13686 "*
13687 {
13688 if (which_alternative != 0)
13689 return \"#\";
13690 else if (get_attr_length (insn) == 4)
13691 return \"bdz %l0\";
13692 else
13693 return \"{bdn|bdnz} $+8\;b %l0\";
13694 }"
13695 [(set_attr "type" "branch")
13696 (set_attr "length" "4,12,16")])
13698 (define_insn "*ctrdi_internal1"
13699 [(set (pc)
13700 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
13701 (const_int 1))
13702 (label_ref (match_operand 0 "" ""))
13703 (pc)))
13704 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13705 (plus:DI (match_dup 1)
13706 (const_int -1)))
13707 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13708 (clobber (match_scratch:DI 4 "=X,X,r"))]
13709 "TARGET_POWERPC64"
13710 "*
13711 {
13712 if (which_alternative != 0)
13713 return \"#\";
13714 else if (get_attr_length (insn) == 4)
13715 return \"{bdn|bdnz} %l0\";
13716 else
13717 return \"bdz $+8\;b %l0\";
13718 }"
13719 [(set_attr "type" "branch")
13720 (set_attr "length" "4,12,16")])
13722 (define_insn "*ctrdi_internal2"
13723 [(set (pc)
13724 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
13725 (const_int 1))
13726 (pc)
13727 (label_ref (match_operand 0 "" ""))))
13728 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13729 (plus:DI (match_dup 1)
13730 (const_int -1)))
13731 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13732 (clobber (match_scratch:DI 4 "=X,X,r"))]
13733 "TARGET_POWERPC64"
13734 "*
13735 {
13736 if (which_alternative != 0)
13737 return \"#\";
13738 else if (get_attr_length (insn) == 4)
13739 return \"bdz %l0\";
13740 else
13741 return \"{bdn|bdnz} $+8\;b %l0\";
13742 }"
13743 [(set_attr "type" "branch")
13744 (set_attr "length" "4,12,16")])
13746 ;; Similar, but we can use GE since we have a REG_NONNEG.
13748 (define_insn "*ctrsi_internal3"
13749 [(set (pc)
13750 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13751 (const_int 0))
13752 (label_ref (match_operand 0 "" ""))
13753 (pc)))
13754 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13755 (plus:SI (match_dup 1)
13756 (const_int -1)))
13757 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13758 (clobber (match_scratch:SI 4 "=X,X,r"))]
13759 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13760 "*
13761 {
13762 if (which_alternative != 0)
13763 return \"#\";
13764 else if (get_attr_length (insn) == 4)
13765 return \"{bdn|bdnz} %l0\";
13766 else
13767 return \"bdz $+8\;b %l0\";
13768 }"
13769 [(set_attr "type" "branch")
13770 (set_attr "length" "4,12,16")])
13772 (define_insn "*ctrsi_internal4"
13773 [(set (pc)
13774 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13775 (const_int 0))
13776 (pc)
13777 (label_ref (match_operand 0 "" ""))))
13778 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13779 (plus:SI (match_dup 1)
13780 (const_int -1)))
13781 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13782 (clobber (match_scratch:SI 4 "=X,X,r"))]
13783 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13784 "*
13785 {
13786 if (which_alternative != 0)
13787 return \"#\";
13788 else if (get_attr_length (insn) == 4)
13789 return \"bdz %l0\";
13790 else
13791 return \"{bdn|bdnz} $+8\;b %l0\";
13792 }"
13793 [(set_attr "type" "branch")
13794 (set_attr "length" "4,12,16")])
13796 (define_insn "*ctrdi_internal3"
13797 [(set (pc)
13798 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
13799 (const_int 0))
13800 (label_ref (match_operand 0 "" ""))
13801 (pc)))
13802 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13803 (plus:DI (match_dup 1)
13804 (const_int -1)))
13805 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13806 (clobber (match_scratch:DI 4 "=X,X,r"))]
13807 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13808 "*
13809 {
13810 if (which_alternative != 0)
13811 return \"#\";
13812 else if (get_attr_length (insn) == 4)
13813 return \"{bdn|bdnz} %l0\";
13814 else
13815 return \"bdz $+8\;b %l0\";
13816 }"
13817 [(set_attr "type" "branch")
13818 (set_attr "length" "4,12,16")])
13820 (define_insn "*ctrdi_internal4"
13821 [(set (pc)
13822 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
13823 (const_int 0))
13824 (pc)
13825 (label_ref (match_operand 0 "" ""))))
13826 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13827 (plus:DI (match_dup 1)
13828 (const_int -1)))
13829 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13830 (clobber (match_scratch:DI 4 "=X,X,r"))]
13831 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13832 "*
13833 {
13834 if (which_alternative != 0)
13835 return \"#\";
13836 else if (get_attr_length (insn) == 4)
13837 return \"bdz %l0\";
13838 else
13839 return \"{bdn|bdnz} $+8\;b %l0\";
13840 }"
13841 [(set_attr "type" "branch")
13842 (set_attr "length" "4,12,16")])
13844 ;; Similar but use EQ
13846 (define_insn "*ctrsi_internal5"
13847 [(set (pc)
13848 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13849 (const_int 1))
13850 (label_ref (match_operand 0 "" ""))
13851 (pc)))
13852 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13853 (plus:SI (match_dup 1)
13854 (const_int -1)))
13855 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13856 (clobber (match_scratch:SI 4 "=X,X,r"))]
13857 "! TARGET_POWERPC64"
13858 "*
13859 {
13860 if (which_alternative != 0)
13861 return \"#\";
13862 else if (get_attr_length (insn) == 4)
13863 return \"bdz %l0\";
13864 else
13865 return \"{bdn|bdnz} $+8\;b %l0\";
13866 }"
13867 [(set_attr "type" "branch")
13868 (set_attr "length" "4,12,16")])
13870 (define_insn "*ctrsi_internal6"
13871 [(set (pc)
13872 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13873 (const_int 1))
13874 (pc)
13875 (label_ref (match_operand 0 "" ""))))
13876 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13877 (plus:SI (match_dup 1)
13878 (const_int -1)))
13879 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13880 (clobber (match_scratch:SI 4 "=X,X,r"))]
13881 "! TARGET_POWERPC64"
13882 "*
13883 {
13884 if (which_alternative != 0)
13885 return \"#\";
13886 else if (get_attr_length (insn) == 4)
13887 return \"{bdn|bdnz} %l0\";
13888 else
13889 return \"bdz $+8\;b %l0\";
13890 }"
13891 [(set_attr "type" "branch")
13892 (set_attr "length" "4,12,16")])
13894 (define_insn "*ctrdi_internal5"
13895 [(set (pc)
13896 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
13897 (const_int 1))
13898 (label_ref (match_operand 0 "" ""))
13899 (pc)))
13900 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13901 (plus:DI (match_dup 1)
13902 (const_int -1)))
13903 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13904 (clobber (match_scratch:DI 4 "=X,X,r"))]
13905 "TARGET_POWERPC64"
13906 "*
13907 {
13908 if (which_alternative != 0)
13909 return \"#\";
13910 else if (get_attr_length (insn) == 4)
13911 return \"bdz %l0\";
13912 else
13913 return \"{bdn|bdnz} $+8\;b %l0\";
13914 }"
13915 [(set_attr "type" "branch")
13916 (set_attr "length" "4,12,16")])
13918 (define_insn "*ctrdi_internal6"
13919 [(set (pc)
13920 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
13921 (const_int 1))
13922 (pc)
13923 (label_ref (match_operand 0 "" ""))))
13924 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13925 (plus:DI (match_dup 1)
13926 (const_int -1)))
13927 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13928 (clobber (match_scratch:DI 4 "=X,X,r"))]
13929 "TARGET_POWERPC64"
13930 "*
13931 {
13932 if (which_alternative != 0)
13933 return \"#\";
13934 else if (get_attr_length (insn) == 4)
13935 return \"{bdn|bdnz} %l0\";
13936 else
13937 return \"bdz $+8\;b %l0\";
13938 }"
13939 [(set_attr "type" "branch")
13940 (set_attr "length" "4,12,16")])
13942 ;; Now the splitters if we could not allocate the CTR register
13944 (define_split
13945 [(set (pc)
13946 (if_then_else (match_operator 2 "comparison_operator"
13947 [(match_operand:SI 1 "gpc_reg_operand" "")
13948 (const_int 1)])
13949 (match_operand 5 "" "")
13950 (match_operand 6 "" "")))
13951 (set (match_operand:SI 0 "gpc_reg_operand" "")
13952 (plus:SI (match_dup 1)
13953 (const_int -1)))
13954 (clobber (match_scratch:CC 3 ""))
13955 (clobber (match_scratch:SI 4 ""))]
13956 "! TARGET_POWERPC64 && reload_completed"
13957 [(parallel [(set (match_dup 3)
13958 (compare:CC (plus:SI (match_dup 1)
13959 (const_int -1))
13960 (const_int 0)))
13961 (set (match_dup 0)
13962 (plus:SI (match_dup 1)
13963 (const_int -1)))])
13964 (set (pc) (if_then_else (match_dup 7)
13965 (match_dup 5)
13966 (match_dup 6)))]
13967 "
13968 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13969 const0_rtx); }")
13971 (define_split
13972 [(set (pc)
13973 (if_then_else (match_operator 2 "comparison_operator"
13974 [(match_operand:SI 1 "gpc_reg_operand" "")
13975 (const_int 1)])
13976 (match_operand 5 "" "")
13977 (match_operand 6 "" "")))
13978 (set (match_operand:SI 0 "nonimmediate_operand" "")
13979 (plus:SI (match_dup 1) (const_int -1)))
13980 (clobber (match_scratch:CC 3 ""))
13981 (clobber (match_scratch:SI 4 ""))]
13982 "! TARGET_POWERPC64 && reload_completed
13983 && ! gpc_reg_operand (operands[0], SImode)"
13984 [(parallel [(set (match_dup 3)
13985 (compare:CC (plus:SI (match_dup 1)
13986 (const_int -1))
13987 (const_int 0)))
13988 (set (match_dup 4)
13989 (plus:SI (match_dup 1)
13990 (const_int -1)))])
13991 (set (match_dup 0)
13992 (match_dup 4))
13993 (set (pc) (if_then_else (match_dup 7)
13994 (match_dup 5)
13995 (match_dup 6)))]
13996 "
13997 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13998 const0_rtx); }")
13999 (define_split
14000 [(set (pc)
14001 (if_then_else (match_operator 2 "comparison_operator"
14002 [(match_operand:DI 1 "gpc_reg_operand" "")
14003 (const_int 1)])
14004 (match_operand 5 "" "")
14005 (match_operand 6 "" "")))
14006 (set (match_operand:DI 0 "gpc_reg_operand" "")
14007 (plus:DI (match_dup 1)
14008 (const_int -1)))
14009 (clobber (match_scratch:CC 3 ""))
14010 (clobber (match_scratch:DI 4 ""))]
14011 "TARGET_POWERPC64 && reload_completed"
14012 [(parallel [(set (match_dup 3)
14013 (compare:CC (plus:DI (match_dup 1)
14014 (const_int -1))
14015 (const_int 0)))
14016 (set (match_dup 0)
14017 (plus:DI (match_dup 1)
14018 (const_int -1)))])
14019 (set (pc) (if_then_else (match_dup 7)
14020 (match_dup 5)
14021 (match_dup 6)))]
14022 "
14023 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14024 const0_rtx); }")
14026 (define_split
14027 [(set (pc)
14028 (if_then_else (match_operator 2 "comparison_operator"
14029 [(match_operand:DI 1 "gpc_reg_operand" "")
14030 (const_int 1)])
14031 (match_operand 5 "" "")
14032 (match_operand 6 "" "")))
14033 (set (match_operand:DI 0 "nonimmediate_operand" "")
14034 (plus:DI (match_dup 1) (const_int -1)))
14035 (clobber (match_scratch:CC 3 ""))
14036 (clobber (match_scratch:DI 4 ""))]
14037 "TARGET_POWERPC64 && reload_completed
14038 && ! gpc_reg_operand (operands[0], DImode)"
14039 [(parallel [(set (match_dup 3)
14040 (compare:CC (plus:DI (match_dup 1)
14041 (const_int -1))
14042 (const_int 0)))
14043 (set (match_dup 4)
14044 (plus:DI (match_dup 1)
14045 (const_int -1)))])
14046 (set (match_dup 0)
14047 (match_dup 4))
14048 (set (pc) (if_then_else (match_dup 7)
14049 (match_dup 5)
14050 (match_dup 6)))]
14051 "
14052 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14053 const0_rtx); }")
14055 \f
14056 (define_insn "trap"
14057 [(trap_if (const_int 1) (const_int 0))]
14058 ""
14059 "{t 31,0,0|trap}")
14061 (define_expand "conditional_trap"
14062 [(trap_if (match_operator 0 "trap_comparison_operator"
14063 [(match_dup 2) (match_dup 3)])
14064 (match_operand 1 "const_int_operand" ""))]
14065 ""
14066 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14067 operands[2] = rs6000_compare_op0;
14068 operands[3] = rs6000_compare_op1;")
14070 (define_insn ""
14071 [(trap_if (match_operator 0 "trap_comparison_operator"
14072 [(match_operand:SI 1 "register_operand" "r")
14073 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14074 (const_int 0))]
14075 ""
14076 "{t|tw}%V0%I2 %1,%2")
14078 (define_insn ""
14079 [(trap_if (match_operator 0 "trap_comparison_operator"
14080 [(match_operand:DI 1 "register_operand" "r")
14081 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14082 (const_int 0))]
14083 "TARGET_POWERPC64"
14084 "td%V0%I2 %1,%2")
14085 \f
14086 ;; Insns related to generating the function prologue and epilogue.
14088 (define_expand "prologue"
14089 [(use (const_int 0))]
14090 "TARGET_SCHED_PROLOG"
14091 "
14092 {
14093 rs6000_emit_prologue ();
14094 DONE;
14095 }")
14097 (define_insn "movesi_from_cr"
14098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14099 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14100 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
14101 ""
14102 "mfcr %0"
14103 [(set_attr "type" "mfcr")])
14105 (define_insn "*stmw"
14106 [(match_parallel 0 "stmw_operation"
14107 [(set (match_operand:SI 1 "memory_operand" "=m")
14108 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14109 "TARGET_MULTIPLE"
14110 "{stm|stmw} %2,%1")
14112 (define_insn "*save_fpregs_si"
14113 [(match_parallel 0 "any_operand"
14114 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14115 (use (match_operand:SI 2 "call_operand" "s"))
14116 (set (match_operand:DF 3 "memory_operand" "=m")
14117 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14118 "TARGET_32BIT"
14119 "bl %z2")
14121 (define_insn "*save_fpregs_di"
14122 [(match_parallel 0 "any_operand"
14123 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14124 (use (match_operand:DI 2 "call_operand" "s"))
14125 (set (match_operand:DF 3 "memory_operand" "=m")
14126 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14127 "TARGET_64BIT"
14128 "bl %z2")
14130 ; These are to explain that changes to the stack pointer should
14131 ; not be moved over stores to stack memory.
14132 (define_insn "stack_tie"
14133 [(set (match_operand:BLK 0 "memory_operand" "+m")
14134 (unspec:BLK [(match_dup 0)] 5))]
14135 ""
14136 ""
14137 [(set_attr "length" "0")])
14140 (define_expand "epilogue"
14141 [(use (const_int 0))]
14142 "TARGET_SCHED_PROLOG"
14143 "
14144 {
14145 rs6000_emit_epilogue (FALSE);
14146 DONE;
14147 }")
14149 ; On some processors, doing the mtcrf one CC register at a time is
14150 ; faster (like on the 604e). On others, doing them all at once is
14151 ; faster; for instance, on the 601 and 750.
14153 (define_expand "movsi_to_cr_one"
14154 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14155 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14156 (match_dup 2)] 20))]
14157 ""
14158 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14160 (define_insn "*movsi_to_cr"
14161 [(match_parallel 0 "mtcrf_operation"
14162 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14163 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14164 (match_operand 3 "immediate_operand" "n")]
14165 20))])]
14166 ""
14167 "*
14168 {
14169 int mask = 0;
14170 int i;
14171 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14172 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14173 operands[4] = GEN_INT (mask);
14174 return \"mtcrf %4,%2\";
14175 }"
14176 [(set_attr "type" "mtcr")])
14178 (define_insn "*mtcrfsi"
14179 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14180 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14181 (match_operand 2 "immediate_operand" "n")] 20))]
14182 "GET_CODE (operands[0]) == REG
14183 && CR_REGNO_P (REGNO (operands[0]))
14184 && GET_CODE (operands[2]) == CONST_INT
14185 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14186 "mtcrf %R0,%1"
14187 [(set_attr "type" "mtcr")])
14189 ; The load-multiple instructions have similar properties.
14190 ; Note that "load_multiple" is a name known to the machine-independent
14191 ; code that actually corresponds to the powerpc load-string.
14193 (define_insn "*lmw"
14194 [(match_parallel 0 "lmw_operation"
14195 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14196 (match_operand:SI 2 "memory_operand" "m"))])]
14197 "TARGET_MULTIPLE"
14198 "{lm|lmw} %1,%2")
14200 (define_insn "*return_internal_si"
14201 [(return)
14202 (use (match_operand:SI 0 "register_operand" "lc"))]
14203 "TARGET_32BIT"
14204 "b%T0"
14205 [(set_attr "type" "jmpreg")])
14207 (define_insn "*return_internal_di"
14208 [(return)
14209 (use (match_operand:DI 0 "register_operand" "lc"))]
14210 "TARGET_64BIT"
14211 "b%T0"
14212 [(set_attr "type" "jmpreg")])
14214 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14215 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14217 (define_insn "*return_and_restore_fpregs_si"
14218 [(match_parallel 0 "any_operand"
14219 [(return)
14220 (use (match_operand:SI 1 "register_operand" "l"))
14221 (use (match_operand:SI 2 "call_operand" "s"))
14222 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14223 (match_operand:DF 4 "memory_operand" "m"))])]
14224 "TARGET_32BIT"
14225 "b %z2")
14227 (define_insn "*return_and_restore_fpregs_di"
14228 [(match_parallel 0 "any_operand"
14229 [(return)
14230 (use (match_operand:DI 1 "register_operand" "l"))
14231 (use (match_operand:DI 2 "call_operand" "s"))
14232 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14233 (match_operand:DF 4 "memory_operand" "m"))])]
14234 "TARGET_64BIT"
14235 "b %z2")
14237 ; This is used in compiling the unwind routines.
14238 (define_expand "eh_return"
14239 [(use (match_operand 0 "general_operand" ""))
14240 (use (match_operand 1 "general_operand" ""))]
14241 ""
14242 "
14243 {
14244 #if TARGET_AIX
14245 rs6000_emit_eh_toc_restore (operands[0]);
14246 #endif
14247 if (TARGET_32BIT)
14248 emit_insn (gen_eh_set_lr_si (operands[1]));
14249 else
14250 emit_insn (gen_eh_set_lr_di (operands[1]));
14251 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
14252 DONE;
14253 }")
14255 ; We can't expand this before we know where the link register is stored.
14256 (define_insn "eh_set_lr_si"
14257 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
14258 (clobber (match_scratch:SI 1 "=&b"))]
14259 "TARGET_32BIT"
14260 "#")
14262 (define_insn "eh_set_lr_di"
14263 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
14264 (clobber (match_scratch:DI 1 "=&b"))]
14265 "TARGET_64BIT"
14266 "#")
14268 (define_split
14269 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
14270 (clobber (match_scratch 1 ""))]
14271 "reload_completed"
14272 [(const_int 0)]
14273 "
14274 {
14275 rs6000_stack_t *info = rs6000_stack_info ();
14277 if (info->lr_save_p)
14278 {
14279 rtx frame_rtx = stack_pointer_rtx;
14280 int sp_offset = 0;
14281 rtx tmp;
14283 if (frame_pointer_needed
14284 || current_function_calls_alloca
14285 || info->total_size > 32767)
14286 {
14287 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
14288 frame_rtx = operands[1];
14289 }
14290 else if (info->push_p)
14291 sp_offset = info->total_size;
14293 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14294 tmp = gen_rtx_MEM (Pmode, tmp);
14295 emit_move_insn (tmp, operands[0]);
14296 }
14297 else
14298 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14299 DONE;
14300 }")
14302 (define_insn "prefetch"
14303 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14304 (match_operand:SI 1 "const_int_operand" "n")
14305 (match_operand:SI 2 "const_int_operand" "n"))]
14306 "TARGET_POWERPC"
14307 "*
14308 {
14309 if (GET_CODE (operands[0]) == REG)
14310 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14311 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14312 }"
14313 [(set_attr "type" "load")])
14315 (include "altivec.md")
14316 (include "spe.md")