1 ;; Scheduling description for Motorola PowerPC processor cores.
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 (define_automaton "mpc,mpcfp")
22 (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
23 (define_cpu_unit "fpu_mpc" "mpcfp")
24 (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
26 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
29 (define_insn_reservation "mpccore-load" 2
30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
31 (eq_attr "cpu" "mpccore"))
34 (define_insn_reservation "mpccore-store" 1
35 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
36 (eq_attr "cpu" "mpccore"))
39 (define_insn_reservation "mpccore-fpload" 2
40 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
41 (eq_attr "cpu" "mpccore"))
44 (define_insn_reservation "mpccore-integer" 1
45 (and (eq_attr "type" "integer")
46 (eq_attr "cpu" "mpccore"))
49 (define_insn_reservation "mpccore-imul" 2
50 (and (eq_attr "type" "imul,imul2,imul3")
51 (eq_attr "cpu" "mpccore"))
54 ; Divide latency varies greatly from 2-11, use 6 as average
55 (define_insn_reservation "mpccore-idiv" 6
56 (and (eq_attr "type" "idiv")
57 (eq_attr "cpu" "mpccore"))
60 (define_insn_reservation "mpccore-compare" 3
61 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
62 (eq_attr "cpu" "mpccore"))
63 "iu_mpc,nothing,bpu_mpc")
65 (define_insn_reservation "mpccore-fpcompare" 2
66 (and (eq_attr "type" "fpcompare")
67 (eq_attr "cpu" "mpccore"))
70 (define_insn_reservation "mpccore-fp" 4
71 (and (eq_attr "type" "fp")
72 (eq_attr "cpu" "mpccore"))
75 (define_insn_reservation "mpccore-dmul" 5
76 (and (eq_attr "type" "dmul")
77 (eq_attr "cpu" "mpccore"))
80 (define_insn_reservation "mpccore-sdiv" 10
81 (and (eq_attr "type" "sdiv")
82 (eq_attr "cpu" "mpccore"))
85 (define_insn_reservation "mpccore-ddiv" 17
86 (and (eq_attr "type" "ddiv")
87 (eq_attr "cpu" "mpccore"))
90 (define_insn_reservation "mpccore-mtjmpr" 4
91 (and (eq_attr "type" "mtjmpr")
92 (eq_attr "cpu" "mpccore"))
95 (define_insn_reservation "mpccore-jmpreg" 1
96 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr")
97 (eq_attr "cpu" "mpccore"))