| blob | 218686117b4267826c920f2be411bc00652b93a6 |
1 ;;- Machine description for GNU compiler, ns32000 Version
2 ;; Copyright (C) 1988, 1994, 1996, 1998, 1999, 2000, 2001, 2002
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
24 ; BUGS:
25 ;; Insert no-op between an insn with memory read-write operands
26 ;; following by a scale-indexing operation.
27 ;; The Sequent assembler does not allow addresses to be used
28 ;; except in insns which explicitly compute an effective address.
29 ;; I.e., one cannot say "cmpd _p,@_x"
30 ;; Implement unsigned multiplication??
32 ;;- Instruction patterns. When multiple patterns apply,
33 ;;- the first one in the file is chosen.
34 ;;-
35 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36 ;;-
37 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38 ;;- updates for most instructions.
40 ;; We don't want to allow a constant operand for test insns because
41 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
42 ;; be folded while optimizing anyway.
43 ;;
44 ;; In order for pic mode to work we cannot generate, for example
45 ;;
46 ;; addd _x+5,r1
47 ;;
48 ;; instead we must force gcc to generate something like
49 ;;
50 ;; addr 5(_x(sb)),r0
51 ;; addd r0,r1
52 ;;
53 ;; This was done through operand constraints (using "rmn" in place of "g"),
54 ;; but with the proper definition of LEGITIMATE_PIC_OPERAND (ns32k.h)
55 ;; this is unnecessary.
56 ;;
58 ;; It seems that in current CVS (2000-01-11), at least with
59 ;; libgcc2.a, that register allocation gets worse when changing
60 ;; "general_operand" "0" to "nonimmediate_operand" "0" (and
61 ;; similar "0"-containing constraints), if operand 0 is (e.g.)
62 ;; "nonimmediate_operand" "=rm". Revisit and test later.
64 (define_insn "tstsi"
65 [(set (cc0)
66 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
67 ""
68 "*
69 { cc_status.flags |= CC_REVERSED;
70 operands[1] = const0_rtx;
71 return \"cmpqd %1,%0\"; }")
73 (define_insn "tsthi"
74 [(set (cc0)
75 (match_operand:HI 0 "nonimmediate_operand" "rm"))]
76 ""
77 "*
78 { cc_status.flags |= CC_REVERSED;
79 operands[1] = const0_rtx;
80 return \"cmpqw %1,%0\"; }")
82 (define_insn "tstqi"
83 [(set (cc0)
84 (match_operand:QI 0 "nonimmediate_operand" "rm"))]
85 ""
86 "*
87 { cc_status.flags |= CC_REVERSED;
88 operands[1] = const0_rtx;
89 return \"cmpqb %1,%0\"; }")
91 (define_insn "tstdf"
92 [(set (cc0)
93 (match_operand:DF 0 "general_operand" "lmF"))]
94 "TARGET_32081"
95 "*
96 { cc_status.flags |= CC_REVERSED;
97 if (TARGET_IEEE_COMPARE)
98 cc_status.flags |= CC_UNORD;
99 operands[1] = CONST0_RTX (DFmode);
100 return \"cmpl %1,%0\"; }")
102 (define_insn "tstsf"
103 [(set (cc0)
104 (match_operand:SF 0 "general_operand" "fmF"))]
105 "TARGET_32081"
106 "*
107 { cc_status.flags |= CC_REVERSED;
108 if (TARGET_IEEE_COMPARE)
109 cc_status.flags |= CC_UNORD;
110 operands[1] = CONST0_RTX (SFmode);
111 return \"cmpf %1,%0\"; }")
113 ;; See note 1
114 (define_insn "cmpsi"
115 [(set (cc0)
116 (compare (match_operand:SI 0 "general_operand" "g")
117 (match_operand:SI 1 "general_operand" "g")))]
118 ""
119 "*
120 {
121 if (GET_CODE (operands[1]) == CONST_INT)
122 {
123 int i = INTVAL (operands[1]);
124 if (i <= 7 && i >= -8)
125 {
126 cc_status.flags |= CC_REVERSED;
127 return \"cmpqd %1,%0\";
128 }
129 }
130 cc_status.flags &= ~CC_REVERSED;
131 if (GET_CODE (operands[0]) == CONST_INT)
132 {
133 int i = INTVAL (operands[0]);
134 if (i <= 7 && i >= -8)
135 return \"cmpqd %0,%1\";
136 }
137 return \"cmpd %0,%1\";
138 }")
140 (define_insn "cmphi"
141 [(set (cc0)
142 (compare (match_operand:HI 0 "general_operand" "g")
143 (match_operand:HI 1 "general_operand" "g")))]
144 ""
145 "*
146 {
147 if (GET_CODE (operands[1]) == CONST_INT)
148 {
149 short i = INTVAL (operands[1]);
150 if (i <= 7 && i >= -8)
151 {
152 cc_status.flags |= CC_REVERSED;
153 if (INTVAL (operands[1]) > 7)
154 operands[1] = GEN_INT (i);
155 return \"cmpqw %1,%0\";
156 }
157 }
158 cc_status.flags &= ~CC_REVERSED;
159 if (GET_CODE (operands[0]) == CONST_INT)
160 {
161 short i = INTVAL (operands[0]);
162 if (i <= 7 && i >= -8)
163 {
164 if (INTVAL (operands[0]) > 7)
165 operands[0] = GEN_INT (i);
166 return \"cmpqw %0,%1\";
167 }
168 }
169 return \"cmpw %0,%1\";
170 }")
172 (define_insn "cmpqi"
173 [(set (cc0)
174 (compare (match_operand:QI 0 "general_operand" "g")
175 (match_operand:QI 1 "general_operand" "g")))]
176 ""
177 "*
178 {
179 if (GET_CODE (operands[1]) == CONST_INT)
180 {
181 char i = INTVAL (operands[1]);
182 if (i <= 7 && i >= -8)
183 {
184 cc_status.flags |= CC_REVERSED;
185 if (INTVAL (operands[1]) > 7)
186 operands[1] = GEN_INT (i);
187 return \"cmpqb %1,%0\";
188 }
189 }
190 cc_status.flags &= ~CC_REVERSED;
191 if (GET_CODE (operands[0]) == CONST_INT)
192 {
193 char i = INTVAL (operands[0]);
194 if (i <= 7 && i >= -8)
195 {
196 if (INTVAL (operands[0]) > 7)
197 operands[0] = GEN_INT (i);
198 return \"cmpqb %0,%1\";
199 }
200 }
201 return \"cmpb %0,%1\";
202 }")
204 (define_insn "cmpdf"
205 [(set (cc0)
206 (compare (match_operand:DF 0 "general_operand" "lmF")
207 (match_operand:DF 1 "general_operand" "lmF")))]
208 "TARGET_32081"
209 "*
210 {
211 if (TARGET_IEEE_COMPARE)
212 cc_status.flags |= CC_UNORD;
213 return \"cmpl %0,%1\";}")
215 (define_insn "cmpsf"
216 [(set (cc0)
217 (compare (match_operand:SF 0 "general_operand" "fmF")
218 (match_operand:SF 1 "general_operand" "fmF")))]
219 "TARGET_32081"
220 "*
221 {
222 if (TARGET_IEEE_COMPARE)
223 cc_status.flags |= CC_UNORD;
224 return \"cmpf %0,%1\";}")
225 \f
226 ;; movdf and movsf copy between general and floating registers using
227 ;; the stack. In principle, we could get better code not allowing
228 ;; that case in the constraints and defining SECONDARY_MEMORY_NEEDED
229 ;; in practice, though the stack slots used are not available for
230 ;; optimization.
231 (define_insn "movdf"
232 [(set (match_operand:DF 0 "nonimmediate_operand" "=lrm<")
233 (match_operand:DF 1 "general_operand" "lFg"))]
234 ""
235 "*
236 {
237 if (FP_REG_P (operands[0]))
238 {
239 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
240 return \"movl %1,%0\";
241 if (REG_P (operands[1]))
242 {
243 rtx xoperands[2];
244 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
245 output_asm_insn (\"movd %1,tos\", xoperands);
246 output_asm_insn (\"movd %1,tos\", operands);
247 return \"movl tos,%0\";
248 }
249 return \"movl %1,%0\";
250 }
251 else if (FP_REG_P (operands[1]))
252 {
253 if (REG_P (operands[0]))
254 {
255 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
256 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
257 return \"movd tos,%0\";
258 }
259 else
260 return \"movl %1,%0\";
261 }
262 return output_move_double (operands);
263 }")
265 (define_insn "movsf"
266 [(set (match_operand:SF 0 "nonimmediate_operand" "=frm<")
267 (match_operand:SF 1 "general_operand" "fFg"))]
268 ""
269 "*
270 {
271 if (FP_REG_P (operands[0]))
272 {
273 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
274 return \"movd %1,tos\;movf tos,%0\";
275 else
276 return \"movf %1,%0\";
277 }
278 else if (FP_REG_P (operands[1]))
279 {
280 if (REG_P (operands[0]))
281 return \"movf %1,tos\;movd tos,%0\";
282 return \"movf %1,%0\";
283 }
284 #if 0 /* Someone suggested this for the Sequent. Is it needed? */
285 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
286 return \"movf %1,%0\";
287 #endif
288 /* There was a #if 0 around this, but that was erroneous
289 for many machines -- rms. */
290 #ifndef MOVD_FLOAT_OK
291 /* GAS understands floating constants in ordinary movd instructions
292 but other assemblers might object. */
293 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
294 {
295 union {int i[2]; float f; double d;} convrt;
296 convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
297 convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
298 convrt.f = convrt.d;
300 /* Is there a better machine-independent way to to this? */
301 operands[1] = GEN_INT (convrt.i[0]);
302 return \"movd %1,%0\";
303 }
304 #endif
305 else return \"movd %1,%0\";
306 }")
308 (define_insn "*movti"
309 [(set (match_operand:TI 0 "memory_operand" "=m")
310 (match_operand:TI 1 "memory_operand" "m"))]
311 ""
312 "movmd %1,%0,4")
314 (define_insn "movdi"
315 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm<,*l,rm")
316 (match_operand:DI 1 "general_operand" "gF,g,*l"))]
317 ""
318 "*
319 {
320 if (FP_REG_P (operands[0]))
321 {
322 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
323 return \"movl %1,%0\";
324 if (REG_P (operands[1]))
325 {
326 rtx xoperands[2];
327 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
328 output_asm_insn (\"movd %1,tos\", xoperands);
329 output_asm_insn (\"movd %1,tos\", operands);
330 return \"movl tos,%0\";
331 }
332 return \"movl %1,%0\";
333 }
334 else if (FP_REG_P (operands[1]))
335 {
336 if (REG_P (operands[0]))
337 {
338 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
339 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
340 return \"movd tos,%0\";
341 }
342 else
343 return \"movl %1,%0\";
344 }
345 return output_move_double (operands);
346 }")
348 ;; This special case must precede movsi.
349 (define_insn "*ldsp"
350 [(set (reg:SI 25)
351 (match_operand:SI 0 "general_operand" "g"))]
352 ""
353 "lprd sp,%0")
355 (define_insn "movsi"
356 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<,rm<,*f,rm,x")
357 (match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
358 ""
359 "*
360 {
361 extern int flag_pic;
363 if (FP_REG_P (operands[0]))
364 {
365 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
366 return \"movd %1,tos\;movf tos,%0\";
367 else
368 return \"movf %1,%0\";
369 }
370 else if (FP_REG_P (operands[1]))
371 {
372 if (REG_P (operands[0]))
373 return \"movf %1,tos\;movd tos,%0\";
374 return \"movf %1,%0\";
375 }
376 if (GET_CODE (operands[0]) == REG
377 && REGNO (operands[0]) == FRAME_POINTER_REGNUM)
378 return \"lprd fp,%1\";
379 if (GET_CODE (operands[1]) == CONST_DOUBLE)
380 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
381 if (GET_CODE (operands[1]) == CONST_INT)
382 {
383 int i = INTVAL (operands[1]);
384 if (! TARGET_32532)
385 {
386 if (i <= 7 && i >= -8)
387 return \"movqd %1,%0\";
388 if (NS32K_DISPLACEMENT_P (i))
389 #if defined (GNX_V3) || defined (UTEK_ASM)
390 return \"addr %c1,%0\";
391 #else
392 return \"addr @%c1,%0\";
393 #endif
394 return \"movd %1,%0\";
395 }
396 else
397 return output_move_dconst(i, \"%1,%0\");
398 }
399 else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
400 {
401 /* Must contain symbols so we don't know how big it is. In
402 * that case addr might lead to overflow. For PIC symbolic
403 * address loads always have to be done with addr.
404 */
405 return \"movd %1,%0\";
406 }
407 else if (GET_CODE (operands[1]) == REG)
408 {
409 if (REGNO (operands[1]) < F0_REGNUM)
410 return \"movd %1,%0\";
411 else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
412 {
413 if (GET_CODE(operands[0]) == REG)
414 return \"sprd fp,%0\";
415 else
416 return \"addr 0(fp),%0\" ;
417 }
418 else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
419 {
420 if (GET_CODE(operands[0]) == REG)
421 return \"sprd sp,%0\";
422 else
423 return \"addr 0(sp),%0\" ;
424 }
425 else abort ();
426 }
427 else if (GET_CODE (operands[1]) == MEM)
428 return \"movd %1,%0\";
430 /* Check if this effective address can be
431 calculated faster by pulling it apart. */
432 if (REG_P (operands[0])
433 && GET_CODE (operands[1]) == MULT
434 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
435 && (INTVAL (XEXP (operands[1], 1)) == 2
436 || INTVAL (XEXP (operands[1], 1)) == 4))
437 {
438 rtx xoperands[3];
439 xoperands[0] = operands[0];
440 xoperands[1] = XEXP (operands[1], 0);
441 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
442 return output_shift_insn (xoperands);
443 }
444 return \"addr %a1,%0\";
445 }")
447 (define_insn "movhi"
448 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<,*f,rm")
449 (match_operand:HI 1 "general_operand" "g,g,*f"))]
450 ""
451 "*
452 {
453 if (GET_CODE (operands[1]) == CONST_INT)
454 {
455 short i = INTVAL (operands[1]);
456 if (i <= 7 && i >= -8)
457 {
458 if (INTVAL (operands[1]) > 7)
459 operands[1] = GEN_INT (i);
460 return \"movqw %1,%0\";
461 }
462 return \"movw %1,%0\";
463 }
464 else if (FP_REG_P (operands[0]))
465 {
466 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
467 return \"movwf %1,tos\;movf tos,%0\";
468 else
469 return \"movwf %1,%0\";
470 }
471 else if (FP_REG_P (operands[1]))
472 {
473 if (REG_P (operands[0]))
474 return \"movf %1,tos\;movd tos,%0\";
475 return \"movf %1,%0\";
476 }
477 else
478 return \"movw %1,%0\";
479 }")
481 (define_insn "movstricthi"
482 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
483 (match_operand:HI 1 "general_operand" "g"))]
484 ""
485 "*
486 {
487 if (GET_CODE (operands[1]) == CONST_INT
488 && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
489 return \"movqw %1,%0\";
490 return \"movw %1,%0\";
491 }")
493 (define_insn "movqi"
494 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<,*f,rm")
495 (match_operand:QI 1 "general_operand" "g,g,*f"))]
496 ""
497 "*
498 { if (GET_CODE (operands[1]) == CONST_INT)
499 {
500 char char_val = (char)INTVAL (operands[1]);
501 if (char_val <= 7 && char_val >= -8)
502 {
503 if (INTVAL (operands[1]) > 7)
504 operands[1] = GEN_INT (char_val);
505 return \"movqb %1,%0\";
506 }
507 return \"movb %1,%0\";
508 }
509 else if (FP_REG_P (operands[0]))
510 {
511 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
512 return \"movbf %1,tos\;movf tos,%0\";
513 else
514 return \"movbf %1,%0\";
515 }
516 else if (FP_REG_P (operands[1]))
517 {
518 if (REG_P (operands[0]))
519 return \"movf %1,tos\;movd tos,%0\";
520 return \"movf %1,%0\";
521 }
522 else
523 return \"movb %1,%0\";
524 }")
526 (define_insn "movstrictqi"
527 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
528 (match_operand:QI 1 "general_operand" "g"))]
529 ""
530 "*
531 {
532 if (GET_CODE (operands[1]) == CONST_INT
533 && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
534 return \"movqb %1,%0\";
535 return \"movb %1,%0\";
536 }")
537 \f
538 ;; Block moves
539 ;; Argument 0 is the destination
540 ;; Argument 1 is the source
541 ;; Argument 2 is the length
542 ;; Argument 3 is the alignment
543 ;;
544 ;; Strategy: Use define_expand to
545 ;; either emit insns directly if it can be done simply or
546 ;; emit rtl to match movstrsi1 which has extra scratch registers
547 ;; which can be used to generate more complex code.
549 (define_expand "movstrsi"
550 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
551 (match_operand:BLK 1 "memory_operand" ""))
552 (use (match_operand:SI 2 "general_operand" ""))
553 (use (match_operand:SI 3 "const_int_operand" ""))])]
554 ""
555 "
556 {
557 if (operands[0]) /* avoid unused code messages */
558 {
559 expand_block_move (operands);
560 DONE;
561 }
562 }")
564 ;; Special Registers:
565 ;; r0 count
566 ;; r1 from
567 ;; r2 to
568 ;; r3 match
571 (define_insn "movstrsi1"
572 [(set (mem:BLK (reg:SI 2))
573 (mem:BLK (reg:SI 1)))
574 (use (reg:SI 0))
575 (set (reg:SI 2) (plus:SI (reg:SI 2) (mult:SI (reg:SI 0) (match_operand:SI 0 "const_int_operand" ""))))
576 (set (reg:SI 1) (plus:SI (reg:SI 1) (mult:SI (reg:SI 0) (match_dup 0))))
577 (set (reg:SI 0) (const_int 0))]
578 ""
579 "*
580 {
581 int align = INTVAL(operands[0]);
582 if (align == 4)
583 return \"movsd\";
584 else
585 return \"movsb\";
586 }")
588 (define_insn "movstrsi2"
589 [(set (mem:BLK (match_operand:SI 0 "address_operand" "p"))
590 (mem:BLK (match_operand:SI 1 "address_operand" "p")))
591 (use (match_operand 2 "immediate_operand" "i"))]
592 ""
593 "movmd %a1,%a0,%2")
595 \f
596 ;; Extension and truncation insns.
597 ;; Those for integer source operand
598 ;; are ordered widest source type first.
600 (define_insn "extendhisi2"
601 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
602 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
603 ""
604 "movxwd %1,%0")
606 (define_insn "extendqihi2"
607 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
608 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
609 ""
610 "movxbw %1,%0")
612 (define_insn "extendqisi2"
613 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
614 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
615 ""
616 "movxbd %1,%0")
618 (define_insn "extendsfdf2"
619 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
620 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
621 "TARGET_32081"
622 "movfl %1,%0")
624 (define_insn "truncdfsf2"
625 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
626 (float_truncate:SF (match_operand:DF 1 "general_operand" "lmF")))]
627 "TARGET_32081"
628 "movlf %1,%0")
630 (define_insn "zero_extendhisi2"
631 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
632 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
633 ""
634 "movzwd %1,%0")
636 (define_insn "zero_extendqihi2"
637 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
638 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
639 ""
640 "movzbw %1,%0")
642 (define_insn "zero_extendqisi2"
643 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
644 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
645 ""
646 "movzbd %1,%0")
647 \f
648 ;; Fix-to-float conversion insns.
649 ;; Note that the ones that start with SImode come first.
650 ;; That is so that an operand that is a CONST_INT
651 ;; (and therefore lacks a specific machine mode).
652 ;; will be recognized as SImode (which is always valid)
653 ;; rather than as QImode or HImode.
655 ;; Rumor has it that the National part does not correctly convert
656 ;; constant ints to floats. This conversion is therefore disabled.
657 ;; A register must be used to perform the conversion.
659 (define_insn "floatsisf2"
660 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
661 (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
662 "TARGET_32081"
663 "movdf %1,%0")
665 (define_insn "floatsidf2"
666 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
667 (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
668 "TARGET_32081"
669 "movdl %1,%0")
671 (define_insn "floathisf2"
672 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
673 (float:SF (match_operand:HI 1 "nonimmediate_operand" "rm")))]
674 "TARGET_32081"
675 "movwf %1,%0")
677 (define_insn "floathidf2"
678 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
679 (float:DF (match_operand:HI 1 "nonimmediate_operand" "rm")))]
680 "TARGET_32081"
681 "movwl %1,%0")
683 (define_insn "floatqisf2"
684 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
685 (float:SF (match_operand:QI 1 "nonimmediate_operand" "rm")))]
686 "TARGET_32081"
687 "movbf %1,%0")
689 ; Some assemblers warn that this insn doesn't work.
690 ; Maybe they know something we don't.
691 ;(define_insn "floatqidf2"
692 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
693 ; (float:DF (match_operand:QI 1 "nonimmediate_operand" "rm")))]
694 ; "TARGET_32081"
695 ; "movbl %1,%0")
696 \f
697 ;; Float-to-fix conversion insns.
698 ;; The sequent compiler always generates "trunc" insns.
700 (define_insn "fixsfqi2"
701 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
702 (fix:QI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
703 "TARGET_32081"
704 "truncfb %1,%0")
706 (define_insn "fixsfhi2"
707 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
708 (fix:HI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
709 "TARGET_32081"
710 "truncfw %1,%0")
712 (define_insn "fixsfsi2"
713 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
714 (fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
715 "TARGET_32081"
716 "truncfd %1,%0")
718 (define_insn "fixdfqi2"
719 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
720 (fix:QI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
721 "TARGET_32081"
722 "trunclb %1,%0")
724 (define_insn "fixdfhi2"
725 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
726 (fix:HI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
727 "TARGET_32081"
728 "trunclw %1,%0")
730 (define_insn "fixdfsi2"
731 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
732 (fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
733 "TARGET_32081"
734 "truncld %1,%0")
736 ;; Unsigned
738 (define_insn "fixunssfqi2"
739 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
740 (unsigned_fix:QI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
741 "TARGET_32081"
742 "truncfb %1,%0")
744 (define_insn "fixunssfhi2"
745 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
746 (unsigned_fix:HI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
747 "TARGET_32081"
748 "truncfw %1,%0")
750 (define_insn "fixunssfsi2"
751 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
752 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
753 "TARGET_32081"
754 "truncfd %1,%0")
756 (define_insn "fixunsdfqi2"
757 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
758 (unsigned_fix:QI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
759 "TARGET_32081"
760 "trunclb %1,%0")
762 (define_insn "fixunsdfhi2"
763 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
764 (unsigned_fix:HI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
765 "TARGET_32081"
766 "trunclw %1,%0")
768 (define_insn "fixunsdfsi2"
769 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
770 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
771 "TARGET_32081"
772 "truncld %1,%0")
774 ;;; These are not yet used by GCC
775 (define_insn "fix_truncsfqi2"
776 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
777 (fix:QI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
778 "TARGET_32081"
779 "truncfb %1,%0")
781 (define_insn "fix_truncsfhi2"
782 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
783 (fix:HI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
784 "TARGET_32081"
785 "truncfw %1,%0")
787 (define_insn "fix_truncsfsi2"
788 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
789 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
790 "TARGET_32081"
791 "truncfd %1,%0")
793 (define_insn "fix_truncdfqi2"
794 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
795 (fix:QI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
796 "TARGET_32081"
797 "trunclb %1,%0")
799 (define_insn "fix_truncdfhi2"
800 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
801 (fix:HI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
802 "TARGET_32081"
803 "trunclw %1,%0")
805 (define_insn "fix_truncdfsi2"
806 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
807 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
808 "TARGET_32081"
809 "truncld %1,%0")
810 \f
811 ;; Multiply-add instructions
812 (define_insn "*madddf"
813 [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
814 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
815 (match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
816 (match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
817 "TARGET_MULT_ADD"
818 "@
819 dotl %1,%2
820 polyl %2,%3
821 mull %2,%0\;addl %3,%0")
823 (define_insn "*maddsf"
824 [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
825 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
826 (match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
827 (match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
828 "TARGET_MULT_ADD"
829 "@
830 dotf %1,%2
831 polyf %2,%3
832 mulf %2,%0\;addf %3,%0")
835 ;; Multiply-sub instructions
836 (define_insn "*msubdf"
837 [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
838 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
839 (match_operand:DF 2 "general_operand" "lmF,lmF"))
840 (match_operand:DF 3 "general_operand" "lmF,lmF")))]
841 "TARGET_MULT_ADD"
842 "@
843 negl %3,%0\;dotl %1,%2
844 mull %2,%0\;subl %3,%0")
846 (define_insn "*msubsf"
847 [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
848 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
849 (match_operand:SF 2 "general_operand" "fmF,fmF"))
850 (match_operand:SF 3 "general_operand" "fmF,fmF")))]
851 "TARGET_MULT_ADD"
852 "@
853 negf %3,%0\;dotf %1,%2
854 mulf %2,%0\;subf %3,%0")
856 ;;- All kinds of add instructions.
858 (define_insn "adddf3"
859 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
860 (plus:DF (match_operand:DF 1 "general_operand" "%0")
861 (match_operand:DF 2 "general_operand" "lmF")))]
862 "TARGET_32081"
863 "addl %2,%0")
866 (define_insn "addsf3"
867 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
868 (plus:SF (match_operand:SF 1 "general_operand" "%0")
869 (match_operand:SF 2 "general_operand" "fmF")))]
870 "TARGET_32081"
871 "addf %2,%0")
873 (define_insn "*add_to_sp"
874 [(set (reg:SI 25)
875 (plus:SI (reg:SI 25)
876 (match_operand:SI 0 "immediate_operand" "i")))]
877 "GET_CODE (operands[0]) == CONST_INT"
878 "*
879 {
880 #ifndef SEQUENT_ADJUST_STACK
881 if (TARGET_32532)
882 if (INTVAL (operands[0]) == 8)
883 return \"cmpd tos,tos\";
884 if (TARGET_32532 || TARGET_32332)
885 if (INTVAL (operands[0]) == 4)
886 return \"cmpqd %$0,tos\";
887 #endif
888 if (! TARGET_32532)
889 {
890 if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
891 return \"adjspb %n0\";
892 else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
893 return \"adjspw %n0\";
894 }
895 return \"adjspd %n0\";
896 }")
898 (define_insn "adddi3"
899 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
900 (plus:DI (match_operand:DI 1 "general_operand" "%0")
901 (match_operand:DI 2 "general_operand" "ron")))]
902 ""
903 "*
904 {
905 rtx low[3], high[3], xops[4];
906 split_di (operands, 3, low, high);
907 xops[0] = low[0];
908 xops[1] = high[0];
909 xops[2] = low[2];
910 xops[3] = high[2];
912 if (GET_CODE (xops[2]) == CONST_INT)
913 {
914 int i = INTVAL (xops[2]);
916 if (i <= 7 && i >= -8)
917 {
918 if (i == 0)
919 {
920 i = INTVAL (xops[3]);
921 if (i <= 7 && i >= -8)
922 output_asm_insn (\"addqd %3,%1\", xops);
923 else
924 output_asm_insn (\"addd %3,%1\", xops);
925 }
926 else
927 {
928 output_asm_insn (\"addqd %2,%0\", xops);
929 output_asm_insn (\"addcd %3,%1\", xops);
930 }
931 return \"\";
932 }
933 }
934 output_asm_insn (\"addd %2,%0\", xops);
935 output_asm_insn (\"addcd %3,%1\", xops);
936 return \"\";
937 }")
939 ;; See Note 1
940 (define_insn "addsi3"
941 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
942 (plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
943 (match_operand:SI 2 "general_operand" "g,i,i")))]
944 ""
945 "*
946 {
947 if (which_alternative == 1)
948 {
949 if (GET_CODE (operands[2]) == CONST_INT)
950 {
951 int i = INTVAL (operands[2]);
952 if (NS32K_DISPLACEMENT_P (i))
953 return \"addr %c2(%1),%0\";
954 else
955 return \"movd %1,%0\;addd %2,%0\";
956 }
957 else
958 {
959 if (flag_pic)
960 return \"addr %a2[%1:b],%0\";
961 else
962 return \"addr %c2(%1),%0\";
963 }
964 }
965 else if (which_alternative == 2)
966 {
967 if (GET_CODE (operands[2]) == CONST_INT &&
968 NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
969 return \"addr %c2(%1),%0\";
970 else
971 return \"sprd %1,%0\;addd %2,%0\";
972 }
973 else if (GET_CODE (operands[2]) == CONST_INT)
974 {
975 int i = INTVAL (operands[2]);
977 if (i <= 7 && i >= -8)
978 return \"addqd %2,%0\";
979 else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
980 && NS32K_DISPLACEMENT_P (i))
981 return \"addr %c2(%0),%0\";
982 }
983 return \"addd %2,%0\";
984 }")
986 (define_insn "addhi3"
987 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
988 (plus:HI (match_operand:HI 1 "general_operand" "%0")
989 (match_operand:HI 2 "general_operand" "g")))]
990 ""
991 "*
992 { if (GET_CODE (operands[2]) == CONST_INT)
993 {
994 int i = INTVAL (operands[2]);
995 if (i <= 7 && i >= -8)
996 return \"addqw %2,%0\";
997 }
998 return \"addw %2,%0\";
999 }")
1001 (define_insn "*addhi_strict_low3"
1002 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1003 (plus:HI (match_operand:HI 1 "general_operand" "0")
1004 (match_operand:HI 2 "general_operand" "g")))]
1005 ""
1006 "*
1007 {
1008 if (GET_CODE (operands[1]) == CONST_INT
1009 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
1010 return \"addqw %2,%0\";
1011 return \"addw %2,%0\";
1012 }")
1014 (define_insn "addqi3"
1015 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1016 (plus:QI (match_operand:QI 1 "general_operand" "%0")
1017 (match_operand:QI 2 "general_operand" "g")))]
1018 ""
1019 "*
1020 { if (GET_CODE (operands[2]) == CONST_INT)
1021 {
1022 int i = INTVAL (operands[2]);
1023 if (i <= 7 && i >= -8)
1024 return \"addqb %2,%0\";
1025 }
1026 return \"addb %2,%0\";
1027 }")
1029 (define_insn "*addqi_strict_low3"
1030 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
1031 (plus:QI (match_operand:QI 1 "general_operand" "0")
1032 (match_operand:QI 2 "general_operand" "g")))]
1033 ""
1034 "*
1035 {
1036 if (GET_CODE (operands[1]) == CONST_INT
1037 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
1038 return \"addqb %2,%0\";
1039 return \"addb %2,%0\";
1040 }")
1041 \f
1042 ;;- All kinds of subtract instructions.
1044 (define_insn "subdf3"
1045 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
1046 (minus:DF (match_operand:DF 1 "general_operand" "0")
1047 (match_operand:DF 2 "general_operand" "lmF")))]
1048 "TARGET_32081"
1049 "subl %2,%0")
1051 (define_insn "subsf3"
1052 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
1053 (minus:SF (match_operand:SF 1 "general_operand" "0")
1054 (match_operand:SF 2 "general_operand" "fmF")))]
1055 "TARGET_32081"
1056 "subf %2,%0")
1058 (define_insn "*sub_from_sp"
1059 [(set (reg:SI 25)
1060 (minus:SI (reg:SI 25)
1061 (match_operand:SI 0 "immediate_operand" "i")))]
1062 "GET_CODE (operands[0]) == CONST_INT"
1063 "*
1064 {
1065 if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT
1066 && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
1067 return \"adjspb %0\";
1068 return \"adjspd %0\";
1069 }")
1071 (define_insn "subdi3"
1072 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
1073 (minus:DI (match_operand:DI 1 "general_operand" "0")
1074 (match_operand:DI 2 "general_operand" "ron")))]
1075 ""
1076 "*
1077 {
1078 rtx low[3], high[3], xops[4];
1079 split_di (operands, 3, low, high);
1080 xops[0] = low[0];
1081 xops[1] = high[0];
1082 xops[2] = low[2];
1083 xops[3] = high[2];
1085 if (GET_CODE (xops[2]) == CONST_INT)
1086 {
1087 int i = INTVAL (xops[2]);
1089 if (i <= 8 && i >= -7)
1090 {
1091 if (i == 0)
1092 {
1093 i = INTVAL (xops[3]);
1094 if (i <= 8 && i >= -7)
1095 output_asm_insn (\"addqd %n3,%1\", xops);
1096 else
1097 output_asm_insn (\"subd %3,%1\", xops);
1098 }
1099 else
1100 {
1101 output_asm_insn (\"addqd %n2,%0\", xops);
1102 output_asm_insn (\"subcd %3,%1\", xops);
1103 }
1104 return \"\";
1105 }
1106 }
1107 output_asm_insn (\"subd %2,%0\", xops);
1108 output_asm_insn (\"subcd %3,%1\", xops);
1109 return \"\";
1110 }")
1112 (define_insn "subsi3"
1113 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1114 (minus:SI (match_operand:SI 1 "general_operand" "0")
1115 (match_operand:SI 2 "general_operand" "g")))]
1116 ""
1117 "*
1118 { if (GET_CODE (operands[2]) == CONST_INT)
1119 {
1120 int i = INTVAL (operands[2]);
1122 if (i <= 8 && i >= -7)
1123 return \"addqd %n2,%0\";
1124 }
1125 return \"subd %2,%0\";
1126 }")
1128 (define_insn "subhi3"
1129 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1130 (minus:HI (match_operand:HI 1 "general_operand" "0")
1131 (match_operand:HI 2 "general_operand" "g")))]
1132 ""
1133 "*
1134 { if (GET_CODE (operands[2]) == CONST_INT)
1135 {
1136 int i = INTVAL (operands[2]);
1138 if (i <= 8 && i >= -7)
1139 return \"addqw %n2,%0\";
1140 }
1141 return \"subw %2,%0\";
1142 }")
1144 (define_insn "*subhi_strict_low3"
1145 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1146 (minus:HI (match_operand:HI 1 "general_operand" "0")
1147 (match_operand:HI 2 "general_operand" "g")))]
1148 ""
1149 "*
1150 {
1151 if (GET_CODE (operands[1]) == CONST_INT
1152 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1153 return \"addqw %n2,%0\";
1154 return \"subw %2,%0\";
1155 }")
1157 (define_insn "subqi3"
1158 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1159 (minus:QI (match_operand:QI 1 "general_operand" "0")
1160 (match_operand:QI 2 "general_operand" "g")))]
1161 ""
1162 "*
1163 { if (GET_CODE (operands[2]) == CONST_INT)
1164 {
1165 int i = INTVAL (operands[2]);
1167 if (i <= 8 && i >= -7)
1168 return \"addqb %n2,%0\";
1169 }
1170 return \"subb %2,%0\";
1171 }")
1173 (define_insn "*subqi_strict_low3"
1174 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
1175 (minus:QI (match_operand:QI 1 "general_operand" "0")
1176 (match_operand:QI 2 "general_operand" "g")))]
1177 ""
1178 "*
1179 {
1180 if (GET_CODE (operands[1]) == CONST_INT
1181 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1182 return \"addqb %n2,%0\";
1183 return \"subb %2,%0\";
1184 }")
1185 \f
1186 ;;- Multiply instructions.
1188 (define_insn "muldf3"
1189 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
1190 (mult:DF (match_operand:DF 1 "general_operand" "%0")
1191 (match_operand:DF 2 "general_operand" "lmF")))]
1192 "TARGET_32081"
1193 "mull %2,%0")
1195 (define_insn "mulsf3"
1196 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
1197 (mult:SF (match_operand:SF 1 "general_operand" "%0")
1198 (match_operand:SF 2 "general_operand" "fmF")))]
1199 "TARGET_32081"
1200 "mulf %2,%0")
1202 ;; See note 1
1203 (define_insn "mulsi3"
1204 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1205 (mult:SI (match_operand:SI 1 "general_operand" "%0")
1206 (match_operand:SI 2 "general_operand" "g")))]
1207 ""
1208 "muld %2,%0")
1210 (define_insn "mulhi3"
1211 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1212 (mult:HI (match_operand:HI 1 "general_operand" "%0")
1213 (match_operand:HI 2 "general_operand" "g")))]
1214 ""
1215 "mulw %2,%0")
1217 (define_insn "mulqi3"
1218 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1219 (mult:QI (match_operand:QI 1 "general_operand" "%0")
1220 (match_operand:QI 2 "general_operand" "g")))]
1221 ""
1222 "mulb %2,%0")
1224 (define_insn "umulsidi3"
1225 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1226 (mult:DI (zero_extend:DI
1227 (match_operand:SI 1 "nonimmediate_operand" "0"))
1228 (zero_extend:DI
1229 (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
1230 ""
1231 "meid %2,%0")
1232 \f
1233 ;; divmod insns: We can only do the unsigned case.
1234 (define_expand "udivmodsi4"
1235 [(parallel
1236 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1237 (udiv:SI (match_operand:SI 1 "general_operand" "")
1238 (match_operand:SI 2 "general_operand" "")))
1239 (set (match_operand:SI 3 "nonimmediate_operand" "")
1240 (umod:SI (match_dup 1) (match_dup 2)))])]
1241 ""
1242 "
1243 {
1244 rtx temp = gen_reg_rtx(DImode);
1245 rtx insn, first, last;
1246 first = emit_move_insn(gen_lowpart(SImode, temp), operands[1]);
1247 emit_move_insn(gen_highpart(SImode, temp), const0_rtx);
1248 emit_insn(gen_udivmoddisi4_internal(temp, temp, operands[2]));
1249 last = emit_move_insn(temp, temp);
1250 {
1251 rtx divdi, moddi, divsi, modsi;
1252 divsi = gen_rtx (UDIV, SImode, operands[1], operands[2]);
1253 modsi = gen_rtx (UMOD, SImode, operands[1], operands[2]);
1254 divdi = gen_rtx (ZERO_EXTEND, DImode, divsi);
1255 moddi = gen_rtx (ZERO_EXTEND, DImode, modsi);
1256 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1257 REG_NOTES (first));
1258 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1259 gen_rtx (EXPR_LIST, REG_EQUAL,
1260 gen_rtx (IOR, DImode, moddi,
1261 gen_rtx (ASHIFT, DImode, divdi, GEN_INT(32))),
1262 REG_NOTES (last)));
1263 }
1265 insn = emit_move_insn(operands[0], gen_highpart(SImode, temp));
1266 insn = emit_move_insn(operands[3], gen_lowpart(SImode, temp));
1267 DONE;
1268 }")
1270 ;; If we try and describe what this does, we have to zero-expand an
1271 ;; operand, which prevents it being a constant (VOIDmode) (see udivmoddisi4
1272 ;; below. This udivmoddisi4_internal never matches anything and is only
1273 ;; ever used when explicitly emitted by a define_expand.
1274 (define_insn "udivmoddisi4_internal"
1275 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1276 (unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "0")
1277 (match_operand:SI 2 "general_operand" "g")] 0))]
1278 ""
1279 "deid %2,%0")
1281 ;; Retain this insn which *does* have a pattern indicating what it does,
1282 ;; just in case the compiler is smart enough to recognize a substitution.
1283 (define_insn "udivmoddisi4"
1284 [(set (subreg:SI (match_operand:DI 0 "nonimmediate_operand" "=rm") 4)
1285 (truncate:SI (udiv:DI (match_operand:DI 1 "nonimmediate_operand" "0")
1286 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))))
1287 (set (subreg:SI (match_operand:DI 3 "nonimmediate_operand" "=0") 0)
1288 (truncate:SI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1289 ""
1290 "deid %2,%0")
1292 ;;;; Part word variants. These seem to never be used at the moment (gcc
1293 ;;;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
1294 ;;;; and use signed div and mod. Keep these insns incase that changes.
1295 ;;;; divmod should have an advantage when both div and mod are needed. However,
1296 ;;;; divmod uses two registers, so maybe the compiler knows best.
1297 ;;
1298 ;;(define_expand "udivmodhi4"
1299 ;; [(parallel
1300 ;; [(set (match_operand:HI 0 "nonimmediate_operand" "")
1301 ;; (udiv:HI (match_operand:HI 1 "general_operand" "")
1302 ;; (match_operand:HI 2 "general_operand" "")))
1303 ;; (set (match_operand:HI 3 "nonimmediate_operand" "")
1304 ;; (umod:HI (match_dup 1) (match_dup 2)))])]
1305 ;; ""
1306 ;; "
1307 ;;{
1308 ;; rtx temp = gen_reg_rtx(DImode);
1309 ;; rtx insn, first, last;
1310 ;; first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
1311 ;; emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
1312 ;; operands[2] = force_reg(HImode, operands[2]);
1313 ;; emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
1314 ;; last = emit_move_insn(temp, temp);
1315 ;; {
1316 ;; rtx divdi, moddi, divhi, modhi;
1317 ;; divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
1318 ;; modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
1319 ;; divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
1320 ;; moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
1321 ;; REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1322 ;; REG_NOTES (first));
1323 ;; REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1324 ;; gen_rtx (EXPR_LIST, REG_EQUAL,
1325 ;; gen_rtx(IOR, DImode, moddi,
1326 ;; gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
1327 ;; REG_NOTES (last)));
1328 ;; }
1329 ;;
1330 ;; insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
1331 ;; insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
1332 ;; DONE;
1333 ;;}")
1334 ;;
1335 ;;;; deiw wants two hi's in separate registers or else they can be adjacent
1336 ;;;; in memory. DI mode will ensure two registers are available, but if we
1337 ;;;; want to allow memory as an operand we would need SI mode. There is no
1338 ;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
1339 ;;(define_insn "udivmoddihi4_internal"
1340 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1341 ;; (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1342 ;; (match_operand:HI 2 "general_operand" "g")] 0))]
1343 ;; ""
1344 ;; "deiw %2,%0")
1345 ;;
1346 ;;(define_insn "udivmoddihi4"
1347 ;; [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 2)
1348 ;; (truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0")
1349 ;; (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm")))))
1350 ;; (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
1351 ;; (truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1352 ;; ""
1353 ;; "deiw %2,%0")
1354 ;;
1355 ;;(define_expand "udivmodqi4"
1356 ;; [(parallel
1357 ;; [(set (match_operand:QI 0 "nonimmediate_operand" "")
1358 ;; (udiv:QI (match_operand:QI 1 "general_operand" "")
1359 ;; (match_operand:QI 2 "general_operand" "")))
1360 ;; (set (match_operand:QI 3 "nonimmediate_operand" "")
1361 ;; (umod:QI (match_dup 1) (match_dup 2)))])]
1362 ;; ""
1363 ;; "
1364 ;;{
1365 ;; rtx temp = gen_reg_rtx(DImode);
1366 ;; rtx insn, first, last;
1367 ;; first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
1368 ;; emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
1369 ;; operands[2] = force_reg(QImode, operands[2]);
1370 ;; emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
1371 ;; last = emit_move_insn(temp, temp);
1372 ;; {
1373 ;; rtx divdi, moddi, divqi, modqi;
1374 ;; divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
1375 ;; modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
1376 ;; divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
1377 ;; moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
1378 ;; REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1379 ;; REG_NOTES (first));
1380 ;; REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1381 ;; gen_rtx (EXPR_LIST, REG_EQUAL,
1382 ;; gen_rtx(IOR, DImode, moddi,
1383 ;; gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
1384 ;; REG_NOTES (last)));
1385 ;; }
1386 ;;
1387 ;; insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
1388 ;; insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
1389 ;; DONE;
1390 ;;}")
1391 ;;
1392 ;;;; deib wants two qi's in separate registers or else they can be adjacent
1393 ;;;; in memory. DI mode will ensure two registers are available, but if we
1394 ;;;; want to allow memory as an operand we would need HI mode. There is no
1395 ;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
1396 ;;(define_insn "udivmoddiqi4_internal"
1397 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1398 ;; (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1399 ;; (match_operand:QI 2 "general_operand" "g")] 0))]
1400 ;; ""
1401 ;; "deib %2,%0")
1402 ;;
1403 ;;(define_insn "udivmoddiqi4"
1404 ;; [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
1405 ;; (truncate:QI (udiv:DI (match_operand:DI 1 "register_operand" "0")
1406 ;; (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "rm")))))
1407 ;; (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
1408 ;; (truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1409 ;; ""
1410 ;; "deib %2,%0")
1411 \f
1412 ;;- Divide instructions.
1414 (define_insn "divdf3"
1415 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
1416 (div:DF (match_operand:DF 1 "general_operand" "0")
1417 (match_operand:DF 2 "general_operand" "lmF")))]
1418 "TARGET_32081"
1419 "divl %2,%0")
1421 (define_insn "divsf3"
1422 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
1423 (div:SF (match_operand:SF 1 "general_operand" "0")
1424 (match_operand:SF 2 "general_operand" "fmF")))]
1425 "TARGET_32081"
1426 "divf %2,%0")
1428 ;; See note 1
1429 (define_insn "divsi3"
1430 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1431 (div:SI (match_operand:SI 1 "general_operand" "0")
1432 (match_operand:SI 2 "general_operand" "g")))]
1433 ""
1434 "quod %2,%0")
1436 (define_insn "divhi3"
1437 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1438 (div:HI (match_operand:HI 1 "general_operand" "0")
1439 (match_operand:HI 2 "general_operand" "g")))]
1440 ""
1441 "quow %2,%0")
1443 (define_insn "divqi3"
1444 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1445 (div:QI (match_operand:QI 1 "general_operand" "0")
1446 (match_operand:QI 2 "general_operand" "g")))]
1447 ""
1448 "quob %2,%0")
1449 \f
1450 ;; Remainder instructions.
1452 ;; See note 1
1453 (define_insn "modsi3"
1454 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1455 (mod:SI (match_operand:SI 1 "general_operand" "0")
1456 (match_operand:SI 2 "general_operand" "g")))]
1457 ""
1458 "remd %2,%0")
1460 (define_insn "modhi3"
1461 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1462 (mod:HI (match_operand:HI 1 "general_operand" "0")
1463 (match_operand:HI 2 "general_operand" "g")))]
1464 ""
1465 "remw %2,%0")
1467 (define_insn "modqi3"
1468 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1469 (mod:QI (match_operand:QI 1 "general_operand" "0")
1470 (match_operand:QI 2 "general_operand" "g")))]
1471 ""
1472 "remb %2,%0")
1474 \f
1475 ;;- Logical Instructions: AND
1477 ;; See note 1
1478 (define_insn "andsi3"
1479 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1480 (and:SI (match_operand:SI 1 "general_operand" "%0")
1481 (match_operand:SI 2 "general_operand" "g")))]
1482 ""
1483 "*
1484 {
1485 if (GET_CODE (operands[2]) == CONST_INT)
1486 {
1487 if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1488 {
1489 if (INTVAL (operands[2]) == 0xffffff00)
1490 return \"movqb %$0,%0\";
1491 else
1492 {
1493 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1494 return \"andb %2,%0\";
1495 }
1496 }
1497 if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1498 {
1499 if (INTVAL (operands[2]) == 0xffff0000)
1500 return \"movqw %$0,%0\";
1501 else
1502 {
1503 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
1504 return \"andw %2,%0\";
1505 }
1506 }
1507 }
1508 return \"andd %2,%0\";
1509 }")
1511 (define_insn "andhi3"
1512 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1513 (and:HI (match_operand:HI 1 "general_operand" "%0")
1514 (match_operand:HI 2 "general_operand" "g")))]
1515 ""
1516 "*
1517 {
1518 if (GET_CODE (operands[2]) == CONST_INT
1519 && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1520 {
1521 if (INTVAL (operands[2]) == 0xffffff00)
1522 return \"movqb %$0,%0\";
1523 else
1524 {
1525 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1526 return \"andb %2,%0\";
1527 }
1528 }
1529 return \"andw %2,%0\";
1530 }")
1532 (define_insn "andqi3"
1533 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1534 (and:QI (match_operand:QI 1 "general_operand" "%0")
1535 (match_operand:QI 2 "general_operand" "g")))]
1536 ""
1537 "andb %2,%0")
1539 ;; See note 1
1540 (define_insn "*bicsi"
1541 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1542 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
1543 (match_operand:SI 2 "general_operand" "0")))]
1544 ""
1545 "bicd %1,%0")
1547 (define_insn "*bichi"
1548 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1549 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1550 (match_operand:HI 2 "general_operand" "0")))]
1551 ""
1552 "bicw %1,%0")
1554 (define_insn "*bicqi"
1555 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1556 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1557 (match_operand:QI 2 "general_operand" "0")))]
1558 ""
1559 "bicb %1,%0")
1560 \f
1561 ;;- Bit set instructions.
1563 ;; See note 1
1564 (define_insn "iorsi3"
1565 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1566 (ior:SI (match_operand:SI 1 "general_operand" "%0")
1567 (match_operand:SI 2 "general_operand" "g")))]
1568 ""
1569 "*
1570 {
1571 if (GET_CODE (operands[2]) == CONST_INT) {
1572 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1573 return \"orb %2,%0\";
1574 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1575 return \"orw %2,%0\";
1576 }
1577 return \"ord %2,%0\";
1578 }")
1580 (define_insn "iorhi3"
1581 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1582 (ior:HI (match_operand:HI 1 "general_operand" "%0")
1583 (match_operand:HI 2 "general_operand" "g")))]
1584 ""
1585 "*
1586 {
1587 if (GET_CODE(operands[2]) == CONST_INT &&
1588 (INTVAL(operands[2]) & 0xffffff00) == 0)
1589 return \"orb %2,%0\";
1590 return \"orw %2,%0\";
1591 }")
1593 (define_insn "iorqi3"
1594 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1595 (ior:QI (match_operand:QI 1 "general_operand" "%0")
1596 (match_operand:QI 2 "general_operand" "g")))]
1597 ""
1598 "orb %2,%0")
1600 ;;- xor instructions.
1602 ;; See note 1
1603 (define_insn "xorsi3"
1604 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1605 (xor:SI (match_operand:SI 1 "general_operand" "%0")
1606 (match_operand:SI 2 "general_operand" "g")))]
1607 ""
1608 "*
1609 {
1610 if (GET_CODE (operands[2]) == CONST_INT) {
1611 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1612 return \"xorb %2,%0\";
1613 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1614 return \"xorw %2,%0\";
1615 }
1616 return \"xord %2,%0\";
1617 }")
1619 (define_insn "xorhi3"
1620 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1621 (xor:HI (match_operand:HI 1 "general_operand" "%0")
1622 (match_operand:HI 2 "general_operand" "g")))]
1623 ""
1624 "*
1625 {
1626 if (GET_CODE(operands[2]) == CONST_INT &&
1627 (INTVAL(operands[2]) & 0xffffff00) == 0)
1628 return \"xorb %2,%0\";
1629 return \"xorw %2,%0\";
1630 }")
1632 (define_insn "xorqi3"
1633 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1634 (xor:QI (match_operand:QI 1 "general_operand" "%0")
1635 (match_operand:QI 2 "general_operand" "g")))]
1636 ""
1637 "xorb %2,%0")
1638 \f
1639 (define_insn "negdf2"
1640 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
1641 (neg:DF (match_operand:DF 1 "general_operand" "lmF")))]
1642 "TARGET_32081"
1643 "negl %1,%0")
1645 (define_insn "negsf2"
1646 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
1647 (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1648 "TARGET_32081"
1649 "negf %1,%0")
1651 (define_insn "negdi2"
1652 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
1653 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "ro")))]
1654 ""
1655 "*
1656 {
1657 rtx low[2], high[2], xops[4];
1658 split_di (operands, 2, low, high);
1659 xops[0] = low[0];
1660 xops[1] = high[0];
1661 xops[2] = low[1];
1662 xops[3] = high[1];
1664 if (rtx_equal_p (operands[0], operands[1]))
1665 {
1666 output_asm_insn (\"negd %3,%1\", xops);
1667 output_asm_insn (\"negd %2,%0\", xops);
1668 output_asm_insn (\"subcd %$0,%1\", xops);
1669 }
1670 else
1671 {
1672 output_asm_insn (\"negd %2,%0\", xops);
1673 output_asm_insn (\"movqd %$0,%1\", xops);
1674 output_asm_insn (\"subcd %3,%1\", xops);
1675 }
1676 return \"\";
1677 }")
1679 ;; See note 1
1680 (define_insn "negsi2"
1681 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
1682 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1683 ""
1684 "negd %1,%0")
1686 (define_insn "neghi2"
1687 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
1688 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1689 ""
1690 "negw %1,%0")
1692 (define_insn "negqi2"
1693 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
1694 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1695 ""
1696 "negb %1,%0")
1697 \f
1698 ;; See note 1
1699 (define_insn "one_cmplsi2"
1700 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
1701 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1702 ""
1703 "comd %1,%0")
1705 (define_insn "one_cmplhi2"
1706 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
1707 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1708 ""
1709 "comw %1,%0")
1711 (define_insn "one_cmplqi2"
1712 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
1713 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1714 ""
1715 "comb %1,%0")
1716 \f
1717 ;; arithmetic left and right shift operations
1718 ;; on the 32532 we will always use lshd for arithmetic left shifts,
1719 ;; because it is three times faster. Broken programs which
1720 ;; use negative shift counts are probably broken differently
1721 ;; than elsewhere.
1723 ;; alternative 0 never matches on the 32532
1724 ;; See note 1
1725 (define_insn "ashlsi3"
1726 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
1727 (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1728 (match_operand:SI 2 "general_operand" "I,g")))]
1729 ""
1730 "*
1731 { if (TARGET_32532)
1732 return \"lshd %2,%0\";
1733 else
1734 return output_shift_insn (operands);
1735 }")
1737 (define_insn "ashlhi3"
1738 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1739 (ashift:HI (match_operand:HI 1 "general_operand" "0")
1740 (match_operand:SI 2 "general_operand" "g")))]
1741 ""
1742 "*
1743 { if (GET_CODE (operands[2]) == CONST_INT)
1744 {
1745 if (INTVAL (operands[2]) == 1)
1746 return \"addw %0,%0\";
1747 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1748 return \"addw %0,%0\;addw %0,%0\";
1749 }
1750 if (TARGET_32532)
1751 return \"lshw %2,%0\";
1752 else
1753 return \"ashw %2,%0\";
1754 }")
1756 (define_insn "ashlqi3"
1757 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1758 (ashift:QI (match_operand:QI 1 "general_operand" "0")
1759 (match_operand:SI 2 "general_operand" "g")))]
1760 ""
1761 "*
1762 { if (GET_CODE (operands[2]) == CONST_INT)
1763 {
1764 if (INTVAL (operands[2]) == 1)
1765 return \"addb %0,%0\";
1766 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1767 return \"addb %0,%0\;addb %0,%0\";
1768 }
1769 if (TARGET_32532)
1770 return \"lshb %2,%0\";
1771 else
1772 return \"ashb %2,%0\";
1773 }")
1775 ;; Arithmetic right shift on the 32k works by negating the shift count.
1776 (define_expand "ashrsi3"
1777 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1778 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1779 (match_operand:SI 2 "general_operand" "g")))]
1780 ""
1781 "
1782 {
1783 if (GET_CODE (operands[2]) != CONST_INT)
1784 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1785 }")
1787 (define_insn "*ashrisi3"
1788 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1789 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1790 (match_operand:SI 2 "immediate_operand" "i")))]
1791 ""
1792 "ashd %n2,%0")
1794 (define_insn "*ashrsi3"
1795 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1796 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1797 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1798 ""
1799 "ashd %2,%0")
1801 (define_expand "ashrhi3"
1802 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1803 (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1804 (match_operand:SI 2 "general_operand" "g")))]
1805 ""
1806 "
1807 {
1808 if (GET_CODE (operands[2]) != CONST_INT)
1809 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1810 }")
1812 (define_insn "*ashrihi3"
1813 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1814 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1815 (match_operand:SI 2 "immediate_operand" "i")))]
1816 ""
1817 "ashw %n2,%0")
1819 (define_insn "*ashrhi3"
1820 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1821 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1822 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1823 ""
1824 "ashw %2,%0")
1826 (define_expand "ashrqi3"
1827 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1828 (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1829 (match_operand:SI 2 "general_operand" "g")))]
1830 ""
1831 "
1832 {
1833 if (GET_CODE (operands[2]) != CONST_INT)
1834 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1835 }")
1837 (define_insn "*ashriqi3"
1838 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1839 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1840 (match_operand:SI 2 "immediate_operand" "i")))]
1841 ""
1842 "ashb %n2,%0")
1844 (define_insn "*ashrqi3"
1845 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1846 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1847 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1848 ""
1849 "ashb %2,%0")
1851 ;; logical shift instructions
1853 ;; Logical right shift on the 32k works by negating the shift count.
1854 (define_expand "lshrsi3"
1855 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1856 (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1857 (match_operand:SI 2 "general_operand" "g")))]
1858 ""
1859 "
1860 {
1861 if (GET_CODE (operands[2]) != CONST_INT)
1862 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1863 }")
1865 (define_insn "*lshrisi3"
1866 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1867 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1868 (match_operand:SI 2 "immediate_operand" "i")))]
1869 ""
1870 "lshd %n2,%0")
1872 (define_insn "*lshrsi3"
1873 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1874 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1875 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1876 ""
1877 "lshd %2,%0")
1879 (define_expand "lshrhi3"
1880 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1881 (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1882 (match_operand:SI 2 "general_operand" "g")))]
1883 ""
1884 "
1885 {
1886 if (GET_CODE (operands[2]) != CONST_INT)
1887 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1888 }")
1890 (define_insn "*lshrihi3"
1891 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1892 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1893 (match_operand:SI 2 "immediate_operand" "i")))]
1894 ""
1895 "lshw %n2,%0")
1897 (define_insn "*lshrhi3"
1898 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1899 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1900 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1901 ""
1902 "lshw %2,%0")
1904 (define_expand "lshrqi3"
1905 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1906 (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1907 (match_operand:SI 2 "general_operand" "g")))]
1908 ""
1909 "
1910 {
1911 if (GET_CODE (operands[2]) != CONST_INT)
1912 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1913 }")
1915 (define_insn "*lshriqi3"
1916 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1917 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1918 (match_operand:SI 2 "immediate_operand" "i")))]
1919 ""
1920 "lshb %n2,%0")
1922 (define_insn "*lshrqi3"
1923 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1924 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1925 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1926 ""
1927 "lshb %2,%0")
1929 ;; Rotate instructions
1931 ;; See note 1
1932 (define_insn "rotlsi3"
1933 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1934 (rotate:SI (match_operand:SI 1 "general_operand" "0")
1935 (match_operand:SI 2 "general_operand" "g")))]
1936 ""
1937 "rotd %2,%0")
1939 (define_insn "rotlhi3"
1940 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1941 (rotate:HI (match_operand:HI 1 "general_operand" "0")
1942 (match_operand:SI 2 "general_operand" "g")))]
1943 ""
1944 "rotw %2,%0")
1946 (define_insn "rotlqi3"
1947 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1948 (rotate:QI (match_operand:QI 1 "general_operand" "0")
1949 (match_operand:SI 2 "general_operand" "g")))]
1950 ""
1951 "rotb %2,%0")
1953 ;; Right rotate on the 32k works by negating the shift count.
1954 (define_expand "rotrsi3"
1955 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1956 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1957 (match_operand:SI 2 "general_operand" "g")))]
1958 ""
1959 "
1960 {
1961 if (GET_CODE (operands[2]) != CONST_INT)
1962 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1963 }")
1965 (define_insn "*rotrisi3"
1966 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1967 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1968 (match_operand:SI 2 "immediate_operand" "i")))]
1969 ""
1970 "rotd %n2,%0")
1972 (define_insn "*rotrsi3"
1973 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1974 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1975 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1976 ""
1977 "rotd %2,%0")
1979 (define_expand "rotrhi3"
1980 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1981 (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1982 (match_operand:SI 2 "general_operand" "g")))]
1983 ""
1984 "
1985 {
1986 if (GET_CODE (operands[2]) != CONST_INT)
1987 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1988 }")
1990 (define_insn "*rotrihi3"
1991 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1992 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1993 (match_operand:SI 2 "immediate_operand" "i")))]
1994 ""
1995 "rotw %n2,%0")
1997 (define_insn "*rotrhi3"
1998 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1999 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
2000 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
2001 ""
2002 "rotw %2,%0")
2004 (define_expand "rotrqi3"
2005 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2006 (rotatert:QI (match_operand:QI 1 "general_operand" "g")
2007 (match_operand:SI 2 "general_operand" "g")))]
2008 ""
2009 "
2010 {
2011 if (GET_CODE (operands[2]) != CONST_INT)
2012 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
2013 }")
2015 (define_insn "*rotriqi3"
2016 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2017 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2018 (match_operand:SI 2 "immediate_operand" "i")))]
2019 ""
2020 "rotb %n2,%0")
2022 (define_insn "*rotrqi3"
2023 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2024 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2025 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
2026 ""
2027 "rotb %2,%0")
2028 \f
2029 ;;- load or push effective address
2030 ;; These come after the move, add, and multiply patterns
2031 ;; because we don't want pushl $1 turned into pushad 1.
2033 (define_insn "*addrsi"
2034 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2035 (match_operand:QI 1 "address_operand" "p"))]
2036 ""
2037 "*
2038 {
2039 if (REG_P (operands[0])
2040 && GET_CODE (operands[1]) == MULT
2041 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
2042 && (INTVAL (XEXP (operands[1], 1)) == 2
2043 || INTVAL (XEXP (operands[1], 1)) == 4))
2044 {
2045 rtx xoperands[3];
2046 xoperands[0] = operands[0];
2047 xoperands[1] = XEXP (operands[1], 0);
2048 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
2049 return output_shift_insn (xoperands);
2050 }
2051 return \"addr %a1,%0\";
2052 }")
2053 \f
2054 ;;; Index insns. These are about the same speed as multiply-add counterparts.
2055 ;;; but slower than using power-of-2 shifts if we can use them
2056 ;
2057 ;;; See note 1
2058 ;(define_insn ""
2059 ; [(set (match_operand:SI 0 "register_operand" "=r")
2060 ; (plus:SI (match_operand:SI 1 "general_operand" "g")
2061 ; (mult:SI (match_operand:SI 2 "register_operand" "0")
2062 ; (plus:SI (match_operand:SI 3 "general_operand" "g") (const_int 1)))))]
2063 ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
2064 ; "indexd %0,%3,%1")
2065 ;
2066 ;(define_insn ""
2067 ; [(set (match_operand:SI 0 "register_operand" "=r")
2068 ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2069 ; (plus:SI (match_operand:SI 2 "general_operand" "g") (const_int 1)))
2070 ; (match_operand:SI 3 "general_operand" "g")))]
2071 ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
2072 ; "indexd %0,%2,%3")
2073 \f
2074 ;; Set, Clear, and Invert bit
2076 ;; See note 1
2077 (define_insn "*sbitsi"
2078 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
2079 (const_int 1)
2080 (match_operand:SI 1 "general_operand" "g"))
2081 (const_int 1))]
2082 ""
2083 "sbitd %1,%0")
2085 ;; See note 1
2086 (define_insn "*cbitsi"
2087 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
2088 (const_int 1)
2089 (match_operand:SI 1 "general_operand" "g"))
2090 (const_int 0))]
2091 ""
2092 "cbitd %1,%0")
2094 ;; See note 1
2095 (define_insn "*ibitsi"
2096 [(set (match_operand:SI 0 "nonimmediate_operand" "+rm")
2097 (xor:SI (ashift:SI (const_int 1)
2098 (match_operand:SI 1 "general_operand" "g"))
2099 (match_dup 0)))]
2100 ""
2101 "ibitd %1,%0")
2103 ;; See note 1
2104 (define_insn "*ibitqi"
2105 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2106 (xor:QI (subreg:QI
2107 (ashift:SI (const_int 1)
2108 (match_operand:QI 1 "general_operand" "g")) 0)
2109 (match_dup 0)))]
2110 ""
2111 "ibitb %1,%0")
2113 ;; Recognize jbs and jbc instructions.
2115 (define_insn "*tbit"
2116 [(set (cc0)
2117 (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
2118 (const_int 1)
2119 (match_operand:SI 1 "general_operand" "g")))]
2120 ""
2121 "*
2122 { cc_status.flags = CC_Z_IN_F;
2123 return \"tbitd %1,%0\";
2124 }")
2126 ;; extract(base, width, offset)
2127 ;; Signed bit-field extraction is not supported in hardware on the
2128 ;; NS 32032. It is therefore better to let GCC figure out a
2129 ;; good strategy for generating the proper instruction sequence
2130 ;; and represent it as rtl.
2132 ;; Optimize the case of extracting a byte or word from a register.
2133 ;; Otherwise we must load a register with the offset of the
2134 ;; chunk we want, and perform an extract insn (each of which
2135 ;; is very expensive). Since we use the stack to do our bit-twiddling
2136 ;; we cannot use it for a destination. Perhaps things are fast
2137 ;; enough on the 32532 that such hacks are not needed.
2139 (define_insn "*extract_bytes"
2140 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2141 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2142 (match_operand:SI 2 "const_int_operand" "i")
2143 (match_operand:SI 3 "const_int_operand" "i")))]
2144 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2145 && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
2146 "*
2147 {
2148 output_asm_insn (\"movd %1,tos\", operands);
2149 if (INTVAL (operands[2]) == 16)
2150 {
2151 if (INTVAL (operands[3]) == 8)
2152 output_asm_insn (\"movzwd 1(sp),%0\", operands);
2153 else
2154 output_asm_insn (\"movzwd 2(sp),%0\", operands);
2155 }
2156 else
2157 {
2158 if (INTVAL (operands[3]) == 8)
2159 output_asm_insn (\"movzbd 1(sp),%0\", operands);
2160 else if (INTVAL (operands[3]) == 16)
2161 output_asm_insn (\"movzbd 2(sp),%0\", operands);
2162 else
2163 output_asm_insn (\"movzbd 3(sp),%0\", operands);
2164 }
2165 if (TARGET_32532 || TARGET_32332)
2166 return \"cmpqd %$0,tos\";
2167 else
2168 return \"adjspb %$-4\";
2169 }")
2171 ;; The exts/ext instructions have the problem that they always access
2172 ;; 32 bits even if the bit-field is smaller. For example the instruction
2173 ;; extsd 7(r1),r0,2,5
2174 ;; would read not only at address 7(r1) but also at 8(r1) to 10(r1).
2175 ;; If these addresses are in a different (unmapped) page a memory fault
2176 ;; is the result.
2177 ;;
2178 ;; Timing considerations:
2179 ;; movd 0(r1),r0 3 bytes
2180 ;; lshd -26,r0 4
2181 ;; andd 0x1f,r0 5
2182 ;; takes about 13 cycles on the 532 while
2183 ;; extsd 7(r1),r0,2,5 5 bytes
2184 ;; takes about 21 cycles.
2185 ;;
2186 ;; The inss/ins instructions suffer from the same problem.
2187 ;;
2188 ;; A machine specific option (-mbitfield/-mnobitfield) is used
2189 ;; to allow/disallow the use of these instructions.
2191 (define_insn "*bitfield_ext"
2192 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2193 (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
2194 (match_operand:SI 2 "const_int_operand" "i")
2195 (match_operand:SI 3 "nonmemory_operand" "rK")))]
2196 "TARGET_BITFIELD"
2197 "*
2198 { if (GET_CODE (operands[3]) == CONST_INT)
2199 return \"extsd %1,%0,%3,%2\";
2200 else return \"extd %3,%1,%0,%2\";
2201 }")
2203 (define_insn "extzv"
2204 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2205 (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
2206 (match_operand:SI 2 "const_int_operand" "i")
2207 (match_operand:SI 3 "nonmemory_operand" "rK")))]
2208 "TARGET_BITFIELD"
2209 "*
2210 { if (GET_CODE (operands[3]) == CONST_INT)
2211 return \"extsd %1,%0,%3,%2\";
2212 else return \"extd %3,%1,%0,%2\";
2213 }")
2215 (define_insn "*bitfield_set"
2216 [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o,+r")
2217 (match_operand:SI 1 "const_int_operand" "i,i")
2218 (match_operand:SI 2 "nonmemory_operand" "rn,rK"))
2219 (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))]
2220 "TARGET_BITFIELD"
2221 "*
2222 { if (GET_CODE (operands[2]) == CONST_INT)
2223 {
2224 if (which_alternative == 0 && INTVAL (operands[2]) >= 8)
2225 {
2226 operands[0] = adjust_address (operands[0], QImode,
2227 INTVAL (operands[2]) / 8);
2228 operands[2] = GEN_INT (INTVAL (operands[2]) % 8);
2229 }
2230 if (INTVAL (operands[1]) <= 8)
2231 return \"inssb %3,%0,%2,%1\";
2232 else if (INTVAL (operands[1]) <= 16)
2233 return \"inssw %3,%0,%2,%1\";
2234 else
2235 return \"inssd %3,%0,%2,%1\";
2236 }
2237 return \"insd %2,%3,%0,%1\";
2238 }")
2241 (define_insn "insv"
2242 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+rm")
2243 (match_operand:SI 1 "const_int_operand" "i")
2244 (match_operand:SI 2 "nonmemory_operand" "rK"))
2245 (match_operand:SI 3 "nonimmediate_operand" "rm"))]
2246 "TARGET_BITFIELD"
2247 "*
2248 { if (GET_CODE (operands[2]) == CONST_INT)
2249 {
2250 if (INTVAL (operands[1]) <= 8)
2251 return \"inssb %3,%0,%2,%1\";
2252 else if (INTVAL (operands[1]) <= 16)
2253 return \"inssw %3,%0,%2,%1\";
2254 else
2255 return \"inssd %3,%0,%2,%1\";
2256 }
2257 return \"insd %2,%3,%0,%1\";
2258 }")
2260 \f
2261 (define_insn "jump"
2262 [(set (pc)
2263 (label_ref (match_operand 0 "" "")))]
2264 ""
2265 "br %l0")
2267 (define_insn "beq"
2268 [(set (pc)
2269 (if_then_else (eq (cc0)
2270 (const_int 0))
2271 (label_ref (match_operand 0 "" ""))
2272 (pc)))]
2273 ""
2274 "*
2275 { if (cc_prev_status.flags & CC_Z_IN_F)
2276 return \"bfc %l0\";
2277 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2278 return \"bfs %l0\";
2279 else return \"beq %l0\";
2280 }")
2282 (define_insn "bne"
2283 [(set (pc)
2284 (if_then_else (ne (cc0)
2285 (const_int 0))
2286 (label_ref (match_operand 0 "" ""))
2287 (pc)))]
2288 ""
2289 "*
2290 { if (cc_prev_status.flags & CC_Z_IN_F)
2291 return \"bfs %l0\";
2292 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2293 return \"bfc %l0\";
2294 else return \"bne %l0\";
2295 }")
2297 (define_insn "bgt"
2298 [(set (pc)
2299 (if_then_else (gt (cc0)
2300 (const_int 0))
2301 (label_ref (match_operand 0 "" ""))
2302 (pc)))]
2303 ""
2304 "bgt %l0")
2306 (define_insn "bgtu"
2307 [(set (pc)
2308 (if_then_else (gtu (cc0)
2309 (const_int 0))
2310 (label_ref (match_operand 0 "" ""))
2311 (pc)))]
2312 ""
2313 "bhi %l0")
2315 (define_insn "blt"
2316 [(set (pc)
2317 (if_then_else (lt (cc0)
2318 (const_int 0))
2319 (label_ref (match_operand 0 "" ""))
2320 (pc)))]
2321 ""
2322 "*
2323 {
2324 if (cc_prev_status.flags & CC_UNORD)
2325 return \"bhi 0f\;blt %l0\;0:\";
2326 else
2327 return \"blt %l0\";
2328 }")
2330 (define_insn "bltu"
2331 [(set (pc)
2332 (if_then_else (ltu (cc0)
2333 (const_int 0))
2334 (label_ref (match_operand 0 "" ""))
2335 (pc)))]
2336 ""
2337 "blo %l0")
2339 (define_insn "bge"
2340 [(set (pc)
2341 (if_then_else (ge (cc0)
2342 (const_int 0))
2343 (label_ref (match_operand 0 "" ""))
2344 (pc)))]
2345 ""
2346 "bge %l0")
2348 (define_insn "bgeu"
2349 [(set (pc)
2350 (if_then_else (geu (cc0)
2351 (const_int 0))
2352 (label_ref (match_operand 0 "" ""))
2353 (pc)))]
2354 ""
2355 "bhs %l0")
2357 (define_insn "ble"
2358 [(set (pc)
2359 (if_then_else (le (cc0)
2360 (const_int 0))
2361 (label_ref (match_operand 0 "" ""))
2362 (pc)))]
2363 ""
2364 "*
2365 {
2366 if (cc_prev_status.flags & CC_UNORD)
2367 return \"bhi 0f\;ble %l0\;0:\";
2368 else
2369 return \"ble %l0\";
2370 }")
2372 (define_insn "bleu"
2373 [(set (pc)
2374 (if_then_else (leu (cc0)
2375 (const_int 0))
2376 (label_ref (match_operand 0 "" ""))
2377 (pc)))]
2378 ""
2379 "bls %l0")
2380 \f
2381 ;; "Reversed" jump instructions.
2383 (define_insn "*rbeq"
2384 [(set (pc)
2385 (if_then_else (eq (cc0)
2386 (const_int 0))
2387 (pc)
2388 (label_ref (match_operand 0 "" ""))))]
2389 ""
2390 "*
2391 { if (cc_prev_status.flags & CC_Z_IN_F)
2392 return \"bfs %l0\";
2393 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2394 return \"bfc %l0\";
2395 else
2396 return \"bne %l0\";
2397 }")
2399 (define_insn "*rbne"
2400 [(set (pc)
2401 (if_then_else (ne (cc0)
2402 (const_int 0))
2403 (pc)
2404 (label_ref (match_operand 0 "" ""))))]
2405 ""
2406 "*
2407 { if (cc_prev_status.flags & CC_Z_IN_F)
2408 return \"bfc %l0\";
2409 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2410 return \"bfs %l0\";
2411 else return \"beq %l0\";
2412 }")
2414 (define_insn "*rbgt"
2415 [(set (pc)
2416 (if_then_else (gt (cc0)
2417 (const_int 0))
2418 (pc)
2419 (label_ref (match_operand 0 "" ""))))]
2420 ""
2421 "*
2422 {
2423 if (cc_prev_status.flags & CC_UNORD)
2424 return \"ble %l0\;bhi %l0\";
2425 else
2426 return \"ble %l0\";
2427 }")
2429 (define_insn "*rbgtu"
2430 [(set (pc)
2431 (if_then_else (gtu (cc0)
2432 (const_int 0))
2433 (pc)
2434 (label_ref (match_operand 0 "" ""))))]
2435 ""
2436 "bls %l0")
2438 (define_insn "*rblt"
2439 [(set (pc)
2440 (if_then_else (lt (cc0)
2441 (const_int 0))
2442 (pc)
2443 (label_ref (match_operand 0 "" ""))))]
2444 ""
2445 "*
2446 {
2447 if (cc_prev_status.flags & CC_UNORD)
2448 return \"bge %l0\;bhi %l0\";
2449 else
2450 return \"bge %l0\";
2451 }")
2453 (define_insn "*rbltu"
2454 [(set (pc)
2455 (if_then_else (ltu (cc0)
2456 (const_int 0))
2457 (pc)
2458 (label_ref (match_operand 0 "" ""))))]
2459 ""
2460 "bhs %l0")
2462 (define_insn "*rbge"
2463 [(set (pc)
2464 (if_then_else (ge (cc0)
2465 (const_int 0))
2466 (pc)
2467 (label_ref (match_operand 0 "" ""))))]
2468 ""
2469 "*
2470 {
2471 if (cc_prev_status.flags & CC_UNORD)
2472 return \"blt %l0\;bhi %l0\";
2473 else
2474 return \"blt %l0\";
2475 }")
2477 (define_insn "*rbgeu"
2478 [(set (pc)
2479 (if_then_else (geu (cc0)
2480 (const_int 0))
2481 (pc)
2482 (label_ref (match_operand 0 "" ""))))]
2483 ""
2484 "blo %l0")
2486 (define_insn "*rble"
2487 [(set (pc)
2488 (if_then_else (le (cc0)
2489 (const_int 0))
2490 (pc)
2491 (label_ref (match_operand 0 "" ""))))]
2492 ""
2493 "*
2494 {
2495 if (cc_prev_status.flags & CC_UNORD)
2496 return \"bgt %l0\;bhi %l0\";
2497 else
2498 return \"bgt %l0\";
2499 }")
2501 (define_insn "*rbleu"
2502 [(set (pc)
2503 (if_then_else (leu (cc0)
2504 (const_int 0))
2505 (pc)
2506 (label_ref (match_operand 0 "" ""))))]
2507 ""
2508 "bhi %l0")
2509 \f
2510 ;; Subtract-and-jump and Add-and-jump insns.
2511 ;; These can actually be used for adding numbers in the range -8 to 7
2513 (define_insn "*sub_br"
2514 [(set (pc)
2515 (if_then_else
2516 (ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
2517 (match_operand:SI 1 "const_int_operand" "i"))
2518 (label_ref (match_operand 2 "" ""))
2519 (pc)))
2520 (set (match_dup 0)
2521 (minus:SI (match_dup 0)
2522 (match_dup 1)))]
2523 "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2524 "acbd %n1,%0,%l2")
2526 (define_insn "*add_br"
2527 [(set (pc)
2528 (if_then_else
2529 (ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
2530 (match_operand:SI 1 "const_int_operand" "i"))
2531 (label_ref (match_operand 2 "" ""))
2532 (pc)))
2533 (set (match_dup 0)
2534 (plus:SI (match_dup 0)
2535 (match_operand:SI 3 "const_int_operand" "i")))]
2536 "INTVAL (operands[1]) == - INTVAL (operands[3])
2537 && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2538 "acbd %3,%0,%l2")
2539 \f
2540 (define_insn "call"
2541 [(call (match_operand:QI 0 "memory_operand" "m")
2542 (match_operand 1 "" ""))]
2543 ;; Operand 1 is not used
2544 ""
2545 "*
2546 {
2547 #ifndef JSR_ALWAYS
2548 if (GET_CODE (operands[0]) == MEM)
2549 {
2550 rtx temp = XEXP (operands[0], 0);
2551 if (CONSTANT_ADDRESS_P (temp))
2552 {
2553 #ifdef ENCORE_ASM
2554 return \"bsr %?%0\";
2555 #else
2556 #ifdef CALL_MEMREF_IMPLICIT
2557 operands[0] = temp;
2558 return \"bsr %0\";
2559 #else
2560 #ifdef GNX_V3
2561 return \"bsr %0\";
2562 #else
2563 return \"bsr %?%a0\";
2564 #endif
2565 #endif
2566 #endif
2567 }
2568 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2569 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2570 return \"jsr %0\";
2571 #else
2572 return \"jsr %a0\";
2573 #endif
2574 }
2575 #endif /* not JSR_ALWAYS */
2576 return \"jsr %0\";
2577 }")
2579 (define_insn "call_value"
2580 [(set (match_operand 0 "" "=rf")
2581 (call (match_operand:QI 1 "memory_operand" "m")
2582 (match_operand 2 "" "")))]
2583 ;; Operand 2 is not used
2584 ""
2585 "*
2586 {
2587 #ifndef JSR_ALWAYS
2588 if (GET_CODE (operands[1]) == MEM)
2589 {
2590 rtx temp = XEXP (operands[1], 0);
2591 if (CONSTANT_ADDRESS_P (temp))
2592 {
2593 #ifdef ENCORE_ASM
2594 return \"bsr %?%1\";
2595 #else
2596 #ifdef CALL_MEMREF_IMPLICIT
2597 operands[1] = temp;
2598 return \"bsr %1\";
2599 #else
2600 #ifdef GNX_V3
2601 return \"bsr %1\";
2602 #else
2603 return \"bsr %?%a1\";
2604 #endif
2605 #endif
2606 #endif
2607 }
2608 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2609 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2610 return \"jsr %1\";
2611 #else
2612 return \"jsr %a1\";
2613 #endif
2614 }
2615 #endif /* not JSR_ALWAYS */
2616 return \"jsr %1\";
2617 }")
2619 ;; Call subroutine returning any type.
2621 (define_expand "untyped_call"
2622 [(parallel [(call (match_operand 0 "" "")
2623 (const_int 0))
2624 (match_operand 1 "" "")
2625 (match_operand 2 "" "")])]
2626 ""
2627 "
2628 {
2629 int i;
2631 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2633 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2634 {
2635 rtx set = XVECEXP (operands[2], 0, i);
2636 emit_move_insn (SET_DEST (set), SET_SRC (set));
2637 }
2639 /* The optimizer does not know that the call sets the function value
2640 registers we stored in the result block. We avoid problems by
2641 claiming that all hard registers are used and clobbered at this
2642 point. */
2643 emit_insn (gen_blockage ());
2645 DONE;
2646 }")
2648 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2649 ;; all of memory. This blocks insns from being moved across this point.
2651 (define_insn "blockage"
2652 [(unspec_volatile [(const_int 0)] 0)]
2653 ""
2654 "")
2656 (define_insn "return"
2657 [(return)]
2658 "0"
2659 "ret 0")
2661 (define_insn "abssf2"
2662 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
2663 (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2664 "TARGET_32081"
2665 "absf %1,%0")
2667 (define_insn "absdf2"
2668 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
2669 (abs:DF (match_operand:DF 1 "general_operand" "lmF")))]
2670 "TARGET_32081"
2671 "absl %1,%0")
2673 ;; See note 1
2674 (define_insn "abssi2"
2675 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2676 (abs:SI (match_operand:SI 1 "general_operand" "g")))]
2677 ""
2678 "absd %1,%0")
2680 (define_insn "abshi2"
2681 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
2682 (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2683 ""
2684 "absw %1,%0")
2686 (define_insn "absqi2"
2687 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
2688 (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2689 ""
2690 "absb %1,%0")
2692 (define_insn "nop"
2693 [(const_int 0)]
2694 ""
2695 "nop")
2697 (define_insn "indirect_jump"
2698 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2699 ""
2700 "jump %0")
2701 \f
2702 (define_insn "tablejump"
2703 [(set (pc)
2704 (plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
2705 (use (label_ref (match_operand 1 "" "")))]
2706 ""
2707 "*
2708 {
2709 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
2710 CODE_LABEL_NUMBER (operands[1]));
2711 return \"cased %0\";
2712 }")
2714 ;; Scondi instructions
2715 (define_insn "seq"
2716 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2717 (eq:SI (cc0) (const_int 0)))]
2718 ""
2719 "*
2720 { if (cc_prev_status.flags & CC_Z_IN_F)
2721 return \"sfcd %0\";
2722 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2723 return \"sfsd %0\";
2724 else return \"seqd %0\";
2725 }")
2727 (define_insn "*seqhi"
2728 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2729 (eq:HI (cc0) (const_int 0)))]
2730 ""
2731 "*
2732 { if (cc_prev_status.flags & CC_Z_IN_F)
2733 return \"sfcw %0\";
2734 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2735 return \"sfsw %0\";
2736 else return \"seqw %0\";
2737 }")
2739 (define_insn "*seqqi"
2740 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2741 (eq:QI (cc0) (const_int 0)))]
2742 ""
2743 "*
2744 { if (cc_prev_status.flags & CC_Z_IN_F)
2745 return \"sfcb %0\";
2746 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2747 return \"sfsb %0\";
2748 else return \"seqb %0\";
2749 }")
2751 (define_insn "sne"
2752 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2753 (ne:SI (cc0) (const_int 0)))]
2754 ""
2755 "*
2756 { if (cc_prev_status.flags & CC_Z_IN_F)
2757 return \"sfsd %0\";
2758 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2759 return \"sfcd %0\";
2760 else return \"sned %0\";
2761 }")
2763 (define_insn "*snehi"
2764 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2765 (ne:HI (cc0) (const_int 0)))]
2766 ""
2767 "*
2768 { if (cc_prev_status.flags & CC_Z_IN_F)
2769 return \"sfsw %0\";
2770 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2771 return \"sfcw %0\";
2772 else return \"snew %0\";
2773 }")
2775 (define_insn "*sneqi"
2776 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2777 (ne:QI (cc0) (const_int 0)))]
2778 ""
2779 "*
2780 { if (cc_prev_status.flags & CC_Z_IN_F)
2781 return \"sfsb %0\";
2782 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2783 return \"sfcb %0\";
2784 else return \"sneb %0\";
2785 }")
2787 (define_insn "sgt"
2788 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2789 (gt:SI (cc0) (const_int 0)))]
2790 ""
2791 "sgtd %0")
2793 (define_insn "*sgthi"
2794 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2795 (gt:HI (cc0) (const_int 0)))]
2796 ""
2797 "sgtw %0")
2799 (define_insn "*sgtqi"
2800 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2801 (gt:QI (cc0) (const_int 0)))]
2802 ""
2803 "sgtb %0")
2805 (define_insn "sgtu"
2806 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2807 (gtu:SI (cc0) (const_int 0)))]
2808 ""
2809 "shid %0")
2811 (define_insn "*sgtuhi"
2812 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2813 (gtu:HI (cc0) (const_int 0)))]
2814 ""
2815 "shiw %0")
2817 (define_insn "*sgtuqi"
2818 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2819 (gtu:QI (cc0) (const_int 0)))]
2820 ""
2821 "shib %0")
2823 (define_insn "slt"
2824 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2825 (lt:SI (cc0) (const_int 0)))]
2826 ""
2827 "sltd %0")
2829 (define_insn "*slthi"
2830 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2831 (lt:HI (cc0) (const_int 0)))]
2832 ""
2833 "sltw %0")
2835 (define_insn "*sltqi"
2836 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2837 (lt:QI (cc0) (const_int 0)))]
2838 ""
2839 "sltb %0")
2841 (define_insn "sltu"
2842 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2843 (ltu:SI (cc0) (const_int 0)))]
2844 ""
2845 "slod %0")
2847 (define_insn "*sltuhi"
2848 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2849 (ltu:HI (cc0) (const_int 0)))]
2850 ""
2851 "slow %0")
2853 (define_insn "*sltuqi"
2854 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2855 (ltu:QI (cc0) (const_int 0)))]
2856 ""
2857 "slob %0")
2859 (define_insn "sge"
2860 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2861 (ge:SI (cc0) (const_int 0)))]
2862 ""
2863 "sged %0")
2865 (define_insn "*sgehi"
2866 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2867 (ge:HI (cc0) (const_int 0)))]
2868 ""
2869 "sgew %0")
2871 (define_insn "*sgeqi"
2872 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2873 (ge:QI (cc0) (const_int 0)))]
2874 ""
2875 "sgeb %0")
2877 (define_insn "sgeu"
2878 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2879 (geu:SI (cc0) (const_int 0)))]
2880 ""
2881 "shsd %0")
2883 (define_insn "*sgeuhi"
2884 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2885 (geu:HI (cc0) (const_int 0)))]
2886 ""
2887 "shsw %0")
2889 (define_insn "*sgeuqi"
2890 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2891 (geu:QI (cc0) (const_int 0)))]
2892 ""
2893 "shsb %0")
2895 (define_insn "sle"
2896 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2897 (le:SI (cc0) (const_int 0)))]
2898 ""
2899 "sled %0")
2901 (define_insn "*slehi"
2902 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2903 (le:HI (cc0) (const_int 0)))]
2904 ""
2905 "slew %0")
2907 (define_insn "*sleqi"
2908 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2909 (le:QI (cc0) (const_int 0)))]
2910 ""
2911 "sleb %0")
2913 (define_insn "sleu"
2914 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2915 (leu:SI (cc0) (const_int 0)))]
2916 ""
2917 "slsd %0")
2919 (define_insn "*sleuhi"
2920 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2921 (leu:HI (cc0) (const_int 0)))]
2922 ""
2923 "slsw %0")
2925 (define_insn "*sleuqi"
2926 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2927 (leu:QI (cc0) (const_int 0)))]
2928 ""
2929 "slsb %0")
2930 \f
2931 ;; ffs instructions
2933 (define_insn "*ffs"
2934 [(set (match_operand:SI 0 "nonimmediate_operand" "+ro")
2935 (minus:SI
2936 (plus:SI (ffs:SI (zero_extract:SI
2937 (match_operand:SI 1 "general_operand" "g")
2938 (minus:SI (const_int 32) (match_dup 0))
2939 (match_dup 0)))
2940 (match_dup 0))
2941 (const_int 1)))]
2942 ""
2943 "ffsd %1,%0\;bfc 1f\;addqd %$-1,%0\;1:")
2945 (define_expand "ffssi2"
2946 [(set (match_operand:SI 0 "nonimmediate_operand" "") (const_int 0))
2947 (set (match_dup 0)
2948 (minus:SI
2949 (plus:SI (ffs:SI (zero_extract:SI
2950 (match_operand:SI 1 "general_operand" "g")
2951 (minus:SI (const_int 32) (match_dup 0))
2952 (match_dup 0)))
2953 (match_dup 0))
2954 (const_int 1)))
2955 (set (match_dup 0)
2956 (plus:SI (match_dup 0)
2957 (const_int 1)))]
2958 ""
2959 "operands[1] = make_safe_from(operands[1], operands[0]);")
2960 \f
2961 ;; Speed up stack adjust followed by a HI fixedpoint push.
2963 (define_peephole
2964 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2965 (set (match_operand:HI 0 "push_operand" "=m")
2966 (match_operand:HI 1 "general_operand" "g"))]
2967 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2968 "*
2969 {
2970 if (GET_CODE (operands[1]) == CONST_INT)
2971 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2972 operands);
2973 else
2974 output_asm_insn (\"movzwd %1,tos\", operands);
2975 return \"\";
2976 }")
2978 ;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push.
2980 (define_peephole
2981 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2982 (set (match_operand:HI 0 "push_operand" "=m")
2983 (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2984 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2985 "*
2986 {
2987 if (GET_CODE (operands[1]) == CONST_INT)
2988 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2989 operands);
2990 else
2991 output_asm_insn (\"movzbd %1,tos\", operands);
2992 return \"\";
2993 }")
2995 ;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push.
2997 (define_peephole
2998 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2999 (set (match_operand:HI 0 "push_operand" "=m")
3000 (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
3001 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
3002 "*
3003 {
3004 if (GET_CODE (operands[1]) == CONST_INT)
3005 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
3006 operands);
3007 else
3008 output_asm_insn (\"movxbd %1,tos\", operands);
3009 return \"\";
3010 }")
3012 ;; Speed up stack adjust followed by a QI fixedpoint push.
3014 (define_peephole
3015 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -3)))
3016 (set (match_operand:QI 0 "push_operand" "=m")
3017 (match_operand:QI 1 "general_operand" "g"))]
3018 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
3019 "*
3020 {
3021 if (GET_CODE (operands[1]) == CONST_INT)
3022 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
3023 operands);
3024 else
3025 output_asm_insn (\"movzbd %1,tos\", operands);
3026 return \"\";
3027 }")
3029 ;; Speed up stack adjust followed by a SI fixedpoint push.
3031 (define_peephole
3032 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 4)))
3033 (set (match_operand:SI 0 "push_operand" "=m")
3034 (match_operand:SI 1 "general_operand" "g"))]
3035 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
3036 "*
3037 {
3038 if (GET_CODE (operands[1]) == CONST_INT)
3039 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,0(sp)\"),
3040 operands);
3041 else if (GET_CODE (operands[1]) != REG
3042 && GET_CODE (operands[1]) != MEM
3043 && address_operand (operands[1], SImode))
3044 output_asm_insn (\"addr %a1,0(sp)\", operands);
3045 else
3046 output_asm_insn (\"movd %1,0(sp)\", operands);
3047 return \"\";
3048 }")
3050 ;; Speed up stack adjust followed by two fullword fixedpoint pushes.
3052 (define_peephole
3053 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 8)))
3054 (set (match_operand:SI 0 "push_operand" "=m")
3055 (match_operand:SI 1 "general_operand" "g"))
3056 (set (match_operand:SI 2 "push_operand" "=m")
3057 (match_operand:SI 3 "general_operand" "g"))]
3058 "! reg_mentioned_p (stack_pointer_rtx, operands[1])
3059 && ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
3060 "*
3061 {
3062 if (GET_CODE (operands[1]) == CONST_INT)
3063 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,4(sp)\"),
3064 operands);
3065 else if (GET_CODE (operands[1]) != REG
3066 && GET_CODE (operands[1]) != MEM
3067 && address_operand (operands[1], SImode))
3068 output_asm_insn (\"addr %a1,4(sp)\", operands);
3069 else
3070 output_asm_insn (\"movd %1,4(sp)\", operands);
3072 if (GET_CODE (operands[3]) == CONST_INT)
3073 output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%3,0(sp)\"),
3074 operands);
3075 else if (GET_CODE (operands[3]) != REG
3076 && GET_CODE (operands[3]) != MEM
3077 && address_operand (operands[3], SImode))
3078 output_asm_insn (\"addr %a3,0(sp)\", operands);
3079 else
3080 output_asm_insn (\"movd %3,0(sp)\", operands);
3081 return \"\";
3082 }")