1 ;; GCC machine description for MMIX
2 ;; Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hans-Peter Nilsson (hp@bitrange.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et al.
27 ;; Uses of UNSPEC in this file:
30 ;; 0 sync_icache (sync icache before trampoline jump)
31 ;; 1 nonlocal_goto_receiver
34 ;; The order of insns is as in Node: Standard Names, with smaller modes
35 ;; before bigger modes.
40 (MMIX_fp_rO_OFFSET -24)]
43 ;; FIXME: Can we remove the reg-to-reg for smaller modes? Shouldn't they
46 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r ,r,x ,r,r,m,??r")
47 (match_operand:QI 1 "general_operand" "r,LS,K,rI,x,m,r,n"))]
60 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,x,r,r,m,??r")
61 (match_operand:HI 1 "general_operand" "r,LS,K,r,x,m,r,n"))]
73 ;; gcc.c-torture/compile/920428-2.c fails if there's no "n".
75 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r ,r,x,r,r,m,??r")
76 (match_operand:SI 1 "general_operand" "r,LS,K,r,x,m,r,n"))]
88 ;; We assume all "s" are addresses. Does that hold?
90 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r ,r,x,r,m,r,m,r,r,??r")
91 (match_operand:DI 1 "general_operand" "r,LS,K,r,x,I,m,r,R,s,n"))]
106 ;; Note that we move around the float as a collection of bits; no
107 ;; conversion to double.
109 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,x,r,r,m,??r")
110 (match_operand:SF 1 "general_operand" "r,G,r,x,m,r,F"))]
122 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,x,r,r,m,??r")
123 (match_operand:DF 1 "general_operand" "r,G,r,x,m,r,F"))]
134 (define_insn "adddi3"
135 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
137 (match_operand:DI 1 "register_operand" "%r,r,0")
138 (match_operand:DI 2 "mmix_reg_or_constant_operand" "rI,K,LS")))]
145 (define_insn "adddf3"
146 [(set (match_operand:DF 0 "register_operand" "=r")
147 (plus:DF (match_operand:DF 1 "register_operand" "%r")
148 (match_operand:DF 2 "register_operand" "r")))]
152 ;; Insn canonicalization *should* have removed the need for an integer
154 (define_insn "subdi3"
155 [(set (match_operand:DI 0 "register_operand" "=r,r")
156 (minus:DI (match_operand:DI 1 "mmix_reg_or_8bit_operand" "r,I")
157 (match_operand:DI 2 "register_operand" "r,r")))]
163 (define_insn "subdf3"
164 [(set (match_operand:DF 0 "register_operand" "=r")
165 (minus:DF (match_operand:DF 1 "register_operand" "r")
166 (match_operand:DF 2 "register_operand" "r")))]
170 ;; FIXME: Should we define_expand and match 2, 4, 8 (etc) with shift (or
171 ;; %{something}2ADDU %0,%1,0)? Hopefully GCC should still handle it, so
172 ;; we don't have to taint the machine description. If results are bad
173 ;; enough, we may have to do it anyway.
174 (define_insn "muldi3"
175 [(set (match_operand:DI 0 "register_operand" "=r,r")
176 (mult:DI (match_operand:DI 1 "register_operand" "%r,r")
177 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "O,rI")))
178 (clobber (match_scratch:DI 3 "=X,z"))]
184 (define_insn "muldf3"
185 [(set (match_operand:DF 0 "register_operand" "=r")
186 (mult:DF (match_operand:DF 1 "register_operand" "r")
187 (match_operand:DF 2 "register_operand" "r")))]
191 (define_insn "divdf3"
192 [(set (match_operand:DF 0 "register_operand" "=r")
193 (div:DF (match_operand:DF 1 "register_operand" "r")
194 (match_operand:DF 2 "register_operand" "r")))]
198 ;; FIXME: Is "frem" doing the right operation for moddf3?
199 (define_insn "moddf3"
200 [(set (match_operand:DF 0 "register_operand" "=r")
201 (mod:DF (match_operand:DF 1 "register_operand" "r")
202 (match_operand:DF 2 "register_operand" "r")))]
206 ;; FIXME: Should we define_expand for smin, smax, umin, umax using a
207 ;; nifty conditional sequence?
209 ;; FIXME: The cuter andn combinations don't get here, presumably because
210 ;; they ended up in the constant pool. Check: still?
211 (define_insn "anddi3"
212 [(set (match_operand:DI 0 "register_operand" "=r,r")
214 (match_operand:DI 1 "register_operand" "%r,0")
215 (match_operand:DI 2 "mmix_reg_or_constant_operand" "rI,NT")))]
221 (define_insn "iordi3"
222 [(set (match_operand:DI 0 "register_operand" "=r,r")
223 (ior:DI (match_operand:DI 1 "register_operand" "%r,0")
224 (match_operand:DI 2 "mmix_reg_or_constant_operand" "rH,LS")))]
230 (define_insn "xordi3"
231 [(set (match_operand:DI 0 "register_operand" "=r")
232 (xor:DI (match_operand:DI 1 "register_operand" "%r")
233 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
237 ;; FIXME: When TImode works for other reasons (like cross-compiling from
238 ;; a 32-bit host), add back umulditi3 and umuldi3_highpart here.
240 ;; FIXME: Check what's really reasonable for the mod part.
242 ;; One day we might persuade GCC to expand divisions with constants the
243 ;; way MMIX does; giving the remainder the sign of the divisor. But even
244 ;; then, it might be good to have an option to divide the way "everybody
245 ;; else" does. Perhaps then, this option can be on by default. However,
246 ;; it's not likely to happen because major (C, C++, Fortran) language
247 ;; standards in effect at 2002-04-29 reportedly demand that the sign of
248 ;; the remainder must follow the sign of the dividend.
250 (define_insn "divmoddi4"
251 [(set (match_operand:DI 0 "register_operand" "=r")
252 (div:DI (match_operand:DI 1 "register_operand" "r")
253 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))
254 (set (match_operand:DI 3 "register_operand" "=y")
255 (mod:DI (match_dup 1) (match_dup 2)))]
256 ;; Do the library stuff later.
257 "TARGET_KNUTH_DIVISION"
260 (define_insn "udivmoddi4"
261 [(set (match_operand:DI 0 "register_operand" "=r")
262 (udiv:DI (match_operand:DI 1 "register_operand" "r")
263 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))
264 (set (match_operand:DI 3 "register_operand" "=y")
265 (umod:DI (match_dup 1) (match_dup 2)))]
269 (define_expand "divdi3"
271 [(set (match_operand:DI 0 "register_operand" "=&r")
272 (div:DI (match_operand:DI 1 "register_operand" "r")
273 (match_operand:DI 2 "register_operand" "r")))
274 (clobber (scratch:DI))
275 (clobber (scratch:DI))
276 (clobber (reg:DI MMIX_rR_REGNUM))])]
277 "! TARGET_KNUTH_DIVISION"
280 ;; The %2-is-%1-case is there just to make sure things don't fail. Could
281 ;; presumably happen with optimizations off; no evidence.
282 (define_insn "*divdi3_nonknuth"
283 [(set (match_operand:DI 0 "register_operand" "=&r,r")
284 (div:DI (match_operand:DI 1 "register_operand" "r,r")
285 (match_operand:DI 2 "register_operand" "1,r")))
286 (clobber (match_scratch:DI 3 "=1,1"))
287 (clobber (match_scratch:DI 4 "=2,2"))
288 (clobber (reg:DI MMIX_rR_REGNUM))]
289 "! TARGET_KNUTH_DIVISION"
292 XOR $255,%1,%2\;NEGU %0,0,%2\;CSN %2,%2,%0\;NEGU %0,0,%1\;CSN %1,%1,%0\;\
293 DIVU %0,%1,%2\;NEGU %1,0,%0\;CSN %0,$255,%1")
295 (define_expand "moddi3"
297 [(set (match_operand:DI 0 "register_operand" "=&r")
298 (mod:DI (match_operand:DI 1 "register_operand" "r")
299 (match_operand:DI 2 "register_operand" "r")))
300 (clobber (scratch:DI))
301 (clobber (scratch:DI))
302 (clobber (reg:DI MMIX_rR_REGNUM))])]
303 "! TARGET_KNUTH_DIVISION"
306 ;; The %2-is-%1-case is there just to make sure things don't fail. Could
307 ;; presumably happen with optimizations off; no evidence.
308 (define_insn "*moddi3_nonknuth"
309 [(set (match_operand:DI 0 "register_operand" "=&r,r")
310 (mod:DI (match_operand:DI 1 "register_operand" "r,r")
311 (match_operand:DI 2 "register_operand" "1,r")))
312 (clobber (match_scratch:DI 3 "=1,1"))
313 (clobber (match_scratch:DI 4 "=2,2"))
314 (clobber (reg:DI MMIX_rR_REGNUM))]
315 "! TARGET_KNUTH_DIVISION"
318 NEGU %0,0,%2\;CSN %2,%2,%0\;NEGU $255,0,%1\;CSN %1,%1,$255\;\
319 DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
321 (define_insn "ashldi3"
322 [(set (match_operand:DI 0 "register_operand" "=r")
324 (match_operand:DI 1 "register_operand" "r")
325 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
329 (define_insn "ashrdi3"
330 [(set (match_operand:DI 0 "register_operand" "=r")
332 (match_operand:DI 1 "register_operand" "r")
333 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
337 (define_insn "lshrdi3"
338 [(set (match_operand:DI 0 "register_operand" "=r")
340 (match_operand:DI 1 "register_operand" "r")
341 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
345 (define_insn "negdi2"
346 [(set (match_operand:DI 0 "register_operand" "=r")
347 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
351 (define_expand "negdf2"
352 [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
353 (neg:DF (match_operand:DF 1 "register_operand" "r")))
354 (use (match_dup 2))])]
357 /* Emit bit-flipping sequence to be IEEE-safe wrt. -+0. */
358 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
361 (define_insn "*expanded_negdf2"
362 [(set (match_operand:DF 0 "register_operand" "=r")
363 (neg:DF (match_operand:DF 1 "register_operand" "r")))
364 (use (match_operand:DI 2 "register_operand" "r"))]
368 ;; FIXME: define_expand for absdi2?
370 (define_insn "absdf2"
371 [(set (match_operand:DF 0 "register_operand" "=r")
372 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
376 (define_insn "sqrtdf2"
377 [(set (match_operand:DF 0 "register_operand" "=r")
378 (sqrt:DF (match_operand:DF 1 "register_operand" "r")))]
382 ;; FIXME: define_expand for ffssi2? (not ffsdi2 since int is SImode).
384 (define_insn "one_cmpldi2"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (not:DI (match_operand:DI 1 "register_operand" "r")))]
390 ;; Since we don't have cc0, we do what is recommended in the manual;
391 ;; store away the operands for use in the branch, scc or movcc insn.
392 (define_expand "cmpdi"
393 [(match_operand:DI 0 "register_operand" "")
394 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "")]
398 mmix_compare_op0 = operands[0];
399 mmix_compare_op1 = operands[1];
403 (define_expand "cmpdf"
404 [(match_operand:DF 0 "register_operand" "")
405 (match_operand:DF 1 "register_operand" "")]
409 mmix_compare_op0 = operands[0];
410 mmix_compare_op1 = operands[1];
414 ;; When the user-patterns expand, the resulting insns will match the
417 ;; We can fold the signed-compare where the register value is
418 ;; already equal to (compare:CCTYPE (reg) (const_int 0)).
419 ;; We can't do that at all for floating-point, due to NaN, +0.0
420 ;; and -0.0, and we can only do it for the non/zero test of
421 ;; unsigned, so that has to be done another way.
422 ;; FIXME: Perhaps a peep2 changing CCcode to a new code, that
424 (define_insn "*cmpcc_folded"
425 [(set (match_operand:CC 0 "register_operand" "=r")
427 (match_operand:DI 1 "register_operand" "r")
429 ;; FIXME: Can we test equivalence any other way?
430 ;; FIXME: Can we fold any other way?
431 "REGNO (operands[1]) == REGNO (operands[0])"
432 "%% folded: cmp %0,%1,0")
434 (define_insn "*cmpcc"
435 [(set (match_operand:CC 0 "register_operand" "=r")
437 (match_operand:DI 1 "register_operand" "r")
438 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
443 [(set (match_operand:CC_UNS 0 "register_operand" "=r")
445 (match_operand:DI 1 "register_operand" "r")
446 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
451 [(set (match_operand:CC_FP 0 "register_operand" "=r")
453 (match_operand:DF 1 "register_operand" "r")
454 (match_operand:DF 2 "register_operand" "r")))]
458 ;; FIXME: for -mieee, add fsub %0,%1,%1\;fsub %0,%2,%2 before to
459 ;; make signalling compliant.
461 [(set (match_operand:CC_FPEQ 0 "register_operand" "=r")
463 (match_operand:DF 1 "register_operand" "r")
464 (match_operand:DF 2 "register_operand" "r")))]
469 [(set (match_operand:CC_FUN 0 "register_operand" "=r")
471 (match_operand:DF 1 "register_operand" "r")
472 (match_operand:DF 2 "register_operand" "r")))]
476 ;; In order to get correct rounding, we have to use SFLOT and SFLOTU for
477 ;; conversion. They do not convert to SFmode; they convert to DFmode,
478 ;; with rounding as of SFmode. They are not usable as is, but we pretend
479 ;; we have a single instruction but emit two.
481 ;; Note that this will (somewhat unexpectedly) create an inexact
482 ;; exception if rounding is necessary - has to be masked off in crt0?
483 (define_expand "floatdisf2"
484 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
486 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
487 ;; Let's use a DI scratch, since SF don't generally get into
488 ;; registers. Dunno what's best; it's really a DF, but that
489 ;; doesn't logically follow from operands in the pattern.
490 (clobber (match_scratch:DI 2 "=&r"))])]
494 if (GET_CODE (operands[0]) != MEM)
498 /* FIXME: This stack-slot remains even at -O3. There must be a
501 = validize_mem (assign_stack_temp (SFmode,
502 GET_MODE_SIZE (SFmode), 0));
503 emit_insn (gen_floatdisf2 (stack_slot, operands[1]));
504 emit_move_insn (operands[0], stack_slot);
509 (define_insn "*floatdisf2_real"
510 [(set (match_operand:SF 0 "memory_operand" "=m")
512 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
513 (clobber (match_scratch:DI 2 "=&r"))]
515 "SFLOT %2,%1\;STSF %2,%0")
517 (define_expand "floatunsdisf2"
518 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
520 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
521 ;; Let's use a DI scratch, since SF don't generally get into
522 ;; registers. Dunno what's best; it's really a DF, but that
523 ;; doesn't logically follow from operands in the pattern.
524 (clobber (scratch:DI))])]
528 if (GET_CODE (operands[0]) != MEM)
532 /* FIXME: This stack-slot remains even at -O3. Must be a better
535 = validize_mem (assign_stack_temp (SFmode,
536 GET_MODE_SIZE (SFmode), 0));
537 emit_insn (gen_floatunsdisf2 (stack_slot, operands[1]));
538 emit_move_insn (operands[0], stack_slot);
543 (define_insn "*floatunsdisf2_real"
544 [(set (match_operand:SF 0 "memory_operand" "=m")
546 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
547 (clobber (match_scratch:DI 2 "=&r"))]
549 "SFLOTU %2,%1\;STSF %2,%0")
551 ;; Note that this will (somewhat unexpectedly) create an inexact
552 ;; exception if rounding is necessary - has to be masked off in crt0?
553 (define_insn "floatdidf2"
554 [(set (match_operand:DF 0 "register_operand" "=r")
556 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))]
560 (define_insn "floatunsdidf2"
561 [(set (match_operand:DF 0 "register_operand" "=r")
563 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))]
567 (define_insn "ftruncdf2"
568 [(set (match_operand:DF 0 "register_operand" "=r")
569 (fix:DF (match_operand:DF 1 "register_operand" "r")))]
574 ;; Note that this will (somewhat unexpectedly) create an inexact
575 ;; exception if rounding is necessary - has to be masked off in crt0?
576 (define_insn "fix_truncdfdi2"
577 [(set (match_operand:DI 0 "register_operand" "=r")
578 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "r"))))]
583 (define_insn "fixuns_truncdfdi2"
584 [(set (match_operand:DI 0 "register_operand" "=r")
586 (fix:DF (match_operand:DF 1 "register_operand" "r"))))]
591 ;; It doesn't seem like it's possible to have memory_operand as a
592 ;; predicate here (testcase: libgcc2 floathisf). FIXME: Shouldn't it be
593 ;; possible to do that? Bug in GCC? Anyway, this used to be a simple
594 ;; pattern with a memory_operand predicate, but was split up with a
595 ;; define_expand with the old pattern as "anonymous".
596 ;; FIXME: Perhaps with SECONDARY_MEMORY_NEEDED?
597 (define_expand "truncdfsf2"
598 [(set (match_operand:SF 0 "memory_operand" "")
599 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
603 if (GET_CODE (operands[0]) != MEM)
605 /* FIXME: There should be a way to say: 'put this in operands[0]
606 but *after* the expanded insn'. */
609 /* There is no sane destination but a register here, if it wasn't
610 already MEM. (It's too hard to get fatal_insn to work here.) */
611 if (! REG_P (operands[0]))
612 internal_error (\"MMIX Internal: Bad truncdfsf2 expansion\");
614 /* FIXME: This stack-slot remains even at -O3. Must be a better
617 = validize_mem (assign_stack_temp (SFmode,
618 GET_MODE_SIZE (SFmode), 0));
619 emit_insn (gen_truncdfsf2 (stack_slot, operands[1]));
620 emit_move_insn (operands[0], stack_slot);
625 (define_insn "*truncdfsf2_real"
626 [(set (match_operand:SF 0 "memory_operand" "=m")
627 (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
631 ;; Same comment as for truncdfsf2.
632 (define_expand "extendsfdf2"
633 [(set (match_operand:DF 0 "register_operand" "=r")
634 (float_extend:DF (match_operand:SF 1 "memory_operand" "m")))]
638 if (GET_CODE (operands[1]) != MEM)
642 /* There is no sane destination but a register here, if it wasn't
643 already MEM. (It's too hard to get fatal_insn to work here.) */
644 if (! REG_P (operands[0]))
645 internal_error (\"MMIX Internal: Bad extendsfdf2 expansion\");
647 /* FIXME: This stack-slot remains even at -O3. There must be a
650 = validize_mem (assign_stack_temp (SFmode,
651 GET_MODE_SIZE (SFmode), 0));
652 emit_move_insn (stack_slot, operands[1]);
653 emit_insn (gen_extendsfdf2 (operands[0], stack_slot));
658 (define_insn "*extendsfdf2_real"
659 [(set (match_operand:DF 0 "register_operand" "=r")
660 (float_extend:DF (match_operand:SF 1 "memory_operand" "m")))]
664 ;; Neither sign-extend nor zero-extend are necessary; gcc knows how to
665 ;; synthesize using shifts or and, except with a memory source and not
666 ;; completely optimal. FIXME: Actually, other bugs surface when those
667 ;; patterns are defined; fix later.
669 ;; There are no sane values with the bit-patterns of (int) 0..255 except
670 ;; 0 to use in movdfcc.
672 (define_expand "movdfcc"
673 [(set (match_operand:DF 0 "register_operand" "")
675 (match_operand 1 "comparison_operator" "")
676 (match_operand:DF 2 "mmix_reg_or_0_operand" "")
677 (match_operand:DF 3 "mmix_reg_or_0_operand" "")))]
681 enum rtx_code code = GET_CODE (operands[1]);
682 rtx cc_reg = mmix_gen_compare_reg (code, mmix_compare_op0,
684 if (cc_reg == NULL_RTX)
686 operands[1] = gen_rtx (code, VOIDmode, cc_reg, const0_rtx);
689 (define_expand "movdicc"
690 [(set (match_operand:DI 0 "register_operand" "")
692 (match_operand 1 "comparison_operator" "")
693 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "")
694 (match_operand:DI 3 "mmix_reg_or_8bit_operand" "")))]
698 enum rtx_code code = GET_CODE (operands[1]);
699 rtx cc_reg = mmix_gen_compare_reg (code, mmix_compare_op0,
701 if (cc_reg == NULL_RTX)
703 operands[1] = gen_rtx (code, VOIDmode, cc_reg, const0_rtx);
706 ;; FIXME: Is this the right way to do "folding" of CCmode -> DImode?
707 (define_insn "*movdicc_real_foldable"
708 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
710 (match_operator 2 "mmix_foldable_comparison_operator"
711 [(match_operand 3 "register_operand" "r,r,r,r")
713 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,0 ,rI,GM")
714 (match_operand:DI 4 "mmix_reg_or_8bit_operand" "0 ,rI,GM,rI")))]
722 (define_insn "*movdicc_real"
724 (match_operand:DI 0 "register_operand" "=r ,r ,r ,r")
727 2 "mmix_comparison_operator"
728 [(match_operand 3 "mmix_reg_cc_operand" "r ,r ,r ,r")
730 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,0 ,rI,GM")
731 (match_operand:DI 4 "mmix_reg_or_8bit_operand" "0 ,rI,GM,rI")))]
739 (define_insn "*movdfcc_real_foldable"
741 (match_operand:DF 0 "register_operand" "=r ,r ,r ,r")
744 2 "mmix_foldable_comparison_operator"
745 [(match_operand 3 "register_operand" "r ,r ,r ,r")
747 (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,0 ,rGM,GM")
748 (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,rGM,GM ,rGM")))]
756 (define_insn "*movdfcc_real"
758 (match_operand:DF 0 "register_operand" "=r ,r ,r ,r")
761 2 "mmix_comparison_operator"
762 [(match_operand 3 "mmix_reg_cc_operand" "r ,r ,r ,r")
764 (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,0 ,rGM,GM")
765 (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,rGM,GM ,rGM")))]
773 ;; FIXME: scc patterns will probably help, I just skip them
774 ;; right now. Revisit.
778 (if_then_else (eq (match_dup 1) (const_int 0))
779 (label_ref (match_operand 0 "" ""))
785 = mmix_gen_compare_reg (EQ, mmix_compare_op0, mmix_compare_op1);
790 (if_then_else (ne (match_dup 1) (const_int 0))
791 (label_ref (match_operand 0 "" ""))
797 = mmix_gen_compare_reg (NE, mmix_compare_op0, mmix_compare_op1);
802 (if_then_else (gt (match_dup 1) (const_int 0))
803 (label_ref (match_operand 0 "" ""))
809 = mmix_gen_compare_reg (GT, mmix_compare_op0, mmix_compare_op1);
814 (if_then_else (le (match_dup 1) (const_int 0))
815 (label_ref (match_operand 0 "" ""))
821 = mmix_gen_compare_reg (LE, mmix_compare_op0, mmix_compare_op1);
823 /* The head comment of optabs.c:can_compare_p says we're required to
824 implement this, so we have to clean up the mess here. */
825 if (operands[1] == NULL_RTX)
827 /* FIXME: Watch out for sharing/unsharing of rtx:es. */
828 emit_jump_insn ((*bcc_gen_fctn[(int) LT]) (operands[0]));
829 emit_jump_insn ((*bcc_gen_fctn[(int) EQ]) (operands[0]));
836 (if_then_else (ge (match_dup 1) (const_int 0))
837 (label_ref (match_operand 0 "" ""))
843 = mmix_gen_compare_reg (GE, mmix_compare_op0, mmix_compare_op1);
845 /* The head comment of optabs.c:can_compare_p says we're required to
846 implement this, so we have to clean up the mess here. */
847 if (operands[1] == NULL_RTX)
849 /* FIXME: Watch out for sharing/unsharing of rtx:es. */
850 emit_jump_insn ((*bcc_gen_fctn[(int) GT]) (operands[0]));
851 emit_jump_insn ((*bcc_gen_fctn[(int) EQ]) (operands[0]));
858 (if_then_else (lt (match_dup 1) (const_int 0))
859 (label_ref (match_operand 0 "" ""))
865 = mmix_gen_compare_reg (LT, mmix_compare_op0, mmix_compare_op1);
868 (define_expand "bgtu"
870 (if_then_else (gtu (match_dup 1) (const_int 0))
871 (label_ref (match_operand 0 "" ""))
877 = mmix_gen_compare_reg (GTU, mmix_compare_op0, mmix_compare_op1);
880 (define_expand "bleu"
882 (if_then_else (leu (match_dup 1) (const_int 0))
883 (label_ref (match_operand 0 "" ""))
889 = mmix_gen_compare_reg (LEU, mmix_compare_op0, mmix_compare_op1);
892 (define_expand "bgeu"
894 (if_then_else (geu (match_dup 1) (const_int 0))
895 (label_ref (match_operand 0 "" ""))
901 = mmix_gen_compare_reg (GEU, mmix_compare_op0, mmix_compare_op1);
904 (define_expand "bltu"
906 (if_then_else (ltu (match_dup 1) (const_int 0))
907 (label_ref (match_operand 0 "" ""))
913 = mmix_gen_compare_reg (LTU, mmix_compare_op0, mmix_compare_op1);
916 (define_expand "bunordered"
918 (if_then_else (unordered (match_dup 1) (const_int 0))
919 (label_ref (match_operand 0 "" ""))
925 = mmix_gen_compare_reg (UNORDERED, mmix_compare_op0, mmix_compare_op1);
927 if (operands[1] == NULL_RTX)
931 (define_expand "bordered"
933 (if_then_else (ordered (match_dup 1) (const_int 0))
934 (label_ref (match_operand 0 "" ""))
940 = mmix_gen_compare_reg (ORDERED, mmix_compare_op0, mmix_compare_op1);
943 ;; FIXME: we can emit an unordered-or-*not*-equal compare in one insn, but
944 ;; there's no RTL code for it. Maybe revisit in future.
946 ;; FIXME: Odd/Even matchers?
947 (define_insn "*bCC_foldable"
950 (match_operator 1 "mmix_foldable_comparison_operator"
951 [(match_operand 2 "register_operand" "r")
953 (label_ref (match_operand 0 "" ""))
961 (match_operator 1 "mmix_comparison_operator"
962 [(match_operand 2 "mmix_reg_cc_operand" "r")
964 (label_ref (match_operand 0 "" ""))
969 (define_insn "*bCC_inverted_foldable"
972 (match_operator 1 "mmix_foldable_comparison_operator"
973 [(match_operand 2 "register_operand" "r")
976 (label_ref (match_operand 0 "" ""))))]
977 ;; REVERSIBLE_CC_MODE is checked by mmix_foldable_comparison_operator.
981 (define_insn "*bCC_inverted"
984 (match_operator 1 "mmix_comparison_operator"
985 [(match_operand 2 "mmix_reg_cc_operand" "r")
988 (label_ref (match_operand 0 "" ""))))]
989 "REVERSIBLE_CC_MODE (GET_MODE (operands[2]))"
992 (define_expand "call"
993 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
994 (match_operand 1 "general_operand" ""))
995 (use (match_operand 2 "general_operand" ""))
996 (clobber (match_dup 4))])
997 (set (match_dup 4) (match_dup 3))]
1001 /* Since the epilogue 'uses' the return address, and it is clobbered
1002 in the call, and we set it back after every call (all but one setting
1003 will be optimized away), integrity is maintained. */
1005 = mmix_get_hard_reg_initial_val (Pmode,
1006 MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1008 /* FIXME: There's a bug in gcc which causes NULL to be passed as
1009 operand[2] when we get out of registers, which later confuses gcc.
1010 Work around it by replacing it with const_int 0. Possibly documentation
1012 if (operands[2] == NULL_RTX)
1013 operands[2] = const0_rtx;
1015 operands[4] = gen_rtx_REG (DImode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1018 (define_expand "call_value"
1019 [(parallel [(set (match_operand 0 "" "")
1020 (call (match_operand:QI 1 "memory_operand" "")
1021 (match_operand 2 "general_operand" "")))
1022 (use (match_operand 3 "general_operand" ""))
1023 (clobber (match_dup 5))])
1024 (set (match_dup 5) (match_dup 4))]
1028 /* Since the epilogue 'uses' the return address, and it is clobbered
1029 in the call, and we set it back after every call (all but one setting
1030 will be optimized away), integrity is maintained. */
1032 = mmix_get_hard_reg_initial_val (Pmode,
1033 MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1035 /* FIXME: See 'call'. */
1036 if (operands[3] == NULL_RTX)
1037 operands[3] = const0_rtx;
1039 /* FIXME: Documentation bug: operands[3] (operands[2] for 'call') is the
1040 *next* argument register, not the number of arguments in registers.
1041 (There used to be code here where that mattered.) */
1043 operands[5] = gen_rtx_REG (DImode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1046 ;; Don't use 'p' here. A 'p' must stand first in constraints, or reload
1047 ;; messes up, not registering the address for reload. Several C++
1048 ;; test-cases, including g++.brendan/crash40.C. FIXME: This is arguably a
1049 ;; bug in gcc. Note line ~2612 in reload.c, that does things on the
1050 ;; condition <<else if (constraints[i][0] == 'p')>> and the comment on
1053 ;; /* All necessary reloads for an address_operand
1054 ;; were handled in find_reloads_address. */>>
1055 ;; Sorry, I have not dug deeper. If symbolic addresses are used
1056 ;; rarely compared to addresses in registers, disparaging the
1057 ;; first ("p") alternative by adding ? in the first operand
1058 ;; might do the trick. We define 'U' as a synonym to 'p', but without the
1059 ;; caveats (and very small advantages) of 'p'.
1060 (define_insn "*call_real"
1062 (match_operand:DI 0 "mmix_symbolic_or_address_operand" "s,rU"))
1063 (match_operand 1 "" ""))
1064 (use (match_operand 2 "" ""))
1065 (clobber (reg:DI MMIX_rJ_REGNUM))]
1071 (define_insn "*call_value_real"
1072 [(set (match_operand 0 "register_operand" "=r,r")
1074 (match_operand:DI 1 "mmix_symbolic_or_address_operand" "s,rU"))
1075 (match_operand 2 "" "")))
1076 (use (match_operand 3 "" ""))
1077 (clobber (reg:DI MMIX_rJ_REGNUM))]
1083 ;; I hope untyped_call and untyped_return are not needed for MMIX.
1084 ;; Users of Objective-C will notice.
1087 (define_expand "return"
1089 "mmix_use_simple_return ()"
1092 ; Generated by the epilogue expander.
1093 (define_insn "*expanded_return"
1098 (define_expand "prologue"
1101 "mmix_expand_prologue (); DONE;")
1103 ; Note that the (return) from the expander itself is always the last insn
1105 (define_expand "epilogue"
1108 "mmix_expand_epilogue ();")
1116 [(set (pc) (label_ref (match_operand 0 "" "")))]
1120 (define_insn "indirect_jump"
1121 [(set (pc) (match_operand 0 "address_operand" "p"))]
1125 ;; FIXME: This is just a jump, and should be expanded to one.
1126 (define_insn "tablejump"
1127 [(set (pc) (match_operand:DI 0 "address_operand" "p"))
1128 (use (label_ref (match_operand 1 "" "")))]
1132 ;; The only peculiar thing is that the register stack has to be unwound at
1133 ;; nonlocal_goto_receiver. At each function that has a nonlocal label, we
1134 ;; save at function entry the location of the "alpha" register stack
1135 ;; pointer, rO, in a stack slot known to that function (right below where
1136 ;; the frame-pointer would be located).
1137 ;; In the nonlocal goto receiver, we unwind the register stack by a series
1138 ;; of "pop 0,0" until rO equals the saved value. (If it goes lower, we
1139 ;; should call abort.)
1140 (define_expand "nonlocal_goto_receiver"
1141 [(parallel [(unspec_volatile [(const_int 0)] 1)
1142 (clobber (scratch:DI))
1143 (clobber (reg:DI MMIX_rJ_REGNUM))])
1144 (set (reg:DI MMIX_rJ_REGNUM) (match_dup 0))]
1149 = mmix_get_hard_reg_initial_val (Pmode,
1150 MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1152 /* Mark this function as containing a landing-pad. */
1153 cfun->machine->has_landing_pad = 1;
1156 ;; GCC can insist on using saved registers to keep the slot address in
1157 ;; "across" the exception, or (perhaps) to use saved registers in the
1158 ;; address and re-use them after the register stack unwind, so it's best
1159 ;; to form the address ourselves.
1160 (define_insn "*nonlocal_goto_receiver_expanded"
1161 [(unspec_volatile [(const_int 0)] 1)
1162 (clobber (match_scratch:DI 0 "=&r"))
1163 (clobber (reg:DI MMIX_rJ_REGNUM))]
1166 rtx temp_reg = operands[0];
1168 HOST_WIDEST_INT offs;
1169 const char *my_template
1170 = "GETA $255,0f\;PUT rJ,$255\;LDOU $255,%a0\n\
1171 0:\;GET %1,rO\;CMPU %1,%1,$255\;BNP %1,1f\;POP 0,0\n1:";
1173 my_operands[1] = temp_reg;
1175 /* If we have a frame-pointer (hence unknown stack-pointer offset),
1176 just use the frame-pointer and the known offset. */
1177 if (frame_pointer_needed)
1179 my_operands[0] = GEN_INT (-MMIX_fp_rO_OFFSET);
1181 output_asm_insn ("NEGU %1,0,%0", my_operands);
1182 my_operands[0] = gen_rtx_PLUS (Pmode, frame_pointer_rtx, temp_reg);
1186 /* We know the fp-based offset, so "eliminate" it to be sp-based. */
1188 = (mmix_initial_elimination_offset (MMIX_FRAME_POINTER_REGNUM,
1189 MMIX_STACK_POINTER_REGNUM)
1190 + MMIX_fp_rO_OFFSET);
1192 if (offs >= 0 && offs <= 255)
1194 = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offs));
1197 mmix_output_register_setting (asm_out_file, REGNO (temp_reg),
1199 my_operands[0] = gen_rtx_PLUS (Pmode, stack_pointer_rtx, temp_reg);
1203 output_asm_insn (my_template, my_operands);
1207 (define_insn "*Naddu"
1208 [(set (match_operand:DI 0 "register_operand" "=r")
1209 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
1210 (match_operand:DI 2 "const_int_operand" "n"))
1211 (match_operand:DI 3 "mmix_reg_or_8bit_operand" "rI")))]
1212 "GET_CODE (operands[2]) == CONST_INT
1213 && (INTVAL (operands[2]) == 2
1214 || INTVAL (operands[2]) == 4
1215 || INTVAL (operands[2]) == 8
1216 || INTVAL (operands[2]) == 16)"
1219 (define_insn "*andn"
1220 [(set (match_operand:DI 0 "register_operand" "=r")
1222 (not:DI (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI"))
1223 (match_operand:DI 2 "register_operand" "r")))]
1227 (define_insn "*nand"
1228 [(set (match_operand:DI 0 "register_operand" "=r")
1230 (not:DI (match_operand:DI 1 "register_operand" "%r"))
1231 (not:DI (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
1236 [(set (match_operand:DI 0 "register_operand" "=r")
1238 (not:DI (match_operand:DI 1 "register_operand" "%r"))
1239 (not:DI (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
1243 (define_insn "*nxor"
1244 [(set (match_operand:DI 0 "register_operand" "=r")
1246 (xor:DI (match_operand:DI 1 "register_operand" "%r")
1247 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
1251 (define_insn "sync_icache"
1252 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")
1253 (match_operand:DI 1 "const_int_operand" "I")] 0)]
1259 ;; indent-tabs-mode: t