| blob | 6d2078c966cd5aaca825169e0f9db7ed6f015432 |
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #ifndef GCC_MCORE_H
23 #define GCC_MCORE_H
25 /* RBE: need to move these elsewhere. */
26 #undef LIKE_PPC_ABI
27 #define MCORE_STRUCT_ARGS
28 /* RBE: end of "move elsewhere". */
32 #ifndef HAVE_MACHINE_MODES
34 #endif
36 /* Run-time Target Specification. */
37 #define TARGET_MCORE
39 /* Get tree.c to declare a target-specific specialization of
40 merge_decl_attributes. */
41 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES
43 /* Support the __declspec keyword by turning them into attributes.
44 We currently only support: dllexport and dllimport.
45 Note that the current way we do this may result in a collision with
46 predefined attributes later on. This can be solved by using one attribute,
47 say __declspec__, and passing args to it. The problem with that approach
48 is that args are not accumulated: each new appearance would clobber any
49 existing args. XXX- FIXME the definition below relies upon string
50 concatenation, which is non-portable. */
51 #define CPP_PREDEFINES \
54 /* If -m4align is ever re-enabled then uncomment this line as well:
55 #define CPP_SPEC "%{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}" */
57 #undef CPP_SPEC
59 %{mbig-endian: \
60 %{mlittle-endian:%echoose either big or little endian, not both} \
61 -D__MCOREBE__} \
62 %{m210: \
63 %{m340:%echoose either m340 or m210 not both} \
64 %{mlittle-endian:%ethe m210 does not have little endian support} \
65 -D__M210__} \
66 %{!mbig-endian: -D__MCORELE__} \
67 %{!m210: -D__M340__} \
68 "
69 /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
70 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */
72 /* We don't have a -lg library, so don't put it in the list. */
73 #undef LIB_SPEC
76 #undef ASM_SPEC
79 #undef LINK_SPEC
82 /* Can only count on 16 bits of availability; change to long would affect
83 many architecture specific files (other architectures...). */
97 #define TARGET_DEFAULT \
98 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
100 #ifndef MULTILIB_DEFAULTS
102 #endif
104 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
105 /* The ability to have 4 byte alignment is being suppressed for now.
106 If this ability is reenabled, you must enable the definition below
107 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
108 #if 0
109 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
110 #else
111 #define TARGET_8ALIGN 1
112 #endif
113 #define TARGET_DIV (target_flags & DIV_BIT)
114 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
115 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
116 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
117 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
118 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
119 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
120 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
121 #define TARGET_M340 (target_flags & M340_BIT)
124 #define TARGET_SWITCHES \
168 }
172 /* Target specific options (as opposed to the switches above). */
175 #define TARGET_OPTIONS \
176 { \
179 }
181 #ifndef CC1_SPEC
182 /* The MCore ABI says that bitfields are unsigned by default. */
184 #endif
186 /* What options are we going to default to specific settings when
187 -O* happens; the user can subsequently override these settings.
189 Omitting the frame pointer is a very good idea on the MCore.
190 Scheduling isn't worth anything on the current MCore implementation. */
191 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
192 { \
193 if (LEVEL) \
194 { \
195 flag_no_function_cse = 1; \
196 flag_omit_frame_pointer = 1; \
197 \
198 if (LEVEL >= 2) \
199 { \
200 flag_caller_saves = 0; \
201 flag_schedule_insns = 0; \
202 flag_schedule_insns_after_reload = 0; \
203 } \
204 } \
205 if (SIZE) \
206 { \
207 target_flags &= ~ HARDLIT_BIT; \
208 } \
209 }
211 /* What options are we going to force to specific settings,
212 regardless of what the user thought he wanted.
213 We also use this for some post-processing of options. */
214 #define OVERRIDE_OPTIONS mcore_override_options ()
216 /* Target machine storage Layout. */
218 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
219 if (GET_MODE_CLASS (MODE) == MODE_INT \
220 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
221 { \
222 (MODE) = SImode; \
223 (UNSIGNEDP) = 1; \
224 }
226 #define PROMOTE_FUNCTION_ARGS
228 #define PROMOTE_FUNCTION_RETURN
230 /* Define this if most significant bit is lowest numbered
231 in instructions that operate on numbered bit-fields. */
232 #define BITS_BIG_ENDIAN 0
234 /* Define this if most significant byte of a word is the lowest numbered. */
235 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
237 /* Define this if most significant word of a multiword number is the lowest
238 numbered. */
239 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
241 #define LIBGCC2_WORDS_BIG_ENDIAN 1
242 #ifdef __MCORELE__
243 #undef LIBGCC2_WORDS_BIG_ENDIAN
244 #define LIBGCC2_WORDS_BIG_ENDIAN 0
245 #endif
247 #define MAX_BITS_PER_WORD 32
249 /* Width of a word, in units (bytes). */
250 #define UNITS_PER_WORD 4
252 /* A C expression for the size in bits of the type `long long' on the
253 target machine. If you don't define this, the default is two
254 words. */
255 #define LONG_LONG_TYPE_SIZE 64
257 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
258 #define PARM_BOUNDARY 32
260 /* Doubles must be alogned to an 8 byte boundary. */
261 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
262 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
263 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
265 /* Boundary (in *bits*) on which stack pointer should be aligned. */
266 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
268 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
270 #define STACK_UNITS_MAXSTEP 4096
272 /* Allocation boundary (in *bits*) for the code of a function. */
273 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
275 /* Alignment of field after `int : 0' in a structure. */
276 #define EMPTY_FIELD_BOUNDARY 32
278 /* No data type wants to be aligned rounder than this. */
279 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
281 /* The best alignment to use in cases where we have a choice. */
282 #define FASTEST_ALIGNMENT 32
284 /* Every structures size must be a multiple of 8 bits. */
285 #define STRUCTURE_SIZE_BOUNDARY 8
287 /* Look at the fundamental type that is used for a bit-field and use
288 that to impose alignment on the enclosing structure.
289 struct s {int a:8}; should have same alignment as "int", not "char". */
290 #define PCC_BITFIELD_TYPE_MATTERS 1
292 /* Largest integer machine mode for structures. If undefined, the default
293 is GET_MODE_SIZE(DImode). */
294 #define MAX_FIXED_MODE_SIZE 32
296 /* Make strings word-aligned so strcpy from constants will be faster. */
297 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
298 ((TREE_CODE (EXP) == STRING_CST \
299 && (ALIGN) < FASTEST_ALIGNMENT) \
300 ? FASTEST_ALIGNMENT : (ALIGN))
302 /* Make arrays of chars word-aligned for the same reasons. */
303 #define DATA_ALIGNMENT(TYPE, ALIGN) \
304 (TREE_CODE (TYPE) == ARRAY_TYPE \
305 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
306 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
308 /* Set this nonzero if move instructions will actually fail to work
309 when given unaligned data. */
310 #define STRICT_ALIGNMENT 1
312 /* Standard register usage. */
314 /* Register allocation for our first guess
316 r0 stack pointer
317 r1 scratch, target reg for xtrb?
318 r2-r7 arguments.
319 r8-r14 call saved
320 r15 link register
321 ap arg pointer (doesn't really exist, always eliminated)
322 c c bit
323 fp frame pointer (doesn't really exist, always eliminated)
324 x19 two control registers */
326 /* Number of actual hardware registers.
327 The hardware registers are assigned numbers for the compiler
328 from 0 to just below FIRST_PSEUDO_REGISTER.
329 All registers that the compiler knows about must be given numbers,
330 even those that are not normally considered general registers.
332 MCore has 16 integer registers and 2 control registers + the arg
333 pointer. */
335 #define FIRST_PSEUDO_REGISTER 20
340 /* RBE: mcore.md depends on CC_REG being set to 17 */
344 /* Specify the registers used for certain standard purposes.
345 The values of these macros are register numbers. */
352 /* The assembler's names for the registers. RFP need not always be used as
353 the Real framepointer; it can also be used as a normal general register.
354 Note that the name `fp' is horribly misleading since `fp' is in fact only
355 the argument-and-return-context pointer. */
356 #define REGISTER_NAMES \
357 { \
361 }
363 /* 1 for registers that have pervasive standard uses
364 and are not available for the register allocator. */
365 #define FIXED_REGISTERS \
367 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
369 /* 1 for registers not available across function calls.
370 These must include the FIXED_REGISTERS and also any
371 registers that can be used without being saved.
372 The latter must include the registers where values are returned
373 and the register where structure-value addresses are passed.
374 Aside from that, you can include as many other registers as you like. */
376 /* RBE: r15 {link register} not available across calls,
377 * But we don't mark it that way here... */
378 #define CALL_USED_REGISTERS \
380 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
382 /* The order in which register should be allocated. */
383 #define REG_ALLOC_ORDER \
385 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
387 /* Return number of consecutive hard regs needed starting at reg REGNO
388 to hold something of mode MODE.
389 This is ordinarily the length in words of a value of mode MODE
390 but can be less for certain modes in special long registers.
392 On the MCore regs are UNITS_PER_WORD bits wide; */
393 #define HARD_REGNO_NREGS(REGNO, MODE) \
394 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
396 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
397 We may keep double values in even registers. */
398 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
399 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
401 /* Value is 1 if it is a good idea to tie two pseudo registers
402 when one has mode MODE1 and one has mode MODE2.
403 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
404 for any hard reg, then this must be 0 for correct output. */
405 #define MODES_TIEABLE_P(MODE1, MODE2) \
406 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
408 /* Value should be nonzero if functions must have frame pointers.
409 Zero means the frame pointer need not be set up (and parms may be accessed
410 via the stack pointer) in functions that seem suitable. */
411 #define FRAME_POINTER_REQUIRED 0
413 /* Definitions for register eliminations.
415 We have two registers that can be eliminated on the MCore. First, the
416 frame pointer register can often be eliminated in favor of the stack
417 pointer register. Secondly, the argument pointer register can always be
418 eliminated; it is replaced with either the stack or frame pointer. */
420 /* Base register for access to arguments of the function. */
421 #define ARG_POINTER_REGNUM 16
423 /* Register in which the static-chain is passed to a function. */
424 #define STATIC_CHAIN_REGNUM 1
426 /* This is an array of structures. Each structure initializes one pair
427 of eliminable registers. The "from" register number is given first,
428 followed by "to". Eliminations of the same "from" register are listed
429 in order of preference. */
430 #define ELIMINABLE_REGS \
431 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
432 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
433 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
435 /* Given FROM and TO register numbers, say whether this elimination
436 is allowed. */
437 #define CAN_ELIMINATE(FROM, TO) \
438 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
440 /* Define the offset between two registers, one to be eliminated, and the other
441 its replacement, at the start of a routine. */
442 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
443 OFFSET = mcore_initial_elimination_offset (FROM, TO)
445 /* Place that structure value return address is placed. */
446 #define STRUCT_VALUE 0
448 /* Define the classes of registers for register constraints in the
449 machine description. Also define ranges of constants.
451 One of the classes must always be named ALL_REGS and include all hard regs.
452 If there is more than one class, another class must be named NO_REGS
453 and contain no registers.
455 The name GENERAL_REGS must be the name of a class (or an alias for
456 another name such as ALL_REGS). This is the class of registers
457 that is allowed by "g" or "r" in a register constraint.
458 Also, registers outside this class are allocated only when
459 instructions express preferences for them.
461 The classes must be numbered in nondecreasing order; that is,
462 a larger-numbered class must never be contained completely
463 in a smaller-numbered class.
465 For any two classes, it is very desirable that there be another
466 class that represents their union. */
468 /* The MCore has only general registers. There are
469 also some special purpose registers: the T bit register, the
470 procedure Link and the Count Registers */
471 enum reg_class
472 {
473 NO_REGS,
474 ONLYR1_REGS,
475 LRW_REGS,
476 GENERAL_REGS,
477 C_REGS,
478 ALL_REGS,
479 LIM_REG_CLASSES
480 };
482 #define N_REG_CLASSES (int) LIM_REG_CLASSES
484 /* Give names of register classes as strings for dump file. */
485 #define REG_CLASS_NAMES \
486 { \
493 }
495 /* Define which registers fit in which classes.
496 This is an initializer for a vector of HARD_REG_SET
497 of length N_REG_CLASSES. */
499 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
500 #define REG_CLASS_CONTENTS \
501 { \
508 }
510 /* The same information, inverted:
511 Return the class number of the smallest class containing
512 reg number REGNO. This could be a conditional expression
513 or could index an array. */
516 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
518 /* When defined, the compiler allows registers explicitly used in the
519 rtl to be used as spill registers but prevents the compiler from
520 extending the lifetime of these registers. */
521 #define SMALL_REGISTER_CLASSES 1
523 /* The class value for index registers, and the one for base regs. */
524 #define INDEX_REG_CLASS NO_REGS
525 #define BASE_REG_CLASS GENERAL_REGS
527 /* Get reg_class from a letter such as appears in the machine
528 description. */
531 #define REG_CLASS_FROM_LETTER(C) \
534 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
535 can be used to stand for particular ranges of immediate operands.
536 This macro defines what the ranges are.
537 C is the letter, and VALUE is a constant value.
538 Return 1 if VALUE is in the range specified by C.
539 I: loadable by movi (0..127)
540 J: arithmetic operand 1..32
541 K: shift operand 0..31
542 L: negative arithmetic operand -1..-32
543 M: powers of two, constants loadable by bgeni
544 N: powers of two minus 1, constants loadable by bmaski, including -1
545 O: allowed by cmov with two constants +/- 1 of each other
546 P: values we will generate 'inline' -- without an 'lrw'
548 Others defined for use after reload
549 Q: constant 1
550 R: a label
551 S: 0/1/2 cleared bits out of 32 [for bclri's]
552 T: 2 set bits out of 32 [for bseti's]
553 U: constant 0
554 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
555 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
556 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
557 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
558 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
559 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
560 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
561 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
562 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
563 CONST_OK_FOR_M(VALUE) || \
564 CONST_OK_FOR_N(VALUE) || \
565 CONST_OK_FOR_M((int)(VALUE) - 1) || \
566 CONST_OK_FOR_N((int)(VALUE) + 1))
568 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
570 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
579 : 0)
581 /* Similar, but for floating constants, and defining letters G and H.
582 Here VALUE is the CONST_DOUBLE rtx itself. */
583 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
585 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
586 : 0)
588 /* Letters in the range `Q' through `U' in a register constraint string
589 may be defined in a machine-dependent fashion to stand for arbitrary
590 operand types. */
591 #define EXTRA_CONSTRAINT(OP, C) \
593 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
595 && mcore_num_zeros (INTVAL (OP)) <= 2) \
597 && mcore_num_ones (INTVAL (OP)) == 2) \
599 && INTVAL(OP) == 1) \
601 && INTVAL(OP) == 0) \
602 : 0)
604 /* Given an rtx X being reloaded into a reg required to be
605 in class CLASS, return the class of reg to actually use.
606 In general this is just CLASS; but on some machines
607 in some cases it is preferable to use a more restrictive class. */
608 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
610 /* Return the register class of a scratch register needed to copy IN into
611 or out of a register in CLASS in MODE. If it can be done directly,
612 NO_REGS is returned. */
613 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
615 /* Return the maximum number of consecutive registers
616 needed to represent mode MODE in a register of class CLASS.
618 On MCore this is the size of MODE in words. */
619 #define CLASS_MAX_NREGS(CLASS, MODE) \
620 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
622 /* Stack layout; function entry, exit and calling. */
624 /* Define the number of register that can hold parameters.
625 These two macros are used only in other macro definitions below. */
626 #define NPARM_REGS 6
627 #define FIRST_PARM_REG 2
628 #define FIRST_RET_REG 2
630 /* Define this if pushing a word on the stack
631 makes the stack pointer a smaller address. */
632 #define STACK_GROWS_DOWNWARD
634 /* Define this if the nominal address of the stack frame
635 is at the high-address end of the local variables;
636 that is, each additional local variable allocated
637 goes at a more negative offset in the frame. */
638 /* We don't define this, because the MCore does not support
639 addresses with negative offsets. */
640 /* #define FRAME_GROWS_DOWNWARD */
642 /* Offset within stack frame to start allocating local variables at.
643 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
644 first local allocated. Otherwise, it is the offset to the BEGINNING
645 of the first local allocated. */
646 #define STARTING_FRAME_OFFSET 0
648 /* If defined, the maximum amount of space required for outgoing arguments
649 will be computed and placed into the variable
650 `current_function_outgoing_args_size'. No space will be pushed
651 onto the stack for each call; instead, the function prologue should
652 increase the stack frame size by this amount. */
653 #define ACCUMULATE_OUTGOING_ARGS 1
655 /* Offset of first parameter from the argument pointer register value. */
656 #define FIRST_PARM_OFFSET(FNDECL) 0
658 /* Value is the number of byte of arguments automatically
659 popped when returning from a subroutine call.
660 FUNTYPE is the data type of the function (as a tree),
661 or for a library call it is an identifier node for the subroutine name.
662 SIZE is the number of bytes of arguments passed on the stack.
664 On the MCore, the callee does not pop any of its arguments that were passed
665 on the stack. */
666 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
668 /* Define how to find the value returned by a function.
669 VALTYPE is the data type of the value (as a tree).
670 If the precise function being called is known, FUNC is its FUNCTION_DECL;
671 otherwise, FUNC is 0. */
672 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
674 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
675 we want to retain compatibility with older gcc versions. */
676 #define DEFAULT_PCC_STRUCT_RETURN 0
678 /* how we are going to return big values */
679 /*
680 * #define RETURN_IN_MEMORY(TYPE) \
681 * (TYPE_MODE (TYPE) == BLKmode \
682 * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \
683 * && !(TYPE_MODE (TYPE) == SImode \
684 * || (TYPE_MODE (TYPE) == BLKmode \
685 * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \
686 * && int_size_in_bytes (TYPE) == UNITS_PER_WORD))))
687 */
690 /* How many registers to use for struct return. */
691 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)
693 /* Define how to find the value returned by a library function
694 assuming the value has mode MODE. */
695 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
697 /* 1 if N is a possible register number for a function value.
698 On the MCore, only r4 can return results. */
699 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
701 #define MUST_PASS_IN_STACK(MODE,TYPE) \
702 mcore_must_pass_on_stack (MODE, TYPE)
704 /* 1 if N is a possible register number for function argument passing. */
705 #define FUNCTION_ARG_REGNO_P(REGNO) \
706 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
708 /* Define a data type for recording info about an argument list
709 during the scan of that argument list. This data type should
710 hold all necessary information about the function itself
711 and about the args processed so far, enough to enable macros
712 such as FUNCTION_ARG to determine where the next arg should go.
714 On MCore, this is a single integer, which is a number of words
715 of arguments scanned so far (including the invisible argument,
716 if any, which holds the structure-value-address).
717 Thus NARGREGS or more means all following args should go on the stack. */
718 #define CUMULATIVE_ARGS int
720 #define ROUND_ADVANCE(SIZE) \
721 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
723 /* Round a register number up to a proper boundary for an arg of mode
724 MODE.
726 We round to an even reg for things larger than a word. */
727 #define ROUND_REG(X, MODE) \
728 ((TARGET_8ALIGN \
729 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
730 ? ((X) + ((X) & 1)) : (X))
733 /* Initialize a variable CUM of type CUMULATIVE_ARGS
734 for a call to a function whose data type is FNTYPE.
735 For a library call, FNTYPE is 0.
737 On MCore, the offset always starts at 0: the first parm reg is always
738 the same reg. */
739 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
740 ((CUM) = 0)
742 /* Update the data in CUM to advance over an argument
743 of mode MODE and data type TYPE.
744 (TYPE is null for libcalls where that information may not be
745 available.) */
746 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
747 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
748 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
750 /* Define where to put the arguments to a function. */
751 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
752 mcore_function_arg (CUM, MODE, TYPE, NAMED)
754 /* A C expression that indicates when an argument must be passed by
755 reference. If nonzero for an argument, a copy of that argument is
756 made in memory and a pointer to the argument is passed instead of
757 the argument itself. The pointer is passed in whatever way is
758 appropriate for passing a pointer to that type. */
759 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
760 MUST_PASS_IN_STACK (MODE, TYPE)
762 /* For an arg passed partly in registers and partly in memory,
763 this is the number of registers used.
764 For args passed entirely in registers or entirely in memory, zero.
765 Any arg that starts in the first NPARM_REGS regs but won't entirely
766 fit in them needs partial registers on the MCore. */
767 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
768 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
770 /* Perform any needed actions needed for a function that is receiving a
771 variable number of arguments. */
772 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
773 mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)
775 /* Call the function profiler with a given profile label. */
776 #define FUNCTION_PROFILER(STREAM,LABELNO) \
777 { \
781 }
783 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
784 the stack pointer does not matter. The value is tested only in
785 functions that have frame pointers.
786 No definition is equivalent to always zero. */
787 #define EXIT_IGNORE_STACK 0
789 /* Output assembler code for a block containing the constant parts
790 of a trampoline, leaving space for the variable parts.
792 On the MCore, the trapoline looks like:
793 lrw r1, function
794 lrw r13, area
795 jmp r13
796 or r0, r0
797 .literals */
798 #define TRAMPOLINE_TEMPLATE(FILE) \
799 { \
806 }
808 /* Length in units of the trampoline for entering a nested function. */
809 #define TRAMPOLINE_SIZE 12
811 /* Alignment required for a trampoline in bits. */
812 #define TRAMPOLINE_ALIGNMENT 32
814 /* Emit RTL insns to initialize the variable parts of a trampoline.
815 FNADDR is an RTX for the address of the function's pure code.
816 CXT is an RTX for the static chain value for the function. */
817 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
818 { \
819 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
820 (CXT)); \
821 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
822 (FNADDR)); \
823 }
825 /* Macros to check register numbers against specific register classes. */
827 /* These assume that REGNO is a hard or pseudo reg number.
828 They give nonzero only if REGNO is a hard reg of the suitable class
829 or a pseudo reg currently allocated to a suitable hard reg.
830 Since they use reg_renumber, they are safe only once reg_renumber
831 has been allocated, which happens in local-alloc.c. */
832 #define REGNO_OK_FOR_BASE_P(REGNO) \
833 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
835 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
837 /* Maximum number of registers that can appear in a valid memory
838 address. */
839 #define MAX_REGS_PER_ADDRESS 1
841 /* Recognize any constant value that is a valid address. */
842 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
844 /* Nonzero if the constant value X is a legitimate general operand.
845 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
847 On the MCore, allow anything but a double. */
848 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
850 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
851 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
852 and check its validity for a certain class.
853 We have two alternate definitions for each of them.
854 The usual definition accepts all pseudo regs; the other rejects
855 them unless they have been allocated suitable hard regs.
856 The symbol REG_OK_STRICT causes the latter definition to be used. */
857 #ifndef REG_OK_STRICT
859 /* Nonzero if X is a hard reg that can be used as a base reg
860 or if it is a pseudo reg. */
861 #define REG_OK_FOR_BASE_P(X) \
862 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
864 /* Nonzero if X is a hard reg that can be used as an index
865 or if it is a pseudo reg. */
866 #define REG_OK_FOR_INDEX_P(X) 0
868 #else
870 /* Nonzero if X is a hard reg that can be used as a base reg. */
871 #define REG_OK_FOR_BASE_P(X) \
872 REGNO_OK_FOR_BASE_P (REGNO (X))
874 /* Nonzero if X is a hard reg that can be used as an index. */
875 #define REG_OK_FOR_INDEX_P(X) 0
877 #endif
878 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
879 that is a valid memory address for an instruction.
880 The MODE argument is the machine mode for the MEM expression
881 that wants to use this address.
883 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
884 #define BASE_REGISTER_RTX_P(X) \
885 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
887 #define INDEX_REGISTER_RTX_P(X) \
888 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
891 /* Jump to LABEL if X is a valid address RTX. This must also take
892 REG_OK_STRICT into account when deciding about valid registers, but it uses
893 the above macros so we are in luck.
895 Allow REG
896 REG+disp
898 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
899 and for DI is 0..56 because we use two SI loads, etc. */
900 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
901 do \
902 { \
903 if (GET_CODE (OP) == CONST_INT) \
904 { \
905 if (GET_MODE_SIZE (MODE) >= 4 \
906 && (((unsigned)INTVAL (OP)) % 4) == 0 \
907 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
908 goto LABEL; \
909 if (GET_MODE_SIZE (MODE) == 2 \
910 && (((unsigned)INTVAL (OP)) % 2) == 0 \
911 && ((unsigned)INTVAL (OP)) <= 30) \
912 goto LABEL; \
913 if (GET_MODE_SIZE (MODE) == 1 \
914 && ((unsigned)INTVAL (OP)) <= 15) \
915 goto LABEL; \
916 } \
917 } \
918 while (0)
920 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
921 { \
922 if (BASE_REGISTER_RTX_P (X)) \
923 goto LABEL; \
924 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
925 { \
926 rtx xop0 = XEXP (X,0); \
927 rtx xop1 = XEXP (X,1); \
928 if (BASE_REGISTER_RTX_P (xop0)) \
929 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
930 if (BASE_REGISTER_RTX_P (xop1)) \
931 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
932 } \
933 }
935 /* Go to LABEL if ADDR (a legitimate address expression)
936 has an effect that depends on the machine mode it is used for. */
937 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
938 { \
939 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
940 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
941 goto LABEL; \
942 }
944 /* Specify the machine mode that this machine uses
945 for the index in the tablejump instruction. */
946 #define CASE_VECTOR_MODE SImode
948 /* Define this if the tablejump instruction expects the table
949 to contain offsets from the address of the table.
950 Do not define this if the table should contain absolute addresses. */
951 /* #define CASE_VECTOR_PC_RELATIVE */
953 /* 'char' is signed by default. */
954 #define DEFAULT_SIGNED_CHAR 0
956 /* The type of size_t unsigned int. */
959 /* Don't cse the address of the function being compiled. */
960 #define NO_RECURSIVE_FUNCTION_CSE 1
962 /* Max number of bytes we can move from memory to memory
963 in one reasonably fast instruction. */
964 #define MOVE_MAX 4
966 /* Define if operations between registers always perform the operation
967 on the full register even if a narrower mode is specified. */
968 #define WORD_REGISTER_OPERATIONS
970 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
971 will either zero-extend or sign-extend. The value of this macro should
972 be the code that says which one of the two operations is implicitly
973 done, NIL if none. */
974 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
976 /* Nonzero if access to memory by bytes is slow and undesirable. */
977 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
979 /* We assume that the store-condition-codes instructions store 0 for false
980 and some other value for true. This is the value stored for true. */
981 #define STORE_FLAG_VALUE 1
983 /* Immediate shift counts are truncated by the output routines (or was it
984 the assembler?). Shift counts in a register are truncated by ARM. Note
985 that the native compiler puts too large (> 32) immediate shift counts
986 into a register and shifts by the register, letting the ARM decide what
987 to do instead of doing that itself. */
988 #define SHIFT_COUNT_TRUNCATED 1
990 /* All integers have the same format so truncation is easy. */
991 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
993 /* Define this if addresses of constant functions
994 shouldn't be put through pseudo regs where they can be cse'd.
995 Desirable on machines where ordinary constants are expensive
996 but a CALL with constant address is cheap. */
997 /* why is this defined??? -- dac */
998 #define NO_FUNCTION_CSE 1
1000 /* Chars and shorts should be passed as ints. */
1001 #define PROMOTE_PROTOTYPES 1
1003 /* The machine modes of pointers and functions. */
1004 #define Pmode SImode
1005 #define FUNCTION_MODE Pmode
1007 /* Compute extra cost of moving data between one register class
1008 and another. All register moves are cheap. */
1009 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
1011 #define WORD_REGISTER_OPERATIONS
1013 /* Implicit library calls should use memcpy, not bcopy, etc. */
1014 #define TARGET_MEM_FUNCTIONS
1016 /* Assembler output control. */
1024 /* Switch to the text or data segment. */
1028 #undef EXTRA_SECTIONS
1029 #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS
1031 #undef EXTRA_SECTION_FUNCTIONS
1032 #define EXTRA_SECTION_FUNCTIONS \
1033 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
1034 SWITCH_SECTION_FUNCTION
1036 /* Switch to SECTION (an `enum in_section').
1038 ??? This facility should be provided by GCC proper.
1039 The problem is that we want to temporarily switch sections in
1040 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
1041 afterwards. */
1042 #define SWITCH_SECTION_FUNCTION \
1043 static void switch_to_section PARAMS ((enum in_section, tree)); \
1044 static void \
1045 switch_to_section (section, decl) \
1046 enum in_section section; \
1047 tree decl; \
1048 { \
1049 switch (section) \
1050 { \
1051 case in_text: text_section (); break; \
1052 case in_data: data_section (); break; \
1053 case in_named: named_section (decl, NULL, 0); break; \
1054 SUBTARGET_SWITCH_SECTIONS \
1055 default: abort (); break; \
1056 } \
1057 }
1059 /* Switch into a generic section. */
1060 #undef TARGET_ASM_NAMED_SECTION
1061 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
1063 /* This is how to output an insn to push a register on the stack.
1064 It need not be very fast code. */
1065 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1067 reg_names[STACK_POINTER_REGNUM], \
1068 (STACK_BOUNDARY / BITS_PER_UNIT), \
1069 reg_names[REGNO], \
1070 reg_names[STACK_POINTER_REGNUM])
1072 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1073 #define REG_PUSH_LENGTH 2
1075 /* This is how to output an insn to pop a register from the stack. */
1076 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1078 reg_names[REGNO], \
1079 reg_names[STACK_POINTER_REGNUM], \
1080 reg_names[STACK_POINTER_REGNUM], \
1081 (STACK_BOUNDARY / BITS_PER_UNIT))
1084 /* Output a reference to a label. */
1085 #undef ASM_OUTPUT_LABELREF
1086 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1088 (* targetm.strip_name_encoding) (NAME))
1090 /* This is how to output an assembler line
1091 that says to advance the location counter
1092 to a multiple of 2**LOG bytes. */
1093 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1094 if ((LOG) != 0) \
1097 #ifndef ASM_DECLARE_RESULT
1098 #define ASM_DECLARE_RESULT(FILE, RESULT)
1099 #endif
1101 #define MULTIPLE_SYMBOL_SPACES 1
1103 #define SUPPORTS_ONE_ONLY 1
1105 /* A pair of macros to output things for the callgraph data.
1106 VALUE means (to the tools that reads this info later):
1107 0 a call from src to dst
1108 1 the call is special (e.g. dst is "unknown" or "alloca")
1109 2 the call is special (e.g., the src is a table instead of routine)
1111 Frame sizes are augmented with timestamps to help later tools
1112 differentiate between static entities with same names in different
1113 files. */
1115 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1116 do \
1117 { \
1118 if (mcore_current_compilation_timestamp == 0) \
1119 mcore_current_compilation_timestamp = time (0); \
1121 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1122 } \
1123 while (0)
1125 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1126 do \
1127 { \
1129 (SRCNAME), (DSTNAME), (VALUE)); \
1130 } \
1131 while (0)
1133 /* Globalizing directive for a label. */
1136 /* The prefix to add to user-visible assembler symbols. */
1137 #undef USER_LABEL_PREFIX
1140 /* Make an internal label into a string. */
1141 #undef ASM_GENERATE_INTERNAL_LABEL
1142 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1145 /* Jump tables must be 32 bit aligned. */
1146 #undef ASM_OUTPUT_CASE_LABEL
1147 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1150 /* Output a relative address. Not needed since jump tables are absolute
1151 but we must define it anyway. */
1152 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1155 /* Output an element of a dispatch table. */
1156 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1159 /* Output various types of constants. */
1161 /* This is how to output an assembler line
1162 that says to advance the location counter by SIZE bytes. */
1163 #undef ASM_OUTPUT_SKIP
1164 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1167 /* This says how to output an assembler line
1168 to define a global common symbol, with alignment information. */
1169 /* XXX - for now we ignore the alignment. */
1170 #undef ASM_OUTPUT_ALIGNED_COMMON
1171 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1172 do \
1173 { \
1174 if (mcore_dllexport_name_p (NAME)) \
1175 MCORE_EXPORT_NAME (FILE, NAME) \
1176 if (! mcore_dllimport_name_p (NAME)) \
1177 { \
1179 assemble_name (FILE, NAME); \
1181 } \
1182 } \
1183 while (0)
1185 /* This says how to output an assembler line
1186 to define an external symbol. */
1187 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1188 do \
1189 { \
1191 assemble_name ((FILE), (NAME)); \
1193 } \
1194 while (0)
1196 #undef ASM_OUTPUT_EXTERNAL
1197 /* RBE: we undefined this and let gas do it's "undefined is imported"
1198 games. This is because when we use this, we get a marked
1199 reference through the call to assemble_name and this forces C++
1200 inlined member functions (or any inlined function) to be instantiated
1201 regardless of whether any callsites remain.
1202 This makes this aspect of the compiler non-ABI compliant. */
1204 /* Similar, but for libcall. FUN is an rtx. */
1205 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
1206 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1207 do \
1208 { \
1210 assemble_name (FILE, XSTR (FUN, 0)); \
1212 } \
1213 while (0)
1216 /* This says how to output an assembler line
1217 to define a local common symbol... */
1218 #undef ASM_OUTPUT_LOCAL
1219 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1221 assemble_name (FILE, NAME), \
1224 /* ... and how to define a local common symbol whose alignment
1225 we wish to specify. ALIGN comes in as bits, we have to turn
1226 it into bytes. */
1227 #undef ASM_OUTPUT_ALIGNED_LOCAL
1228 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1229 do \
1230 { \
1232 assemble_name ((FILE), (NAME)); \
1234 } \
1235 while (0)
1237 /* Print operand X (an rtx) in assembler syntax to file FILE.
1238 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1239 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1240 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1242 /* Print a memory address as an operand to reference that memory location. */
1243 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1245 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1248 /* This is to handle loads from the constant pool. */
1249 #define MACHINE_DEPENDENT_REORG(X) mcore_dependent_reorg (X)
1251 #define PREDICATE_CODES \